| Document | Document Title |
|---|---|
| US09258372B2 |
Wireless router system and method
A wireless router employing a technique to couple a plurality of host services or host systems and a plurality of wireless networks. A method to route data items between a plurality of mobile devices and a plurality of host systems through a common wireless router. A point-to-point communication connection is preferably established between a first host system and a common wireless router, a mobile network message at a mobile device is generated, the mobile network is transmitted via a wireless network to the common wireless router which in turn routes a data item component of the mobile network message to the appropriate host service. |
| US09258371B1 |
Managing interaction with hosted services
Systems and methods are disclosed which facilitate managing interaction with instances corresponding to hosted services. Customers may implement services on a hosted computing environment. Further, the customer may allow limited interaction with the hosted service to a third party (e.g., in connection with a secondary service). For example, the third party may interact with a temporary copy of the hosted service. Thereafter, the customer may, given the consent of the third party, view details of the third party's interaction with the copy, and may be enabled to merge any alterations with the initial hosted service. In addition, a customer may monitor their own interactions with a hosted service or copies of a hosted service, and view details of the differences between multiple versions of the hosted service. |
| US09258366B2 |
Remote management system and operating method thereof
A remote management system includes a remote management apparatus and a user interface. The remote management apparatus has an network interface, a computer interface, and a console interface. The network interface is coupled to a first computer via a network. The computer interface is a signal transmitting interface between the remote management apparatus and a second computer. The user interface corresponds to a set of cursor control device and monitor. The user interface provides a plurality of functional options corresponding to a plurality of functions managing the remote management apparatus respectively. The user interface also shows a plurality of steps on the screen needed for the user to perform the function corresponding to the functional option on the remote management apparatus in response to one of functional options selected by the user to guide the user to finish the function interactively. |
| US09258365B2 |
Remote direct memory access acceleration via hardware context in non-native applciations
Provided are techniques generating a data structure, wherein the data structure specifies both a specified size of a memory space to allocate within an application and a virtual address within the application to locate a data path transmission queue; including within a verb for allocating the data path transmission queue the defined data structure; in response to a call of the verb, allocate, within the application, the data path transmission queue of the specified size and at the virtual location; in response to a request to transmit control data, employ a remote direct memory access (RDMA) transmission path; and, in response to a request to transmit data, employ the data path transmission queue rather than an RDMA transmission path. |
| US09258363B2 |
Data cube high availability
The subject disclosure is directed towards making cube data highly available and efficient to access by separating the read cube server from the processing cube server, on different physical machines. The read cube server may be mirrored, and the write cube server may be mirrored. When the primary read cube server is not operational (e.g., has failed) or is having its read cube synchronized, the read queries are handled by the mirror read cube server. When a processing cube server (or its write cube) is not operational, its mirror processing cube server takes over and performs cube processing operations via its mirror write cube. |
| US09258361B2 |
Transferring data among nodes on a network
Techniques for transferring data among nodes on a network are disclosed. Some example methods include a downloader-initiated random linear network coding algorithm. A downloading node may be aware of the chunks of original data held by neighboring nodes, and the downloading node can request linear combinations of chunks from the neighboring nodes that are linearly independent of any linear combinations of chunks already held by the downloading node. |
| US09258358B2 |
Parallel computing system and control method of parallel computing system
A parallel computing system includes: each computing node including: a first channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; a second channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; and a computational processor receiving data which the first or second channel has received, and transferring processed data to a subsequent node; an input-output node including: a third channel receiving data which the first channel or the computational processor of a preceding node transfers; a fourth channel receiving data which the first channel or the computational processor of a preceding computing node transfers, and transferring the received data to the second channel of a subsequent computing node; and an input-output processor receiving data which the third channel has received, and transferring inputted and outputted data to the first channel of a subsequent computing node. |
| US09258356B2 |
Flow-directed collaborative communication
A method for resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query. |
| US09258354B2 |
Progressive multimedia synchronization
There is disclosed means for uploading/downloading images to/from a remote server and for viewing the same. The uploading/downloading of the images to/from the remote server is parallel instead of serial. This means that the images, instead of being transferred as a sequential stream of bytes, instead are arranged in scans of image data in such a way that the uploaded/downloaded images can be browsed early albeit at a lower quality than if the entire image data is considered. As in the serial case, it is possible to interrupt the uploading/downloading process at any time, and still browse the received image data. Likewise it is possible to re-start the uploading/downloading process in the future. |
| US09258353B2 |
Multiple buffering orders for digital content item
Various embodiments are disclosed that relate to buffering digital content items in different orders for different user experiences. For example, one disclosed embodiment provides, on a computing device, a method for providing a buffering order for a digital content item. The method includes receiving from a remote computing device a request to access a selected digital content item, the selected digital content item comprising a plurality of content portions consumable in a plurality of different orders, the plurality of different orders corresponding to a plurality of user experiences for the selected digital content item, and in response, providing a selected content provision schema selected from a plurality of content provision schemas for the selected digital content item, each content provision schema defining a buffering order of the plurality of content portions of the selected digital content item for a corresponding user experience of the selected digital content item. |
| US09258351B2 |
System and method for message processing and routing
A message routing system that allows applications at either end of the system to run as-is without modification. The system functions in a multithreaded environment and is capable of handling complex routing rules and message transformation. It is also capable of learning and executing new routing rules and message transformations in formats previously unrecognized by the system. The system enables precise and reliable logging of messages throughout processing and supports publication of enterprise-wide broadcast messages. The system further preferably employs cooperating inbound and outbound transport processes for consuming, routing, processing, safely storing and publishing messages in batches of logical units of work to ensure that the logical units of work are not lost in system transactions. The system also preferably utilizes a replay server for preserving and replaying messages that might otherwise fail to reach their intended destinations. |
| US09258350B2 |
Analyte data retriever
Methods and apparatus, including computer program products, are provided for processing analyte data. In some example implementations, a method may include receiving, at a first processing system including a user interface, an installation package including a plug-in and code configured to provide at the first processing system an interface between a sensor system configured to measure an analyte concentration level in a host and a second processing system; storing, by the first processing system, the installation package in a location based on a role of a user initiating the installation of the code; installing the plug-in for the user interface to enable the plug-in to control one or more aspects of an installation of the code; and initiating, by at least the plug-in, the installation of the code at the first processing system to provide the interface. Related systems, methods, and articles of manufacture are also disclosed. |
| US09258343B2 |
Streaming data downloading method and computer readable recording medium thereof
A streaming data downloading method is illustrated, which is adaptive to a video player downloading a video file from a video server via Internet. The method includes dividing the video file into a plurality of time sections by the video player, sending several downloading requests to the video server for simultaneously downloading data corresponding to different time sections based on the number of the downloading requests. Therefore, data of the video file may be downloaded efficiently and waiting time for users may be drastically reduced. |
| US09258340B2 |
Secure digital remediation systems and methods for managing an online reputation
Secure digital remediation methods and systems are provided for managing a reputation. A method for managing a reputation includes receiving a complaint from a victim regarding an unfavorable item published by one or more third parties, extracting information from the unfavorable item, and providing a communication to the one or more third parties of the complaint including the information, the communication requesting a response from the one or more third parties. The method also includes scoring the unfavorable item on a severity scale based on the information, responses to queries and/or a ruleset to produce a severity score, the ruleset including instructions for responding to the complaint based on the severity score. |
| US09258339B2 |
Presenting data to electronic meeting participants
Described is a method for presenting web conference contents to one or more attendees in a shared session. Metadata is aggregated that is related to one or more participant electronic devices and a presenter electronic device that communicate with each other in the web conference. A presentation parameter is determined from the metadata. A selection interface is generated from the presentation parameter. A conference setting is selected from the selection interface. A set of content is presented at the presenter electronic device and shared with the one or more participant devices according to the selected conference setting. |
| US09258335B1 |
Connection-aggregation proxy service
A connection-aggregation proxy service disclosed in various embodiments receives connection requests from a plurality of local initiating services, where the connection requests are not targeted at the connection-aggregation proxy service. The connection-aggregation proxy service establishes connections with the local initiating services, receives packets over those connections, and transmits the packets across the same connection when the packets are for the same external target. A local connection-aggregation proxy service in one example executes on the same physical computing device as the local initiating services. A gateway connection-aggregation proxy service in another example resides at a network edge between the local initiating services and the external target that the network local initiating services are requesting. In yet another example, a central connection-aggregation proxy service establishes a connection with multiple local connection-proxy aggregation services and acts as an upstream aggregator for the connections from those local connection-aggregation proxy services. |
| US09258332B2 |
Distributed multi-processing security gateway
A system and method for a distributed multi-processing security gateway establishes a host side session, selects a proxy network address for a server, uses the proxy network address to establish a server side session, receives a data packet, assigns a central processing unit core from a plurality of central processing unit cores in a multi-core processor of the security gateway to process the data packet, processes the data packet according to security policies, and sends the processed data packet. The proxy network address is selected such that a same central processing unit core is assigned to process data packets from the server side session and the host side session. By assigning central processing unit cores in this manner, higher capable security gateways are provided. |
| US09258331B2 |
System and method for hardware-based trust control management
A trust control management method for security, operable on a computer system generates a unique Trust ID value by combining user-defined values with hardware-specific values associated with the user's computer system and storing the Trust ID value in a memory register physically associated with the hardware of the computer system. A Trust Control Suite (TCS) operable with a server OS/hypervisor maintains a database of user-defined values and hardware-specific values for computer systems clustered in a trusted computing pool. An attestation procedure is performed by the trust control server combining the user-defined values with the hardware-specific values from its database and comparing it to the user-stored Trust ID value stored in the memory register associated with a user's computer system. Depending on whether it is a match or mismatch, the TCS can determine if it is a trusted computer or not, and can take appropriate alerts and policy actions. |
| US09258328B2 |
Identifying malicious devices within a computer network
This disclosure describes techniques for proactively identifying possible attackers based on a profile of a device. For example, a device includes one or more processors and network interface cards to receive, from a remote device, network traffic directed to one or more computing devices protected by the device, determine, based on content of the network traffic, a first set of data points for the device, send a response to the remote device to ascertain a second set of data points for the device, and receive, from the remote device, at least a portion of the second set of data points. The device also includes a security module operable by the processors to determine a maliciousness rating, and selectively manage, based on the maliciousness rating, additional network traffic directed to the one or more computing devices protected by the security device and received from the remote device. |
| US09258323B1 |
Distributed filtering for networks
A firewall coordinates with devices in a network to create a distributed filtering system. The firewall detects an attack in the network, such as a distributed denial of service attack, and creates attack information defining characteristics of malicious packets used in the attack. The attack information is forwarded to the devices in the network. The devices use the attack information to configure themselves to detect packets having the characteristics of the malicious packets. After configuration, the devices detect and discard malicious packets. |
| US09258322B2 |
Systems and methods for assessing the compliance of a computer across a network
The disclosed principles describe systems and methods for assessing the security posture of a target device, wherein the assessment is performed by a scanning computer in communication with the target device via a communication network. By employing a system or method in accordance with the disclosed principles, distinct advantages are achieved. Specifically, conducting such a remote scan allows for the scanner computer to perform a remote scan of the remote device without installing client software to the remote device. Thus, the disclosed principles reduce the need for internal IT resources to manage the deployment and updates of client software on the target device. Also, conducting a remote scan according to the disclosed principles allows for the remote scan to be performed even if the scanner computer and remote device run different operating systems. |
| US09258319B1 |
Detection of and responses to network attacks
Disclosed are various embodiments for detecting and responding to attacks on a computer network. One embodiment of such a method describes monitoring data communications transmitted to a target class of first computing nodes; in response to detecting a non-legitimate data communication to a computing node in the target class, determining whether the non-legitimate data communication is a form of attack on a network to which the computing nodes are connected; and in response to determining that the network is under attack, implementing new security measures for second computing nodes that are not part of the target class to protect the second computing nodes against the attack on the network while the attack is ongoing. |
| US09258316B1 |
Systems and methods for generating reputation-based ratings for uniform resource locators
An exemplary computer-implemented method for generating reputation ratings for URLs may include (1) identifying a URL that identifies the location of at least one web resource, (2) identifying the computing health of at least one member of a computing community that has accessed the URL, (3) generating, based at least in part on the computing health of the member(s) that accessed the URL, a reputation rating for the URL that indicates whether the URL represents a potential security risk, and then (4) providing the reputation rating for the URL to at least one additional computing device to enable the additional computing device to evaluate whether the URL represents a potential security risk. In addition, a client-side, computer-implemented method for determining whether a URL represents a potential security risk may be based at least in part on such a reputation rating. Various other methods, systems, and computer-readable media are also disclosed. |
| US09258315B2 |
Dynamic filtering for SDN API calls across a security boundary
Presented herein are techniques to reduce the vulnerabilities of network elements to malicious API calls. One or more filters that validate data across an API boundary at a network element are dynamically loaded into the network element such that a reboot of the network element is not required to use the one or more filters. An API call is received for an API function, wherein the API call contains one or more parameter values associated with the API function. The parameters may be validated using the one or more filters. If it is determined that the one or more filters validate the parameters for the API function, the API function may be executed using the parameter values. If it is determined that the one or more filters do not validate the parameters for the API function, the execution of the API function may be aborted. |
| US09258309B2 |
Method and system for operating a wireless access point for providing access to a network
A method is described for operating a single network adapter for use on two different sub-networks of the same type, and a corresponding apparatus. The method comprises setting up a first network address and routing table in the network adapter for use in the first sub-network; setting up a second network address and routing table in the network adapter for use in the second sub-network; receiving data for one of the first and second sub networks, and re-transmitting the data to the other of the first and second sub-network, using the network addresses and routing tables. |
| US09258306B2 |
Methods for confirming user interaction in response to a request for a computer provided service and devices thereof
A method, non-transitory computer readable medium, and access manager device includes providing an initial challenge to a client computing device requesting access to a service. The initial challenge includes one or more of one or more objects, one or more indicative answers, and one or more questions based on the one or more objects. At least one challenge response to the initial challenge is received from the client computing device. A determination is when there is a match between the at least one challenge response to the initial challenge and corresponding response data associated with the initial challenge. One or more actions with respect to the request to access the service are performed based on the determination. |
| US09258305B2 |
Authentication method, transfer apparatus, and authentication server
It is provided an authentication method for realizing a network authentication function for an authentication system, the authentication system including an authentication server for authenticating a terminal used by a user, and a switch for mediating an authentication sequence between the terminal and the authentication server. The authentication method includes steps of: providing, by the switch, identification information for identifying the switch to the authentication server in the authentication sequence; authenticating, by the authentication server, an authentication request transmitted from the terminal; transmitting, by the authentication server, an authentication result of the authentication to the switch based on the provided identification information on the switch; and authenticating, by the switch, access from the terminal based on the authentication result received from the authentication server. |
| US09258304B2 |
Methods and apparatus for using keys conveyed via physical contact
An example touch key system may include a master device, one or more carrier devices and protected devices, and a server. The master device may automatically detect a predefined trigger action. In response, the master device may automatically generate a carrier device credential and a corresponding cloud credential. The master device may then automatically send the cloud credential to the server. The master device may also automatically detect the carrier device in electrical communication with the master device. In response, the master device may automatically determine whether the carrier device credential from the key pair is intended for the carrier device. If so, the master device may automatically transfer the carrier device credential to the carrier device. The carrier device may use the carrier device credential to obtain access to the protected device. Other embodiments are described and claimed. |
| US09258303B1 |
Method of providing real-time secure communication between end points in a network
A method of establishing a multiplicity of shared secrets at two mutually authenticated end points in a network. The method includes authenticating a first end point in the network based on an asymmetric key pair and authenticating a second end point based on an asymmetric key pair. Upon successful authentication of the first and second end points, the end points negotiate a shared secret. Multiple shared secret keys are generated from the negotiated shared secret and session keys are computed from the multiple shared secret keys. |
| US09258302B2 |
Method and system for distinguishing humans from machines
A method and an apparatus for distinguishing humans from computers. During user registration, a computer prompts a human user to provide a spoken response to certain authentication information for registration. The computer obtains registration voice data from the spoken response and establishes a registration voiceprint of the human user. During user logon, the computer identifies the user requesting to logon by the user's logon credentials, provides authentication information for logon to the user, and prompts the user to provide a spoken response to the authentication information for logon. The computer obtains logon voice data from the spoken response, and establishes a logon voiceprint of the user. The computer then determines whether the user requesting to logon is human by comparing the logon voiceprint with the registration voiceprint. |
| US09258301B2 |
Advanced authentication techniques
A method, system, apparatus, and computer program product are provided for facilitating advanced authentication techniques. For example, a method is provided that includes receiving at least one request to access at least one resource and receiving at least one composite authentication credential, the composite authentication credential comprising a first credential component and a second credential component. The method further includes determining whether the first credential component is valid, determining whether the second credential component is valid and, in an instance in which it is determined that the first and second credential components are valid, causing access to the at least one resource to be permitted. |
| US09258298B2 |
Simplified configuration of a network device
Methods, systems, and computer readable media can be operable to pair a client device with a CPE device. The methods, systems and computer readable media described in this disclosure can enable the pairing of a client device with a CPE device upon a connection of the client device to a whole-network associated with the CPE device. Further, methods, systems and computer readable media can enable the secure pairing of a client device with a CPE device with little to no user-input. |
| US09258297B2 |
Methods, devices, and mediums for securely sharing restricted content
A computing device is disclosed for securely sharing restricted content. The computing device includes a memory storing computer readable instructions, and one or more processors configured to execute the computer readable instructions. The computer readable instructions configure the one or more processors to, collectively, receive a share request to share the restricted content; in response to the share request, encode a link with encrypted access information, the access information including a first password and identifying the restricted content; receive an access request for access to the restricted content from a client device executing the link, the access request including the encrypted access information; receive a second password from the client device in association with the access request; and grant the client device access to the restricted content in response to determining the first password matches the second password. A method and a computer readable medium are also disclosed. |
| US09258294B2 |
Remote authentication method with single sign on credentials
Systems and methods for remote authentication using Single Sign-On (SSO) credentials are disclosed. An implementation includes transmitting a request for an identification code from an application to a wireless service provider, the request provided through an encrypted transport protocol, receiving the identification code as a messaging service message from the wireless service provider, securely routing the received identification code to the requesting application, upon receipt of the identification code at the application, retrieving an authentication token for the application through the encrypted transport protocol and providing the authentication token to an application content server to allow content transfer between the application content server and the application. |
| US09258291B2 |
Pre-authorizing a client application to access a user account on a content management system
A content management system can tag a client installer with an information tag linking the client installer to a user account. The client installer can be configured to install the client-side application on the client device and pass the identification tag to the installed client-side application. The client-side application can transmit the identification tag to the content management system, which can use the identification tag to identify the linked user account and log the client-side application into the user account. The content management system can implement several verification measures such as limiting the number of times and when an identification tag can be used, as well as IP addresses that can use the identification tag. The content management system can also use data cached by the web-browser application to determine if the web-browser application was used to access the user account in the past. |
| US09258290B2 |
Secure administration of virtual machines
Methods and systems for performing secure administration of virtual domain resource allocation are provided herein. A cloud service provider (CSP) may provide instances of virtual machines to one or more contracting user entities. The cloud service provider may store an authorization database identifying one or more resources (e.g., storage, CPU, etc.) that each of the different contracting user entities is authorized to use on a virtual machine server device. The CSP may subsequently receive a request from an unverified entity to instantiate a virtual machine with access to one or more resources. The request may include security information. The CSP validates the request by verifying the unverified entity using the first security information (e.g., checking a PKI certificate, requiring a login/password, etc.) and, when the request is validated, provides access to the verified entity to a subset of the requested one or more resources based on the authorization database. |
| US09258289B2 |
Authentication of IP source addresses
A method and system for authenticating IP source addresses by accessing one or more HTTP requests whose source client identifies itself as a legitimate web crawler. One or more IP addresses are detected from the one or more HTTP requests and each detected IP address is authenticated via a probability estimation regarding its association with a legitimate web crawler. A lookup table is preferably compiled for the authenticated IP addresses for reference, publication and authentication purposes. |
| US09258287B2 |
Secure active networks
A secure active network includes a plurality of secure elements which communicate with one another to share and log information such as identification, location, and user activity associated with each secure element. Secure elements exchange data with one another, and log data received. The periodicity of communication between secure elements, encryption of the information, and the operating frequency in which the information is transmitted and received may be changed if communication is lost between any of the secure elements or if a determination is made that a secure element has traveled outside a predetermined zone. The integrity of the secure network may be verified at any time by comparing the logged information to a reference network. |
| US09258286B1 |
Systems and methods for communications channel authentication
A user may access an institution system via more than one communications channel, either by the same device (e.g., a mobile device accessing the institution system via a voice channel and a data channel) or by different devices (e.g., a personal computer via a web channel and a phone via a voice channel). If a user is not currently authenticated to a communications channel and attempts to access the institution system via a communications channel, the user may be authenticated using strong authentication. If the user is currently authenticated to the institution system via a communications channel and would like to engage a second communications channel to access the institution system, the user may authenticate to the second communications channel using both communications channels and weak authentication, such as single factor authentication or a challenge question. |
| US09258283B2 |
Key management system, key management method, and communication device
In a key management system, a RFID tag decrypts a first key encrypted by a master key and stores the decrypted first key to a service key storage region, then decrypts a second key encrypted by the first key in a third party server, then, encrypts the decrypted second key by the master key and transmits the second key encrypted by the master key to an application of a mobile information terminal, and then decrypts the encrypted second key returned from the application and stores the decrypted second key to the service key storage region. |
| US09258282B2 |
Simplified mechanism for multi-tenant encrypted virtual networks
The present disclosure provides protection of customer data traveling across a network. A reverse cryptographic map (also referred to herein as a reverse crypto map) can be defined for a customer, where the reverse crypto map indicates how customer data should be protected. A reverse crypto map for a customer is applied to an interface of an edge device that is coupled to that customer's private subnet (or customer-facing interface). A reverse crypto map can be configured by a network administrator on a provider edge device, or can be pushed from a key server as part of group policy. A provider edge device can protect customer data by encrypting and decrypting the customer data according to the reverse crypto map. A provider edge device can also be configured with virtual routing and forwarding (VRF) tables that can be used to forward the VPN traffic flow across a provider network. |
| US09258277B1 |
Decentralized packet dispatch in network devices
In general, techniques are described for performing decentralized packet dispatch. A network device comprising one or more service processing units (SPUs) and an interface may implement the techniques. The interface receives a packet associated with a session and selects a first one of SPUs to dispatch the packet based on first information extracted from the packet. The first one of the SPUs dispatches the packet to a second one of the SPUs based on second information extracted from the packet. The second one of the SPUs performs first pass processing to configure the network security device to perform fast path processing of the packet such that second one of the SPUs applies one or more services to the packet and subsequent packets associated with the same session without application of services to the packets by the first one of the service processing units. |
| US09258276B2 |
Efficient packet handling, redirection, and inspection using offload processors
A method for handling packets is disclosed. The method can include providing at least one main processor connected to a plurality of offload processors by a memory bus; configuring the offload processors to provide security related services on packets prior to redirection to the main processor; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus. |
| US09258273B2 |
Duplicating packets efficiently within a network security appliance
A network security appliance uses a switch to switch packets between cores configured for fast path processing and slow path processing. The switch duplicates packets for delivery to the slow path processing cores, eliminating the need for the fast path processing cores to expend processor resources on packet duplication. The switch can use IEEE 802.1ad Q-in-Q VLAN tags in the packet to perform the switching and packet duplication. Slow path processing cores may also broadcast packets to other slow path processing cores via the switch. |
| US09258270B2 |
Selecting between domain name system servers of a plurality of networks
A method and computer for managing domain name system services for a plurality of networks is disclosed. A computer identifies information for the plurality of networks to which a client device is connected. The computer receives a request to identify an internet protocol address for a domain name or vice-versa. In response to the request, the computer selects a particular set of domain name system servers of a particular network in the plurality of networks based on the information for the plurality of networks and a set of rules for selecting the particular set of domain name system servers when identifying the internet protocol address for the domain name. The computer then sends the request to identify the internet protocol address for the domain name to a domain name system server in the particular set of domain name system servers. |
| US09258267B1 |
Highly scalable data center architecture with address resolution protocol (ARP)-free servers
A network device establishes a logical channel with each server device of multiple server devices, where each logical channel is not shared with another server device of the multiple server devices. The network device also determines a network loopback Internet protocol (IP) address for each server device of the multiple server devices, and associates each network loopback IP address with a corresponding logical channel. The network device further receives a packet destined for a particular server device, and provides the packet to the particular server device via the logical channel associated with the particular server device. |
| US09258265B2 |
Message tracking with thread-recurrent data
A method, system, computer program product, and related business methods are described in the context of a web-based business information system having an internal email facility, wherein e-mail communications between a native e-mail system of an end user of the web-based business information system and an external contact are facilitated and automatically tracked by the web-based business information system, the native e-mail system lying outside the web-based business information system but often being preferred by the end user over the internal e-mail facility of the web-based business information system. The described preferred embodiments provide for easy-to-use, reasonably transparent, “no-click” integration of the web-based business information system with the end user's native e-mail system in a manner that is independent of the particular type and choice of native e-mail system. |
| US09258263B2 |
Dynamic granular messaging persistence
Embodiments of the present invention provide a method, system and computer program product for dynamic, granular messaging persistence in a messaging system. In an embodiment of the invention, a method for dynamic, granular messaging persistence in a messaging system is provided. The method includes monitoring operational performance of a message broker and receiving a message for queuing in a message queue of the message broker. The method also includes parsing the message to extract different fields and corresponding priorities and selectively storing in fixed storage, data for corresponding ones of the different fields based upon consideration of corresponding ones of the priorities and the monitored operational performance. Finally, the method includes queuing the message in the message queue. |
| US09258262B2 |
Mailbox-based communications system for management communications spanning multiple data centers and firewalls
System and methods for effecting communications between a trusted management process and one or more managed processes in a distributed computing environment where direct communications between processes via a data communications network is blocked by a firewall or other security system. The method includes a file server that is accessible to all communicating processes. The file server provides a secure mailbox for each managed process. The mailbox is used to hold messages that are stored as individual files. The management and managed processes communicate by writing and reading files in the mailbox of the managed process. The stateless manner of the message-based communications makes it easy to replicate the management process in order to provide scalability and fault-tolerance for the management functions. |
| US09258261B1 |
System and method for detecting unwanted content
A system and method for detecting unwanted electronic content, such as spam. As a user operates an application to send messages, several metrics are tracked to allow the system to analyze her activity. Illustrative metrics may include, but are not limited to, block count (e.g., how many other users have blocked her), block rate (e.g., the rate at which other users block her), peer symmetry (e.g., percentage of her messages that are to other users that have her in their address book), message uniqueness (e.g., how unique her messages are from each other), peer uniqueness (e.g., how unique the addressees of her messages are), and message rate (e.g., the rate at which she sends messages). Periodically, metrics may be compared to corresponding thresholds. Depending on whether a threshold is crossed, and which threshold is crossed, she may be banned from using the application or placed on a watch list. |
| US09258260B2 |
Filtering electronic messages based on domain attributes without reputation
A messaging application filters electronic messages based on domain attributes without a reputation. A message with a uniform resource identifier (URI) is received and determined to not be included within a trusted or a block list. A total score is computed from weighted scores assigned to factors associated with the message. The message is evaluated for an unsolicited message determination by comparing the total score against a predetermined threshold. |
| US09258259B2 |
Retrieval of offline instant messages
Retrieving messages stored in a mail server and pending to be retrieved by a user is disclosed. A summary of the messages stored in the mail server and pending to be retrieved by the user is received at a terminal device of the user, each message associated with a unique identifier. At least one of the messages to be retrieved from the mail server is selected on the basis of the summary of messages. From the unique identifier associated with the at least one message an identifier valid for retrieval of the at least one message is determined, and a retrieval request with the identifier valid for retrieval is sent to the mail server. Upon receiving the retrieval request with the at least one identifier valid for retrieving the at least one of the stored messages, the mail server sends the at least one message towards the terminal device. |
| US09258257B2 |
Direct memory access rate limiting in a communication device
Rate limiting operations can be implemented at an ingress DMA unit to minimize the probability of dropped packets because of differences between the communication rates of the ingress DMA unit and a packet processing engine. The communication rate associated with each of the software ports of a communication device can be determined and an aggregate software port ingress rate can be calculated by summing the communication rate associated with each of the software ports. The transfer rate associated with the ingress DMA unit can be limited so that packets are transmitted from the ingress DMA unit to the packet processing engine at a communication rate that is at least equal to the aggregate software port ingress rate. If each software port comprises a dedicated rate-limited ingress DMA queue, packets from a rate-limited ingress DMA queue can be transmitted at the at least the communication rate of the corresponding software port. |
| US09258254B2 |
Virtual router and switch
An input/output (I/O) switch fabric includes input physical ports that convey packets associated with at least a first network flow. Moreover, virtual routers in the I/O switch fabric, which have associated routing tables, provide types of service and/or routes for different source-destination pairs based on link-layer information and network-layer information in the packets. Note that different virtual routers can provide different types of service and/or different routes. For example, a type of service associated with a first virtual router may include changing packet headers when crossing service domains in a global network, and a type of service associated with a second virtual router may avoid changing packet headers when providing connectivity in the network. Furthermore, the I/O switch fabric includes output physical ports that convey packets associated with at least a second network flow. The virtual routers may facilitate InfiniBand inter-subnet crossing. |
| US09258253B2 |
System and method for flexible switching fabric
A system and method for a flexible switching fabric includes a network switching device. The network switching device includes a plurality of connectors configured to couple the network switching device to other network devices, one or more front panel cards, each front panel card including one or more first ports and configured to forward network packets between the first ports, one or more fabric cards, each fabric card including one or more second ports and configured to forward network packets between the second ports, and a port multiplexing unit configured to flexibly couple the connectors to the one or more first ports and the one or more second ports to the one or more first ports. The flexible coupling between the one or more first ports and the connectors and the one or more second ports is determined based on a desired configuration for the network switching device. |
| US09258252B1 |
Virtual server resource monitoring and management
A system is provided that monitors a first and second virtual server on a first physical server containing a physical processor, monitors physical processor usage wherein capacity is allocated to a first entitlement comprising a first percentage of the capacity guaranteed to the first virtual server, to a second entitlement comprising a second percentage guaranteed to the second virtual server, and to a third percentage one of unallocated and partially and totally allocated to a virtual server based on need, and wherein the percentages total to one hundred percent. The system monitors usage of a first virtual processor associated with the first virtual server, receives a request for first virtual processor utilization by percentage, determines utilization comprising first virtual processor usage divided by a first allocated processing capacity comprising the first entitlement and a portion of the third percentage currently allocated to the first virtual server, and reports the utilization. |
| US09258243B2 |
Symmetric service chain binding
A plurality of network nodes are deployed in a network, each network node configured to apply a service function to traffic that passes through the respective network nodes. A controller generates information for a service chain that involves application to traffic of one or more service functions at corresponding ones of the plurality of network nodes along a forward path through the one or more network nodes. The controller identifies one or more of the service functions within the service chain that is stateful. When one or more of the service functions of the service chain is stateful, the controller generates information for a reverse path through the one or more service nodes for the one or more stateful service functions. The controller binds a forward chain identifier for the forward path with a reverse chain identifier for the reverse path for the service chain. |
| US09258242B1 |
Path selection using a service level objective
In one aspect, a method includes measuring performance parameters for each path, determining classifications of each path based on a service level objective and sending I/Os using load balancing by the classifications determined. In another aspect, an apparatus includes electronic hardware circuitry configured to measure performance parameters for each path, determine classifications of each path based on a service level objective and send I/Os using load balancing by the classifications determined. In a further aspect, an article includes a non-transitory computer-readable medium that stores computer-executable instructions. The instructions cause a machine to measure performance parameters for each path, determine classifications of each path based on a service level objective and send I/Os using load balancing by the classifications determined. |
| US09258241B2 |
Transparent provisioning of services over a network
An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the apparatus provides external connectivity to other devices that wish to intercept packets as well. The apparatus applies one or more rules to the intercepted packets which execute one or more functions on a dynamically specified portion of the packet and take one or more actions with the packets. The apparatus is capable of analyzing any portion of the packet including the header and payload. Actions include releasing the packet unmodified, deleting the packet, modifying the packet, logging/storing information about the packet or forwarding the packet to an external device for subsequent processing. Further, the rules may be dynamically modified by the external devices. |
| US09258240B2 |
Available bandwidth estimating device
An available bandwidth estimating device 300 is equipped with: a transmission rate acquiring part 301 configured to acquire a transmission rate, which is the amount of data transmitted by a transmitting device per unit time to a receiving device connected so as to be capable of communicating via a communication network; and an available bandwidth estimating part 302 configured to estimate the available bandwidth based on a mathematical model constructed by representing a relation between an available bandwidth, which is a communication bandwidth available in a communication path between the transmitting device and the receiving device, and the transmission rate by a dynamic model including a mobile body movable in a preset moving direction and an elastic body transforming in the moving direction by a movement amount of the mobile body having moved in the moving direction, and based on the acquired transmission rate. |
| US09258232B2 |
Ingress traffic flow control in a data communications system
Embodiments of the invention provide flow control of incoming data packets to data processing resources via a controller that can receive and react to advanced backpressure messages. These advanced backpressure messages are used to rate limit the data packets based one or more of the following factors: traffic class, traffic priority, destination port. The controller can also generate a traffic preference message to an upstream source of the data packets to inform the upstream unit of the most appropriate type of data that should be transmitted downstream at that time, thereby improving the likelihood of the transmitted data being processed in a proper and timely manner by the downstream data processing resources. Embodiments of the invention can improve the performance of a communications system during periods of congestion by ensuring that high-priority traffic has precedence over traffic of lower priority while maximizing utilization of the ingress data path bandwidth. |
| US09258230B2 |
In flight TCP window adjustment to improve network performance
A system and method for reconfiguring a TCP window in a switch of a network system, where the size of the window is determined based on the operating speed of a work station to which data packets in the window are being sent and the size of the switch buffer. The algorithm includes establishing a connection between a server and the station, where the connection includes TCP data packets. The algorithm identifies a TCP window size requested by the station, and identifies the connection speed of the station in the switch. The algorithm then modifies the TCP window size of the connection if the identified TCP window size does not support the connection speed and the size of the buffer. The algorithm also changes the TCP check-sum based on the new TCP window size. |
| US09258228B2 |
Filtering and route lookup in a switching device
Methods and devices for processing packets are provided. The processing device may Include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data units. |
| US09258226B2 |
Systems and methods for dual network address translation
Included are systems and methods for providing dual network address translation. Accordingly, some embodiments include translating, via a processor at a network operations center (NOC), a public source address and a public destination address to and from assigned unique private addresses for data to be communicated across a wide area network, while including gateway functions to manage an application with an imbedded IP address. Some embodiments include communicating, via the processor at the NOC, the data to a ReNAT virtual private network (VPN) with packets wrapped in a private ReNAT defined protocol that includes the public source address and the public destination address. Still some embodiments include mapping, via the processor at the NOC, a unique private address in the data to customer defined private IP addresses. |
| US09258225B2 |
System and method for efficient matching of regular expression patterns across multiple packets
A system and method for efficient matching regular expression patterns across multiple packets. A deep packet inspection system can be embodied in a switch ASIC using a flow tracker and a signature matching engine. The flow tracker can be positioned in an ingress portion of the switch ASIC at a location where packets in a bi-direction flow can be observed and recorded. The flow tracker generates a signature match request that is forwarded to a signature matching engine in an auxiliary pipeline. The signature matching engine is enabled to perform cross-packet signature matching using signature matching state machines and reports the signature matching results to the flow tracker using a response packet that is sent to the ingress pipeline. |
| US09258218B2 |
Software-defined network overlay
A software-defined network overlay capability is configured to control one or more overlay networks using software-defined networking (SDN) in which control functions and forwarding functions are separated. The software-defined network overlay capability may be configured to vertically move packets across network layers, e.g., into an overlay network (e.g., into a tunnel via encapsulation), out of an overlay network (e.g., out of a tunnel via decapsulation), or the like. The software-defined network overlay capability may be configured to move packets from native forwarding infrastructure into an overlay network, between overlay networks (e.g., into a first overlay network from a second overlay network without leaving the second overlay network, out of a first overlay network and into a second overlay network, out of a first overlay network while remaining within a second overlay network, or the like), from an overlay network onto native forwarding infrastructure, or the like. |
| US09258217B2 |
Systems and methods for rule-based anomaly detection on IP network flow
A system to detect anomalies in internet protocol (IP) flows uses a set of machine-learning (ML) rules that can be applied in real time at the IP flow level. A communication network has a large number of routers that can be equipped with flow monitoring capability. A flow collector collects flow data from the routers throughout the communication network and provides them to a flow classifier. At the same time, a limited number of locations in the network monitor data packets and generate alerts based on packet data properties. The packet alerts and the flow data are provided to a machine learning system that detects correlations between the packet-based alerts and the flow data to thereby generate a series of flow-level alerts. These rules are provided to the flow time classifier. Over time, the new packet alerts and flow data are used to provide updated rules generated by the machine learning system. |
| US09258206B2 |
System administration
A technique for improving system administration involves implementing system administration agent programs on a plurality of devices in an administered network. A deployment agent deploys the system administration agent program or a portion thereof to suitable devices when they are detected. System monitoring agents monitor the administered network to generate data. A reporting engine sends agent reports including the generated data to a system administration server. The system administration server facilitates administration of the administered network in real time. |
| US09258204B2 |
Method and apparatus for deciding network coding method based on link utilization
A method and apparatus for deciding a network coding method based on link utilization are disclosed herein. The method may include a step of setting up an output link utilization reference value of a network intermediate node, a step of calculating an average utilization of output links for each network intermediate node, a step of deciding a network coding method in accordance with the average utilization of the output link for each network intermediate node, a step of consistently updating the average utilization of the output link for each network intermediate node, and a step of changing the network coding method, when a value of the average utilization value is changed. |
| US09258203B1 |
Monitoring computer performance metrics utilizing baseline performance metric filtering
A system and method for managing performance metric information is provided. Baseline performance metrics, such as network bandwidth capabilities, of various client computing devices may be obtained. The baseline performance metrics can be used to separate client computing devices into one or more groups. Based on the groupings, subsequent performance metrics associated with the one or more monitored groups can be collected in a manner to mitigate performance latencies associated with the baseline performance metric. The subsequent performance metrics can be processed to determine which metrics correspond to a potential performance problem. |
| US09258202B2 |
Correlation of performance monitoring records for logical end points within a protected group
A network system comprising logical work and protect Connection Termination Points. Performance Monitoring (PM) records are provided by generating for each work Connection Termination Point (CTP) a work bit vector and a protect bit vector. The work bit vector keeps track of severely errored seconds (SES) occurrences at the work CTP only when the work CTP is selected. The protect bit vector keeps track of severely errored seconds (SES) occurrences at the protect CTP only when the protect CTP is selected. Processing the work bit vector and the protect bit vector provides accurate PM records. |
| US09258201B2 |
Active device management for use in a building automation system
A building automation system (BAS) comprising a plurality of end devices, at least one communication network, and a server engine comprising a communication state manager for actively managing the state of various devices in building automation system and an associated reconnect manager to reestablish communication with off-line devices. The communication manager and the reconnect manager coordinate the interaction between the server engine and the devices in order to minimizing the load on the communication network, while also working to establish the working state of any of the end devices and to transition off-line to an on-line state. |
| US09258198B2 |
Dynamic generation of policy enforcement rules and actions from policy attachment semantics
At least one defined service policy to be enforced by a policy enforcement point (PEP) is obtained. The obtained at least one defined service policy is parsed to identify at least one set of enforceable policy provisions and the at least one set of enforceable policy provisions is identified. Each set of enforceable policy provisions includes a policy subject, a policy domain, and at least one assertion as the enforceable policy provisions within the at least one defined service policy. At least one runtime processing rule including at least one processing action usable by the PEP is created to enforce the policy subject, the policy domain, and the at least one assertion of each identified at least one set of enforceable policy provisions. |
| US09258192B2 |
Multi-chassis topology discovery using in-band signaling
A multi-chassis network device may automatically detect whether cables connected between chassis devices are correctly inserted. The device may insert, into a first data stream output from a first port of the device, control information identifying the first port. The device may receive, from a second data stream received by the first port of the device, second control information identifying a second port, at another device connected to the device via a cable. The device may determine, based on the second control information, whether the connection of the first port to the second port, via the cable, is valid and cause, when the connection of the first port to the second port is determined to not be valid, the device to output an indication that the connection is not valid or to reconfigure the device to make the connection of the first port to the second port valid. |
| US09258191B2 |
Direct network having plural distributed connections to each resource
A direct network is described in which each resource is connected to a switching fabric via a set of two or more routing nodes. The routing nodes are distributed so as to satisfy at least one inter-node separation criterion. In one case, the separation criterion specifies that, for each resource, a number of routing nodes that share a same coordinate value with another routing node in the set (in a same coordinate dimension) is to be minimized. In some network topologies, such as a torus network, this means a number of unique loops of the direct network to which each resource is connected is to be maximized. The routing provisions described herein offer various performance benefits, such as improved latency-related performance. |
| US09258190B2 |
Systems and methods for managing excess optical capacity and margin in optical networks
A method, a network element, and a network include determining excess margin relative to margin needed to insure performance at a nominal guaranteed rate associated with a flexible optical modem configured to communicate over an optical link; causing the flexible optical modem to consume most or all of the excess margin, wherein the capacity increased above the nominal guaranteed rate includes excess capacity; and mapping the excess capacity to one or more logical interfaces for use by a management system, management plane, and/or control plane. The logical interfaces can advantageously be used by the management system, management plane, and/or control plane as one of restoration bandwidth or short-lived bandwidth-on-demand (BOD) connections, such as sub-network connections (SNCs) or label switched paths (LSPs). |
| US09258189B2 |
Method, node device and system for establishing label switched path
A method, node device, and system are disclosed for establishing a label switched path, which belong to the field of communications technologies. Establishing the label switched path between a source node and a sink node utilizes a connection establishment request message that carries bandwidth request information corresponding to different conditions. Based on the bandwidth request information corresponding to the different conditions, various amounts of bandwidth resources corresponding to the different conditions are reserved on local links that establish a connection between the source node and the sink node. |
| US09258186B2 |
System and method for configuration of network-capable appliances
A controlling device is used to configure a target device for wireless network communications through use of a setup wizard. The setup wizard is used to obtain information required to perform communications on a wireless network via a wireless network router and a digital representation of the information obtained through use of the setup wizard is provided to the target device via use of the controlling device. The target device will use the digital representation of the information to configure itself for wireless network communications. |
| US09258184B1 |
System and method for monitoring the status of multiple servers on a network
A system and method for monitoring a plurality of servers by a monitoring server in a computer network. A list of servers and a plurality of services to monitor in the computer network is generated at the monitoring server. A status query is transmitted sequentially by the monitoring server to each of the plurality of servers, the status query including the plurality of services to monitor at each server. A status message report is received from each of the plurality of servers in response to each status query. An event is reported in an event log for each server that has an abnormal service status. The transmission of the status query to each server is performed by the monitoring server at a specified service time interval. |
| US09258181B1 |
Managing agent login to multiple conference call bridges
A method, a computer readable medium, and a system for managing agent login to multiple bridges are provided. The method comprises reserving at least one bridge for at least one agent, creating a first queue for the at least one bridge, the first queue comprising the at least one agent, monitoring efficiency of the at least one bridge, determining if a need for a first bridge of the at least one bridge is high, creating a second queue for the first bridge of the at least one bridge if the need for the first bridge of the at least one bridge is high, assigning at least one agent from the first queue to the second queue, and moving the at least one agent up in the second queue. |
| US09258173B2 |
Vehicle communication network including wireless communications
A wired and wireless vehicle communication network includes network node modules, switch modules, bridge-routing modules, and a network manager. The network manager is operable to determine a wired packet communication mode and/or a wireless packet communication mode. When the network is in the wireless packet communication mode, the network manager coordinates wireless communication of packets among the network node modules, the switch modules, and the bridge-routing modules based on individual content of the packets and wireless channel mapping. When the network is in the wired packet communication mode, the network manager coordinates wired communication of packets among the network node modules, the switch modules, and the bridge-routing modules based on the individual content of the packets and in accordance with a global vehicle network communication protocol. |
| US09258161B2 |
Reference signal design for massive MIMO communication
The present disclosure is directed to a system and method for extending a reference signal pattern to define additional reference signals using a phase division multiplexing (PDM) technique. The reference signal pattern can be a predefined reference signal pattern in a wireless communication standard and can be extended to support massive MIMO communication. |
| US09258160B2 |
Multiplexing demodulation reference signals in wireless communications
Methods and apparatuses are provided for determining cyclic shift (CS) values and/or orthogonal cover codes (OCC) for a plurality of demodulation reference signals (DM-RS) transmitted over multiple layers in multiple-input multiple-output (MIMO) communications. A CS index can be received from a base station in downlink control information (DCI) or similar signaling. Based at least in part on the CS index, CS values for the plurality of DM-RSs can be determined. In addition, OCC can be explicitly signaled or similarly determined from the CS index and/or a configured CS value received from a higher layer. In addition, controlling assignment of CS indices and/or OCC can facilitate providing orthogonality for communications from paired devices in multiuser MIMO. |
| US09258158B2 |
Method for determining uplink transmission power
There is provided a method for determining uplink transmission power. The method may performed by a user equipment (UE) and comprise: receiving, by the UE, a value of additional maximum power reduction (A-MPR) from a base station (BS), if the UE is configured to use for uplink transmission a frequency range of 1980 MHz through 2010 MHz or 1920 MHz through 2010 MHz and if another UE which is located in an adjacent BS and is to be protected uses for an uplink transmission a frequency range of 2010 MHz through 2025 MHz; and determining an uplink transmission power by applying the value of A-MPR. |
| US09258157B2 |
Method and system for mapping bit sequences
A method of mapping a plurality of different bit sequences to a plurality of different signal points in a constellation, the number of bit sequences being greater than the number of signal points. The method includes, for a device in a telecommunication network, the acts of: determining, for each signal point in the constellation, a number of bit sequences to be mapped to each signal point, the numbers of bit sequences being distributed according to a discrete Gaussian distribution among the constellation, selecting in the plurality of bit sequences, for each signal point in the constellation, a set including the determined number of bit sequences (u) that minimize the maximal Hamming distance among the selected sets. |
| US09258155B1 |
Pam data communication with reflection cancellation
The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a communication system that removes reflection signals. A digital data stream is processed through both tentative path and the main path. The tentative path uses a first DFE device and a reflection cancellation circuit to generate a correction signal for removing reflection signal from the digital data stream. A second DFE device removes ISI and other noises from the corrected digital data stream. There are other embodiments as well. |
| US09258153B1 |
Inter-symbol interference (ISI) loss filter device
An inter-symbol interference (ISI) loss filter device emulates frequency dependent losses to an electrical signal. The ISI loss filter device includes amplifier stages connected in series for cascading programmable poles or zeros in a signal path carrying the electrical signal. Each amplifier stage includes a high performance bypass path, a bandwidth limited path parallel to the high performance bypass path, a controllable signal router for routing a variable first and second portions of the electrical signal through the high performance bypass path and the bandwidth limited path, respectively, and a summing junction to combine outputs of the high performance bypass path and the bandwidth limited path for outputting a test signal with high and low frequency content. The high performance bypass path transmits an entire bandwidth of the first portion of the electrical signal, and the bandwidth limited path transmits a controllable limited bandwidth of the second portion of the electrical signal. |
| US09258150B2 |
Channel estimation filtering
The disclosed methods and systems for improved OFDM channel estimation filtering take advantage of the presence of highly correlated adjacent subcarriers to reduce the computational intensiveness of channel estimation filtering. Specifically, baseband signals corresponding to a channel are received. The cyclic prefixes of the baseband signals are removed, and the resulting signal is transformed into the frequency domain, and compensated by a first time offset of the baseband receive signal. Subcarrier signals used to transmit the baseband signal are then extracted. Adjacent subcarriers having channel responses highly correlated to the subcarriers of the channel are identified, and the signal is compensated by a second time offset that corresponds to a minimal angle of the autocorrelation function of the subcarrier and adjacent subcarriers. The resulting signal is filtered to produce filtered channel estimates, using a filter having a filter length corresponding to the number of highly correlated subcarriers that were identified. |
| US09258148B2 |
Method for channel estimation, related channel estimator, receiver, and computer program product
An embodiment of a method for channel estimation for an Orthogonal Frequency Division Multiplexing communication system, including estimating a Time Domain Least Squares channel impulse response having a given maximum number of L taps based on a channel covariance matrix Q, and for each tap l=1, . . . , L a respective channel impulse response in the time-domain ĥl, wherein the channel impulse responses in the time-domain are grouped as a channel impulse response vector in the time domain ĥ. Specifically, an updated channel-impulse-response vector in the time domain {tilde over (h)} is determined by computing for each tap l the solution of the following system: Q1:l, 1:l{tilde over (h)}l×1=ĥ1:l, wherein the updated channel-impulse-response vector in the time domain {tilde over (h)} is computed recursively via a Levinson Durbin algorithm. |
| US09258144B2 |
Methods, systems and computer-readable media for integrating a composite MIME message
The present invention provides a method and system for integrating a composite message such as a Multipurpose Internet Mail Extensions (MIME) message. A metadata template associated with a metadata XML object is extracted from a content management system, whereby a key of the metadata XML object is passed with the request for communicating the composite message. One or more content assemblers are configured to retrieve one or more static content from one or more content management systems and one or more document management systems, in an iterative manner, based on the metadata template. A child content assembler is further configured to extract the dynamic content required for merging with the retrieved static content, to generate one or more message parts. A message generator is configured to concatenate the one or more message parts in a sequence for generating the composite message. |
| US09258140B2 |
Architecture for routing data of a customer network over provider's network in provider backbone bridges
Embodiments of the disclosure are related to routing or switching data of a customer network over a provider's network in Provider Backbone Bridge (PBB) to another customer network such that the traffic in the communication channel between the two customer networks is reduced and thus prevents packet loss. The architecture model for routing or switching data of a customer network over a provider's network is a B-component bridge used in backbone networks which performs Σn1 data path protection to prevent packet loss, data aggregation for load sharing, TDM (Time Division Multiplexing) to Ethernet Circuit Emulation. |
| US09258136B2 |
Browser with dual scripting engine for privacy protection
A data processing system has a browser with scripting engine means for executing a script. The scripting engine means implements a public scripting engine and a private scripting engine. The browser is configured to have the script executed by the public scripting engine if the script does not require access to a pre-determined resource at the system. The browser is configured to have the script executed by the private scripting engine if the script requires access to the pre-determined resource. Only the private scripting engine has an interface for enabling the script to access the predetermined resource. The scripting engine means is configured to prevent the private scripting engine from communicating data to the public scripting engine or to a non-approved server external to the data processing system. |
| US09258135B2 |
Scalable method to support multi-device link aggregation
A network device determines whether the network device has a local link for a link aggregation group (LAG), and identifies, when the network device has a local link for the LAG, the network device as a designated forwarder for the LAG. The network device also identifies, when the network device does not have a local link for the LAG, a closest network device to the network device, with a local link for the LAG, as the designated forwarder for the LAG. |
| US09258129B2 |
Resilient device authentication system
A resilient device authentication system comprising: one or more verification authorities (VAs) including a memory loaded with a complete verification set that includes hardware part-specific data, and configured to create a limited verification set (LVS) therefrom; one or more provisioning entities (PEs) each connectable to at least one of the VAs, including a memory loaded with a LVS, and configured to select a subset of data therefrom so as to create an application limited verification set (ALVS). Also disclosed is a device for use with an authentication system, comprising: a first hardware part and a second hardware part that are adapted to communicate with and perform authentication on each other; and/or a hardware part that contains two or more chips that are adapted to communicate with and perform authentication on each other. |
| US09258128B1 |
Systems and methods for creating customer-specific tools for generating certificate signing requests
A method for creating customer-specific tools for generating certificate signing requests may include (1) identifying a request from a customer for a tool for generating a certificate signing request for a digital certificate, (2) creating, in response to the request, a customer-specific version of the tool that is unique to the customer by injecting information into the customer-specific version of the tool that (a) uniquely identifies the customer and (b) identifies a desired encryption algorithm for the digital certificate and/or a desired certificate authority for the digital certificate, (3) configuring the customer-specific version of the tool to generate the certificate signing request using the injected information, and (4) providing the customer-specific version of the tool to the customer to enable the customer to generate, using the customer-specific version of the tool, the certificate signing request without having to manually provide the injected information. |
| US09258125B2 |
Generating evidence of web services transactions
Methods, systems, and products are disclosed in which generating evidence of web services transactions are provided generally by receiving in an ultimate recipient web service from an initial sender a request, the request containing a proof of message origin (‘PMO’). The PMO contains an element addressed to the ultimate recipient web service and the element bears a first signature, the first signature having a value. Embodiments also include authenticating the identity of the initial sender; creating a proof of message receipt (‘PMR’) including signing the value of the first signature; sending the PMR to the initial sender, receiving, by the initial sender, the PMR; and saving, by the initial sender, the PMR. |
| US09258120B1 |
Distributed public key revocation
Techniques for improving the security and availability of cryptographic key systems are described herein. A graph representation of a network of cryptographic key servers is created with vertices representing the servers and edges representing connections between pairs of servers. As cryptographic key events are received, the graph is used to locate the appropriate servers upon which to perform the operations associated with the events. In the event that the network requires repairing, the graph is first repaired obeying any constraints on the graph and then the network is updated to reflect alterations to the graph. |
| US09258119B2 |
Trusted tamper reactive secure storage
A cryptographic system includes a memory device and a processor. The memory device has at least two sections, including a first section and a second section. The processor is configured to determine a mode of operation, receive a signal, and selectively zeroize at least one section of the memory device based at least in part on the received signal and the determined mode of operation. |
| US09258114B2 |
Quantum key distribution (QSD) scheme using photonic integrated circuit (PIC)
Described herein are techniques related to implementation of a quantum key distribution (QKD) scheme by a photonic integrated circuit (PIC). For example, the PIC is a component in a wireless device that is used for quantum communications in a quantum communications system. |
| US09258113B2 |
Username based key exchange
A method and apparatus for an system and process for sharing a secret over an unsecured channel in conjunction with an authentication system. A client computes a message authentication code based on a hashed password value and a first random string received from the server. The client sends a response to the server that includes authentication data including a second random string. Both the client and server concatenate the first random string, second random string and username. Theses values are processed to generate as a shared master secret to further generate shared secrets or keys to establish a secured communication channel between the client and server. The secured communication can be based on stateless messaging where the decryption key associated with the message is identified by the message authentication code, which is placed within the message. |
| US09258110B2 |
Phase detector
A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed. |
| US09258105B2 |
Ethernet physical layer device using time division duplex
An Ethernet physical layer device using time division duplex. A time division duplex frame can be defined with uplink and downlink transmission periods. These defined uplink and downlink transmission periods can be adjusted based on bandwidth and latency considerations on the network link. |
| US09258104B2 |
Pattern indicator signal for new DMRS pattern
A small cell station communicates with user equipment utilizing a reduced overhead demodulation reference signal (DMRS) pattern when good channel conditions are detected. An indicator field is used to identify whether a reduced overhead DMRS pattern is being transmitted. If appropriate, the reduced overhead DMRS pattern is generated and transmitted by the small cell station and received and used by the user equipment as indicated by the indicator field. |
| US09258102B2 |
Methods and systems to mitigate inter-cell interference
The present invention provides methods and devices for mitigating inter-cell interference in communication environments having a plurality of cells. In some embodiments, a time-frequency transmission resource that includes multiple sub-carriers over multiple OFDM symbol intervals is partitioned into a first zone and a second zone. In the first zone, transmissions are transmitted on at least one frequency sub-band which is common to all of the plurality of cells. In the second zone, transmissions are transmitted on at least one frequency sub-band which is used by less than all of the plurality of cells, so as to mitigate inter-cell interference. In some embodiments, in the first zone transmissions are transmitted using a transmission power which is common to all of the plurality of cells and in the second zone transmissions are transmitted using a transmission power which is used by less than all of the plurality of cells so as to mitigate inter-cell interference. |
| US09258100B2 |
Multiple frequency band information signal frequency band compression
A wireless device includes processing circuitry and a Radio Frequency (RF) receiver section. The processing circuitry determines a set of a plurality of information signals of interest within a RF Multiple Frequency Bands Multiple Standards (MFBMS) signal. The RF receiver section down-converts the plurality of information signals by a shift frequency to produce a plurality of down-converted signals and filters the plurality of down-converted signals to produce a plurality of filtered signals corresponding to the set of the information signals of interest. The processing circuitry further extracts data corresponding to the set of the information signals from the plurality of filtered signals. |
| US09258096B2 |
Method and system for supporting multiple hybrid automatic repeat request processes per transmission time interval
A method and apparatus may be used for supporting multiple hybrid automatic repeat request (H-ARQ) processes per transmission time interval (TTI). A transmitter and a receiver may include a plurality of H-ARQ processes. Each H-ARQ process may transmit and receive one TB per TTI. The transmitter may generate a plurality of TBs and assign each TB to a H-ARQ process. The transmitter may send control information for each TB, which may include H-ARQ information associated TBs with the TBs. The transmitter may send the TBs using the associated H-ARQ processes simultaneously per TTI. After receiving the TBs, the receiver may send feedback for each of the H-ARQ processes and associated TBs indicating successful or unsuccessful receipt of each of the TBs to the transmitter. The feedback for multiple TBs may be combined for the simultaneously transmitted H-ARQ processes, (i.e., TBs). |
| US09258095B2 |
Uplink demodulation reference signal design for MIMO transmission
A base station capable of communicating with a plurality of subscriber stations is provided. The base station transmits control information and data to at least one of the plurality of subscriber stations in a subframe using a subset of antenna ports corresponding to a subset of antenna port numbers. The base station maps reference signals corresponding to the subset of antenna ports according to a transmission rank R. The base station indicates, via a cyclic shift indicator (CSI) field in an uplink grant, an assigned resource index corresponding to the mapped reference signal. The CSI field includes a cyclic shift and an orthogonal cover code (OCC) index. The subscriber station uses a resource mapping table to identify the assigned resource index based on the transmission rank, cyclic shift and OCC index. |
| US09258094B2 |
Channel state information feedback method and apparatus in a multi-node system
A method and apparatus of feeding back channel state information in a multi-node system are provided. The method includes receiving a reference signal of N nodes, wherein N is a natural number equal to or more than 2, aligning the N nodes in an order of preferring the N nodes based on a result of measuring the reference signal, generating channel state information for the aligned nodes, and transmitting the generated channel state information to the base station, wherein the channel state information is generated with respect to N node combinations configured from the aligned nodes, and wherein the N node combinations are obtained by adding next highest-priority nodes to a first node combination one by one, the first node combination consisting a highest-priority node among the aligned nodes. |
| US09258092B2 |
Sounding reference signal transmission in carrier aggregation
A cell-specific sounding reference symbol (SRS) subframe configuration and UE-specific SRS configuration are defined for carrier aggregation. For the cell-specific SRS subframe configuration, the same cell-specific SRS subframes are configured for all uplink (UL) carrier components (CCs). For the UE-specific SRS configuration, different configurations are applied for UL CCs. Also, to reduce signaling overhead, the different UE-specific SRS configuration is signaled by using an offset on top of the UE-specific SRS configuration of a primary component carrier (PCC). |
| US09258086B2 |
Allocating physical hybrid ARQ indicator channel (PHICH) resources
Certain aspects of the present disclosure relate to techniques for allocating resources for Physical Hybrid Automatic Repeat Request (HARQ) Indicator Channel (PHICH). |
| US09258085B2 |
Apparatus and method for transmitting and receiving signal in broadcasting and communication systems
A method for transmitting a signal in broadcasting and communication systems is provided. The method includes dividing source data into two or more streams and respectively coding the two or more streams through coders, selecting two or more symbols from among coded codeword symbols, mapping the selected two or more symbols to one signal constellation for modulation, and transmitting a modulated signal, in which the codeword symbols include one or more non-binary codewords, and a product of orders of finite fields on which the codeword symbols are defined is equal to an order of the signal constellation. |
| US09258082B2 |
Network system configured for resolving forward error correction during a data mode
Apparatus, systems, and methods for resolving a forward error correction (FEC) protocol include requesting, by a network node element during an auto-negotiation period between the node element and a link partner, to resolve at least one FEC mode during a data mode period, wherein auto-negotiation period occurs before the data mode period. At least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner are determined by the network node element during the data mode period. The network node determines, during the data mode period, whether to enable or disable at least one FEC mode for use by the network node element based on, at least in part, the at least one channel quality parameter. |
| US09258071B1 |
Wireless communication session initiation based on a frequency modulation (FM) radio data service (RDS)
A wireless communication system wirelessly receives a Frequency Modulation (FM) signal including audio data and Radio Data System (RDS) data. The wireless communication system audibly plays the audio data and graphically displays the RDS data from the FM signal. The wireless communication system detects action codes in the RDS data, and in response, initiates a wireless communication session with a wireless communication network. The wireless communication system also audibly captures user data. The wireless communication system then wirelessly transfers the captured user data for delivery to a server over the wireless communication session. |
| US09258070B2 |
Simultaneous feedback signaling for dynamic bandwidth selection
A method of simultaneously providing channel quality feedback information in all valid sub-channels is provided to facilitate and improve the performance of dynamic transmission bandwidth adjustment and fast link adaptation. A receiving device receives a sounding signal over a wide channel in a wireless system. The sounding signal is transmitted from a transmitting device over multiple sub-channels of the wide channel. The receiving device estimates channel quality information based on the sounding signal for each sub-channel. The channel quality information includes estimated average SNR and recommended MCS and other channel quality metrics. The receiving device transmits a feedback message to the transmitting device. The feedback message contains the estimated channel quality information for all valid sub-channels within the transmission bandwidth. The transmitting device performs dynamic transmission bandwidth selection and fast link adaptation based on the channel quality information for all valid sub-channels. |
| US09258069B2 |
Non-contiguous carrier aggregation
A method of operating a user equipment for measuring non-contiguous carriers comprises: changing a position of a local oscillator to be in the middle of the non-contiguous carriers; measuring the carriers simultaneously; estimating a power level of an interferer in a gap in the non-contiguous carriers which creates image interference; and compensating the measurement dependent on the interferer power level and an image rejection factor. |
| US09258066B2 |
Interference removal method in multi-node system and terminal using same
The present invention provides an interference removal method in a multi-node system. The interference removal method comprises receiving node information from a base station; receiving a first signal from an objective node and a second signal from an interference node; and removing interference due to the second signal by applying a receive filter to a receive signal including the first and the second signal, where the node information includes at least one of information about a reference signal included in the second signal and information about a pre-coding matrix applied to the second signal and the receive filter is determined based on the node information. |
| US09258063B1 |
Optical transmitter having multiple optical sources and a method to activate the same
An algorithm to reduce a peak current for a transmitter module with multiple laser diodes (LDs) is disclosed. When the current temperature of the LDs is higher than the target temperature, the thermo-electric cooler (TEC) controller is first activated then the LD driver to drive the LDs is subsequently activated with a substantial delay. When the ambient temperature of the LDs is lower than the target temperature, the LD driver is first driven; then, the TEC controller is subsequently activated. |
| US09258061B2 |
Individual information in lower and upper optical sidebands
This disclosure is directed to an optical transmitter arrangement 100 and a method therein producing a first RF-signal UA1 comprising a first set of data A1 carried by a subcarrier fC1, and a second RF-signal UB1 comprising a second set of data B1 carried by the subcarrier fC1. Further producing a first transform signal H(UA1) being a Hilbert Transform of the first RF-signal UA1, and a second transform signal −H(UB1) being a Hilbert Transform of the second RF-signal UB1. In addition, modulating the optical carrier fopt with the first RF-signal UA1 and the first transform signal H(UA1), and forming a first sideband SB1 comprising the first set of data A1 at one side of the frequency f0 of the optical carrier fopt. In addition, modulating the optical carrier fopt with the second RF-signal UB1 and the second transform signal −H(UB1), and forming a second sideband SB2 comprising the second set of data B1 at the other side of the frequency f0 of the optical carrier fopt. |
| US09258055B2 |
Wireless earpiece and wireless microphone to service multiple audio streams
A wireless microphone and wireless earpiece each may exchange radio frequency (RF) signals with a base unit and render content contained within the exchanged RF signals to a user. This wireless earpiece further includes a wireless interface, a processor, a speaker, a user interface, and an authentication module. The wireless interface allows the earpiece to wirelessly communicate with the base unit. The processor recovers communications exchanged with the base unit that the speaker then renders audible. A user interface coupled to the processor may alert the user to any additional incoming audio communications. Having received the alert, the user may select between the communications. The authentication module allows the wireless earpiece and microphone to pair and register with the base unit. |
| US09258054B2 |
Cyclical obstruction communication system
Techniques for improving data rates at mobile terminals that are subject to periodic channel interruptions in a beyond-line-of-sight communication system are disclosed, including improved encoding and decoding systems that identify blockages and modify receiver operation during blockages to reduce data errors. In certain embodiments, encoding, symbol mapping, interleaving, and use of unique periodic identifiers function to enable a series of packets that may be received in a blockage impaired channel with reduced errors. |
| US09258049B2 |
Communication device and orientation control method
The communication device includes: a phased array antenna having a plurality of antenna elements arranged on a plane for receiving signals transmitted from one or more transmitting devices; a signal converter for combining signals received through antenna elements for each sub-array and converting the combined signal for each sub-array into a baseband signal, the each sub-array being grouped from the plurality of antenna elements; a signal processor for decoding playback data based on respective baseband signals for sub-arrays in each resource block and detecting an error of the decoded playback data; and an orientation controller for controlling orientation of the phased array antenna based on the base band signals for the sub-arrays and a signal of a resource block with the playback data having no error. |
| US09258047B2 |
MIMO beamforming method and method of constructing a differential codebook for a wireless network
A MIMO beamforming method comprises receiving at a base station information regarding a difference between an ideal beamforming matrix and an averaged beamforming direction, using the information to construct a beamforming matrix at the base station, and performing a beamforming operation using the reconstructed beamforming matrix. Alternatively, the method comprises computing at a subscriber station an averaged beamforming direction, computing at the subscriber station a quantization index corresponding to a differential matrix in a differential codebook, and transmitting the quantization index across a wireless channel of the wireless network. The differential codebook may be constructed by identifying a codebook center and transforming a predefined codebook that is stored in a memory of a component of the wireless network. |
| US09258045B2 |
Method for efficiently transmitting signal in multi-antenna wireless communication system and apparatus for same
The present invention relates to a method for a transmitting end efficiently transmitting a signal in a wireless communication system supporting a multi-antenna and an apparatus for same. More particularly, the method comprises a step of transmitting a downlink signal based on a precoding matrix (W) for an antenna comprising a plurality of antenna elements aligned perpendicularly, wherein the precoding matrix (W) corresponds to a codebook configured so that phase increase is limited with respect to a plurality of precoding vector values populating a same column. |
| US09258040B2 |
Channel sounding for improved system performance
A transmitter generates and transmits a low rate signal to its intended receiver. Upon receiving the low rate signal, the intended receiver generates and transmits a channel sounding response (CSR), said CSR being a short burst having a predefined transmit format and carrying predetermined information. The transmitter then analyzes the CSR and determines uplink channel response, estimates downlink channel response, and determines appropriate transmit parameter settings based on the analysis and downlink response estimate. Adjustment of the transmit parameters can be made in either the MAC or PHY layer or in a combination of both. After adjusting its transmit parameters and modulating sub-carriers with user-data according to the determined transmit settings, the transmitter transmits the user-data to the receiver on a preferred portion of bandwidth. In a preferred embodiment, the transmitter also generates and transmits a transmit format control (TFC) signal containing the determined transmit parameter settings, including sub-carrier modulation information, to the receiver. |
| US09258038B2 |
Method and apparatus for transmitting reference signal in multi-antenna system
A method for transmitting a reference signal in a multi-antenna system is provided. The method includes: selecting at least one orthogonal frequency division multiplexing (OFDM) symbol in a subframe containing a plurality of OFDM symbols; allocating a channel quality indication reference signal (CQI RS) capable of measuring a channel state for each of a plurality of antennas to the selected at least one OFDM symbol; and transmitting the CQI RS, wherein the CQI RS is allocated to an OFDM symbol which does not overlap with an OFDM symbol to which a common reference signal to be transmitted to all user equipments in a cell or a dedicated reference signal to be transmitted to a specific user equipment in the cell is allocated. |
| US09258036B1 |
Narrow and secure near field communication ring device
The present invention winds an antenna wire of a NFC (Near Field Communication) chip and antenna component round inside a hard concave ring, which is then encapsulated in a room temperature-solidifiable resin adhesive. If metal material is used, then a repeater material is disposed between the metal and the NFC chip and antenna component to prevent interference thereto. The present invention thus resolves the frequently seen shortcomings of NFC circuit component failure because of the high temperature when encapsulating, poor waterproofing, and the main body of the ring being too wide. In particular, wearing the NFC ring device on a finger reduces the sensing distance of the NFC device to a minimum, and prevents data from being stolen. If there are abnormalities in receiving and transmitting information, then taking off the ring and placing the circumferential plane of the ring close to the NFC sensor improves the situation. |
| US09258029B2 |
Protective sheath
A protective sheath includes a first cover portion, a flexible display unit, a second cover portion, a flexible portion, and a control unit. The first cover portion includes an external surface portion having an opening and an internal surface portion. The flexible display unit is sandwiched between the external and internal surface portions. A second display surface of the flexible display unit is exposed by the opening. The second cover portion has two bending openings. The second cover portion is bent along the bending openings to be divided into a leaning portion and a supporting portion. Two opposite sides of the flexible portion are foldably connected to the first cover portion and the supporting portion of the second cover portion. The control unit is disposed in an accommodating space of the supporting portion and electrically connected to the flexible display unit. |
| US09258028B2 |
Spectacle-type wireless communicator
A glasses-type radio communication device (1) to be worn on the head of a user includes: left and right eyepiece parts (11), temples (14), an antenna (100) for carrying out a radio communication, hinges (17) each provided for folding each of the temples (14) towards a corresponding one of the eyepiece parts (11), while one of the temples (14) being folded towards a corresponding one of the eyepiece parts (11), the temple (14) having a shape in which the temple curves so as to be away from the antenna (100) provided in an outer edge region along an outer edge of the eyepiece part (11). |
| US09258027B2 |
Proximity detection using an antenna and directional coupler switch
Detection of an increase in a mismatch of an antenna of a radio frequency (RF) device and/or a change in a capacitance value of the antenna indicates proximity of a body to the antenna. Upon detection of proximity of a body to the antenna, reduction of transmit power of the RF device may be done to meet Specific Absorption Rate (SAR) level regulations. |
| US09258020B2 |
Scalable mapping with integrated summing of samples for multiple streams in a radio interface frame
An apparatus includes a first circuit, a second circuit, and a third circuit. The first circuit may be configured to buffer a plurality of antenna carrier sample streams. The second circuit is coupled to the first circuit and may be configured to generate message data through pipelined processing and mapping of the antenna carrier samples. The third circuit is coupled to the second circuit and may be configured to generate a master frame in response to the processed and mapped message data. |
| US09258016B2 |
Method and apparatus for controlling the decoding of codewords received by a linear block code pipelined decoder from an input buffer
A computer implemented method of controlling the decoding of codewords received by a linear block code pipelined decoder from an input buffer, the pipelined decoder comprising at least two decoding stages. The method comprises iteratively: loading the decoding stages of the pipelined decoder, executing a decoding step, determining the number of residual errors in the codewords and outputting error free codewords. The method allows the different decoding stages to be loaded with any codeword coming from the buffer or from any decoding stage of the decoder. Accordingly, the occupation rate of the pipeline is improved. |
| US09258011B2 |
Efficient two-stage asynchronous sample-rate converter
Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter. |
| US09258008B2 |
Adaptive delay based asynchronous successive approximation analog-to-digital converter
An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle. |
| US09258000B1 |
Combined lock/out-of-lock detector for phase locked loops
A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state. |
| US09257997B2 |
Analog loop filter systems, apparatus, and methods
Described herein is a distributed analog loop filter that can be employed in a phase locked loop or a delay locked loop. A circuit block of the distributed analog loop filter includes at least two parallel equivalent circuit elements. The parallel equivalent circuit elements each have an input line. The input lines for each of the parallel equivalent circuit elements are activated sequentially, one after the other. The parallel equivalent circuit elements have sequentially produced outputs that are also activated sequentially, one after another. The parallel equivalent circuit elements extend the tuning range of distributed analog filter while reducing noise associated with the distributed analog filter. |
| US09257996B2 |
Oscillator circuits and methods to compensate frequency pulling
An oscillator circuit may include a local oscillator to generate a carrier signal having a tunable frequency, a first modulator and a power amplifier coupled in cascade to the local oscillator to generate an output signal. The first modulator may be activated from a first modulating signal having a first frequency alternatively defining ON and OFF states of the first modulator. An estimator unit may receive the carrier signal during a time window and detect an estimated frequency variation of the carrier signal during the ON and OFF states. A compensation unit may include a second modulator to generate a compensation signal proportional to the estimated frequency variation and modulated with a second modulating frequency. The second modulating frequency may be substantially the same as the first modulating frequency, and the compensation signal may be added to a bias signal of the local oscillator to tune the tunable frequency. |
| US09257993B2 |
Control of multi-temperature micro-oven for MEMS devices
Disclosed are microelectromechanical system (MEMS) devices and methods of using the same. In some embodiments, a MEMS device comprises a micro-oven comprising a MEMS oscillator configured to generate a reference signal. The device further comprises a control unit comprising at least one input node configured to receive a parameter set, where the parameter set comprises at least a first parameter indicative of a sensed ambient temperature, and where the control system is configured to (i) based on the parameter set, select from a plurality of pre-characterized operation temperatures an operation temperature for the MEMS oscillator, and (ii) generate a temperature-setting signal indicating the selected operation temperature. The device still further comprises a temperature control system communicatively coupled to the control unit and configured to (i) receive the temperature-setting signal and (ii) maintain the MEMS oscillator at the selected operation temperature. |
| US09257990B2 |
Clock dividing device
A clock dividing device includes an accumulator that accumulates a first accumulated value and a denominator value and stores a second accumulated value, a register that stores a delayed accumulated value obtained by delaying the second accumulated value, a first comparison operation unit that performs a comparative operation on the second accumulated value and a numerator value and stores the second accumulated value as a greater value if the second accumulated value is greater than or equal to the numerator value, a second comparison operation unit that performs a comparative operation on the delayed accumulated value and the numerator value and stores the delayed accumulated value as a delay greater value if the delayed accumulated value is greater than or equal to the numerator value, and a third comparison operation unit that performs a comparative operation on the greater value and the delay greater value and determines the shape of a clock, wherein the shape of the clock is one of a bypass, a rising edge, and a falling edge. |
| US09257986B2 |
Rescaling
A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits. |
| US09257984B2 |
Multi-threshold circuitry based on silicon-on-insulator technology
Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors. |
| US09257983B2 |
Level shifter utilizing a capacitive isolation barrier
According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal. |
| US09257980B2 |
Measuring capacitance of a capacitive sensor with a microcontroller having digital outputs for driving a guard ring
A guard ring is provided around each capacitive sensor plate and charged to substantially the same voltage as a voltage on the capacitive sensor plate. The guard ring reduces parasitic capacitances of the capacitive sensor plate caused by differences in voltage potentials between the capacitive sensor plate, and adjacent circuit conductors, ground planes and power planes. Two digital outputs and associated voltage divider resistors are used to drive the guard ring voltage to substantially the same voltage as the voltage on the capacitive sensor plate. |
| US09257978B2 |
Multiplex driving circuit
A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals. |
| US09257974B1 |
Quadrature phase relaxation oscillator
A low voltage quadrature phase wideband relaxation oscillator. An ultra-wideband tuning range from Mega to Giga Hz order is also realized by tuning the I/Q coupling factor, zeros and poles. Preferably, a novel synchronous quadrature injection lock is proposed to validate low noise performance. |
| US09257972B1 |
High speed dynamic flip-flop circuit with split output driver
A flip-flop circuit is disclosed. The flip-flop circuit includes pull-up and pull-down circuits each coupled to a data input and configured to be activated responsive to a clock signal transition from a first phase to a second phase, depending on the input data. A write circuit is configured to write data into a latch of the flip-flop responsive to activation of one of the pull-up and pull-down circuits. An output driver circuit includes a dynamic portion and a static portion, with the dynamic portion being activated responsive to activation of one of the pull-up and pull-down circuits. Activation of the dynamic portion may occur concurrently with writing of the data into the latch. The output driver circuit also includes a static portion. After the clock transitions back to the first phase, the static portion may drive and hold the output while the dynamic portion is deactivated. |
| US09257969B2 |
Frequency locking oscillator
A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle. |
| US09257966B2 |
Clock correction circuit and clock correction method
An operation clock generation circuit performs calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock. |
| US09257965B2 |
VCC charge and free-wheeling detection via source controlled MOS transistor
A driver circuit using a power converter allows free-wheeling detection and/or provision of supply voltage. A circuit controls a switching state of a power switch. A first port of the switch is coupled to an inductor. The circuit is coupled to a control port of the switch wherein the control port of the switch is different from the first port of the switch. The circuit comprises a unit generating a signal for controlling the switching state of the switch wherein the signal is provided to the control port of the switch. Furthermore, the circuit comprises free-wheeling sensing means to detect an oscillation of a voltage at a measurement port of the switch wherein the measurement port of the switch is different from the first port of the switch and wherein the oscillation of the voltage at the measurement port indicates free-wheeling of the inductor. |
| US09257960B2 |
Electroacoustic transducer having reduced losses due to transverse emission and improved performance due to suppression of transverse modes
An electroacoustic transducer has reduced loss due to acoustic waves emitted in the transverse direction. For this purpose, a transducer comprises a central excitation area, inner edge areas flanking the central excitation area, outer edge areas flanking the inner edge areas, and areas of the busbar flanking the outer edge areas. The longitudinal speed of the areas can be set so that the excitation profile of a piston mode is obtained. |
| US09257959B2 |
Resonator element, resonator, oscillator, electronic apparatus, sensor, and moving object
A resonator element includes a quartz crystal substrate having a base, a pair of vibration arms extending from the base, and a support arm located between the vibration arms and extending from the base in the direction in which the vibration arms extend. Each of the vibration arms has an arm portion and a hammer head provided at the front end of the arm portion. The arm portion has a pair of principal surfaces and a groove that has a bottom and opens through each of the principal surfaces. In the invention, the width of each of bank-shaped portions of each of the principal surfaces that are disposed side by side on opposite sides of the groove along the width direction of the vibration arm perpendicular to the longitudinal direction thereof is set at 6 μm or smaller. |
| US09257956B2 |
Passive filter
A passive filter may include at least one elliptical filter unit and at least one asymmetric rejection filter unit coupled in series with the elliptical filter unit. The at least one asymmetric rejection filter unit may have a frequency response curve that includes a dip with different attenuations on either side, and an overshoot upon exiting the dip at the side with the lower attenuation. |
| US09257955B2 |
Common mode noise reduction circuit
A common mode noise reduction circuit includes at least one first input end, at least one second input end, at least one first output end, and at least one second output end. The circuit is further provided with at least one resistor, at least one inductor, and at least one capacitor, symmetrically disposed within the circuit loop defined by the four ends. Common mode noise, after entering the circuit, is transformed into heat by the resistance of the circuit such that the common mode noise is suppressed. Differential mode signals, on the contrary, after entering the circuit, can pass through the circuit with minimum loss. |
| US09257942B2 |
Audio amplifier apparatus
An audio amplifier apparatus for driving a loudspeaker is provided. The audio amplifier apparatus includes a soft charge unit, a first amplification module, and a second amplification module. The soft charge unit is coupled to the loudspeaker through an output terminal and supplies a driving current according to a first control signal to soft charge the loudspeaker, so as to gradually increase a voltage level on the output terminal. The first amplification module receives an audio signal according to the first control signal and amplifies the audio signal to output a first amplified signal for driving the loudspeaker. The second amplification module receives the audio signal according to a second control signal and amplifies the audio signal to output a second amplified signal for driving the loudspeaker. The soft charge unit generates the second control signal by comparing the voltage level on the output terminal with a predetermined voltage level. |
| US09257941B2 |
Adaptive biasing scheme for an amplifier
There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal. |
| US09257938B2 |
Integrated system for cooling a building, collecting rainwater, and cleaning a rooftop solar array
This invention provides a simple integrated system that uses roof-spray, water collection, and water storage components to cool a building, collect and store rainwater, and clean a rooftop solar array. |
| US09257937B2 |
Minimal penetration modular roof-top mounting racks and solar photovoltaic systems incorporating the same
The present invention provides for a modular, plug-and-play DC/AC compatible solar photovoltaic power system and mounting frames therefor, having inexpensive modular designs which require no or minimal penetration for rooftop installation and provide enhanced wind-induced position disruption protection. |
| US09257936B2 |
System and method for efficient drive of capacitive actuators with voltage amplification
A circuit for driving a plurality of capacitive actuators, the circuit having a low-voltage side, a high voltage side and a flyback transformer between the two. The low-voltage side comprises first and second pairs of low-side switches connected in series across an input voltage. The flyback transformer has a primary winding connected to the two pairs of switches. The high-voltage side has a pair of switches connected between the secondary winding of the flyback transformer and a ground and a plurality of capacitive loads and bidirectional switches to connect the loads to the secondary winding of the flyback transformer and a ground. |
| US09257934B2 |
Apparatus for parallel operation of pulse-width modulation power converters
To perform an anti-windup control without interference with a cross current compensating function even in case of voltage saturation.There is provided a feedback value calculating section to calculate an average of voltage commands V1_cmd, V2_cmd after output limitation, as a feedback value. As a deviation used for an integral calculation of a current control section 6a, 6b, a sum obtained by adding a product to a deviation between a current command value Id_cmd, Iq_cmd and a current detection value Id_det, Iq_det is used. The product is a quantity obtained by multiplying a saturation quantity by a feedback gain Kfb. The saturation quantity is a saturation quantity of an operation quantity limited by a voltage command limiting section 3a, 3b, and the saturation quantity is a deviation or difference between a feedback value V_fb (Vd_fb, Vq_fb) and the voltage command Vd_cmd. |
| US09257932B2 |
Control device for servomotor
A control device of a servomotor includes a current control loop selecting unit configured to select a first current control loop or a second current control loop having a response speed slower than that of the first current control loop, as a current control loop for controlling a current flowing through the servomotor; a filter configured to attenuate an input or an output of the first current control loop or the second current control loop selected by the current control loop selecting unit in accordance with a set attenuation ratio in a specific frequency range; and a filter attenuation ratio setting unit configured to set, as the attenuation ratio of the filter, a first attenuation ratio when the first current control loop is selected by the current control loop selecting unit, and a second attenuation ratio smaller than the first attenuation ratio when the second current control loop is selected. |
| US09257925B2 |
Speed control for power tools
A power tool, typically battery-operated, such as a lawnmower, comprising: a driven element (9), an electric motor (7) coupled to the driven element so as to drive the driven element, an electric power source (2) electrically coupled to the motor (7) so as to supply electric current to the motor (7) and a control circuit (3) arranged to control the supply of electric current to the motor (7) from the power source (2), and a current sensor (6) operable to output a current signal indicative of the current flowing through the motor (7); in which the control circuit (3) has a high speed mode (40) and a low speed mode (32), the control circuit (3) being arranged so that: when it is in the high speed mode (40), the control circuit supplies electric current to the motor (7) so as to attempt to drive the driven element (9) at a first desired speed (54); when it is in the low speed mode (32), the control circuit supplies electric current to the motor (7) so as to attempt to drive the driven element (9) at a second desired speed (52) which is lower than the first desired speed (54); and the control circuit (3) switches between the high speed mode (40) and the low speed mode (32) dependent on the current signal. As such, energy can be saved by efficient use of electrical power, by increasing the speed of the driven element when the load increases. |
| US09257924B2 |
Method for determining the rotary position of the rotor of an electric machine
A method for determining the rotary position of the rotor of an electric machine, which includes star-connected phase conductors, wherein a measurement signal representing the rotary position of the rotor within a magnetic half-period is determined from the potential at the star point. At a measurement time a specified voltage is applied to the ends of all the phase conductors by forcing the star point to a specific potential. At a time following the measurement time a voltage that deviates from the specified voltage is applied to the ends of one of the phase conductors. Then the measurement signal is derived from the current that develops from the measurement time in a connection of the star point to the specified potential. |
| US09257920B2 |
Method and related driver of a permanent magnet synchronous electric motor
A method of driving a permanent magnet synchronous electric motor includes sensing or estimating a back electromotive force induced in at least a winding of the motor by the rotation of a rotor of the motor; and reading, from a memory, values of a first voltage waveform having a phase angle with respect to the back electromotive force. The method also includes generating a driving voltage corresponding to the sum of values of a control voltage, obtained as product of the values of the first voltage waveform by a first coefficient determined as a function of a desired value of motor torque, and values of a cancelation voltage of the back electromotive force. The method also includes applying the driving voltage at the motor winding. |
| US09257916B2 |
Power inverters with multiple input channels
A method and apparatus is disclosed for intelligently inverting DC power from DC sources such as photovoltaic (PV) solar modules to single-phase or three-phase AC power to feed the power grid for electricity generation. A power inverter with multiple input channels or input ports that can connect to multiple DC sources is disclosed. |
| US09257915B2 |
Bridge rectifier circuit
A bridge rectifier circuit has first to fourth diode groups which are bridge-connected and each include a main diode and sub-diodes being enabled to be respectively connected in parallel to the main diode, first and second input terminals to which AC power is supplied, a first output terminal connected to the first input terminal via the first diode group and connected to the second input terminal via the second diode group, a second output terminal connected to the first input terminal via the third diode group and connected to the second input terminal via the fourth diode group, and a control circuit configured to detect a current flowing through at least one diode group and increases the number of sub-diodes connected in parallel to the main diode of the diode group through which the detected current flows in accordance with an increase in the detected current. |
| US09257914B2 |
Active rectification control
A method of active rectification control of an active rectifier includes detecting a phase angle and a frequency of a voltage input of the active rectifier; regulating a DC output voltage of the active rectifier with d-q components of a pole voltage; and aligning a reference current input of the active rectifier to the d-q components of the pole voltage. |
| US09257912B2 |
Switching power supply device
In a switching power supply device, a partition portion that includes a slit divides a winding portion of a bobbin. A primary winding of a transformer is wound to a height h1 in a first section, and a secondary winding is wound to a height h2 in a second section. A low side drive winding and a high side drive winding are wound around the primary winding to a height h3 with the high side drive winding being located toward the secondary winding. |
| US09257907B2 |
Semiconductor integrated circuit and method for operating the same
A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q11 and Q12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q12 from an on-state to an off-state by delaying Q12 relative to Q11. Q11 and Q12 are divided into a plurality of parts inside a semiconductor chip Chip 1, a plurality of partial first transistors formed by dividing Q11 and a plurality of partial second transistors formed by dividing Q12 are alternately arranged in an arrangement direction of Q11 and Q12, inside the semiconductor chip Chip 1. |
| US09257906B2 |
Internal compensation for power management integrated circuits
A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage. |
| US09257905B1 |
Method and apparatus for power supply with fast transient response
An efficient power supply with fast transient response has been disclosed. In one implementation, two loops with different frequency responses are combined to provide an efficient, fast responding power supply. |
| US09257904B2 |
Direct current conversion circuit
A direct current (DC) conversion circuit suitable for driving a load comprises a buck-boost converter, a resonant stage circuit and an output stage circuit. The buck-boost converter has two input ends receiving a first DC signal, and two output ends outputting a second DC signal. The resonant stage circuit has two input ends receiving the second DC signal. The resonant stage circuit converts the second DC signal to energy and further converts the energy to a negative voltage by a resonance effect. The resonant stage circuit has two input ends outputting the energy. The output stage circuit has two input ends receiving the energy to store the energy, and two output ends outputting energy to the load. |
| US09257898B1 |
Power supplying circuit and soft-start circuit of the same
The soft-start circuit includes a first charging transistor, a first capacitor, a second charging transistor, a second capacitor and a clamping p-type transistor. The first charging transistor is conducted in response to activating pulses to charge the first capacitor through a first output node such that a first output voltage at the first output node gradually increases. The second charging transistor is conducted in response to the first output voltage to charge the second capacitor through a second output node such that a second output voltage at the second output node gradually increases. The clamping p-type transistor includes a source terminal electrically connected to a clamping node, a drain terminal connected to a ground terminal and a gate electrically connected to the second output node, and is conducted when a voltage at the clamping node exceeds a clamping threshold value to pull low the voltage at the clamping node. |
| US09257897B2 |
Circuit arrangement for protecting electronic devices against incorrect logic voltages
The invention is based on the problem of devising a circuit arrangement (10) for protecting electronic devices from incorrect logic voltages, wherein this circuit arrangement delivers increased protection against overvoltages, so that this circuit arrangement could also be used in multi-channel fail-safe systems that satisfy, for example, Performance Level “e” according to DIN EN ISO 13849. The circuit arrangement (10) has an input terminal (80) for connecting a power supply device and at least one voltage converter (90) that delivers, on the output side, an adjustable logic voltage. A controllable switching element (70) is connected between the one or more voltage converters (90, 95) and the input terminal (80). Furthermore, a first monitoring device (20) is provided for monitoring the logic voltage. The first monitoring device (20) is constructed so that it triggers the opening of the switching element (70) when the logic voltage reaches or exceeds a predetermined threshold. |
| US09257896B1 |
Control circuit of power converter and method for maximum power point tracking
A control circuit of a power converter including a first and a second control modules is provided. The first control module sets sampling points for a ripple signal of an input voltage according to a reference signal. The first control module determines whether a power point is the maximum power point according to ripple voltages of the sampling points. The second control module controls the power converter to output a maximum power according to the maximum power point based on the determination result of the first control module and the reference signal. An embodiment of a method for tracking a maximum power point is provided. The input voltage of the power converter is measured. The sampling points are set for the ripple signal of the input voltage and phase information of the ripple signal is determined, such that the maximum power point is determined by using the ripple voltages. |
| US09257891B2 |
Vibration type electromagnetic generator
A vibration type electromagnetic generator is formed by a nonmagnetic material and includes a hollow first pipe whose both end portions are closed, a magneto coil which is wound around the periphery of the first pipe and which is provided with solenoid coils, and a movable magnet which is arranged inside the first pipe and which is movable along a winding axis direction of a magneto coil. Then, the movable magnet includes a plurality of magnets and a magnet fixing unit composed of a nonmagnetic body for fixing the plurality of magnets whose same magnetic poles are facing one another, and among the plurality of solenoid coils, the coil length of one or more solenoid coils are made to be length equal to or greater than the magnet length of the magnet. |
| US09257888B2 |
Rotary solenoid
In one of its aspects the technology disclosed herein concerns a process of making a rotary solenoid. In a generic mode, the process comprises fitting together two mating core half members (22A, 22B) of a stator until two respective pole faces (32A, 32B) of the two mating core half members (22A, 22B) press to a positive stop against a precision diameter pin positioned between the two mating core half members and so that the two mating core half members interlock at the positive stop. The process further comprises removing the precision diameter pin to provide an axially extending space comprising a predetermined distance between the two respective pole faces (32A, 32B). The process further comprises inserting a rotor (26) within the axially extending space. The process further comprises fitting the two mating core half members (22A, 22B) and the rotor (26) between the two opposing end caps (20, 30). The act of fitting the two mating core half members and the rotor between the two opposing end caps preferably comprises aligning the two pole faces (32A, 32B) with pole face alignment features provided on the two opposing end caps whereby the two pole faces are retained at a predetermined position relative to the rotor. |
| US09257887B2 |
Brush DC motor with permanent magnet rotor
A direct current motor has a wound stator, a permanent magnet rotor having a commutator assembly, and brush gear. The brush gear has a first pole brush, a second pole brush and a plurality of commutating brushes. The commutator assembly has a cylindrical insulating base, and first and second members fixed to the base. The first member includes a radially extending first slip ring and a number of axially extending first bars. The second member includes a radially extending second slip ring and a number of axially extending second bars. The first and second pole brushes make continuous sliding contact with the first and second slip rings respectively. The first and second bars are fixed to the outer cylindrical surface of the base and form a cylindrical surface against which the commutating brushes make sliding contact. |
| US09257883B2 |
Electric machine with rotor interior ventilation
An electric machine includes a stator, a rotor interacting magnetically with the stator, a housing surrounding the stator and rotor, and a hollow shaft provided for arrangement of the rotor and mounted on the housing. A radial fan is mounted rotationally fixed on the hollow shaft on the ventilation side. A section of a fan blade of the radial fan extends axially away from the housing to a greater extent than the hollow shaft. A guide element with radially extending plate is arranged in the hollow shaft, wherein the plate is arranged axially further away from the housing than the end side of the hollow shaft on the ventilation side. An inner coolant flow can thus be delivered from the section of the fan blade out of the hollow shaft through a passage between the end side of the hollow shaft on the ventilation side and the plate radially outwards. |
| US09257882B2 |
Vehicle AC generator
Provided is a vehicle AC generator having a retainer attached on a bearing containing portion of a front bracket, thereby realizing temperature reduction in a bearing without deteriorating the cooling performance as a whole. In the vehicle AC generator, a front bracket 2 has a bearing containing portion 21 supporting a bearing 5 fitted therein, and an air inlet 22 that is provided along the outer circumference of the bearing containing portion 21 and allows cooling air from a fan 83 to pass therethrough. In addition, a retainer 15 is attached on the bearing containing portion 21, so as to cover the bearing 5. The retainer 15 has a planar shape, and has a fin 15b as a surface area increasing portion for increasing an area of contact with the cooling air, formed at a position facing to and outside the air inlet 22 in the shaft direction. |
| US09257873B2 |
Method and apparatus for generator stator core separation
An intercoupled stator core is separated from a non-vertically oriented (including horizontal) generator frame by decoupling the stator core and frame coupling members and interposing a slidable member between them. Thereafter they are separated relative to each other on the sliding member. The sliding or slidable member may comprise a rail, or alternatively a roller adapted for rolling contact with one of the opposed stator core or generator structures and an engagement surface in contact with the other structure. A system for separating the stator core from a non-vertically oriented generator frame includes first and second raising end plates adapted coupled to axial ends of the stator core. The end plates project outwardly from the generator frame ends, for coupling to a raise mechanism. After the raise mechanism raises the stator core the slidable member is interposed between the stator core and generator frame. |
| US09257872B2 |
Linear motor
A linear motor is provided. The linear motor includes a first member including a plurality of armature modules each comprising a magnetic core, a plurality of salient poles, and coils, where the coils are wound around a portion or all of the salient poles or the magnetic core between the salient poles; and a second member including one or more permanent magnet modules each including a plurality of permanent magnets each projected toward the magnetic core to be arranged between two salient poles of the armature module, where poles of the permanent magnets are alternated in a moving direction of the linear motor. Power is supplied to the coil of each armature module such that a thrust according to a traveling magnet fie is generated by using as one unit an S number of armature modules and a P number of permanent magnets arranged in the moving direction. |
| US09257869B2 |
Method and device for charging a battery
A method for charging a battery, in particular a lithium ion battery, be performing the following: charging the battery using a constant charging current in a first phase, charging the battery using a constant charging voltage in a subsequent second phase, ending the charging as a function of a specifiable boundary value of the charging current in the second phase. In this context, the following operations are provided: comparing a guide voltage specified for setting the constant voltage to at least one stored switch-off value determined as a function of the boundary value, and ending the charging when the guide voltage reaches the switch-off value. Also described is a device for charging the battery. |
| US09257868B2 |
Integrated power system control method and related apparatus with energy storage element
Systems and methods for controlling a hybrid power architecture to provide fuel or energy savings. Recharge time of an energy storage device (ESD) is reduced through the application of a controlled potential and ESD recharge time management over the life of the hybrid system through manipulation of the ESD charge state window of operation. Fuel or energy savings is achieved by controlling the partial-state-of-charge (PSOC) window of the ESD based on a recharge resistance profile of the ESD and by controlling a charging potential applied to the ESD based on a recharge current and/or the estimated recharge resistance profile of the ESD. |
| US09257859B2 |
Dynamic battery control based on demand
A system is provided that includes a plurality of power units each configured to supply power. Additionally, the system includes a plurality of contacts each configured to toggle an electrical connection of each of the plurality of power units as a network. Moreover, the network is configured to supply power to a load. Furthermore, the system includes a controller configured to control when each of the plurality of contacts toggle according to a power state, and the power state includes information regarding a charge of each power unit, a load demand, and a supplied power being supplied by the plurality of power units. |
| US09257857B2 |
Cable positioning device and charger using same
A cable positioning device and a charger using the cable positioning device is disclosed to include a cable positioning device mounted in a mounting structure inside the charger to secure a cable. The cable positioning device includes a polygonal column that can be forced by an external pressure to deform non-elastically and to further tightly fit the cable, having at least one surface thereof abutted against an inner wall of the mounting structure in the axial direction of the cable to prevent displacement of the cable positioning device and the internal electric wires of the cable due to accidental twisting of the external part of the cable, improving the cable installation efficiency. |
| US09257844B2 |
Arrangement and method for reactive power compensation
An arrangement and a method for reactive power compensation in connection with a power transmission line. The arrangement includes at least one transformer and at least one reactive power compensator connected to the low-voltage side of the transformer and at least one adapter reactor, the adapter reactor being connected in series with the transformer so that the reactive power compensator is connected to the power transmission line via the transformer and the adapter reactor. |
| US09257841B2 |
USB connector, PCB connected thereto, and USB device
A USB connector, a PCB connected to the USB connector, and a USB device are provided. The USB connector includes a metal surface, and on the metal surface, a solid metal part is set at a location corresponding to a spring of a socket, so that the spring contacts the solid metal part after the USB connector is inserted into the socket to reduce electromagnetic interference. The USB connector may include an in-line weld leg; a metal enclosure located at the same side as the in-line weld leg fully contacts a PCB when the USB connector is connected to the PCB; and contact surfaces on the USB connector that contact the PCB are metal surfaces. The PCB includes a suppression circuit configured to suppress harmonic waves in USB data transmission. |
| US09257834B1 |
Single-laminate galvanic isolator assemblies
An isolator assembly is disclosed. The assembly comprises a laminate consisting essentially of a block of homogenous material and a set of electrical contacts. A first die is coupled to a surface of the laminate. An isolation barrier is located entirely above the surface of the laminate. A second die is coupled to the laminate. The second die is galvanically isolated from the first die by the isolation barrier. The second die is in operative communication with the first die via the isolation barrier and a conductive trace on the laminate. The first die, the second die, the laminate, and the isolation barrier are all contained within an assembly package. |
| US09257830B2 |
Semiconductor device
In a semiconductor device, a surge voltage is lowered on turning OFF of a switching element, and output current is reduced on turning ON of the switching element in a non-saturated condition to achieve a reduced amount of self-heating. The semiconductor device can comprise a semiconductor switching element, an overvoltage protection circuit, and a resistance circuit to transmit a control signal for turning the switching element ON and OFF to a control terminal of the switching element. The semiconductor device can further comprise a voltage detecting switch that receives a signal corresponding to a voltage appearing at the output terminal of the switching element on turning OFF of the switching element, and a gate resistor change-over switch that operates according to a voltage of a timing capacitor connected to the output side of the voltage detecting switch to increase a resistance value of the resistance circuit. |
| US09257829B2 |
Grounding apparatus
A grounding apparatus includes a current detector configured to detect a current flowing in the ground line, a fuse inserted in series in a part of the around line and configured to melt when the current flowing in the ground line exceeds the first protection setting value, not destroying the current detector, and then exceeds the first protection setting value, causing a complete grounding fault, and a determination device configured to give an open command to the circuit breaker when the current detected by the current detector exceeds the first protection setting value of the circuit breaker. |
| US09257825B2 |
Power electronics interconnection for electric motor drives
The bus bar includes a first bus bar layer formed of a first generally uniform thickness of a first bus bar conductor; a first dielectric layer overlying a top surface of the first bus bar layer; and a second bus bar layer formed of a second generally uniform thickness of a second bus bar conductor overlying a top surface of the first dielectric layer and the top surface of the first bus bar layer wherein: the first bus bar layer includes a first via for receipt of a first electrical lead of an electrical component and a second via for receipt of a second electrical lead of the electrical component and wherein: the first dielectric layer and the second bus bar layer each include a via aligned with the first via wherein the first electrical lead is extendable from beneath the first bus bar layer through the first dielectric layer and through the second bus bar layer. |
| US09257821B2 |
Cable stripper
A cable stripper having a stripper body having at least one hole and opposite first and second ends, a cable stripper guide having a connection part and a guiding part, the connection part engaging the first end of the cable stripper body, at least one marble located within the at least one hole in the cable stripper body, and at least one spring having first and second ends and being located within the at least one hole in the cable stripper body and engaging the at least one marble. |
| US09257819B1 |
Electrical fishing system for a drop ceiling
An electrical wire fishing system provides assistance in the pulling of cable through drop ceiling cavities. The system comprises a first component which is used at the entrance to the drop ceiling cavity and comprises a tube held in place by clamps. The first component utilizes a pair of spring-loaded cams which allow the cable to only travel in a single direction. Should the cable attempt to fall down, the cams will lock in place preventing such an action. A second component is used at the exit of the ceiling cavity and utilizes a pair of guideposts. These guideposts guide the cable out of the ceiling cavity and prevent it from becoming caught up on ceiling grid. With the system properly in place, cable can be pulled through a ceiling cavity by a single person. |
| US09257818B2 |
Enclosure power distribution architectures
Computational enclosures may be designed to distribute power from power supplies to load units (e.g., processors, storage devices, or network routers). The architecture may affect the efficiency, cost, modularity, accessibility, and space utilization of the components within the enclosure. Presented herein are power distribution architectures involving a distribution board oriented along a first (e.g., vertical) axis within the enclosure, comprising a power interconnect configured to distribute power among a set of load boards oriented along a second (e.g., lateral) axis and respectively connecting with a set of load units oriented along a third (e.g., sagittal) axis, and a set of power supplies also oriented along the third axis. This orientation may compactly and proximately position the loads near the power supplies in the distribution system, and result in a comparatively low local current that enables the use of printed circuit boards for the distribution board and load boards. |
| US09257816B2 |
Vertical cavity surface emitting laser and atomic oscillator
A vertical cavity surface emitting laser includes: a substrate; a first mirror layer; an active layer; a second mirror layer; a first electrode which is electrically connected to the first mirror layer; a second electrode which is electrically connected to the second mirror layer; and a pad which is electrically connected to the second electrode, in which the first mirror layer, the active layer, and the second mirror layer configure a laminated body, the laminated body includes a resonance portion, an insulation layer is provided on a side surface of the laminated body, in a plan view, the insulation layer has a shape line-symmetrical with respect to a virtual straight line passing through a center of the resonance portion, the pad is provided over the insulation layer, and in the plan view, the pad is only provided on one side of the virtual straight line. |
| US09257815B1 |
Optical semiconductor device
An optical semiconductor device includes: a mesa stripe structure including an n-type cladding layer, an active layer, and a p-type cladding layer laid one on another; and a buried layer buried on opposite sides of the mesa stripe structure, wherein the active layer is a multiple quantum well structure having well layers and carbon-doped barrier layers, the buried layer includes a p-type semiconductor layer and an Fe-doped or Ru-doped high-resistance semiconductor layer laid one on another, side surfaces of the n-type cladding layer are covered with the p-type semiconductor layer and are not contiguous with the high-resistance semiconductor layer, and side surfaces of the active layer are not contiguous with the p-type semiconductor layer. |
| US09257813B2 |
Flip chip type laser diode
A flip chip type laser diode includes a substrate, a first semiconductor layer, an emitting layer, a second semiconductor layer, at least one current conducting layer, a patterned insulating layer, at least one first electrode and a second electrode. The first semiconductor layer is disposed on the substrate. The emitting layer is disposed on a part of the first semiconductor layer. The second semiconductor layer is disposed on the emitting layer and forms a ridge mesa. The current conducting layer is disposed on a part of the first semiconductor layer. The patterned insulating layer covers the first semiconductor layer, the emitting layer, a part of the second semiconductor layer and a part of the current conducting layer. The first electrode and the second electrode are disposed on areas of the current conducting layer and the second semiconductor layer which are not covered by the patterned insulating layer. |
| US09257812B2 |
Laser module, light source device, and method for fabricating laser module
Provided is a laser module wherein any defective laser device can be isolated by performing burn-in on laser devices mounted on a mounting substrate. The laser module includes laser devices that emit laser light, a driver IC for driving the laser devices, a mounting substrate on which the laser devices and the driver IC are mounted, a common electrode terminal to which a common electrode of the laser devices is connected, individual electrode terminals to which individual electrodes of the laser devices are respectively connected, driver terminals to which the driver IC is connected, and test terminals which are respectively connected to the common electrode terminal and the individual electrode terminals, and to which an external power supply is to be connected when performing burn-in of the laser devices, wherein the number of the laser devices and the number of the test terminals are each larger than the number of the driver terminals. |
| US09257811B2 |
Broad band continuous tunable laser
The invention relates to a broad band continuous tunable laser. The laser includes a first laser cavity mirror, a laser gain medium, an intracavity collimating lens, an active optical phase modulator, a tunable acousto-optic filter, and the tunable laser further includes an intracavity reflection mirror to reflect the first order diffracted beam of the first diffraction back to the tunable acousto-optic filter to compensate the wavelength shift, a tunable Fabry-Perot filter arranged in the optical path of the second diffraction beam, a second laser cavity mirror and a laser drive and control circuit system. A stable laser output and the precision optical frequency tuning for less than 1 GHz frequency accuracy within a wide spectrum range can be realized. The invention is compact with stable performance, low cost for volume production and easy installation without moving parts. |
| US09257810B2 |
Optical device and fiber laser device
An optical device includes a first medium which (i) has a refractive index lower than (a) a refractive index of an outermost shell part in a first outer shell removed area of a first optical fiber and (b) a refractive index of an outermost shell part in a second outer shell removed area of a second optical fiber and (ii) surrounds an entire side surface of the first outer shell removed area. Moreover, the optical device includes a second medium which (i) has a refractive index higher than a refractive index of an outermost shell part in the second outer shell removed area and (ii) surrounds at least a part of a side surface in the second outer shell removed area. The second outer shell removed area has a diameter larger than a diameter in the first outer shell removed area. |
| US09257808B1 |
Integrated wire harness batch production with double buffer assembly systems and methods
Automated wire harness production systems and methods that rapidly present individual circuits to an assembler operating a wire harness layout board. Automatic wire indexing, sorting, and delivery systems transfer circuits into, and retrieve circuits from, a transportable programmable, automated, indexed storage system equipped with an array of individual circuit tubes, and a script-controlled assembly system sends visual, aural, and other cues to help an assembler populate and configure a wire harness layout board with connector blocks and turn posts, and guides the assembler in building, testing, reworking, and delivering the corresponding batch of wire harnesses. |
| US09257806B2 |
Pliers for crimping terminals on wires or conductors
Pliers include a pair of handles, at least one arm member connected to one of the handles, a seat body secured in a receiving room of the arm member, a working jaw detachably engaged with the seat body, and a control assembly to control whether the working jaw is allowed to be released from the seat body. The working jaw defines in a side thereof an indentation to be communicated with a through hole of the seat body. The control assembly has a knob and a positioning pin. Rotation of the knob displaces the knob axially with respect to the seat body, causing the positioning pin to move between a locking position to stop the working jaw from departing from the seat body, and a releasing position where the working jaw is allowed to be removed from the seat body. |
| US09257805B2 |
Rotatable frame, connector, and connector support system
A rotatable frame is provided for accommodating a connector. The rotatable frame can be used with a plate and includes a frame body, two positioning portions, and two pivots. The frame body has a first sidewall, a second sidewall, a top plate, and a bottom plate, wherein the first sidewall, the second sidewall, the top plate, and the bottom plate are connected to enclose an accommodation space for accommodating the connector and to form a connector inserting opening. The two positioning portions are respectively formed on the top plate and the bottom plate at one side that is near the connector inserting port. The two positioning portions respectively have a blocking surface, wherein the blocking surface obliquely extends away from the connector inserting opening. The two pivots respectively protrude from the outer side of the first sidewall and the outer side of the second sidewall coaxially. |
| US09257803B2 |
Power strip holder
A combination storage receptacle and power strip/surge protector holder includes an enclosure perimeter defining an aperture for receiving objects, and a power strip mounted to the enclosure perimeter for reducing the clutter of wiring of power strips. |
| US09257802B2 |
Slidable low profile electrical connector
An electrical connector includes a base with a number of contacts, a cover pivotally mounted to the base, a pair of supporting components for mating with the cover and a pair of rail brackets for mating with the base. Each supporting component is pivotal between an opening status and a closed status relative to the base. The base is slidable relative to the rail brackets along a front-to-back direction. The cover and the pair of supporting components are mateable with each other in condition that one of the cover and the pair of supporting components pivots clockwise while a remaining one of the cover and the pair of supporting components pivots anticlockwise. |
| US09257801B2 |
Electrical connector with shielding plate
An electrical connector has a conductive shell, a terminal module and a shielding plate. The conductive shell has a mating portion and an accommodate room. The mating portion has a first mating face. The terminal module is secured in the accommodate room and has a first insulator and a plurality of first terminals. The first insulator has a first face and a second face. Each of the first terminals has a first contacting portion protruding out of the first face of the first insulator. The shielding plate is disposed in the accommodate room and contacts with the conductive shell. The shielding plate presses on the second face of the first insulator so as to make first contacting portions be exposed to the first mating face. The disposition of the shielding plate has the function of pressing on the terminal module and preventing the interference of signal transmission between the terminals. |
| US09257799B2 |
Vehicle electronic connector hub
A console assembly includes a console housing with a storage compartment having a member in a wall that is rotatable between a plurality of positions. The member includes an electronic port for connecting an electronic device that is accessible from within the compartment when the member is rotated to a first position and accessible from outside the compartment when the member is rotated to a second position. A second port may be added to the member such that the member can rotate to an intermediate position where one port is accessible from within the compartment while the second port on the member is simultaneously accessible from the outside of the compartment. |
| US09257798B2 |
Socket having overheating destructive limiting element
A socket having an overheating destructive limiting element includes a housing, a live wire conductive plate, a neutral wire conductive plate, at least one live wire terminal, at least one neutral wire terminal, and at least one limiting element. The live wire terminal includes a live wire contact portion in contact with the live wire conductive plate. The neutral wire terminal includes a neutral wire contact portion in contact with the neutral wire conductive plate. The limiting element is an insulating body, and is placed at contact parts of the live wire conductive plate and the live wire contact portion, and/or at contact parts of the neutral wire conductive plate and the neutral wire contact portion. When an operating temperature becomes excessively high, the limiting element becomes deformed and destructed to form a turn-off position. |
| US09257797B2 |
Cable assembly having an improved circuit board
A cable assembly (100) includes a cover (8) defining an outer cavity (822), a shielding cage (7) defining an inner cavity (712) and being mounted into the outer cavity, an inner board (20) assembled in said inner cavity, and a cable (5) assembled onto the inner board. The inner board includes a top surface (38), a bottom surface (37) and two side surfaces (31). The side surface has a first ground pad (310) adapted to connect with the shielding cage, the bottom surface has a second ground pad (33) adapted to connect with the cable, and the top surface has a third ground pad (343) adapted to connect with the cable. |
| US09257796B1 |
Electrical connector for high-speed transmission using twisted-pair cable
An electrical connector for a shielded, twisted-pair cable comprises a conductive isolator body, multiple conductive contacts, inner and outer insulators, and inner and outer ferrules. The isolator provides electrical shielding and isolation for the contacts and untwisted portions of the wires connected to the contacts. The inner and outer insulators prevent contact between the contacts and between the contacts and the isolator, an outer shell, or a connector insert. The inner ferrule maintains electrical contact between the isolator and the shielding sheath of the cable. The outer ferrule retains the inner ferrule in place and can establish continuity between the isolator and the outer shell or connector insert. |
| US09257795B2 |
Push-on type grounding bushing
A push-type grounding bushing has an electrically conductive body having a first end, a second end, a bore formed therethrough, and an intermediate shoulder stop to contact an end of a conduit. The bushing has with a locking device gripping tabs forming a helix so that the conduit can be pushed and held in the locking device and removed by rotating the conduit relative to the body. A throat insulator is placed into the second end of the body and has a flange to cover the second end. An electrically conducting lug is secured to the body and has a recess or bore for receipt of at least one electrical conductor to ground the bushing while a fastener mechanically and electrically secures the conductor to the lug. |
| US09257792B2 |
Connectors and systems having improved crosstalk performance
Embodiments of the present invention generally relate to the field of electronic communication, and more particularly, to techniques used to compensate for/reduce/or otherwise manipulate crosstalk in communication connectors, and apparatuses and methods which employ such techniques. In an embodiment, the present invention is a communication connector that includes a plurality of signal pairs including at least a first pair and a second pair, a first compensation stage between the first pair and the second pair, and an orthogonal compensation network between the first pair and the second pair. The orthogonal compensation network can be time delayed from the first compensation stage. |
| US09257791B2 |
Multistage capacitive crosstalk compensation arrangement
Methods and systems for providing crosstalk compensation in a jack are disclosed. According to one method, the crosstalk compensation is adapted to compensate for undesired crosstalk generated at a capacitive coupling located at a plug inserted within the jack. The method includes positioning a first capacitive coupling a first time delay away from the capacitive coupling of the plug, the first capacitive coupling having a greater magnitude and an opposite polarity as compared to the capacitive coupling of the plug. The method also includes positioning a second capacitive coupling at a second time delay from the first capacitive coupling, the second time delay corresponding to an average time delay that optimizes near end crosstalk. The second capacitive coupling has generally the same overall magnitude but an opposite polarity as compared to the first capacitive coupling, and includes two capacitive elements spaced at different time delays from the first capacitive coupling. |
| US09257790B2 |
Electrical connector having improved shielding means
An electrical connector includes a housing unit and a contact unit received therein. The housing unit includes a shielding member and an insulating member retained on the shielding member. The shielding member defines opposite upper end and lower end while the insulating member includes a first portion and a second portion seated on the upper and lower ends respectively and defines a cavity therebetween. The contact unit includes a plurality of contacts, a metal plate defining a plurality of through holes and an insulating body retaining the contacts and the metal plate. The metal plate divides the cavity into a first cavity and a second cavity, the contact runs through the through hole of the metal plate and comprises a first arm above the metal plate received in the first cavity and a second arm under the metal plate received in the second cavity. |
| US09257788B1 |
Connector retention and alignment assembly for use in computer and data storage mounting racks
A cable connector assembly useful for properly aligning/positioning and retaining (during connecting and disconnecting) a number of connectors for computing devices. The assembly uses left and right side walls with flexible and resilient connector engagement members that provide at least some amount of outward “give” or movement to facilitate assembly but are designed to spring back into place after insertion of the connectors. The engagement members of the left and right side walls may each take the form of a leaf spring that can be flexed a distance outward but then spring back to or towards a non-deformed state to mate with and apply an inward retention force against the adjacent connector. The assembly includes removable and rotatable middle walls or dividers that are placed on posts extending upward from the inner surface of the assembly's base and allowed to rotate about the posts during the assembly process. |
| US09257778B2 |
High speed electrical connector
Electrical connector assemblies are provided that include electrical connectors having electrical contacts that have receptacle mating ends are provided. The connector housings of the provided electrical connectors include alignment members that are capable of performing staged alignment of components of the electrical connector assemblies. The provided electrical connector assemblies and the electrical connectors provided therein are capable of operating at a data transfer rate of forty gigabits per second with worst case multi-active cross talk that does not exceed a range of about two percent to about four percent. |
| US09257777B2 |
Flash drive
A flash drive including a storage module and a rotating member is provided. The storage module has a carrier, a first connecting interface, and a second connecting interface. The carrier has a groove. The first and the second connecting interfaces are assembled to the carrier and disposed backward from each other at opposite sides of the carrier along a first axis. The rotating member has a driving portion connected to the groove. The rotating member is rotated on a rotation axis, such that the driving portion is slid in the groove, and the carrier is moved along the first axis. A traveling path of the first connecting interface along the first axis is different from a traveling path of the second connecting interface along the first axis. |
| US09257773B2 |
Connector
A female connector (F) includes a retainer (30) to be housed into a mounting hole (14) and selectively mounted, in a housing (10), at a partial locking position for allowing insertion of terminal fittings (50) and a full locking position for locking already inserted terminal fittings (50). A base (33) is at a rear end of the retainer (30) in a mounting direction into the housing (10) and is located outside a mounting hole (14) when the retainer (30) is at the partial locking position. Backlash eliminating portions (21, 22, 41, 42) are formed on the base (33) and in the housing (10) and are configured to restrict a relative displacement of the retainer (30) with respect to the housing (10) when the retainer (30) is at the partial locking position. |
| US09257769B2 |
Contact element and connector
A contact element capable of arranging beam portions at a narrower pitch and also facilitating insertion of a mating contact, and a connector have second and fourth contact portions which are displaced from each other in an orthogonal direction DR which is orthogonal to an arranging direction DP of first and second beam portions and a thickness direction DB of a linking portion. When a metal plate is blanked, the first and fourth contact portions are displaced from each other in a longitudinal direction L of the first and second beam portions, and the second and third contact portions are displaced from each other in the longitudinal direction L of the first and second beam portions. |
| US09257760B2 |
Stranded composite core compression connector assembly
A coupling member for receiving wire strands of a stranded composite core conductor includes a substantially cylindrical body having first and second ends. A first through hole extends from a first opening at the first end to a second opening at the second end of the body for receiving a wire strand of the stranded conductor. A first protrusion extends axially outwardly from the first end of the body. A first recess in the second end of the body is adapted to receive a protrusion of an adjacent coupling member. |
| US09257755B2 |
Apparatus for controlling electric field distribution by utilizing short trace structures
An apparatus for controlling electric field distribution is provided, where the apparatus includes at least one portion of a portable electronic device, the portable electronic device includes a plurality of wireless communication functions respectively corresponding to different communication standards, and the plurality of wireless communication functions includes a mobile phone function and at least one other wireless communication function. The apparatus includes: a main antenna, connected to a first side of a PCB of the portable electronic device, for performing the mobile phone function; and a plurality of short trace structures, positioned at the first side of the PCB and connected to the PCB, wherein at least one of the plurality of short trace structures is selectively utilized as at least one short trace or utilized as at least one secondary antenna corresponding to the at least one other wireless communication function. |
| US09257753B2 |
Array antenna
An array antenna includes radiating antenna elements arranged to form an antenna aperture, the radiating antenna elements including a first group and a second group of radiating antenna elements; a corporate feed network configured to feed the radiating antenna elements, wherein the corporate feed network includes a 4-port device including a sum port, a difference port, a first signal port and a second signal port, with the first signal port coupled via the corporate feed network to the first group of radiating elements and the second signal port coupled via the corporate feed network to the second group; a first phase shift element proximal to the antenna aperture to introduce a first predetermined phase shift to the first group of radiating antenna elements; and a second phase shift element proximal to the second signal port to introduce a second predetermined phase shift to the second group of radiating antenna elements. |
| US09257748B1 |
Broadband, low-profile antenna structure
The invention is directed to a broadband, low-profile antenna structure that in one embodiment includes a compound radiator and a ground plane. The compound radiator is comprised of a dipole radiator portion and a Vivaldi radiator portion that is electrically connected to the dipole radiator portion. In operation, the dipole radiator portion operates in the lower end of the bandwidth and the Vivaldi radiator portion operates in the upper end of the bandwidth. |
| US09257747B2 |
Vivaldi-monopole antenna
A Vivaldi-Monopole antenna is a small form ultra-wideband antenna configured for low frequency operation in modern wireless devices. The Vivaldi-Monopole antenna comprises a tapered-slot element and a monopole element, wherein current modes of each element are combined to yield a functional and small form ultra-wideband antenna configured for low frequency resonances. |
| US09257737B2 |
Antenna switching circuit and electronic device and antenna switching method thereof
An antenna switching circuit and an electronic device and an antenna switching method thereof are provided. The antenna switching circuit is disposed in the electronic device including an internal antenna and a RF module, and includes an external antenna connector and a controller. The external antenna connector has an independent ground terminal for receiving an independent ground signal, and the external antenna connector is electrically connected to an external antenna. The controller has a first RF terminal, a second RF terminal and a control terminal, the first RF terminal is electrically connected to the RF module, the second RF terminal is electrically connected to the internal antenna, and the control terminal detects the independent ground signal. When the controller detects no change in the independent ground signal, the controller electrically connects the RF module to the internal antenna; otherwise, the controller electrically connects the RF module to the external antenna. |
| US09257734B2 |
Compact amplitude and phase trimmer
In some examples, a device includes a waveguide transition section comprising a first mode suppressor, an attenuation section coupled to the first waveguide transition section via a first adjustable rotation joint, wherein the attenuation section is operable to attenuate the electromagnetic signal, and a first quarter-wave plate section coupled to the attenuation section, wherein the first quarter-wave plate section is operable to introduce a first differential phase shift between a first mode of the electromagnetic signal and a second mode of the electromagnetic signal. The device also includes a second quarter-wave plate section coupled to the first quarter-wave plate section via a second adjustable rotation joint, wherein the second quarter-wave plate section is operable to introduce a second differential phase shift between the second mode of the electromagnetic signal and the first mode of the electromagnetic signal. |
| US09257728B2 |
Battery pack
A battery pack has battery cells and bus bars. Each of the battery cells is covered with an exterior case. All the battery cells are electrically connected in series through the bus bars. The battery cells are divided into a first stacked group and a second stacked group arranged adjacent to each other in a lateral direction of the battery pack. The battery cells in each stacked group are stacked in a thickness direction of the battery pack. The stacked groups have a different number of the battery cells in order to make a stair structure. An electrode terminal of one end terminal of the battery cells connected in series is arranged adjacent to the stair structure. A control board is arranged on a lower step part of the stair structure. Devices formed on the control board detect a state of each battery cell. |
| US09257723B2 |
Aryl diazonium salt and use in an electrolytic solution of an electrochemical generator
The invention relates to a diazonium aryl salt devoid of hydroxyl functions of the following general formula (1): X−+N≡N-A-R1—(OR2)n—O—R4-A′-N≡N+X− (1) in which: n is in a range of from 1 to 10, preferably from 1 to 4, X− represents a counter-ion of the diazonium cation selected from the group consisting of halogenides, BF4—, NO3—, HSO4—, PF6—, CH3COO—, N(SO2CF3)2—, CF3SO3—, CH3SO3—, CF3COO—, (CH3O)(H)PO2—, and N(CN)2—; R1, R2 and R4 are identical or different and are independently selected from the group consisting of —CH2—, a cyclic alkyl group, an acyclic alkyl group, a linear alkyl group, and a branched alkyl group; and A and A′ are identical or different and independently represent a mono or polycyclic, aromatic hydrocarbonated group chosen from the group formed by phenyl, aryl groups, condensed polyaromatic groups, which may be substituted. |
| US09257721B2 |
Method for manufacturing all solid-state lithium-ion rechargeable battery, and method for testing all solid-state lithium-ion rechargeable battery
A method for manufacturing an all solid-state lithium-ion rechargeable battery includes forming a first active material layer on a base, forming a solid electrolyte layer connected to the first active material layer, forming a second active material layer connected to the solid electrolyte layer, and repairing a short-circuit defect produced between the first active material layer and the second active material layer by supplying a repair current between the first active material layer and the second active material layer. |
| US09257720B2 |
Nonaqueous electrolyte solution and nonaqueous electrolyte battery using same
The present invention provides a non-aqueous electrolytic solution including a methylenebissulfonate derivative and improving initial irreversible capacity and other characteristics of a battery such as a cycle characteristics, electric capacity, and storage characteristics; a method for producing thereof; and a battery using the electrolytic solution. The non-aqueous electrolytic solution includes: (1) a non-aqueous solvent comprising at least one selected from a cyclic carbonate ester, a straight chained carbonate ester and/or a cyclic carboxylic acid ester, (2) a lithium salt which may be dissolved in the non-aqueous solvent, as an electrolyte salt, and (3) a methylenebissulfonate derivative of formula [1]: The method includes steps of dissolving a lithium salt in a non-aqueous solvent, and then dissolving the methylenebissulfonate derivative. The non-aqueous electrolytic solution battery includes (i) the non-aqueous electrolytic solution, (ii) a negative electrode, (iii) a positive electrode, and (iv) a separator. |
| US09257717B2 |
Nonaqueous electrolyte secondary battery
In a wound electrode group, a positive electrode includes positive electrode active material layers formed on both surfaces of a band-like positive electrode current collector, and a negative electrode includes negative electrode active material layers on both surfaces of a band-like negative electrode current collector. Charge capacity of the negative electrode falls within a range of 83-99% of theoretical capacity of the negative electrode in a full charge state of a nonaqueous electrolyte secondary battery. An active material mass M1 per unit area of a negative electrode active material layer formed on an outer circumference of the negative electrode current collector, and an active material mass M2 per unit area of a negative electrode active material layer formed on an inner circumference satisfy a relational expression of M1/M2<(R1+t/2)/(R1−t/2), where the electrode group has an innermost diameter of R1, and the negative electrode has a thickness of t. |
| US09257716B2 |
Battery
A battery includes a roll-up unit provided by winding a sheet unit around an axis, the sheet unit including an electrode sheet having an active material and a separator, the roll-up unit having an exposed portion on which the active material is not placed at an end of the electrode sheet in a direction of the axis; an outer case housing the roll-up unit and having an electrode terminal; an intermediate terminal inside the roll-up unit and having a pair of arm portions resistance-welded to the exposed portion, a first connecting portion connecting the arm portions, and a hole portion formed in the first connecting portion and located between welding points formed in the arm portions; and a collector terminal outside the roll-up unit and resistance-welded to a position opposite to the arm portion in the exposed portion to provide electrical continuity between the roll-up unit and the electrode terminal. |
| US09257715B2 |
Cylindrical secondary battery
The present invention provides a cylindrical secondary electrode including a first electrode plate, a second electrode plate, a separator interposed between the first electrode plate and the second electrode plate, and a case having a space for receiving the electrode assembly, wherein the cylindrical secondary electrode may include a core element having a space at the center thereof and having a tubular shape with a circular cross section, which is inserted into a space at the center of an electrode assembly and has at least one slit including a bent portion. |
| US09257713B2 |
Solid oxide fuel cell system equipped with carbon monoxide generator using ultraclean coal or graphite
A solid oxide fuel cell system has a carbon monoxide generator using ash-free coal or graphite, which includes a carbon supply unit, a carbon dioxide supply unit, a carbon monoxide generating unit, and a fuel cell unit. The carbon monoxide generating unit supplies CO to the anode of the fuel cell unit, and CO2 discharged from the fuel cell unit is recycled to the carbon dioxide supply unit. Because ash-free coal or graphite is used, a separate reformer does not need to be used, and thus energy can be produced with high efficiency even at low costs. Because CO2 discharged from the solid oxide fuel cell, which uses carbon monoxide as a fuel, after a fuel cell reaction, is reused as reactant gas, carbon dioxide is not emitted into the atmosphere. Gasification can be smoothly achieved by the carbon monoxide generating unit including heating powder or a heating reaction chamber. |
| US09257710B2 |
Flow battery start-up and recovery management
A start-up plating process for a flow cell battery is disclosed. Upon start-up of the flow-cell stack, catalysts may have deplated from the electrodes. The catalyst is replated to the electrode by application of currents to the stack prior to circulating electrolyte fluids. |
| US09257708B2 |
Fuel cartridge with connecting valve
A shut-off valve or connecting valve capable of connecting a fuel supply to a fuel cell is disclosed. The valve comprises a first valve component and a second valve component. Each valve component has an outer housing and a biased slidable member disposed inside the housing forming an internal seal. During the connection process, the two valve components establish an inter-component seal. Afterward, in one suitable embodiment the slidable member moves inward and opens the internal seal in the valve component to establish a flow path. In another embodiment, the slidable member moves inward and exposes a first filler and the first filler abuts a second filler in the other valve component to establish a flow path. In other embodiments, at least one valve component is sized and dimensioned to limit access to the internal seal. |
| US09257703B2 |
Electrode binder composition for nonaqueous electrolyte battery, electrode for nonaqueous electrolyte battery, and nonaqueous electrolyte battery
Provided is a binder composition for electrodes that has high stability in the form of a liquid composition dissolved or dispersed in a solvent and can improve cycle property of a non-aqueous electrolyte battery. The binder composition used is a binder composition including a polymer A containing 80% by weight or more and 99.9% by weight or less of a repeating unit derived from a monomer including a nitrile group and 0.1% by weight or more and 20% by weight or less of a repeating unit derived from an ethylenically unsaturated compound, wherein a weight-average molecular weight of the polymer A is 500,000 to 2,000,000, and a molecular weight distribution (Mw/Mn) of the polymer A is 13 or smaller. |
| US09257702B2 |
Plate-like particle of cathode active material for lithium secondary battery, cathode of the lithium secondary battery and lithium secondary battery
To provide a lithium secondary battery which has high capacity while maintaining excellent charge-discharge characteristic, and to provide a cathode of the lithium secondary battery and a plate-like particle for cathode active material to be contained in the cathode. The plate-like particle of cathode active material for a lithium secondary battery of the present invention has a layered rock salt structure, a thickness of 5 μm or more and less than 30 μm, 2 or less of [003]/[104] which is a ratio of intensity of X-ray diffraction by the (003) plane to intensity of X-ray diffraction by the (104) plane, a voidage of 3% or more and less than 30%, and an open pore ratio of 70% or higher. |
| US09257700B2 |
Electrode, nonaqueous electrolyte battery and battery pack
According to one embodiment, an electrode includes a current collector and an active material-including layer. The active material-including layer includes a first layer and a second layer. The first layer is provided on a surface of the current collector and includes lithium titanium oxide having a spinel structure. The second layer is provided on the first layer and includes a monoclinic β-type titanium composite oxide. |
| US09257697B2 |
Positive electrode material, manufacturing method thereof, positive electrode for non-aqueous rechargeable battery, and non-aqueous rechargeable battery
A positive electrode material that can form a positive electrode mixture containing composition with reduced changes over time and high productivity, a manufacturing method thereof, a non-aqueous rechargeable battery less likely to swell and having a high storage characteristic during storage at high temperatures, and a positive electrode that can form the battery are provided. The object is solved by providing a positive electrode material having a coating layer of an organic silane compound on a surface of a positive electrode active material made of a lithium nickel composite oxide represented by the general compositional formula (1): Li1+xMO2 where −0.5≦x≦0.5, M represents a group of at least two elements including at least one of Mn and Co and Ni, and 20≦a<100 and 50≦a+b+c≦100 when the ratios (mol %) of Ni, Mn, and Co in the elements forming M are a, b, and c, respectively. |
| US09257693B2 |
Nonaqueous electrolyte secondary battery and battery module
A nonaqueous electrolyte secondary battery, having an internal resistance of 10 mΩ or less as an alternating-current impedance value of 1 kHz, comprises a metal outer container, a nonaqueous electrolyte contained in the container, a positive electrode contained in the container, a negative electrode contained in the container, a separator interposed between the negative electrode and the positive electrode, a negative electrode lead having one end connected to the negative electrode, and a negative electrode terminal attached to the outer container so as to be connected electrically to the other end of the negative electrode lead, at least the surface of the negative electrode terminal which is connected to the negative electrode lead being formed of aluminum alloy with an aluminum purity of less than 99 wt. % containing at least one metal selected from the group consisting of Mg, Cr, Mn, Cu, Si, Fe and Ni. |
| US09257691B2 |
Battery pack
A battery pack includes a plurality of battery units that are side by side along a first direction, a connection member that connects the battery units in series, in parallel, or in series and parallel, the connection member being adjacent to one surface of each battery unit of the plurality of battery units, an upper cap on and accommodating the connection member, upper portions of all of the battery units being inserted into the upper cap, a lower cap that is spaced apart from the upper cap by a predetermined gap, lower portions of all of the battery units being inserted into the lower cap, and a label that at least partially surrounds the battery units exposed between the upper cap and the lower cap. The upper cap and the lower cap fix an arrangement of the battery units. |
| US09257690B2 |
Energy vehicle and battery locking device thereof
A battery locking device for a new energy vehicle including: a battery compartment fit for a battery, the battery compartment being provided with a battery inlet; and a battery clamping device provided on the battery compartment and controlled by a linkage mechanism. Since the battery clamping device is controlled by the linkage mechanism, during the mounting or removing of the battery, the battery can be integrally clamped or released by merely operating an operating end of the linkage mechanism. Compared with the prior art in which the battery is fixed through bolts, the battery can be integrally clamped or released by the battery locking device through a single operation, which greatly simplifies the disassembling or assembling process of the battery and reduces the time required for replacing the battery. A new energy vehicle provided with the above battery locking device has the same advantages. |
| US09257683B2 |
Power battery
A power battery, the power battery includes an inner case (4), an outer case (1), a battery body (2) and electrodes (3), the battery body (2) includes electrode plates, the external surface of the outer case is provided with an external heat abstractor and the internal surface of the inner case is provided with an internal heat abstractor, a cylindrical holding cavity (5) with an annular cross section is formed between the outer case (1) and the inner case (4) and the electrode plates are rolled in the holding cavity (5), the electrodes (3) are arranged in an inner cavity of the inner case (4) and the inner case also has at least an airway going through the inner cavity. |
| US09257676B2 |
Light-emitting device
A first electrode having light transmissivity is formed on a first surface of a first light transmissive substrate and. An organic functional layer includes a light-emitting layer and is located on an opposite side to the first light transmissive substrate with the first electrode interposed therebetween. A second electrode is located on an opposite side to the first electrode with the organic functional layer interposed therebetween. A second surface which is a surface of the first light transmissive substrate on an opposite side to the above-mentioned first surface is fixed to the second light transmissive substrate, which has a bending rigidity higher than that of the first light transmissive substrate. First irregularities are formed in the second surface of the first light transmissive substrate, and second irregularities are formed in a surface of the second light transmissive substrate which faces the first light transmissive substrate. |
| US09257675B2 |
Substrate for an organic electronic device and an organic electronic device comprising the same
A substrate including a base substrate; a scattering layer which is formed on the base substrate, includes a binder and scattering particles for scattering light, and has an uneven structure formed on a surface thereof opposite the base substrate; and a planarizing layer which is formed on the scattering layer and has a flat surface formed thereon, is provided. Here, the refractive index Na of the scattering particles and the refractive index Nb of the planarizing layer satisfy the expression |Na−Nb|≧0.3, an organic electronic device including the substrate, and a method of manufacturing the same are provided. Light-extraction efficiency can be improved and the manufacturing process can be simplified without degrading device performance. |
| US09257673B2 |
Organic light emitting diode display
Disclosed is an organic light emitting diode (OLED) display comprising a substrate; an organic light emitting element disposed on the substrate; an encapsulation substrate disposed on the organic light emitting element; and an adhesive layer formed on the substrate, covering the organic light emitting element, and bonding the substrate on which the organic light emitting element is formed with the encapsulation substrate. |
| US09257671B2 |
Resin composition for sealing organic electroluminescent device; method of producing the same; and adhesive film, gas-barrier film, organic electroluminescent device and organic electroluminescent panel using the resin composition
A resin composition for sealing an organic electroluminescent device, containing: a drying agent, and a curable component, wherein a surface roughness Ra of the shear failure surface after curing the resin composition is 0.5 μm or more; a production method thereof; an adhesive film and a gas-barrier formed of the resin composition; an organic electroluminescent device and an organic electroluminescent panel using the same. |
| US09257668B2 |
Organic light-emitting diode (OLED) display and method for manufacturing the same
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a first substrate including a display area and a second substrate facing the first substrate. The OLED display also includes a sealing member surrounding the display area and attaching the first and second substrates to each other and a gold layer formed on the sealing member. |
| US09257662B2 |
Quantum dot light-emitting device
There is provided a quantum dot light-emitting device including: a light-emitting layer containing a quantum dot luminescent material; and a metal-based particle assembly layer being a layer consisting of a particle assembly including 30 or more metal-based particles separated from each other and disposed in two-dimensions, said metal-based particles having an average particle diameter in a range of 200 to 1600 nm, an average height in a range of 55 to 500 nm, and an aspect ratio, as defined by a ratio of said average particle diameter to said average height, in a range of 1 to 8, wherein said metal-based particles that compose said metal-based particle assembly layer are disposed such that an average distance between adjacent metal-based particles may be in a range of 1 to 150 nm. The quantum dot light-emitting device provides enhanced emission via the metal-based particle assembly layer and thus presents high luminous efficiency. |
| US09257657B2 |
Light emitting device and electronic appliance using the same
The light emitting element includes a first electrode and a second electrode, between which a light emitting layer, a hole transporting layer provide in contact with the light emitting layer, an electron transporting layer provided in contact with the light emitting layer, and a mixed layer provided between the electron transporting layer and the second electrode. The mixed layer includes an electron transporting substance and a substance showing an electron donating property with respect to the electron transporting substance. The light emitting layer includes an organometallic complex represented in General Formula (1) and a host. R1 and R2 each represent an electron-withdrawing substituent group. R3 and R4 each represent any of hydrogen or an alkyl group having 1 to 4 carbon atoms. L represents any of a monoanionic ligand having a beta-diketone structure, a monoanionic bidentate chelating ligand having a carboxyl group, or a monoanionic bidentate chelating ligand having a phenolic hydroxyl group. |
| US09257648B2 |
Memory cells, methods of forming memory cells, and methods of programming memory cells
Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another. |
| US09257643B2 |
Phase change memory cell with improved phase change material
A phase change memory cell. The phase change memory cell includes a substrate and a phase change material. The phase change material is deposited on the substrate for performing a phase change function in the phase change memory cell. The phase change material is an alloy having a mass density change of less than three percent during a transition between an amorphous phase and a crystalline phase. |
| US09257636B2 |
Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method
Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask. |
| US09257631B2 |
Piezoelectric vibration element, piezoelectric vibration device, and portable terminal
A piezoelectric vibration element capable of reducing occurrence of unnecessary vibration, and a piezoelectric vibration device and a portable terminal using the same are disclosed. The piezoelectric vibration element includes a plurality of electrode layers and a plurality of piezoelectric layers being stacked along a first direction, the piezoelectric vibration element having two surfaces that face each other to be at intervals in the first direction, and vibrating in bending mode in the first direction with an amplitude varying along a second direction perpendicular to the first direction according to input of an electric signal, one of the two surfaces having such a shape that a central portion thereof in a third direction perpendicular to the first direction and the second direction protrudes as compared with opposite end portions thereof in the third direction. |
| US09257630B2 |
Multilayer piezoelectric device with polycrystalline and single crystal members and intermediate member provided between the polycrystalline member and the single crystal member
The present invention relates to a piezoelectric device. A piezoelectric device in accordance with an embodiment of the present invention includes a piezoelectric member and a connection member which are coupled to each other, wherein the piezoelectric member includes a polycrystalline member made of a polycrystalline piezoelectric material, a single crystal member made of a single crystal piezoelectric material and coupled to the connection member, and a textured member provided between the polycrystalline member and the single crystal member and having intermediate properties of the polycrystalline piezoelectric material and the single crystal piezoelectric material. |
| US09257629B2 |
Ultrasonic array transducer, associated circuit and methods of making the same
In some embodiments, circuits for ultrasonic transducer element arrays are provided. In some embodiments, a circuit described herein comprises a first layer for receiving a transducer element array, a ground layer comprising at least one ground disposed over the first layer and a plurality of first vias corresponding to transducer elements of the array, the first vias extending through the first layer to the at least one ground and comprising first ends for receiving ground electrodes of the transducer elements and second ends electrically connected to the ground. |
| US09257628B2 |
Process for producing nanoparticles and their use in the production of high-temperature superconductors
Known processes for the production of nanoparticles of compounds of the transition metals Zr, Ti, Ta, rare earths (RE), Mn, and Fe via microemulsions lead to products that contain impurities from the reactants, particularly water, which make the further use of said nanoparticles difficult, for instance in high-temperature super conductors (HTSC). It is proposed that the nanoparticles be produced via anhydrous microemulsions having an outer phase composed of a nonpolar solvent and inner phase composed of a polar anhydrous solvent. The nanoparticles thus obtained exhibit good monodispersity and can be used in the production of REBa2Cu3O7 super conductors by incorporation into the precursor coating solution. |
| US09257627B2 |
Method and structure for thermoelectric unicouple assembly
Method for assembling thermoelectric unicouples is provided and applied with silicon-based nanostructure thermoelectric legs. The method includes preparing and disposing both n-type and p-type thermoelectric material blocks in alternative columns on a first shunt material. The method includes a sequence of cutting processes to resize the thermoelectric material blocks to form multiple singulated unicouples each having an n-type thermoelectric leg and a p-type thermoelectric leg bonded to a section of the first shunt material. Additionally, the method includes re-disposing these singulated unicouples in a serial daisy chain configuration with a predetermined pitch distance and bonding a second shunt material on top. The method further includes performing additional cutting processes to form one or more daisy chains of thermoelectric unicouples. The first shunt material is coupled to a cold-side heat sink and the second shunt material is coupled to a hot-side heat sink. |
| US09257614B2 |
Warm white LED with stacked wafers and fabrication method thereof
A warm-white-light LED structure combines a red light wafer and a blue light wafer via a bonding layer. A reflecting layer is arranged over upper and lower surfaces of the bonding layer respectively; the lower surface of the red light wafer takes up one-third or less of the upper surface of the blue light wafer, which effectively reduces packaging structure volume and time of bondings so as to optimize process flow and save fabrication cost. |
| US09257608B2 |
Nitride semiconductor light emitting device
A light emitting device includes a first layer of a first conductivity type, a second layer of a second conductivity type, a light emitting layer between the first and second layers, a first electrode disposed on a surface of the first layer, and a second electrode disposed on a surface of the second layer and electrically insulated from the first layer. The first layer has first and second regions, each of which contacts the first electrode. A dopant concentration in the first region is less than a dopant concentration in the second region. |
| US09257606B2 |
Direct bandgap substrates and methods of making and using
An indirect bandgap thin film semiconductor circuit can be combined with a compound semiconductor LED such as to provide an active matrix LED array that can have high luminous capabilities such as for a light projector application. In another example, a highly efficient optical detector is achievable through the combination of indirect and direct bandgap semiconductors. Applications can include display technologies, light detection, MEMS, chemical sensors, or piezoelectric systems. An LED array can provide structured illumination, such as for a light and pattern source for projection displays, such as without requiring spatial light modulation (SLM). An example can combine light from separate monolithic light projector chips, such as providing different component colors. An example can provide full color from a single monolithic light projector chip, such as including selectively deposited phosphors, such as to contribute individual component colors to an overall color of a pixel. |
| US09257600B2 |
White light quantum dot complex particle and process for preparing same
A white light quantum dot complex particle, comprising a seed particle (1) in the core, and a first shell layer (2), a second shell layer (3) and a third shell layer (4) wrapped around the seed particle (1) in order; in the first shell layer (2), the second shell layer (3) and the third shell layer (4) are one of a red light quantum dot layer, a green light quantum dot layer and a blue light quantum dot layer respectively, and are different from one another. Also disclosed is the process for preparing the white light quantum dot complex particle. |
| US09257596B2 |
Light-emitting diode chip
A light-emitting diode chip comprising:—a semiconductor body (1) having a plurality of active regions (2), wherein—at least one of the active regions (2) has at least two subregions (21 . . . 28),—the active region (2) has at least one barrier region (3) arranged between two adjacent subregions (21 . . . 28) of said at least two subregions (21 . . . 28),—the at least two subregions (21 . . . 28) emit light of mutually different colour during operation of the light-emitting diode chip,—in at least one of the subregions (21 . . . 28) the emission of light is generated electrically, and—the barrier region (3) is configured to hinder a thermally activated redistribution of charge carriers between the two adjacent subregions (21 . . . 28), is specified. |
| US09257593B2 |
Method for producing photoelectric conversion element
There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer (16) and an n-type amorphous silicon layer (14) are formed over a light-receiving surface of an n-type monocrystalline silicon substrate (18); a second step in which an i-type amorphous silicon layer (22a) and an n-type amorphous silicon layer (23a) are formed over a back surface of the n-type monocrystalline silicon substrate (18); and a third step in which, after the first step and the second step are completed, protection layers are formed over the n-type amorphous silicon layer (14) and the n-type amorphous silicon layer (23a). |
| US09257592B2 |
Translucent solar cell and manufacturing method thereof
The present invention provides a translucent solar cell and a manufacturing method thereof. The translucent solar cell comprises, in stacking order, a substrate, a first electrode layer, a photoconductive layer and a second electrode layer. The translucent solar cell is characterized in that there are formed a plurality of first light-transmissive apertures on the second electrode layer and the plurality of first light-transmissive apertures are further extended in a depth direction to the photoconductive layer to form a plurality of second light-transmissive apertures corresponding to the first light-transmissive apertures. A projected area of each of the second light-transmissive apertures is equal to or smaller than that of a corresponding first light-transmissive aperture. |
| US09257590B2 |
Photoelectric element, display unit and method for fabricating the same
A photoelectric element including a transparent bottom electrode, a photosensitive layer, a first electrode, a second electrode and a transparent top electrode is provided. The photosensitive layer is located above the transparent bottom electrode. The first electrode and the second electrode are disposed on the photosensitive layer. The transparent top electrode is located above the photosensitive layer. |
| US09257586B2 |
Monolithic multiple solar cells
A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell. For this purpose, the semiconductor mirror has a high degree of reflection in at least one part of a spectral absorption area of the partial cell which is arranged above the semiconductor mirror and a high degree of transmission within the spectral absorption range of the partial cell arranged below the semiconductor mirror. |
| US09257580B2 |
Textured transparent plate and method of manufacturing such a plate
A monolithic transparent plate including, on at least one of its faces, at least one region textured by a plurality of geometric features in relief relative to a general plane of the face, each feature having a cross section, parallel to the general plane, which diminishes with distance from the face, from a base to a peak of the feature. The area of the zones of the textured region for which the inclination angle relative to the general plane is less than 30° C. represents less than 35% of the total area of the textured region. |
| US09257579B2 |
Electronic devices and method of fabricating the same
Provided is a method of fabricating an electronic device. The method according to the present inventive concept may include forming a lower electrode having a flat portion and protrusions on a substrate, forming an intermediate layer on the lower electrode, and forming an upper electrode on the intermediate layer. The forming of the lower electrode may include forming a conductive film by depositing a first metal on the substrate, and depositing a second metal on the conductive film to prepare an alloy of the first metal and the second metal. |
| US09257574B2 |
Diode and method of manufacturing diode
A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode. |
| US09257573B2 |
Semiconductor device and method of fabricating the same
A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer. |
| US09257565B2 |
Display panel and manufacturing method thereof
A display panel manufacturing method includes forming a gate electrode on a substrate and a gate insulator, a semiconductor layer, and an etch stop layer covering the gate electrode. A photoresist layer covering on the etch stop layer is pattern from two opposite side of the substrate by two photolithography processes to form a photoresist pattern. The etch stop layer is dry etched to form an etch stop pattern via the photoresist pattern. The photoresist pattern is formed again by two photolithography processes. The semiconductor layer is wet etched to form a semiconductor pattern via the photoresist pattern. A source electrode and a drain electrode is formed corresponding to two opposite sides of the gate electrode to orderly cover the etch pattern, the semiconductor pattern, and the gate insulator. |
| US09257564B2 |
Thin film transistor and method of fabricating same
A thin film transistor (TFT) includes a gate, a drain, a source, an insulating layer, a metal oxide layer, and an etch stopper layer. The metal oxide layer includes a source area, a drain area, and a channel area. The source is electrically coupled to the source area and the drain is electrically coupled to the drain area. Oxygen ions are implanted into the channel area via a surface treatment process to make an oxygen concentration of the channel area be greater than an oxygen concentration of each of the source area and the drain area. |
| US09257562B2 |
Semiconductor device
It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate, and is heated. A thermal expansion coefficient of the substrate is 6×10−7/° C. to 38×10−7/° C., preferably 6×10−7/° C. to 31.8×10−7/° C. Next, the layer including the semiconductor film is irradiated with a laser beam to crystallize the semiconductor film so as to form a crystalline semiconductor film. Total stress of the layer including the semiconductor film is −500 N/m to +50 N/m, preferably −150 N/m to 0 N/m after the heating step. |
| US09257559B2 |
Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow. |
| US09257558B2 |
FinFET device with gate oxide layer
The present disclosure provides a semiconductor structure. In accordance with some embodiments, the semiconductor structure includes a substrate, one or more fins each including a first semiconductor layer formed over the substrate, an oxide layer formed wrapping over an upper portion of each of the one or more fins, and a gate stack including a high-K (HK) dielectric layer and a metal gate (MG) electrode formed wrapping over the oxide layer. The first semiconductor layer may include silicon germanium (SiGex), and the oxide layer may include silicon germanium oxide (SiGexOy). |
| US09257557B2 |
Semiconductor structure with self-aligned wells and multiple channel materials
Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation. |
| US09257555B1 |
Semiconductor structure
A semiconductor structure is provided. The semiconductor structure comprises a doped substrate, a gate structure, a source, a drain and a field doped region. The source and the drain are in the doped substrate on opposing sides of the gate structure respectively. The field doped region has a conductivity type opposite to a conductivity type of the source and the drain. The field doped region is extended from the source to be beyond a first gate sidewall of the gate structure but not reach a second gate sidewall of the gate structure opposing to the first gate sidewall. |
| US09257554B2 |
Split gate embedded memory technology and method of manufacturing thereof
Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure. |
| US09257552B2 |
Semiconductor device and method of manufacturing same
In one embodiment, a method of manufacturing a semiconductor device includes forming, on a semiconductor substrate, a sacrificial semiconductor pillar having a pillar-like shape extending in a first direction perpendicular to a main surface of the semiconductor substrate, and being formed of a first semiconductor material. The method further includes forming, around the sacrificial semiconductor pillar, a channel semiconductor layer having a tube-like shape extending in the first direction, and being formed of a second semiconductor material different from the first semiconductor material. The method further includes removing the sacrificial semiconductor pillar after the channel semiconductor layer is formed. The channel semiconductor layer is formed on electrode layers via an insulator, the electrode layers being formed on the semiconductor substrate. |
| US09257548B2 |
Nitride semiconductor element and nitride semiconductor package
A nitride semiconductor element includes a Si substrate; a buffer layer including (a) an AlN layer formed on a primary surface of the Si substrate; and (b) an AlGaN deposit layer formed by laminating multiple AlGaN layers on the AlN layer and having a total thickness ranging from 100 nm to 500 nm; a GaN electron transfer layer formed on the AlGaN deposit layer and having a thickness ranging from 500 nm to 2000 nm provided that the GaN electron transfer layer is thicker than the AlGaN deposit layer; and an AlGaN electron supply layer formed on the GaN electron transfer layer, wherein the AlGaN deposit layer includes an AlGaN layer that is provided closer to the AlN layer and has an Al component that ranges from about 40% to about 60%, and a reference AlGaN layer that has an Al component (%) that is lower than that of the AlGaN layer. |
| US09257545B2 |
Stacked nanowire device with variable number of nanowire channels
A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack. |
| US09257541B2 |
High-breakdown-voltage power semiconductor device having a diode
A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p+-type diffusion region, a p−-type region, and an anode electrode. The p−-type region is formed as a region of relatively high electrical resistance sandwiched between the p+-type diffusion regions. |
| US09257535B2 |
Gate-all-around metal-oxide-semiconductor transistors with gate oxides
A method and structure for a semiconductor transistor, including various embodiments. In embodiments, a transistor channel can be formed between a semiconductor source and a semiconductor drain, wherein a transistor gate oxide completely surrounds the transistor channel and a transistor gate metal that completely surrounds the transistor gate oxide. Related fabrication processes are presented for similar device embodiments based on a Group III-V semiconductor material and silicon-on-insulator materials. |
| US09257531B2 |
Self-aligned contact structure for replacement metal gate
A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material. |
| US09257527B2 |
Nanowire transistor structures with merged source/drain regions using auxiliary pillars
A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures. |
| US09257525B2 |
Systems and methods for forming isolated devices in a handle wafer
A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer. |
| US09257524B2 |
Layered film including heteroepitaxial PN junction oxide thin film
Semiconductors of different types are formed by a crystal growth technique and joined at the interface at which rapid atomic-layer-level compositional changes occur while maintaining high crystallinity of the semiconductor layers so as to form a heterogeneous PN junction. A layered film that includes a PN junction oxide thin film is formed on a single crystal substrate. The PN junction oxide thin film is constituted by an N-type semiconductor oxide thin film and a P-type semiconductor oxide thin film that are epitaxially grown to have c-axis orientation represented by (00k). |
| US09257523B2 |
Avalanche diode having an enhanced defect concentration level and method of making the same
The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated. |
| US09257507B2 |
Semiconductor device
This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes. |
| US09257506B2 |
CMOS devices having dual high-mobility channels
A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (MOS) device. The step of forming the first MOS device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric. The step of forming the second MOS device includes forming a second silicon germanium layer over the second region of the semiconductor substrate; forming a second gate dielectric layer over the second silicon germanium layer with no substantially pure silicon layer therebetween; and patterning the second gate dielectric layer to form a second gate dielectric. |
| US09257504B2 |
Isolation structures for semiconductor devices
Isolation structures for isolating semiconductor devices from a substrate include floor isolation regions buried within the substrate and one or more trenches extending from a surface of the substrate to the buried floor isolation region. |
| US09257499B2 |
Connection structure for an integrated circuit with capacitive function
An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced. |
| US09257498B1 |
Process to improve performance for metal-insulator-metal (MIM) capacitors
Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions. |
| US09257494B2 |
Organic light-emitting display apparatus
An organic light-emitting display apparatus includes a thin film transistor including an active layer, gate, source and drain electrodes, a first insulating layer disposed between the active layer and the gate electrode, and a second insulating layer disposed between the gate electrode and the source and drain electrodes; a pad electrode including a first pad layer disposed on the same layer as the source and drain electrodes and a second pad layer disposed on the first pad layer; a third insulating layer covering the source electrode and the drain electrode and an end portion of the pad electrode; a pixel electrode including a semi-transmissive metal layer and disposed in an opening formed in the third insulating layer; and a fourth insulating layer having an opening formed in a location corresponding to an opening formed in the third insulating layer and covering the end portion of the pixel electrode. |
| US09257491B2 |
Electroluminescence display device
There is provided an EL display device of a color filter system which obtains sufficient brightness and contrast while making it difficult to generate a color mixture even if pixels become fine. An EL display device 100 according to the present invention includes a first substrate 1, a circuit layer 2 formed on the first substrate 1, a color selection reflection layer 11 formed in an upper layer of the circuit layer 2, lower electrodes 5 formed in an upper layer of the color selection reflection layer 11, a white light emission EL layer 7 formed in an upper layer of the lower electrodes 5, an upper electrode 8 formed in an upper layer of the EL layer 7, and a sealing layer 9 formed in an upper layer of the upper electrode 8. |
| US09257490B2 |
Full-color active matrix organic light emitting display with hybrid
A full-color AM OLED includes a transparent substrate, a color filter positioned on an upper surface of the substrate, and a metal oxide thin film transistor backpanel positioned in overlying relationship on the color filter and defining an array of pixels. An array of OLEDs is formed on the backpanel and positioned to emit light downwardly through the backpanel, the color filter, and the substrate in a full-color display. Light emitted by each OLED includes a first emission band with wavelengths extending across the range of two of the primary colors and a second emission band with wavelengths extending across the range of the remaining primary color. The color filter includes for each pixel, two zones separating the first emission band into two separate primary colors and a third zone passing the second emission band. |
| US09257487B2 |
Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same
A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates. |
| US09257483B2 |
Magnetic memory, method of manufacturing the same, and method of driving the same
There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other. |
| US09257482B2 |
Display device using semiconductor light emitting device
Discussed is a display device using a semiconductor light emitting device. In a display device including a plurality of semiconductor light emitting devices, each of the plurality of semiconductor light emitting devices includes a first conductive semiconductor layer, a second conductive semiconductor layer overlapped with the first conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, a first electrode deposited on the first conductive semiconductor layer, and a second electrode deposited on the second conductive semiconductor layer, wherein the first electrode is extended toward an adjoining semiconductor light emitting device to be electrically connected to the adjoining semiconductor light emitting device. |
| US09257480B2 |
Method of manufacturing photodiode detectors
A radiation detector assembly including an organic photodetector that generate charge in response to an incident radiation, a thin film transistor array including a plurality of pixels. The plurality of pixels may produce electric signals corresponding to the charge generated by the organic photodetector. The radiation detector assembly also includes a spacer disposed on the thin film transistor array. The spacer surrounds one or more pixels and may confine the organic photodetector within the surrounded one or more pixels such that the surrounded one or more pixels are electrically isolated from a neighboring pixel. |
| US09257477B2 |
Solid-state imaging device and camera module
A solid-state imaging device is provided. The solid-state imaging device includes a plurality of arrayed pixels, an optical inner filter layer, and a light-blocking side wall. The plurality of arrayed pixels each includes a photoelectric conversion portion and a pixel transistor. The optical inner filter layer is provided for blocking infrared light and formed facing toward a light-receiving surface of the photoelectric conversion portion of a desired pixel among the arrayed pixels. The light-blocking side wall is formed on a lateral wall of the optical inner filter layer. |
| US09257476B2 |
Grids in backside illumination image sensor chips and methods for forming the same
A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines. |
| US09257473B2 |
Solid-state imaging device
According to one embodiment, a solid-state imaging device is provided which comprises a floating diffusion, a transfer gate, and a photoelectric conversion element. The floating diffusion is provided in a surface of a semiconductor layer. The transfer gate extends inward from the surface of the semiconductor layer and bends in the semiconductor layer toward the floating diffusion side. The photoelectric conversion element is provided in part of the semiconductor layer on the opposite side of the transfer gate from the floating diffusion and stretches from the side-surface side of the transfer gate to a position under the bottom thereof. |
| US09257469B2 |
Color imaging device
An imaging apparatus 10 according to one implementation of the present invention includes: a plurality of photodetectors 5a and 5b; a transparent layer 2 provided at the side of a light-receiving surface 15a, 15b of the photodetectors 5a and 5b; a plurality of spectroscopic portions 3 provided between a light-entering surface 2a of the transparent layer 2 and the photodetectors 5a and 5b; and a plurality of high refractive index transparent members 6 provided closer to the photodetectors 5a and 5b than are the spectroscopic portions 3. The high refractive index transparent members 6 have a higher refractive index than does the transparent layer 2. |
| US09257459B2 |
Image pickup apparatus with pixels that include an amplifier and method for driving the same
An image pickup apparatus of the present invention includes a clipping circuit that clips the voltage of an input node of an amplifying unit in a pixel. The clipping circuit can operate at least in a time period in which a charge is transferred from a photoelectric conversion unit to the input node of the amplifying unit, and can switch among multiple clipping voltages. |
| US09257451B2 |
Display device and semiconductor device
An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased. |
| US09257449B2 |
Semiconductor device and manufacturing method thereof
An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor including a silicon region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, a first insulating layer, a second insulating layer, a third insulating layer, and a second transistor, which includes an oxide semiconductor layer over the third insulating layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode, and a fourth insulating layer and a fifth insulating layer. A first electrode passes through the first insulating layer and the second insulating layer to be electrically connected to the silicon region, and a second electrode passes through the third insulating layer, the fourth insulating layer and the fifth insulating layer to be electrically connected to the first electrode. |
| US09257446B2 |
Semiconductor device and method of manufacturing same
To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy. |
| US09257440B2 |
Non-volatile anti-fuse with consistent rupture
In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped. |
| US09257439B2 |
Structure and method for FinFET SRAM
Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure. |
| US09257435B2 |
Semiconductor device and manufacturing method therefor
A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane. |
| US09257432B2 |
Semiconductor memory device and method of manufacturing semiconductor memory device
A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4F2 at a minimum. |
| US09257430B2 |
Semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode. |
| US09257425B2 |
Semiconductor device and manufacturing method thereof
A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included. |
| US09257417B2 |
Light emitting device package, light emitting device using that package, and illumination device using the light emitting devices
The light emitting device package of the present invention has a longitudinal direction (as viewed from above) and a transverse direction perpendicular to the longitudinal direction, and is provided with a first and second lead-frame lined-up in the longitudinal direction and molded resin holds the first and second lead-frames integrally. The package is characterized in that the first lead-frame has a main body and an extension that extends from the main body with a narrowed width towards the second lead-frame. Further, a recess is established in the bottom surface of the first lead-frame, and at least part of the exposed region of the bottom surface of the extension is separated from the exposed region of the bottom surface of the main body by the molded resin that fills the recess. |
| US09257413B2 |
Stack packages including diffusion barriers over sidewalls of through via electrodes and methods of manufacturing the same
Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed. |
| US09257411B2 |
Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump. |
| US09257410B2 |
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate
Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed. |
| US09257405B2 |
Multi-solder techniques and configurations for integrated circuit package assembly
Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed. |
| US09257403B2 |
Copper ball bond interface structure and formation
An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad. |
| US09257398B2 |
Semiconductor device and method for forming the same
A semiconductor device includes a first pad region including a plurality of first storage nodes, a second pad region neighboring the first pad region and including a plurality of second storage nodes, a coupling portion disposed between the first pad region and the second pad region, and a plate electrode disposed over the plurality of first storage nodes of the first pad region and the plurality of second storage nodes of the second pad region, and disposed in the coupling portion to interconnect the first pad region and the second pad region. |
| US09257395B2 |
Semiconductor device
A semiconductor device includes a base substrate on which a substrate electrode is arranged, and a semiconductor element which includes a chip electrode electrically connected via solder to the substrate electrode and in which a light absorbing layer is formed on a lower surface side. |
| US09257391B2 |
Hybrid graphene-metal interconnect structures
Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene. |
| US09257389B2 |
Semiconductor device having metal interconnections
A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer. |
| US09257382B2 |
Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer
A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings. |
| US09257381B2 |
Semiconductor package, and interposer structure of the semiconductor package
A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. |
| US09257377B2 |
Semiconductor device and measurement device having an oscillator
A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components. |
| US09257376B2 |
Semiconductor package and method of manufacturing the same
There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package according to an exemplary embodiment of the present disclosure includes: a substrate having a first device mounted thereon; a first lead frame formed on the substrate; a second lead frame formed to be spaced apart from the substrate; a post formed on the substrate and formed between the first lead frame and the second lead frame; and a molding part formed to surround the substrate and formed to protrude portions of the first and second lead frames, wherein the post includes a body part bonded to the substrate and a protruding part protruded to an exterior of the molding part. |
| US09257374B1 |
Thin shrink outline package (TSOP)
Consistent with an example embodiment, a thin outline shrink package (TSOP) provides for a significant reduction in lead pitch along with a reduced package profile for a semiconductor device die packaged, therein. |
| US09257373B2 |
Electronic component device
A wiring board includes a wiring forming region in which a plurality of wiring layers are stacked while sandwiching insulating layers, an outer periphery region which is arranged around the wiring forming region and in which a reinforcing pattern is formed in the same layer as each of the wiring layers. An area ratio of the reinforcing pattern to the outer periphery region and an area ratio of the wiring layer to the wiring forming region are substantially the same in each of the layers, and the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective. |
| US09257367B2 |
Integrated circuit device, method for producing mask layout, and program for producing mask layout
According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement. |
| US09257365B2 |
Cooling assemblies and power electronics modules having multiple-porosity structures
Cooling assemblies and power electronics modules having multiple-level porosity structures with both a micro- and macro-level porosity are disclosed. In one embodiment, a cooling assembly includes a jet impingement assembly including a fluid inlet channel fluidly coupled an array of orifices provided in a jet plate, and a heat transfer substrate having a surface. The heat transfer substrate is spaced apart from the jet plate. A first array of metal fibers is bonded to the surface of the heat transfer substrate in a first direction, and a second array of metal fibers is bonded to the first array of metal fibers in a second direction. Each metal fiber of the first array of metal fibers and the second array of metal fibers includes a plurality of metal particles defining a micro-porosity. The first array of metal fibers and the second array of metal fibers define a macro-porosity. |
| US09257362B2 |
Heat dissipation module with heat pipe
A heat dissipation module configured on a substrate having a heat producing element thereon includes a holder configured on the substrate and a heat sink having a base opposite to the heat producing element and pivotally connected to the holder and capable of joining to the substrate with the heat producing element covered by the base. |
| US09257361B2 |
In-situ thermoelectric cooling
Methods and structures for thermoelectric cooling of 3D semiconductor structures are disclosed. Thermoelectric vias (TEVs) to form a thermoelectric cooling structure. The TEVs are formed with an etch process similar to that used in forming electrically active through-silicon vias (TSVs). However, the etched cavities are filled with materials that exhibit the thermoelectric effect, instead of a conductive metal as with a traditional electrically active TSV. The thermoelectric materials are arranged such that when a voltage is applied to them, the thermoelectric cooling structure carries heat away from the interior of the structure from the junction where the thermoelectric materials are electrically connected. |
| US09257360B2 |
Backplane for display device, and display device including the same
A backplane for a display device and the display device are disclosed. In one aspect, the backplane includes a substrate, an active layer formed over the substrate including a channel region, a source region contacting a first side of the channel region, and a drain region contacting a second side of the channel region. The backplane further includes a gate electrode formed adjacent to the channel region, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. The active layer includes a plurality of heat radiation pins that extend in a direction of the thickness of the active layer. |
| US09257356B2 |
Semiconductor device and method of forming an IPD beneath a semiconductor die with direct connection to external devices
A semiconductor device has a conductive layer formed on a substrate. The conductive layer has a first portion constituting contact pads and a second portion constituting an integrated passive device such as an inductor. A spacer is formed on the substrate around the second portion of the conductive layer. The spacer can be insulating material or conductive material for shielding. A semiconductor die is mounted to the spacer. An electrical connection is formed between contact pads on the semiconductor die and the contact pads on the substrate. An encapsulant is formed around the semiconductor die, electrical connections, spacer, and conductive layer. The substrate is removed to expose the conductive layer. An interconnect structure is formed on the backside of the substrate. The interconnect structure is electrically connected to the conductive layer. The semiconductor device can be integrated into a package. |
| US09257351B2 |
Metrology marks for bidirectional grating superposition patterning processes
Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a template mask that extends across and perpendicular to such spacer gratings. Cut spacer gratings are etched into a second layer using the template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer. |
| US09257346B2 |
Apparatus and methods for forming a modulation doped non-planar transistor
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed. |
| US09257345B2 |
Anti-fuse array of semiconductor device and method for forming the same
An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region. |
| US09257343B2 |
Method for fabricating fin field effect transistors
A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric. |
| US09257336B2 |
Bottom-up plating of through-substrate vias
According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad. |
| US09257335B2 |
Electronic devices utilizing contact pads with protrusions and methods for fabrication
An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front-side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front-side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s). |
| US09257331B2 |
Method of making interconnect structure
A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening. |
| US09257329B2 |
Methods for fabricating integrated circuits including densifying interlevel dielectric layers
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ILD layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material. The densified surface layer and the ILD layer are etched through to expose a metal line of the metallization layer. |
| US09257327B2 |
Methods of forming a Field Effect Transistor, including forming a region providing enhanced oxidation
Methods of forming a Field Effect Transistor (FET) are provided. The methods may include forming a region that provides enhanced oxidation under a fin-shaped FET (FinFET) body. |
| US09257326B2 |
Method of making backside illuminated image sensors
A method of making a backside illuminated image sensor includes forming a first isolation structure in a pixel region of a substrate, where a bottom of the first isolation structure is exposed at a back surface of the substrate. The method further includes forming a second isolation structure in a peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. Additionally, the method includes forming an implant region adjacent to at least a portion of sidewalls of the first isolation structure, where the portion of the sidewalls is located closer to the back surface than a front surface of the substrate, and where the second isolation structure is free of the implant region. |
| US09257325B2 |
Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices
Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HDPCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability. |
| US09257321B2 |
Singulation apparatus and method
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process. |
| US09257320B2 |
Wafer carrier purge apparatuses, automated mechanical handling systems including the same, and methods of handling a wafer carrier during integrated circuit fabrication
A wafer carrier purge apparatus, an automated mechanical handling system, and a method of handling a wafer carrier during integrated circuit fabrication are provided. The wafer carrier purge apparatus includes a purge plate adapted for insertion into a carrier storage position. The purge plate includes a gas port and a gas nozzle in fluid communication with the gas port. The gas port receives a gas flow. The gas nozzle is adapted to contact an inlet port of a wafer carrier. The purge plate further includes a vacuum port and a vacuum nozzle in fluid communication with the vacuum port, spaced from the gas nozzle. The vacuum nozzle is adapted to capture gas that escapes from the wafer carrier through an outlet port of the wafer carrier. The purge plate is separate and removable from the carrier storage position. |
| US09257314B1 |
Methods and apparatuses for deuterium recovery
Novel methods, systems, and apparatuses for reclaiming annealing gases from a high pressure annealing processing system are disclosed. According to an embodiment, the exhaust gasses from the high pressure annealing processing system are directed into a gas reclaiming system only when a precious gas, e.g., deuterium is used. The annealing gas is the separated from other gasses used in the high pressure annealing processing system and is then pressurized, filtered, and purified prior to transferring the gas to a bulk storage distribution unit. In one embodiment, the reclaimed gas is then again provided to the high pressure annealing processing system to anneal the wafers. |
| US09257306B2 |
Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device
A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region. |
| US09257304B2 |
Method of manufacturing non-volatile memory device
A method for manufacturing a non-volatile memory includes depositing a first conductive film and a protective film on a substrate including a logic area and a cell area, patterning the protective film, depositing a hard mask layer on the first conductive film and the patterned protective film to pattern the hard mask layer, using the patterned hard mask layer to form a logic gate on the logic area, exposing a surface of the first conductive film in the cell area and forming a control gate on the cell area. |
| US09257302B1 |
CVD flowable gap fill
Provided are methods of filling gaps on a substrate by creating flowable silicon oxide-containing films. The methods involve introducing vapor-phase silicon-containing precursor and oxidant reactants into a reaction chamber containing the substrate under conditions such that a condensed flowable film is formed on the substrate. The flowable film at least partially fills gaps on the substrate. In certain embodiments, the methods involve using a catalyst in the formation of the film. The catalyst may be incorporated into one of the reactants and/or introduced as a separate reactant. |
| US09257296B2 |
Etch process with pre-etch transient conditioning
A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence. |
| US09257294B2 |
Methods and apparatuses for energetic neutral flux generation for processing a substrate
Apparatuses and methods for processing substrates are disclosed. A processing apparatus includes a chamber for generating a plasma therein, an electrode associated with the chamber, and a signal generator coupled to the electrode. The signal generator applies a DC pulse to the electrode with sufficient amplitude and sufficient duty cycle of an on-time and an off-time to cause events within the chamber. A plasma is generated from a gas in the chamber responsive to the amplitude of the DC pulse. Energetic ions are generated by accelerating ions of the plasma toward a substrate in the chamber in response to the amplitude of the DC pulse during the on-time. Some of the energetic ions are neutralized to energetic neutrals in response to the DC pulse during the off-time. Some of the energetic neutrals impact the substrate with sufficient energy to cause a chemical reaction on the substrate. |
| US09257289B2 |
Lowering parasitic capacitance of replacement metal gate processes
The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance. |
| US09257287B2 |
Laser annealing device and method
A laser annealing device for compensating wafer heat maps and its method are disclosed. A laser annealing device comprises a pump laser source array including of a plurality of pump laser sources for irradiating a tunable mask, each pump laser source emitting pump laser, an annealing laser source for emitting annealing laser and irradiating the tunable mask, and a tunable mask for transmitting at least part of the annealing laser after being irradiated by the pump laser. |
| US09257286B2 |
Supply source and method for enriched selenium ion implantation
A novel method for ion implanting isotopically enriched selenium containing source material is provided. The source material is selected and enriched in a specific mass isotope of selenium, whereby the enrichment is above natural abundance levels. The inventive method allows reduced gas consumption and reduced waste. The source material is preferably stored and delivered from a sub-atmospheric storage and delivery device to enhance safety and reliability during the selenium ion implantation process. |
| US09257284B2 |
Silicon heterojunction solar cells
Methods are described for fabricating HIT solar cells, including double heterojunction and hybrid heterojunction-homojunction solar cells, with very thin single crystal silicon wafers, where the silicon wafer may be less than 80 microns thick, and even less than 50 microns thick. The methods overcome potential issues with handling these very thin wafers by using a process including epitaxial silicon deposition on a growth substrate, partial cell fabrication, attachment to a support substrate and then separation from the growth substrate. Some embodiments of the present invention may include a solar cell device architecture comprising the combination of a heterostructure on the front side of the device with a homojunction at the rear of the device. Furthermore, device performance may be enhanced by including a dielectric stack on the backside of the device for reflecting long wavelength infrared radiation. |
| US09257282B2 |
Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench. |
| US09257281B2 |
Methods of fabricating a pattern using the block co-polymer materials
A method of fabricating a pattern comprising sequentially forming a pattern formation layer and a neutral layer on over a substrate having in a first regions and a second regions, forming guide patterns on first portions of over the neutral layer in the second regions, forming a first block copolymer layers on over second portions of the neutral layer in the first regions, phase-separating the tint block copolymer layers such that each of the first block copolymer layers includes to form first polymer blocks having a first phase and first polymer blocks having a second phase, removing the guide patterns to form openings that expose the first portions of the neutral layer in the second region, forming a second block copolymer layer on over the phase-separated first block copolymer layers and in the openings, phase-separating the second block copolymer layer into to form second polymer blocks having the first phase and second polymer blocks having the second phase removing the second polymer blocks having the second phase and the first polymer blocks having the second phase, and etching the neutral layer and the pattern formation layer using the first polymer blocks having the first phase and the second polymer blocks having the first phase as an etch masks. |
| US09257278B2 |
Method for forming TiN and storage medium
When forming a TiN film to be formed as a metallic hard mask for etching a film formed on a substrate to be processed, a first step and a second step are repeated a plurality of times to form a TiN film having reduced film stress. In the first step (step 1), the substrate to be processed is conveyed into a processing chamber, TiCl4 gas and a nitriding gas are fed into the processing chamber, the interior of which being kept in a depressurized state during this time, and a plasma from the gases is generated to form a TiN unit film. In the second step (step 2), a nitriding gas is fed into the processing container, a plasma of the gas is generated, and the TiN unit film is subjected to plasma nitriding. |
| US09257275B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first layer containing boron and a halogen group by supplying a first precursor gas containing boron and the halogen group to the substrate; and forming a second layer containing the predetermined element, boron, carbon, and nitrogen by supplying a second precursor gas containing the predetermined element and an amino group to the substrate and modifying the first layer. |
| US09257264B2 |
Harmonic cold plasma devices and associated methods
A gas cartridge is described that is configured to provide sufficient gas to support cold plasma generation for a specific medical process. The gas cartridge has a seal that is pierced upon connection of the gas cartridge to the cold plasma delivery system. Different embodiments are described that use different connection locations between the gas cartridge and the cold plasma delivery system. A shroud is also described that shields the user if the cold plasma delivery system is dropped and the gas cartridge ruptures. Use of an ID system assists in ensuring that the correct gas mixture, correct gas cartridge and correct power supply settings are used for the particular medical treatment process. |
| US09257260B2 |
Method and system for adaptively scanning a sample during electron beam inspection
A system for adaptive electron beam scanning may include an inspection sub-system configured to scan an electron beam across the surface of a sample. The inspection sub-system may include an electron beam source, a sample stage, a set of electron-optic elements, a detector assembly and a controller communicatively coupled to one or more portions of the inspection sub-system. The controller may assess one or more characteristics of one or more portions of an area of the sample for inspection and, responsive to the assessed one or more characteristics, adjust one or more scan parameters of the inspection sub-system. |
| US09257259B2 |
Electron beam irradiation method and scanning electronic microscope
Provided is an electron beam scanning method for forming an electric field for appropriately guiding electrons emitted from a pattern to the outside of the pattern, and also provided is a scanning electron microscope. When an electron beam for forming charge is irradiated to a sample, a first electron beam is irradiated to a first position (1) and a second position (2) having the center (104) of a pattern formed on the sample as a symmetrical point, and is then additionally irradiated to two central positions (3, 4) between the first and second irradiation position, the two central positions (3, 4) being on the same radius centered on the symmetrical point as are the first and second positions. Further, after that, the irradiation of the first electron beam to the central positions between existing scanning positions on the radius is repeated. |
| US09257255B2 |
Single-pole x-ray emitter
A single-pole x-ray emitter includes an emitter housing, in which an x-ray tube with a vacuum housing and a drive motor are arranged. A cathode that generates an electron beam, and a rotating anode that is struck by the electron beam along a focal path are arranged in the vacuum housing. The vacuum housing includes a drive-side housing wall and an anode-side housing wall, and the rotating anode is held in a torsionally rigid manner on an anode tube that is rotatably mounted on a stationary part of a rotor shaft that is coupled to the drive motor. The stationary part of the rotor shaft is joined to the anode-side housing wall of the vacuum housing via a ring-shaped fixing. The anode tube incorporates a temperature compensation element. The focal path is arranged on a side of the rotating anode that faces away from the anode-side housing wall. |
| US09257254B2 |
Transmissive target, X-ray generating tube including transmissive target, X-ray generating apparatus, and radiography system
A transmissive target includes a target layer configured to include target metal and generate X-ray when receiving electrons and a substrate configured to support the target layer and include carbon as a main component. A carbide region including carbide of the target metal and a non-carbide region including the target metal are disposed in a mixed manner on a boundary surface between the substrate and the target layer on a target layer side. |
| US09257248B2 |
Semiconductor switch and power conversion apparatus
According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off. |
| US09257244B2 |
Electronic device with power switch
A power switch includes an operating button, an elastic member, a printed circuit board, a support member, and a fixing module. The operating button includes a connecting portion. The elastic member includes a fixing portion and an elastic portion. The printed circuit board includes a main body and a contacting element. The support member includes a base portion and a receiving portion perpendicularly extending from the base portion, and the base portion defines a hole communicating with the receiving portion. The fixing module includes a cover and a contacting member formed on the cover. The connecting portion of the operating button is fixed to the main body and is received in the hole of the support member and the receiving portion. The fixing portion of the elastic member is sandwiched between the connecting portion of the operating button and the main body. |
| US09257243B2 |
Operating device, in particular for a vehicle component
The operating device (10), in particular for a vehicle component or generally for a human/machine interface, is provided with at least one pushbutton (28), which has a depressible pushbutton element (26). In addition, the operating device (10) has a guide element (18), which defines an accommodating area (24) in which the pushbutton element (26) is at least partially accommodated and in which the pushbutton element (26) is guided, and a capacitive proximity sensor (36) with an electrode (34) for detecting an object approaching the pushbutton element (26), in particular a hand or a finger of a hand. The electrode (34) is arranged outside the accommodating area (24) of the guide element (18). |
| US09257239B2 |
Binder composition for electrode
An object of the invention is to provide an electrode material slurry for preparation of lithium-ion secondary batteries favorable in properties and superior in storage stability and an aqueous binder composition for lithium-ion secondary batteries that can be used for production of lithium-ion secondary batteries superior in discharge rate characteristics and cycle characteristics.Provided is a binder composition for lithium-ion secondary battery electrode, comprising polymer particles containing (a) an ethylenic unsaturated carboxylic ester compound and (b) an ethylenic unsaturated sulfonic acid compound at a (a)/(b) mass ratio of (98 to 91)/(2 to 9) in a total (a) and (b) amount of 70 mass % or more, based on the monomeric raw materials. |
| US09257236B2 |
Organic dye for a dye-sensitized solar cell
Organic dye for a dye-sensitized solar cell (DSSC) comprising at least one electron-acceptor unit and at least one π-conjugated unit. Said organic dye is particularly useful in a dye-sensitized photoelectric transformation element which, in its turn, can be used in a dye-sensitized solar cell (DSSC). |
| US09257235B2 |
Electrochemical capacitor
An electrochemical capacitor includes a positive electrode, a negative electrode disposed proximally to the positive electrode, and a non-aqueous electrolyte, wherein the positive electrode and the negative electrode are immersed in the non-aqueous electrolyte, and a case is presented in the energy storage system to accommodate the non-aqueous electrolyte, the positive electrode, and the negative electrode. The positive electrode has a porous matrix having a plurality of micrometer sized pores and nanostructured metal oxides, wherein the porous matrix is a 3-dimensional (3D) mesoporous metal or a 3D open-structured carbonaceous material, and the nanostructured metal oxides are coated inside the plurality of pores of the porous matrix. The non-aqueous electrolyte includes organic compounds having at least one acylamino group and lithium salts characterized as LiX, wherein Li is lithium and X comprises SCN−; the organic compounds are cyclic compounds; and the cyclic compounds comprise 2-oxazolidinone, ethyleneurea, or the combination thereof. |
| US09257233B2 |
Method for manufacturing laminated ceramic capacitor
A method of manufacturing a laminated ceramic capacitor having a dielectric ceramic which contains, as its main constituent, a perovskite-type compound containing Ca and Zr and optionally containing Sr, Ba, and Ti, and further contains Si, Mn, and Al, and when the total content of Zr and Ti is regarded as 100 parts by mol, the total content (100×m) of Ca, Sr, and Ba meets 1.002≦m≦1.100 in terms of parts by mol, the Si content n meets 0.5≦n≦10 in terms of parts by mol, the Mn content u meets 0.5≦u≦10 in terms of parts by mol, and the Al content w meets 0.02≦w≦4 in terms of parts by mol, m and n satisfying −0.4≦100(m−1)−n≦3.9. |
| US09257232B2 |
Multilayer electronic components with an inhibitor-influencing layer and method for manufacturing the same
A multilayer electronic component is provided having a structure in which a dielectric layer and an internal electrode layer are alternately laminated. The internal electrode layer includes metal powder and an inhibitor. The inhibitor includes 0.5 to 20 mol % of a Ca component based on 100 mol % of a barium titanate (BT) base material. A method for manufacturing the same is also provided. |
| US09257231B2 |
High energy capacitors
The following invention relates to high energy capacitors with increased thermal resilience over conventional bulk ceramic capacitors, particularly capacitors that may be formed into a three dimensional shape to fit inside an existing device. The capacitor is provided with first and second electrodes which have a plurality of interlocating protrusions, which increase the relative surface area of the electrodes. The first and second electrodes and interlocating protrusions are provided with through holes. The devices are filled with a flowable dielectric material. |
| US09257230B2 |
Multilayer ceramic capacitor and board having the same mounted thereon
A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers and having first and second main surfaces, first and second side surfaces, and first and second end surfaces; a capacitor part formed in the ceramic body and including first and second internal electrodes, the first internal electrode having a first lead exposed to the second main surface and the second internal electrode having a second lead exposed to the first main surface; resistor parts including first and second internal connection conductors formed on the same dielectric layers among the plurality of dielectric layers in the ceramic body; and first to fourth external electrodes, first and third connection terminals, and second and fourth connection terminals. The capacitor part and the resistor parts may be connected in series to one another. |
| US09257227B2 |
Method for manufacturing rare-earth magnet
Provided is a manufacturing method of a rare-earth magnet with high coercive force, including a first step of pressing-forming powder as a rare-earth magnet material to form a compact S, the powder including a RE-Fe—B main phase MP (RE: at least one type of Nd and Pr) and a RE-X alloy (X: metal element) grain boundary phase surrounding the main phase; and second step of bringing a modifier alloy M into contact with the compact S or a rare-earth magnet precursor C obtained by hot deformation processing of the compact S, followed by heat treatment to penetrant diffuse melt of the modifier alloy M into the compact S or the rare-earth magnet precursor C to manufacture the rare-earth magnet RM, the modifier alloy including a RE-Y (Y: metal element and not including a heavy rare-earth element) alloy having a eutectic or a RE-rich hyper-eutectic composition. |
| US09257225B2 |
Methods and configurations of LC combined transformers and effective utilizations of cores therein
The LC combined transformer is a combination of capacitors, inductors and an electrically-isolated mutual inductor, i.e. conventional transformer; which in principle is a unity-coupled mutual capacitor or a cascade connection of an ideal transformer and unity-coupled mutual capacitor(s). To improve the imperfections of widely-used transformers, by employing the simplest passive-circuit design to attain a perfectly-functional match between mutual capacitors and the mutual inductor, this invention achieves optimal features of current or/and voltage transformation, and introduces a new function of waveform conversion from square to quasi-sine. The ideal current transformer herein is suitable for sinusoidal current measurements, the ideal voltage transformer herein suitable for sinusoidal voltage measurements, and they also could be upgraded to ideal transformers for both current and voltage transformations. This transformer can be designed as power transferable as well as waveform convertible, applicable in power systems or power electronics. Herein also states the design approach of integrated inductor and mutual inductor, and the use of push-pull inductor, materials being fully utilized and sizes decreased. |
| US09257223B2 |
Inductor
An inductor includes soft magnetic alloy powder-containing resin that contains amorphous soft magnetic alloy powder, which resin is used as a sealing material that seals a coil wound around a winding core of the core. This soft magnetic alloy powder-containing resin contains two groups of large and small particles having a first peak and second peak in their particle size distribution, where the particle size corresponding to the second peak is equal to or smaller than one-half the particle size corresponding to the first peak, and the magnitude ratio (abundance ratio) of the second peak and first peak is 0.2 or more but 0.6 or less. The inductor demonstrates improved DC superimposition characteristics and does not cause sealing irregularities. |
| US09257217B2 |
Inductor element, method for manufacturing inductor element, and wiring board
An inductor element has a support layer, a first conductive layer formed on the support layer and having a first inductor pattern and a first pad at one end of the first inductor pattern, a first insulation layer formed on the support layer and first conductive layer and including a magnetic material layer and a resin layer, a second conductive layer formed on the first insulation layer and having a second inductor pattern and a second pad at one end of the second inductor pattern, and a via conductor formed through the first insulation layer and connecting the first and second conductive layers. The magnetic material layer is covering at least part of the first inductor pattern, the resin layer is covering the first pad and has opening exposing at least part of the first pad, and the via conductor is formed in the opening of the first insulation layer. |
| US09257214B1 |
Bus bar extender
An apparatus for extending a bus bar is disclosed. The apparatus may include a first extension piece and a second extension piece. The first extension piece may have multiple surfaces. A first surface may have a first group of receiving portions, a second may have a second group of receiving portions, and a third surface may have a curvature that offsets the third surface from the second surface. The second extension piece may also have multiple surfaces. The second extension piece may have a first surface that includes a first group of receiving portions, a second surface that includes a second group of receiving portions, and a third surface that is substantially parallel to the second surface and includes a third group of receiving portions. When connected to a bus bar, the first extension piece and the second extension piece may be substantially adjacent to one another. |
| US09257212B2 |
Dielectric material with low dielectric loss
The invention provides a dielectric material with low dielectric loss. The dielectric material comprises (i) 40˜80 parts by weight of polyphenylene ether resin having a Mw of 1000˜7000, a Mn of 1000˜4000 and Mw/Mn=1.0˜1.8; (ii) 5˜30 parts by weight of bismaleimide resins; and (iii) 5˜30 parts by weight of polymer additives, wherein the dielectric material has Dk of 3.75˜4.0 and Df of 0.0025˜0.0045. The dielectric material is suitably used in prepregs and insulation layers of a circuit board, because it has high Tg, low thermal expansion coefficient, low moisture absorption and excellent dielectric properties such as Dk and Df. |
| US09257199B2 |
Canary circuit with passgate transistor variation
A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate transistor that is driven by a wordline voltage. The canary circuit further includes a regulator circuit that outputs a wordline voltage that accounts for a predetermined offset of a threshold voltage of the passgate transistor. In an embodiment, the regulator circuit is a subtractor circuit that generates the wordline voltage from a reference voltage based in part on the threshold voltage variation of the passgate transistor. |
| US09257185B2 |
Nonvolatile memory device, nonvolatile memory system, program method thereof, and operation method of controller controlling the same
According to example embodiments, a nonvolatile memory device includes a first memory cell configured to store a first data pattern, a second memory cell configured to be programmed using a program voltage, and a coupling program control unit. The coupling program control unit may be configured to perform a verification operation for verifying whether the first memory cell is programmed with the first data pattern. The verification operation may provide to the first memory cell a verification voltage corresponding to the first data pattern. The coupling program control unit may be configured to end programming the second memory cell when the verification operation on the first memory cell indicates a pass. |
| US09257183B2 |
Semiconductor storage device having nand-type flash memory
A semiconductor storage device includes a plurality of memory cell transistors that are connected to each other in series, a plurality of word lines that are connected to the plurality of memory cell transistors, and a control circuit. The control circuit applies a first potential to a selected one of the plurality of word lines. The control circuit applies a second potential that is higher than the first potential to the word lines that are not selected at different timings before the first potential is applied to the selected word line. |
| US09257182B2 |
Memory devices and their operation having trim registers associated with access operation commands
Methods, and apparatus configured to perform methods, including loading trim settings into a trim register of a memory device associated with a command for an access operation, receiving the command for the access operation at the memory device, setting trims for the access operation in response to the trim settings of the trim register associated with the command for the access operation, and performing the access operation using the trims for the access operation; and including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access operation, loading updated trim settings into a particular trim register of the memory device, setting updated trims for the access operation in response to the updated trim settings of the particular trim register, and resuming the access operation using the updated trims. |
| US09257180B2 |
Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal. |
| US09257178B1 |
Devices and methods for writing to a memory cell of a memory
A method for writing to a memory cell of a memory is disclosed. The method includes generating a write voltage, generating a write current that flows from one of a bit line and a source line of the memory, generating a mirror current that mirrors the write current, generating a compliance current, generating a write detect voltage based on the mirror current and the compliance current, detecting the write detect voltage, when it is detected that the write detect voltage is less or greater than a threshold value, permitting application of the write voltage to the memory cell of the memory, and when it is detected that the write detect voltage increases or decreases to the threshold value, inhibiting the application of the write voltage to the memory cell of the memory. A device that performs the method is also disclosed. |
| US09257174B2 |
Tracking bit cell and method
A method includes generating a first edge of a first tracking signal for a tracking cell, generating a first edge of a second tracking signal for the tracking cell based on the first edge of the first tracking signal, generating a first edge of a cell signal for a memory cell, generating a second edge of the first tracking signal based on the first edge of the second tracking signal, and generating a second edge of the cell signal based on the second edge of the first tracking signal. A transistor in the tracking cell operates at a tracking voltage value and a transistor in the memory cell operates at a memory voltage value different from the tracking voltage value. |
| US09257165B2 |
Assisted local source line
In some examples, a memory device has a memory array configured to include sets of bit cells grouped based in part on an arrangement of local source lines. Each of the groups of cells may include an assist bit having a lower impedance than the other bit cells of the group to cause current distributed by the local source lines to be largely provided to the assist bit. In some examples, the assist bit include a shorted tunnel junction and in other examples, multiple assist bits may be connected by one or more bridge assisted bit lines. |
| US09257164B2 |
Circuits and methods for DQS autogating
In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer. |
| US09257161B2 |
Mechanism for enabling full data bus utilization without increasing data granularity
A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity. |
| US09257160B2 |
Precharge circuit and semiconductor memory apparatus using the same
A precharge circuit may include a precharge control unit, a first precharge unit, and a second precharge unit. The precharge control unit may generate a read precharge signal and a write precharge signal in response to a read signal, a write signal, and a precharge signal. The first precharge unit may precharge a data input/output line to a first voltage level in response to the read precharge signal. The second precharge unit may precharge the data input/output line to either a second voltage level or a third voltage level in response to the write precharge signal. |
| US09257158B2 |
Semiconductor device
A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a D flip-flop may be saved. |
| US09257157B2 |
Memory storage device, memory controller, and temperature management method
A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device. |
| US09257155B2 |
Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. |
| US09257152B2 |
Memory architectures having wiring structures that enable different access patterns in multiple dimensions
Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions. |
| US09257149B2 |
Broadcast pause and resume for enhanced television
Embodiments of the present invention provide for broadcast pause and resume for enhanced television. In some embodiments, software key frames identifying a state of a browser at a plurality of points in time may be used for synchronizing a series of graphics to a video stream. Other embodiments may be described and claimed. |
| US09257146B1 |
Data storage device comprising sequence detector compensating for inter-track interference
A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. A first data track is read to generate a first read signal, the first read signal is sampled to generate first read signal samples, a first data sequence is detected based on the first read signal samples, and the first data sequence is converted into corresponding first expected samples. A second data track adjacent the first data track is read to generate a second read signal, the second read signal is sampled to generate second read signal samples, and a second data sequence is detected based on the second read signal samples and the first expected samples. |
| US09257141B2 |
Polarization conversion element
A polarization conversion element includes a phase reversal element and a polarization plane rotation element including a liquid crystal layer. The liquid crystal layer has a plurality of regions disposed along circumferential direction with the intersection point of the polarization plane rotation element and the optical axis as the center with alignment directions different from each other. When electric voltage in accordance with the wavelength of linear polarization incident on the polarization plane rotation element is applied, each region rotates the polarization plane of the polarization component transmitted by each region, and thereby converts linear polarization to radial polarization. The phase reversal element reverses, among the first and the second annular portions alternately disposed along the radial direction with the optical axis as the center, the phase of light incident on the first annular portion relative to the phase of light incident on the second annular portion. |
| US09257140B2 |
Systems and methods for determining a position error of a read/write head
A system for tracking a position error of a read/write head. The read/write head is configured to read data recorded to a data layer of a recording medium and read servo information recorded to a dedicated servo layer of the recording medium. To read the servo information, the read/write head is configured to read, from a first track, a first servo signal including first servo bursts of a predetermined frequency, and read, from a second track adjacent to the first track, a second servo signal including second servo bursts of the predetermined frequency. The first servo bursts are orthogonal to the second servo bursts. A position error signal determination circuit is configured to determine the position error using at least one of the first servo signal and the second servo signal. |
| US09257138B1 |
Slider assembly and method of manufacturing same
A substrate assembly includes a chip coupled with a carrier, a substrate having a first surface and an opposing second surface, and a support structure mounted to the second surface of the substrate and in contact with the carrier. A method of bonding a chip and carrier assembly to a substrate includes contacting the chip and carrier assembly with the bond material and applying heat and force on the chip and carrier assembly until the support structure is mounted on the second surface of the substrate and in contact with the carrier. A substrate assembly includes a chip coupled with a carrier, a substrate having a first surface and an opposing second surface, and one of the carrier or the substrate comprising a trench having a periphery, wherein the second surface of the substrate supports the carrier along the periphery of the trench. |
| US09257137B2 |
Magnetic writer having multiple gaps with more uniform magnetic fields across the gaps
A magnetic device according to one embodiment includes a source of flux; a magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and riot positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux. |
| US09257135B2 |
Systems and methods for reading data from a storage medium
A system for reading data from a storage medium. The system includes a reader and a data determination circuit. The reader is configured to receive a first signal from a first position relative to the storage medium and read a second signal from a second position relative to the storage medium. Each of the first signal and the second signal includes a combination of first data stored in a first track and second data stored in a second track. The data determination circuit is configured to determine third data stored at a predetermined position using the combination of the first data stored in the first track and the second data stored in the second track as received in the first signal and the combination of the first data stored in the first track and the second data stored in the second track as received in the second signal. |
| US09257133B1 |
Secure input to a computing device
A computing device senses speech or other user input. One or more physical variable pertaining to a user of the computing device are also sensed, and respective signals are analyzed or compared to the user input. The analysis determines if the user input is likely that of an authorized user, and assigns a confidence metric to that determination. The computing device may then perform actions corresponding to the speech or user input content in accordance with the determination. |
| US09257130B2 |
Audio encoding/decoding with syntax portions using forward aliasing cancellation
A codec supporting switching between time-domain aliasing cancellation transform coding mode and time-domain coding mode is made less liable to frame loss by adding a further syntax portion to the frames, depending on which the parser of the decoder may select between a first action of expecting the current frame to have, and thus reading forward aliasing cancellation data from the current frame and a second action of not-expecting the current frame to have, and thus not reading forward aliasing cancellation data from the current frame. In other words, while a bit of coding efficiency is lost due to the provision of the new syntax portion, it is merely the new syntax portion which provides for the ability to use the codec in case of a communication channel with frame loss. Without the new syntax portion, the decoder would not be capable of decoding any data stream portion after a loss and will crash in trying to resume parsing. Thus, in an error prone environment, the coding efficiency is prevented from vanishing by the introduction of the new syntax portion. |
| US09257128B2 |
Apparatus and method for coding and decoding multi object audio signal with multi channel
Provided are an apparatus and method for coding and decoding a multi object audio signal with multi channel. The apparatus includes: a multi channel encoding means for down-mixing an audio signal including a plurality of channels, generating a spatial cue for the audio signal including the plurality of channels, and generating first rendering information including the generated spatial cue; and a multi object encoding unit for down-mixing an audio signal including a plurality of objects, which includes the down-mixed signal from the multi channel encoding unit, generating a spatial cue for the audio signal including the plurality of objects, and generating second rendering information including the generated spatial cue, wherein the multichannel encoding unit generates a spatial cue for the audio signal including the plurality of objects regardless of a Coder-DECoder (CODEC) scheme the limits the multi channel encoding unit. |
| US09257127B2 |
Apparatus and method for coding and decoding multi-object audio signal with various channel including information bitstream conversion
Provided is an apparatus and method for coding and decoding multi-object audio signals with various channels and providing backward compatibility with a conventional spatial audio coding (SAC) bitstream. The apparatus includes: an audio object coding unit for coding audio-object signals inputted to the coding apparatus based on a spatial cue and creating rendering information for the coded audio-object signals, where the rendering information provides a coding apparatus including spatial cue information for audio-object signals; channel information of the audio-object signals; and identification information of the audio-object signals, and used in coding and decoding of the audio signals. |
| US09257125B2 |
Audio frame timing correction method and wireless device
An audio frame timing correction method and a wireless device are provided. A controller generates a reference clock for audio coding/decoding such that the reference clock runs fast and moved forward within an audio data sampling interval with the remaining time becoming a margin of the interval. An audio codec decodes demodulated data based on the reference clock, and codes an audio signal based on the reference clock. A demodulator detects wireless frame deviation and determines an adjustment timing whereat the wireless frame symbol timing and the audio frame timing are corrected based on the deviation and the margin. Upon the adjustment timing, the controller synchronizes audio sampling timing with the wireless frame symbol timing. |
| US09257123B2 |
Vocoder processing method, semiconductor device, and electronic device
In a semiconductor device, a vocoder processing unit requests, after executing a first vocoder process being one of an encoding process and a decoding process and before executing a following second vocoder process being other one of the encoding process and the decoding process, a cache memory to prefetch first program data to be used for the second vocoder process from an external memory. |
| US09257122B1 |
Automatic prediction and notification of audience-perceived speaking behavior
Systems and methods are provided for indicating an audience member's perception of a speaker's speech by receiving a speech sample associated with a speaker and then by analyzing the speech to predict whether an audience would perceive the speech as exemplary of good or poor behavior. This can be also used to notify people when they exhibit good or poor behaviors. For example, good or poor behaviors could include: condescending, whining, nagging, weak, strong, refined, kind, dull, energetic, interesting, boring, engaging, manipulative, likeable, not likeable, sincere, artificial, soothing, abrasive, pleasing, aggravating, inspiring, unexciting, opaque, clear, etc. This invention has applicability to areas such as consumer self-improvement, corporate training, presentation skills training, counseling, and novelty. |
| US09257120B1 |
Speaker verification using co-location information
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying a user in a multi-user environment. One of the methods includes receiving, by a first user device, an audio signal encoding an utterance, obtaining, by the first user device, a first speaker model for a first user of the first user device, obtaining, by the first user device for a second user of a second user device that is co-located with the first user device, a second speaker model for the second user or a second score that indicates a respective likelihood that the utterance was spoken by the second user, and determining, by the first user device, that the utterance was spoken by the first user using (i) the first speaker model and the second speaker model or (ii) the first speaker model and the second score. |
| US09257117B2 |
Speech analytics with adaptive filtering
Contact center agents often work in close proximity to other agents. As a primary agent is engaged in a call, a neighboring agent speech may be picked up by the primary agent's microphone. Contact centers using automated speech recognition systems may monitor the agent's speech for key terms and, if detected, respond accordingly. Determining a primary agent spoke a key term, when the true speaker of the key term is a neighboring agent, may cause errors or other problems. Characterizing at least the primary agent's voice and then, once a key term is detected, determining if it was the primary agent that spoke the key term, may help to reduce the errors. Additionally, computational requirements may be reduced as non-key terms may be quickly discarded and optionally, key terms determined to not have been spoke by the primary agent, may also be discarded without further processing. |
| US09257104B1 |
Layered wood and silk guitar picks
A composite plectrum with a strum direction is disclosed. The plectrum is generally triangular in shape and includes a first layer of wood having a first grain direction, a layer of silk fabric with silk threads that are woven at angles to one another, and a second layer of wood with a grain in a second grain direction. The second layer of wood being adhered to the layer of silk while at 90 degrees to the first layer of wood, so that the layer of silk extends between the two layers of wood and is adhered to both layers of wood. |
| US09257102B2 |
Fully-adjustable capo for stringed musical instruments
A tuning apparatus for a musical instrument is provided. The apparatus includes a clamp, a plurality of string-contacting members, and a string-contacting member spacing adjustment mechanism. The clamp removably attaches to a desired longitudinal position on the instrument's neck. Each member is rotatably supported by the clamp and rotates thereon independently of the other members. Each member also adjustably impinges upon and urges a given string or course thereof on the instrument toward a user-selectable one of three different longitudinal positions on the neck's front surface, these positions including a home position, a home−1 position, and a home+1 position. The mechanism allows a user to adjust the location of the members as a group on the clamp so as to substantially center the plane of rotation of each member over a different string or course thereof, and to maintain substantially equal spacing between each different adjacent pair of members. |
| US09257101B2 |
Method for reducing graphics rendering failures
A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use. |
| US09257100B2 |
Display device and driving method thereof
A display device includes: a display panel displaying a still image and a motion picture; a display panel which displays a still image and a motion picture; a signal controller which controls signals to drive the display panel; and a graphics processing unit which transmits input image data to the signal controller, where the signal controller includes a frame memory which stores compressed image data generated by compressing the input image data, and a mixer which mixes compression recovered image data generated by recovering the compressed image data and the input image data to generate mixed image data. |
| US09257097B2 |
Remote rendering for efficient use of wireless bandwidth for wireless docking
Methods, systems, and devices are described for remote display of content in a wireless network. A source device capable of displaying content may identify one or more rendering instructions for content to be displayed remotely on a sink device. The source device may transmit the one or more rendering instructions to the sink device via a wireless peer-to-peer connection. The sink device may receive the one or more rendering instructions and may execute the one or more rendering instructions to render a display of at least part of the content. Further, the source device may receive data from the sink device via the wireless peer-to-peer connection. The identifying of the one or more rendering instructions by the source device may thus include identifying at least one rendering instruction based at least in part on the received data. |
| US09257095B2 |
Display device with a backlight
A display includes a backlight portion having at least one broad spectrum emitter (such as white) and at least one narrow spectrum emitter (such as red, green, and blue), a liquid crystal panel for displaying an image by spatial light modulation, and control electronics configured to receive input image data and output control signals to both the backlight portion and liquid crystal panel. The control electronics is configured to use color rendering capabilities of the liquid crystal panel under illumination from each of the emitter types individually to calculate a minimum power combination of emission from each emitter type required to display the input image data. The control electronics is further configured to modify the input image data according to the calculated minimum power combination of emitter powers so a resulting display of colors in the image data remains despite changing illumination conditions. |
| US09257092B2 |
Method and system for enhancing user experience for remoting technologies
The disclosure herein describes a client-side system that enhances user experience on a remoting client without consuming additional network bandwidth. During operation, the system receives a sequence of frame updates for a display screen, and determines a sequence of frames corresponding to the frame updates. The system further adaptively applies one or more image enhancing techniques to the sequence of frames based on available network bandwidth, frame refresh rate, or image quality. The image enhancement techniques include predicting a frame based on previously received frames, interpolating a frame based on at least two buffered frames, and reducing appearance of artifacts in a received frame, thereby reducing visual artifacts. |
| US09257088B2 |
Display panel and method of driving the same
A display panel includes: a first pixel including: a first high pixel configured to represent a first high gray level; and a first low pixel configured to represent a first low gray level; and a second pixel adjacent the first pixel in a first direction, the second pixel including: a second high pixel configured to represent a second high gray level based on a second data voltage and the common voltage in response to the first gate signal; and a second low pixel configured to represent a second low gray level based on the second data voltage, the common voltage, and a second divided voltage different from the first divided voltage in response to the first gate signal. |
| US09257085B2 |
Electronic circuit, display device, electronic device, and method for driving electronic circuit
To control the state of an input signal and output signal of a sequential circuit in order to prevent a malfunction of an electronic circuit. An electronic circuit includes a sequential circuit and a control circuit. A first signal, a second signal, and a third signal are input to the sequential circuit as a start signal, a clock signal, and a reset signal, respectively. The sequential circuit outputs, as an output signal, a fourth signal whose state is set in accordance with the state of the inputted first signal, second signal, and third signal. The control circuit controls the state of the third signal input to the sequential circuit. |
| US09257077B2 |
Liquid crystal display apparatus and driving method thereof
An LCD apparatus has a first scan line transmitting a first scan signal, a second scan line transmitting a second scan signal, a data line intersecting the first and second scan lines, a switch element electrically coupled to the first scan line and the data line, a pixel electrode electrically coupled to the switch element, a coupling capacitance electrically coupled to the pixel electrode and the second scan line. The second scan line has three different voltage levels. When the first scan line enables the switch element, the pixel electrode receives a data signal through the data line. When the second scan signal switches to the third voltage level from the second voltage level, the pixel electrode is negative polarity, and when the second scan signal switches to the second voltage level from the third voltage level, the pixel electrode is positive polarity. |
| US09257073B2 |
Display panel driving method, display apparatus, display panel driving apparatus and electronic apparatus
A display panel driving method for controlling the total light emitting period length within a one-field period includes placing a first light emission period, a second light emission period, and a third light emission period within the one-field period, and adjusting, in a state in which a period length from a starting timing of the first light emission period to an ending timing of the third light emission period is at least 25% and at most 75% of a one-field period length, a first no-light emission period between the first light emission period and the second light emission period and a second no-light emission period between the second light emission period and the third light emission period. |
| US09257071B2 |
Semiconductor device and method for driving semiconductor device
One electrode of SW1 is connected to a first wiring, and the other electrode of the SW1 is connected to one electrode of SW2, one electrode of second capacitor, and a gate electrode of a transistor. The other electrode of the SW2 is electrically connected to one electrode of SW3 and one electrode of first capacitor. The other electrode of the SW3 is connected to the other electrode of the second capacitor and one electrode of SW4. The other electrode of the SW4 is connected to a source electrode of the transistor and one electrode of SW5. The other electrode of the SW5 is connected to the other electrode of the first capacitor, an anode electrode of a load, and one electrode of SW6. The other electrode of the SW6 is connected to a fourth wiring. A drain electrode of the transistor is connected to a second wiring. |
| US09257067B2 |
Light source driving circuit of light emitting semiconductor and backlight module
A light source driving circuit of light emitting semiconductor and a backlight module are provided. The light source driving circuit of light emitting semiconductor includes a driving control circuit and a constant current driving circuit coupled to the driving control circuit for controlling a current flowing through the light emitting semiconductor. When the driving control circuit receives a display-mode-switch signal which has an indication for switching from a present display mode to a new display mode, the driving control circuit controls the constant current driving circuit such that in the process of switching from the present display mode to the new display mode, the current flowing through the light emitting semiconductor changes gradually. |
| US09257064B2 |
Stereoscopic image display
A stereoscopic image display includes a liquid crystal display panel including a plurality of pixels, each of which is divided into a main pixel unit and an switchable black stripe, a data driving circuit, a gate driving circuit, and a 3D control voltage generation circuit, which supplies AC voltages, of which phases are sequentially shifted, to a plurality of 3D control lines in a 3D mode. |
| US09257062B2 |
Transportable sign
A transportable sign (1) is provided which comprises a base portion (3), a support portion (5), and a display portion (7), In the sign, the display portion comprises a carrier (9) configured to carry a display medium (11) to display an image (13), e.g. a board, a cloth or a sail etc. The base portion is configured to position the sign supporting the support portion and the display portion, and the support portion is configured to support the display portion, when mounted to or on the base portion. In the sign, the display portion is mounted or mountable to the support portion to form a transformable assembly such that, when mounted to the base portion, the display portion is positionable in and movable between at least a first, relatively high, position and a second, relatively low, position with respect to the base portion. |
| US09257060B2 |
Fixed window badge
A badge for displaying indicia. The badge includes a base plate that defines a landing area that has a recessed portion. The badge also includes a top panel coupled to the base plate. The top panel defines an at least partially transparent portion. A strip is removably disposed between the base plate and the top panel and at least partially disposed underneath the at least partially transparent portion such that a portion of the strip is viewable through the at least partially transparent portion. |
| US09257052B2 |
Evaluating candidate answers to questions in a target knowledge domain
Evaluating candidate answers to questions in a target knowledge domain, including: identifying, by a question answering module, a plurality of evidence items in the target knowledge domain; identifying, by the question answering module, a plurality of answers to questions in the target knowledge domain; determining, by the question answering module, associations between each evidence item and one or more of the answers; receiving, by the question answering module, a question; receiving, by the question answering module, values for the one or more evidence items; and providing, by the question answering module, an answer to the question in dependence upon the associations between each evidence item and one or more of the answers and the values for the one or more evidence items. |
| US09257051B2 |
Aircraft avoidance method and drone provided with a system for implementing said method
A method enabling an aerial drone not having a TCAS system to avoid an intruder aircraft, the method including the steps of acquiring the position of the intruder aircraft in order to determine the distance between the aerial drone and the intruder aircraft, measuring the angular speed of the intruder aircraft in a horizontal plane, and determining whether the intruder aircraft is fitted with a TCAS system, and, if so, receiving a resolution advisory transmitted by the TCAS of the intruder aircraft and following a previously-determined avoidance path. The invention also provides a drone fitted with a system implementing the method. |
| US09257050B2 |
Airplane position assurance monitor
An onboard monitor that ensures the accuracy of data representing the calculated position of an airplane during final approach to a runway. This airplane position assurance monitor is a software function that uses dissimilar sources of airplane position and runway data to ensure the accuracy of the respective data from those dissimilar sources. ILS data and GPS or GPS/Baro data are the dissimilar sources of airplane position data used by this function. This function will calculate the airplane's angular deviations from the runway centerline and from the glide slope with onboard equipment and then compare those angular deviations to the ILS angular deviation information. |
| US09257048B1 |
Aircraft emergency landing route system
A method and apparatus for managing a landing site for an aircraft is presented. The landing site is selected from a group of landing sites. A description is communicated to a platform about a state of the aircraft along a route of the aircraft over time to the landing site. The aircraft is flown to the landing site using the description of the state of the aircraft along the route of the aircraft over time. |
| US09257043B2 |
Lane correction system, lane correction apparatus and method of correcting lane
The embodiment provides a method of correcting a lane. The method includes receiving first lane information detected by a lane departure warning system; comparing the received first lane information with previously stored second lane information to identify a degree of variation of a lane as a function for time; sensing whether a fault detection of the received first lane information exists according to the identified degree of variation of the lane; correcting the received first lane information when the fault detection of the first lane information is sensed; and transmitting the corrected lane information to the lane departure warning system. |
| US09257040B2 |
Method and device for learning and playing back electromagnetic signals
Methods and device for learning electromagnetic signals, saving the signals, and pairing the signals with commands interpreted by a processor. The methods comprise the steps of detecting an electromagnetic signal transmitted from an external device; converting the detected electromagnetic signal into a numerical representation; placing the numerical representation into an array; associating the array with a reference or transforming the array with an algorithm and adding the reference or transformation into a memory table; and associating the reference or transformation with a computer command or combination of computer commands and adding the associated computer command or combination of commands into the memory table. |
| US09257037B2 |
System and method for automatically setting up a universal remote control
A system and method for configuring a remote control to command the operation of appliances, to capture demographic data, and to provide services, such as automated warranty registration, instructions, viewing guides, etc., relevant to the appliances is provided. The system includes a database and associated server that are located remotely from the remote control and accessible via a network connection. Command codes, graphical user interface elements, and services are accessed and downloaded to the remote control, as appropriate, using data supplied to the server that identifies the appliances and/or functional capabilities of the appliances. This data can be supplied by the appliances directly or can be obtained from other sources such as barcode labels, network devices, etc. |
| US09257034B2 |
Systems, methods and apparatus for providing an audio indicator via a remote control
Apparatus, systems and methods are described for outputting audible or visual indicators via a remote control for a controlled device. A remote control queries an associated controlled device for information. The controlled device generates a request for the remote control to activate an audio or visual indicator. The request is integrated with a response to the query that is transmitted to the remote control. The remote control outputs an audio or visual indicator responsive to the request. |
| US09257032B2 |
System and method for emergency communication in a TCP/IP based redundant fire panel network
A system and method for providing emergency alarm communications in an fire panel network having a ring topology. The fire panels of the network each include an emergency interface between a panel processor and a panel transceiver. The emergency interface includes a communication link that is different from a normal TCP/IP communication link of the associated panel. The emergency interface comprises a separate communication path from the normal communication link. When normal TCP/IP communications are interrupted, the emergency interface is operable to transmit alarm signals to an adjacent panel in the network. The alarm signals may then be transmitted between subsequently connected panels and a workstation or central monitoring station via the normal TCP/IP mode. The workstation and/or central monitoring station can recognize the alarm signals as being generated by the originating panel. Other embodiments are disclosed and claimed. |
| US09257031B2 |
Method and device for detecting crack formation in a hoisting member
The invention relates to a method for detecting crack formation in a hoisting member, comprising the steps of measuring a stress under load at two points of the hoisting member, comparing the measured stresses and generating a warning signal when the measured stresses differ too much from each other.The invention also relates to a device for detecting crack formation in a hoisting member, comprising means arranged at two points of the hoisting member for measuring a stress under load, means connected to the measuring means for comparing the measured stresses, and means connected to the comparing means for generating a warning signal when the measured stresses differ too much from each other.Finally, the invention relates to a hoisting frame, comprising a number of hoisting members which are mounted thereon close to its corners, and crack detection devices connected thereto. |
| US09257028B2 |
Dual-network locator and communication system for emergency services personnel
A communications system is provided for emergency services personnel that includes a plurality of portable devices and a base station. The portable devices are configured to be carried by emergency services personnel while at an emergency site. The portable devices each have a first transceiver configured to communicate over a first network and a second transceiver configured to communicate over a second network, where the first and second networks operate independent of one another. For example, they may have at least one of different first and second carrier frequencies, protocol, channels and the like. The base station has at least one transceiver for communicating with the portable devices over at least one of the first and second networks. Optionally, the first and second networks may have different transmission characteristics, such as different transmit ranges, power levels and the like. |
| US09257027B2 |
Duct detector
There is described a duct detector and components for duct detectors. In one form the duct detector includes: a port unit and detector unit. The port unit is mountable to a duct in use so as to position one or more ports in the duct. The detector unit includes a detection region. The port unit and detector unit are reconfigurable between a close coupled configuration and a separated configuration in which the units are mountable with a variable separation between them and coupled by one or more elongate conduits to provide fluid communication between the units. |
| US09257023B2 |
Media device and control method thereof
A media device connected to an external device and a control method thereof are provided. The media device includes a display unit configured to output a plan view denoting a structure of a building, a signal input/output unit configured to, when emergency occurs, receive information regarding a location in which emergency has occurred from a management center, and a controller configured to classify a plurality of emergency exits disposed in the building into available emergency exits and unavailable emergency exits by using the location information, map a fire escape route leading to an emergency exit closest to the location in which the media device is installed, among the available emergency exits. |
| US09257018B2 |
Point-of-sale system
A point-of-sale system includes a stand that supports a tablet computer. The tablet computer can run a merchant application to provide the typical functionality for a point-of-sale system. The stand can be rotatable to face either the merchant or the customer. The stand can incorporate a card reader. The tablet computer can be connected through a hub to other peripheral components, such as a controllable cash drawer, a printer and/or a bar code reader. The cash drawer can include a slidable drawer having sliding rails that are hidden from a top view of the drawer. |
| US09257011B2 |
Gaming machine capable of realistically informing of a payout rate
The present invention provides a gaming machine that is capable of realizing an attractive payout rate for a player. The gaming machine is adapted to suggest that a state advantageous to a player be established, by shielding a symbol that is scrolled and then displaying a shade of a specific character. In this manner, the player can play a game with a sense of expectation. After the shading has been released, a specific symbol is displayed, thereby establishing the state advantageous to the player. Therefore, the player can realize that the routine migrates to the state advantageous to the player. |
| US09257002B2 |
Gaming machine with common game featuring 3D effects
A plurality of gaming terminals 10, a terminal image display panel 16 and an upper display 700 which display effect images in accordance with the gaming state of a game on the gaming terminals 10 and display at least one of the effect images in three dimensions, a terminal controller 630, which switches at least one of the effect images on the terminal image display panel 16 and the upper display 700 from two dimensional display to three dimensional display when the gaming state satisfies a predetermined condition, and a center controller 200. |
| US09257001B2 |
Integrated gaming and services system and method
An integrated gaming and services system is disclosed. The system includes a gaming terminal and a server system. The gaming terminal may include a reader system connected to the gaming terminal, the reader system configured to read identification information of a player. The gaming terminal may further include an input/output system including one or more input components that permit a player to input at least voice commands to the gaming terminal, and one or more output components that output gaming and services information to the player in response to the voice commands. The gaming terminal may additionally include a communication interface connecting the gaming terminal to a communication network. The server system communicates with the gaming terminal via the communication interface, and provides enhanced services to the player based at least on the identification information of the player. |
| US09256998B2 |
Banknote handling machine
A banknote handling machine according to the present invention efficiently utilizes stacking units so as to efficiently process banknotes by returning odd banknotes of a first predetermined type in every transaction whereas keeping odd banknotes of a second predetermined type in a stacking unit, and performing subsequent transaction when banknote processing including depositing, taking-in, recognizing, sorting/stacking, and bundling of banknotes and confirming the deposit amount for one transaction is sequentially performed for a plurality of transactions. |
| US09256993B2 |
Electronic control apparatus
An electronic control apparatus includes a vehicle state storing processing part, which stores a vehicle state data when a predetermined trigger is generated, and a trigger setting processing part, which sets the trigger in correspondence to a designation from an external side. The electronic control apparatus further includes a data type setting part for setting, based on the designation from the external side, a stored vehicle state data type. The vehicle data storing part stores the vehicle state data in different addresses. The trigger setting part sets the trigger based on the address designated from the external side and a data length of the vehicle state data stored in the address. The data type setting part sets the stored vehicle state data type based on the address designated from the external side and the data length of the vehicle state data stored in the address. |
| US09256987B2 |
Tracking head movement when wearing mobile device
Methods for tracking the head position of an end user of a head-mounted display device (HMD) relative to the HMD are described. In some embodiments, the HMD may determine an initial head tracking vector associated with an initial head position of the end user relative to the HMD, determine one or more head tracking vectors corresponding with one or more subsequent head positions of the end user relative to the HMD, track head movements of the end user over time based on the initial head tracking vector and the one or more head tracking vectors, and adjust positions of virtual objects displayed to the end user based on the head movements. In some embodiments, the resolution and/or number of virtual objects generated and displayed to the end user may be modified based on a degree of head movement of the end user relative to the HMD. |
| US09256986B2 |
Automated guidance when taking a photograph, using virtual objects overlaid on an image
There is provided an image processing device including a data acquisition unit configured to acquire a recommended angle-of-view parameter that represents a recommended angle of view for a subject in an environment that appears in an image, and a display control unit configured to overlay on the image a virtual object that guides a user so that an angle of view for capturing an image of the subject becomes closer to the recommended angle of view, using the recommended angle-of-view parameter. The recommended angle-of-view parameter is a parameter that represents a three-dimensional position and attitude of a device that captures an image of the subject at the recommended angle of view. |
| US09256983B2 |
On demand image overlay
In one embodiment, a building model is presented to a user. The building model may be a three-dimensional rendering of a geographic region. A user selects a point on the three-dimensional rendering of a geographic region. Based on the selected point one or more image bubbles are chosen. The image bubbles are photographs or similar image data. The image bubbles and the three-dimensional rendering are associated with the same geographical space. The one or more image bubbles are incorporated with the building model such that at least a portion of one of the image bubbles is displayed in a window with the building model. |
| US09256980B2 |
Interpolating oriented disks in 3D space for constructing high fidelity geometric proxies from point clouds
An “Oriented Disk Interpolator” provides various techniques for interpolating between points in a point cloud using RGB images (or images in other color spaces) to produce a smooth implicit surface representation that can then be digitally sampled for ray-tracing or meshing to create a high fidelity geometric proxy from the point cloud. More specifically, the Oriented Disk Interpolator uses image color-based consistency to build an implicit surface from oriented points and images of the scene by interpolating disks in 3D space relative to a point cloud of a scene or objects within the scene. The resulting implicit surface is then available for a number of uses, including, but not limited to, constructing a high fidelity geometric proxy. |
| US09256972B2 |
Fast high-fidelity flood-filling on vector artwork
Techniques are disclosed for performing flood-fill operations on vector artwork. In one embodiment, a region under a point of interest (POI) of vector artwork is rasterized and flood-filled, and an initial bounding shape around that area is used as a first guess as to the area to be filled. In other cases, the initial bounding shape is created around some initial area that includes the POI (no rasterization). In any such case, vector objects having bounding shapes that intersect the initial bounding shape are identified and fed into a planar map. After map planarization, a new bounding shape is created around a new area resulting from the planarizing and that includes the POI. In response to that bounding shape not extending beyond the initial bounding shape, a vector-based flood-fill operation can be performed on that new area. Process repeats if new bounding shape extends beyond previous bounding shape. |
| US09256967B2 |
Systems and methods for partial volume correction in PET penalized-likelihood image reconstruction
A computer-implemented method for partial volume correction in Positron Emission Tomography (PET) image reconstruction includes receiving emission data related to an activity distribution, reconstructing the activity distribution from the emission data by maximizing a penalized-likelihood objective function to produce a reconstructed PET image, quantifying an activity concentration in a region of interest of the reconstructed PET image to produce an uncorrected quantitation, and correcting the uncorrected quantitation based on a pre-calculated contrast recovery coefficient value to account for a partial volume error in the uncorrected quantitation. |
| US09256961B2 |
Alternate viewpoint image enhancement
In one embodiment, panoramic images, images bubbles, or any two-dimensional views of three-dimensional subject matter are enhanced with one or more alternate viewpoints. A controller receives data indicative of a point on the two-dimensional perspective and accesses a three-dimensional location based on the point. The controller selects an image bubble based on the three-dimensional location. The three-dimensional location may be determined according to a depth map corresponding to the point. A portion of the image bubble is extracted and incorporated into the two-dimensional perspective. The resulting image may be a seamless enhanced resolution image or include a picture-in-picture enhanced resolution window including subject matter surrounding the selected point. |
| US09256960B2 |
Image coding method and image decoding method
An image decoding method includes: arithmetic decoding steps for performing arithmetic decoding processes on decoding target signals according to contexts determined based on the types of the decoding target signals and the symbol occurrence probabilities determined based on the contexts; and a context update step for executing a group of context update processes on the decoding target signals in each of processing units each obtained as a segment having a certain size, according to the decoded signals resulting from the arithmetic decoding processes. |
| US09256956B2 |
Dataset creation for tracking targets with dynamically changing portions
A mobile platform visually detects and/or tracks a target that includes a dynamically changing portion, or otherwise undesirable portion, using a feature dataset for the target that excludes the undesirable portion. The feature dataset is created by providing an image of the target and identifying the undesirable portion of the target. The identification of the undesirable portion may be automatic or by user selection. An image mask is generated for the undesirable portion. The image mask is used to exclude the undesirable portion in the creation of the feature dataset for the target. For example, the image mask may be overlaid on the image and features are extracted only from unmasked areas of the image of the target. Alternatively, features may be extracted from all areas of the image and the image mask used to remove features extracted from the undesirable portion. |
| US09256952B2 |
Vehicle speed calculator, and vehicle including same
A vehicle speed calculator includes a vehicle speed calculation unit for calculating a vehicle speed from a traveled distance per unit time of a feature point in a captured image shot by a camera for capturing a road surface, a reference distance mark irradiation unit and an image reference distance detection unit. The reference distance mark irradiation unit irradiates a reference distance mark to the road surface in parallel with an optical axis of the camera. The reference distance mark is formed in such a manner as to have a reference distance in a longitudinal direction of a motorcycle. The image reference distance detection unit detects an image reference distance, the longitudinal length of the reference distance mark in the shot image. The vehicle speed calculation unit calculates the vehicle speed from the traveled distance using the image reference distance and the reference distance. |
| US09256950B1 |
Detecting and modifying facial features of persons in images
Implementations relate to detecting and modifying facial features of persons in images. In some implementations, a method includes receiving one or more general color models of color distribution for a facial feature of persons depicted in training images. The method obtains an input image, and determines a feature mask associated with the facial feature for one or more faces in the input image. Determining the mask includes estimating one or more local color models for each of the faces in the input image based on the general color models, and iteratively refining the estimated local color models based on the general color models. The refined local color models are used in the determination of the feature mask. The method applies a modification to the facial feature of faces in the input image using the feature mask. |
| US09256947B2 |
Automatic positioning of imaging plane in ultrasonic imaging
The invention is directed to a method for ultrasonic imaging, in which two-dimensional images (10, 11) are acquired, one of which is aligned with a longitudinal direction of an interventional object (e.g. a needle) (13) to be moved towards a target area (7) within a subject of examination and the other one is intersecting the longitudinal direction of the interventional object (13) and automatically positioned dependent on the automatically determined position and orientation of the interventional object (13). Further, the invention is directed to an ultrasonic imaging device (1) adapted to conduct such a method. |
| US09256946B2 |
Accuracy compensation method, system, and device
A method for applying accuracy compensation to a computer numerically controlled (CNC) machine can compensate control program that controls the CNC machine. The method recognizes an actual outline of the product using an image of product produced by the CNC machine controlled by the control program, and further obtains an ideal outline of the product. The method obtains compensation values by computing coordinate differences between points of the actual outline and points on the ideal outline, and compensates the control program using the compensation values. |
| US09256945B2 |
System for tracking a moving object, and a method and a non-transitory computer readable medium thereof
According to one embodiment, a plurality of moving objects is detected from a plurality of frames acquired in time series. Each of the moving objects is corresponded among the frames. A tracklet of each moving object corresponded is extracted and stored. A frame to calculate a position of a moving object is set to a notice frame. The frames are grouped into a first block including at least the notice frame, a second block positioned before the first block in time series, and a third block positioned after the first block in time series. A secondary tracklet included in the second block is acquired from the stored tracklets. The secondary tracklet is corresponded with tracklets included in the first block and the third block, based on a similarity between the secondary tracklet and each of the tracklets. The secondary tracklet is associated with the corresponded tracklets, as a tertiary tracklet. |
| US09256943B2 |
Projector-camera misalignment correction for structured light systems
A method of misalignment correction in a structured light device is provided that includes extracting features from a first captured image of a scene, wherein the first captured image is captured by an imaging sensor component of the structured light device, and wherein the first captured image includes a pattern projected into the scene by a projector component of the structured light device, matching the features of the first captured image to predetermined features of a pattern image corresponding to the projected pattern to generate a dataset of matching features, determining values of alignment correction parameters of an image alignment transformation model using the dataset of matching features, and applying the image alignment transformation model to a second captured image using the determined alignment correction parameter values. |
| US09256938B2 |
Characteristic X-ray escape correction in photon-counting detectors
A method and an apparatus for determining primary and secondary escape probabilities for a large photon-counting detector without pile-up. A model for the detector with no pile-up is formulated and used for spectrum correction in a computed tomography scanner. The method includes computing primary K-escape and secondary K-escape probabilities occurring at a certain depth within the photon-counting detector. Further, a no pile-up model for the photon-counting detector is formulated by determining a response function, based on the computed primary and secondary K-escape probabilities and geometry of the photon-counting detector. The method includes obtaining a measured CT scan of an object and further performs spectrum correction by determining the incident input spectrum based on the response function and the measured spectrum of the large photon-counting detector. |
| US09256934B2 |
Enhanced image reconstruction in photoacoustic tomography
Various embodiments of methods and systems are provided for image reconstruction in photoacoustic tomography. In one embodiment, among others, a method includes obtaining photoacoustic time-domain data; reconstructing an image from the photoacoustic time-domain data using total-variation minimization based photoacoustic tomography reconstruction; and providing the reconstructed image for rendering on a display device. In another embodiment, a system includes a computing device and an image reconstruction program executable in the computing device. The image reconstruction program includes logic that obtains photoacoustic time-domain data; logic that reconstructs an image from the photoacoustic time-domain data using total-variation minimization based photoacoustic tomography reconstruction; and logic that provides the reconstructed image for rendering on a display device. |
| US09256931B2 |
Method for inspecting at least one copy of a printed product
A method is used for inspecting at least one copy of a printed product. At least one element, which is spatially constant with respect to a fixed reference point and at least one element which is spatially variant with respect to the same fixed reference point are reliably inspected by reference image data being used for a desired-actual value comparison of the at least one spatially variant element. The reference image data takes account of the variable position of the at least one element; i.e. the spatial variance thereof. |
| US09256930B2 |
X-ray inspection method and device
A first X-ray image is obtained by imaging a target in a first direction and at a first elevation angle, and a second X-ray image is obtained by imaging the target in a second direction and at a second elevation angle. Based on these two X-ray images, cross-section data of the target is obtained. The first and second X-ray images are converted into first and second thickness data, and first cross-section data based on a first surface side of the target and second cross-section data based on a second surface side of the target are obtained based on the first thickness data. Similar third cross-section data and four cross-section data are obtained based on the second thickness data. The cross-section data of the target is obtained by partially extracting and synthesizing cross-section data of a highly reliable region from these pieces of cross-section data. |
| US09256926B2 |
Use of inpainting techniques for image correction
A method of processing an image signal comprising image and depth information is provided. The method is configured to perform segmentation on an image based on depth/disparity information present in the image signal comprising said image, and subsequently inpaint background for correction of the errors in the image around the foreground objects into a region that extends beyond the segment boundary of the foreground object and/or inpaint foreground for correction of errors in the image into a region that extends inside the segment boundary of the foreground object. In this way compression and other artifacts may be reduced. |
| US09256923B2 |
Image processing apparatus, image processing method, and program
An image processing apparatus includes: a representative value calculation unit that selects a designation area from a first image, and that calculates a representative value of each of the color components in the designation area, a class classification unit that performs class classification on the designation area, a coefficient reading unit that reads a coefficient that is stored in advance, a color component conversion unit that sets the pixel value relating to a predetermined pixel within the designation area to be a prediction tap, sets the pixel value of one color component, to be a reference, and converts the pixel value of each color component into a conversion value, and a product and sum calculation unit that sets the conversion value to be a variable and calculates each of the pixel values of a second image, by performing product and sum calculation which uses the coefficient which is read. |
| US09256922B2 |
Applying super resolution for quality improvement of OCR processing
Systems and methods for improving the quality of recognition of the object based on a series of frame images of objects are described herein. A plurality of images depicting the same object are received. A first image is selected from the plurality of images. The first image may be an image with the highest quality from plurality of images. For each image in the plurality of images, motion estimation of elements of an image in the plurality of images and the first image is performed. Based on the results of motion estimation, motion compensation and signal accumulation of the object in the images in the plurality of images using the first image are performed. A high resolution image of the object obtained based on the motion compensation and signal accumulation is generated. Character recognition on the resulting high resolution image is performed. |
| US09256919B2 |
Systems and methods for image processing using a resizing template
Disclosed are various embodiments for systems and methods for image processing. A resizing template may be generated having one or more image sizes of an original image based at least in part on resize settings. A preview may then be generated of preview images of the original image based at least in part on the resizing template and the resize settings. The resize settings may be further adjusted via the preview. Upon approval of the preview and the adjusted resize settings, the original image is processed to generate final resized images according to the template and the modified resize settings. |
| US09256916B2 |
Image processing method and apparatus and program
An image processing method for registering first and second images including the same subject is provided. The method includes the repeating the following steps multiple times: a first step including determining feature vectors related to gradients of pixels values at coordinates on the first and second images for each of the coordinates, a second step including calculating for all mutually corresponding coordinates on the first and second images, correlation values each equivalent to a value obtained by an N-th (where N is a natural number) power of an absolute value of an inner product of the feature vectors at the coordinates and determining an evaluation value including an integrated value of the correlation values calculated for each of the coordinates, and a third step including changing the second image in such that the evaluation value becomes larger. |
| US09256910B2 |
Medical monitoring/consumables tracking device
The present invention generally provides medical monitoring devices, and corresponding systems, that includes at least one sensor for detecting usage of at least one consumable, an electronic controller electrically connected to the sensor to receive a signal therefrom produced when consumable usage is detected, and an electronic memory electrically connected to the controller for storing consumable usage data thereon. The medical monitoring device may further include at least one sensor for determining one or more physiological parameter of a subject and a display device for displaying the physiological parameter. The medical monitoring device may also include a communications unit for communicating stored data, such as usage and physiological parameter data, over a communication network to a remote computer. |
| US09256898B2 |
Managing shared inventory in a virtual universe
Generally speaking, systems, methods and media for managing shared inventory in a virtual universe are disclosed. Embodiments of the method may include receiving notification of a user session being established between a user and a virtual universe simulator. The method may also include accessing a list of shared inventory items for the user where the list of shared inventory items includes one or more shared inventory items each having an inventory source associated with it. Embodiments may also include retrieving at least one shared inventory item from its associated inventory source and passing the retrieved shared inventory item to the virtual universe simulator. Further embodiments may include retrieving an updated listing for the shared inventory items from their associated inventory sources and passing the updated shared inventory item list to the virtual universe simulator. Further embodiments may include passing metadata for shared inventory items to the virtual universe simulator. |
| US09256892B2 |
Content selection using performance metrics
Methods, systems, and apparatus, including computer programs encoded on a computer program product, for selecting advertisements. In one aspect, a method includes receiving publisher selections of advertisements; associating the selected advertisements with an advertisement environment in a document; generating an advertisement request code for inclusion in the document; evaluating performance metrics for the selected advertisements; and in response to determining that the selected advertisements do not meet the performance threshold, optimizing the selection of selected advertisements based on the performance metrics; substituting a selected advertisement with a candidate advertisement and causing a client device to render the candidate advertisement in the advertisement environment in the document. |
| US09256884B2 |
System and method to increase efficiency and speed of analytics report generation in audience measurement systems
A method of generating television Audience Measurement System (AMS) reports and a system executing the method are disclosed. The method comprises the steps of receiving a plurality of encoded report payloads from a plurality of client devices, storing the encoded report payloads in a database, transferring at least one encoded report payload from the database into randomly addressable memory (RAM), decoding the at least one encoded report payload in RAM, parsing the decoded data in RAM with at least one matching algorithm to determine the occurrence of events, compiling a database of parsed data, and generating an AMS report from the database of parsed data. |
| US09256882B2 |
Methods, communications devices, and computer program products for selecting an advertisement to initiate device-to-device communications
Methods, communications devices, and computer program products for selecting an advertisement to initiate communications between communication devices using an Internet protocol enabled television infrastructure are provided. Input of a call back number is received. Advertisement data of an enterprise is accessed via an Internet protocol enabled device. A selection is received to initiate a communication to the enterprise. A selection of the call back number is received. The call back number is contacted, in response to an indication that the enterprise has been contacted for initiation of the communication. |
| US09256876B2 |
Real-time spend management with savings goals
A computer-implemented method, including receiving, by one or more computer systems, a withdrawal request for withdrawal of funds from one or more financial accounts; determining, by the one or more computer systems, whether a discretionary balance of the one or more financial accounts is greater than or equal to an amount of the withdrawal request, with the discretionary balance being based on an amount of funds that are available in the one or more financial accounts and a portion of the available funds allocated to a savings goal; causing an approval of the withdrawal request when the discretionary balance is greater than or equal to the amount of the withdrawal request; and sending a real time notification to a client device of a user associated with the one or more financial accounts when the discretionary balance is less than the amount of the withdrawal request with a real time opportunity for the user to reduce funds allocated to savings goals if required and thereby increasing the discretionary balance to facilitate the approval of withdrawal request. |
| US09256874B2 |
Method and system for enabling merchants to share tokens
One embodiment of the present disclosure provides a system and associated processes for sharing cardholder data (CHD) between a merchant that utilizes tokenization and a second merchant that may or may not utilize tokenization. In one embodiment, the merchant, or an employee of the merchant, can use the system and associated processes to reacquire CHD from a tokenization provider system. In one embodiment, the merchant identifies to the tokenization provider system a desire to share CHD, which is associated with a token, with a second merchant. The merchant and/or the tokenization provider system can then invite the second merchant to register with the tokenization provider system. Once registered with the tokenization provider system, the second merchant can access any CHD that the merchant associated with the second merchant. |
| US09256873B2 |
Method and device for retrofitting an offline-payment operated machine to accept electronic payments
A payment module includes: one or more processors, memory, a first interface module configured to couple the payment module with a control unit of an offline-payment operated machine, and a short-range communication capability for communicating with one or more mobile devices each including a complimentary short-range communication capability and a long-range communication capability. The payment module receives a transaction request via the short-range communication capability from a mobile device to perform a transaction with the offline-payment operated machine. The payment module validates the transaction request to verify that the mobile device is authorized to initiate payment for the transaction by a remote server via the long-range communication capability. In accordance with a determination that the transaction request is valid, the payment module causes the offline-payment operated machine to perform the requested transaction by issuing a signal, via the first interface module, to the control unit to perform the transaction. |
| US09256869B2 |
Authentication and verification services for third party vendors using mobile devices
A method to provide authentication services to third party vendors by a service provider hosting an authentication, authorization and accounting (AAA) server or a similar device that can authenticate users for some other service. This method enables easy and substantially error-free end-user authentication, which forms the basis for enabling electronic transactions (e.g., web-based) that are less vulnerable to fraud. |
| US09256866B2 |
Drivers license look-up
A method for enabling a driver's license to be used as a credit account, including: accessing data from a scanned bar code of a driver's license; comparing the accessed data from the scanned bar code to a store of information comprising a stored set of profile information; based on the comparing, determining if a match between the accessed data and a stored set of profile information exists, and identifying a matched stored set of profile information; identifying a customer credit account, of the customer credit account information, linked to the matched stored set of profile information; generating an credit verification for the customer, such that, as to the customer, a particular transactional activity is allowed to be processed using the identified customer credit account. |
| US09256860B2 |
Tracking participation in a shared media session
A method for tracking user participation in a shared media session. A shared media session is connected to, where the shared media session includes a plurality of participants. A first identity is determined for a first participant with a first confidence level. The first participant is identified as the first identity if the first confidence level is above a first threshold. An amount of participation is tracked for the first identity. The amount of participation by the first identity is displayed on an electronic calendar for the shared media session to the plurality of participants. |
| US09256859B2 |
Systems and methods for fragmenting newsfeed objects
A technique allows a newsfeed item shown in a newsfeed of a social network to be easily promoted to another newsfeed in the social network. In a specific embodiment, the system receives a first user's promotion selection of an item displayed in a newsfeed of the first user. The item includes content provided by a second user. The first user is prompted to select a destination newsfeed. A selection of the destination newsfeed is received and the item is published on the destination newsfeed for a third user. |
| US09256855B2 |
System and method for providing a referral network in a social networking environment
A user-content generated network is provided for presenting business listings, as well as commentary and reviews of businesses, by participants of the network. In an embodiment, businesses can participate in the network and receive referrals from members of the network. The network can track and monitor referrals that individual businesses receive as a mechanism for promoting the business to other users in the network's user base. |
| US09256852B1 |
Autonomous delivery platform
Package delivery platform. An autonomous road vehicle is operative to receive destination information, and to drive to a destination based on the destination information. A package securing subsystem is attached to the autonomous road vehicle and comprises at least one securable compartment. Each securable compartment is operative to secure at least one package therein. Each securable compartment is associated with compartment access information. An access subsystem comprising at least one access information interface. The access subsystem is operative, upon receipt through the access information interface of compartment access information, to permit access to the compartment associated with the received compartment access information. |
| US09256849B2 |
Apparatus and methods for evaluating a quality of a locate operation for underground utility
Methods and apparatus to evaluate a quality of a locate operation performed at a work site of proposed excavation following issuance of the instruction to a field-service technician. An input/output (I/O) interface receives an electronic manifest of the locate operation. The electronic manifest includes geographic information indicating a first location at which the electronic manifest was created. A distance is determined between the first location and a second location at which the locate operation was requested to be performed. One or more indications of a quality assessment of the locate operation are generated based on whether the distance is within or equal to a predefined range. |
| US09256848B2 |
Systems and methods for identifying and delivering tailored content based upon a service dialog
The present disclosure identifies and/or delivers tailored content based upon a service dialog. For example, the systems may receive a request for tailored content, facilitate a service dialog to obtain information related to the request, and communicate a plurality of tailored content based upon the information related to the request. Further, the systems may identify tailored content based upon a consumer profile, communicate the tailored content to a web client, and/or receive a selection of the tailored content. Further still, the systems may modify a magazine (e.g., content that is presented electronically) based upon tailored content. |
| US09256845B2 |
Icafépre-ordering
Technology for pre-ordering (e.g., pre-fetching content) at a shared computing premise is described. The technology can enable a user to locate and reserve an available seat at a shared computing premise (e.g., an iCafé). A service can transmit to the user a list of nearby iCafés or available seats that is ranked or ordered based on various criteria. The selected iCafé may pre-fetch content. The iCafé may also provide the pre-fetched content on removable media so that the user does not need to view all the pre-fetched content only at the iCafé. The iCafé may provide a search and/or document notification service and perform searches, download documents, and check for changes to specified documents even when the user is not logged on or using a computer at the iCafé. After the documents are retrieved and stored, the iCafé may send a notification to the user. |
| US09256843B1 |
System for situational awareness and method implementing the same
A system for implementing a situational awareness includes a plurality of data gathering devices for observing the physical environment and transforming observations of physical phenomena into digital information; a plurality of field monitoring units with each of the plurality of units communicating with a corresponding plurality of data gathering devices to obtain data therefrom; and an aggregate monitoring unit communicating with each of the plurality of field monitoring units to monitor and control each of the plurality of field monitoring units and collect and store data from the plurality of data gathering devices. |
| US09256836B2 |
Reconfigurable model for auto-classification system and method
A reconfigurable automatic document-classification system and method provides classification metrics to a user and enables the user to reconfigure the classification model. The user can refine the classification model by adding or removing exemplars, creating, editing or deleting rules, or performing other such adjustments to the classification model. This technology enhances the overall transparency and defensibility of the auto-classification process. |
| US09256834B2 |
Quantum computers having partial interferometric quantum gates
A quantum computer may include topologically protected quantum gates and non-protected quantum gates, which may be applied to topological qubits. The non-protected quantum gates may be implemented with a partial interferometric device. The partial interferometric device may include a Fabry-Pérot double point contact interferometer configured to apply “partial” interferometry to a topological qubit. |
| US09256832B2 |
Inference pipeline system and method
A system to infer place data is disclosed that receives location data collected on a user's mobile electronic device, recognizes when, where and for how long the user makes stops, generates possible places visited, and predicts the likelihood of a user to visit those places. |
| US09256827B2 |
Portable data management using rule definitions
Embodiments for methods, systems, and computer program products for creating and managing a portable data rule using an electronic computing device are presented including: causing the electronic computing device to create a rule definition including, defining an expression by a user, where the expression defines a logic of a rule, causing the electronic computing device to parse the expression into a logical variable associated with the expression, causing the electronic computing device to identify the logical variable, and causing the electronic computing device to store the rule definition, where the rule definition includes the expression and the logical variable. In some embodiments, the causing the electronic computing device to identify the logical variable includes: causing the electronic computing device to return a name of the logical variable; and causing the electronic computing device to return an expected type of the logical variable. |
| US09256825B2 |
Emotion script generating, experiencing, and emotion interaction
An emotion script generating method includes receiving a user's emotion data, and generating emotion script using the emotion data based on a predefined template. |
| US09256820B2 |
Data transfer system and associated management method
A method for managing a data transfer system includes recovering energy at peripheral devices, and wireless transfer recovered energy to a base by synchronizing RF signals transmitted by double-loop antennas. Synchronizing includes implementing a listening phase to detect a radio-frequency signal transmitted by said central base, and either sending an RF signal that is synchronous with the detected signal or transmitting a signal at a predetermined frequency depending on whether an RF signal is detected at the base. The method includes, in response to receiving a signal from the peripheral device at that frequency, causing the base to recover the received signal and to re-transmit at the predetermined frequency to the peripheral devices. This signal synchronization enables simultaneous energy transfer from peripheral devices to the central base while avoiding mutually destructive effects between said signals. |
| US09256809B2 |
Enabling an authentication device with temporary target
A method of enabling an authentication device includes providing a first enabling target. One or more attributes of the first enabling target is measured with the authentication device at a first time and compared to a first predetermined expected value. When the at least one measured attribute of the first enabling target matches the first predetermined expected value, the authentication device is enabled for only a first predetermined enablement time. |