最新美国发明专利
Document Document Title
US09246662B2 Mechanisms addressing dynamic component carrier change in relay systems
The present invention proposes methods and devices to further improve relay systems operating on the basis of carrier aggregation on the access as well as on the backhaul link. Under an aspect of such approach, there is proposed a relay node as a device, comprising a transceiver device, configured to communicate via a first interface with a terminal and via a second interface with a remote network device, wherein communication via the first and/or second interface is configured to operate based on aggregation of plural individual component carriers, and a control device, configured to perform, per component carrier: detection of a change concerning a component carrier on the first interface, sending, responsive thereto, of update information pertaining to at least the first interface towards the remote network device, reception of reconfiguration instructions, implied by the detected change, to be applied on the first interface, and initiation of reconfiguration of the first interface based on the received instructions. Similar approach is applied to a donor eNB as well as to corresponding methods and computer program products.
US09246661B2 Control apparatus, base station, and terminal
A control apparatus in a communication system including a base station and terminals, the control apparatus including: a memory, and a processor coupled the memory and configured to receive data addressed to M terminals (where M is a natural number equal to or greater than 2) of the terminals, and to transmit the received data to the base station, such that N terminals (where N is a natural number less than M) of the M terminals are scheduled in the same timing by the base station.
US09246657B2 Wireless communication base station equipment, wireless communication terminal device and search space setting method
Disclosed is wireless communication base station equipment in which CCE allocation can be flexibly performed without collision of ACK/NACK signals between a plurality of unit bands, even when wideband transmission is performed exclusively on a downlink circuit. In this equipment, an allocation unit (105) sets up mutually different search spaces for each of a plurality of downlink unit bands, with respect to wireless communication terminal devices that communicate using a plurality of downlink unit bands, and allocates resource allocation information of downlink circuit data destined for the wireless communication terminal devices to CCEs in mutually different search spaces for each of the plurality of downlink unit bands, and an ACK/NACK reception unit (119); extracts a response signal in respect of the downlink circuit data from the uplink control channel associated with the CCE to which the resource allocation information of this downlink circuit data was allocated.
US09246654B2 Methods and arrangements for transmitting and decoding reference signals
In a radio network node, a reference signal is transmitted over an antenna port, in a code division multiplexing (CDM) group. The CDM group includes CDM subgroups of resource elements, the CDM subgroups being transmitted on different subcarriers. First, the radio network node transmits the reference signal over a first CDM subgroup using an orthogonal cover code (OOC). The first CDM subgroup includes resource elements in a first time slot and a subsequent time slot. Then, the radio network node transmits the reference signal over a second CDM subgroup using a permutation of the OOC. The second CDM subgroup includes resource elements in the first time slot and the second time slot. The permutation of the OOC is selected such that to enable decoding of the reference signal in the frequency domain, by applying the OOC only to resource elements in the CDM group in the first time slot.
US09246653B2 Method for transceiving data in a wireless access system, and base station and terminal for same
Disclosed are a method for transceiving data in a wireless access system, and a base station and terminal therefor. More particularly, the present invention relates to a method for transceiving data, and to a base station device for the method, wherein the method comprises the steps of: transmitting, in a single first subframe, a physical downlink control channel (PDCCH) including downlink scheduling information on each terminal; and transmitting, in a plurality of second subframes, a physical downlink shared channel (PDSCH) relevant to said PDCCH to each terminal. The PDCCH supports a carrier aggregation that includes a field indicating said plurality of second subframes in which said PDSCH is transmitted.
US09246649B2 Using a field format on a communication device
A communication device for transmitting a Very High Throughput Signal Field B (VHT-SIG-B) is described. The communication device includes a processor and instructions stored in memory that is in electronic communication with the processor. The communication device allocates bits for the VHT-SIG-B in a backwards compatible preamble. The communication device additionally applies a pilot mapping for the VHT-SIG-B that is the same as a pilot mapping for the DATA field. The communication device further transmits the VHT-SIG-B.
US09246645B2 Apparatus and method of transmitting reception acknowledgement in wireless communication system
A method and apparatus for transmitting reception acknowledgment for hybrid automatic repeat request (HARQ) in a wireless communication system are provided. A user equipment receives a plurality of downlink resource allocations on a plurality of downlink control channels by using a plurality of downlink carriers, and receives a plurality of downlink transfer blocks on a plurality of downlink shared channels indicated by the plurality of downlink resource allocations. The user equipment determines a plurality of acknowledgment (ACK)/negative acknowledgment (NACK) resource indices based on a plurality of resource indices obtained from downlink resources which use the plurality of downlink control channels. The user equipment transmits ACK/NACK for the plurality of downlink transfer blocks by using ACK/NACK resources indicated by the plurality of ACK/NACK resource indices.
US09246643B2 Method of determining an error rate and a suitable testing device
The invention relates to a method and to a test device (12) which is used to determine an error rate during the transfer of data (1) in a mobile radio system. Said mobile radio system comprises at least one transfer channel, wherein several data partial flows (2.1, 2.2, 2.6) are transferred. The several data partial flows (2.1, 2.2 . . . 2.6) are produced in a signal generator unit (8). A transport format is determined, in an individual manner, for each data partial flow (2.1, 2.2 . . . 2.6). The data partial flows (2.1, 2.2 . . . 2.6) are sent, respectively, to a number of transfer blocks which belong together (5.1, . . . 7.1). A device which is to be tested captures the transfer blocks (5.1, . . . 7.1) of the data partial flows (2.1, 2.2 . . . 2.6) and evaluates them. According to the accuracy of the evaluation, a positive or negative actuation signal (ACK, NACK) is sent back by the device which is to be tested. An error rate of each data partial flow (2.1, 2.2 . . . 2.6) is determined by the test device (12) from the actuation signals (ACK, NACK) which are captured by the test device (12).
US09246638B2 Method and apparatus for polling transmission status in a wireless communications system
When a polling procedure is triggered, the value of the poll sequence number field within a status protocol data unit is always set to be a sequence number of a next protocol data unit to be transmitted for the first time minus 1, regardless of the configured transmission window size so as to avoid unnecessary transmission delay.
US09246633B2 Information additive code generator and decoder for communication systems
An encoder uses an input file of data and a key to produce an output symbol. An output symbol with key I is generated by determining a weight, W(I), for the output symbol to be generated, selecting W(I) of the input symbols associated with the output symbol according to a function of I, and generating the output symbol's value B(I) from a predetermined value function F(I) of the selected W(I) input symbols. An encoder can be called repeatedly to generate multiple output symbols. The output symbols are generally independent of each other, and an unbounded number (subject to the resolution of I) can be generated, if needed. A decoder receives some or all of the output symbols generated. The number of output symbols needed to decode an input file is equal to, or slightly greater than, the number of input symbols comprising the file, assuming that input symbols and output symbols represent the same number of bits of data.
US09246629B2 Systems and methods for radio frequency hopping communications jamming utilizing software defined radio platforms
A dynamically-reconfigurable multiband multiprotocol communications jamming system and method is provided that are particularly suited for the generation of effective radio-frequency waveforms/noise output that successively translates up and down the RF spectrum. The system and method are particularly suited for strategically targeting specific frequencies in order to disrupt a communications network or networks, and can be rapidly deployed via delivery platforms, such as artillery and other projectile mechanisms, remote operated vehicles (unmanned aerial, sea or land systems) or targeted air or land delivery via manned assets or automated or robotic support means, or manual delivery by personnel.
US09246627B2 Joint optimization procedure for routing and wavelength assignment with combined dedicated shared protections in multi-cable multi-fiber optical WDM networks
A joint-optimization method addresses the generalized routing and wavelength assignment problem with variable number of combined 1+1 dedicated and shared connections. The inventive method enables a solution in time that is polynomial of the input size. Thus, the time complexity of the joint-optimization method is significantly less than that of existing methods.
US09246626B2 Network operating system with distributed data architecture
A network operating system NOS for an agile optical network with a plurality of mesh interconnected switching nodes, manages the network using an object-oriented network information model. The model is common to all applications requiring the data stored in the network managed information base. The core model can be expanded for serving specific application areas. The NOS is organized in layers, at the optical module level, connection level and network level. A distributed topology server DTS organizes the physical, logical and topological data defining all network entities as managed objects MO and topology objects TO for constructing a complete network view. The network information model associates a network element NE information model, specified by managed objects MO and a topological information model, specified by topology objects TO. The MOs are abstract specific NE data that define network implementation details and do not include any topological data, while the TOs abstract specific topological data for defining a trail established within the network, and do not include any NE data. The models are associated in a minimal number of points to construct the model of a trial in response to a connection request.
US09246624B1 Low noise optical phase-sensitive amplifier for dual-polarization modulation formats
A method and system for amplifying optical signals includes generating idler signals for input signals using a pump signal at a first non-linear element (NLE). Phase and amplitude regulation is performed using the output from the first NLE. Optical power monitoring of the input signals may be used for power equalization. The phase regulation may use input from a feed forward phase-power monitoring of the output phase-sensitive amplified signal. After phase regulation the phase-sensitive amplified signal is generated at a second NLE using the pump signal. Optical power monitoring of the input signals may be used for power equalization and other control functions to achieve low-noise operation.
US09246623B2 Method and apparatus for routing traffic using asymmetrical optical connections
A method, computer-readable storage device and apparatus for routing traffic in a reconfigurable optical add-drop multiplexer layer of a dense wavelength division multiplexing network are disclosed. For example, the method determines the reconfigurable optical add-drop multiplexer layer has asymmetric traffic, and routes the asymmetric traffic in the reconfigurable optical add-drop multiplexer layer over a plurality of asymmetrical optical connections, wherein the plurality of asymmetrical optical connections is provided with only uni-directional equipment in the reconfigurable optical add-drop multiplexer layer.
US09246622B2 Semiconductor optical element, optical module and method of manufacturing semiconductor optical element
A semiconductor optical element and an optical module in which extinction ratio variation among integrated optical modulation elements is reduced. An optical module has a wavelength multiplexer that multiplexes light respectively emerging from electric-field-absorption modulator (EAM) portions of integrated optical modulation elements, and that outputs the multiplexed light. The integrated optical modulation element has a signal input terminal, a laser element portion, and an EAM portion. Each of the integrated optical modulation elements has a difference between an oscillation wavelength and a barrier layer bandgap wavelength, represented as an LDBG wavelength difference. Variation of the LDBG wavelength differences is limited within a range of ±1 nm.
US09246620B2 Method and apparatus for transmitting ACK/NACK in a TDD-based wireless communication system
Provided are a method and an apparatus for transmitting ACK/NACK in a time division duplex (TDD)-based wireless communication system. A terminal receives zero or more downlink transmission blocks in M downlink subframes from a first serving cell, and determines an ACK/NACK state {HARQ-ACK(1),HARQ-ACK(2),HARQ-ACK(3),HARQ-ACK(4)} for the first serving cell. The terminal determines an ACK/NACK response based on said ACK/NACK state, and transmits the ACK/NACK response in an uplink subframe.
US09246614B2 Methods and devices for transmission line analysis
Improved diagnostics of transmission line noise are enabled by adapting DSL equipment to make measurements of quiet line noise also in the transmit bands, so that noise can be measured at both ends for the same frequency or frequency bands.An estimate of the point where noise enters the line, as well as an estimate of the noise power at that point can be made from the relationship between the so measured noise levels at both ends of the line.
US09246610B2 Multimedia alerting
A method, system, and device provide alert information using weather prediction data. The method includes: converting weather prediction data to a tile based tile set, the tiles each representative of a unique geographic projection of a rendered geographical area of defined size; determining for each time period of the forecast whether any of the one or more weather variables associated with each prediction geographical tile violates a weather variable threshold for the location associated with the prediction geographical tile, the determining performed by comparing for each time period of the forecast each weather variable of the one or more weather variables associated with the prediction geographical tile to the weather variable threshold for the location associated with the prediction geographical tile; and generating and communicating one or more alerts corresponding to one or more violations of the weather variable thresholds for the locations associated with the prediction geographical tiles.
US09246607B2 Automatic phase calibration
A method is provided for calibrating a test platform to establish a phase relationship between copies of a signal at a measurement location within the test platform. Phase relationships of the copies of the signal traversing signal paths and ending at the measurement location are manipulated. Vector signal addition from the copies of the signal is analyzed as the phase relationships are manipulated to find a phase offset adjustment that establishes a particular phase relationship between the signal paths.
US09246605B2 Receiver and method for the reception of a node by a receiver in a wireless network
In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.
US09246599B2 Coherent optical receiver, apparatus and method for detecting interchannel skew in coherent optical receiver
In a coherent optical receiver, sufficient demodulation becomes impossible and consequently receiving performance deteriorates if an interchannel skew arises, therefore, a coherent optical receiver according to an exemplary aspect of the invention includes a local light source; a 90-degree hybrid circuit; an optoelectronic converter; an analog-to-digital converter; and a digital signal processing unit, wherein the 90-degree hybrid circuit makes multiplexed signal light interfere with local light from the local light source, and outputs a plurality of optical signals separated into a plurality of signal components; the optoelectronic converter detects the optical signals and outputs detected electrical signals; the analog-to-digital converter quantizes the detected electrical signals and outputs quantized signals; and the digital signal processing unit includes a skew compensation unit for compensating a difference in propagation delay between the plurality of signal components, and a demodulation unit for demodulating the quantized signals.
US09246598B2 Efficient pulse amplitude modulation integrated circuit architecture and partition
A transmitter is disclosed as being configured to encode optical signals in accordance with a multi-level coding scheme. The transmitter includes an Integrated Circuit architecture and partition that relaxes the bandwidth and linearity constraints of a gearbox-to-laser driver interface. In the proposed architecture, the gearbox Integrated Circuit aligns two or more digital data streams and transmits the aligned two or more data streams to the laser driver via separate signals.
US09246596B2 Monolithic widely-tunable coherent receiver
Various embodiments of a coherent receiver including a widely tunable local oscillator laser are described herein. In some embodiments, the coherent receiver can be integrated with waveguides, optical splitters and detectors to form a monolithic optical hetero/homodyne receiver. In some embodiments, the coherent receiver can demodulate the full phase information in two polarizations of a received optical signal over a range of optical wavelengths.
US09246590B2 Smart optical transceiver having integrated optical dying gasp function
An optical transceiver includes an electric terminal that can receive power from a host equipment and provide a power supply voltage to the optical transceiver, and a power failure monitor circuit that can detect an imminent loss of the power supply voltage. The power failure monitor circuit can produce a dying-gasp control signal when such imminent loss of power supply voltage is detected or when a disabling control signal is received from the host equipment. A driver can receive the dying-gasp control signal. An optical transmitter is powered by the power supply voltage and can emit a first optical signal under the control of the driver. The driver can modulate an envelope of the first optical signal in response to the dying-gasp control signal to produce a modulated envelope comprising a first dying gasp signal.
US09246589B2 Two-dimensional optical beam steering module
An interference-free communication system having a central communication controller (CCC) with a wavelength-tunable light source that emits a tunable wavelength optical data signal, and controls the wavelength-tunable light source by conditioning, modulation and wavelength-tuning, the CCC includes a signal-transparent optical crossconnect and fiber optic network, a pencil-radiating antenna (PRA) that is a passive 2-dimensional diffractive module is coupled to the wavelength-tunable light source via the fiber optic network, the crossconnect routes the optical data signal to the PRA, the optical data signal is transmitted through a confined optical pencil beam, the PRA deflects the pencil beam in 2 angular dimensions as a function of a wavelength of the pencil beam, the deflected pencil beam is disposed for communication with an opto-electronic communication device, and a radio return channel that provides upstream communication from the communication device to the CCC includes a lack-of-connection communication between the communication device and the CCC.
US09246586B2 Method and system for enabling and controlling communication topology, access to resources, and document flow in a distributed networking environment
Described are a system and method for use by a computing device to transmit information over a communication medium. The computing device communicates over the medium according to a protocol stack having a plurality of protocol layers. Information having an identifier is received at a first protocol layer from a higher protocol layer in the protocol stack. The computing device determines whether to present the information to the network communication medium based on at least one term of a contract associated with the identifier. Upon determining to present the information to the communication medium, the computing device incorporates the identifier in the information before placing the information on the network communication medium.
US09246585B2 System and method for visible light communication
A transmitter in a visible light communication system is provided, in which a plurality of light sources emit light in different colors, a data converter converts data to predetermined chromaticity coordinates, a data transmitter emits light having a chromaticity corresponding to the chromaticity coordinates by controlling light intensity of each of the light sources, and a pre-light emitter emits light having chromaticities corresponding to all chromaticity coordinates by controlling the light intensity of each of the light sources, before the light intensity control of the data transmitter.
US09246584B2 Method and apparatus for providing communication using a terahertz link
A method and apparatus for establishing a terahertz link using a multi-element lens array that comprises a liquid lens are disclosed. For example, the method receives detected terahertz signals from one or more detectors, where a liquid lens is deployed with each of the one or more detectors. The method determines, for each of the detected signals, if the detected signal is out of focus, and applies a corrective voltage to each liquid lens that corresponds to a detected terahertz signal that is out of focus, wherein the corrective voltage adjusts a focus of the detected signal. The method measures a signal-to-noise ratio of the detected signals, and establishing a terahertz link via at least one of the detected terahertz signals with a highest signal-to-noise ratio.
US09246583B2 Method and apparatus for measuring round trip delay in a unified optical-coaxial network
A method of determining a round trip delay time in a network comprising receiving a gate message allocating a transmission time window; retrieving a first timestamp from the gate message; setting a first clock to the time corresponding to the first timestamp, and wherein the first clock runs synchronously with a second clock recovered from a received data stream; sending upstream, after a time interval comprising a grant start time included in the transmission time window offset by a random delay time, a registration request message, wherein the registration request message includes a second timestamp obtained from the first clock; and determining a round trip delay (RTT) from a time the registration request message is received and the second timestamp.
US09246578B2 Method for allocating CDMA channels
A method for allocating CDMA channels applicable to a mobile communication system that performs communication by using two or more CDMA channels, the method comprising: for each active sector corresponding to a particular mobile station, independently allocating CDMA channels (i.e., frequency assignments) such that each active sector is allocated at least one CDMA channel; and transmitting packet data by using the allocated CDMA channel.
US09246577B2 Vehicular communication apparatus
A vehicular communication apparatus includes a communication device and an adjuster. The communication device exchanges a signal with an external communication device that is disposed external to the vehicle. The adjuster adjusts a transmission output of the communication device based on at least one of an operation mode of a vehicular device, which influences the communication device by generating a noise, or a classification of a signal exchanged between the communication device and the external communication device. The vehicular communication apparatus either prevents a deteriorated operation quality of the vehicular device or prevents a deteriorated communication quality of the communication device.
US09246576B2 Apparatus and methods for dynamic spectrum allocation in satellite communications
A communication system including Satellite Communication apparatus providing communication services to at least a first set of communicants, the first set of communicants including a first plurality of communicants, wherein the communication services are provided to each of the communicants in accordance with a spectrum allocation corresponding thereto, thereby to define a first plurality of spectrum allocations apportioning a first predefined spectrum portion among the first set of communicants; and Dynamic Spectrum Allocations apparatus operative to dynamically modify at least one spectrum allocation corresponding to at least one of the first plurality of communicants without exceeding the spectrum portion.
US09246572B2 Diversity indicating method in geran/muros systems
A diversity indication method in GERAN/MUROS system, includes the steps: after a user receives a diversity indication, it receives data from two sub-channels, and then carries out diversity combination; if the user does not receive diversity indications, users receive data from subchannel allocated to them. Using the method of this invention, we can carry out diversity indications in GERAN/MUROS system. In this way, users do not need to determine whether current frame is using diversity transmission in all sub-channels by carrying out autocorrelated operations over training sequences 26 bit long in each frame, and the users may demodulate information from another paired subchannel only when they receive diversity indications in subchannel allocated regularly to greatly reduce the user's complexity.
US09246567B2 Transmission signal generation method, transmission signal generation apparatus, reception signal generation method, and reception signal generation apparatus
Of any one of a transmission method X of transmitting modulated signal A and modulated signal B including the same data from a plurality of antennas and a transmission method Y of transmitting modulated signal A and modulated signal B having different data from the plurality of antennas, a base station apparatus does not change the transmission method during data transmission and changes only the modulation scheme. The base station apparatus transmits modulated signal A and modulated signal B to a communication terminal apparatus using the determined transmission method and modulation scheme. In this way, it is possible to improve data transmission efficiency when transmitting data using the plurality of antennas.
US09246565B2 User equipment, base station and method for selecting remote radio head
The present invention relates to a User Equipment (UE), a base station and a method for selecting a Remote Radio Head (RRH). A UE, including: a storage unit configured to store a code book including a plurality of precoding matrixes which contain a precoding matrix having an element zero corresponding to an antenna; a precoding matrix selection unit configured to select the precoding matrix to be used according to the code book stored in the storage unit; and a report unit configured to report an index of the precoding matrix selected by the precoding matrix selection unit. In the preferred embodiments, elements of a same precoding matrix for antennas of same RRH are all zero or non-zero.
US09246561B1 Method and apparatus for spatial modulation
A method of transmitting signals by a transmitting side device having multiple antennas (hereinafter ‘N antennas’) is disclosed. In this method, the transmitting side device transmits reference signals (RSs) via M antenna among the N antennas, where M≦N, where one or more of M and a sequence of antenna numbers used for transmitting RSs informs a receiving side device of first information for data transmission, and where the RSs are used by the receiving side device for identifying second information for channel estimation. Transmitting side device transmits data to the receiving side device according to the first information.
US09246560B2 Systems and methods for beamforming and rate control in a multi-input multi-output communication systems
Methods and apparatuses are disclosed that determine a type of channel information based upon whether a wireless device is scheduled to receive symbols. In addition, a determination may be as to a number of hop periods to determine the type of channel information. Further, a distance between hop regions may be utilized to determine a type of channel information.
US09246556B2 Radio network control
A radio network control method that allows uplink signals transmitted by a mobile station to be received by two or more selected base station radio systems and then combined, thus providing receiver diversity. The method requires measurement of radio link qualities of the OFDM signals passing between mobile station and base station radio system. The method is selectively applied to individual mobile stations and for each mobile station to a selection from the available base station radio systems—the selection being based upon the relative and/or absolute measurements of radio link qualities.
US09246555B2 System and associated NFC tag using plurality of NFC tags associated with location or devices to communicate with communications device
A Near Field Communications (NFC) tag includes a housing and a magnet carried by the housing and configured to be magnetically sensed by a magnetic sensor carried by a communications device to activate an NFC circuit within the communications device to communicate using an NFC communications protocol. A data store stores data regarding a function of the communications device to be magnetically coupled by the magnet. The data store is configured to be read by the communications device using an NFC communications protocol after the NFC circuit had been activated.
US09246552B2 Digital shunt regulator for NFC devices
A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
US09246549B2 Dielectric resonator driven near field transducer
An optical device includes a near field transducer; and a dielectric resonant structure coupled to the near field transducer; wherein the dielectric resonant structure comprises a dielectric material that decreases a dissipation of energy in the dielectric resonant structure, relative to other dissipations of energy associated with other materials; and wherein the decrease in the dissipation of energy increases an efficiency of energy transfer from the near field transducer to a target structure, relative to other efficiencies of energy transfer from the near field transducer to the target structure.
US09246548B2 Electromagnetic coupling of electronic devices using resonant terminations that shift resonant frequencies
An electromagnetic coupler comprising: a transmitter configured to operate at a first central frequency, a first termination configured to connect to the transmitter and having a second resonant frequency, a receiver configured to operate at the first frequency, a second termination configured to connect to the receiver and having a third resonant frequency, wherein when the first and second terminations are bought into close proximity when engaged, the equivalent resonant frequency is substantially the first frequency, and wherein the second and/or third frequencies being substantially spectrally spaced from the first frequency.
US09246547B2 Method and arrangement for transmitting data via an electric conductor of a current network
A method transmits data via an electric conductor of a current network. At least one first node and at least one second node are coupled to the electric conductor by a respective impedance-transparent coupling device. The method involves transmitting a carrier signal by the first node via the electric conductor, rectifying the transmitted carrier signal at the second node in order to supply energy to the second node, and modulating the transmitted carrier signal by the second node using a load modulation in order to transmit response data to the first node. The method is suitable in particular for low-maintenance and inexpensive sensor applications in current networks. An arrangement is used to transmit data via the electric conductor of a current network.
US09246546B2 Digital subscriber line management using virtual noise calculation
A digital subscriber line management system is provided. It comprises a device for calculating a set of values specifying a virtual noise mask. The device includes a receiver for receiving or otherwise obtaining a set of measurements of noise levels experienced at a digital subscriber line transceiver at each of a plurality of frequencies at different times, and a processor for calculating, in respect of each frequency, a combined value based on a plurality of measurements taken at different times, and for generating the set of values specifying a virtual noise mask in dependence upon the combined values.
US09246545B1 Adaptive estimation of delay in audio systems
Features are disclosed for adaptively estimating propagation delay in an audio system. A first device in communication with a speaker may be configured produce sound based on an audio playback signal. A second device in communication with one or more microphones may be configured to detect sound as a microphone signal. The second device may perform acoustic echo cancellation using a first propagation delay parameter and determine a first echo return loss enhancement. The second device may perform acoustic echo cancellation using a second propagation delay parameter and determine a second echo return loss enhancement. A propagation delay between the audio playback signal and the microphone signal may be adaptively estimated based on a comparison of the first and second echo return loss enhancements.
US09246541B2 UTRAN enhancements for the support of inter-cell interference cancellation
Systems and methodologies are described that facilitate providing uplink inter-cell interference cancellation. A radio network controller can receive measurement reports in order to identify non-serving nodes that are receiving interference from user equipment. Based on evaluation of such measurement reports, an interference message can be communicated to a Node B, wherein such measurement report can include information that allows the Node B to cancel or terminate the interference caused by such identified user equipment.
US09246534B2 Controling Tx/Rx mode in serial half-duplex UART separately from host
Signaling to control transmit/receive mode transitions of a serial half-duplex transceiver coupled externally to an integrated circuit is provided by the integrated circuit separately from a host processor of the integrated circuit with which the transceiver communicates. This can avoid slow transceiver turn-around times that may be associated with host processor control of the mode transitions.
US09246533B2 Electronic device including filter
An electronic device includes a main circuit connected between an input terminal and an output terminal, and an auxiliary circuit connected in parallel to the main circuit between the input terminal and the output terminal. The main circuit includes a filter having a first passband and a stopband. The auxiliary circuit has a passing characteristic that allows a signal having a frequency in a certain frequency band inside the stopband to pass through the auxiliary circuit. The main circuit is configured to output a main signal in response to an input signal. The auxiliary circuit is configured to output an auxiliary signal in response to the input signal. The main signal and the auxiliary signal contain phase components opposite to each other in the certain frequency band inside the stopband. This electronic device has an attenuation amount in the stopband.
US09246525B2 Device and method for predistortion
A device for predistortion and pulse shaping filtering in a communication system includes input scaling means arranged for scaling an applied transmit symbol with an adaptable input gain scaling factor, and a pulse shaping filter and a predistortion unit arranged for applying on the input gain scaled transmit symbol in either order a filtering operation and a non-linear predistortion operation to obtain a predistorted signal. The non-linear predistortion operation is represented by a set of parameter values selectable among a plurality of given sets of parameter values. The predistortion unit is arranged for selecting the set of parameter values exploiting a given performance measure. The device includes output scaling means arranged for scaling the predistorted signal with an output gain scaling factor to obtain a transmit signal. The adaptable input gain scaling factor and the output gain scaling factor are precalculated values corresponding to the selected set of parameter values.
US09246522B1 Apparatus and method for selecting antenna paths for multiple wireless communication components
An arbiter circuit receives a plurality of media access request signals from multiple protocol processing devices, and generates a plurality of media access grant indicators using i) the plurality of media access request signals, and ii) coexistence arbitration rules. A selector circuit receives the plurality of media access grant indicators from the arbiter circuit, and when the plurality of media access grant indicators indicate more than one protocol processing device is authorized to access an antenna, determines a compatibility of the more than one protocol processing device simultaneously accessing the antenna. The selector circuit, based on i) the plurality of media access grant indicators, and ii) the determined compatibility of the more than one protocol processing device simultaneously accessing the antenna, controls one or more switches to selectively enable antenna paths in a plurality of antenna paths coupled to the antenna.
US09246516B2 Techniques for error correction of encoded data
Techniques for error correction of encoded data are described. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is then made as to whether the ECC encoded data includes a single error, two errors or more than two errors. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes two errors, first and second error locations are identified. If the ECC encoded data includes more than two errors, separate error locations are identified for the more than two errors. The single error, the two errors or the more than two errors is/are corrected and the ECC encoded data is then be decoded.
US09246515B2 Error correction code block having dual-syndrome generator, method thereof, and system having same
An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.
US09246513B2 Method and apparatus for transmitting uplink data in a wireless access system
A method of channel coding for transmitting data in a wireless access system includes: calculating a number C of code blocks by an equation of C=┌B/(Z−L)┐, wherein B denotes a size of an input bit sequence, wherein Z denotes a maximum size of the code blocks, and wherein L denotes a size of a cyclic redundancy check (CRC) which is to be attached to each of the code blocks; calculating a size B′ of a modified input bit sequence by an equation of B′=B+C*L; generating the code blocks based on the number C of the code blocks and the size B′ of the modified input bit sequence; and channel-coding the code blocks.
US09246512B2 Error correcting device, method for monitoring an error correcting device and data processing system
An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.
US09246511B2 Method and apparatus to process data based upon estimated compressibility of the data
A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.
US09246508B2 Analog-to-digital conversion with noise injection via wavefront multiplexing techniques
A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.
US09246507B2 Analogue to digital conversion device
An A/D conversion device has an A/D conversion section including A/D conversion units. Each A/D conversion unit has a pulse delay circuit including delay units connected in daisy chain to form a ring delay line. Each delay unit delays a pulse signal by a delay time corresponding to an input voltage. The A/D conversion section counts the number of pulse signals that passed through the delay units during a period counted from a timing when a start signal is switched to an activation level from a non-activation level at a timing when a sampling signal is received. When each two successive timing signals CKi (i=1, 2, . . . and m) have a same specific period. The each two successive timing signals have a different phase shifted by 1/m of the specific period. Each A/D conversion unit receives the timing signal CK1 as the start signal, and the timing signal CKi+1 (CKm+1=CK1) as the sampling signal.
US09246504B2 Circuits and methods for implementing a residue amplifier
Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator.
US09246502B2 Control method of D/A converter, D/A converter, control method of A/D converter, and A/D converter
The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.
US09246497B1 Integrated circuit (IC) clocking techniques
Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.
US09246495B2 Resonator arrangement and method for exciting a resonator
A method for exciting a resonator having a resonance frequency, the resonator is excited in a first period with a first frequency that differs from the resonance frequency by a first frequency difference is provided. During a second period, the resonator is excited with a second frequency that differs from the resonance frequency by a second frequency difference. The first frequency difference and the second frequency difference have different signs. Additionally, the amounts of the first frequency difference and of the second frequency difference differ from one another by less than 10% of the greater amount.
US09246494B2 Metering circuit including a floating count window to determine a count
A method includes receiving a count corresponding to a number of peaks of a resonant signal that exceed a reference signal and comparing the count to a floating count window defined by a first count threshold and a second count threshold, the first count threshold is larger than the second count threshold. The method further includes selectively shifting the floating count window in a direction of the count when the count falls outside of the floating count window.
US09246493B2 Level shift circuit and semiconductor device
A level shift circuit includes: a latch circuit (Q5, Q6, Q7, Q8) including first (Q5, Q7) and second (Q6, Q8) inverter circuits; a first input MOS transistor (Q1) operating in accordance with an input signal; a second input MOS transistor (Q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control MOS transistor (Q9). The latch circuit (Q5, Q6, Q7, Q8) outputs a voltage having been converted from the input voltage in level. Each of the first and second input MOS transistors (Q1, Q2) receives the input signal at its gate terminal, and drives the latch circuit (Q5, Q6, Q7, Q8) in accordance with the input signal. The current-voltage control MOS transistor (Q9) is provided between the input MOS transistor (Q1, Q2) and the latch circuit (Q5, Q6, Q7, Q8), and is driven in accordance with an inversion operation of the latch circuit by receiving an input of the control voltage at its gate terminal.
US09246489B1 Integrated clock gating cell using a low area and a low power latch
The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.
US09246487B2 Keyboard with user configurable granularity scales for pressure sensitive keys
Systems and methods are disclosed for user configurable pressure sensitive keys and techniques for controlling these keys for keyboards. User configuration information, including information for user configurable granularity scales for pressure levels, can be communicated from a host system to the keyboard and stored for later use by a keyboard controller to control the operation of the pressure sensitive keys. In this way, greater control of the pressure sensitive keys can be provided. This configurability is of particular use for applications such as where the keyboard is being used for gaming by a user running a gaming application on an information handling system.
US09246482B2 Power switches for aircraft
The present invention relates generally to power switches for aircraft. According to a first aspect, the present invention provides an integrated solid state power switch for fault protection in an aircraft power distribution system. The integrated solid state power switch is formed of semiconductor material that provides a field effect transistor (FET) channel that is operable during normal device operation to provide an operating current flow path and a bipolar transistor channel that is operable during device overload conditions to provide an overload current flow path. A method for manufacturing such an integrated solid state power switch is also described. Various embodiments of the invention provide automatic overload current protection for aircraft systems without the need to use bulky switches or heavy cooling equipment.
US09246480B2 Method for performing phase shift control in an electronic device, and associated apparatus
A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases, wherein any two phases of the set of phases are different from each other; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital weighting control signals, wherein the phase shift corresponds to the set of digital weighting control signals, and the set of digital weighting control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital weighting control signals.
US09246478B2 Electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal
The present application suggests an electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal. The device comprises a random number generator to generate a random number signal varying in time which represents a divisor fraction signal; a signal mixer to mix the timely varying random number signal and a clock divisor signal and to output a mixed divisor signal; and a fractional clock divider to generate an output clock signal from a source clock signal, wherein the output clock signal has a frequency fout(t), which is substantially equal to the frequency fsource of the source clock signal being a narrow-band clock signal divided by a divisor D(t) represented by the mixed divisor signal.
US09246475B2 Dual-complementary integrating duty cycle detector with dead band noise rejection
A method for correcting the duty cycle of a clock signal uses two-dual-slope integrators with two comparators; each comparator is connected to both integrators and configured to include a “dead band” when the input pulse duty cycle is at or near 50%. One comparator detects when duty cycle is high and the other comparator detects when the duty cycle is low. When the duty cycle is within the “dead band” range, neither comparator goes valid. This provides an analog filter where the output comparators will not instantaneously switch between opposite duty cycle correction states. When the duty cycle is greater or less than 50%, the integrated voltages on the two integrators move in opposite directions producing twice the signal magnitude on differential inputs of the comparators, as compared with using a single integrator architecture.
US09246471B2 Resonator element, resonator, oscillator, electronic device, and mobile object
A resonator element includes a base, a quartz crystal resonator blank which is integrally disposed with the base, and has a pair of vibrating arms which are disposed in parallel in an X axial direction, and extend from the base in a Y′ axial direction, the vibrating arms include arms, hammerheads which are positioned on tip end sides of the arms, and are longer than the arms in the X axial direction, a relationship of 0.033×T [μm]
US09246469B2 Manufacturing method of oscillator, manufacturing method of circuit device and the circuit device
A manufacturing method of an oscillator is a manufacturing method of an oscillator which includes a vibrator and a semiconductor circuit device including an oscillation part connected to the vibrator and a control part to switch an operation mode between a normal mode in which the oscillation part performs an oscillation operation and an inspection mode in which characteristics of the vibrator are inspected, and the manufacturing method includes preparing the semiconductor circuit device in which the operation mode is set to the inspection mode, connecting the semiconductor circuit device and the vibrator electrically, and inspecting the characteristics of the vibrator which is in a state electrically connected to the semiconductor circuit device.
US09246467B2 Integrated resonator with a mass bias
An integrated resonator apparatus includes a piezoelectric resonator and an acoustic Bragg reflector formed adjacent the piezoelectric resonator. The integrated resonator apparatus also includes a mass bias formed over the Bragg reflector on a side of the piezoelectric resonator opposite the piezoelectric resonator.
US09246463B2 Compensation networks and communication connectors using said compensation networks
The present invention generally relates to the field of network communication, and more specifically to networks for crosstalk reduction/compensation and communication connectors which employ such networks. In some embodiments, the present invention employs an orthogonal network implemented within a communication jack to compensate for crosstalk which occurs within a communication plug and at the plug/jack interface.
US09246461B2 Manufacturing method of piezoelectric-body film, and piezoelectric-body film manufactured by the manufacturing method
A method for manufacturing a piezoelectric thin film including an aluminum nitride thin film containing scandium on a substrate, the method includes: sputtering step for sputtering aluminum and scandium under an atmosphere containing at least a nitrogen gas. In the sputtering step in the method according to the present invention, a scandium content rate falls within the range from 0.5% by atom to 50% by atom when a temperature of the substrate falls within the range from 5° C. to 450° C. during the sputtering step.
US09246460B2 Power management architecture for modulated and constant supply operation
A power management system, which includes a parallel amplifier circuit and a switch mode power supply converter, is disclosed. The switch mode power supply converter cooperatively operates with the parallel amplifier circuit to form the power management system. The power management system operates in one of a high power modulation mode, a medium power modulation mode, and a low power average power tracking mode. Further, during the high power modulation mode and the medium power modulation mode, the power management system controls a power amplifier supply voltage to a radio frequency power amplifier to provide envelope tracking. During the low power average power tracking mode, the power management system controls the power amplifier supply voltage to the radio frequency power amplifier to provide average power tracking.
US09246459B2 Variable gain amplifier
A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.
US09246458B2 Fixed gain amplifier circuit
An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.
US09246456B2 Amplification circuit and reception chain
An amplification circuit including: an input for receiving an input voltage; an output for exhibiting an output voltage; a primary amplifier configured to receive the input voltage from the input, receive a primary control voltage, first amplify the input voltage by a primary gain dependent on the control voltage, the output voltage corresponding to the first amplified input voltage, and supply the output voltage to the output; and a secondary amplifier configured to receive the input voltage from the input, second amplify the input voltage by a secondary gain, the primary control voltage corresponding to the second amplified input voltage, and supply the primary control voltage to the primary amplifier. The secondary amplifier has in operation an input admittance of at least 1 millisiemens.
US09246446B2 Chopper amplifier
A chopper amplifier includes a chopper modulator to modulate a certain detection signal and a bias voltage by a certain control signal and output a chopper modulation signal, a first differential amplifier to differentially amplify the chopper modulation signal from the chopper modulator and output a differential modulation signal, a chopper demodulator to demodulate the differential modulation signal from the first differential amplifier by the control signal and output a demodulation signal, a second differential amplifier to extract a detection signal component from the demodulation signal, and a plurality of filters connected at an input terminal of the second differential amplifier and having different cutoff frequencies from each other relative to the demodulation signal.
US09246445B2 Audio amplifier performance while maintaining USB compliance and power down protection
An apparatus comprises a first audio amplifier circuit configured to provide an analog audio signal and an analog switch circuit including a first input configured to receive the analog audio signal, a second input configured to receive a first digital data signal, and a first output configured to provide one of the digital data signal or the analog audio signal. The apparatus also includes a first feedback circuit coupled to the first audio amplifier circuit and the analog switch circuit output, the feedback circuit configured to bias the first audio amplifier circuit.
US09246438B2 Receiver architecture for a compact and low power receiver
A circuit for a receiver with reconfigurable low-power or wideband operation may comprise one or more main signal paths each coupled to a first port and including a low-noise amplifier (LNA) configured to provide a radio frequency (RF) signal to a main mixer circuit. An auxiliary signal path may be coupled to a second port. The auxiliary signal path may include an auxiliary mixer configured to provide an on-chip matching input impedance that may match an impedance of the antenna. The first port may be coupled to an RF antenna through an off-chip matching circuit, when a low-power operation is desired. The first port may be coupled to the second port and to the RF antenna, when a wideband operation is desired.
US09246435B1 Method to pre-charge crystal oscillators for fast start-up
A method and apparatus for charging a crystal oscillator are provided. A voltage generating module outputs a ramp voltage signal to a ring oscillator. The ring oscillator generates and outputs a waveform based on the ramp voltage signal. The ramp voltage signal facilitates the ring oscillator to output the waveform at a frequency that varies with time, wherein the varying frequency is within a frequency range of the crystal oscillator. An inverter generates a digital input signal based on the waveform. The digital input signal is sent to an input of the crystal oscillator for charging the crystal oscillator. A feedback module outputs a feedback signal based on the digital input signal, wherein the feedback signal controls the voltage generating module to generate a fixed voltage signal that facilitates the ring oscillator to output the waveform at a frequency that is equal to a resonance frequency of the crystal oscillator.
US09246434B2 System and method for estimating the short circuit current of a solar device
Described herein is a method and system for determining a short-circuit current of a solar device before the solar device is tested in a solar simulator. A solar device includes a substrate layer, a front contact layer, a window/emitter layer, an absorber layer and a back contact. A thickness of the window/emitter layer and an absorption wavelength of the absorber layer are determined. The window/emitter layer thickness and absorber layer absorption wavelength are used with a fitting parameter that corresponds to transmission properties of the substrate and first contact layers in order to determine the solar device's short-circuit current.
US09246428B2 Vector control device for an electric motor that controls an electric power converter that converts DC power to AC power, electric motor, vehicle drive system, and vector control method for electric motor
A vector control device includes a vector control unit computing an output voltage output from the electric power converter according to vector control based on torque command and flux command and generating a PWM signal for controlling the electric power converter based on the output voltage, a first flux-command generation unit generating a flux command for asynchronous PWM mode, and a second flux-command generation unit generating a flux command for synchronous PWM mode. When an output frequency of the electric power converter is lower than a predetermined value, a flux command generated by the first flux-command generation unit is input to the vector control unit, and when the output frequency of the electric power converter is equal to or higher than a predetermined value, a flux command generated by the second flux-command generation unit is input to the vector control unit.
US09246425B2 Apparatus and systems for engine and generator control within an aircraft
A system is provided for engine and generator control. The system includes a compound AC generator, a generator control unit (GCU) module and an engine electronic controller (EEC) module. The compound AC generator includes a shaft, and a permanent magnet generator (PMG) configured to be driven by the shaft to generate an AC power signal. The GCU module is configured to control the compound AC generator. The PMG is coupled to the GCU module and the EEC module such that it is configured to simultaneously supply the AC power signal to the GCU module and to the EEC module.
US09246424B2 Dynamic mixed-mode current decay apparatus and methods
Stepper motor winding current regulation methods and apparatus continuously and bi-directionally sense winding current to determine both the magnitude of the winding current and the slope of a waveform representing the winding current. The magnitude and slope information is used to more precisely control periods of current rise and characteristics of fast and slow current decay during pulse-width modulation (“PWM”) regulation cycles. Winding current rise and decay shaping is based upon the sensed magnitude of the winding current, the magnitude of the winding current regulation set-point ITRIP, whether the sensed winding current is greater than or less than ITRIP at a selected sampling time, whether the sensed winding current is increasing or decreasing when a waveform of the sensed winding current crosses over ITRIP, and whether or not the magnitude of ITRIP changes during a PWM cycle in response to a receipt of a subsequent DAC code.
US09246418B2 EC motor with dynamic determination of optocoupler degradation
In an EC motor, comprising a motor electronics, a signal input or a signal output, and an optocoupler for the galvanically isolated transmission of a useful signal between the motor control unit and the signal input or the signal output, the intention is to reliably determine the degradation of the optocoupler and to improve the service life of the EC motor. This is achieved in that an evaluation unit regularly evaluates a saturation voltage of the optocoupler at the output of the optocoupler in relation to a reference threshold when the optocoupler is wired and generates a warning signal when the saturation voltage exceeds the reference threshold.
US09246413B2 Ultrasonic motor
An ultrasonic motor (10) includes a vibrator (50) and an application means (oscillation circuit 80). A first vibrator area (51) and a second vibrator area (52), which form a vibrator (50), include piezoelectric elements polarized in the thickness direction, and fixed portions (30a, 30b) respectively. The oscillation circuit 80 applies an AC voltage to the piezoelectric elements respectively and makes the first vibrator area (51) and the second vibrator area (52) resonate individually in the surface-spreading directions. The ultrasonic motor (10) includes a coupling portion (55) for coupling vibration end portions (23a, 23b) each other and a contact element (60) which is provided on this coupling portion (55). The vibration end portions (23a, 23b) are positions which vibrate respectively in the approaching and separating directions by the resonances of the first vibrator area (51) and the second vibrator area (52) in the surface-spreading directions with respect to the fixed portions (30a, 30b).
US09246408B2 Power conversion apparatus
The power conversion apparatus includes an inverter circuit which converts a DC current into an AC current and have a U-phase, V-phase, and w-phase power semiconductor modules, and a capacitor module for smoothing the DC current. Each of the power semiconductor modules is configured separately and connected to a first bus bar. The first bus bar is configured with a first positive side bus bar, a first negative side bus bar, and a first insulation member arranged between the first positive side bus bar and the first negative side bus bar. The first bus bar includes a first to third terminals to which the U-phase, V-phase, and W-phase power semiconductor modules are connected, respectively, and a fourth terminal connected to a terminal of the second bus bar protruding from a surface of sealing material of a second bus bar.
US09246405B2 Electrical energy transmission system with a single transmission line
An electrical energy transmission system has a three-phase electric current power source which generates a three-phase electric current having three electric currents, a converting device which converts the three-phase electric current to obtain a common electric current signal formed by summation of three electric currents having the same phases, and a single-line electrical transmission line which transmits further the thusly produced common electric current signal.
US09246403B2 Lighting systems with uniform LED brightness
Solid state lighting systems are disclosed for providing uniform brightness of LEDs serially connected in a string. In some embodiments, the LEDs can be powered directly from the mains such that no switch-mode power supply or the output storage elements associated therewith are needed. In some such cases, a linear regulator and switches can be used to control the current through the LEDs to provide uniform brightness. Other embodiments can be used with a switch-mode based driver topology and/or storage elements coupled in parallel with clusters of the LEDs. In any such cases, control logic (e.g., microcontroller or other suitable controller) can be used to control the switches accordingly to provide uniform brightness, and in some cases, to mitigate the implications of having no SMPS output storage element. In some embodiments, the switching pattern provided by the control logic is random, although other switching patterns can be used.
US09246398B2 Power converter
A power converter includes a rectifier section, an inverter section, a capacitance element connected between inverter section input ends, an inductance element forming part of an LC filter with the capacitance element, a voltage detector detecting an inductance element voltage, and a controller controlling the inverter section based on the detected voltage. The LC filter has a resonance frequency set such that ripple current components contained in DC current outputted from the rectifier section passes through, and current components of a frequency equal to a carrier frequency of the inverter section are dampened. The controller controls the inverter section so that a transfer characteristic of input voltage of the inverter section versus the DC voltage from the rectifier section becomes a damping characteristic given by a phase lead element and a second-order lag element connected in series, and a damping coefficient of the transfer characteristic is set larger than 1.
US09246395B1 Circuits and methods for determining peak current
Embodiments include circuits and methods to determine peak current for current regulation. A control signal circuit monitors a current on the primary side of a transformer based a turn on time of a switch coupled to the primary side. The control signal circuit determines whether the monitored current exceeds an over-current protection threshold, and determines a duration that the monitored current exceeds the over-current protection threshold. The control signal circuit determines a peak primary current in the primary side based on the over-current protection threshold, the duration that the monitored current exceeds the over-current protection threshold, and the turn on time of the switch. The control signal circuit controls the turn on time for the switch based on the determined peak primary current.
US09246390B2 Power converter with controller operable in selected modes of operation
A power converter and method of controlling the same for selected modes of operation. In one embodiment, the power converter includes a first power switch coupled to a source of electrical power and a second power switch coupled to the first power switch and to an output terminal of the power converter. The power converter also includes a controller configured to control an operation of the first and second power switches during selected modes of operation.
US09246377B2 Apparatus for transferring substrate
Disclosed is an apparatus for transferring substrates capable of stably transferring substrates by using magnetic levitation. The apparatus includes a substrate stage including a substrate loading unit, a first guide block disposed at a first end of the substrate stage and including a first magnet generator, a second guide block disposed at a second end of the substrate stage and including a second magnet generator, a first guide rail accommodating the first magnet generator and including a third magnet generator, and a second guide rail accommodating the second magnet generator and including a fourth magnet generator. The first magnet generator and the third magnet generator exert repulsive force on each other, and the second magnet generator and the fourth magnet generator exert repulsive force on each other.
US09246373B2 Cooling assembly for electrical machines and methods of assembling the same
An assembly for cooling an electrical coil winding having a first coil, a second coil, a first end turn and a second end turn is provided. The assembly includes a supply header; a return header; and a plurality of flow members coupled in flow communication to the supply header and the return header. The flow members are configured to channel a flow agent from supply header to the return header. Each the flow member of the plurality of flow members includes a first portion coupled to the first coil; a second portion coupled to the second coil; a first end portion coupled to the first end turn and coupled in flow communication to the first portion and the second portion; and a second end portion coupled to the second end turn and coupled in flow communication to the second portion.
US09246369B2 Electric motor
An electric motor includes a rotor and a stator. The stator surrounds the rotor, has a top half, a bottom half, and wire windings, and is fixed with respect to the drive-unit housing. The stator is cooled by gravity feed via a fluid supplied by an external source and flowing onto and past the top half. The motor also includes a fluid dam fixed relative to the stator. The fluid dam is configured to guide the fluid around the stator and shield the rotor from the fluid flowing past the stator thereby limiting an amount of the fluid between the rotor and the stator such that spin losses in the electric motor are controlled. An electro-mechanical drive-unit employing the above described electric motor is also disclosed.
US09246361B2 Segmented magneto-conductive structure applied in rotating machines
A segmented magneto-conductive structure applied in rotating machines comprises a rotor assembly and a stator assembly. The rotor assembly includes a rotor yoke component and a plurality of rotor teeth components. The rotor yoke component is made of non-oriented silicon steel. The rotor teeth components are made of grain-oriented silicon steel. The stator assembly includes a plurality of stator yoke components and a plurality of stator teeth components. The stator yoke components and the stator teeth components are made of grain-oriented silicon steel. Thereby, an operational efficiency of a motor applying the segmented magneto-conductive structure is enhanced.
US09246356B2 Adaptive inductive power supply
A contactless power supply has a dynamically configurable tank circuit powered by an inverter. The contactless power supply is inductively coupled to one or more loads. The inverter is connected to a DC power source. When loads are added or removed from the system, the contactless power supply is capable of modifying the resonant frequency of the tank circuit, the inverter frequency, the inverter duty cycle or the rail voltage of the DC power source.
US09246354B2 Electricity storage device for solar energy harvesting device
An electricity storage device for a solar energy harvesting device comprising at least a first electricity storage unit, at least a second electricity storage unit, a battery monitoring unit and a power converter. The second electricity storage unit is for coupled to an exterior power supply system which charges/discharges the second electricity storage unit in a predetermined voltage. The battery monitoring unit controls the power converter according to the output voltage of the first electricity storage unit for converting the electricity of the first electricity storage unit to the second electricity unit. When the output voltage of the first electricity storage unit is larger than a start voltage, the electricity of the first electricity storage unit is converted to the second electricity storage unit. When the output voltage of the first electricity storage unit is less than a stop voltage, the battery monitoring unit disables the power converter.
US09246353B2 Smart dock charging
A multi-display device can interface with two or more different types of docking stations. The device can determine the type of dock and change the pin outs for a connector to interface with that dock. Once docked, the device can determine a charge status for the device and the dock to present the status to the user. Further, the dock can enter one of several modes, including a call receipt mode and an entertainment mode. The modes allow for expanded functionality for the device while docked. Two particular docks, the laptop dock and the smart dock, provide special functionality with the device.
US09246352B2 Electronic device having a wireless charger coil and an antenna element on the same plane
A portable terminal is provided. The portable terminal includes a shielding member disposed on an external part, a first coil disposed on a surface of the shielding member that faces the external part, and a second coil disposed on the surface of the shielding member, and surrounding the first coil on a same plane.
US09246350B2 Method and apparatus for wirelessly charging a mobile terminal
A mobile terminal and a method for wirelessly charging the mobile terminal are provided. The method includes searching for a wirelessly rechargeable mobile terminal; receiving, upon finding a wirelessly rechargeable mobile terminal, power state information from the found rechargeable mobile terminal; setting the mobile terminal as one of a power supplying terminal and a power receiving terminal based on the received power state information; and performing a power charging operation with the found rechargeable mobile terminals according to the setting.
US09246349B2 Method and system for wireless battery charging utilizing ultrasonic transducer array based beamforming
An ultrasound power transmitter comprising a transmit ultrasonic transducer array has a plurality of transmit ultrasonic transducers. The ultrasound power transmitter activates a set of transmit ultrasonic transducers in close proximity of an electronic device to be arranged to beam ultrasound energy to the electronic device. Alignment magnets of the ultrasound power transmitter are aligned with corresponding alignment magnets of the electronic device to manage the ultrasound beaming. The ultrasound energy may be converted into electric power to charge the battery of the electronic device. Feedbacks may be provided by the electronic device to the ultrasound power transmitter to increase power transmission efficiency. The ultrasound power transmitter may pair the electronic device with other different electronic devices utilizing ultrasonic signals. A spacer with good ultrasound power transmission properties may be located between the ultrasound power transmitter and an ultrasound power receiver of an intended electronic device to enhance power transmission.
US09246348B2 Battery charge modulator with boost capability
A system and method for controlling a converter of a power stage receiving an adapter current for providing current to a load. The converter is operative in a buck mode for charging a battery and in a boost mode for discharging the battery to the load to supplement adapter current. The adapter current is compared with a predetermined level to develop a control signal, and at least one pulse control signal is developed based on the control signal and used to control the modulator. The modulator operates the converter in the buck mode when the adapter current up to the predetermined level, and operates the converter in the boost mode when the adapter current exceeds the predetermined level. The battery current may also be monitored to adjust the control signal to limit battery charge or discharge current in both modes.
US09246342B2 Charging system for portable electronic equipment
In a charging system for portable electronic equipment, providing the charging current is automatically restarted even in the case where an amount of charging current taken into the portable electronic equipment exceeds charging current providing capacity of a USB battery charger and the USB battery charger stops providing the charging current. When a voltage at a VBUS terminal is lower than a first predetermined voltage, a CPU assumes that the USB battery charger has stopped providing the charging current and turns off a first switching device. And the CPU turns on a second switching device for a predetermined period of time. As a result, the voltage at the VBUS terminal falls to 0.7V or below during the predetermined period of time. In response to the change in the voltage at the VBUS terminal, the USB battery charger restarts providing the charging current to the VBUS terminal.
US09246330B2 Photovoltaic device
A method and system for operating a photovoltaic module includes providing a reversed electrical bias to the photovoltaic module.
US09246327B2 Arrangement for controlling the electric power transmission in a HVDC power transmission system
An arrangement for controlling the electric power transmission in a high voltage direct current, HVDC, power transmission system includes at least one HVDC transmission or distribution line for carrying direct current, DC, and the arrangement includes an apparatus connectable to the HVDC transmission or distribution line, the apparatus being arranged to control the direct current of the HVDC transmission or distribution line by introducing a DC voltage in series with the HVDC transmission or distribution line. The arrangement includes a protection device for protecting the apparatus against over-current or overvoltage occurrences. The protection device includes a bypass device connectable to the HVDC transmission or distribution line and connected in parallel with the apparatus. The bypass device is arranged to be in a non-conducting mode and arranged to be set to a conducting mode. When being in the conducting mode, the bypass device is arranged to conduct direct current of the HVDC transmission or distribution line to electrically bypass the apparatus. A HVDC power transmission system includes at least one arrangement of the above-mentioned sort. A method for protecting an apparatus against over-current or overvoltage occurrences, the apparatus being included in an arrangement of the above-mentioned sort.
US09246326B2 Method and system for online ferroresonance detection
The invention concerns a method and a system for online ferroresonance detection in a high voltage electrical distribution network. The method includes: Overflux detection (23), which acts as the start element, overflux being set if the flux is greater than a threshold for specified time duration, mode verification (26) which is to recognize the modes of the ferroresonance, a fuzzy logic method being used to discriminate the ferroresonance modes.
US09246323B2 Current controller and protection circuit
A current controller for generating a control signal which controls supply current flowing from a power source to a load includes an interface circuit which sets a threshold based on an instruction from an outside of the current controller, a threshold setting circuit which stores and outputs the threshold, a sensing circuit which determines a current or a temperature of a sensing element, and outputs a signal indicating that the supply current should be interrupted as the control signal if a determined current or a determined temperature exceeds the threshold, and a sensing control circuit which generates a clock signal including pulses with a predetermined period. The sensing circuit determines the current or the temperature of the sensing element during an active period of the clock signal.
US09246318B2 Adjustable wireway assembly, method of employing, and enclosure employing the same
An adjustable wireway assembly for use in an electrical enclosure includes a panel structured to form a portion of the electrical enclosure, the panel having a first aperture defined therein. The assembly further includes a plate member selectively coupled to the panel about a portion of the first aperture in at least one of a first position and a second position in a manner that blocks at least a portion of the first aperture and thereby defines a second aperture formed from a portion of the first aperture. When coupled in the first position, the second aperture is of a first area and when coupled in the second position, the second aperture is of a second area different than the first area.
US09246315B2 Seals to barrier penetrations
A number of devices (floor grommets) for providing an air seal of an aperture through which one or more cables or conduits pass are disclosed. The devices (1, 90) include a frame (6) and at least first and second opposing sealing members (91, 92) defining sealing faces mounted in the frame. At least one of the sealing members (91, 92) is movable between a position in which the aperture is substantially closed and a position in which the aperture is substantially open. The sealing members (91, 92) includes resilient flexible compressible foamed plastics or polymeric material or the like. The sealing members provide a substantial air seal across the frame opening in use with said resilient flexible compressible foamed plastics or polymeric material forming the sealing members deforming and conforming around any cables or conduits or the like extending through the frame.
US09246314B2 Mobile device configured to perform tasks related to a power transmission system
Described embodiments include a system and an apparatus. A described mobile robotic device includes a mobile chassis configured to travel on a transmission line of a power transmission system. The mobile robotic device includes an inspection module physically associated with the mobile chassis and configured to automatically inspect a structure associated with the power transmission system. The mobile robotic device includes a risk-assessment module physically associated with the mobile chassis and configured to assess a potential risk to the power transmission system in response to inspection data provided by the inspection module. The mobile robotic device includes a communication module physically associated with the mobile chassis and configured to output data indicative of the assessed potential risk.
US09246312B2 Dynamical Fabry-Perot tuneable filter device
A Fabry-Pérot tuneable filter device is described with reflecting elements separated by an optical path length to form an optical resonator cavity. A first actuator means is directly or indirectly coupled with a first reflecting element. And the first actuator means is configured to modulate the optical path length between first and second reflecting elements by a modulation amplitude to thereby sweep the optical resonator cavity through a band of optical resonance frequencies with a sweep frequency of 70 kHz or more. And the mechanical coupling between selected elements of the arrangement is sufficiently low such that when operated at the sweep frequency, the selected elements act as a system of coupled oscillating elements. In addition or alternatively, the first actuator means is directly or indirectly coupled with the first reflecting element so as to substantially drive the first reflecting element only.
US09246311B1 Method of manufacture for an ultraviolet laser diode
A method for fabricating a laser diode device includes providing a gallium and nitrogen containing substrate member comprising a surface region, a release material overlying the surface region, an n-type gallium and nitrogen containing material; an active region overlying the n-type gallium and nitrogen containing material, a p-type gallium and nitrogen containing material; and a first transparent conductive oxide material overlying the p-type gallium and nitrogen containing material, and an interface region overlying the first transparent conductive oxide material. The method includes bonding the interface region to a handle substrate and subjecting the release material to an energy source to initiate release of the gallium and nitrogen containing substrate member.
US09246309B2 Quantum cascade laser
A quantum cascade laser includes a semiconductor substrate, and an active layer that is provided on the substrate, and has a cascade structure in which emission layers and injection layers are alternately laminated by multistage-laminating unit laminate structures each consisting of the quantum well emission layer and the injection layer, the active layer generates light by intersubband transition in a quantum well structure. Further, in a laser cavity structure for light with a predetermined wavelength to be generated in the active layer, reflection control films including at least one layer of CeO2 film are formed on a first end face and a second end face facing each other. Thereby, it is possible to realize a quantum cascade laser capable of preferably realizing reflectance control for light within a mid-infrared wavelength region on the laser device end face.
US09246308B2 Quantum cascade laser
A quantum cascade laser includes a semiconductor substrate including a principal surface; a mesa waveguide disposed on the principal surface of the semiconductor substrate, the mesa waveguide including a light emitting region and an upper cladding layer disposed on the light emitting region, the mesa waveguide extending in a direction orthogonal to a reference direction; and a current blocking layer formed on a side surface of the mesa waveguide. The light emitting region includes a plurality of core regions and a plurality of buried regions. The core regions and the buried regions are alternately arranged in the reference direction. The core region at a central portion of the mesa waveguide has a width smaller than a width of the core region at a peripheral portion of the mesa waveguide in the reference direction.
US09246305B1 Light-emitting devices with integrated diamond
A light-emitting device having one or more diamond layers integrated therein and methods for forming a light-emitting device with integrated diamond layers. The diamond is grown either directly on the semiconductor material comprising the light-emitting structure, on a nucleation layer deposited on the semiconductor material, or on a dielectric layer deposited on the semiconductor material before growth of the diamond layer. The device can include a trench or thermal shunt formed in the substrate on the backside of the device, or can include a heat sink to provide additional thermal management.
US09246302B2 Precision photonic oscillator and method for generating an ultra-stable frequency reference using a two-photon rubidium transition
Embodiments of an ultra-stable frequency reference generating system and methods for generating an ultra-stable frequency reference using a two-photon Rubidium transition are generally described herein. In some embodiments, a cavity-stabilized reference laser comprising a laser source is locked to a stabilized cavity. A Rubidium cell is interrogated by a stabilized laser output to cause at least a two-photon Rubidium transition and a detector may detect fluorescence resulting from spontaneous decay of the upper state Rubidium transition. The output of the detector is provided at a wavelength of the fluorescence to lock the cavity-stabilized reference laser to generate a stabilized laser output. A frequency comb stabilizer may be locked to the stabilized laser output to generate a super-continuum of optical wavelengths for use in generating an ultra-stable frequency reference.
US09246295B2 Pulse-shaping interferometer for chirped-pulsed amplification laser
A high power ultrashort chirped pulse amplifier laser system, with a chirped pulse amplifier laser module including an optical pulse stretcher, at least one optical power amplifier, and an optical pulse compressor, and a beam interferometer module in the optical path. The beam interferometer receives splits the pulse into at least two pulses, adds a time delay to at least one of the pulses and recombines the pulses to produce a temporally modulated pulse. The resulting modulated output pulse from the CPA laser module can have enhanced laser contrast due to greatly reduced subpicosecond pedestal in the immediate region of the peak pulse, or can have other desirable characteristics.
US09246294B2 Tool for attaching a cable connector to a cable
A tool for changing first and second parts of a connector from a pre-assembly relationship into an assembled relationship. The tool is portable and has a frame with an operating mechanism thereon. The operating mechanism has a plunger that is movable to thereby change the relationship of the connector parts. The operating mechanism is operable by a pressurized fluid within a container that is connected to the frame.
US09246293B2 Leadframe for a contact module and method of manufacturing the same
A leadframe for a contact module includes signal contacts arranged in pairs carrying differential signals. Each pair of signal contacts includes a first signal contact and a second signal contact. Each signal contact has a mating beam at an end thereof configured to be electrically connected to a corresponding header contact of a header assembly. Each mating beam includes a stem and a branch extending from the stem. A first paddle extends from the stem and a second paddle extends from the branch. In an initial, stamped orientation, the mating beams are stamped such that the mating beams of the first and second signal contacts within the same pair of signal contacts are angled non-parallel to one another.
US09246292B2 Terminal, method of manufacturing terminal, and termination connection structure of electric wire
A terminal includes a tubular crimp portion that crimp connects with an electric wire. The tubular crimp portion is composed of a metal member. The tubular crimp portion includes a non-weld portion and a weld portion, the weld portion being formed by welding. A metal base material constituting the metal member of the non-weld portion includes a normal portion and an annealed portion.
US09246288B2 Multipurpose in-vehicle diagnostic II adapter
The present invention is directed to an extension connector. The extension connector may include a first connector communicatively coupled to an in-vehicle connector associated with an automobile. The extension connector may further include a second connector that may be communicatively coupled to the first connector. The extension connector may further include a third connector that may be communicatively coupled to the first connector and the second connector.
US09246285B2 Network jack with backwards capability and systems using same
The present invention relates to the field of telecommunication jacks, and more specifically, to network jacks adapted for operating with more than one type of a plug. In an embodiment, the present invention is a communication connector that includes a housing configured to receive a communication plug, a printed circuit board connected to the housing, and a rocker switch pivotally connected to the housing, the rocker switch configured for actuating the printed circuit board. In a variation of this embodiment, the communication connector could be used in a communication system having communication equipment therein.
US09246283B2 Connector terminal and electrical connector
A socket terminal includes a movable portion that includes a first extension that extends from a position near a fixed housing in an insertion/extraction direction of a plug connector, a hairpin portion that is continuous with the first extension, and a second extension that is continuous with the hairpin portion and that extends in the insertion/extraction direction toward a movable housing. The movable portion elastically supports the movable housing in such a way that the movable housing is displaceable relative to the fixed housing. The second extension of the movable portion includes a spring portion that is bent in such a way that the width of a gap between the second extension and a base at one end portion of the second extension continuous with the hairpin portion is larger than that at the other end portion of the second extension continuous with the base.
US09246282B1 Electrically conducting, environmentally sealing, load transferring cable termination fitting
A corrosion resistant, environmentally sealing, swaged-on conductive fitting for a coaxial cable is provided. The cable has inner and external conductors. A stepped intermediate ring is fitted over exposed lengths of trimmed layers of the inner conductor and abuts a trimmed end of a jacket that covers the inner conductor. An inner ring having a socket with interior recessed circumferential grooves is placed over and swaged against the intermediate ring so that the grooves overlap the cable's jacket and are embossed into and anchor the inner ring to the jacket. The external conductor is anchored between the inner ring and an outer ring when the outer ring is swaged. An electrically conductive path is provided from said external conductor through the inner and intermediate rings to the inner conductor without exposing the inner conductor to a corrosive environment.
US09246281B1 Receptacle/plug assembly
An authorized electrical plug has a plug surface with first and second plug edges and left and right side plug edges. The plug surface has left and right prongs projecting outwardly from the plug surface. A recess has a depth formed in the plug surface. An authorized electrical receptacle has a receptacle surface with first and second receptacle edges, left and right side receptacle edges, and left and right slots extending inwardly. A projection has a height formed in the receptacle surface. Left and right slots receive the left and right prongs respectively with the recess receiving the projection when an authorized electrical receptacle receives an authorized electrical plug.
US09246278B1 Connector module with cable exit region gasket
A connector module includes a housing, a cable, and a gasket. The housing is defined by a first shell and a second shell that mate at a seam. The housing includes a cable exit region defining a passage from a cable opening to an interior chamber of the housing. The cable is coupled to and extends from the cable exit region of the housing. A passage segment of the cable is disposed within the housing along the passage. A distal end of the cable is disposed within the interior chamber. The gasket is helically wrapped around the passage segment of the cable and positioned within the cable exit region of the housing. As the first and second shells are mated, the gasket seals the passage between an outer perimeter of the passage segment of the cable and an inner surface of the cable exit region.
US09246267B2 Connector mateable with a mating connector including a mating shell and having a mated-state maintaining structure
A connector is mateable with a mating connector including a mating shell. The connector includes a maintaining member. The maintaining member has a first portion and a second portion. The first portion has a first arm and a first maintaining portion supported by the first arm. The second portion has a second arm and a second maintaining portion supported by the second arm. When the connector and the mating connector are mated with each other, a side portion of the mating shell is inserted between a front end of the first portion and a front end of the second portion. When the connector is in a mated state where the connector is mated with the mating connector, the maintaining member holds the side portion of the mating shell by the first maintaining portion and the second maintaining portion to maintain the mated state.
US09246266B2 Plug-connectable equipment combination
A plug-connectible equipment combination has a plug module and an equipment socket with a latching connection. A rotation point is formed on the plug module between an attachment on the housing side for a latching arm and the latching catch of the latching arm. A pivoting section is formed between the rotation point and the latching catch and an actuating section for exerting pressure is formed between the rotation point and the attachment of the latching arm on the housing. The pivoting section of the latching arm pivots outwards about the rotation point and the latching catch is released from the mating latch.
US09246265B2 Notched contact for a modular plug
A metallic contact for insertion into a modular telecommunications plug includes a generally planar body defining a top end, a bottom end, a front end, a rear end, and a length extending from the front end to the rear end. The bottom end is at least partially defined by a blade for piercing an insulation of a wire positioned within the plug. At least a portion of the top end is configured to electrically contact a conductor of a jack that receives the plug. The top end is defined at least in part by a first engagement surface that is separated from a second engagement surface by a notch. An uppermost portion of the first engagement surface defines a first push surface that is generally at the same height as a second push surface defined by an uppermost portion of the second engagement surface. The notch is defined by a front vertical wall spaced from a rear vertical wall, wherein the front vertical wall is positioned at a distance of at least half the length of the contact from the front end of the contact.
US09246257B2 Connector
An electrical connector housing is disclosed having a first housing member, and a second housing member mated with the first housing member. A front wall is disposed on an outer surface of at least one of the housing members and extends perpendicular to an insertion direction. A first sidewall is disposed on the outer surface of the first housing member and extends along the insertion direction, perpendicular to the front wall. A second sidewall is disposed on the outer surface of the second housing member and extends along the insertion direction, parallel with the first sidewall and perpendicular to the front wall. A cantilevered first lock arm extends along an insertion direction and is positioned between the first sidewall and second sidewall. The lock arm includes a fixed end, a free end, and a hook.
US09246253B1 Connector with stabilization members and method of assembly
An embodiment is directed to a method and a connector for mounting on a substrate. Terminal receiving recesses extend through a bottom wall of the connector. Contacts are positioned in the terminal receiving recesses. The contacts have securing sections for securing the contacts in the terminal receiving recesses and substrate mating sections which extend from the bottom wall of the housing in a direction away from the top wall. At least one stabilization member extends from the bottom wall of the housing in a direction away from the top wall. The at least one stabilization member is movable between a first position and a second position. The at least one stabilization member engages the substrate when the at least one stabilization member is in the first position to maintain the connector in a stable position relative to the substrate.
US09246252B2 Electrical connector having a thermal washer around a plurality of cages enclosing a plurality of housings on a circuit board
A connector system includes a plurality of housing mounted on a circuit board and a plurality of cages are provided, each cage enclosing one of the housings, each of the cages including a front face that defines a first port, the cages being spaced apart a predetermined distance. A thermal washer is positioned around the cages, the thermal washer including a front portion and a main portion with air apertures that allow air to flow through the thermal washer and along a gap between the cages.
US09246248B2 Motor vehicle power conductor having a metallic flat conductor enclosed by an insulation and a bent jump-start connection point
A motor vehicle power conductor (1) is described and illustrated, in particular a battery conductor of a motor vehicle, having a first end (3) on the battery side and having a second end (4), wherein the motor vehicle power conductor (1) has a metallic flat conductor (2) and an insulation (8) enclosing the metallic flat conductor (2). In order to provide a connection means for a jump-start device in a simple and cost-effective way, it is proposed that the motor vehicle power conductor (1) is formed in one area as a jump-start connection point (5).
US09246247B2 Surface mount zipcord connector and method of making electrical contact with zipcord conductors
A surface mount connector includes one or two spaced conductive contacts. Each conductive contact(s) include a substantially flat base portion suitable for soldering to a pad or land on a printed circuit board (PCB), At least one vertical finger extends substantially normally from each flat base portion and each terminates in a point or hook formed with a piercing tip at the free end thereof remote from the that base portion. The vertical finger(s) and flat base portion(s) define a space for receiving an insulated conductor arranged in a plane substantially parallel to the plane of the flat base portion(s). The finger(s) are directed inwardly at their free end(s) proximate to the piercing tip(s) and configured to deflect inwardly in a curling action when forced downwardly and crimped to pierce an associated insulated conductor positioned on the flat base portion(s).
US09246241B2 Crimping structure
A crimping structure includes a crimping terminal that has a base plate and a crimping blade part on the base plate, a coated electric wire that has a conductor which is electrically connected to the crimping blade part by crimping the coated electric wire to the crimping blade, and is bend to be formed into a mountain-like shape whose top part is a connecting part where the conductor and the crimping blade part are connected, and an insulative resin part that covers a part of the coated electric wire from the top part to hem parts at two sides of the mountain-like shape and the crimping blade part.
US09246240B2 Electrical connector assembly with detachable pivot shaft and pivot hub with insert
An electrical cable connector assembly comprising a top pivot shaft and a base pivot hub having an insert with fixture conductor channels form fitted on the base pivot hub to hold the fixture conductor wires. The top pivot shaft interlocks with the base pivot hub at one end and upon rotation at ninety degrees the connector assembly is closed completely. Upon closure with nominal hand force, a pair of metal conductor pins molded to the top inside end of the top pivot shaft easily penetrates the fixture conductor wires held in the insert and the source conductor wire held in the source conductor wire channel in the base pivot hub, to connect the two sets of conductors electrically. The small diameter of circumference at the mid section of the uniquely designed cable connector allows for the use of an optional closure to secure the cable connector in place.
US09246238B2 System for controlling a radiation pattern of a directional antenna
The present system relates to radiation pattern control. More particularly, the present system is adapted for controlling a radiation pattern of a directional antenna. The system comprises a sample collection unit, a power angular spectrum estimation unit and a control unit. The sample collection unit is adapted for collecting a plurality of samples of a signal with a current radiation pattern and a plurality of samples of the signal with different radiation patterns. The power angular spectrum estimation unit is adapted for estimating a preliminary spectrum of the signal based on the collected plurality of samples with the current radiation pattern and for estimating an optimized spectrum of the signal based on the collected plurality of samples with different radiation patterns. Then, the control unit sets the radiation pattern of the directional antenna to the estimated optimized spectrum.
US09246236B2 Dual-polarization radiating element of a multiband antenna
A dual-polarization radiating element for a multiband antenna comprises a support with a high dielectric constant whose shape is roughly cylindrical, having an axis of revolution, at least a first and a second pair of dipoles printed on a first surface of the support, the dipoles of the first pair being roughly orthogonal to the dipoles of the second pair, and conductive lines, to feed each dipole, printed onto a second surface of the support. The support is placed on a flat reflector, with the cylindrical support's axis of revolution being perpendicular to the plane of the reflector.
US09246228B2 Multiband composite right and left handed (CRLH) slot antenna
An antenna device includes a substrate having a first surface and a second surface. A first conductive layer is formed on the first surface of the substrate, the first conductive layer having a perimeter defined by one or more shapes having straight or curved edges. The first conductive layer defines a slot and a coupling gap, and also includes a top ground. The coupling gap separates the top ground from a metal plate region. A second conductive layer is formed on the second surface of the substrate, the second conductive layer including a bottom ground. The slot, coupling gap, first conductive layer, and substrate form a composite right and left handed (CRLH) structure.
US09246227B2 Horn antenna device and step-shaped signal feed-in apparatus thereof
The present invention relates to a horn antenna device. The horn antenna device has a step-shaped signal feed-in apparatus and a conical horn antenna. The step-shaped signal feed-in apparatus has a stepped body having multiple stairs and a connecting pin. The stepped body is adapted to radiate electromagnetic waves and receive a reflection of the electromagnetic waves. According to the structure of the step-shaped signal feed-in apparatus of the invention, the resonating modes are easy to be determined. The directivity and the signal-to-noise rate are improved. In addition, the connecting pin is directly connected to the stairs for improving the signal stability of the horn antenna device.
US09246224B2 Broadband antenna system allowing multiple stacked collinear devices and having an integrated, co-planar balun
A broadband antenna system is disclosed. The antenna system relates to a cylindrical structure, wherein the feed region comprises segmented radiators with tapered feed points, distributed around the circumference of the structure, and a balun that is co-planar with the cylindrical structure. This allows a plurality of feed lines, cables, piping, or other structures to be run through the center of the antenna without interfering with the performance of the antenna system. Segmentation of the radiators permits the integration of a corporate feed network, suppresses overmoding, and permits operation without the need for a ground plane. The invention further relates to a stacked broadband antenna system wherein additional antenna elements or devices may be stacked collinearly on the antenna structure and operated via the plurality of feed lines or other structures. The overall system thus provides a wide range of transmitting, receiving, sensing and other capabilities over a virtually infinite bandwidth.
US09246221B2 Tunable loop antennas
Electronic devices are provided that contain wireless communications circuitry. The wireless communications circuitry may include radio-frequency transceiver circuitry and antenna structures. A parallel-fed loop antenna may be formed from portions of a conductive bezel and a ground plane. The antenna may operate in multiple communications bands. The bezel may surround a peripheral portion of a display that is mounted to the front of an electronic device. The bezel may contain a gap. Antenna feed terminals for the antenna may be located on opposing sides of the gap. A variable capacitor may bridge the gap. An inductive element may bridge the gap and the antenna feed terminals. A switchable inductor may be coupled in parallel with the inductive element. Tunable matching circuitry may be coupled between one of the antenna feed terminals and a conductor in a coaxial cable connecting the transceiver circuitry to the antenna.
US09246220B2 Full-band antenna
A full-band antenna includes a dielectric layer, and a first and a second patterned conductive layer provided on the dielectric layer. The first patterned conductive layer includes a feed portion and a loop portion outwardly extended from the feed portion. The loop portion defines a plurality of radiation sections, between which a multi-coupling effect is created to form at least one variable frequency. The second patterned conductive layer includes a conductive portion and a short-circuit portion. The conductive portion forms at least one fixed frequency. The at least one variable frequency of the loop portion can be adjusted in its frequency distribution and frequency range by changing a width of the radiation sections and a spacing distance between the radiation sections.
US09246217B2 Adjusting mechanism and related antenna system
An adjusting mechanism includes a base, a supporter, a connecting component and a jointing component. A slide slot is formed on the base. The supporter is pivotally connected to the base via a shaft. The connecting component is rotatably and slidably disposed on the slide slot on the base. A curved slot is formed on the connecting component. The jointing component is disposed on the supporter and slidably inserts to the curved slot on the connecting component. The connecting component slides relative to the supporter via the jointing component along a direction of the curved slot to simultaneously rotate the supporter relative to the base.
US09246216B2 System and method for adaptive beam forming for specific absorption rate control
A system may include a modifiable mobile device having at least two antennas coupled to fractional amplifiers, with returned power detectors. A beamformer unit provides adaptive beam shaping pattern, and a baseband processor provides beam pattern requirements, wherein the beamformer unit modifies the beam pattern requirements with return loss sampling information to shape the adaptive beam pattern so that a transmitted beam pattern minimizes transmitted power reflected back to the mobile device. A method may include regularly measuring a return power level, if output power is greater than a specific absorption rate level, comparing the return power level to a first threshold, else implementing mobile transmit diversity (MTD), and repeating. If the return power level is greater than the first threshold, implementing a MTD combined with reflection-based beamforming that modifies beam pattern requirements of the mobile device with return loss sampling information to create an adaptive beam pattern.
US09246214B2 Electronic device antenna structures with ferrite layers
Electronic devices may be provided that have antenna traces. The antenna traces may be configured to form an inductive loop that serves as a near field communications antenna. A layer of ferrite may be provided to reduce interference between the antenna and internal device components. The layer of ferrite and the antenna traces may be deposited on a common substrate such as a layer of polymer or a dielectric electronic device housing. A protective layer of polymer may be used to form a coating on the layer of ferrite. Ferrite may be formed on the same side of a substrate as the antenna traces or may be formed on an opposing side of the substrate.
US09246211B2 Portable electronic device and method for tuning an antenna
A portable electronic device and method for tuning an antenna is provided. The portable electronic device includes an antenna, a tunable element, a first input unit, at least one additional input unit, and a processor. The method involves receiving a first set of data, determining a plurality of possible physical states, activating a second input unit, receiving a second set of data from the second input unit, selecting a physical state of the portable electronic device from the plurality of possible physical states, and tuning the antenna based on the physical state of the portable electronic device.
US09246207B2 Antenna aiming system and method for broadband wireless access
A system and method are provided for automatically aiming an antenna to communicate with a remote broadband wireless communication device.
US09246202B1 Low impedance circulator
A circulator may include a first port having a first port impedance matching circuit defining an impedance of the first port, a second port having a second port impedance matching circuit defining an impedance of the second port, and a third port having a third port impedance matching circuit defining an impedance of the third port. In an example embodiment, the impedance of the first port may be provided to match an impedance of a first external circuit, the impedance of the second port may be provided to match an impedance of a second external circuit, and the impedance of the third port may be provided to match an impedance of a third external circuit. The impedance of the third port may be different than the impedance of the first port.
US09246201B2 Battery temperature control device
Even when temperature sensors (12, 13) used in a device for warming a battery (1) being not in use by using a battery-driven heater (2) have failed, the battery (1) is prevented from freezing. Based on a battery temperature (Tb) and an outside air temperature (Ta), times (Δt1 to Δt8) during which Tb will decrease down to a warming start temperature (Tb_start) are each set to the next controller startup time (Δt). A controller (9) is started up every Δt, at t2, t3, and t4, and checks whether Tb
US09246200B2 Battery module receiving apparatus, battery module thermostat, and power storage system comprising the same
Disclosed is a battery module receiving apparatus of a rectangular parallelepiped shape having an inner space with the open front and rear, in which a plurality of battery cell insertion slots are formed at corresponding locations on the upper plate and the lower plate constituting the inner space to erectly insert a plurality of battery cells, and a plurality of heat transfer plate insertion slots are formed adjacent to a plurality of the battery cell insertion slots to erectly insert a plurality of heat transfer plates. A battery pack and a stack-type power storage system may be implemented by inserting a battery module through the front of the battery module receiving apparatus and a battery module thermostat through the rear of the battery module receiving apparatus.
US09246197B2 Battery system and driving method thereof
A battery system capable of cooling overheated battery packs among a plurality battery packs each mounted in a battery case by measuring temperatures of the battery packs is disclosed, and a driving method thereof is provided. In one embodiment, the battery system includes a plurality of battery packs, an air compressor for supplying a compressed cooling air to the plurality of battery packs, a gas dividing unit coupled between the plurality of battery packs and the air compressor and including a plurality of valves, and a controller for controlling opening and closing of each of the plurality of valves according to temperatures of the plurality of battery packs.
US09246194B2 Device for folding electrode assembly
Disclosed herein is a folding device to manufacture a stacked/folded type electrode assembly having unit cells sequentially stacked in a state in which a separation film is disposed between the respective unit cells, the folding device including a web supply unit to supply a web having plate-shaped unit cells arranged at the top of a separation film at predetermined intervals, a winding jig to rotate the unit cells while holding a first one of the unit cells of the web so that the unit cells are sequentially stacked in a state in which the separation film is disposed between the respective unit cells, and a Y-axis directional rotary shaft compensation unit to compensate for a position of a rotary shaft of the winding jig in a direction (Y-axis direction) perpendicular to an advancing direction of the web, wherein the Y-axis directional rotary shaft compensation unit periodically changes the position of the rotary shaft in the direction (Y axis) perpendicular to the advancing direction (X axis) of the web to minimize vertical amplitude of the web during winding.
US09246191B2 Non-aqueous electrolyte lithium secondary battery
A lithium secondary battery has an anode, a cathode, a separator between the anode and the cathode and a non-aqueous electrolyte. The non-aqueous electrolyte includes a lithium salt; and a non-linear carbonate-based mixed organic solvent in which (a) a cyclic carbonate compound, and (b) a propionate-based compound are mixed at a volume ratio (a:b) in the range from about 10:90 to about 70:30. The cathode has a capacity density in the range from about 3.5 to about 5.5 mAh/cm2 and a porosity in the range from about 18 to about 35%. This battery may be manufactured as a high-loading lithium secondary battery.
US09246189B2 Secondary battery including electrolyte additive
Disclosed is a secondary battery including a cathode, an anode, and an electrolyte including a lithium salt and a non-aqueous organic solvent, wherein the electrolyte includes an electrolyte additive to be decomposed at 4.5 V or higher to less than 5.5 V vs. reduction voltage of Li+.
US09246185B2 Electrochemical cell having a folded electrode and separator, battery including the same, and method of forming same
An electrochemical cell including a folded electrode layer and a folded separator, a battery including the electrochemical cell, and methods of forming the electrochemical cell and battery are disclosed. The electrode layer is folded in a first direction and the separator is folded in a second direction, such that the first direction and second direction are orthogonal each other.
US09246183B1 Methods and materials for use with fuel cells
A composition of matter is configured for use as at least a part of an energy source when combined with water. The composition of matter includes a metal comprising gallium and aluminum that is alloyed with the metal. The metal comprising gallium is liquid at a room temperature of 70° F. and at a standard atmospheric pressure of 14.7 psi.
US09246177B2 Bimetallic alloy electrocatalysts with multilayered platinum-skin surfaces
Compositions and methods of preparing a bimetallic alloy having enhanced electrocatalytic properties are provided. The composition comprises a PtNi substrate having a surface layer, a near-surface layer, and an inner layer, where the surface layer comprises a nickel-depleted composition, such that the surface layer comprises a platinum skin having at least one atomic layer of platinum.
US09246175B2 Composite support, method of preparing the same, electrode catalyst including the composite support, and membrane-electrode assembly and fuel cell each including the electrode catalyst
A composite support including: an ordered mesoporous carbon including mesopores having an average diameter of about 2 nanometers to about 8 nanometers; and silicon carbide dispersed in the ordered mesoporous carbon.
US09246174B2 Lithium ion battery
It is an object of this exemplary embodiment to provide a lithium ion battery using a lithium manganese complex oxide, in which the dissolution of manganese and resistance increase are inhibited, and which is excellent in life characteristics at high temperature. One aspect of this exemplary embodiment is a lithium ion battery comprising at least a positive electrode comprising a positive electrode active material, and an electrolytic solution, wherein the positive electrode active material is a lithium manganese complex oxide, the positive electrode comprises a bismuth oxide, and a metal compound attached to part of a surface of the lithium manganese complex oxide, and a dissolution rate of a metal of the metal compound in the electrolytic solution is lower than a dissolution rate of manganese of the lithium manganese complex oxide.
US09246173B2 Process for synthesis of hybrid siloxy derived resins and crosslinked networks therefrom
A hybrid siloxy derived resin and a method of making them and a method of applying them as a benign passivant on electrochemical electrodes is provided. These resins are made by the process of reacting a silane and an alkaline, transition metal or metalloid alkoxide, in the presence of a lewis acid. The methods described do not require further purification steps; heat; or strong acid/base catalysis to initiate hydrolysis.
US09246172B2 Cathode material for lithium ion secondary batteries, cathode member for lithium ion secondary batteries, and lithium ion secondary battery
A cathode material for a lithium ion secondary battery includes an oxide represented by a composition formula Li2-xMIIyM(Si,MB)O4, wherein MII represents a divalent element; M represents at least one element selected from the group consisting of Fe, Mn, Co and Ni; and MB represents, as an optional component, an element substituted for Si to compensate for a difference between an electric charge of [Li2]2+ and an electric change of [Li2-xMIIy]n+ as needed. In the composition formula representing the oxide, x and y are −0.25
US09246166B2 Composite cathode active material, cathode and lithium battery including the composite cathode active material, and preparation method thereof
In an aspect, a composite cathode active material a cathode and a lithium battery including the composite cathode active material, and a method of preparing the composite cathode active material is disclosed.
US09246159B2 Electrode for lithium ion batteries
An electrode for lithium ion batteries, the electrode having a metal film which is inert to lithium ions and having a plurality of silicon nanowires protruding from the film, which are arranged on at least one flat side of the film, wherein sections of the nanowires are enclosed by the metal film.
US09246156B2 Waterproof battery pack
A battery pack for an electric bicycle is disclosed. In one embodiment, the battery pack includes i) a lower case having a top, a bottom and an interior space formed between the top and bottom and ii) a battery cell placed in the interior space of the lower case, wherein the battery cell has first and second surfaces opposing each other, and wherein the first surface of the battery cell is closer to the bottom of the lower case than the second surface of the battery cell. The battery pack may further include i) a protection circuit board mounted on the second surface of the battery cell and placed in the interior space of the lower case, ii) an upper case formed over the top of the lower case and iii) a separator case formed between the protection circuit board and the upper case.
US09246151B2 Electrical connection assembly, battery device and electronic apparatus
An electrical connection assembly is provided to electrically connect with at least one electrical contact of an electronic apparatus. The electrical connection assembly includes an insulating casing, a circuit board and a resilient conductive element. An inner space is defined in the insulating casing, and at least one opening is defined on the insulating casing for communicating the inner space and the exterior of the insulating casing. The circuit board is disposed in the inner space of the insulating casing. The resilient conductive element includes a connecting side for fixing on and electrically connecting with the circuit board. The resilient conductive element further includes a compressible side for facing the opening and being exposed therethrough. The thickness of the resilient conductive element is reduced when an external force is applied thereon and recovers when the external force is removed.
US09246150B2 Non-aqueous electrolyte battery
A non-aqueous electrolyte battery in which formation of a flame retardant layer formed on the surface of an electrode or the like hardly affects the discharge characteristics is provided. A non-aqueous electrolyte battery 1 includes a positive electrode 3, a negative electrode 5, and a separator 7. A porous layer having ion permeability is formed using a flame retardant material on a surface of the positive electrode 3. The porous layer is formed by applying a hot melt, which is a fused flame retardant material made of a thermoplastic resin, to the surface of the positive electrode 3.
US09246146B2 Battery pack
A battery pack including a plurality of battery cells; a housing accommodating the plurality of battery cells; a connector coupled to the housing, at least a portion of the connector being exposed outside of the housing; and a sealing member coupled to the connector, the sealing member surrounding the exposed portion of the connector.
US09246144B2 Battery pack and method for manufacturing the same
A battery pack and a method for manufacturing the same are provided, which can protect a plurality battery cells from external shock or vibration by preventing the plurality battery cells from moving within a case. The battery pack includes a plurality of battery cells, a case accommodating the battery cells and including a plurality of injection holes, and a shock absorbing member integrally formed at the outside and inside of the case so as to penetrate the injection holes and supporting the battery cells.
US09246141B2 Secondary battery
A secondary battery including an electrode assembly; a case accommodating the electrode assembly; a cap plate covering the case; and an electrode terminal electrically connected to the electrode assembly, wherein the cap plate includes at least one bending induction groove at a periphery of a central portion of the cap plate in a region between an edge and the central portion of the cap plate.
US09246136B2 Array substrate and manufacturing method thereof
Embodiments of the present invention disclose a method for manufacturing an array substrate comprising: forming patterns of a thin film transistor structure and a passivation layer on a base substrate to define a plurality of pixel units on the base substrate; forming subsequently patterns of a transflective layer and a color filter in a pixel region of the pixel unit, the color filter being disposed above the transflective layer; forming an organic light-emitting diode in the pixel region of the pixel unit so that the transflective layer and the color filter are disposed between the organic light-emitting diode and the thin film transistor structure. Embodiments of the present invention also provide an array substrate.
US09246135B2 Organic layer deposition apparatus, method of manufacturing organic light-emitting display apparatus using the same, and organic light-emitting display apparatus manufactured using the method
An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display device by using the same, and an organic light-emitting display device manufactured using the method, and in particular, an organic layer deposition apparatus that is suitable for use in the mass production of a large substrate and enables high-definition patterning, a method of manufacturing an organic light-emitting display device by using the same, and an organic light-emitting display device manufactured using the method.
US09246133B2 Light-emitting module, light-emitting panel, and light-emitting device
One embodiment of the present invention relates to a light-emitting device comprising an insulating surface; a lower electrode over the insulating surface; a protrusion over the insulating surface having a sidewall sloping toward the lower electrode; a light-transmitting partition overlapping with an end portion of the lower electrode and the sidewall of the protrusion; and a light-emitting element including the lower electrode, an upper electrode overlapping with the lower electrode, and a layer containing a light-emitting organic compound between the lower electrode and the upper electrode. In the light-emitting device, the sidewall of the protrusion can reflect light emitted from the light-emitting element. As a result, the light-emitting device that has reduced power consumption is provided.
US09246130B2 Organic electroluminescence display device
An organic electroluminescence display device includes a thin film transistor substrate and a counter substrate, in which the thin film transistor substrate includes: a moisture blocking area that surrounds an outside of the display area and is made of only an inorganic material between the first substrate and the sealing film, and an auxiliary area between the display area and the moisture blocking area, and a thickness of areas of the counter substrate opposite to the auxiliary area and the moisture blocking area is thinner than a thickness of an area of the counter substrate opposite to the display area.
US09246129B2 Display device
A display device is disclosed. In one aspect, the device includes a first substrate in which an image displaying area and a non-displaying area are formed, a second substrate facing the first substrate, a first electrode formed over the first substrate, an emission layer formed over the first electrode and a second electrode formed over the emission layer. The device further includes a sealing member interposed between the non-displaying area of the first substrate and the second substrate, a reinforcement member interposed between the non-displaying area of the first substrate and the second substrate, the reinforcement member being adjacent to the sealing member and at least one spacer formed adjacent to the reinforcement member.
US09246126B2 Organic light emitting diode display
An OLED display is disclosed. The display includes a rear substrate, a front substrate facing the rear substrate, a cell seal provided between the rear and front substrates to adhere the two substrates to each other, and a reinforcement member provided between the rear and front substrates adjacent to the cell seal to adhere the two substrates to each other.
US09246125B2 Organic light-emitting diode display
An organic light-emitting diode display including: a display panel; a bezel on which the display panel is mounted; and a buffer disposed between a lower surface of the display panel and the bezel. The buffer includes a peripheral buffer and a central buffer that has a step-shaped structure. The peripheral buffer is disposed at first and second sides of the central buffer.
US09246124B2 Carrier for flexible substrate, substrate processing apparatus including the carrier, and method of manufacturing flexible display apparatus
Provided is a carrier for a flexible substrate which is capable of handling a flexible substrate during a flexible substrate processing process, while allowing the flexible substrate to be easily separated. Also provided is a substrate processing apparatus, including the carrier, and a method of manufacturing a flexible display apparatus. The carrier includes a substrate supporting portion having a top surface including a mounting surface, an outer circumferential surface, surrounding the mounting surface, and a first heat cutting portion. The first heat cutting portion is located outside the mounting surface so as to be exposed on the top surface and generates heat when a current flows through the first heat cutting portion.
US09246123B2 Organic light-emitting display device and method of manufacturing the same
Provided is an organic light-emitting display device comprising a substrate, an insulating layer disposed on the substrate, a first electrode disposed on the insulating layer, an organic layer disposed on the first electrode, a second electrode disposed on the organic layer, an auxiliary electrode disposed on the insulating layer and a metal layer disposed adjacent to the auxiliary electrode and connected to the auxiliary electrode and the second electrode.
US09246121B2 Organic light-emitting diode
In at least one embodiment, the organic light-emitting diode (10) comprises a carrier substrate (1) and a first electrode (21). Furthermore, the organic light-emitting diode (10) comprises an organic layer sequence (3) having at least one active layer (30) for generating an electromagnetic radiation. The organic layer sequence (3) is situated at a side of the first electrode (21) which faces away from the carrier substrate (1). Moreover, the organic light-emitting diode (10) comprises a second electrode (22), which is mounted at a side of the organic layer sequence (2) which faces away from the carrier substrate (1). Furthermore, the organic light-emitting diode (10) comprises a protective diode (4) designed for protection against damage from electrostatic discharges. The protective diode (4) is mounted on the carrier substrate (1) and is situated at the same main side (11) of the carrier substrate (1) as the organic layer sequence (3).
US09246117B2 Modulatable light-emitting diode
Described is an (organic) light-emitting diode ((O)LED) wherein the light-emitting layer comprises a blend of an electroluminescent semiconducting material with a ferro-electric material. Either of the electrodes forms a modulatable injection barrier with the ferro-electric material, the modulation requiring a voltage Vm serving to polarize or repolarize the ferro-electric material. With Vm being larger than the voltage Ve required for light emission, the (O)LED can be turned “on” or “off” by applying a pulse voltage to (re)polarize the ferro-electric material.
US09246115B2 Organic solar cell and method of manufacturing the same
An organic solar cell and a method of manufacturing the same.
US09246114B2 Organic optoelectronic component and use of a transparent inorganic semiconductor in a charge carrier pair generating layer sequence
Various embodiments may relate to an organic optoelectronic component with a layer structure for generating and separating charge carriers of a first charge carrier type and charge carriers of a second charge carrier type, the layer structure including a hole-conducting transparent inorganic semiconductor.
US09246111B1 Organic light-emitting device
An organic light-emitting device including a first electrode; a second electrode; and an organic layer, the organic layer including an emission layer, a hole transport region including a hole transport layer, a hole injection layer, or a buffer layer, and an electron transport region including a hole blocking layer, an electron transport layer, or an electron injection layer, wherein a triplet energy of a hole transport material of the hole transport layer is from about 2.4 to about 3.2 eV, an electron affinity of the hole transport material is from about 2.2 to about 2.6 eV; the triplet energy of the hole transport material is greater than a triplet energy of a dopant of the emission layer and a triplet energy of a host material of the emission layer, the host material of the emission layer includes the compound represented by Formula 1.
US09246110B2 Organic material and photoelectric conversion element
An organic material represented by the following General Formula (1): where in the General Formula (1), R1 and R2, which may be identical to or different from each other, each represent an alkyl group having 4 to 24 carbon atoms, X represents a substituted or unsubstituted aromatic hydrocarbon group, Y represents an aromatic hydrocarbon group, an alkoxyl group, or an alkyl group, which may be substituted with a substituent, and n represents an integer of 1 to 3.
US09246105B2 Fluorinated aromatic materials and their use in optoelectronics
Fluorinated aromatic materials, their synthesis and their use in optoelectronics. In some cases, the fluorinated aromatic materials are perfluoroalkylated aromatic materials that may include perfluoropolyether substituents.
US09246097B2 Diffusion barrier layer for resistive random access memory cells
Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.
US09246093B2 Phase change memory cell with self-aligned vertical heater and low resistivity interface
A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change chalcogenide material is deposited directly on the vertical heater element. In an embodiment, the vertical heater element in L-shaped, having a curved vertical wall along the wordline direction and a horizontal base. In an embodiment, the low resistivity interface material is deposited into a trench with a negative profile using a PVD technique. An upper surface of the low resistivity interface material may have a tapered bird-beak extension.
US09246089B2 Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.
US09246088B2 Semiconductor memory device having a variable resistance layer serving as a memory layer
A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
US09246086B2 Conductive bridge memory system and method of manufacture thereof
A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer.
US09246078B2 Piezoelectric apparatuses, systems and methods therefor
Various aspects as described herein are directed to piezoelectric materials. As consistent with one or more embodiments, an apparatus includes a nanomaterial and structures coupled to the nanomaterial. This nanomaterial-structure combination manifests piezoelectric characteristics, via the combination. In certain implementations, neither the nanomaterial nor the coupled structures independently exhibit piezoelectric characteristics, yet do so in combination.
US09246077B2 Ultrasonic transducer device, head unit, probe, and ultrasonic imaging apparatus
An ultrasonic transducer device includes an ultrasonic transducer element array, a first signal terminal, and a second signal terminal. The ultrasonic transducer element array has a 1st element group to a kth element group (where k is a natural number such that k≧2). The first signal terminal is connected with a control section configured and arranged to perform at least one of receiving and transmitting of signals. The second signal terminal is connected with the first signal terminal via the ultrasonic transducer element array. Each of the 1st element group to the kth element group includes a plurality of ultrasonic transducer elements electrically connected in series. The 1st element group to the kth element group are electrically connected in parallel between the first signal terminal and the second signal terminal.
US09246076B2 Thermoelectric conversion module and production method therefor
A production method for a thermoelectric conversion module having a thermoelectric conversion element and an electrode, which are metallurgically bonded together via a porous metal layer. The porous metal layer is made of nickel or silver and has a density ratio of 50 to 90%.
US09246071B2 Manufacturing method of grating
The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a photoresist film is formed on a surface of the substrate. Third, a nano-pattern is formed on the photoresist film by nano-imprint lithography. Fourth, the photoresist film is etched to form a patterned photoresist layer. Fifth, a mask layer is covered on the patterned photoresist layer and the surface of the substrate exposed to the patterned photoresist layer. Sixth, the patterned photoresist layer and the mask layer thereon are removed to form a patterned mask layer. Seventh, the substrate is etched through the patterned mask layer by reactive ion etching, wherein etching gases includes carbon tetrafluoride, sulfur hexafluoride, and argon. Finally, the patterned mask layer is removed.
US09246063B2 Phosphor encapsulating sheet, light emitting diode device, and producing method thereof
A phosphor encapsulating sheet, for encapsulating a light emitting diode element, includes a phosphor layer, an encapsulating layer formed at one side in a thickness direction of the phosphor layer, and an adhesive layer formed at the other side in the thickness direction of the phosphor layer for being adhered to a cover layer.
US09246061B2 LED having vertical contacts redistruted for flip chip mounting
A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-Type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.
US09246056B2 Light emitting device
It is an object of the present invention to provide a light-emitting device in which, even when a material with high reflectivity such as aluminum is used for an electrode, a layer containing oxygen can be formed over the electrode without increasing contact resistance and a manufacturing method thereof. According to the present invention, a feature thereof is a light-emitting element having an electrode composed of a stacked structure where a conductive film having high reflectivity such as aluminum, silver, and an alloy containing aluminum or an alloy containing silver, and a conductive film composed of a refractory metal material is provided over the conductive film, or a light-emitting device having the light-emitting element.
US09246054B2 Light emitting device having light extraction structure and method for manufacturing the same
A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.
US09246052B2 Packaging structure of light emitting diode and method of manufacturing the same
The present disclosure relates to a light emitting diode packaging structure and the method of manufacturing the same. The light emitting diode packaging structure has an insulating substrate with through holes formed on each side of the upper surface thereof, the through hole being filled with conductive metal. Additionally, a n-type layer, an active layer, a p-type layer, an insulating layer and a p-type electrode are formed on the insulating substrate. The structure further may include a n-type electrode provided on a side of the upper surface of the n-type layer; a first back electrode provided at one side of the back surface of the insulating substrate; a second back electrode provided at the other side of back surface of the insulating substrate; and an optical element packaged on the base substrate.
US09246050B2 Method for fabricating nano-patterned substrate for high-efficiency nitride-based light-emitting diode
Provided is a method of manufacturing a substrate for a light emitting diode including a convex section forming step and a crystallization/crystallizing step. According to the method and the substrate for the light emitting diode, light extraction is significantly improved and nano to micron sized pattern, economically formed.
US09246047B2 Semiconductor device
A semiconductor device in which charge capacity of a capacitor is increased without a reduction in aperture ratio is provided. In a transistor including a light-transmitting semiconductor film and a capacitor in which a dielectric film is provided between a pair of electrodes, the pair of electrodes and the dielectric film are formed using a light-transmitting material. A semiconductor film which is formed on the same surface as the semiconductor film of the transistor is used as one of the pair of electrodes. The dielectric film included in the capacitor is formed using a gate insulating film. The other of the pair of electrodes is formed using a light-transmitting semiconductor film or a light-transmitting conductive film.
US09246046B1 Etching processes for solar cell fabrication
A method of fabricating a solar cell can include forming a first dopant region over a silicon substrate and an oxide region over the first dopant region. In an embodiment, the oxide region can protect the first dopant region from a first etching process. In an embodiment, a second dopant region can be formed over the silicon substrate, where a mask can be formed to protect a first portion of the second dopant region from the first etching process. In an embodiment, the first etching process can be performed to expose portions of the silicon substrate and/or a silicon region. A second etching process can be performed to form a trench region to separate a first and second doped region of the solar cell. A third etching process can be performed to remove contaminants from the solar cell and remove any remaining portions of the oxide region.
US09246043B2 Manufacturing method of photovoltaic device and manufacturing apparatus for photovoltaic device
A manufacturing method includes a step of forming an impurity diffusion layer by diffusing an impurity element in a surface of a silicon-based substrate; and an etching step of removing the impurity diffusion layer in at least a portion of a first-surface side of the silicon-based substrate, wherein the etching step includes an etching-fluid supplying step of, on the first-surface side, supplying an etching fluid that flows to an outer edge portion of the silicon-based substrate from a supply position, and an air supplying step of, on a second-surface side, which is opposite to the first-surface side, of the silicon-based substrate, supplying air in a same direction as the etching fluid in accordance with supply of the etching fluid at the etching-fluid supplying step.
US09246037B2 Folded fin heat sink
A heat sink can include a folded fin with a base portion, an offset portion extending away from the base portion, the offset portion having a width, a narrowing tapering portion having a maximum width equal to the width of the offset portion, and an extension portion extending away from the narrowing tapering portion, the extension portion having a width smaller than the width of the offset portion.
US09246035B2 Portable solar panel power source
An apparatus and method for portable solar panel assemblies configured to enable the unit to be transported by multiple means in order to provide both grid tied and off grid power as needed. Solar panel assemblies are configured to have a range of rotation of approximately 0 to 25 degrees in two directions to allow efficient sunlight capture. The solar panel assembly in the closed position will allow for more compact and aerodynamic profile when being transported.
US09246034B2 Solar cell and method of manufacturing the same
A method of manufacturing a solar cell, including: forming a first conductivity type semiconductor layer extending along a predetermined direction on aback surface of a semiconductor substrate that has a light-receiving surface and the back surface opposite to the light-receiving surface, the first-conductivity-type semiconductor layer being divided into plural island-shaped sections arranged side by side in the predetermined direction; forming a semiconductor layer of a second conductivity type in the predetermined direction on the back surface; and forming conductive layers respectively on the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer by using a conductive paste, the conductive layer to be formed on the first-conductivity-type semiconductor layer being formed by a printing method such that the conductive layer to be formed on the first-conductivity-type semiconductor layer extends on a line of the plural island-shaped sections to bridge adjacent two of the plural island-shaped sections.
US09246033B2 Contact for silicon heterojunction solar cells
A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
US09246029B2 Method for manufacturing an interdigitated back contact solar cell
A method for manufacturing an interdigitated back contact solar cell, comprising steps of: (a) providing a doped silicon substrate; (b) doping the rear surface of the substrate homogeneously with boron in a blanket pattern, thereby forming a p+ region on the rear surface of the silicon substrate; (c) forming a silicon dioxide layer on the front and rear surface; (d) depositing a phosphorus-containing doping paste on the rear surface in a second pattern; (e) heating the silicon substrate to locally diffuse phosphorus into the rear surface of the silicon substrate, thereby forming an n+ region on the rear surface of the silicon substrate through the second pattern, wherein the p+ region and the n+ region on the rear surface collectively form an interdigitated pattern; and (f) removing the second silicon dioxide layer from the silicon substrate.
US09246024B2 Photovoltaic device with aluminum plated back surface field and method of forming same
A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other. A plurality of patterned antireflective coating layers is located on a p-type semiconductor surface of the semiconductor substrate, wherein at least one portion of the p-type semiconductor surface of the semiconductor substrate is exposed. Aluminum is located directly on the at least one portion of the p-type semiconductor surface of the semiconductor substrate that is exposed.
US09246019B2 High efficiency rectifier
A method for forming a rectifier device is provided. The method forms a first layer on a substrate, a second layer is formed on the first layer and a photoresist layer is deposited on the second layer in which a plurality of trench patterns are formed. A plurality of trenches are formed in the first layer and the second layer by etching based on the trench patterns in the photoresist. The method then laterally etches the second layer to expose a corner portion of the first layer at mesas formed in between the two trenches. A portion of the second layer is preserved at an edge of the rectifier device.
US09246018B2 Micromachined monolithic 3-axis gyroscope with single drive
This document discusses, among other things, a cap wafer and a via wafer configured to encapsulate a single proof-mass 3-axis gyroscope formed in an x-y plane of a device layer. The single proof-mass 3-axis gyroscope can include a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards an edge of the 3-axis gyroscope sensor, a central suspension system configured to suspend the 3-axis gyroscope from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 3-axis gyroscope about a z-axis normal to the x-y plane at a drive frequency.
US09246015B2 Vertical channel transistor structure and manufacturing method thereof
A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
US09246012B2 Display unit and electronic apparatus
A display unit includes: an oxide semiconductor layer configured to form a channel; a first layer having electrical insulation or electrical conductivity; and a second layer including a hydrogen absorbent and disposed between the oxide semiconductor layer and the first layer.
US09246010B2 Thin film transistor substrate
In an oxide semiconductor layer, a degree of oxidation S1 of a portion located on the side of the gate insulating film, and a degree of oxidation S2 of surface layer portions located in connection regions with source and drain electrodes have a relation of S2
US09246009B2 Semiconductor device and method for manufacturing the same
An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
US09246003B2 FINFET structures with fins recessed beneath the gate
A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.
US09245995B2 Semiconductor device having power metal-oxide-semiconductor transistor
A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity, a drain extension insulating layer on the drift region, a gate insulating layer and a gate electrode sequentially stacked across a portion of the body region and a portion of the drift region, a drain extension electrode on the drain extension insulating layer, a drain region contacting a side of the drift region opposite to the body region, the drain region having the first conductivity, and a source region in the body region, the source region having the second conductivity.
US09245989B2 High voltage field effect transistors
Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.
US09245987B2 Semiconductor devices and fabrication methods
Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.
US09245986B2 Power semiconductor device and method of manufacturing the same
A power semiconductor device may include: a base substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.
US09245984B2 Reverse blocking semiconductor device, semiconductor device with local emitter efficiency modification and method of manufacturing a reverse blocking semiconductor device
A reverse blocking semiconductor device includes a base region of a first conductivity type and a body region of a second, complementary conductivity type, wherein the base and body regions form a pn junction. Between the base region and a collector electrode an emitter layer is arranged that includes emitter zones of the second conductivity type and at least one channel of the first conductivity type. The channels extend through the emitter layer between the base region and the collector electrode and reduce the leakage current in a forward blocking state.
US09245983B2 Method for manufacturing semiconductor device
An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.
US09245980B2 Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device
One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.
US09245979B2 FinFET semiconductor devices with local isolation features and methods for fabricating the same
FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.
US09245974B2 Performance boost by silicon epitaxy
The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.
US09245971B2 Semiconductor device having high mobility channel
In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.
US09245967B2 Semiconductor device including metal silicide layer and method for manufacturing the same
A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.
US09245965B2 Uniform finFET gate height
A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.
US09245962B1 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a sacrificial pattern, forming a first stacked structure including first material layers and second material layers alternately stacked on the sacrificial pattern, forming first semiconductor patterns passing through the first stacked structure and dielectric multi-layers surrounding the first semiconductor patterns, forming a slit passing through the first stacked structure and exposing the sacrificial pattern, forming a spacer on an inner wall of the slit, forming a first opening by removing the sacrificial pattern through the slit, forming a second opening by partially removing the dielectric multi-layers through the first opening to expose lower portions of the first semiconductor patterns, and forming a connection pattern in contact with the first semiconductor patterns in the first and second openings.
US09245960B2 Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered airgap field plates
Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having tapered dielectric field plates positioned laterally between conductive field plates and opposing sides of a drain drift region of the LEDMOSFET. Each dielectric field plate comprises, in whole or in part, an airgap. These field plates form plate capacitors that can create an essentially uniform horizontal electric field profile within the drain drift region so that the LEDMOSFET can exhibit a specific, relatively high, breakdown voltage (Vb). Tapered dielectric field plates that incorporate airgaps provide for better control over the creation of the uniform horizontal electric field profile within the drain drift region, as compared to tapered dielectric field plates without such airgaps and, thereby ensure that the LEDMOSFET exhibits the specific, relatively high, Vb desired. Also disclosed herein are embodiments of a method of forming such an LEDMOSFET.
US09245958B2 Semiconductor device and method for manufacturing the same
A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided. Oxide semiconductor films are stacked so that the conduction band has a well-shaped structure. A second oxide semiconductor film having a crystalline structure is provided over the first oxide semiconductor film and a third oxide semiconductor film is provided over the second oxide semiconductor film. The bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than the bottom of a conduction band in the first oxide semiconductor film and the bottom of a conduction band in the third oxide semiconductor film.
US09245957B2 Semiconductor materials, transistors including the same, and electronic devices including transistors
According to example embodiments, a semiconductor material may include zinc, nitrogen, and fluorine. The semiconductor material may further include oxygen. The semiconductor material may include a compound. For example, the semiconductor material may include zinc fluorooxynitride. The semiconductor material may include zinc oxynitride containing fluorine. The semiconductor material may include zinc fluoronitride. The semiconductor material may be applied as a channel material of a thin film transistor (TFT).
US09245954B2 Semiconductor device and production method thereof
An aluminum material can be used on a surface of the electrode of a semiconductor element, this aluminum layer need not be formed thick unnecessarily, a copper wire is bonded strongly to the semiconductor element irrespective of a diameter of the wire, and high heat resistance can be achieved. Silicon carbide (SiC) is used as a substrate of the semiconductor element 10, the titanium layer 20 and the aluminum layer 21 are formed as the electrode 15 on the silicon carbide substrate, and by a ball bonding or a wedge bonding of the copper wire 16 to the aluminum layer 21 of the electrode 15 while applying ultrasonic wave, the copper-aluminum compound layer 23 (Al4Cu9, AlCu or the like) is formed between the copper wire 16 and the titanium layer 20.
US09245951B1 Profile control over a collector of a bipolar junction transistor
Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.
US09245949B2 Nanotube semiconductor devices
Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a semiconductor layer on a semiconductor substrate of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. In another embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.
US09245942B2 Composite substrate, electronic component, and method of manufacturing composite substrate and electronic component
A composite substrate having silicon substrate with excellent crystallinity and a method of manufacturing the composite substrate and an electronic component using the composite substrate are provided. A composite substrate (1) is configured to bond a support substrate (10) having electrical insulating property, and a silicon substrate (20) which is overlaid on the support substrate (10). The semiconductor substrate (20) of the composite substrate (1) includes a plurality of first regions (20x) in which a device function unit functioning as a semiconductor device is formed, and a second region (20y) located between these first regions (20x). In the semiconductor substrate (20) of the composite substrate (1), an amorphous form (22) containing silicon and a metal is present in the second region (20y).
US09245941B2 Electrode for low-leakage devices
A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.
US09245934B2 Organic light-emitting display apparatus having bi-directional light emission and method of manufacturing the same
An organic light-emitting display apparatus includes a plurality of pixels, a plurality of first electrodes, a plurality of second electrodes, an intermediate layer, a third electrode, an auxiliary layer, and a fourth electrode. Each pixel includes a first region that emits light in a first direction and a second region that emits light in a second direction that is opposite to the first direction. The first electrodes are respectively located in the first region of each of the pixels. The second electrodes are respectively located in the second region of each of the plurality of pixels. The intermediate layer is on the plurality of first electrodes and the plurality of second electrodes, and includes an organic emission layer. The third electrode is on the intermediate layer and in the first and second regions. The fourth electrode is in the first region and contacts the third electrode.
US09245931B2 Organic light-emitting diode (OLED) display
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels and each pixel includes a first area configured to emit light and a second area configured to transmit external light therethrough. Each pixel also includes a first electrode formed in the first area and an organic layer formed in the first area and the second area, wherein the organic layer covers the first electrode. Each pixel further includes a second electrode covering at least the organic layer formed in the first area and having a first opening exposing at least a portion of the organic layer formed in the second area. A reflection prevention layer is formed substantially covering the organic layer formed in the second area. The reflection prevention layer has a refractive index lower than that of the organic layer.
US09245930B2 Method of manufacturing display panel
A method of manufacturing a display panel includes: a first step of forming a partition wall layer above a substrate; a second step of exposing the partition wall layer using a first photomask that has a mask pattern corresponding to a blue opening; a third step of exposing the partition wall layer using a second photomask that has a mask pattern corresponding to a red opening and a green opening; a fourth step of forming a partition wall by removing the partition wall layer to form the red opening, the green opening , and the blue opening in the partition wall layer; and a fifth step of forming a light emitting layer in each opening.
US09245926B2 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
US09245920B2 Methods of driving image sensors including unit pixels having photoelectric conversion and floating diffusion regions
A method of driving an image sensor including a plurality of unit pixels, each unit pixel having photoelectric conversion and floating diffusion regions, may include resetting a potential level of the floating diffusion region by a first voltage level, the first voltage level being lower than a power supply voltage; converting incident light into electrical charges in the photoelectric conversion region; and accumulating at least one of collected, first overflowed, and second overflowed electrical charges in the floating diffusion region based on the incident light, the collected electrical charges indicating electrical charges that are collected in the photoelectric conversion region, the first overflowed electrical charges indicating charges overflowed from the photoelectric conversion region within potential well capacity of the floating diffusion region, and the second overflowed electrical charges indicating charges overflowed from the photoelectric conversion region over the potential well capacity of the floating diffusion region.
US09245917B2 Vertically stacked image sensor
A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.
US09245915B2 Monolithic multispectral visible and infrared imager
The invention relates to a radiation detection device including a silicon substrate and an infrared photodiode made of a material optimized for infrared detection. The substrate comprises a photosensitive area, readout circuits, and interconnects formed in an electrically-insulating material. The interconnects and the metal contact connect the readout circuits, the photosensitive areas, and the infrared photodiode. The detection device also comprises an infrared radiation filtering structure which covers the photosensitive area without covering the infrared photodiode.
US09245912B2 Method and apparatus for low resistance image sensor contact
A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.
US09245911B2 Semiconductor device
A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region. The electric field shield film is positioned below the wiring, and has a cutout portion in an overlapping region which overlaps the wiring. By forming the cutout portion, end portions of the electric field shield film is arranged to be shifted. Therefore, formation of a deep concave portion which is based on a concave portion on the silicon oxide film and a step of the electric field shield film over the entire width of the wiring can be prevented, and the disconnection of the wiring can be prevented.
US09245909B2 Semiconductor device
A semiconductor device capable of high-speed operation. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is supplied with a first signal. One of a source and a drain of the second transistor is supplied with a first potential. A gate of the second transistor is supplied with a second signal. A first electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor. A second electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor. In a first period, the first signal is low and the second signal is high. In a second period, the first signal is high and the second signal is either low or high.
US09245908B2 Thin-film transistor array substrate, display device including the same, and method of manufacturing the thin-film transistor array substrate
A method of manufacturing a thin film transistor (TFT) array substrate is disclosed. In one aspect, the method includes forming an active layer on a substrate, forming a first insulating layer on the substrate to cover the active layer, and forming a first gate electrode on the first insulating layer in an area corresponding to the active layer, doping the active layer with ion impurities, forming a second insulating layer on the first insulating layer to cover the first gate electrode, performing an annealing process on the active layer, forming a lower electrode of a capacitor on the second insulating layer, forming a third insulating layer on the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant that is greater than those of the first and second insulating layers, and forming an upper electrode of the capacitor on the third insulating layer.
US09245905B2 Back plane for flat panel display device and method of manufacturing the same
A method of manufacturing a flat panel display device includes forming a first gate electrode and a second gate electrode on a substrate. The method includes forming a gate insulating layer on the substrate covering the gate electrodes. The method includes forming a first active layer and a second active layer on the gate insulating layer. The method includes forming an active insulation layer on the gate insulating layer to cover the first active layer. The active insulation layer includes a first hole and a second hole exposing portions of the first active layer. The method includes forming a first source electrode and a first drain electrode on the active insulation layer respectively filling the first hole and the second hole. The method includes forming a second source electrode and a second drain electrode to contact portions of the second active layer.
US09245903B2 High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process
An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region.
US09245902B2 Method of fabricating three-dimensional semiconductor device
A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer.
US09245898B2 NAND flash memory integrated circuits and processes with controlled gate height
A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels.
US09245897B2 Flash memory device and related manufacturing method
A method for manufacturing a memory device may include obtaining a substrate structure that includes a substrate, an oxide material layer positioned on the substrate, a polysilicon material layer positioned on the oxide material layer, a first control gate and a second control gate positioned on the polysilicon material layer, and an offset oxide layer positioned between the first control gate and the second control gate. The method may further include the following steps: removing, using the offset oxide layer as a first mask, a portion of the polysilicon material layer for forming a polysilicon structure that includes a first step structure; forming a masking oxide layer on the offset oxide layer; removing, using the masking oxide layer as a second mask, a portion of the polysilicon structure for forming a floating gate polysilicon member that includes the first step structure and a second step structure.
US09245894B2 Self aligned active trench contact
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
US09245893B1 Semiconductor constructions having grooves dividing active regions
Some embodiments include semiconductor constructions having an active region surrounded by insulating material. A groove crosses the active region to divide the active region into first and second portions. A conductive wordline material is within the groove. First and second diffusion regions are within the first portion of the active region, and vertically arranged to sandwich a part of the first portion therebetween. Third and fourth diffusion regions are within the second portion of the active region, and are vertically arranged to sandwich a part of the second portion therebetween. First and second conductive regions are in electrical contact with the first and second diffusion regions, respectively. Third and fourth conductive regions are in an electrical contact with the third and fourth diffusion regions, respectively.
US09245892B2 Semiconductor structure having buried conductive elements
Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.
US09245890B2 Method of manufacturing precise semiconductor contacts
A first dielectric layer including a first opening is provided on a first surface of a semiconductor layer. A second dielectric layer is provided on top of the first dielectric layer in the first opening. A first portion of the second dielectric layer is then removed, such that a second portion of the second dielectric layer remains in the first opening. The first dielectric layer is then removed, leaving only the second portion of the second dielectric layer on the surface of the semiconductor layer. An epitaxial layer or a base dielectric layer is grown on the exposed portions of the first surface of the semiconductor layer not covered by the second portion of the second dielectric layer. The second portion of the second dielectric layer is then removed to define one or more contact windows, and a contact metal is deposited in the one or more contact windows.
US09245885B1 Methods of forming lateral and vertical FinFET devices and the resulting product
One illustrative method disclosed herein includes, among other things, forming first and second recessed gate structures, recessing the second recessed gate structure so as to define a further recessed second gate structure that exposes a channel structure within a gate cavity, forming first and second gate cap layers in first and second replacement gate cavities, respectively, forming a recess in the second gate cap layer that exposes the channel structure, forming a semiconductor material on the exposed portion of the channel structure within the recess in the second gate cap layer so as to define a first source/drain region for the vertical FinFET device, and forming various contact structures to the gates of the devices and the first source/drain region.
US09245883B1 Method of making a FinFET device
A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a first gate stack and a second gate stack over different portions of a fin feature formed on a substrate, forming a first dielectric layer in a space between the first and second gat stacks, removing the first gate stack to form a first gate trench, therefore the first gate trench exposes a portion of the fin feature. The method also includes removing the exposed portion of the fin feature and forming an isolation feature in the first gate trench.
US09245880B2 High voltage semiconductor power switching device
A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET.
US09245877B2 LED device and LED lamp using the same
A LED device is provided. The LED comprises a frame, a housing, a LED chip and a protection component. The frame comprises a first lead frame and a second lead frame disposed along a first direction and isolated from each other. The housing partially covers the first and second lead frames, and has a receiving portion exposing parts of the surfaces of the first and second lead frames. The LED chip is disposed in the receiving portion on the exposed surface of the first lead frame, and electrically connected to the first and second lead frames. The protection component is disposed on a surface of the second lead frame that is covered by the housing and electrically connected to the first lead frame. None of the sides of a vertical projection of the protection component on the second lead frame is parallel or perpendicular to the first direction.
US09245875B2 Light emitting diodes and a method of packaging the same
Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising: positioning dies in fluid; exposing the dies to a magnetic force to attract the dies onto magnets that are arranged at pre-determined locations either on or near the substrate; and forming permanent connections between the dies and the substrate thereby constituting an array of LED dies on a substrate.
US09245870B1 Systems and methods for providing data channels at a die-to-die interface
A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.
US09245869B2 Method for fastening chips with a contact element onto a substrate provided with a functional layer having openings for the chip contact elements
A method for tacking of chips onto a substrate at chip positions which are distributed on a surface of the substrate. The method includes the following steps: formation or application of a function layer onto the substrate, removing the function layer from the substrate at the chip positions at least in the region of contacts to uncover the contacts, tacking chips onto one chip contact side of the function layer at the chip positions and contacting the chips with the contacts via contact elements.
US09245867B2 Package-on-package electronic devices including sealing layers and related methods of forming the same
A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.
US09245866B2 Antenna device and wireless apparatus
According to one embodiment, an antenna device includes a feeding portion, first and second wire-like metal portions, third and fourth plate-like metal portions and a fifth metal portion. One ends of the first and second wire-like metal portions are connected to the feeding portion. The third and fourth plate-like metal portions are respectively connected to the other ends of the first and second metal portions and disposed separately from each other with a predetermined distance therebetween. The fifth metal portion is configured to connect the third metal portion to the fourth metal portion. A total electrical length of the first to fifth metal portions is 3/2 wavelength at operating frequency band.
US09245864B2 Ball grid array semiconductor package and method of manufacturing the same
A BGA semiconductor package includes a semiconductor device adhered by adhesive to a substrate, and a conductive micro ball fitted into a through-hole provided in the substrate. A bonding wire electrically connects the semiconductor device and the micro ball to each other. An encapsulation member made of resin encapsulates the semiconductor device, the adhesive, part of the micro ball, and the bonding wire, only on a surface side of the substrate on which the semiconductor device is mounted. At least a part of a bottom surface of the micro ball has an exposed portion as an external connection terminal, which is exposed through the through-hole provided in the substrate as a bottom surface of the encapsulation member.
US09245860B2 Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom
In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.
US09245859B2 Wireless module
A wireless module includes a first board (2), in which an electronic component is mounted on one board (2a) and a ground layer (GND1) is formed on the other board (2b), a second board (3) which is laminated on the first board, a connecting member (8) which electrically connects the first board to the second board, a wiring pad (4) which electrically connects the first board to the connecting member, and a wiring pad (4b) which is provided on a bonded surface of the one board and the other board. A signal path of the connecting member has predetermined impedance which is determined depending on a distance between the second wiring pad and the ground layer.
US09245857B2 Chip package
A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.
US09245855B2 Methods and apparatus to reduce semiconductor wafer warpage in the presence of deep cavities
Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated circuits; providing a photomask defining a plurality of cavities to be formed by an etch on a backside surface of the semiconductor wafer; defining structural support areas for the backside surface, the structural support areas being contiguous areas; providing areas on the photomask that correspond to the structural support areas, the structural support areas being areas that are not to be etched; using the photomask, performing an etch on the backside surface of the semiconductor wafer to form the cavities by removing semiconductor material from the backside surface of the semiconductor wafer; and the structural supports on the backside of the semiconductor wafer formed as areas that are not subjected to the etch. Additional methods and apparatus are also disclosed.
US09245850B2 Through silicon via wafer, contacts and design structures
Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the viaformed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.
US09245845B2 Semiconductor device
A semiconductor device includes a first wiring layer stacked over element electrodes above a silicon substrate and a second wiring layer stacked over the first wiring layer. The first wiring layer includes first source electrode wires and first drain electrode wires. The second wiring layer includes second source electrode wires and second drain electrode wires. The first wiring layer includes a first region and second regions. In the first region, each of the first source electrode wires and the first drain electrode wires is continuous. In each of the second regions, each of the first source electrode wires and the first drain electrode wires is discontinuous. Second source electrode wires and second drain electrode wires are arranged to alternately over the first regions and the second regions in one direction. External connection terminals are not connected over the second regions, and are connected over the first regions.
US09245836B2 Interposers including fluidic microchannels and related structures and methods
Interposers for use in the fabrication of electronic devices include semiconductor-on-insulator structures having fluidic microchannels therein. The interposers may include a multi-layer body in which a semiconductor material is bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel may extend in a lateral direction through at least one of the layer of dielectric material and the semiconductor material. The interposers may include redistribution layers and electrical contacts on opposing sides thereof. Semiconductor structures include one or more semiconductor devices coupled with such interposers. Such interposers and semiconductor structures may be formed by fabricating a semiconductor-on-insulator type structure using a direct bonding method and defining one or more fluidic microchannels at a bonding interface during the direct bonding process.
US09245834B2 Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
A semiconductor device has a semiconductor die. The semiconductor die has a contact pad. A first conductive layer is formed over the contact pad. A conductive shell having a hollow core is formed over the first conductive layer. A compliant material is deposited in the hollow core. The semiconductor die is mounted over a substrate with the conductive shell electrically connected to a conductive trace on the substrate. A second conductive layer is formed over the conductive shell. The compliant material is an insulating material. A bump material is deposited around the conductive shell. A pre-solder material is deposited over the conductive trace. The conductive shell has a cross-sectional width less than 7 micrometers. The second conductive layer is a conductive lip. Mounting the semiconductor die over the substrate further includes mounting the semiconductor die over the substrate in a bump on lead (BOL) configuration.
US09245830B2 Lead built-in type circuit package and method for producing same
A circuit package having an inner lead, an outer lead and a circuit element is provided, in which the circuit element is connected a first surface of the inner lead. The circuit package has a first molded resin portion and second molded resin portions. The first molded resin portion is formed from a second surface, opposite to the first surface, of the inner lead toward the first surface inner lead embedding the inner lead and the circuit element. And the second molded resin portions are formed on side portions of the outer lead excluding the first and second surfaces of the outer lead.
US09245827B2 3D semiconductor device
A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
US09245822B2 Dummy patterns and method for generating dummy patterns
A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.
US09245821B2 Cooling device for semiconductor module, and semiconductor module
A cooling device for a semiconductor module supplying a coolant from outside into a water jacket and cooling a semiconductor element, includes a heat sink thermally connected to the semiconductor element; a first flow channel extending from a coolant introducing port and including a guide section having an inclined surface for guiding the coolant toward one side surface of the heat sink; a second flow channel disposed parallel to the first flow channel and extending toward a coolant discharge port; a flow velocity adjusting plate disposed in the second flow channel and formed parallel to the other side surface of the heat sink at a distance therefrom; and a third flow channel formed to communicate the first flow channel and the second flow channel. The heat sink is disposed in the third flow channel.
US09245818B2 Integrated assembly for installing integrated circuit devices on a substrate
In one embodiment, a biasing device is actuated using an actuator which is aligned with the biasing device along an alignment axis. A first frame is thereby biased toward a second frame along the alignment axis to bias an integrated circuit package toward a socket. The actuator also latches the first and second frames together and biased towards each other with the integrated circuit package and the socket biased toward each other. Other aspects and features are also described.
US09245817B2 Semiconductor device with embedded heat spreading
A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.
US09245813B2 Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance
The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.
US09245810B2 Electrical and opto-electrical characterization of large-area semiconductor devices
The present invention relates to an electrical and/or opto-electrical characterisation method for testing large-area semiconductor devices in production, the method comprising the steps of providing a first electrode and placing it into electrical contact with a contact area of a conducting layer of a semiconductor device; providing a movable electrode assembly, comprising a container holding an electrolyte solution and at least a second electrode; immersing the second electrode into the electrolyte solution; positioning the electrode assembly such that the electrolyte solution places the second electrode into electrical contact with a top surface of the semiconductor device; and scanning the movable electrode assembly relative to the top surface of the semiconductor device while performing electrical measurements. It also relates to a corresponding electrical and/or opto-electrical characterisation device comprising a first electrode, a movable electrode assembly with a container holding an electrolyte solution and a second electrode immersed into it and scanning means.
US09245809B2 Pin hole evaluation method of dielectric films for metal oxide semiconductor TFT
The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer.
US09245807B2 Integrated circuit with a thin body field effect transistor and capacitor
A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
US09245806B2 Semiconductor device with transistor and method of fabricating the same
A method of fabricating a semiconductor device that includes forming a gate stack layer including a metal-containing layer on a semiconductor substrate having an NMOS region and a PMOS region, introducing arsenic to the gate stack layer in the NMOS region, introducing aluminum to the gate stack layer in the PMOS region, and etching the gate stack layers, where the arsenic and the aluminum are introduced, to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively.
US09245803B1 Hybrid wafer dicing approach using a bessel beam shaper laser scribing process and plasma etch process
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a Bessel beam shaper laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
US09245802B2 Wafer dicing using femtosecond-based laser and plasma etch
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
US09245801B2 Crack stop barrier and method of manufacturing thereof
A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier.
US09245800B2 Method of manufacturing a semiconductor device
To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.
US09245794B2 Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application
An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.
US09245793B2 Plasma treatment of low-K surface to improve barrier deposition
Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated species. The activated species can be used to treat the surfaces of low-k and/or ultra low-k dielectric materials to facilitate improved deposition of diffusion barrier materials.
US09245790B2 Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.
US09245786B2 Apparatus and methods for positioning a substrate using capacitive sensors
Embodiments of the present invention provide apparatus and methods for positioning a substrate in a processing chamber using capacitive sensors. One embodiment of the present invention provides an apparatus for processing a substrate. The apparatus includes first and second capacitive sensors disposed in an inner volume. The first capacitive sensor is positioned to detect a location of an edge of the substrate at a first angular location. The second capacitive sensor is positioned to detect a vertical position of the substrate.
US09245781B2 Article storage facility and article storage method
An article storage facility includes a transport device for transporting containers to a plurality of storage sections, an inactive gas feed section which supplies inactive gas to the interior of the container stored in the storage section, and a controller for controlling operation of the device and operation of the flow rate adjusting device of the inactive gas feed section. The controller is configured to cause a state of the inactive gas feed section associated with the storage section to be both a storage feed state and an unfeeding state depending on if the carrier is stored or not stored be. The controller is also configured to store the transporting container in the storage section after changing the state of the inactive gas feed section associated with the storage section in which the container is to be stored to a pre-storage feed state from the unfeeding state.
US09245779B2 Method of preparing thin film, thin film, apparatus for preparing thin film, and electronic device including thin film
A method of preparing a thin film includes coating a thin film-forming composition on a substrate, and heat-treating the coated thin film-forming composition under a pressure less than 760 Torr. The thin film includes a compact layer having a thickness in a range of greater than 50 Å to about 20,000 Å and a refractive index in a range of about 1.85 to about 2.0.
US09245771B2 Semiconductor packages having through electrodes and methods for fabricating the same
Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.
US09245768B2 Method of improving substrate uniformity during rapid thermal processing
Methods for controlling substrate uniformity in a thermal processing chamber include a measuring process to provide temperature-related quantities across a radius of a substrate, correlating substrate properties with processing parameters to simulate deformation of the substrate at various radial distances over a temperature range, a thermal process so that temperature of at least one reference region within the substrate matches a target set point temperature, measuring a temperature of at least one reference region as the substrate rotates, measuring deformation of the substrate as the substrate rotates, correlating measured temperatures of at least one reference region with simulated deformation of the substrate and measured temperature-related quantities of the substrate to calculate a simulated shape change of the substrate over a temperature range, tuning substrate flatness by adjusting lamp temperature profile across the substrate based on simulated shape change of the substrate and actual shape of the substrate.
US09245759B2 Method for manufacturing a dual work function semiconductor device
A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element. The method additionally includes annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer, and subsequently removing the first metal layer/stack and the second metal layer/stack. The method further includes forming a third metal layer/stack in the first and second predetermined areas.
US09245751B2 Anti-reflective layer and method
A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.
US09245749B2 Method of forming Ga2O3-based crystal film and crystal multilayer structure
A method of forming a Ga2O3-based crystal film includes epitaxially growing a Ga2O3-based crystal film on a (001)-oriented principal surface of a Ga2O3-based substrate at a growth temperature of not less than 750° C. A crystal multilayer structure includes a Ga2O3-based substrate with a (001)-oriented principal surface, and a Ga2O3-based crystal film formed on the principal surface of the Ga2O3-based substrate by epitaxial growth. The principal surface has a flatness of not more than 1 nm in an RMS value.
US09245748B2 Methods for growing III-V materials on a non III-V material substrate
The present invention relates to a method for manufacturing semiconductor materials comprising epitaxial growing of group III-V materials, for example gallium arsenide (GaAs), on for example a non III-V group material like silicon (Si) substrates (wafers), and especially to pre-processing steps providing a location stabilization of dislocation faults in a surface layer of the non III-V material wafer in an orientation relative to an epitaxial material growing direction during growing of the III-V materials, wherein the location stabilized dislocation fault orientations provides a barrier against threading dislocations (stacking of faults) from being formed in the growing direction of the III-V materials during the epitaxial growth process.
US09245745B2 Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus and non-transitory computer-readable recording medium
A method of manufacturing a semiconductor device, includes: forming a film containing a predetermined element on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a first precursor containing the predetermined element and a halogen group to the substrate; supplying a second precursor containing the predetermined element and an amino group to the substrate; and supplying a reducing agent not containing halogen, nitrogen and carbon to the substrate.
US09245742B2 Sulfur-containing thin films
In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
US09245738B2 High electron mobility transistor and method of manufacturing the same
According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer; a channel supply layer on the channel layer; a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer; a gate electrode on a part of the channel supply layer between the source electrode and the drain electrode; a first depletion-forming layer between the gate electrode and the channel supply layer; and a at least one second depletion-forming layer on the channel supply layer between the gate electrode and the drain electrode. The at least one second depletion-forming layer is electrically connected to the source electrode.
US09245736B2 Process of forming a semiconductor wafer
A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.
US09245730B2 Apparatus and methods for generating electromagnetic radiation
An apparatus for generating electromagnetic radiation includes an envelope, a vortex generator configured to generate a vortexing flow of liquid along an inside surface of the envelope, first and second electrodes within the envelope configured to generate a plasma arc therebetween, and an insulative housing associated surrounding at least a portion of an electrical connection to one of the electrodes. The apparatus further includes a shielding system configured to block electromagnetic radiation emitted by the arc to prevent the electromagnetic radiation from striking all inner surfaces of the insulative housing. The apparatus further includes a cooling system configured to cool the shielding system.
US09245726B1 Controlling charged particles with inhomogeneous electrostatic fields
An energy analyzer for a charged-particle spectrometer may include a top deflection plate and a bottom deflection plate. The top and bottom deflection plates may be non-symmetric and configured to generate an inhomogeneous electrostatic field when a voltage is applied to one of the top or bottom deflection plates. In some instances, the top and bottom deflection plates may be L-shaped deflection plates.
US09245719B2 Dual phase cleaning chambers and assemblies comprising the same
In one embodiment, a dual phase cleaning chamber may include a turbulent mixing chamber, a fluid diffuser, an isostatic pressure chamber and a rupture mitigating nozzle. The turbulent mixing chamber may be in fluid communication with a first fluid inlet and a second fluid inlet. The fluid diffuser may be in fluid communication with the turbulent mixing chamber. The rupture mitigating nozzle may include a first fluid collecting offset, a second fluid collecting offset, and a displacement damping projection. The displacement damping projection may be disposed between the first and second fluid collecting offset and may be offset away from each of the first fluid collecting offset and the second fluid collecting offset, and towards the fluid diffuser. A pressurized cleaning fluid introduced from the first fluid inlet, the second fluid inlet, or both flows through the outlet passage of the first and second fluid collecting offset.
US09245718B2 Showerhead electrode assembly in a capacitively coupled plasma processing apparatus
A showerhead electrode assembly for use in a capacitively coupled plasma processing apparatus comprising a heat transfer plate. The heat transfer plate having independently controllable gas volumes which may be pressurized to locally control thermal conductance between a heater member and a cooling member such that uniform temperatures may be established on a plasma exposed surface of the showerhead electrode assembly.
US09245716B2 Edge-clamped and mechanically fastened inner electrode of showerhead electrode assembly
An inner electrode of a showerhead electrode assembly useful for plasma etching includes features providing improved positioning accuracy and reduced warping, which leads to enhanced uniformity of plasma processing rate. The assembly can include a thermal gasket set and fasteners such as bolts or cam locks located on a radius of ¼ to ½ the radius of the inner electrode. A method of assembling the inner electrode and gasket set to a supporting member is also provided.
US09245712B2 Focused ion beam system
A focused ion beam system includes a gas field ion source which generates gas ions, an ion gun unit which accelerates the gas ions and radiates the gas ions as an ion beam, a beam optical system which includes at least a focusing lens electrode and radiates the ion beam onto a sample, and an image acquiring mechanism which acquires an FIM image of a tip of an emitter based on the ion beam. The image acquiring mechanism includes an alignment electrode which is disposed between the ion gun unit and the focusing lens electrode and adjusts a radiation direction of the ion beam, an alignment control unit which applies an alignment voltage to the alignment electrode, and an image processing unit which combines a plurality of FIM images acquired when applying different alignment voltages to generate one composite FIM image.
US09245710B2 Charged particle beam device
A charged particle beam device that appropriately maintains a throughput of the device for each of specimens different in a gas emission volume from each other is provided. A scanning electron microscope includes an electron source, a specimen stage, a specimen chamber, and an exchange chamber, and further includes a vacuum gauge that measures an internal pressure of the exchange chamber, a time counting unit that counts time taken when a measurement result by the vacuum gauge has reached a predetermined degree of vacuum, and an integral control unit that performs comparative calculation and determination based on a measurement result by the time counting unit and integral control based on a process flow. And, the integral control unit controls changing of a content of a subsequent process based on a shift of the degree of vacuum of the exchange chamber.
US09245702B1 Keypad having tamper-resistant keys
A tamper resistant keypad includes one or more key assemblies having a resilient key member and a contact. The resilient key member is configured to flex when the key assembly is depressed to allow the contact to close a key press detection circuit on a circuit board to register a key press. A tamper detection switch assembly at least partially surrounds the resilient key member. The tamper detection switch assembly is configured to detect attempts to access the key assembly.
US09245701B2 Pressure switch for a motor vehicle
An actuating device for actuating a function on a motor vehicle includes a touch surface actuated by a user. The touch surface is arranged in such a way that it can be moved under pressure from a first end position to a second end position. An elastic reset urges the touch surface into the first end position. A contact switch is arranged between the touch surface and a support surface. A guide sleeve and a guide pin guide the touch surface when actuated. When moving the touch surface, the guide pin is moved in an axial direction into the sleeve and is secured against lateral movement in a small diameter section of the pin. However, the guide pin can be tipped in the sleeve about a pivot point in the small diameter section, thus preventing the touch surface from being jammed in the event of a decentralized impact.
US09245700B2 Circuit breaker
A circuit breaker including a first and a second contact movable relative each other between an open position, in which the contacts are at a distance from each other, and a closed position, in which the contacts are in electrical contact with each other. The first contact includes one or more contact elements adapted to be in electrical contact with the second contact when the contacts are in the closed position, and a mesh made of metal arranged in thermal contact with the contact elements. The mesh is arranged to at least partly surround the contact elements to allow heat to conduct from the contact elements to the mesh.
US09245696B2 Display device
A touch panel includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of wirings. Each of the plurality of first electrodes has a first portion formed on a layer different from that on which the second electrodes are formed and intersecting the second electrodes, and a second portion formed on the same layer as that on which the second electrodes are formed, but separated from the second electrode. The second electrode and the second portion of the first electrode are formed on a layer different than the layer where the wiring is formed. The first portion of the first electrode is connected to the second portion through a contact portion formed in an insulating film made of a negative resist between the first portion and the second electrode.
US09245695B2 Integration of energy storage devices onto substrates for microelectronics and mobile devices
In an embodiment of the invention, an energy storage device is described including a pair of electrically conductive porous structures, with each of the electrically conductive porous structures containing an electrolyte loaded into a plurality of pores. A solid or semi-solid electrolyte layer separates the pair of electrically conductive porous structures and penetrates the plurality of pores of the pair of electrically conductive porous structures. In an embodiment of the invention, an electrically conductive porous structure is formed on a substrate, the electrically conductive porous structure containing a plurality of pores. An electrolyte is then loaded into the plurality of pores, and an electrolyte layer is formed over the electrically conductive porous structure. In an embodiment, the electrolyte layer penetrates the plurality of pores of the electrically conductive porous structure.
US09245694B2 Solid-state supercapacitor
Embodiments of the present disclosure relate to a solid-state supercapacitor. The solid-state supercapacitor includes a first electrode, a second electrode, and a solid-state ionogel structure between the first electrode and the second electrode. The solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode. Further, the solid-state ionogel structure substantially fills voids inside the first electrode and the second electrode.
US09245693B2 High voltage EDLC cell and method for the manufacture thereof
A method of manufacturing an electrode includes printing an electrode ink on a portion of a substrate using a rotary lithographic printer. The electrode ink is allowed to dry on the substrate. A separator material is printed on the portion of the substrate using the rotary lithographic printer. A sealant wall is printed around the portion of the substrate using the rotary lithographic printer.
US09245692B2 Dye-sensitized solar cell
Disclosed is a dye-sensitized solar cell which includes a working electrode having a porous titanium oxide layer on a conductive substrate capable of transmitting light, a counter electrode disposed so as to face the working electrode, a photosensitizing dye supported on the porous titanium oxide layer of the working electrode, and an electrolyte disposed between the working electrode and the counter electrode. The porous titanium oxide layer includes a rutile crystal-containing layer containing an anatase crystal-type titanium oxide composed of an anatase crystal and a spherical rutile crystal-type titanium oxide composed of a rutile crystal, and a content of the rutile crystal-type titanium oxide in the rutile crystal-containing layer is from 3 to 15% by mass.
US09245690B2 Multilayer ceramic capacitor, board having the same mounted thereon, and method of manufacturing the same
There is provided a multilayer ceramic capacitor including: a ceramic body including a plurality of dielectric layers; a plurality of first and second internal electrodes disposed in the ceramic body to be alternately exposed to the third and fourth end surfaces, having the dielectric layers interposed therebetween; and first and second external electrodes electrically connected to the first and second internal electrodes, wherein the first and second external electrodes include: first and second conductive glass layers; first and second conductive resin layers containing copper and an epoxy; and first and second insulating layers.
US09245688B2 Monolithic ceramic capacitor
A monolithic ceramic capacitor having a large capacity and high reliability includes a ceramic sintered body including a plurality of stacked ceramic layers, and first and second inner electrodes and alternately disposed inside the ceramic sintered body to be opposed to each other in a stacking direction of the ceramic layers with one of the ceramic layers being interposed between the adjacent first and second inner electrodes. The ceramic sintered body includes a first portion in which the first and second inner electrodes are opposed to each other, and a second portion positioned outside the first portion. A ratio (Ic/Ia) of c-axis peak intensity (Ic) to a-axis peak intensity (Ia) measured with an XRD analysis of the one of the ceramic layers is about 2 or more.
US09245687B2 Multilayer ceramic capacitor and manufacturing method thereof
There is provided a multilayer ceramic capacitor, including a ceramic body, a plurality of first and second internal electrodes, and first and second external electrodes, wherein the first and second external electrodes include first and second internal layers including first and second internal head portions and first and second internal bands formed on both main surfaces of the ceramic body, and first and second external layers including first and second external head portions and first and second external bands formed on the first and second internal bands and having a distance shorter than a distance of the first and second internal bands, the first and second external layers having viscosity higher than that of the first and second internal layers.
US09245685B2 Common mode filter and method of manufacturing the same
Disclosed herein is a common mode filter including: a body element including an insulating member enclosing a coil electrode pattern and a magnetic member disposed on one surface or both surfaces of the insulating member; and an insulating layer disposed on at least one side of the body element, thereby increasing an interlayer adhesion between the respective components configuring the common mode filter.
US09245683B2 Inductive coupler
An inductive coupler apparatus have a first inductive coupler with a first magnetic center shaft having a recessed portion, a first outer magnetic layer disposed around the first magnetic center shaft, and a first coil disposed around the first magnetic center shaft and disposed within the first outer magnetic layer and a second inductive coupler with a second magnetic center shaft having a recessed portion, a second outer magnetic layer disposed around the second magnetic center shaft, and a second coil disposed around the second magnetic center shaft and disposed within the second outer magnetic layer. When the first and second inductive couplers are in the coupled position the inductive couplers can provide for the transmission of power and/or communication between downhole tools in a bottom hole assembly.
US09245682B2 Transformer
To greatly improve the productivity, the general versatility, the downsizing, the performance and the like, as compared to those of the conventional transformer, provided is a transformer including: a core; a primary winding; a secondary winding; a bobbin provided with a low voltage side coil winding portion and a high voltage side coil winding portion, wherein the secondary winding is wound onto each of the coil winding portions; and a casing disposed so as to cover an outer periphery of the bobbin, wherein the primary winding is wound onto a portion of an outer periphery of the casing corresponding to a position of the low voltage side coil winding portion.
US09245680B2 Common mode choke coil and method for manufacturing the same
There is provided a common mode choke coil in which a non-magnetic layer and a second magnetic layer stacked on a first magnetic layer and two facing conductive coils are included in the non-magnetic layer, the non-magnetic layer is formed of sintered glass ceramics, the conductive coils and are formed of a conductor containing copper, and at least one of the first magnetic layer and the second magnetic layer is formed of a sintered ferrite material containing Fe2O3, Mn2O3, NiO, ZnO and CuO. The sintered ferrite material has an Fe2O3-reduced content of 25 to 47 mol % and a Mn2O3-reduced content of 1 to 7.5 mol %, or Fe2O3-reduced content of 35 to 45 mol % and a Mn2O3-reduced content of 7.5 to 10 mol %, and a CuO reduced content of 5 mol %.
US09245676B2 Soft magnetic alloy powder, compact, powder magnetic core, and magnetic element
Provided are a soft magnetic alloy powder, a compact made from the soft magnetic alloy powder, a powder magnetic core including the compact, and a magnetic element including the powder magnetic core. The soft magnetic alloy powder contains Fe—Ni-based particles containing 38% to 48% by mass Ni, 1.0% to 15% by mass Co, and 1.2% to 10% by mass Si relative to the total mass of Fe, Ni, Co, and Si, the remainder being Fe. The Fe—Ni-based particles have an average size of more than 1 μm to less than 10 μm.
US09245674B2 Rare-earth permanent magnetic powder, bonded magnet, and device comprising the same
A rare-earth permanent magnetic powder, a bonded magnet, and a device comprising the bonded magnet are provided. The rare-earth permanent magnetic powder is mainly composed of 7-12 at % of Sm, 0.1-1.5 at % of M, 10-15 at % of N, 0.1-1.5 at % of Si, and Fe as the balance, wherein M is at least one element selected from the group of Be, Cr, Al, Ti, Ga, Nb, Zr, Ta, Mo, and V, and the main phase of the rare-earth permanent magnetic powder is of TbCu7 structure. Element Si is added into the rare-earth permanent magnetic powder for increasing the ability of SmFe alloy to from amorphous structure, and for increasing the wettability of the alloy liquid together with the addition of element M in a certain content, which enables the alloy liquid prone to be injected out of a melting device. The average diameter of the rare-earth permanent magnetic powder is in the range of 10-100 μm, and the rare-earth permanent magnetic powder is composed of nanometer crystals with average grain size of 10-120 nm or amorphous structure.
US09245673B2 Performance improvement of magnetocaloric cascades through optimized material arrangement
A magnetocaloric cascade containing at least three different magnetocaloric materials with different Curie temperatures, which are arranged in succession by descending Curie temperature, wherein none of the different magnetocaloric materials with different Curie temperatures has a higher layer performance Lp than the magnetocaloric material with the highest Curie temperature and wherein at least one of the different magnetocaloric materials with different Curie temperatures has as lower layer performance Lp than the magnetocaloric material with the highest Curie temperature wherein Lp of a particular magnetocaloric material being calculated according to formula (I): Lp=m*dTad,max with dTad,max: maximum adiabatic temperature change which the particular magnetocaloric material undergoes when it is magnetized from a low magnetic field to high magnetic field during magnetocaloric cycling, m: mass of the particular magnetocaloric material contained in the magnetocaloric cascade.
US09245672B2 Chip resistor and method of producing same
An object of the disclosure is to provide a chip resistor without causing the disconnection in atmosphere of sulfidizing gas and without precipitating silver sulfide on its surface. The chip resistor of the present disclosure includes a resistor layer disposed on a top surface of a substrate; a first upper electrode layer disposed at both sides of the resistor layer and being electrically connected to the resistor layer; and a second upper electrode layer disposed on the first upper electrode layer and including between 75% by weight and 85% by weight (inclusive) of silver particles with an average particle diameter ranging from 0.3 um to 2 um, between 1% by weight and 10% by weight (inclusive) of carbon, and a resin.
US09245667B2 Circuit board
The invention provides a circuit board comprising a substrate and a dielectric material provided on the substrate. The dielectric material comprises (i) 40˜80 parts by weight of polyphenylene ether resin having a Mw of 1000˜7000, a Mn of 1000˜4000 and Mw/Mn=1.0˜1.8; (ii) 5˜30 parts by weight of bismaleimide resins; and (iii) 5˜30 parts by weight of polymer additives, wherein the dielectric material has Dk of 3.75˜4.0 and Df of 0.0025˜0.0045. The dielectric material is suitably used in prepregs and insulation layers of a circuit board, because it has high Tg, low thermal expansion coefficient, low moisture absorption and excellent dielectric properties such as Dk and Df.
US09245660B2 Electroconductive particle and metal paste, and electrode
The present invention is an electroconductive particle for forming an electrode including a precious metal particle including Pt or a Pt alloy and having an average particle diameter of 50 to 150 nm, a first ceramic particle including Al2O3 or ZrO2 dispersed in the precious metal particle and having an average particle diameter of 5 to 50 nm, and a second ceramic particle including Al2O3 or ZrO2 bonded to an outer periphery of the precious metal particle and having an average particle diameter of 5 to 50 nm. The sum of the volume of the first ceramic particle and the volume of the second ceramic particle is preferably 2 to 40 vol % based on the whole electroconductive particle. A metal paste containing the electroconductive particle according to the invention is one from which an electrode film of low resistance and excellent durability can be manufactured and further excellent in adherence and conformability to a substrate.
US09245657B2 Energy modulator
The present disclosure relates to a particle energy modulating device for variably changing the energy of the particles of a particle beam. The particle energy modulating device has a variable energy varying device with a control value correcting device for correcting a supplied control value. The control value correcting device corrects the supplied control values through the use of previously determined calibration data.
US09245653B2 Reduced level cell mode for non-volatile memory
Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values.
US09245648B1 Logic high-dielectric-constant (HK) metal-gate (MG) one-time-programming (OTP) memory device sensing method
In a one-time-programming (OTP) memory cell, dual-voltage sensing is utilized to determine whether the memory cell has experienced a non/soft breakdown or a hard breakdown. The drain current of the memory cell is read when the gate voltage is at a first predetermined voltage, and if the read drain current is greater than a predetermined current level, then a hard breakdown is detected. One or more additional readings of the current may be obtained to determine that a hard breakdown has occurred. If the read drain current is less than the predetermined current level, then a non/soft breakdown is detected. The threshold voltage of the memory cell may be shifted, and a second reading of the drain current may be obtained when the gate voltage is at a second predetermined voltage in case the memory cell experiences a non/soft breakdown.
US09245645B2 Multi-pulse programming for memory
Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.
US09245644B2 Method and apparatus for reducing erase disturb of memory by using recovery bias
A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
US09245640B2 Non-volatile semiconductor memory having multiple external power supplies
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
US09245638B2 Method of operating a split gate flash memory cell with coupling gate
A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.
US09245635B2 Nonvolatile semiconductor memory
A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines. Those current path switching circuits which are connected to the selected bit lines supply a current from the power supply line to the memory cells or a predetermined terminal depending on a measured value of the amount of charge measured by the charge amount measurement section.
US09245632B1 Write pre-compensation for nonvolatile memory
A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values. The one or more of the interference values are selected based on (i) the state to which the memory cell is to be programmed, and (ii) the states of the one or more memory cells.
US09245631B2 Apparatus and method of storing data at a multi-bit storage element
A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.
US09245630B2 Memory system comprising nonvolatile memory device and program method thereof
A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode.
US09245628B2 Non-volatile semiconductor memory device
A non-volatile semiconductor memory device includes a semiconductor layer of a first conductivity type, and a plurality of wells of a second conductivity type formed on the first semiconductor layer, the wells being arranged in a first direction. A memory block is arranged in each well. A plurality of word lines are provided, each word line being commonly connected to a plurality of NAND cell units in one memory block. A plurality of bit lines extend in a first direction, the bit lines being connected to first ends of the NAND cell units present in the memory blocks. A source line is connected to second ends of the NAND cell units. A well driver performs a control of selectively providing a first voltage or a second voltage higher than the first voltage to each well.
US09245627B2 Compact memory device including a SRAM memory plane and a non volatile memory plane, and operating methods
A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.
US09245622B1 Pre-conditioning two-terminal memory for increased endurance
Providing for preconditioning of multi-programmable, two-terminal memory for improved endurance and switching functionality is described herein. By way of example, one or more pre-conditioning signals can be applied to a memory cell post-fabrication. The preconditioning signal(s) can have relatively small power, avoiding programming of the memory cell, compared with an associated program signal. The preconditioning signal(s) can facilitate reliable erasure of the memory cell following subsequent programming at normal programming power. Accordingly, switching functionality of the two-terminal memory can be preserved, maintaining the multi-programmable nature of the memory cell.
US09245619B2 Memory device with memory buffer for premature read protection
Devices and methods for accurate reading of data in memory technology prone to drifting memory characteristics. An example device includes a memory array for storing data, and a memory buffer for storing a subset of the data in the memory array. A memory controller is configured to read data from the memory buffer if the data was written to the memory array before a predetermined duration of time, and to read the data from the memory array if the data is at least one of not valid or not available at the memory buffer.
US09245618B2 Read measurement of resistive memory cells
A method for read measurement of resistive memory cells having s≧2 programmable cell-states includes applying to each cell at least one initial voltage and making a measurement indicative of cell current due to the initial voltage; determining a read voltage for the cell in dependence on the measurement; applying the read voltage to the cell; making a read measurement indicative of cell current due to the read voltage; and outputting a cell-state metric dependent on the read measurement; wherein the read voltages for cells are determined in such a manner that the cell-state metric exhibits a desired property.
US09245617B2 Nonvolatile memory cells programable by phase change and method
A nonvolatile memory comprising at least one ferromagnetic region having permittivity which changes from a first state to a second state of lower permittivity upon heating; at least one heater operatively associated with the at least one ferromagnetic region which selectively provides heat to the ferromagnetic region to change its permittivity; and a plurality of connectors operatively connected to the at least one heater and adapted to be connected to a current source that provides a current which causes the heater to change the at least one ferromagnetic region from a first state to a second state. Optionally, the memory is arranged as an array of memory cells. Optionally, each cell has a magnetic field sensor operatively associated therewith. Optionally, the nonvolatile memory is radiation hard. Also, a method of recording data by heating at least one ferromagnetic region to change its permittivity.
US09245613B2 Storage interface apparatus for solid state drive tester
Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used.
US09245612B2 Semiconductor device having bit lines hierarchically structured
Disclosed herein is a device that includes: a sense amplifier circuit activated in response to a first control signal; a first global bit line coupled to the sense amplifier circuit; a first local bit line; a first transistor electrically coupled between the first global bit line and the first local bit line, the first transistor being rendered conductive in response to a second control signal; a first memory cell; a first cell transistor electrically coupled between the first local bit line and the first memory cell, the first cell transistor being rendered conductive in response to a third control signal; and a control circuit producing the first, second, and third control signals such that the second control signal is produced after producing the third control signal and the first control signal is produced after producing the second and third control signals.
US09245610B2 OTP cell with reversed MTJ connection
A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.
US09245608B2 Thermally tolerant perpendicular magnetic anisotropy coupled elements for spin-transfer torque switching device
Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier. A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells.
US09245607B2 Resistance-change semiconductor memory
According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared.
US09245603B2 Integrated circuit and operating method for the same
An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.
US09245592B2 Memory elements with elevated control signal levels for integrated circuits
Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.
US09245591B2 Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts
A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition.
US09245590B2 Stacked die flash memory device with serial peripheral interface
Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
US09245589B2 Semiconductor device having Schmitt trigger NAND circuit and Schmitt trigger inverter
A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.
US09245584B2 Information processing apparatus and information processing method
In an information processing apparatus, a cue playback decision unit 610 determines, based on recording information acquired from a recording information storage unit in which a recorded content having a program recorded and the recording information of the recorded content are associated with each other, whether or not a recorded content of a playback target is a recorded content whose recording is started prior to starting time of the program and which is to be played back by cue playback. A time confirmation unit 612 acquires, when it is determined that the recorded content is a recorded content to be played back by cue playback, recording starting time included in the recording information of the recorded content of the playback target from the recording information storage unit. A skip time acquisition unit 614 determines, based on the number of seconds of the recording starting time acquired by the time confirmation unit 612, a period of time to be skipped upon cue playback of the recorded content of the playback target.
US09245582B2 User interface for method for creating a custom track
A system for allowing a user to create a custom track on a user apparatus, the user apparatus having a display is described. A memory stores a plurality of video clips and an audio track having a timeline. An application is stored in the memory. The application is configured to provide, on the display of the user apparatus, a plurality of video source windows, each of the plurality of video source windows corresponding to a respective one of the plurality of video clips. The application is further configured to allow the user to create the custom track while the audio track is playing by correlating portions of the plurality of video clips with the audio track by selecting respective ones of the plurality of video source windows at desired times in the timeline of the audio track.
US09245578B1 Disk drive compensating for inter-track interference in analog read signal
A disk drive is disclosed comprising a disk comprising a plurality of data tracks, and a head comprising a first read element and a second read element. The first read element is positioned over a first data track and the second read element is positioned over a second data track. A first analog read signal emanating from the first read element is adjusted based on a second analog read signal emanating from the second read element in order to reduce noise in the first analog read signal due to interference from the second data track.
US09245575B2 Library device
It is required that setting information and mechanical correction information of a preceding device can be automatically carried over only by replacing a unit, to implement reduction in the maintenance cost and prevention of human operational mistakes. Library device control firmware 11 updates, if drive identification information kept in a library control unit 10 differs from drive identification information kept in two other units on the basis of logic of decision by majority, a drive serial number 4A and device setting information 2A kept in the library control unit 10 based on a drive serial number 4B and device setting information 2B kept in an accessor control unit 20.
US09245574B2 Optical disc drive having a tray with guide supports and main circuit board
An optical disk drive including: a housing; a tray installed in the housing; an optical pickup unit mounted in the tray; and a guide shaft mounted in the tray such that the optical pickup unit and the guide shaft are configured such that the optical pickup unit is reciprocally movable along the guide shaft.
US09245572B2 Optical tape pick up unit with holographic optical element
An optical tape pick up unit includes a holographic optical element and an aspheric objective lens. The holographic optical element splits a laser beam into first order beams and introduces pre-compensating wavefront error into the first order beams. The aspheric objective lens focuses the first order beams onto optical tape and introduces wavefront error into the first order beams having a magnitude similar to and polarity opposite that of the pre-compensating wavefront error.
US09245570B2 Reproducing apparatus and reproducing method
Provided is a reproducing apparatus including: an optical system that obtains a signal light by radiating light emitted from a light source and generates a reference light from the light emitted from the light source, with respect to a recording medium, and that generates first to fourth groups of the signal light beams and the reference light beams, with respect to the superposed light in which the signal light and the reference light are superposed onto each other; a light receiving unit that receives light beams of the first to fourth groups of the signal light beams and the reference light beams respectively through first to fourth light receiving elements; and a reproduction signal generation circuit that calculates a first differential signal and a second differential signal, and that generates a reproduction signal by performing an arithmetic operation using the first and second differential signals.
US09245567B2 Magnetic recording medium and magnetic storage apparatus
A magnetic recording medium includes a substrate, a magnetic layer including a FePt alloy having a L10 type structure, and a plurality of underlayers arranged between the substrate and the magnetic layer, wherein at least one of the plurality of underlayers includes TiO2.
US09245565B2 Magnetic recording medium lubricant mixture and systems thereof
In one embodiment, a magnetic recording medium includes a magnetic recording layer adapted to store magnetic information, a protective film positioned above the recording layer, the protective film being adapted to reduce wear to the magnetic recording layer, and a lubricant positioned above the protective film, the lubricant being adapted to provide a stable head-to-disk interface, wherein the lubricant includes a first lubricant, the first lubricant including a material having the following chemical formula: wherein Rf represents: and wherein Y is a repeating chain including carbon and fluorine.
US09245564B2 Soft underlayer having a multilayer structure for high areal density perpendicular recording media
According to one embodiment, a soft underlayer structure includes a coupling layer, at least one outer soft underlayer positioned above and below the coupling layer, and at least one inner soft underlayer positioned above and below the coupling layer between the coupling layer and the associated outer soft underlayer, where the inner soft underlayers have a saturation magnetic flux density and/or a thickness that is different than a saturation magnetic flux density and/or a thickness of the outer soft underlayers.
US09245561B1 Apparatus and method for measuring surface charge of a slider
An apparatus comprises a slider that includes a fly height sensor. A signal generator is coupled to the slider. The signal generator is configured to generate an AC electrical signal having a DC offset voltage and to adjust the DC offset of the AC electrical signal to a plurality of DC offset voltages. Circuitry is coupled to the fly height sensor and the signal generator. The circuitry is configured to measure fly height of the slider in response to application of the AC electrical signal with varying DC offset voltages to the slider. The circuitry is further configured to determine an extremum of the measured fly heights and generate an output that includes the DC offset voltage associated with the fly height extremum.
US09245560B1 Data storage device measuring reader/writer offset by reading spiral track and concentric servo sectors
A data storage device is disclosed comprising a disk comprising a spiral track, and a head actuated over the disk, wherein the head comprises a read element offset radially from a write element by a reader/writer offset. The spiral track is first read to write a plurality of concentric servo sectors on the disk that define at least one concentric servo track on the disk. The spiral track is second read and the concentric servo sectors are read to measure the reader/writer offset.
US09245556B2 Disk drive employing multiple read elements to increase radial band for two-dimensional magnetic recording
A disk drive is disclosed comprising a disk comprising a plurality of tracks, and a head comprising at least three read elements including a first read element, a second read element, and a third read element. When the head is within a first radial band of the disk, data recorded on the disk is detected using the first read element and the second read element. When the head is within a second radial band of the disk different from the first radial band, data recorded on the disk is detected using the first read element and the third read element. The first read element is substantially aligned down-track with the third read element when the head is over a first radial location of the disk.
US09245555B2 Low resistance ground joints for dual stage actuation disk drive suspensions
Stable, low resistance conductive adhesive ground connections between motor contacts and a gold-plated contact area on a stainless steel component of a dual stage actuated suspension. The stainless steel component can be a baseplate, load beam, hinge, motor plate, add-on feature or flexure.
US09245554B2 Tilted structures to reduce reflection in laser-assisted TAMR
A TAMR (Thermal Assisted Magnetic Recording) write head uses the energy of optical-laser excited surface plasmons in a plasmon generator to locally heat a magnetic recording medium and reduce its coercivity and magnetic anisotropy. The optical radiation is transmitted to the plasmon generator by means of a waveguide, whose optical axis (centerline) is tilted relative to either or both the backside surface normal and ABS surface normal in order to eliminate back reflections of the optical radiation that can adversely affect the properties and performance of the laser. Variations of the disclosure include tilting the plasmon generator, the waveguide and the laser diode.
US09245553B2 Submount-integrated photodetector for monitoring a laser for a heat-assisted magnetic recording head
In a heat-assisted magnetic recording hard disk drive, a laser module includes a submount-integrated photodetector configured to receive optical energy from a laser by way of a head slider. The submount may be formed of a semiconductor material such as a crystalline silicon material, and the photodetector may be a photodiode that is integrally formed with the submount. A HAMR head slider may comprise a feedback waveguide configured to guide optical energy from the laser through the slider to a feedback photodiode at an interface of the submount and the slider, to detect the optical energy transmitted through the slider to the slider air bearing surface (ABS). A back facet photodiode may also be integrally formed with the submount and configured to receive back facet optical energy to detect the optical energy generated by the laser.
US09245552B2 Head gimbal assembly and disk device with the same
According to an embodiment, a head gimbal assembly includes a support plate, a wiring member, a magnetic head and drive members. A gimbal portion of the wiring member includes a thin metallic plate including a tongue portion mounted with a magnetic head, a proximal end portion fixed to the support plate, support projections, and link portions, an insulating layer including first bridge portions extending from the proximal end portion to the tongue portion, and second bridge portions extending from the proximal end portion to middle portions of the first bridges, and a conducive layer including signal wirings extending to the tongue portion through the second and first bridge portions, and reinforcement wiring portions. The drive members are provided at the first bridge portions.
US09245551B2 Nitrogen-vacancy nanocrystal magnetic source sensor
A sensor may be configured with a nanocrystal that has a nitrogen-vacancy. The nanocrystal can be positioned proximal a magnetic source, mount, and articulable stage. Various embodiments configure the articulable stage configured to align the nanocrystal and the magnetic source along a common axis to sense magnetic fields about the magnetic source with a sub-nanometer resolution.
US09245549B2 Thermally stable low random telegraph noise sensor
In one embodiment, magnetic read head includes a seed layer including an amorphous alloy film and Ru film positioned thereon, and an antiferromagnetic (AFM) layer positioned above the seed layer, the AFM layer including an alloy of MnIr having an L12 ordered phase, the amorphous alloy including a Co—X alloy having more Co than any other element, with X including at least one of: Zr, Nb, Ta, Hf, W, Si, and Al. In another embodiment, a method for forming a magnetic read head includes forming a seed layer above a substrate, heating at least the substrate to a first temperature in a range from about 150° C. to about 300° C., cooling at least the substrate to a second temperature of less than about 100° C., and forming an AFM layer above the seed layer between the heating and the cooling, the AFM layer comprising a MnIr alloy.
US09245540B1 Voice coil motor temperature sensing circuit to reduce catastrophic failure due to voice coil motor coil shorting to ground
An electrical circuit includes: a controlled switch; one or more temperature sensors in thermal contact with the controlled switch; and a control unit configured to: receive a temperature signal from the one or more temperature sensors; compare the received temperature signal to a predetermined threshold; and in response to the received temperature signal exceeding the predetermined threshold, render the controlled switch inoperative.
US09245537B2 Speech enhancement apparatus and method for emphasizing consonant portion to improve articulation of audio signal
In a speech enhancement apparatus, a generator part generates a value representing likelihood of a consonant from an input audio signal, and a calculator part generates a consonant/vowel discriminating signal for discriminating a consonant portion and a vowel portion based on the generated value, detects a first signal level of the vowel portion and a second signal level of the consonant portion based on the audio signal and the consonant/vowel discriminating signal, and outputs a level-related signal. A determining part determines a gain coefficient that exceeds one when the second signal level is smaller than the first signal level based on the level-related signal so that the gain coefficient increases as the second signal level becomes smaller than the first signal level. A multiplier part multiplies the audio signal by the gain coefficient to output an audio signal having an emphasized consonant portion.
US09245531B2 Joint source channel decoding using parameter domain correlation
Methods, systems, and apparatuses are provided for performing joint source channel decoding in a manner that exploits parameter domain correlation. Redundancy in speech coding and packet field parameters is exploited to generate conditional probabilities that a decoder utilizes to perform joint source channel decoding. The conditional probabilities are based upon correlations of parameters of a current frame with parameters of the same or other frames or historical parameter data. Parameter domain correlation provides significant channel decoding improvement over prior bit domain solutions. Also provided are methods, systems, and apparatuses for utilizing received statistics of monitored data bits from which conditional probabilities are generated to perform channel decoding. The techniques described may be implemented at the decoder side and thus do not interfere with transmission standards.
US09245524B2 Speech recognition device, speech recognition method, and computer readable medium
The present invention can increase the types of noises that can be dealt with enough to enable speech recognition with a speech recognition rate of high accuracy.A speech recognition device of the present invention performs processes of: storing, in a manner to relate them to each other, a suppression coefficient representing a noise suppression amount and an adaptation coefficient representing an adaptation amount of a noise model, where the noise model is generated on the basis of a predetermined noise and is to be compounded (synthesized) to a clean acoustic model generated on the basis of a voice including no noise; estimating noise from an input signal; suppressing from the input signal a portion of the estimated noise of an amount specified by a suppression amount specified on the basis of the suppression coefficient; generating an adapted acoustic model which is noise-adapted, by compounding (synthesizing) the clean acoustic model with a noise model generated on the basis of the estimated noise in accordance with an adaptation amount specified on the basis of the adaptation coefficient; and recognizing voice on the basis of the noise-suppressed input signal and the generated adapted acoustic model.
US09245520B2 Reverberator and method for reverberating an audio signal
A reverberator for reverberating an audio signal includes a feedback delay loop processor for delaying at least two different frequency subband signals representing the audio signal by different loop delays to obtain reverberated frequency subband signals.
US09245519B2 Forward speaker noise cancellation in a vehicle
Systems and methods to cancel noise in a vehicle are disclosed. A first speaker is positioned forward of a steering wheel of a vehicle. The first speaker generates a first signal configured to acoustically cancel noise produced by operation of the vehicle. A second speaker is positioned forward of the steering wheel. The second speaker generates a second signal to acoustically cancel the noise produced by the operation of the vehicle. The first and the second speakers are capable of generating the first and the second signals independently of one another.
US09245516B2 Noise removal device
A noise removal device which removes noise included in a signal, includes: a statistical parameter calculation portion configured to calculate a parameter which expresses distribution of the noise based on the signal; and a noise removal portion configured to remove the noise from the signal by changing an element which relates to a process of removing the noise from the signal depending on the parameter which expresses the distribution of the noise.
US09245509B2 Recording and reproduction of waveform based on sound board vibrations
In a musical instrument, such as a piano, having a sound board, the sound board vibrates in response to vibrations of a string responsive to depression of a key. A waveform corresponding to such vibrations of the sound board is detected and recorded into a memory for each of the keys. The recorded vibration waveform is usable for reproduction of a sound based on sound board vibrations. In a sound reproduction apparatus, such as a piano, having a sound board, an excitation device physically excitable in response to an input waveform is provided on the sound board. In response to an operation of a key, a sound board vibration waveform corresponding to the operated key is read out from the memory, and the excitation device is driven in accordance with the read-out waveform signal so that the sound board is vibrated.
US09245508B2 Music piece order determination device, music piece order determination method, and music piece order determination program
A beat information corrector acquires beat position information including information regarding a point of time when a beat is reproduced, acquires a tempo value indicating a number of beats per unit time in a music piece, and corrects the beat position information of the music piece so that the tempo value of the music piece be a same value as the reference value. A correlation value calculator calculates a correlation value, which indicates a degree of correlation of beat position information between respective music pieces among a plurality of the music pieces, based on the corrected beat position information. A music piece order determiner determines a music piece order as a reproduction order of music pieces, which are to be reproduced successively, so that a product or total sum of the correlation values between the music pieces be at a maximum or an approximate solution thereof.
US09245504B1 Instructional drum music practice device
An instructional drum practice pad overlays a larger polygon base containing preferably twelve typical rudiments used in teaching musical drum playing to students. Preferably the polygonal base is a twelve sided polygon, known as a dodecagon. The lightweight durable base has a diameter of preferably about 13 inches and a height of about ½ inch, with the upper pad having a diameter of about 10 inches and being preferably a ⅜ inches thickness pad of 40 durometer gum rubber. There is a bottom base of neoprene that is about 3/16 inch thick. Rudiments, or symbolic music note symbols to teach the proper drum music beats, are provided in a peripheral array around the base frame, while leaving the striking pad free of any visual distractions. Optionally, multiple rudiment bearing rings can be stacked over the upper drum practice pad.
US09245501B2 Total field of view classification
Virtual objects are located for display in a head-mounted display (HMD) to provide an augment reality view to an HMD wearer. An HMD wearer's total field of view (TFOV) is classified into two or more regions. Additionally, a field of view (FOV) for the HMD wearer is determined. The FOV is compared with the two or more regions of the HMD wearer's TFOV. Responsive to this comparison, virtual objects are determined for display based on a location of the FOV relative to the two or more regions of the HMD wearer's TFOV. The virtual objects may then be displayed by the HMD at an appropriate location.
US09245500B1 System and method for preventing image capture
The present invention is directed to a non-transitory machine readable storage medium containing program instructions for displaying digital content while preventing image capture, the non-transitory machine readable storage medium configured to generating a mask to superimpose upon a display object with the mask including one or more transparent portions and one or more opaque portions that blocks the display object therebeneath from viewing; and moving the one or more transparent portions of the mask incrementally to expose various portions of the display object in sequence. The display object may be image, text, video, or any combination thereof. The one or more transparent portions of the mask may have a linear shape extending along a first direction and may move in a second direction substantially perpendicular to the first direction. Alternatively, the one or more transparent portions of the mask may have a sector-shaped opening that rotates to expose the display object.
US09245499B1 Displaying glasses with recorded images
Processing a set of images is disclosed, including: receiving a set of images; and searching for a representation of a user's face associated with the set of images and a plurality of sets of extrinsic information corresponding to respective ones of at least a subset of the set of images. Rendering a glasses frame is disclosed, including: receiving a selection associated with the glasses frame; rendering the glasses frame using at least a representation of a user's face and a set of extrinsic information corresponding to an image in a recorded set of images; and overlaying the rendered glasses frame on the image.
US09245498B2 Display system having a semitransparent display device displaying symbols with a contrasted outline
The general field of the invention is that of display systems comprising means for generating graphic symbols and an associated semitransparent display device. The display device according to the invention has two overlaid semitransparent flat display screens, one passive and the other active, each symbol displayed on the semitransparent display device comprising a first representation and a second representation. The first representation is displayed on the first display screen with a low transmission rate for the light and with a predetermined first size. The second representation is displayed on the second display screen in the same place as the first representation, with a luminance and a predetermined second size that is smaller than the first size so that the second representation is overlaid on the first representation and the displayed symbol appears bright with a dark border.
US09245493B2 Devices and methods for indicating active frame starts
Devices and methods for providing an indication of an active frame start, while reducing a number of line buffers utilized by conventional systems are provided herein. By way of example, an electronic display panel may include a host device (e.g., a processor) that provides an indication of a pending active frame start. The indication may be provided at a predetermined and fixed time/line interval before the active frame start. Next, a timing controller of the display circuitry may generate a vertical start pulse during vertical blanking based upon the indication and the fixed time/line interval. The vertical start pulse may be used to drive multi-clock integrated row driver circuits.
US09245491B2 First de-compressing first compressing schemes for pixels from/to bus interface
A multimedia system includes a processor coupled to a memory, a three-dimensional (3D) graphics engine to generate 3D graphics content, and a display controller to process and transport pixel data for transmission to a display via a display interface. Each of the processor, the 3D graphics engine, and the display controller accesses pixel data stored in the memory using a common decompression scheme. Additionally, each of the processor, the 3D graphics engine, and the display controller stores pixel data in the memory using a common compression scheme.
US09245489B2 Gate driving circuit and display apparatus having the same
A display apparatus including a gate driving circuit configured to include a plurality of stages connected to each other one after another. An i-th stage of the stages includes an output transistor and a control part. At least one control transistor included in the control part includes a first control electrode to which a switching control signal is applied, and a second control electrode disposed on a layer different from a layer on which the first control electrode is disposed, and to which a reference voltage is applied.
US09245487B2 Systems and methods for reducing loss of transmittance due to column inversion
Systems, methods, and devices for reducing the loss of transmittance caused by column inversion. To provide one example, an electronic display may include a display panel with columns of pixels and driver circuitry to drive the pixels using column inversion. Adjacent columns that are driven at like polarity are spaced more closely than adjacent columns driven at opposite polarities.
US09245485B1 Dithering techniques for electronic paper displays
Techniques for generating dithered images for display on electronic paper displays set to one-bit display modes are described herein. An electronic device having an electronic paper display sets a display mode parameter associated with the electronic paper display to a one-bit display mode. The electronic device or a remote service further generates a dithered image from a monochrome image based at least in part on a one-bit dithering algorithm. While the display mode parameter is set to the one-bit display mode, the electronic device then displays the dithered image on the electronic paper display.
US09245484B2 E-book reader
An e-book reader including a display panel having a thin film transistor with stable electrical characteristics is provided. Alternatively, an e-book reader capable of holding images for a long time is provided. Alternatively, a high-resolution e-book reader is provided. Alternatively, an e-book reader with low power consumption is provided. Display on the display panel of the e-book reader is controlled by a thin film transistor whose channel formation region is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor by removal of an impurity that might be an electron donor in the oxide semiconductor and has a larger energy gap than a silicon semiconductor.
US09245483B2 Backlight module and display apparatus
A backlight module including a light guide plate, light source sets, and controlling circuits is provided. The light guide plate has a plurality of regions, and each region of the light guide plate has a light incident surface correspondingly. Each light source set is disposed at the light incident surface of one of the regions of the light guide plate, and each light source set has at least one middle light source and at least one edge light source. The middle light source is disposed in a middle region of the light source set and the edge light source is disposed at an edge of the light source set. Each controlling circuit is electrically connected to the middle light source of one of the light source sets, and the edge light source of each light source set is electrically connected to the controlling circuit of the adjacent light source set.
US09245475B2 Display panel and demultiplexer circuit thereof
A display panel and a demultiplexer circuit are provided. The demultiplexer circuit includes a first to a Pth switch units. The first to the Pth switch units are coupled to a first to a Pth data lines of a display panel respectively and collectively receive a data voltage and turn on sequentially in sequence to provide the data voltage to corresponding data lines. A period of the first to the Pth switch units provide the data voltage to the first to the P data lines sequentially which is defined to a data transmission period. When the switch unit is turned on, N transistors are turned on simultaneously according to a plurality of control signals. When the switch unit is turned off, at least one of the N transistors is turned off according to a corresponding control signal.
US09245474B2 Display driving device and method for driving display
A display driving device and a method for driving a display are provided. The display driving device includes a host and a driving chip. The host transmits an image data and a synchronization signal. The driving chip receives the image data and the synchronization signal and drives a display panel to display frames. The driving chip includes a storage unit, a driving module, and a control circuit. The storage unit stores the image data. The driving module drives the display panel to display the frames according to the image data from the host and a timing generator frequency of the driving module. The control circuit detects a target frequency of the synchronization signal and the timing generator frequency of the driving module, compares the target frequency and the timing generator frequency, outputs an adjustment value according to the comparison result, and adjusts the timing generator frequency of driving module.
US09245471B2 Multiple-primary color liquid crystal display apparatus
A multi-primary-color liquid crystal display device (100) according to the present invention includes a liquid crystal display panel (10) with a pixel made up of red, green, blue and yellow subpixels (R, G, B, Ye) and a signal conversion circuit (20) which converts an input three-primary-color video signal into a four-color video signal. If the three-primary-color video signal supplied to the signal conversion circuit is indicated as (r, g, b) using the grayscale levels r, g and b (each of which is an integer of 0 through 255) of the three primary colors of red, green and blue and if the luminance of the color white displayed by the pixel in response to a three-primary-color video signal indicated as (255, 255, 255) is supposed to be 100%, the signal conversion circuit adjusts the level of the four-color video signal so that when a three-primary-color video signal indicated as (186, 0, 0) is input, the luminance of the color red displayed by the red subpixel becomes equal to or greater than 6.5%.
US09245466B2 Safety sign system
A safety sign system comprises one or more traffic or informational signs, an expandable pole, a detachable umbrella canopy assembly, and a safety finial assembly. The signs are removably attached to a sleeve that surrounds a portion of a pole and rests upon a sign support. The sleeve with the signs attached swivels about the pole. The umbrella canopy assembly is attached to an upper end of the pole and may include additional features including reflective tape, vents, drop-down flaps, reflective coating, and lights. The safety finial assembly is removably attached to the top of the umbrella canopy assembly and may include flag supports, removable flags, and a safety light assembly. The safety sign system optionally further comprises a collapsible seat, a beverage holder, a satellite tracking device, a communication device, a base, and a control panel for operating the safety light and other features.
US09245463B2 Display apparatus and method of manufacturing the same
A display apparatus includes a first substrate, a second substrate, a pixel layer and an adhesive part. The first substrate includes an adhesive area, fiber bundles and a base material which is impregnated between the fiber bundles. The second substrate includes an adhesive area, fiber bundles and a base material which is impregnated between the fiber bundles. The pixel layer is between the first and second substrates and includes a display area. The adhesive part is between the first substrate and the second substrate, is in each of the adhesive areas of the first and second substrates, and seals the pixel layer between the first and second substrates. The adhesive area of the first or second substrate includes an exposure area through which the fiber bundles are exposed, and the adhesive part contacts the exposure area.
US09245460B2 Multipurpose rotation structure
Disclosed herein is a multipurpose rotation structure which is installed indoors or outdoors to be utilized for multiple purposes such as experience teaching tools by using repelling force between magnets disposed in an outer ring frame having the shape of a ring and in a weight body rotating in an inner space of the outer ring frame, by particularly using repelling force between magnets disposed in a weight body and a second weight body placed on the same guide ring, or by using repelling force between magnets disposed in an outer ring frame and an inner ring frame that are opposite to each other with respect to a weight body, or by using attractive force and repulsive force between magnets while sequentially changing the polarity of electromagnets disposed in an outer ring frame and an inner ring frame.
US09245459B2 Display screen and display system thereof
A display screen includes a substrate and a fluorescent material. The substrate includes a plurality of pixel regions arranged in an array, wherein each pixel region includes a fluorescent region and a transparent region, and the area of the transparent region is larger than the area of the fluorescent region. The fluorescent material is arranged in the fluorescent region and excited by an excitation light to emit a visible light to form an image. The above-mentioned display screen allows a viewer to see the images formed by the fluorescent region and the environmental image at the other side of display screen. A display system including the above-mentioned display screen is also disclosed.
US09245449B1 Constraint processing as an alternative to flight management systems
Methods and apparatus for providing trajectory planning for an aircraft based on constraint processing are disclosed. The method may take into consideration the dynamic or real-time operational and environmental factors, and utilizes constraint processing to provide trajectory optimizations between the end points of the flight. The trajectory planning method may be performed utilizing a computer or processor onboard the aircraft. The method may include receiving a starting location and an ending location for a phase of flight of the aircraft; receiving a set of constraints from multiple systems and sensors for the phase of flight of the aircraft, wherein operations of the aircraft during the phase of flight are subject to the set of constraints; and analyzing the set of constraints to determine an optimal trajectory between the starting location and the ending location, the optimal trajectory is determined based on compliance with the set of constraints.
US09245448B2 Driver assistance system for a vehicle
A driver assistance system for a vehicle includes a forward facing and a control having an image processor that processes image data captured by the camera. At least in part responsive to processing by the image processor, an alert to a driver of the equipped vehicle is generated based upon at least one of (i) detection of an inappropriate lane change maneuver of the equipped vehicle and (ii) a detection of a potential impact with another vehicle. The image processor processes image data captured by the forward facing camera to detect a traffic control device present within the field of view of the forward facing camera, and the system may generate an alert to the driver when it is determined that the vehicle is not appropriately responding to the detected traffic control device.
US09245446B2 Switched link-based vehicular network architecture and method
A multiple hop communications method among a plurality of moving vehicles. Each moving vehicles has a plurality of unidirectional radio. The method comprises receiving an incoming packet at one of the plurality of unidirectional radios, determining if there is an active link between each of the plurality of unidirectional radios and an unidirectional radio of a neighbor vehicle, relaying the incoming packet to the plurality of unidirectional radios having an active link and transmitting the incoming packet as an outgoing packet from at least one of the plurality of unidirectional radios. If more than one packet is received, the packets can be encoded using group coding before send the packets out as an outgoing packet.
US09245445B2 Optical target detection
An optically-based target detection system includes a holographic detection filter designed to produce a concentrated spot when a target is present.
US09245436B1 Hydrogen sulfide alarm methods
H2S (hydrogen sulfide) alarm methods include automated systems for creating reports, initiating different safety drills and/or recording certain calibration and bump tests. The methods being automated reduces the chance of human error and falsified records. The H2S alarm methods are particularly useful for ensuring the safety of workers at remote worksites.
US09245428B2 Systems and methods for haptic remote control gaming
Systems and methods for haptic remote control gaming are disclosed. In one embodiment a portable multifunction device receives information from a remotely controllable device. The portable multifunction device can be operable as a remote control for the remotely controllable device. The portable multifunction device may be a smartphone, a tablet computer, or another suitable electronic device. The portable multifunction device can determine a haptic effect based at least in part on the information received from the remotely controllable device. The portable multifunction device may generate a signal configured to cause an actuator to output the determined haptic effect. The portable multifunction device can output the signal.
US09245426B2 Control of lighting devices
A network of active sensors in a control system is considered. The active sensors, which may be fixed-infrastructure sensors, provide presence detection information to a distributed lighting system. The active sensors communicate by transmitting probe signals. The communication of probe signals may result in cross-interference which may vary in time. Cross-interference is detected, and can later be avoided, by determining a difference between signals received in a first part of a timeslot and signals received in a second part of the timeslot. In order to do so probe signals comprising two non-zero pulses are transmitted in respective parts of the timeslot. Applications are, for example, active presence sensors in lighting control applications in indoor as well as outdoor environments.
US09245418B2 Multiple game gaming machine
A gaming machine comprises a display and a game controller arranged to control images of symbols displayed on the display. The game controller is arranged to play a game wherein at least one random event is caused to be displayed on the display and, if a predefined winning event occurs, a prize is awarded. A plurality of sub-games constitute the game displayed on the display. As an initial display, fewer than a full set of images of each of the sub-games are displayed to show a partial outcome of the game, the fewer than the full set of images being representative of a determination of an expected value for each of the sub-games.
US09245416B2 Secure identification devices and methods for detecting and monitoring access thereof
A game token having a counter system including a denomination value, a housing, and a token identification element at least partially contained within the housing is disclosed. The token identification element includes an antenna configured to receive and transmit a signal, a memory configured to store a plurality of different types of token data, a counter configured to modify and maintain a read attempt value, and a processor or control logic. The processor or logic control configured to, upon a read attempt of the memory by a reader, compare a signature of the reader against the one or more authorized reader signatures, and generate an alert when the signature does not match any one of the one or more authorized reader signatures.
US09245415B2 Single sign-on for wager gaming players over a wide-area network
When the player identifies herself to a gaming machine at a casino, for example by inserting a player tracking card into the card reader, she is, at generally the same time, logging onto a game provider's backend system (the game provider being different from the casino operator). This concurrent sign-on to the game provider's system is done in a non-intrusive, transparent, and passive manner. The player is not distracted from the normal steps leading to game play on the machine until she is ready to redeem points with the game provider or for some reason additional authentication is needed from the player. By virtue of this single sign-on to the game provider network, in addition to continuing game play across different casinos, the player can publish events to the Internet, such as on social networking sites, take advantage of offers targeted specifically for her, or facilitate responsible gaming programs.
US09245414B2 Gaming system and method for rewarding players
A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer, including storing player-useable points at a network-accessible location, enabling a player to convert at least some of the points into monetary units at a conversion rate, wherein the monetary units are convertible into credits for wagering on at least one of the electronic gaming machines, awarding a personal points conversion rate multiplier to a player, and applying the points conversion rate multiplier to the conversion rate.
US09245397B2 Instrument gauge
An instrument gauge includes a gauge face. A rotary portion is located on the gauge face. The rotary portion includes a rotary indicating element that is configured to rotate between a first rotary position and a second rotary position to indicate a first range of values of a vehicle parameter. A digital portion is located on the gauge face and includes a digital indicating element that is configured to move between a first digital position and a second digital position to indicate a second range of values of the vehicle parameter.
US09245393B2 Vehicle diagnostic system, vehicle diagnostic method, and external diagnostic device
In a vehicle diagnostic system and a vehicle diagnostic method, malfunction codes recorded in each ECU in a vehicle include idle stop malfunction codes that disallow idle stop, and a non-idle stop malfunction code that does not disallow idle stop. The idle stop malfunction codes include: a first idle stop malfunction code that operates a warning light provided corresponding to a specific ECU; and a second idle stop malfunction code that does not operate the relevant warning light. An external diagnostic device extracts, from the plurality of ECUs, only the second idle stop malfunction codes, among the first idle stop malfunction codes and the second idle stop malfunction codes, when performing malfunction diagnosis for non-execution of idle stop.
US09245391B2 Driver risk assessment system and method employing automated driver log
A system for reducing driving risk comprises an event capture device and a processor. The event capture device is to capture a driving event of a vehicle during a driving trip. A processor configured to assign a risk identifier to the driving event, to generate an event score based at least in part on the risk identifier, and to generate a driver score based at least in part on the event score and one or more driver challenge factors.
US09245389B2 Information processing apparatus and recording medium
There is provided an information processing apparatus including a display control unit configured to include a first display control mode in which control is performed in a manner that a first image from a user viewpoint, which is captured by a first imaging unit, is displayed on a display unit or control is performed in a manner that the display unit is transmissive, and a second display control mode in which control is performed in a manner that a second image captured by a second imaging unit including a user within an angle of view is displayed on the display unit, and a switching control unit configured to perform control in response to an instruction from the user in a manner that a display control mode of the display control unit is switched from the first display control mode to the second display control mode.
US09245382B2 User-guided surface reconstruction
Described is a technology by which a user interacts with a surface representative of a point cloud data to correct for imperfect scan data. The surface is reconstructed based on the interaction. Real time viewing of the image is facilitated by parallel surface reconstruction. For example, the user may draw strokes to reduce topological ambiguities in poorly-sampled areas. An algorithm automatically adds new oriented sample points to the original point cloud based on the user interaction. Then a new isosurface is generated for the augmented point cloud. The user also may specify the geometry of missing areas of the surface. The user copies a set of points from another point cloud, and places the points around the target area. A new isosurface is then generated.
US09245377B1 Image processing using progressive generation of intermediate images using photon beams of varying parameters
A method for rendering radiance for a volumetric medium is provided. A photon simulation produces a representation of photon beams in a scene. The photon beams are rendered with respect to a camera viewpoint, by computing an estimated radiance associated with the photon beams. A global radius scaling factor can be applied to obtain different radii for the photon beams. Over multiple applications of these steps, the global radius scaling factor can be decreased, thereby reducing overall error by facilitating convergence. Finally, the renderer can be efficiently implemented on the GPU as a splatting operation, for use in interactive and real-time applications.
US09245370B2 Image drawing apparatus, computer-readable medium storing program, and method of the same
An image drawing apparatus includes a drawing position judging unit configured to judge a figure drawn on the scan line to be processed and extract each of vertexes constituting the judged figure, an vertex information reading unit configured to read vertex information, an image generating unit configured to generate graphics data of the scan line, and a line buffer configured to store the graphics data, wherein the vertex information reading unit includes a cache memory, a cache tag configured to store an address storing the vertex information when the vertex information is stored in the cache memory, and a control unit configured to refer to the cache tag, and read the vertex information from the address of the cache memory when the address is stored, and store the vertex information in the cache memory and store the address in the cache tag when the address is not stored.
US09245368B2 Device and method for dynamically rendering an animation
A device includes one or more processors, and memory storing programs. The programs include a respective application and an application service module. The application service module includes instructions for, in response to a triggering event from the respective application, initializing an animation object with one or more respective initialization values corresponding to the triggering event. The animation object includes an instance of a predefined animation software class. At each of a series of successive times, the device updates the animation object so as to produce a respective animation value in accordance with a predefined animation function based on a primary function of an initial velocity and a deceleration rate and one or more secondary functions. The device updates a state of one or more user interface objects in accordance with the respective animation value, and renders on a display a user interface in accordance with the updated state.
US09245365B2 Dynamic digital image compositing using image templates
Techniques are disclosed for dynamic digital image compositing using a digital image template. A request is received to generate a composite digital image at a user-specified resolution based on a master digital image. Each of a plurality of digital image templates includes image data representing a different, particular resolution of the master digital image. The digital image templates can be stored in a common file with the master digital image. One of the digital image templates associated with a resolution that is at least as high as and closest to the user-specified resolution is selected for compositing. Composite image data is then generated based on the selected digital image template. Next, the composite image is rendered based on the composite image data and scaled to the user-specified resolution.
US09245361B2 Consolidating glyphs of a font
One or more techniques and/or systems are disclosed for consolidating one or more glyphs of a font. A common contour, comprising a glyph contour that occurs more than once in one or more glyphs of the font, can be identified. A common simple glyph can be created for the identified common contour. A reference to the common simple glyph can replace one or more occurrences of the common contour in the one or more glyphs of the font. Given that the common simple glyph is generally smaller than the common contour, an amount of font related data for the font can be reduced, thus reducing overhead associated with storing and/or presenting the font.
US09245359B2 Apparatus and method for generating medical image using linear gamma ray source
Methods and apparatuses for generating a blur model of a detector, and methods and apparatus for generating a medical image are provided. A method of generating a blur model of a detector may involve: changing locations of linear gamma ray sources along at least one line and obtaining signals emitted from the linear gamma ray sources; obtaining a point spread function (PSF) with respect to at least one voxel included in the at least one line; and generating a blur model of the detector from the PSF.
US09245352B1 Systems and methods for near lossless image compression
Systems and methods for iterative near lossless image compression are provided. An exemplary computer-implemented method of compressing image data can include performing a plurality of compression iterations. Each compression iteration can include at least one decision regarding a loss of image data. The method can also include updating an entropy model following each compression iteration. The entropy model can describe an entropy associated with selected of a plurality of data blocks. The at least one decision regarding the loss of image data can be decided, for each compression iteration, based on the entropy model as updated following the previous compression iteration. Further, a total loss of image data from each data block can remain within an acceptable loss bound associated with the pixel described by such data block. An exemplary system can include a loss determination module, an entropy modeling module, a compression module, and an entropy coding module.
US09245348B2 Determining a maximum inscribed size of a rectangle
Embodiments perform an iterative process for enlarging a rectangle having a fixed aspect ratio within a convex polygon to find the largest rectangular area within the convex polygon. The iterative process includes detecting an intersection of one or more corners of the rectangle with the convex polygon and adjusting a position of the rectangle based on the quantity of intersecting corners. The iterative growth process continues until a maximum inscribed size of the rectangle has been determined. Some embodiments process images from bracketed photography and crop areas outside the determined maximum inscribed size when combining the images into a single image.
US09245347B2 Image Cropping suggestion
Image cropping suggestion is described. In one or more implementations, multiple croppings of a scene are scored based on parameters that indicate visual characteristics established for visually pleasing croppings. The parameters may include a parameter that indicates composition quality of a candidate cropping, for example. The parameters may also include a parameter that indicates whether content appearing in the scene is preserved and a parameter that indicates simplicity of a boundary of a candidate cropping. Based on the scores, image croppings may be chosen, e.g., to present the chosen image croppings to a user for selection. To choose the croppings, they may be ranked according to the score and chosen such that consecutively ranked croppings are not chosen. Alternately or in addition, image croppings may be chosen that are visually different according to scores which indicate those croppings have different visual characteristics.
US09245344B2 Method and apparatus for acquiring geometry of specular object based on depth sensor
A method of acquiring geometry of a specular object is provided. Based on a single-view depth image, the method may include receiving an input of a depth image, estimating a missing depth value based on connectivity with a neighboring value in a local area of the depth image, and correcting the missing depth value. Based on a composite image, the method may include receiving an input of a composite image, calibrating the composite image, detecting an error area in the calibrated composite image, and correcting a missing depth value of the error area.
US09245333B1 Systems and methods for detecting obstructions within the field-of-view of an image sensor
An imaging system may include an image sensor and a transparent protective layer formed within the field-of-view of the image sensor. The imaging system may include a light source that emits light in a predetermined pattern. The imaging system may include circuitry that may detect a reflected version of the predetermined pattern of light in image data captured by image sensor. In response, the imaging system may determine an obstruction is present within the field-of-view of the image sensor. The obstruction may be located on the transparent protective layer and may be within 10 centimeters of the image sensor. The light source and image sensor may be located in the interior of a vehicle and oriented to face the exterior of the vehicle. The imaging system may use the image data captured by the image sensor to perform vehicle assist functions for the vehicle.
US09245332B2 Method and apparatus for image production
An improved lighting technique via a lighting technique utilizing a light source invisible to the subject is provided herein. The improved lighting technique capability blends image data from an image detector sensitive to visible light with corresponding image data from an image detector sensitive to light not visible to humans to create an improved image.
US09245328B2 Algorithm for minimizing latent sharp image cost function and point spread function with a spatial mask in a fidelity term
A method for deblurring a blurry image (18) includes utilizing a spatial mask and a variable splitting technique in the latent sharp image estimation cost function. Additionally or alternatively, the method can include the utilizing a spatial mask and a variable splitting technique in the PSF estimation cost function. The spatial mask can be in a fidelity term in either or both the latent sharp image estimation cost function and the PSF cost function. The latent sharp image estimation cost function can be used for non-blind deconvolution. Alternatively, one or both cost functions can be used for blind deconvolution.
US09245326B2 Method and device for generating a super-resolution version of a low resolution input data structure
The invention relates to the improvement of the resolution of regularly sampled multi-dimensional signals, where a single low-resolution signal is available. These methods are generically referred to as example-based super-resolution or single-image super-resolution. The method for super-resolving a single image comprises three stages. First, an interpolation-based up-scaling of the input image is performed, followed by an equivalent low-pass filtering operation on the low-resolution image. The second stage comprises a search for low-frequency matches between an inspected patch in the high-resolution image and patches in a local neighborhood in the low-resolution low-frequency image, including partly overlapping patches, and accumulating the high-frequency contribution obtained from the low-resolution image. The third stage comprises adding the contributions of the low-frequency band of the high-resolution image and the extrapolated high-frequency band.
US09245323B2 Medical diagnostic device and method of improving image quality of medical diagnostic device
A medical diagnostic device is characterized in that an image processing unit (22) includes an image noise removal part (211, 211′) which removes the noise in the generated image of a person to be examined, a signal component enhancement processing part (212, 212′) which generates an enhanced-signal component image by performing signal component enhancement processing of the image from which the noise is removed by the image noise removal part, and an image combining part (213, 213′) which generates a combined image by combining the image of the person to be examined, the image from which the noise is removed by the image noise removal part, and an enhanced-signal component image subjected to signal component enhancement processing by the signal component enhancement processing part.
US09245312B2 Image panning and zooming effect
In one embodiment, when an image is displayed on an electronic device, the image may be panned from one portion to another portion based on information associated with the image or a user viewing the image. In some embodiments, the image may pan starting from a leftmost user in the image and moving to the rightmost user in the image. In some embodiments, the image may pan starting from a specific user near the center of the image and zooming outward until the entire image is displayed. In some embodiments, the image may pan starting from a first user in the image having a highest affinity with the user viewing the image, and ending with a second user in the image having a lowest affinity with the user viewing the image.
US09245310B2 Content watermarking
In an embodiment, a method of watermarking a video includes generating three or more pilot signals. The method also includes generating a watermark. The method also includes embedding the three or more of the pilot signals in first frames of the video. The method also includes embedding the watermark in second frames of the video according to a watermarking just-noticeable-difference (JND) model. The second frames may be non-overlapping with the first frames.
US09245309B2 Feedback and simulation regarding detectability of a watermark message
Providing feedback regarding potential detectability by a decoder of a watermark message produced by a watermarking encoder includes receiving a watermark detectability indication that does not directly correspond to detectability of the watermark message by the decoder but is only a proxy for detectability of the watermark message by the decoder, transforming the watermark detectability indication into an enhancement indication corresponding to a prescribed enhancement to a watermark signal in which the watermark message is embedded based on the watermark detectability indication, and transmitting the enhancement indication to enhance the watermark signal thereby enhancing detectability of the watermark message.
US09245308B2 Encoding in two chrominance directions
The present disclosure relates generally to advanced digital signal processing including digital watermarking. One claim recites an apparatus comprising: memory for storing a color video signal or color image signal comprising first data representing a first chrominance direction and second data representing a second chrominance direction; and a processor programmed for: transforming the first data representing the first chrominance direction by encoding a first digital watermark component in the first data, the encoding a first digital watermark component in the first data utilizing a first encoding gain, and transforming the second data representing the second chrominance direction by encoding a second digital watermark component in the second data, the encoding a digital watermark signal in the second data utilizing a second encoding gain, wherein the second digital watermark component comprises an inverted signal relative to the first digital watermark component. Of course, other claims and combinations are disclosed.
US09245307B2 Structured light projection for motion detection in augmented reality
Technologies are generally described for projecting structured light patterns onto an Augmented Reality (AR) scene in order to track AR camera motion in AR systems. In some examples, structured light patterns may be projected onto the AR scene from a light source in the same plane as the AR camera in order to preserve a consistent reference point for detecting the structured light pattern. The AR camera may detect the structured light patterns and determine the location of the AR camera based on a distance analysis of the detected structured light patterns. Based on the changing locations of the AR camera, the system may track the movement of the AR camera as its location relative to the AR scene changes.
US09245303B2 On-board vessel entertainment system
An improved user experience is provided for passengers on a vessel such as an airplane, train or ship. Passengers can customize their travel experience ahead of time by accessing a web-based server system to indicate preferences with respect to a number of in-flight entertainment options. The passenger's experience is also enhanced by allowing passengers to share preferences such as media playlists with others. Meals can be ordered on-demand once on board, and seat-to-seat chat as well as group chatting is also made available through an in-seat or other proximate entertainment device.
US09245300B2 Social network mapping
Methods and systems are disclosed that may retrieve and filter a call history log or related data, select users based on the results of filtering, and provide proposed contacts to a communication service. The filtering may comprise a variety of criteria and the criteria may be assigned different weights.
US09245299B2 Segmentation and stratification of composite portfolios of investment securities
A stratified or segmented composite portfolio can be formed by selecting a group of investment securities, stratifying or segmenting them according to attributes that correlate to a specific asset risk, and assigning relative portfolio weights to the components based on their stratified or segmented positions. The attributes are selected from a universe of possible values. Further positive and negative biases can be applied at any arbitrary point or position, including to individual assets, groups of arbitrarily selected assets, or arbitrary positions.
US09245297B2 Forward-looking transactive pricing schemes for use in a market-based resource allocation system
Disclosed herein are representative embodiments of methods, apparatus, and systems for distributing a resource (such as electricity) using a resource allocation system. One of the disclosed embodiments is a method for generating a bid value for purchasing electricity in a market-based resource allocation system. In this embodiment, a desired performance value indicative of a user's desired performance level for an electrical device is received. Price information from an electricity futures market is received. A bid value for purchasing electricity from a local resource allocation market sufficient to operate the electrical device at the desired performance level is computed. In this embodiment, the computing is performed based at least in part on the desired performance value and based at least in part on the price information from the electricity futures market.
US09245296B2 Expense report system with receipt image processing
A system and method for processing receipt image data is disclosed. The system includes an image capture device and an image splitting module. In one embodiment, the image capture device is augmented to capture in a single scan four images arranged in a 2×2 grid pattern, nine images arranged in a 3×3 grid pattern, twelve images arranged in a 3×4 grid pattern or sixteen images arranged in a 4×4 grid pattern. The image splitting module recognizes scans of the image capture device that include multiple images and splits the images for the proper processing by the rest of the system.
US09245291B1 Method, medium, and system for purchase requisition importation
In an embodiment, a computer-implemented method operating at a server system is disclosed. The server hosts and electronic procurement system. One or more user instructions for importing a purchase requisition are received. In response to the one or more instructions, a purchase requisition is received, where the purchase requisition originates from outside the electronic procurement system. The purchase requisition is converted from a first format to a second format, wherein the second format is native to the electronic procurement system. The converted purchase requisition verified to be consistent with business rules associated with the electronic procurement system, including at least a rule to verify that the purchase requisition originates from a recognized user of the electronic procurement system. Then, the purchaser requisition is routed for approval. Related methods and systems are also disclosed.
US09245290B2 Caspase inhibitors and uses thereof
This invention provides novel caspase inhibitors useful for prophylaxis or treatment of a number of pathologies, including, for example, Huntington's disease. In certain embodiments the inhibitors include inhibitors of casepase-3 and/or casepase-6.
US09245289B2 Taxonomy and data structure for an electronic procurement system
A computer-implemented method is described, performed at a server hosting an electronic procurement system. Supplier catalog data is received at the server from a plurality of respective suppliers associated with the electronic procurement system. The supplier catalog data is in a plurality of formats. The supplier catalog data is converted from the respective plurality of formats to respective common format catalog data. The respective common format catalog data is added to a database.
US09245288B1 Experience sharing for a registry event
Disclosed herein are methods and corresponding systems for facilitating a live registry event between a shopper and one or more remote viewers. In the live registry event, the shopper, registers for gifts that they would like to receive while sharing their registering experience with the viewers in real-time. When the user registers for an item, a server system allows the viewers to purchase the gift for the shopper.
US09245285B2 Collection controller for influencing service to a user station
A content provider provides a content provider and service identification to a collection controller. The collection controller retrieves content provider and service specific service provision characteristics from a user subscription database and sets these service provision characteristics as a filter in a service provision control device to be used in the provision of a service from the content provider to the user equipment. Thus, the content provider, through the retrieved content server & service related characteristics from the user subscriber database, can influence the charging and transmission policies used by service provision control device for providing the service.
US09245283B2 Incentive imaging methods and devices
A method of providing incentives to customers which involves providing customers with cards having changeable display areas. During a transaction, the cards are received from the customers and an incentive image is displayed on the display areas of the cards when they are returned to the customers. The incentive images can be coupons, discount certificates, or other marketing or promotional offerings, prize notifications, loyalty rewards, etc. The cards can be credit cards, including gift cards, debit cards, ATM cards, shoppers' cards, merchants' cards, phone cards, casino cards, or any other similar cards. A transaction card that displays updated value balances on the card and a system for performing the value updates is also disclosed.
US09245280B2 Predictive video advertising effectiveness analysis
Effectiveness of video content is predicted using an automated or semi-automated analysis process operating on a computer. Video content is analyzed using image and audio data processing to assign a collection of attributes to a video ad. The collection of attributes is correlated to a historical effectiveness (e.g., click-thru rate) of past video ads in the same or similar attribute space to obtain predicted ad effectiveness. Differences between the collection of attributes and historical attribute spaces of greater effectiveness may also be determined and reported in the form of suggestions for improving the effectiveness of the ad.
US09245276B2 Time-in-store estimation using facial recognition
A method of monitoring the amount of time spent in a specified area by an individual comprises employing a first camera to automatically create one or more entrance images, each entrance image containing a face of an entering individual that passes a first location, and storing each entrance image in a database along with a corresponding entrance time that the entering individual passed the entrance location. A second camera is also employed to automatically create an exit image of a face of an exiting individual that passes a second location, and the exit image is recorded along with the corresponding exit time that the exiting individual passed the exit location. The exit image is then compared to the entrance images in the database to identify a matching entrance image containing the same face as the exit image. A stay time is then determined for the exiting individual by determining the difference between the entrance time corresponding to the matching entrance image and the exit time.
US09245268B1 Dynamic card validation
A card validation system receives a request to validate a card and receives one or more received cell values corresponding to one or more cell identifiers of a card validation matrix. The system determines one or more stored cell values corresponding to the one or more cell identifiers of the card validation matrix. The system compares the received cell values to the one or more stored cell values. Based at least in part upon the comparison, the system determines whether the card is validated.
US09245264B2 Reading apparatus
In accordance with one embodiment, a reading apparatus, arranged at a position between an operator and a customer who stand in a face to face manner, comprises a main body having an opening on a surface thereof facing the operator, an image capturing section for operator, housed in the main body, configured to photograph a commodity through the opening of the main body to capture an image of the commodity, and a reading section for customer, arranged on the main body, configured to communicate with an object, which is held by the customer and is capable of realizing near field communication, to read specified additional information stored in the object.
US09245259B2 Presenting E-mail on a touch device
Messages are presented so as to make effective use of the display area to convey information to the user. For example, message content of primary interest to the user (e.g., new content) can be distinguished from secondary content (e.g., content quoted from a previous message), and the message can be initially displayed with the secondary content hidden using an expandable visual indicator that the user can expand to reveal the secondary content. Different elements within a message, such as textual content and graphical content elements, can be scaled independently using magnification factors optimized for each element.
US09245257B2 System and method for generating a user profile based on skill information
Disclosed are systems, apparatus, and methods for generating a user profile interface based on skill information associated with a user. Skill information associated with the user may be received. The skill information may include data values that identify at least one skill associated with the user, and that further identify a skill level associated with the at least one skill. A plurality of user interface components may be generated based on the received skill information. The plurality of user interface components may be configured to display a graphical representation generated based on at least some of the skill information. An input may be received. The input may identify a configuration of the plurality of user interface components and may further identify a representation of the skill information within the plurality of user interface components. The plurality of user interface components may be rendered and displayed on a display device.
US09245250B2 Systems and methods for identifying and delivering tailored content based upon a service dialog
The present disclosure identifies and/or delivers tailored content based upon a service dialog. For example, the systems may receive a request for tailored content, facilitate a service dialog to obtain information related to the request, and communicate a plurality of tailored content based upon the information related to the request. Further, the systems may identify tailored content based upon a consumer profile, communicate the tailored content to a web client, and/or receive a selection of the tailored content. Further still, the systems may modify a magazine (e.g., content that is presented electronically) based upon tailored content.
US09245248B2 Data metric resolution prediction system and method
In one embodiment, a method includes receiving an identity of a metric of interest and a future time point. The method further includes retrieving a prediction configuration previously associated with the metric of interest. The prediction configuration comprising a period combination. The period combination comprises a plurality of time periods, each time period comprises one or more segments, and each segment of the one or more segments comprises adapted historical values of the metric of interest incrementally inserted therein. The method also includes, for each time period of the plurality of time periods, identifying, for the future time point, a corresponding segment of the one or more segments, accessing a set of adapted historical values from the corresponding segment, and computing an intermediate predicted value from the set of adapted historical values. Moreover, the method includes calculating a predicted value for the metric of interest based on the computing.
US09245247B2 Queue analysis
A method and system for analyzing a queue comprising: obtaining a first image acquired at a first time of a first position within a queue; obtaining a second image acquired at a second time of a second position within the queue; detecting a queue member within the first image; detecting a queue member with the second image; determining that the queue member detected within the second image is the same as the queue member detected within the first image; and determining a trajectory of the queue member within the queue based on a difference between the first time and the second time.
US09245244B2 System and method for enabling product development
A comprehensive platform for developing digital products. A standardized process is applied to a product development effort and an online portal provides tools to aid the product development, assessment, funding and commercializing products. Project management, workflow and data security functionality enable consistent, efficient and secure interactions between users. Business rules, workflows, valuation models and rating methods may be user defined or based upon marketplace, industry or technology standards.
US09245238B2 Dynamic grouping of email recipients
A method, system, and computer usable program product for dynamic grouping of email recipients are provided in the illustrative embodiments. A first recipient and a second recipient of a first email are identified and an association is formed between them. A selection of the first recipient is detected in a second email. Using the association, the second recipient is suggested as a recipient of the second email. The first email may be a previously sent email, and the second email may be an email being composed. A characteristic of the first email is identified and the characteristic may be used as a basis for the association in forming the association. The characteristic may be a phrase in, a type of content in, an attachment in, or a periodicity of the first email. Strength of the association may be modified based on the third email.
US09245235B2 Integrated approach to model time series dynamics in complex physical systems
A system and method for analysis of complex systems which includes determining model parameters based on time series data, further including profiling a plurality of types of data properties to discover complex data properties and dependencies; classifying the data dependencies into predetermined categories for analysis; and generating a plurality of models based on the discovered properties and dependencies. The system and method may analyze, using a processor, the generated models based on a fitness score determined for each model to generate a status report for each model; integrate the status reports for each model to determine an anomaly score for the generated models; and generate an alarm when the anomaly score exceeds a predefined threshold.
US09245233B2 Automatic detection of anomalies in graphs
A method, apparatus and product for automatic detection of anomalies in graphs. The method comprising obtaining training data, the training data comprising a plurality of graphs, each defined by nodes and edges connecting between the nodes, at least some of the nodes are labeled; determining a statistical model of a graph in accordance with the training data, the statistical model takes into account at least one structured and labeled feature of the graph, wherein the structured and labeled feature of the graph is defined based on a connection between a plurality of nodes and based on at least a portion of the labels of the plurality of nodes; obtaining an examined graph; and determining a score of the examined graph indicative of a similarity between the examined graph and the training data, wherein the score is based on a value of the structured and labeled feature in the examined graph.
US09245231B2 Inferring user preferences from an internet based social interactive construct
In embodiments of the present invention improved capabilities are described for a computer program product embodied in a computer readable medium that, when executing on one or more computers, helps determine an unknown user's preferences through the use of internet based social interactive graphical representations on a computer facility by performing the steps of (1) ascertaining preferences of a plurality of users who are part of an inter-net based social interactive construct, wherein the plurality of users become a plurality of known users; (2) determining the internet based social interactive graphical representation for the plurality of known users; and (3) inferring the preferences of an unknown user present in the interact based social interactive graphical representation of the plurality of known users based on the interrelationships between the unknown user and the plurality of known users within the graphical representation.
US09245230B2 Inferring user preferences from an internet based social interactive construct
In embodiments of the present invention improved capabilities are described for a computer program product embodied in a computer readable medium that, when executing on one or more computers, helps determine an unknown user's preferences through the use of internet based social interactive graphical representations on a computer facility by performing the steps of (1) ascertaining preferences of a plurality of users who are part of an internet based social interactive construct, wherein the plurality of users become a plurality of known users; (2) determining the internet based social interactive graphical representation for the plurality of known users; and (3) inferring the preferences of an unknown user present in the internet based social interactive graphical representation of the plurality of known users based on the interrelationships between the unknown user and the plurality of known users within the graphical representation.
US09245226B2 Detecting change points in data streams
A computerized method for detecting a change point in a data stream by testing whether two sets of samples from the data stream were derived from the same distribution, wherein the test uses the unique convergence properties of the two sample tests to probabilistically find the point which maximizes their value, said point closely approximating the change point.
US09245222B2 Synaptic, dendritic, somatic, and axonal plasticity in a network of neural cores using a plastic multi-stage crossbar switching
Embodiments of the invention provide a neural network comprising multiple functional neural core circuits, and a dynamically reconfigurable switch interconnect between the functional neural core circuits. The interconnect comprises multiple connectivity neural core circuits. Each functional neural core circuit comprises a first and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons, and multiple electronic synapses interconnecting the incoming axons to the neurons. Each neuron has a corresponding outgoing electronic axon. In one embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing axons in a functional neural core circuit to incoming axons in the same functional neural core circuit. In another embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing and incoming axons in a functional neural core circuit to incoming and outgoing axons in a different functional neural core circuit, respectively.
US09245215B2 Image processing device for generating and printing image data for one or some of colors at a higher resolution than the other colors
A density corrector performs a density correction processing on a resolution-converted image dataset to obtain a density-corrected image dataset by: determining whether each of first and second pixels in the resolution-converted image dataset is a deletion-target pixel, the first pixels each being a pixel located at a position including a longitudinal edge in a second original image, the second pixels each being a pixel located at a position including a lateral edge in the second original image, patterns of edges in regions in the first and second original images corresponding to the deletion-target pixel being the same; correcting a density of the deletion-target pixel to “0”; and correcting a density of respective pixels other than the deletion-target pixel among the first and second pixels to a value equal to or larger than an original density of the respective pixels.
US09245214B2 Image processing compression with a defined pixel window in a linear array
A method is described that includes defining a window of one or more consecutive pixel values in a linear array of pixel values of an image. The defining includes adding a pixel value in the linear array to the window so long as the pixel value does not deviate from the pixel values that exist within the window to a degree that causes a threshold value to be exceeded, and, wherein the threshold value decreases as the size of the window increases. The method also includes encoding the window of pixel values with a value determined from pixel values within the window and the number of pixel values within the window.
US09245210B2 Ink jet head and ink jet printing apparatus having the same
An ink jet head includes an actuator configured to cause ejection of ink, and a driver. The driver is configured to receive serial data including a first command, a second command subsequent thereto, and print data for printing or setting data for setting of the ink jet head that is subsequent to the second command, detect the first command in the serial data, decode the second command, and control the actuator based on the decoded second command.
US09245208B2 Patient modeling from multispectral input image volumes
A computer-implemented method is provided for generating patient models from multiple imaging contrast sources which may be, for example from magnetic resonance imaging without computed tomography. The method includes: acquiring multiple sets of image data representing a volume of a patient using magnetic resonance imaging, wherein each set of image data is acquired in a different manner so as to create contrast amongst tissue types of the patient; classifying tissue in each voxel in the volume using the multiple sets of image data as input to a classification algorithm; and generating a patient model for the volume from probability distributions of the classes of tissue as derived from the classification algorithm.
US09245205B1 Supervised mid-level features for word image representation
Disclosed is a method and system to learning mid-level features for text images that leverages character bounding box annotations. According to an exemplary embodiment, the disclosed method and system includes extracting semantic local descriptors by aggregating local statistics of small patches and correlating them with character bounding box annotations.
US09245197B2 Image processing apparatus, image processing method, and computer-readable recording medium
An image processing apparatus is disclosed, including a modification part, a model creation part, and a division part. The modification part instructs modification of a portion of a foreground area or a background area which is erroneously divided as a result of dividing predetermined image data into the foreground area being an extraction target and the background area being an out-of-extraction target. The model creation part creates a foreground model of the foreground area and a background model of the background area which are modified, based on first pixel values of a predetermined line segment where the modification is instructed and second pixel values of the foreground area and the background area which are divided. The division part divides the image data into the foreground area and the background area by using the foreground model and the background model which are created by the model creation part.
US09245196B2 Method and system for tracking people in indoor environments using a visible light camera and a low-frame-rate infrared sensor
A method and system tracks objects in an environment by acquiring a first sequence of images of the environment with a visible-light camera having a first frame rate and a second sequence of images with a thermal infrared sensor having a second frame rate. The second frame rate is substantially lower than the first frame rate. The objects are tracked in the first sequence of images to obtain tracks. Warm regions in the second sequence of images are detected to obtain detections. The tracks and the detections are aligned spatially and temporally, and verified to determine whether the tracks and detections coincide after the aligning.
US09245195B2 Apparatus, method and program for image search
One or more representative images extracted from an image group comprising a plurality of images is/are displayed. A part or all of the representative image or images, such as a main subject region or a background region including a search target, is/are selected from the representative image or images, and used for setting search conditions. The image group is searched for an image or images agreeing with the search conditions having been set.
US09245193B2 Dynamic selection of surfaces in real world for projection of information thereon
One or more devices capture a scene of real world, and process one or more image(s) which include distances to points on surfaces in the real world. The distances are used to automatically identify a set of surfaces in the real world. Then, the one or more devices check whether a surface in the set is suitable for display of an element of information to be projected into the scene. On finding that a surface is suitable, a transform function is automatically identified, followed by automatic application of the transform function to the element of the information. A transformed element, which results from automatically applying the transform function, is stored in a frame buffer coupled to a projector, at a specific position in the frame buffer identified during the check for suitability. When no surface is suitable, user input is obtained, followed by projection of information as per user input.
US09245189B2 Object appearance frequency estimating apparatus
An estimation apparatus of an object appearance frequency is provided. The apparatus estimates an appearance frequency of objects, such as pedestrians, in a predetermined estimation area. The apparatus calculates a matrix FPFP by searching an appearance frequency data in the past. In detail, an estimated result that is an output of an estimating module is expressed as a vector. Objects to be estimated are classified into a total of 12 kinds, such as a “man, woman, child, bike, unknown, dog” and a “right, left”. Feature vector of appearance frequency of pedestrians, i.e., objective variables of estimation, is expressed by 12th dimension vector space. Moreover, status information is used as explaining variables, which explain the feature vectors when a feature vector occurs. The regression relationship of the feature vector with respect to the status information vector expressed in 28th dimension is solved by the linear least squares method.
US09245187B1 System and method for robust motion detection
Method and system for detecting objects of interest in a camera monitored area are disclosed. Statistical analysis of block feature data, particularly Sobel edge and spatial high frequency responses is used to model the background of the scene and to segregate foreground objects from the background. This technique provides a robust motion detection scheme prone to catching genuine motions and immune against false alarms.
US09245186B2 Semantic parsing of objects in video
Methods, systems, and computer program products for parsing objects in a video are provided herein. A method includes producing a plurality of versions of an image of an object derived from a video input, wherein each version has a different resolution of said image of said object; computing an appearance score at each of a plurality of regions on the lowest resolution version of said plurality of versions of said image for at least one attribute for said object, wherein said appearance score denotes a probability of the at least one attribute appearing in the region; determining a configuration of the at least one attribute in the lowest resolution version based on at least the appearance score in each of the plurality of regions in the lowest resolution version; and displaying said configuration.
US09245177B2 Limiting avatar gesture display
Technology determines whether a gesture of an avatar depicts one of a set of prohibited gestures. An example of a prohibited gesture is a lewd gesture. If the gesture is determined to be a prohibited gesture, the image data for display of the gesture is altered. Some examples of alteration are substitution of image data for the prohibited gesture, or performing a filtering technique to the image data depicting the gesture to visually obscure the prohibited gesture.
US09245176B2 Content retargeting using facial layers
Techniques are disclosed for retargeting facial expressions. Input is received that represents a facial expression of a first character. Facial layers are generated based on the received input. The facial layers include one or more parameters extracted from the received input. A facial expression for a second character and corresponding to the facial expression of the first character is generated, based on the facial layers and without defining any spatial correspondence between the first character and the second character.
US09245173B2 Apparatus and method for identifying fake face
An apparatus for identifying a fake face is provided. A first eye image acquirer acquires a first eye image by taking a picture of a subject while radiating a first ray having a first wavelength. A second eye image acquirer acquires a second eye image by taking a picture of the subject while radiating a second ray having a second wavelength that is shorter than the first wavelength. A controller extracts a first area and a second area having brighter lightness than the first area from each of the first and second eye images, calculates a lightness of the first area and a lightness of the second area in the first eye image, and a lightness of the first area and a lightness of the second area in the second eye image, and determines whether the subject uses a fake face based on the calculated lightness.
US09245172B2 Authentication apparatus, authentication method, and non-transitory computer readable medium
An authentication apparatus includes a feature acquiring unit that acquires a feature of an authentication target; an extracting unit that extracts one or more registered persons having features similar to the acquired feature; a determining unit that determines whether any registered person having a feature similar to the feature of at least one extracted registered person exits in the registered persons; a first identifying unit that, if the determination is negative, identifies the registered person having the feature having a highest degree of similarity with the acquired feature as the authentication target; a specific information accepting unit that accepts information specific to the authentication target; and a second identifying unit that, if the determination is affirmative and the accepted specific information coincides with the information specific to any extracted registered person, identifies the registered person having the coinciding specific information as the authentication target.
US09245171B2 Gaze point detection device and gaze point detection method
A gaze point detection device includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute, capturing an image of at least part of a scene around a vehicle; detecting a direction of a line of sight of a person in the vehicle; determining an intersection between a plane and a line of sight of the person in the vehicle, the plane being along a running direction of the vehicle and apart from the vehicle by a given distance; and presenting a resultant projected point on the image as a gaze point.
US09245169B2 Apparatus, system, and method for image normalization using a Gaussian residual of fit selection criteria
An apparatus and method for image normalization using a Gaussian residual of fit selection criteria. The method may include acquiring a two-dimensional image of a plurality of particles, where the plurality of particles comprises a plurality of calibration particles, and identifying a calibration particle by correlating a portion of the image corresponding to the calibration particle to a mathematical model (e.g. Gaussian fit). The measured intensity of the calibration particle may then be used to normalize the intensity of the image.
US09245165B2 Auxiliary functionality control and fingerprint authentication based on a same user input
A sensor structure (110) for a device includes both a fingerprint sensor (112) and one or more touch sensors (114). As a user input of the user moving his or her finger across the sensor structure is received, an appropriate auxiliary functionality operation as indicated by the pattern of movement is identified and performed. Additionally, during the same user input the fingerprint sensor senses fingerprint data identifying a fingerprint on the user's finger, and an attempt is made to authenticate the user's fingerprint. Thus, as the user provides a user input by moving his or her finger across the sensor structure, both an attempt is made to authenticate the user's fingerprint based on fingerprint data sensed during the user input and the operation requested by the user input is performed.
US09245161B2 Method and system for computed radiography using a radio frequency identification device
A method for obtaining an X-ray image of a subject on a flexible information carrier plate for computed radiography. A memory is affixed to a surface of the plate, wherein the affixed memory stores information about the plate and is in wireless communication with a computer. A first scan date is stored in the affixed memory. Obtaining the X-ray image uses steps of storing at least a job identifier and a scan status for the plate in the affixed memory; acquiring image data from a scan of the plate following exposure to X-rays, acquiring at least the job identifier from the affixed memory, and associating the acquired image data with the acquired job identifier; incrementing a scan count value and updating the scan status in the affixed memory; erasing image content from the plate; and storing the acquired image data in a second, computer-accessible memory according to the acquired job identifier.
US09245159B2 Low power radio frequency communication
A method, system and tag for low power radio frequency communication is described. In one embodiment, the RF tag comprises: an access point comprising: a first antenna; a first radio coupled to the first antenna; a central processing unit coupled to the first radio; a backscatter adapter coupled to the access point via a wired communication interface, the backscatter adapter comprising a backscatter radio and a second antenna coupled to the backscatter radio for use in communicating with an RF tag in the network via backscatter.
US09245151B2 Input to locked computing device
The subject matter of this specification can be embodied in, among other things, a method that includes receiving at a computing device that is in a locked state, one or more user inputs to unlock the device and to execute at least one command that is different from a command for unlocking the device. The method further includes executing in response to the user inputs to unlock the device an unlocking operation by the device to convert the device from a locked state to an unlocked state. The method further includes executing the at least one command in response to receiving the user inputs to execute the at least one command. The at least one command executes so that results of executing the at least one command are first displayed on the device to a user automatically after the device changes from the locked state to the unlocked state.
US09245149B1 System and method for controling privileges of consumers of personal data
Disclosed are systems, methods and computer program products for controlling privileges of consumers of personal data. An example method includes: formulating user requirements to personal data control quality; determining weighting factors for corresponding functions of application programming interfaces (APIs) for personal data control of a centralized personal data control system based on the formulated user requirements to personal data control quality; determining correspondence between the functions of APIs for personal data control of the centralized personal data control system and functions of APIs for personal data control of the consumer of personal data; calculating a personal data control rating of the consumer of personal data based on the determined correspondence and the determined weighting factors; and determining the privileges of the consumer of personal data based on the personal data control rating of the consumer of personal data.
关于PatentHub
关于我们 加入我们 联系我们 帮助中心
PatentHub产品
专利百科 商标查询 专利交易 大学排行榜 行业专题库
API接口 排行榜 专利资讯 最新中国发明专利 最新美国发明专利
PatentHub联系方式
QQ：3307693423 QQ：3236401158