| Document | Document Title |
|---|---|
| US09160052B2 |
Lange coupler and fabrication method
A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer. |
| US09160051B2 |
Radio frequency combiner/divider
An RF combiner/divider includes an input switch, an output switch, an impedance-matching transmission network for connecting the input switch to the output switch, and a control circuit connected to the input switch and the impedance-matching transmission network. The RF combiner/divider is used for automatic impedance transformation for impedance-matching. The RF combiner/divider is suitable for use in an RF system with a changeable number of combiner/divider branches. |
| US09160050B2 |
Planar balun transformer device
An electric transformer device (balun) is formed on a support plate having a first base face and an opposite second base face. The balun includes a first port (40) connectable to an electrical line for a differential signal and a second port connectable to an electrical line for a single-ended signal. A first printed conductive track is associated to the first base face of the support plate for connecting the first port to the second port. A printed conductive path is associated to the second base face of the support plate for connecting the first port to the second port. The printed conductive path is formed of a symmetric second and third printed conductive tracks. |
| US09160048B2 |
Electronic device with terminal circuits
A semiconductor device includes: a terminal configured to input a signal from a signal source; a receiver configured to receive the signal from the signal source through the terminal; and a terminal circuit configured to be coupled between the terminal and an input end of the receiver, and to suppress reflected wave caused by signal reflection at the receiver, wherein impedance of a wire line connecting the terminal and the input end of the receiver, and direct-current impedance of a resistance component included in the terminal circuit are set lower than impedance of an external wire line connected to the terminal. |
| US09160042B2 |
Battery pack for electric vehicle and battery pack mounting structure
In a battery pack for an electric vehicle, since a cooling air suction port (48a) is provided in the vicinity of an end part, on the downstream side in a direction of flow of cooling air, of a battery case (24) so as to oppose the direction of flow, cooling air is in full contact with the battery case (24) before flowing into the cooling air suction port (48a), and dust or water contained in cooling air can be made to adhere to the battery case (24) and removed, thus preventing dust or water from entering the interior of the battery case (24). In particular, since the battery case (24) includes a projecting portion (39a) that rises on the upstream side in the direction of flow of the cooling air suction port (48a) and disturbs the flow of cooling air, and an upper end of the projecting portion (39a) is at a position higher than that of the cooling air suction port (48a), it is possible to reliably put cooling air in contact with the projecting portion (39a) of the battery case (24), thus enhancing the effect in removing dust or water. |
| US09160040B2 |
Cell delta-temperature optimized battery module configuration
A battery module includes a plurality of battery cells. Each battery cell includes an anode having an anode active area, a cathode having a cathode active area, and an ion-conducting separator interposed between the anode active area and the cathode active area. A first subset of the battery cells are arranged in parallel wired battery cell pairs. Each parallel wired battery cell pair of the first subset has two adjacent battery cells with a cooling fin interposed between the two adjacent battery cells. |
| US09160039B2 |
Battery cell of excellent heat dissipation property and middle or large-sized battery module employed with the same
Disclosed herein is a battery cell constructed in a structure in which an electrode assembly of a cathode/separator/anode structure is mounted in a battery case formed of a laminate sheet including a resin layer and a metal layer while the electrode assembly is connected to electrode terminals extruding out of the battery case, wherein the battery cell is constructed in a structure to accelerate heat dissipation by the heat conduction through at least some of a sealing part of the battery case where the electrode terminals are not located. |
| US09160037B2 |
Apparatus and method for estimating available time of battery
Disclosed are an apparatus and method for estimating an available time of a battery relatively accurately in consideration of a driving pattern of a user. The apparatus for estimating an available time of a battery includes a current measuring unit for measuring an output current of the battery, a SOC estimating unit for estimating SOC (State Of Charge) of the battery, and a controller for estimating an available time of the battery by using a measured current value obtained by the current measuring unit, an estimated SOC value obtained by the SOC estimating unit and an entire capacity of the battery. |
| US09160033B2 |
Non-aqueous electrolyte composition and non-aqueous electrolyte secondary battery
The present invention provides a non-aqueous electrolyte composition with excellent high-temperature stability and a non-aqueous electrolyte secondary battery using the same. The non-aqueous electrolyte composition includes a supporting electrolyte, an organic solvent, and at least one kind of chemical compound (a) selected from the group consisting of a chemical compound (a1) indicated by the following general formula (1) and a chemical compound (a2) indicated by the following general formula (2). |
| US09160032B2 |
Electrochemical cells and use thereof
Electrochemical cells comprise (A) at least one cathode comprising at least one lithiated Mn-containing compound having an Mn content of from 60 to 80 mol %, based on transition metal in cathode (A), (B) at least one anode comprising carbon in electrically conductive form, (C) at least one electrolyte comprising (a) at least one aprotic organic solvent, (b) at least one lithium salt, and (c) at least one organic compound having at least one Si—N single bond per molecule. |
| US09160028B2 |
Device and method for stacking units for secondary battery
Provided is a unit stacking device for a secondary battery, which stacks one or more first radical units having a first size and one or more second radical units having a second size greater than the first size and includes a stack jig, which includes a first inner space having a size corresponding to the first size and a second inner space disposed above the first inner space and communicating with the first inner space and having a size corresponding to the second size. The first radical units are stacked in the first inner space through the second inner space, and then, the second radical units are stacked in the second inner space. |
| US09160023B2 |
Reinforced matrix impregnated with electrolytes for molten carbonate fuel cell and fabrication method thereof
The present invention relates to an electrolyte-impregnated, reinforced matrix for molten carbonate fuel cells and a manufacturing method thereof. According to the invention, the electrolyte-impregnated matrix, which comprises both the electrolyte and the reinforcing particles including a metal and an oxide, is manufactured by adding the electrolyte, as required per unit cell of a fuel cell, and the reinforcing particles including the metal and the oxide, to a slurry during the matrix preparation step, and subjecting the resulting slurry to a tape casting process. By doing so, the matrix stacking operation is facilitated, and the matrix manufacturing process is simplified. In addition, cracking caused by the difference in thermal expansion coefficient between an electrolyte sheet and the matrix can be suppressed, and thermal shock occurring during operation of the fuel cell stack can be reduced, thus improving the performance and lifetime of the fuel cell. |
| US09160019B2 |
Membrane electrode assembly and method for making the same
A method for making membrane electrode assembly includes providing a proton exchange membrane and two electrodes. An array of carbon nanotubes is formed on a substrate. The array of carbon nanotubes is pressed by a pressing device to form a carbon nanotube film. A catalyst layer is formed on the carbon nanotube film to obtain an electrode. Two electrodes are disposed on two opposite surfaces of a proton exchange membrane, to obtain the membrane electrode assembly. |
| US09160018B2 |
Fuel cell system, control method for the fuel cell system, and electric vehicle equipped with the fuel cell system
A fuel cell system includes: a secondary cell; a voltage converter provided between the secondary cell and a load; a fuel cell; an FC relay that turns on and off electrical connection between the fuel cell and the shared electrical path; an electrical leakage detector that detects electrical leakage in an electrical system; and a control portion that performs determination regarding electrical leakage. The control portion has: start means for starting the fuel cell by raising voltage of the fuel cell from a starting voltage to an operation voltage that is lower than an open-circuit voltage; and electrical leakage determination means for performing the determination regarding electrical leakage after a predetermined time elapses, when the FC relay is closed while a voltage difference between the voltage of the fuel cell and voltage supplied from the voltage converter to the load is greater than a predetermined threshold value. |
| US09160016B2 |
Fuel cell
A fuel cell includes a membrane-electrode assembly and a separator. The membrane-electrode assembly has an electrolyte and a pair of electrodes that are disposed on respective sides of the electrolyte. The membrane-electrode assembly and the separator are stacked in a stacking direction. A reaction surface of the membrane-electrode assembly is in a vertical direction along a direction of gravity and has a shape having a longer dimension in a horizontal direction. The fuel cell is provided with a reactant gas passage to allow a reactant gas to flow along a longitudinal direction of the reaction surface. The reactant gas is an oxidant gas or a fuel gas. A drain channel to allow product water from the reactant gas passage to be drained away is disposed between the membrane-electrode assembly and the separator and under the reaction surface in the direction of gravity. |
| US09160011B2 |
Fuel cell separator sealing material and fuel cell separator
For use in a fuel cell separator comprising a separator substrate, a primer layer, and an elastomeric seal, a sealing material comprises a primer composition containing Si—H groups of which the primer layer is formed, and a liquid addition-curable silicone rubber composition containing alkenyl groups and Si—H groups of which the elastomeric seal is formed. A molar ratio of the total amount of Si—H groups to the total amount of alkenyl groups per unit weight of the primer composition and the silicone rubber composition is in the range: 5.0 |
| US09160004B2 |
Lithium ion secondary battery
In a lithium ion secondary battery including a positive electrode, a separator, and a negative electrode opposed to the positive electrode with an intervention of the separator, the negative electrode includes a negative electrode active material including a silicon compound, and a negative electrode binder including a particular polyimide, and lithium is occluded in both the negative electrode active material and the negative electrode binder even during discharge. |
| US09160001B2 |
Lithium-ion battery materials with improved properties
A cobalt-containing phosphate material can comprise lithium (Li) (or, alternatively or additionally other alkali metal(s)), cobalt (Co), phosphate (PO4), and at least two additional metals other than Li and Co (e.g., as dopants and/or metal oxides), and can have a molar ratio of Co to a total amount of Co and the additional metals (e.g., as dopants and/or metal oxides) of at least 0.2, at least 0.3, at least 0.5, at least 0.7, or at least about 0.75. The cobalt-containing phosphate material can have a molar ratio of Co to a total amount of Co and the additional metals (e.g., as dopants and/or metal oxides) ranging from 0.2 to 0.98, from 0.3 to 0.98, from 0.3 to 0.94, from 0.5 to 0.98, from 0.5 to 0.94, or alternatively from 0.5 to 0.9, from 0.7 to 0.9, or from 0.75 to 0.85. |
| US09159999B2 |
Complexometric precursor formulation methodology for industrial production of fine and ultrafine powders and nanopowders for lithium metal oxides for battery applications
A compound MjXp which is particularly suitable for use in a battery prepared by the complexometric precursor formulation methodology wherein: Mj is at least one positive ion selected from the group consisting of alkali metals, alkaline earth metals and transition metals and j is an integer representing the moles of said positive ion per moles of said MjXp; and Xp, a negative anion or polyanion from Groups IIIA, IV A, VA, VIA and VIIA and may be one or more anion or polyanion and p is an integer representing the moles of said negative ion per moles of said MjXp. |
| US09159996B2 |
Synthesizing method for lithium titanium oxide nanoparticle using supercritical fluids
A method for synthesizing lithium titanium oxide-based anode active material nanoparticles, and more particularly, a method for synthesizing lithium titanium oxide-based anode active material nanoparticles using a supercritical fluid condition is disclosed herein. The method may include (a) preparing a lithium precursor solution and a titanium precursor solution, (b) forming lithium titanium oxide-based anode active material nanoparticles by introducing the lithium precursor solution and titanium precursor solution into an reactor at a supercritical fluid condition, and (c) cleaning and drying the nanoparticles, and may further include (d) calcinating the nanoparticles at 500-1000° C. for 10 minutes to 24 hours after the step (c). |
| US09159993B2 |
Alkaline battery
In an alkaline battery, a positive electrode 2 containing manganese dioxide, a negative electrode 3, and a separator 4 interposed therebetween are housed in a closed-end cylindrical battery case 1 whose opening 1b is sealed with a gasket. The positive electrode contains graphite in such a manner that a ratio of graphite to the positive electrode is in the range of 2.5-4.3 mass %. A half-width of a 110 plane of the manganese dioxide measured by a powder X-ray diffraction analysis is in the range of 2.00-2.40 degrees. |
| US09159987B2 |
Method for manufacturing battery electrode including depositing a liquid phase bilayer
The present invention provides a method for manufacturing a battery electrode. This method comprises the steps of applying a binder solution 50 that contains a binder 54 and is adjusted so that the contact angle of the binder solution 50 with the surface of a current collector 10 is 73° or less, to form a binder solution layer 56; applying a mixed material paste 40 containing an active material 22 on top of the binder solution layer 56, to deposit both the binder solution layer 56 and a mixed material paste layer 46 on the current collector 10; and obtaining an electrode 30 in which a mixed material layer 20 is formed on the current collector 10, by drying the deposited binder solution layer 56 and mixed material paste layer 46 together. |
| US09159985B2 |
Circuit breaker and battery pack including the same
A breaker includes a fixed metal plate, a moving metal plate, a bimetal, and a heater. The fixed plate includes a fixed contact in a space of an exterior case having an electrically-insulating case and an exterior metal plate. The exterior plate and the fixed plate are arranged opposed to each other, and fixed to the electrically-insulating case. The bimetal has a convex shape, and is arranged between the heater and the moving plate. The electrically-insulating case includes first and second outer walls and protruding from the both ends of the case. A central part of the fixed plate is fixed to the first outer wall, and a part of moving plate is fixed to the second outer wall. The exterior plate closes the opening of the space. |
| US09159984B2 |
Rechargeable battery
A rechargeable battery including an electrode assembly; a case containing the electrode assembly; a cap plate covering an opening of the case; and a current collecting member including a current collecting portion coupled to the electrode assembly; a terminal coupling portion extending from the current collecting portion at a corner portion of the current collecting member, the corner portion extending in a first direction along a width of the current collecting member; and a fuse portion, the current collecting member having a fuse hole formed therein adjacent the fuse portion, a centerline of the fuse hole extending through the fuse portion in a direction crossing the first direction. |
| US09159983B2 |
Battery, vehicle mounting the battery, and device mounting the battery
A battery includes a current breaking mechanism 20 provided in a battery and configured such that an external terminal 21 connecting a terminal rivet 31 connected to a power generating element 16 to an electrode terminal is provided with thick portions 48 and 49 and a breakable portion 45 so that the thick portions 48 and 49 are continuous through the breakable portion 45 only. The battery further includes: the terminal rivet 31 placed passing through a closing plate 12 forming a part of a battery case 11, a part of the terminal rivet 31 located outside the battery case 11 being placed on the thick portion 48 of the external terminal 21 in close contact relation, the terminal rivet 31 having a through hole 32; and a sealing cap 25 covering an exit of the through hole 32 on the outside of the battery case 11 and being joined to the external terminal 21 over the entire circumference of the through hole 32 or joined to both the external terminal 21 and the terminal rivet 31 across them. When the internal pressure of the battery case 11 rises, at least part of the sealing cap 25 is moved away from the battery case 11, deforming a part of the external terminal 21, thereby breaking the breakable portion 45. |
| US09159980B2 |
Electrochemical cell
An electrochemical cell is presented. The cell includes a housing formed of a metallic material. A component is disposed within an anode compartment of the cell that contains an alkali metal. The component comprises a sacrificial metal that has an oxidation potential less than the oxidation potential of the housing material. An energy storage device including such an electrochemical cell is also provided. |
| US09159977B2 |
Method for producing electric storage device, spacer and electric storage device
A method for producing an electric storage device having a bus bar and an electric storage element equipped with an external terminal includes the steps of: arranging the electric storage element having the external terminal, positioning a resin member having either one of a receiving portion or a projection relative to the electric storage element, arranging the bus bar having the other one of the receiving portion or the projection on the external terminal, connecting the bus bar to the external terminal, and inserting the projection into the receiving portion in the step of arranging the bus bar. |
| US09159968B2 |
Battery pack case
Disclosed herein are a pack case constructed in a structure in which a plurality of battery cells are mounted in the pack case to electrically connect the battery cells with each other, wherein the pack case includes an upper case and a lower case constructed in a hollow structure in which the upper case and the lower case are coupled with each other while the battery cells are mounted between the upper case and the lower case, each case is integrally provided at the inner part thereof with a plurality of spacers for supporting the battery cells, and each case is provided at the outer part thereof with a plurality of ventilation openings which communicate with the interior of each case, and a battery pack including the pack case. The pack case according to the present invention has effects in that a plurality of battery cells are stably mounted in the pack case in a compact structure through a simple assembly process, heat generated from the battery cells is effectively removed during the charge and discharge of the battery cells, and an additional safety unit, such as a detection member and/or a protection circuit module, is easily mounted to the pack case. |
| US09159967B1 |
Battery storage and dispensing system
A battery storage and dispensing system for efficiently storing and dispensing various sizes of batteries. The battery storage and dispensing system generally includes a housing having a plurality of vertical compartments that each receive a type of battery, a door pivotally connected to the housing to selectively enclose the vertical compartments forming a plurality of lower openings for batteries to be removed from the vertical compartments and a removal device having a magnet that magnetically connects to the metal terminal end of a battery to allow for efficient removal of the lowermost battery from a compartment. |
| US09159963B2 |
Secondary battery having first and second non-coated portions
A stacked-type electrode assembly is disclosed. In one embodiment, the electrode assembly includes at least one first electrode plate including i) a first active material coating portion formed on a first base material and coated with a first active material and ii) a first non-coated portion, wherein the first electrode plate has a first width and a first length greater than the first width, and wherein the first electrode plate has upper and lower portions formed in the direction of the first length. The assembly also includes at least one second electrode plate including i) a second active material coated portion formed on a second base material and coated with a second active material and ii) a second non-coated portion, wherein the second electrode plate has a second width and a second length greater than the second width. |
| US09159962B2 |
Battery, method of manufacturing battery, battery pack, electronic device, electric vehicle, capacitive storage device, and power system
A battery including cladding members in which a metal layer, an external resin layer, an inner resin are laminated; an electrode body which includes a positive electrode and a negative electrode; electrolyte which is accommodated in the cladding member; a positive electrode lead which is electrically connected to the positive electrode; and a negative electrode lead which is electrically connected to the negative electrode, the thickness of the heat sealed portions of both end portions of the positive electrode lead is formed larger than the thickness of the heat sealed portion on a center line in a width direction of the positive electrode lead, and the thickness of the heat sealed portions of both end portions of the negative electrode lead is formed larger than the thickness of the heat sealed portion on a center line in a width direction of the negative electrode lead. |
| US09159960B2 |
Annealing apparatus and annealing method
The present disclosure relates to an annealing apparatus and an annealing method, which are applied to the packaging art of the AMOLED panel, wherein the annealing apparatus comprises an electromagnetic wave generator coupled with a plurality of irradiators and comprises a plate whose surface is provided with the irradiators and which is placed above or below the AMOLED panel for annealing it. The method comprises the following steps: annealing the AMOLED panel by an annealing apparatus which comprises an electromagnetic wave generator and a plate having lots of irradiators; when the irradiators aim at the annealing area, the annealing areas are annealed by the high frequency electromagnetic wave generated by the electromagnetic wave generator and irradiated from the irradiators. The present disclosure can save the time of the annealing process and can improve the process situation. Meanwhile, the present disclosure increases production yield and improves product quality. |
| US09159957B2 |
White organic light emitting device
A white organic light emitting device which has high color temperature characteristics and no change in color coordinates according to luminance change, includes a first electrode and a second electrode opposite to each other on a substrate, a charge generation layer formed between the first electrode and the second electrode, a second stack including a second light emitting layer formed between the charge generation layer and the second electrode, and a first stack including a first light emitting layer formed between the first electrode and the charge generation layer, wherein the first emitting layer has low singlet-triplet exchange energy to change triplet excitons into a singlet state by triplet-triplet annihilation and a dopant concentration of the first light emitting layer is adjusted according to a luminance change curve of the second stack. |
| US09159953B2 |
Organic light-emitting display device and manufacturing method thereof
An organic light-emitting display device includes a first substrate; a display unit on the first substrate; an encapsulation layer covering the display unit; a second substrate on the first substrate, wherein the display unit is interposed therebetween; a sealant between the encapsulation layer and the second substrate and at the outside of the display unit, wherein the sealant bonds the encapsulation layer and the second substrate to seal them; and a getter on the encapsulation layer in a region between the sealant and the display unit. |
| US09159952B2 |
Flexible packaging substrate and fabricating method thereof and packaging method for OLED using the same
Provided herein is a flexible packaging substrate, comprising a first polymer layer; a metal foil layer disposed on the first polymer layer; a second polymer layer disposed on the metal foil layer; and wherein the surface area of the metal foil layer is larger than those of both the first and the second polymer layer. Also provided are a fabricating method for the same and a method for packaging an organic electroluminescent device using the same. The flexible packaging substrate according to the present invention is able to prevent oxygen and moisture from permeating effectively, allowing the service life of the packaged device prolonged. Additionally, the fabrication according to the examples of the present invention was performed through simple processes, and thereby the packaging process was simplified and the packaging performance was improved. |
| US09159948B2 |
Display device including light-emitting element and electronic device
To inhibit surface reflection of a display device. A display device which includes a reflective electrode layer 110; a partition 118 formed to surround the reflective electrode layer; a layer 120 containing a light-emitting organic compound and formed over the partition and the reflective electrode layer; a semi-transmissive electrode layer 122 formed over the layer containing the light-emitting organic compound; and a coloring layer 162 formed over the semi-transmissive electrode layer. The coloring layer overlaps with the reflective electrode layer and the partition. The partition does not overlap with the reflective electrode layer. |
| US09159942B2 |
Light-emitting element, light-emitting device, electronic appliance, and lighting device
A light-emitting element which has low driving voltage and high emission efficiency is provided. The light-emitting element includes, between a pair of electrodes, a hole-transport layer and a light-emitting layer over the hole-transport layer. The light-emitting layer contains a first organic compound having an electron-transport property, a second organic compound having a hole-transport property, and a light-emitting third organic compound converting triplet excitation energy into light emission. A combination of the first organic compound and the second organic compound forms an exciplex. The hole-transport layer is formed using two or more kinds of organic compounds and contains at least the second organic compound. |
| US09159929B2 |
Rigid amines
A monomer for use in manufacturing a conjugated polymer, the monomer having a structure as shown formula (2): Ar1, Ar2 and Ar3 are independently selected from optionally substituted aryl or heteroaryl, X1 and X3 both independently comprise a leaving group capable of participating in polymerization and Z represents a direct bond or an optionally substituted bridging atom. |
| US09159927B2 |
Electroactive materials
A compound having Formula I, Formula II, or Formula III: Ar1 may independently be phenylene, substituted phenylene, naphthylene, or substituted naphthylene. Ar2 is the same or different at each occurrence and is an aryl group. M is the same or different at each occurrence and is a conjugated moiety. T1 and T2 are independently the same or different at each occurrence and are conjugated moieties which are connected in a non-planar configuration; a and e are the same or different at each occurrence and are an integer from 1 to 6; b, c, and d are mole fractions such that b+c+d=1.0, with the proviso that c is not zero, and at least one of b and d is not zero, and when b is zero, M has at least two triarylamine units; and n is an integer greater than 1. |
| US09159924B2 |
Method of preparing carbon thin film, electronics comprising carbon thin film, and electrochemical device comprising carbon thin film
A method of preparing a carbon thin film, and electronics including the carbon thin film. |
| US09159923B2 |
Evaporation donor substrate, method for manufacturing the same, and method for manufacturing light-emitting device
An evaporation donor substrate that makes it possible to evaporate only a desired evaporation material in the case of performing deposition by an evaporation method. Thus, the use efficiency of an evaporation material can be increased resulting in reduction in production cost, and further a film with high uniformity can be deposited. The evaporation donor substrate can be obtained by forming a reflective layer having an opening over a substrate, forming a thermal insulation layer having a light-transmitting property separately over the substrate and the reflective layer, forming a light absorption layer over the thermal insulation layer, and forming a material layer over the light absorption layer. |
| US09159918B2 |
Resistive random access memory
A resistive random access memory includes a first electrode, a second electrode and a first metal oxide composite layer. The second electrode is opposite to the first electrode. The first metal oxide composite layer is disposed between the first electrode and the second electrode. The first metal oxide composite layer has a film layer and a nanorod structure. |
| US09159916B2 |
Resistive random access memory, controlling method and manufacturing method therefor
A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer. |
| US09159913B2 |
Two-terminal reversibly switchable memory device
A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. |
| US09159911B2 |
Memory element and memory device
There are provided a memory element and a memory device in which the state of erasing remains stable by deactivation of a localized site(s) formed inside of a resistance change layer. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer including an n-type dopant or a p-type dopant, and disposed on the first electrode side, and an ion source layer disposed between the resistance change layer and the second electrode. |
| US09159909B2 |
Electrical device having magnetically doped topological insulator quantum well film
An electrical device includes an insulating substrate and a magnetically doped TI quantum well film. The insulating substrate includes a first surface and a second surface. The magnetically doped topological insulator quantum well film is located on the first surface of the insulating substrate. A material of the magnetically doped topological insulator quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3, wherein 0 |
| US09159902B2 |
Resonator
A resonator includes an interdigital transducer electrode, a resonance part, a supporting part, and two beam parts. The interdigital transducer electrode is disposed on a piezoelectric thin film. The resonance part is held on a substrate through an air gap. The supporting part supports the resonance part. The two beam parts connect the resonance part to the supporting part at both ends of the resonance part. The air gap forms a level difference at the supporting part or level differences at the respective two beam parts. |
| US09159898B2 |
Oxide superconductor thin film and superconducting fault current limiter
An oxide superconducting thin film includes a substrate, and an intermediate layer and a superconducting layer provided in this order on the substrate. The intermediate layer has an average thickness of from 10 nm to 20 nm and a surface roughness Ra of 0.5 nm or less. The superconducting layer is formed on a surface of the intermediate layer and includes an oxide superconductor as a main component. A superconducting fault current limiter including the oxide superconducting thin film is also provided. |
| US09159897B2 |
Superconducting structure having linked band-segments which are each overlapped by directly sequential additional band-segments
A superconducting structure (1) has a plurality of linked band-segments (2), with each linked band-segment (2) having a substrate (3) and a superconducting layer deposited onto it (4). The linked band-segments (2) are joined to one another by superconducting layers (4) that face each other. Each linked band-segment (2) is joined to two additional band-segments (7a, 7b) in such a way that the superconducting layers (4) of the two additional band-segments (7a, 7b) and of the linked band-segment (2) face each other. The additional band-segments (7a, 7b) together substantially overlap the total length (L) of the linked band-segment (2). This provides for a superconducting structure, which exhibits high superconductivity and which is very suitable for long distances. |
| US09159894B2 |
Light emitting device and lighting system
A light emitting device includes a conductive support member, a first conductive layer disposed on the conductive support member, a second conductive layer disposed on the first conductive layer, a light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulation layer disposed between the first conductive layer and the second conductive layer. The first conductive layer includes a first expansion part penetrating through the second conductive layer, the second semiconductor layer and the active layer, and includes a second expansion part extending from the first expansion part and being disposed in the first semiconductor layer. The insulation layer is disposed on the lateral surface of the first expansion part, and the lateral surface of the second expansion part contacts with the first semiconductor layer. |
| US09159887B2 |
Light-emitting device, lighting device including the light-emitting device, and method of manufacturing the light-emitting device
A light-emitting device includes a light-emitting element with a pair of element electrodes as a first element electrode and a second element electrode positioned at the lower surface of the light-emitting element; a phosphor plate disposed on the upper surface of the light-emitting element; a first resin covering the lower surface and the peripheral side surface of the light-emitting element with the first element electrode and the second element electrode partly appearing from the first resin; and a second resin provided in the phosphor plate. |
| US09159882B2 |
Semiconductor light-emitting device
A semiconductor light-emitting device includes a first conductive type semiconductor layer having a main surface, a plurality of vertical type light-emitting structures protruding upward from the first conductive type semiconductor layer; a transparent electrode layer covering the plurality of vertical type light-emitting structures; and an insulation-filling layer disposed on the transparent electrode layer. The insulation-filling layer extends parallel to the first conductive type semiconductor layer so as to cover the plurality of vertical type light-emitting structures. A selected one of the first conductive type semiconductor layer and the insulation-filling layer, which is disposed on a light transmission path through which light generated from the plurality of vertical type light-emitting structures is radiated externally, has an uneven outer surface. The uneven outer surface is opposite to an inner surface of the selected one, and the inner surface faces the plurality of vertical type light-emitting structures. |
| US09159881B2 |
Light-emitting device
Disclosed is a light-emitting device comprising: a semiconductor stack layer; a reflective layer on the semiconductor stack layer; a first buffer layer comprising a compound comprising a metallic element and a non-metallic element on the reflective layer; a first electrode; and an electrical insulating layer disposed between the first buffer layer and the first electrode. |
| US09159879B2 |
Semiconductor light emitting element
The light emitting element including: a semiconductor laminate including a first layer, an active layer and a second layer; a first electrode including protrusions that penetrate the second layer and the active layer, the first electrode connected to the first layer via the protrusions; a second electrode connected to the second layer on an lower face of the second layer; and an insulation film between the protrusions and the semiconductor laminate, wherein the protrusions each include a protrusion body covered with the insulation film and a protrusion tip, an upper face and a side face of the protrusion tip being exposed from the insulation film, the first layer includes recesses arranged on an upper face of the first layer so as to sandwich first areas located above the respective the protrusions, and a distance between the recesses sandwiching the first area is larger than a width of the protrusion tip. |
| US09159878B2 |
Semiconductor light emitting device
According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first electrode, and a second electrode. The stacked structural body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting portion. The stacked structural body has a first major surface on a side of the second semiconductor layer. The first electrode is provided on the first semiconductor. The second electrode is provided on the second semiconductor layer. The first electrode includes a first pad portion and a first extending portion that extends from the first pad portion along a first extending direction. The first extending portion includes a first width-increasing portion. A width of the first width-increasing portion along a direction orthogonal to the first extending direction is increased from the first pad portion toward an end of the first extending portion. |
| US09159872B2 |
Semiconductor structure having nanocrystalline core and nanocrystalline shell
Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. |
| US09159869B2 |
LED on silicon substrate using zinc-sulfide as buffer layer
A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices. |
| US09159867B2 |
Array substrate, manufacturing method thereof, and display device
Embodiments of the invention provide an array substrate, a manufacturing method thereof and a display device. The array substrate comprises: a base substrate; a gate line and a gate electrode formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a source electrode, a drain electrode and a pixel electrode formed on the gate insulating layer, wherein the pixel electrode is directly connected to the drain electrode; and an active layer formed on the gate insulating layer, the source electrode and the drain electrode. |
| US09159865B2 |
Method of forming zinc oxide prominence and depression structure and method of manufacturing solar cell using thereof
A method of forming a nanometer-scale prominence and depression structure on a zinc oxide thin film in a wet-etching method, and the method includes the steps of: preparing a substrate; forming a nano structure having a height and a width of a nanometer range; forming the zinc oxide thin film on the substrate on which the nano structure is formed; and wet-etching the zinc oxide thin film, in which in the wet-etching step, zinc oxide having relatively low physical compactness is preferentially etched since the zinc oxide is positioned on the nano structure, and thus the prominence and depression structure is formed around the nano structure by the etching.The method is effective in that a thin film can be uniformly formed on the prominence and depression structure, and an electrolyte or an organic material may uniformly penetrate between the prominence and depression structure. |
| US09159857B2 |
Solar apparatus and mounting system thereof
A solar apparatus includes a solar cell, a frame including a main body and a hollow rib, a pair of first support racks, and a pair of second support racks. The main body surrounds the edge of the solar cell. The hollow rib protrudes over the circumference of the main body. The first support racks are located on a first side of the frame, and each of the first support racks includes a first engaging clamp for coupling to the hollow rib of the frame. The second support racks are located on a second side of the frame facing away from the first side, and each of the second support racks includes a second engaging clamp for coupling to the hollow rib of the frame. |
| US09159851B2 |
Photovoltaic structures having a light scattering interface layer and methods of making the same
Photovoltaic (PV) cell structures having an integral light scattering interface layer configured to diffuse or scatter light prior to entering a semiconductor material and methods of making the same are described. |
| US09159850B2 |
Back contact having selenium blocking layer for photovoltaic devices such as copper—indium-diselenide solar cells
A photovoltaic device (e.g., solar cell) includes: a front substrate (e.g., glass substrate); a semiconductor absorber film; a back contact including a first conductive layer of or including copper (Cu) and a second conductive layer of or including molybdenum (Mo); and a rear substrate (e.g., glass substrate). A selenium blocking layer is provided between at least the Cu inclusive layer and the Mo inclusive layer. |
| US09159848B2 |
Light receiving circuit
According to one embodiment, a light receiving circuit includes a light receiving element, a differential circuit, a fifth transistor, and first and second current sources. The differential circuit includes an amplifier and a bias circuit. The amplifier includes a first transistor, a second transistor, and a first feedback resistor. The amplifier is configured to convert a current from the light receiving element into a voltage. The bias circuit includes a third transistor, a fourth transistor, and a second feedback resistor. A reference voltage is supplied to a control electrode of the fourth transistor. The second and third transistors are included in a current mirror circuit. A fifth transistor has a control electrode connected to a connection point between the first and second transistors. A voltage signal switched to a high level or a low level according to a change of an optical signal is outputted. |
| US09159846B2 |
SiC semiconductor device
A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer. |
| US09159845B2 |
Charge-retaining transistor, array of memory cells, and methods of forming a charge-retaining transistor
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed. |
| US09159843B2 |
Semiconductor device and method of manufacturing the same
To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a. |
| US09159842B1 |
Embedded nonvolatile memory
A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. |
| US09159839B2 |
Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%. |
| US09159832B2 |
Semiconductor fin structures and methods for forming the same
An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope. |
| US09159830B2 |
Field effect transistor
In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized. |
| US09159826B2 |
Vertical tunneling field-effect transistor cell and fabricating the same
A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature. |
| US09159824B2 |
FinFETs with strained well regions
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band. |
| US09159821B2 |
Nitride semiconductor device with limited instantaneous current reduction
A GaN device suppressing the instantaneous current reduction after the shut-off of a high frequency signal is disclosed. The GaN device provides, on a SiC substrate, an AlN layer, a GaN layer, and an AlGaN layer, The SiC substrate has an energy difference greater than 0.67 eV but less than 1.43 eV; the AlN layer has a thickness less than 50 nm; and the GaN layer has a thickness less than 1.5 μm. |
| US09159818B2 |
High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor
A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor. |
| US09159817B2 |
Heterojunction bipolar transistors with an airgap between the extrinsic base and collector
Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface. |
| US09159812B1 |
Fin sidewall removal to enlarge epitaxial source/drain volume
A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface. |
| US09159810B2 |
Doping a non-planar semiconductor device
In doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. A first ion implant is performed in a region of the non-planar semiconductor body. The first ion implant has a first implant energy and a first implant angle. A second ion implant is performed in the same region of the non-planar semiconductor body. The second ion implant has a second implant energy and a second implant angle. The first implant energy may be different from the second implant energy. Additionally, the first implant angle may be different from the second implant angle. |
| US09159805B2 |
TFT array substrate and a method for manufacturing the same graphene based display device
Embodiments of the present invention provide a thin film transistor (TFT) array substrate and a method for manufacturing the same and a display device. The TFT array substrate improves a structure of a TFT array substrate and has a small thickness, and process flow is simplified. The method for manufacturing a thin film transistor (TFT) array substrate comprises: obtaining a gate line and a gate electrode through a first patterning process on a glass substrate; forming a gate insulating layer on the gate line and the gate electrode; forming a graphene layer on the gate insulating layer, and obtaining a semiconductor active layer over the gate electrode by a second patterning process and a hydrogenation treatment; obtaining a data line, a source electrode, a drain electrode and a pixel electrode which are located on the same layer by a third patterning process; and forming a protection layer on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode. |
| US09159803B2 |
Semiconductor device with HCI protection region
A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate. |
| US09159798B2 |
Replacement gate process and device manufactured using the same
A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. |
| US09159794B2 |
Method to form wrap-around contact for finFET
Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs. |
| US09159790B2 |
Device and method for controlling the turn-off of a solid state switch (SGTO)
A circuit for turning OFF a thyristor. The circuit includes at least one first circuit element configured to provide a high reverse turn-OFF voltage to the thyristor gate for a predetermined period of time. Immediately following the predetermined period of time, at least one second circuit element provides a normal reverse turn-OFF voltage to the thyristor gate. The normal reverse turn-OFF voltage is substantially lower than the high reverse turn-OFF voltage. |
| US09159789B2 |
Field effect transitor and semiconductor device using the same
An field effect transistor has a plurality of cells provided on a first straight line. Each cell has a plurality of multi-finger electrodes and is connected to a gate terminal electrode and a drain terminal electrode. The multi-finger electrode has at least two finger gate electrodes, a finger drain electrode, and a finger source electrode. The gate terminal electrode connects the finger gate electrodes of two adjoining cells in common. The drain terminal electrode connects the finger drain electrodes of two adjoining cells in common. The finger gate electrode of one cell of two adjoining cells and the finger gate electrode of another cell of the two adjoining cells cross perpendicularly. The gate terminal electrode and the drain terminal electrode are provided alternately in a region where the finger gate electrodes of the two adjoining cells cross. |
| US09159788B2 |
Nitride semiconductor structure
A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer, in which the buffer layer includes n sub-buffer layers where n≧2, and each of the sub-buffer layers has island structures. The nitride semiconductor layer is disposed on the buffer layer. |
| US09159786B2 |
Dual gate lateral MOSFET
A dual gate lateral MOSFET comprises a drift region over a substrate, an isolation region formed in the drift region and a channel region formed in the drift region. The dual gate lateral MOSFET comprises a drain region formed in the drift region and a source region formed in the channel region, wherein the source region and drain region are formed on opposing sides of the isolation region. The dual gate lateral MOSFET further comprises a first gate and a second gate formed adjacent to the source region, wherein the first gate and the second gate are stacked together and separated by a dielectric layer. |
| US09159785B2 |
Semiconductor device having buried layer and method for forming the same
Semiconductor devices having a buried layer and methods for forming the same are disclosed. In an exemplary method, a hard mask layer can be provided on a semiconductor substrate. The hard mask layer can have a plurality of through-openings. A plurality of deep trenches can be formed in the semiconductor substrate using the hard mask layer as a mask. A bottom of each of the plurality of deep trenches in the semiconductor substrate can be doped to form a plurality of heavily-doped regions. One or more of the plurality of heavily-doped regions can be connected to form the buried layer in the semiconductor substrate. There is thus no need to use an epitaxial process to form active regions. In addition, lateral isolation structures can be simultaneously formed in the semiconductor substrate. |
| US09159784B2 |
Aluminum gallium nitride etch stop layer for gallium nitride based devices
A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure. |
| US09159783B2 |
Semiconductor device and substrate with chalcogen doped region
A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first side to a depth into the semiconductor material and includes chalcogen dopant atoms which provide a base doping concentration for the first region. The second region extends from the first region to the second side and is devoid of base doping. Further, a power semiconductor component is provided. |
| US09159780B2 |
Methods of forming capacitors
A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric. |
| US09159777B2 |
Die arrangements containing an inductor coil and methods of manufacturing a die arrangement containing an inductor coil
In various embodiments, a die arrangement may be provided. The die arrangement may include a die, at least one bond pad, at least one redistribution trace electrically connecting the die with the at least one bond, and at least one inductor enclosing the at least one bond pad and the at least one redistribution trace. |
| US09159775B1 |
Anode connection structure of organic light-emitting diode and manufacturing method thereof
A method is provided for manufacturing an anode connection structure of an organic light-emitting diode. The anode connection structure includes: a thin-film transistor and an anode of an organic light-emitting diode arrange don the thin-film transistor. The thin-film transistor includes a low-temperature poly-silicon layer formed on a substrate, a gate insulation layer formed on the low-temperature poly-silicon layer, a gate formed on the gate insulation layer, a protection layer formed on the gate, and a source/drain formed on the protection layer. The method includes a step of forming a hole in the thin-film transistor to expose the low-temperature poly-silicon layer and a step of forming an electrically conductive layer in the hole for direct engagement with the low-temperature poly-silicon layer to serve as an anode and also the source/drain of the thin-film transistor. The anode of the organic light-emitting diode is thus directly connected to the low-temperature poly-silicon layer. |
| US09159774B2 |
Light-emitting device
A structure of an EL display device which has an increased display area is provided. Further, a structure of an EL display device which has a high definition display is provided. An auxiliary electrode is formed over a first partition and side surfaces of the auxiliary electrode are covered with a second partition. A top surface of the auxiliary electrode is in contact with the conductive film which is one electrode of a light-emitting element and has a light-transmitting property, which enables a large-area display. Further, even the distance between the adjacent light-emitting elements is shortened, the auxiliary electrode can be provided between the adjacent light-emitting elements, which enables a high definition display. |
| US09159773B2 |
Thin film transistor and active matrix organic light emitting diode assembly
A thin film transistor includes a semiconductor layer including a source region, a drain region, a channel region, first lightly doped drain regions adjacent to the channel region and second lightly doped drain regions adjacent to the first lightly doped drain regions; wherein the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions. According to the present application, the leakage current in a switching transistor may be further reduced, thereby avoiding instability and even failure in the operation of the assembly caused by overlarge leakage current. |
| US09159772B2 |
Organic light emitting display
An organic light emitting display is disclosed. In one embodiment, the display includes 1) a substrate, 2) a plurality of pixels formed on the substrate, wherein each of the pixels comprises at least one circuit region including i) a first light emission area, ii) a second light emission area iii) at least one transmission area transmitting external light, and iv) a pixel circuit unit and 3) a first pixel electrode formed in the first light emission area and electrically connected to the pixel circuit unit, wherein the first pixel electrode comprises a first transparent conductive layer and a reflective layer. The display may further include 1) a second pixel electrode formed in the second light emission area and electrically connected to the first pixel electrode, wherein the second pixel electrode comprises a second transparent conductive layer, 2) a first opposite electrode substantially directly below or above the first pixel electrode, 3) a second opposite electrode substantially directly below or above the second pixel electrode and 4) an organic emission layer formed between the first pixel electrode and the first opposite electrode and between the second pixel electrode and the second opposite electrode. |
| US09159770B2 |
3 dimensional semiconductor device and method of manufacturing the same
A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes. |
| US09159768B2 |
Semiconductor device and electronic device including the same
A semiconductor device includes: a vertical electrode provided over a substrate; a variable resistance layer provided at least a sidewall of the vertical electrode; a plurality of horizontal electrodes extending from the sidewall of the vertical electrode and having the variable resistance layer interposed; a transition metal oxide layer provided (i) between the vertical electrode and the variable resistance layer or (ii) between the plurality of horizontal electrodes and the variable resistance layer; and a threshold voltage switching layer provided in the transition metal oxide layer and selectively between the vertical electrode and the any of the plurality of horizontal electrodes. |
| US09159766B2 |
Solid-state image pick-up device and manufacturing method thereof, image-pickup apparatus, semiconductor device and manufacturing method thereof, and semiconductor substrate
A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer. |
| US09159763B2 |
Solid state imaging device having a charge accumulation capacitor section
A solid-state imaging device includes a plurality of pixels, each of which includes a photoelectric converter section formed on a first substrate to generate and accumulate signal charges corresponding to incident light, a charge accumulation capacitor section formed on the first substrate or a second substrate to temporarily hold the signal charges transferred from the photoelectric converter section, and a plurality of MOS transistors formed on the second substrate to transfer the signal charges accumulated in the charge accumulation capacitor section, connection electrodes formed on the first substrate, and connection electrodes formed on the second substrate and electrically connected to the connection electrodes formed on the first substrate. |
| US09159757B2 |
Photodetection device and sensor package
A photodetection device of the present invention includes a semiconductor substrate which is defined such that a first light-receiving portion and a second light-receiving portion are spaced from one another, and an optical filter which is formed on the semiconductor substrate, and includes a first filter which is disposed so as to cover the first light-receiving portion, to selectively allow an optic element in a first wavelength band to transmit through, and a second filter which is disposed so as to cover the second light-receiving portion, to selectively allow an optic element in a second wavelength band different from the first wavelength band, to transmit through, and the optical filter has a filter laminated structure which is defined such that edge portions of the first filter and the second filter overlap one another on a boundary region between the first light-receiving portion and the second light-receiving portion. |
| US09159756B2 |
Solid-state imaging device and manufacturing method of the same
According to one embodiment, there is a solid-state imaging device including an imaging region. In the imaging region, a plurality of pixels are arranged two-dimensionally. A first inclination angle of a light incidence surface of a dichroic filter in a first pixel among the plurality of pixels relative to a normal to a surface of a semiconductor substrate and a second inclination angle of a light incidence surface of a dichroic filter in a second pixel located farther from a center of the imaging region than the first pixel among the plurality of pixels relative to the normal are decided on so as to make, for light incident on the imaging region, a filter property of the dichroic filter in the first pixel and a filter property of the dichroic filter in the second pixel equalized. |
| US09159754B1 |
Image sensor having anti-reflective layer and fabricating method thereof
An image sensor includes a pixel layer in which an active pixel array and an optical black pixel array are formed; a first anti-reflective layer which is formed over the active pixel array, and including a hafnium oxide layer with a high transmittance; and a second anti-reflective layer which is formed over the optical black pixel array, and including a hafnium oxide layer with a low transmittance. |
| US09159752B2 |
Solid-state image pickup device, and camera module
According to one embodiment, a solid-state image pickup device includes a pixel array that includes a two-dimensionally arranged matrix of photoelectric conversion elements corresponding to pixels of a picked-up image. Each of the photoelectric conversion elements includes a first conductive semiconductor region and a second conductive semiconductor region between which an uneven junction plane is formed. |
| US09159751B2 |
Unit pixel of image sensor and image sensor including the same
A unit pixel of an image sensor includes a photoelectric conversion region, a floating diffusion region, and a transfer gate. The photoelectric conversion region is in an active region defined by an isolation region of a semiconductor substrate. The photoelectric conversion region generates electric charges corresponding to incident light. The transfer gate transfers the electric charges to the floating diffusion region, which is located in the active region. The transfer gate includes first and second portions divided relative to a reference line, and at least one of the first or second portions does not overlap the isolation region. |
| US09159750B2 |
Solid-state image sensing device
An image sensor comprises plural sets of a unit pixel outputting a pixel signal based on an electric charge generated through photoelectric conversion and a conversion unit converting the pixel signal into a digital signal. A reference signal source generates reference signals and supplies the generated reference signals to the conversion unit through signal lines. The conversion unit of each set comprises a comparator which compares the level of the reference signal with that of the pixel signal, a count circuit which counts a clock based on the comparison processing, a selection circuit which selects, among the signal lines, a signal line to be selectively connected to the input of the comparator, and a switch which selectively connects the selected signal line to the input of the comparator, and selectively connects a load to an unselected one of the signal lines. |
| US09159745B2 |
Display substrate
A display substrate is provided. The display substrate includes a gate interconnection disposed on an insulating substrate, an oxide semiconductor pattern disposed on the gate interconnection and including an oxide semiconductor, and a data interconnection disposed on the oxide semiconductor pattern to interconnect the gate interconnection. The oxide semiconductor pattern includes a first oxide semiconductor pattern having a first oxide and a first element and a second oxide semiconductor pattern having a second oxide. |
| US09159742B2 |
Non-volatile memory device
A non-volatile memory device includes: a semiconductor pillar stretched perpendicularly to a substrate; a plurality of memory cells stacked along the semiconductor pillar; a bit line coupled with a first end of the semiconductor pillar; a first source line coupled with one of the first end and a second end of the semiconductor pillar; a second source line disposed over the bit line and the first source line; a first switch having a first end coupled with the first source line and a second end coupled with a first voltage supplier, and controlling whether to supply a first voltage to the first source line; and a second switch having a first end coupled with the first source line and a second end coupled with the second source line, and controlling whether or not to supply a second voltage supplied from the second source line to the first source line. |
| US09159740B2 |
Vertical type semiconductor device and fabrication method thereof
A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region. |
| US09159739B2 |
Floating gate ultrahigh density vertical NAND flash memory
A monolithic three dimensional NAND string includes a semiconductor channel, with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, and a plurality of copper containing control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes a blocking dielectric located over the plurality of control gates, a tunnel dielectric in contact with the semiconductor channel, and at least one charge storage region located between the blocking dielectric and the tunnel dielectric. |
| US09159737B2 |
Semiconductor devices including device isolation structures and method of forming the same
Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced. |
| US09159731B2 |
Methods of forming capacitors and semiconductor devices including a rutile titanium dioxide material
Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material. |
| US09159730B2 |
Methods for fabricating a semiconductor device
A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape. |
| US09159726B2 |
Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2. |
| US09159725B2 |
Controlled on and off time scheme for monolithic cascoded power transistors
A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor. |
| US09159722B2 |
Semiconductor device
A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion. |
| US09159717B2 |
Method for permanently bonding wafers
This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate, the second substrate having at least one reaction layer, with the following steps, especially the following sequence: forming a reservoir in a reservoir formation layer on the first contact surface, at least partial filling of the reservoir with a first educt or a first group of educts, the first contact surface making contact with the second contact surface for formation of a prebond connection, thinning of the second substrate and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with the second educt contained in the reaction layer of the second substrate. |
| US09159716B2 |
Stacked chip layout having overlapped active circuit blocks
A stacked chip layout includes a central processing chip has a first area and a first active circuit block over the central processing chip, the first active circuit block has a second area. The stacked chip layout further includes a second active circuit block over the first active circuit block, the second active circuit block has a third area, the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The stacked chip layout further includes a third active circuit block over the second active circuit block, the third active circuit block has a fourth area, the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes a portion of the first active circuit block and the second active circuit block. |
| US09159715B2 |
Miniaturized semiconductor device
To realize further miniaturization of a semiconductor device.The semiconductor device 10 is provided with a switching element (FET 14) provided on a substrate 18, a first electrode (electrode 13) provided on an opposite side of the substrate 18 interposing the switching element, a diode 12 provided on an opposite side of the switching element interposing the first electrode, and a second electrode (electrode 11) provided on an opposite side of the first electrode interposing the diode 12. |
| US09159711B2 |
Integrated circuit systems including vertical inductors
An integrated circuit system is provided that includes a circuit function in and on a surface of a semiconductor substrate. First and second portions of an inductor overlie the surface of the semiconductor substrate and each is coupled to the first circuit function. A third portion of the inductor is positioned on a second substrate. A first through substrate via (TSV) extends through the semiconductor substrate and electrically couples the first portion to the third portion and a second TSV extends through the semiconductor substrate and electrically couples the second portion to the third portion. |
| US09159701B2 |
Method of manufacturing a chip package, chip package, method of manufacturing a chip assembly and chip assembly
A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip. |
| US09159699B2 |
Interconnection structure having a via structure
An interconnection structure is provided having a substrate with at least one electric device formed adjacent to a first side of the substrate and a via hole formed therethrough. The via hole has a first opening adjacent to the first side of the substrate. A via structure is disposed in the via hole without exceeding the first opening. A first pad is disposed on the first side of the substrate and covers the via hole. A second pad is disposed on a second side of the substrate opposite to the first side, wherein the via structure extends into the second pad. The first pad is adjoined to the via structure and electrically connects with the at least one electric device, and the first pad has a protrusion portion extending into the via hole. |
| US09159698B2 |
Method for producing a semiconductor module arrangement
A method for producing a semiconductor module arrangement includes providing a semiconductor module and a printed circuit board. The semiconductor module has a circuit mount populated with a semiconductor chip, an adjustment device in a first relative position with respect to the circuit mount, and a plurality of electrical connections each of which has a free end. Each of the connections is routed through a different passage opening in the adjustment device. The printed circuit board is pushed onto the electrical connections by each of the free ends being inserted into a different contact opening in the printed circuit board. The adjustment device is moved to a second relative position, which is different from the first relative position, with respect to the circuit mount. |
| US09159694B2 |
Die stacking system and method
Die stacking systems and methods are disclosed. In an embodiment, a semiconductor device includes a passivation surface and a conductive die receiving surface located in an opening of the passivation surface. The conductive die receiving surface has a surface area that is larger than a footprint of a second die that is electrically coupled to the conductive die receiving surface. |
| US09159687B2 |
Solder bump for ball grid array
A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1. |
| US09159685B2 |
Conductive structure and method for forming the same
A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer. |
| US09159684B1 |
Wafer-level packaged device having self-assembled resilient leads
A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board. |
| US09159682B2 |
Copper pillar bump and flip chip package using same
Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads. |
| US09159681B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals. |
| US09159680B2 |
Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes preparing a semiconductor substrate having a circuit unit on an upper surface thereof, a metal pad electrically connected to the circuit unit, and a passivation layer that covers the circuit unit and exposes the metal pad, forming a first re-wiring layer that is electrically connected to the metal pad and is formed by a printing method to extend from the metal pad on the passivation layer and forming a second re-wiring layer on the first re-wiring layer using the first re-wiring layer as a seed by using an electro-plating process. |
| US09159679B2 |
Semiconductor package with integrated passives and method for fabricating same
According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device. |
| US09159676B2 |
Semiconductor module
A power module includes: a base plate having a front surface provided with positioning wire bonding portions; an insulating substrate provided with hole portions accommodating the positioning wire bonding portions on a side of a back surface facing the base plate, and fixed to the base plate with being positioned with respect to the base plate by the hole portions accommodating the positioning wire bonding portions; and a semiconductor chip arranged on a side of a front surface of the insulating substrate opposite to the back surface. |
| US09159670B2 |
Ultra fine pitch and spacing interconnects for substrate
Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer. |
| US09159668B2 |
E-fuse circuit and method for programming the same
An electronic-fuse (e-fuse) circuit includes: an e-fuse array; a control switch, coupled to the e-fuse array, for controlling whether a voltage supply is applied to the e-fuse array in programming; and a close loop feedback circuit, coupled to the control switch and the e-fuse array, for clamping at lease one node voltage of the e-fuse array to a reference voltage, and for controlling the control switch to control a blowing current in programming the e-fuse array. |
| US09159666B2 |
Device and method for reducing contact resistance of a metal
A structure for an integrated circuit includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N2 flow at least 20 sccm. |
| US09159660B2 |
Semiconductor package structure and method for making the same
A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate. |
| US09159657B2 |
Semiconductor device
A semiconductor device includes a semiconductor chip which includes a first circuit and a second circuit that are spaced apart from each other, without internal wirings electrically connecting the first circuit and the second circuit to each other, a substrate on which the semiconductor chip is disposed, and substrate wirings that are arranged on the substrate and electrically connect the first circuit and the second circuit to each other. |
| US09159655B2 |
Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements
A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region. |
| US09159654B2 |
Semiconductor device
A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate. |
| US09159647B2 |
Method and apparatus for connecting memory dies to form a memory system
A method, system and apparatus for connecting multiple memory device dies 51-54 to a substrate 56 which requires no trace between dies. A first embodiment assigns the connections of a memory device die 51 to be matched with other memory device dies 52-54 when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses 57,58 between memory device dies 51,52,53 are reduced. The number of vias 57,58,59 is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. 7 arranges the dies in a closed loop. |
| US09159642B2 |
Silicon-based heat dissipation device for heat-generating devices
Embodiments of a silicon-based heat dissipation device and a chip module assembly utilizing the silicon-based heat dissipation device are described. In one aspect, the chip module assembly includes a chip module and a primary heat dissipation module. The chip module includes a board and at least one heat-generating device. The board includes a first primary side and a second primary side opposite the first primary side. The at least one heat-generating device is disposed on the first primary side of the board. The primary heat dissipation module includes at least one silicon-based heat dissipation device disposed on the at least one heat-generating device. |
| US09159638B2 |
Conductive via structure
The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55. |
| US09159634B2 |
Transistor outline housing and method for producing same
A transistor outline housing is provided that has bonding wires on an upper surface. The bonding wires are reduced in length and have connection leads with an excess length at an end opposite the bonding end. |
| US09159632B2 |
Fabrication method of semiconductor apparatus
A method of fabricating a semiconductor apparatus includes forming an insulating layer on a semiconductor substrate, forming a source post in the insulating layer, and forming a semiconductor layer over the source post and the insulating layer. |
| US09159631B2 |
Method and system for template assisted wafer bonding using pedestals
A method of fabricating a composite semiconductor structure includes providing a first substrate comprising a first material and having a first surface and forming a plurality of pedestals extending to a predetermined height in a direction normal to the first surface. The method also includes attaching a plurality of elements comprising a second material to each of the plurality of pedestals, providing a second substrate having one or more structures disposed thereon, and aligning the first substrate and the second substrate. The method further includes joining the first substrate and the second substrate to form the composite substrate structure and removing at least a portion of the first substrate from the composite substrate structure. |
| US09159628B2 |
Combination-type transistor and method for manufacturing same
Disclosed is a combination-type transistor including a first MOSFET that includes a gate, a first source formed on one side of the gate, and a first drain formed on the other side of the gate; a second MOSFET that includes the gate, a second drain formed on the one side of the gate, and a second source formed on the other side of the gate; a first BJT that is formed such that the first source of the first MOSFET is used as an emitter, the second drain of the second MOSFET is used as a collector, and the substrate is used as a base; and a second BJT that is formed such that the second source of the second MOSFET is used as an emitter, the first drain of the first MOSFET is used as a collector, and the substrate is used as a base. |
| US09159626B2 |
FinFET and fabricating method thereof
A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided. |
| US09159621B1 |
Dicing tape protection for wafer dicing using laser scribe process
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of scribing a semiconductor wafer having a plurality of integrated circuits involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier that includes a tape frame mounted above the carrier tape. The method also involves overlaying a protective frame above a front side of the semiconductor wafer and above an exposed outer portion of the carrier tape, the protective frame having an opening exposing an inner region of the front side of the semiconductor wafer. The method also involves laser scribing the front side of the semiconductor wafer with the protective frame in place. |
| US09159620B2 |
Semiconductor structure and method for making same
One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a substrate; forming a dielectric layer over the substrate; forming a first opening and a second opening at least partially simultaneously through the dielectric layer over the substrate; and forming a third opening through the bottom surface of the first opening and into at least a portion of the substrate. |
| US09159619B2 |
Method for producing an electrical feedthrough in a substrate, and substrate having an electrical feedthrough
A method for producing an electrical feedthrough in a substrate having an electrical feedthrough, including: forming an etch stop layer on the front side of the substrate; forming a mask on the back side of the substrate; forming an annular trench in the substrate, which trench extends from the back to the front side, by an etching process that stops at the etch stop layer, using the mask, the trench surrounding a substrate punch; depositing a metal layer over the back side of the substrate using the mask, the metal layer penetrating into the annular trench and being deposited on the substrate punch; forming a metal silicide layer on the substrate punch by at least partially converting the metal layer into the metal silicide layer on the substrate punch; selectively removing a remainder of the metal layer; and closing off the annular trench at the back side of the substrate. |
| US09159618B2 |
Semiconductor device with contacts and metal interconnects and method of manufacturing the semiconductor device
A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact. |
| US09159617B2 |
Structure and method of forming silicide on fins
Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET. |
| US09159616B2 |
Silicon carrier space transformer and temporary chip attach burn-in vehicle for high density connections
A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures. |
| US09159615B2 |
Graphene interconnection and method of manufacturing the same
According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench. |
| US09159614B2 |
Packaging substrate and method for manufacturing same
A packaging substrate includes a first wiring layer, a first dielectric layer formed on the first wiring layer, a second wiring layer formed on the first dielectric layer, and a number of copper pillar bumps. Each copper pillar bump includes a base portion and a protruding portion. The base portion is connected to the first wiring layer, and the protruding portion is formed on the base portion. A size of the protruding portion is less than a size of the base portion, and a size of the copper pillar bump gradually increases from the protruding portion to the base portion. |
| US09159611B2 |
Method of forming electric contact interface regions of an electronic device
A method for forming electrical-contact interface regions on a wafer including a silicon-carbide substrate having a surface with at least one conductive region facing the surface. The method includes forming a first and a second resist layer; forming; removing portions of the second resist layer to form a through opening partially aligned to the conductive region; removing, selective portions of the first resist layer to expose the surface of the substrate; removing portions of the first resist layer that extend laterally staggered with respect to the through opening; depositing a nickel layer on the wafer to form a nickel region on the substrate in an area corresponding to the conductive region; removing the first and second resist layers; and carrying out a step of thermal treatment of the wafer to form nickel-silicide regions in electrical contact with the conductive region. |
| US09159608B2 |
Method for forming TiSiN thin film layer by using atomic layer deposition
There is disclosed a method for forming a TiSiN thin film on a substrate according to ALD including a first process of preheating a substrate while supplying Ar or N2 containing inert gas to a chamber, after disposing a substrate in a chamber; a second process of forming a TiN film on the substrate by repeating at least one time a process of purging over-supplied Ti containing gas after supplying Ti containing gas and inert gas after that and a process of purging residual product after supplying N containing gas and inert gas after that; a third process of forming a SiN film by repeating at least one time a process of purging over-supplied Si containing gas after supplying Si containing gas on the TiN film and supplying inert gas after that and a process of purging residual product after supplying N containing gas and supplying inert gas after that; and a fourth process of forming a TiSiN film having a desired thickness by repeating the second and third processes at least one time, a partial pressure range of the gas used in forming the TiSiN thin film is Ti containing gas: 9×10−3 Torr or less, Si containing gas: 1×10−3˜3×10−1 Torr and N containing gas: 7×10−3˜6×10−1 Torr, and a pressure range of the gas is 500 mTorr˜5 Torr and the Si content of the formed TiSiN thin film is 20 atom % or less. |
| US09159606B1 |
Metal air gap
Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The air gaps may be located between copper lines on the same layer. A sacrificial patterned dielectric layer is used as a template to form a layer of copper by physical vapor deposition in a substrate processing system (i.e. a mainframe). Without breaking vacuum, the copper is redistributed into the gaps with a copper reflow process. Dielectric material from the template is removed, again in the same mainframe, using a remote fluorine etch process leaving the gapfill copper as the structural material. A conformal capping layer (such as silicon carbon nitride) is then deposited (e.g. by ALD) to seal the patterned substrate before removing the patterned substrate from the mainframe. |
| US09159599B2 |
Apparatus for chemically etching a workpiece
Apparatus for chemically etching a workpiece includes a chamber for receiving a process gas and having a pumping port for extracting exhaust gases, and a workpiece support located in the chamber upstream of the pumping port. The chamber further includes a sub-chamber located upstream of the pumping port and downstream of the workpiece support, and the sub-chamber includes a window and an excitation source, adjacent the window, for creating a plasma in a sample of the exhaust gases to create an optical emission which can be monitored through the window. |
| US09159596B2 |
Clamping apparatus for cleaving a bonded wafer structure
Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave. |
| US09159594B2 |
Liquid processing apparatus and liquid processing method
Disclosed are a liquid processing apparatus and a liquid processing method that can advance a plurality of nozzle supporting arms into a processing chamber. The liquid processing apparatus includes a processing chamber, a nozzle configured to supply a fluid to a substrate held by a substrate holding unit, a nozzle supporting arm configured to support the nozzle, and an arm standby unit installed adjacent to the processing chamber and configured for the nozzle supporting arm retreating from the processing chamber to stand by. In the liquid processing apparatus, a plurality of nozzle supporting arms are installed and one nozzle supporting arm has a different height level from the other nozzle supporting arms. |
| US09159592B2 |
Method and apparatus for an automated tool handling system for a multilevel cleanspace fabricator
The present invention provides methods and apparatus capable of routine placement and replacement of fabricator tools in a designated tool location. The tool location can be selected from multiple tool locations arranged in a matrix with horizontal and vertical designations. The operation may be fully automated. In another aspect, the invention describes Cleanspace fabricators which use devices to routinely remove and place tooling. |
| US09159588B2 |
Packaged leadless semiconductor device
A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant. |
| US09159587B2 |
Glass wafers for semiconductors fabrication processes and methods of making same
The present disclosure is directed to the use of glass wafers as carriers, interposers, or in other selected applications in which electronic circuitry or operative elements, such as transistors, are formed in the creation of electronic devices. The glass wafers generally include a glass having a coefficient of thermal expansion equal to or substantially equal to a coefficient of thermal expansion of semiconductor silicon, an indexing feature, and a coating on at least a portion of one face of the glass. |
| US09159584B2 |
Methods and systems of retrieving documents
Methods and Systems of Retrieving Documents. Coding a plurality of stored documents as respective document feature vectors in a bit-attribute matric, each feature vector comprising an attribute or class. Generating a query vector based on a query document. Performing one or more logical operations between the query vector and the respective document features vectors in the bit-attribute matrix to obtain respective similarity measures. Assigning an attribute or class to the query document based on the attribute or classes of one or more of the feature vectors. |
| US09159581B2 |
Method of making a semiconductor device using a bottom antireflective coating (BARC) layer
This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees. |
| US09159577B2 |
Method of forming substrate pattern
According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region. |
| US09159575B2 |
Method for etching high-K dielectric using pulsed bias power
A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm). |
| US09159572B2 |
Method of producing semiconductor substrate product, and etching method to be used therein
A method of producing a semiconductor substrate product, the method containing: a step of preparing an aqueous solution containing 7% by mass or more and 25% by mass or less of a quaternary alkyl ammonium hydroxide; a step of preparing a semiconductor substrate having a silicon film comprising a polycrystalline silicon film or an amorphous silicon film; and a step of heating the aqueous solution at 80° C. or higher and applying the resultant aqueous solution onto the semiconductor substrate to etch at least a part of the silicon film. |
| US09159571B2 |
Tungsten deposition process using germanium-containing reducing agent
Methods for depositing low resistivity tungsten in features of substrates in semiconductor processing are disclosed herein. Methods involve using a germanium-containing reducing agent during tungsten nucleation layer deposition to achieve thin, low resistivity nucleation layers. |
| US09159569B2 |
Methods of forming charge-trapping regions
Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells. |
| US09159568B2 |
Method for fabricating memory cells having split charge storage nodes
Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element. |
| US09159563B2 |
Semiconductor device manufacturing method and semiconductor manufacturing apparatus
A semiconductor device manufacturing method according to the present invention includes a step of arranging a plurality of processing objects on a first tray and a second tray adjacent to the first tray, a plurality of application steps in which application of an application substance to the plurality of processing objects is repeated a certain number of times by emitting the application substance from an application device formed right above a contact position at which the first tray and the second tray contact each other, by swinging the application device along a first direction across the contact position, and by moving the first tray and the second tray in a second direction perpendicular to the first direction, and an interchange step of interchanging the first tray and the second tray in position without changing the directions of the first tray and the second tray corresponding to the second direction, the interchange step being executed at least one time among the plurality of application steps. |
| US09159558B2 |
Methods of reducing defects in directed self-assembled structures
Methods are disclosed for reducing the number of defects in a directed self-assembled structure formed on a guiding pre-pattern (e.g., a chemical pre-pattern) on a substrate. A first layer comprising a first self-assembly material is applied onto the guiding pre-pattern, with the first self-assembly material forming domains whose alignment and orientation are directed by the guiding pre-pattern; as a result, a first self-assembled structure is formed. The first self-assembled structure is washed away, and a second layer comprising a second self-assembly material is then applied. The second self-assembly material forms a second self-assembled structure having fewer defects than the first self-assembled structure. |
| US09159556B2 |
Alleviation of the corrosion pitting of chip pads
Methods for processing a metal pad of a chip and chip structures including a chip with a metal pad. A surface modification agent is applied to the metal pad on the chip. The surface modification agent is effective to increase the hydrophobicity of the metal pad and may involve silylation. |
| US09159553B2 |
Semipolar or nonpolar nitride-based devices on partially or fully relaxed alloys with misfit dislocations at the heterointerface
A dislocation-free high quality template with relaxed lattice constant, fabricated by spatially restricting misfit dislocation(s) around heterointerfaces. This can be used as a template layer for high In composition devices. Specifically, the present invention prepares high quality InGaN templates (In composition is around 5-10%), and can grow much higher In-composition InGaN quantum wells (QWs) (or multi quantum wells (MQWs)) on these templates than would otherwise be possible. |
| US09159547B2 |
Two step method of rapid curing a semiconductor polymer layer
A semiconductor device and method of making the semiconductor device is described. A semiconductor die is provided. A polymer layer is formed over the semiconductor die. A via is formed in the polymer layer. The polymer layer is crosslinked in a first process. The polymer layer is thermally cured in a second process. The polymer layer can comprise polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), or siloxane-based polymers. A surface of the polymer layer can be crosslinked by a UV bake to control a slope of the via during subsequent curing. The second process can further comprise thermally curing the polymer layer using conduction, convection, infrared, or microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer at a rate greater than or equal to 10 degrees Celsius per minute, and can be completely cured in less than or equal to 60 minutes. |
| US09159544B2 |
Mass analyser and method of mass analysis
An electrostatic ion trap for mass analysis includes a first array of electrodes and a second array of electrodes, spaced from the first array of electrode. The first and second arrays of electrodes may be planar arrays formed by parallel strip electrodes or by concentric, circular or part-circular electrically conductive rings. The electrodes of the arrays are supplied with substantially the same pattern of voltage whereby the distribution of electrical potential in the space between the arrays is such as to reflect ions isochronously in a flight direction causing them to undergo periodic, oscillatory motion in the space, focused substantially mid-way between the arrays. Amplifier circuitry is used to detect image current having frequency components related to the mass-to-charge ratio of ions undergoing the periodic, oscillatory motion. |
| US09159543B2 |
Ion deflector for a mass spectrometer
There is provided an ion deflector for use with a mass spectrometer for directing a flow of ions between two distinct axes of travel. The ion deflector includes an electric field inducer arranged so as to establish at least one electrostatic field capable of deflecting ions travelling substantially along a first intended path of travel so as to travel substantially along a second intended path of travel. |
| US09159539B2 |
Method and apparatus to provide parallel acquisition of mass spectrometry/mass spectrometry data
A system and method for acquisition of mass spectrometry data is configured to provide a stream of charged particles (e.g., from an analytical volume). A primary mass spectrometer (e.g., time-of-flight mass spectrometer) may be used to separate charged particles of the stream of charged particles based on their mass-to-charge ratio and detect the charged particles in a mass-to-charge spectrum. A stream of precursor ions having a selected mass range may be diverted from the stream of charged particles for fragmentation to provide fragment ions (e.g., fragment ions from the analytical volume). The fragment ions may be provided to a second mass spectrometer for analysis of the fragment ions (e.g., during the same time as the time-of-flight mass spectrometer is separating and detecting charged particles of the stream of charged particles based on their mass-to-charge ratio). |
| US09159536B2 |
Plasma processing apparatus, abnormal oscillation determination method and high-frequency generator
A plasma processing apparatus includes a processing container and a plasma generating mechanism including a high-frequency oscillator. The arrangement is configured to generate plasma within the processing container by using a high frequency wave oscillated by the high-frequency oscillator. In addition, an impedance regulator is configured to adjust impedance to be applied to the high-frequency oscillator. Further, a determining unit is configured to change the impedance to be adjusted by the impedance regulator and to determine an abnormal oscillation of the high-frequency oscillator based on (a) a component of a center frequency of a fundamental wave that is the high frequency wave oscillated by the high-frequency oscillator, and (b) a component of a peripheral frequency present at both ends of a predetermined frequency band centered around the center frequency of the fundamental wave in a state where the impedance is changed. |
| US09159534B2 |
Methods and structures for rapid switching between different process gases in an inductively-coupled plasma (ICP) ion source
An openable gas passage provides for rapid pumpout of process or bake out gases in an inductively coupled plasma source in a charged particle beam system. A valve, typically positioned in the source electrode or part of the gas inlet, increases the gas conductance when opened to pump out the plasma chamber and closes during operation of the plasma source. |
| US09159532B2 |
Method of analyzing a sample and charged particle beam device for analyzing a sample
The invention refers to a method and a charged particle beam device for analyzing an object using a charged particle beam interacting with the object. The object comprises a sample embedded in a resin. Interaction radiation in the form of cathodoluminescence light is detected for identifying areas in which the resin is arranged and in which the sample is arranged. Interaction particles are detected to identify particles within the resin and the sample for further analysis by using EDX analysis. |
| US09159529B2 |
Scanning electron microscope
It is an object of the present invention to provide a scanning electron microscope for discriminating an angle of an electron ejected from a sample without providing an opening for restricting the angle at outside of an axis. In order to achieve the object described above, there is proposed a scanning electron microscope which includes a deflector to deflect an irradiating position of an electron beam, and a control unit to control the deflector, and further includes a detector to detecting an electron provided by irradiating a sample with the electron beam, an opening configuring member arranged between the detector and the deflector and having an opening for passing the electron beam, and a secondary signal deflector to deflect an electron ejected from the sample, in which the secondary signal deflector is controlled to deflect the electron ejected from the sample toward an opening of passing the electron beam in accordance with a deflection control of the deflector. |
| US09159528B2 |
Electron beam apparatus
An electron beam apparatus includes at least one electron beam column. The at least one beam column includes an electron beam optical system to irradiate an electron beam on a surface of a sample, and a detection system to detect electrons generated from the electron beam. The electron beam optical system includes an object lens to focus the electron beam on a surface of the sample. The object lens includes an electrostatic lens having a first electrode to which a first voltage is applied, a second electrode that is grounded, a third electrode to which a second voltage is applied, and a fourth electrode that is grounded. The first through fourth electrodes sequentially arranged relative to the sample. |
| US09159527B2 |
Systems and methods for a gas field ionization source
In one aspect the invention provides a gas field ion source assembly that includes an ion source in connection with an optical column such that an ion beam generated at the ion source travels through the optical column. The ion source includes an emitter having a width that tapers to a tip comprising a few atoms. In other aspects, the methods provide for manufacturing, maintaining and enhancing the performance of a gas field ion source including sharpening the tip of the ion source in situ. |
| US09159521B1 |
LED area lighting optical system
A dual-reflector assembly includes an upper reflector and a lower reflector. The upper reflector includes a proximal end and a distal end. The lower reflector includes a proximal end and a distal end. A light source is positioned between the proximal ends of the upper reflector and the lower reflector. The upper reflector surrounds at least a portion of the lower reflector. The shape and orientation of the dual-reflector assembly can be formed by placing a cup reflector having an upper edge profile and a lower edge profile a predetermined distance away from a rotational axis and at a desired orientation, rotating the cup reflector around the rotational axis, obtaining the shape and orientation of the upper reflector and the lower reflector from the rotating upper edge profile and the rotating lower edge profile, respectively. |
| US09159517B2 |
Photocathode enhancement system
A photocathode enhancement system includes a cathode plate that is movably positioned relative to an incident optical beam. The emission surface of the cathode plate has an area between about 0.5 cm2 to greater than 100 cm2. The system includes a motion controller that is configured to control the movement of the cathode plate relative to the optical beam, so that the optical beam successively strikes non-overlapping portions of the emission surface, and may reach substantially the entire emission surface over a time period of about 10 seconds to about 100 seconds. The movement of the cathode plate is controlled so that on average, the heat from the optical beam is uniformly distributed over the emission surface of the cathode plate. |
| US09159515B2 |
Electromagnetic relay
An electromagnetic relay includes: a yoke capable of changing a magnetic pole thereof by an electromagnet; an armature that is magnetized by a permanent magnet and contacts with or separates from the yoke in accordance with the magnetic pole of the yoke; a movable contact that contacts with a fixing contact; an elastic body that biases the movable contact; and a pressing member that presses the elastic body in accordance with a movement of the armature to cause the movable contact to at least contact with or separate from the fixing contact, wherein a cover fixing the permanent magnet and the armature, and the pressing member are integrally formed. |
| US09159512B2 |
Electromagnetic opening/closing device
An electromagnetic opening/closing device A1 includes a detector 5 for detecting an opened or closed state of a contact unit 1; a malfunction determination unit 6 configured to determine presence or absence of malfunction based on the opened or closed state of the contact unit 1 detected through the detector 5 and an opened or closed state of the contact unit 1 corresponding to an exterior command; and an output unit 8 configured to supply an exterior with a determination result by the malfunction determination unit 6. |
| US09159511B2 |
Circuit and method for interrupting a current flow in a DC current path
A DC current path for DC power transmission includes a switchable element. An inductance is connected in series to the switchable element. When an interrupt scenario is detected, a resonance circuit is connected in parallel to the series connection of the switchable element and the inductance for charging a capacitance of the resonance circuit. An open state of the switchable element is effected and the resonance circuit is connected in parallel to the switchable element. By means of such arrangement and method, favorable fast interrupt times can be achieved. |
| US09159509B2 |
Hybrid keypad apparatus
Hybrid keypad apparatus are disclosed herein. An example dome sheet carrier apparatus disclosed herein includes a first carrier portion having a first plurality of domes and a second carrier portion adjacent the first carrier portion. The second carrier portion has a second plurality of domes different than the first plurality of domes, where each of the second plurality of domes has a conductive material adjacent an apex of the second plurality of domes. |
| US09159508B2 |
Switchgear device having at least one single-pole breaking unit comprising a contact bridge and circuit breaker comprising one such device
A switchgear device having a single-pole breaking unit which includes one of a pair of stationary contacts connected to a line-side current conductor, a movable contact bridge for closing and opening the stationary contacts, a line-side panel, a load-side panel opposite the line-side panel and two opposing lateral-side panels, which panels surround the stationary contacts and contact bridge, and form arc extinguishing chambers with a stationary contact within each chamber, an opening volume between chambers, and a quenching gas exhaust channel connected to a chamber, and opening through the line-side panel, which is opposite another load-side panel for contact with a trip device. |
| US09159500B2 |
Photoelectric conversion element
A photoelectric conversion element (100) according to the present disclosure includes: a photoanode (15); a counter electrode (32); a solid compound layer (22) disposed between the photoanode (15) and the counter electrode (32); a charge storage electrode (55) disposed at an interspace from the counter electrode (32); and an electrolyte medium (24) being contained in the solid compound layer (22) and filling the interspace. |
| US09159499B2 |
Additives for dye-sensitized solar cells
The present invention relates to the use of at least one imidazol derivative of formula I or 1-(3,3,4,4,4-pentafluorobutyl)-1H-imidazole, 1-(3,3,4,4,4-pentafluorobutyl)-1,2,3-triazole or 1-(2′-thioethyl)ethylimidazole as additive in dye-sensitized solar cells and to special electrolyte formulations and a dye-sensitized solar cell comprising at least one compound of formula I or 1-(3,3,4,4,4-pentafluorobutyl)-1H-imidazole, 1-(3,3,4,4,4-pentafluorobutyl)-1,2,3-triazole or 1-(2′-thioethyl)ethylimidazole. |
| US09159497B2 |
Low band gap copolymer and method for manufacturing same
Disclosed herein are a copolymer having a low band gap and a preparing method thereof, and more specifically, a copolymer having a low band gap and other various and excellent physical properties, and a preparing method thereof. |
| US09159495B2 |
Multilayer ceramic electronic component, manufacturing method thereof and board for mounting the same
There is provided a multilayer ceramic electronic component including a ceramic body including a plurality of dielectric layers stacked in a thickness direction and satisfying T/W>1.0 when it is defined that a width thereof is W and a thickness thereof is T, a plurality of first and second internal electrodes disposed in the ceramic body so as to face each other, having the dielectric layer interposed therebetween, and alternately exposed through both end surfaces of the ceramic body, and first and second external electrodes including head parts formed on both end surfaces of the ceramic body and two band parts connected to the head parts and formed on portions of upper and lower main surfaces of the ceramic body so as to be spaced apart from each other in a width direction, and electrically connected to the first and second internal electrodes, respectively. |
| US09159494B2 |
Multilayer ceramic condenser and method of manufacturing the same
Disclosed are a multilayer ceramic condenser and a method of manufacturing the same. The method includes printing a plurality of stripe-type inner electrode patterns in parallel on ceramic green sheets; forming a laminate by staking the ceramic green sheets having the plurality of stripe-type inner electrode patterns printed thereon; cutting the laminate in order to have a structure in which first and second inner electrode patterns are alternately stacked; and forming a first side part and a second side part by applying ceramic slurry in order to cover the sides of the laminate to which the first and second inner electrode patterns are exposed. |
| US09159488B2 |
Vacuum capacitor-voltage-transformer
[Task] The present invention aims to provide a vacuum capacitor instrument voltage transformer by which current and voltage can be much precisely measured.[Means for achieving task] The means is so made that a main capacitor portion 8 and a voltage dividing capacitor portion 10 are installed in a earthed vacuum vessel, a main ground circuit 30 is provided through which a leak current I2 flows from an outer surface of the primary line-path side vacuum vessel to the earth E, and a voltage dividing ground circuit 31 is provided through which a leak current I11 flows to the earth E through a voltage dividing insulating cylindrical member 11 that is disposed between an earthed portion and each of the main capacitor portion and the voltage dividing capacitor portion. |
| US09159487B2 |
Linear electromagnetic device
A linear electromagnetic device, such as an inductor, transformer or the similar device, may include a core in which a magnetic flux is generable. The device may also include an opening through the core. The device may additionally include a primary conductor received in the opening and extending through the core. The primary conductor may include a substantially square or rectangular cross-section. An electrical current flowing through the primary conductor generates a magnetic field about the primary conductor, wherein substantially the entire magnetic field is absorbed by the core to generate the magnetic flux in the core. |
| US09159486B2 |
Core for wire-wound electronic component, wire-wound electronic component, and common mode choke coil
A core for a wire-wound electronic component. The core has a winding base to be wound with a wire, and flanges located at both ends of the winding base in an extending direction of the winding base. The flanges protrude from the winding base in a first direction perpendicular to the extending direction. Each of the flanges has a plurality of protrusions on a first surface at a side of the flange in the first direction. An inclined surface is provided to extend from the first surface of each of the flanges to a second surface of the winding base at a side of the winding base in the first direction. |
| US09159485B2 |
Method for making an electrical inductor and related inductor devices
A method is for making an electrical inductor. The method includes forming a first subunit having a sacrificial substrate, and an electrically conductive layer defining the electrical inductor and including a first metal on the sacrificial substrate. The method includes forming a second subunit having a dielectric layer and an electrically conductive layer thereon defining electrical inductor terminals and having the first metal, and coating a second metal onto the first metal of one of the first and second subunits. The method includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate. |
| US09159482B2 |
Rupture resistant tank system
A rupture resistant system is provided and comprises a tank comprising a top member, a combined body member, the combined body member forming a side and bottom of the tank, the combined body member comprising at least one curved non-linear surface to define a partially curved interior in at least a portion of the tank; and a component situated within the tank and susceptible to creating increasing pressure within the tank when under a fault condition. At least one of the top, sidewall, and bottom members is connected to another of the top, sidewall, and bottom members in a manner so as to cause an increase in inner volume of the tank under increased pressure conditions. |
| US09159474B2 |
Connecting structure and connecting method of insulated wires
A connecting structure includes a sheathing connecting section in which sheathed sections of a plurality of electric wires, which are sections at both sides of exposed conductor sections, are bundled together in a state of being superimposed with each other; and a conductor connecting section in which the conductor sections of the plurality of electric wires are intertwined in a state of being folded back, and a section of the folded back conductor section remaining as a result of excluding a portion of the folded back conductor section are ultrasonically bonded in integration. |
| US09159473B2 |
Method of electrically conductively connecting two superconductive cables
A method of electrically conductively connecting two superconductive cables includes freeing the conductors and screens of surrounding layers at the ends of the two cables. Subsequently, the ends of the two cables (1, 2) are placed next o each other and parallel to one another in such a way that their free ends point, in the same direction, and the ends are rigidly connected to one another in this position. The conductors and their screens are electrically conductively connected to each other through electrical contact elements (8, 9) extending transversely of the axial direction. and the two cable ends treated in this manner are arranged in a housing (10) of a cryostat when building up the transmission length which, during operation of the transmission length, a flowable cooling agent with insulating properties flows through the housing. |
| US09159472B2 |
Twinax cable design for improved electrical performance
A twinax cable is described. The twinax cable has at least one twinax wire pair with a first shield tape wrapped around it and then surrounded by a second shield tape wrapped around the twinax wire pair and the first shield tape. The shield tapes are wrapped such that the metallic sides of the tape face and make contact with each other. |
| US09159469B2 |
Umbilical
An umbilical for use in the offshore production of hydrocarbons, and in particular a power umbilical for use in deep water applications, is described comprising a plurality of longitudinal strength members, wherein at least one longitudinal strength member comprises rope comprising high strength organic fibers having a tensile modulus >100 GPa. In this way, the or each longitudinal strength member being such a rope achieves the synergistic benefit of favorable mechanical properties in the axial direction, with weight reduction and other favorable mechanical properties, especially during tensioning or the like of the umbilical, more especially during manufacture, installation and/or repair. With weight reduction, longer umbilicals for deeper water can be made and used. |
| US09159467B2 |
Dielectric ceramic composition, electronic element, and composite electric element
In order to provide a dielectric ceramic composition capable of sintering at a low temperature, implementing a low relative dielectric constant, providing other excellent properties (such as a relative density and an insulation resistance), performing co-firing of different materials, and suppressing dispersion of Ag in the sintered body when the internal electrode is formed, the dielectric ceramic composition includes a main ingredient containing SiO2—K2O—B2O3-based glass of 40 to 65 weight %, quartz of 35 to 50 weight %, and amorphous silica of remaining weight %; and a subsidiary ingredient containing alumina of 1.5 to 4 weight %, K2O-MO—SiO2—B2O3-based glass (where “MO” denotes at least any one selected from a group consisting of CaO and SrO) of 5 to 20 weight % relative to the main ingredient of 100 weight %. |
| US09159465B2 |
Structures incorporating conformationally flexible conjugated polymers and methods of use
Methods, compositions and articles of manufacture involving conformationally flexible conjugated polymers are provided. A structure is provided comprising the conformationally flexible conjugated polymer bound to or associated with at least one member of a binding pair comprising a sensor molecule and a target molecule or the complex they form. The conformationally flexible conjugated polymer comprises at least one angled linker having bonds to its two adjacent polymeric units which form an angle of less than about 155° with respect to one another. Methods of use of such structures and solutions comprising them are also provided. |
| US09159463B2 |
Conductive material
According to one embodiment, a conductive material includes a carbon substance and a metallic substance mixed with and/or laminated to the carbon substance. The carbon substance has at least one dimension of 200 nm or less. The carbon substance includes a graphene selected from single-layered graphene and multi-layered graphene, a part of carbon atoms constituting the graphene is substituted with a nitrogen atom. The metallic substance includes at least one of a metallic particle and a metallic wire. |
| US09159462B2 |
Detection apparatus
The invention relates to a detection apparatus comprising a filter (20) for filtering a conical radiation beam (4) such that at least a first region (22) and a second region (23) of the radiation beam are generated having different energy spectra, wherein the first region of the radiation beam illuminates a first detector area (25) on a detection surface (21) of a detector, thereby generating a first set of detection values, and the second region of the radiation beam illuminates a second detector area (26) on the detection surface, thereby generating a second set of detection values. For example, by using the filter the detection apparatus can be used as dual-energy computed tomography apparatus, wherein, for instance, a standard computed tomography apparatus can be transformed to a dual-energy computed tomography apparatus by adding the filter to the standard computed tomography apparatus, preferentially without modifying the radiation source and the detector. |
| US09159458B2 |
Flash interface error injector
A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped. |
| US09159456B2 |
Semiconductor device
A semiconductor device of an embodiment is provided with a memory, a register configured to store a first data group including test data and read/write instruction data to the memory, a first inversion portion having an inverting function of a value of the test data outputted from the register, a second inversion portion having the inverting function of a value of the read/write instruction data outputted from the register, first and second input portions configured to input a data inversion instruction to the first and second inversion portions, and a data switching portion configured to switch between a test data group obtained by applying predetermined processing to the first data group outputted from the register through the first and second inversion portions and a second data group used for reading/writing of data held in the memory during a system operation as input data into the memory. |
| US09159455B2 |
Data retention error detection system
A particular method includes selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell. A pinned layer of the MTJ memory cell has a first direction of magnetization, and a free layer of the MTJ memory cell has a second direction of magnetization. An external magnetic field that has a third direction of magnetization that is opposite to the second direction of magnetization is applied to the MTJ memory cell. A strength of the external magnetic field is determined based on the threshold data retention time. Subsequent to applying the external magnetic field, a read operation is performed on the MTJ memory cell to determine a logic value of the MTJ memory cell. The method further includes determining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value. |
| US09159453B2 |
Memory device and method for measuring resistance of memory cell
A memory device includes a plurality of resistive memory units configured to receive a voltage of a corresponding line of a plurality of program/read lines, a plurality of switch units configured to each electrically connect a corresponding one of the resistive memory units with a corresponding line of a plurality of column lines in response to a voltage of a corresponding line of a plurality of row lines, where the program/read lines correspond to the row lines, respectively, a row control circuit configured to turn on the switch units by selecting at least one of the row lines and apply an external voltage to a program/read line corresponding to the selected row line in a first test mode, and a column control circuit configured to select at least one of the column lines and couple the selected column line with a ground voltage terminal in the first test mode. |
| US09159452B2 |
Automatic word line leakage measurement circuitry
The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device. |
| US09159451B2 |
Testing system and testing method thereof
A testing system for a wafer having a plurality of flash memory dies is provided. The testing system includes a testing apparatus and a probe card coupled to the testing apparatus via a specific transmission line. The testing apparatus provides a testing requirement. The probe card includes a plurality of probes and a controller. The probes contact with at least one of the flash memory dies of the wafer. The controller writes a testing data to the flash memory die according to the testing requirement and reads the testing data from the flash memory die via the probes. The controller provides a testing result to the testing apparatus according to the read testing data. |
| US09159450B2 |
Sampling circuit for measuring reflected voltage of transformer for power converter operated in DCM and CCM
A sampling circuit of the power converter according to the present invention comprises an amplifier circuit receiving a reflected voltage for generating a first signal. A first switch and a first capacitor are utilized to generate a second signal in response to the reflected voltage. A sample-signal circuit generates a sample signal in response to the disable of a switching signal. The switching signal is generated in accordance with a feedback signal for regulating an output of the power converter. The feedback signal is generated in accordance with the second signal. The sample signal is utilized to control the first switch for sampling the reflected voltage. The sample signal is disabled once the first signal is lower than the second signal. The sampling circuit precisely samples the reflected voltage of the transformer of the power converter for regulating the output of the power converter. |
| US09159447B2 |
Shift register unit, shift register, array substrate and display apparatus
The present disclosure relates to a field of display. Particularly, embodiments of the present invention disclose a shift register unit, a shift register, an array substrate and a display apparatus that enable the respective shift register units to be reset independently. The shift register unit includes a sampling part, an output part and a reset part, wherein the sampling part includes a first switching transistor and a second switching transistor, the output part includes a fifth switching transistor, a sixth switching transistor, a first capacitor and a second capacitor, and the reset part includes a third switching transistor and a fourth transistor. |
| US09159444B2 |
Semiconductor device and method for driving the same
A semiconductor device includes at least one first row selection line, at least one column selection line that intersects with the first row selection line, and a first fuse circuit including a first fuse array, and suitable for outputting a first fuse signal programmed in the first fuse array by using an external voltage as a source voltage in a power-up mode, wherein the first fuse array includes at least one first fuse cell coupled with the first row selection line and the column selection line. |
| US09159439B2 |
Semiconductor memory device
A semiconductor memory device includes a sense amplifier, and the sense amplifier includes a bus, first and second latch circuits, and a third transistor. The first latch circuit includes a first transistor connected to the bus, and the second latch circuit includes a second transistor connected to the bus. When data is transmitted from the first latch circuit to the second latch circuit, a third transistor is switched on to precharge the bus by applying a first voltage that is lower than a power source voltage of the first and second latch circuits to a gate of the third transistor. Thereafter, second and third voltages that are lower than the power source voltage are applied to gates of first and second transistors, respectively. |
| US09159432B2 |
Method of programming a nonvolatile memory device
In method of programming a nonvolatile memory device including first and second cell strings that are coupled to one bitline, a first channel of the first cell string and a second channel of the second cell string are precharged by applying a first voltage to the bitline, one cell string is selected from the first and second cell strings, and a memory cell included in the selected cell string is programmed by applying a second voltage greater than a ground voltage and less than the first voltage to the bitline. |
| US09159430B2 |
Method for block-erasing a page-erasable EEPROM-type memory
A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines. |
| US09159428B2 |
Auto-refresh method for SONOS non-volatile memory array
A method for performing auto-refresh of a SONOS memory in a field programmable gate array in a system, includes sensing an auto-refresh condition, selecting a memory segment that has not yet been refreshed, storing the contents of memory segment, erasing the memory cells in the memory segment, and reprogramming the memory cells in the memory segment, until all of the memory segments have been reprogrammed. |
| US09159427B2 |
Memory devices and their operation with different sets of logical erase blocks
Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria. |
| US09159422B1 |
Cross page management to avoid NAND physical page size limitation
A method of writing data to non-volatile computer storage is disclosed. A logical page of data is received and stored in an intermediate storage. A first portion of the logical page is read from the intermediate storage and written to a first physical page in the non-volatile computer storage. A second portion of the logical page is read from the intermediate storage and written to a second physical page in the non-volatile computer storage. A method of reading data from non-volatile computer storage is disclosed. A first portion of a logical page is read from a first physical page in the non-volatile computer storage and written in an intermediate storage. A second portion of the logical page is read from a second physical page and written in the intermediate storage. The first portion and the second portion of the logical page are concatenated to form the logical page. |
| US09159419B2 |
Non-volatile memory interface
Apparatuses, systems, methods, and computer program products are disclosed for a memory controller. An apparatus includes a volatile memory medium located on a memory module. An apparatus includes a non-volatile memory medium located on a memory module. A memory controller is located on a memory module. A memory controller may be configured to provide access to at least a non-volatile memory medium over a direct wire interface with a processor. |
| US09159415B2 |
Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof
The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor. |
| US09159413B2 |
Thermo programmable resistor based ROM
An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell. |
| US09159407B2 |
Soft readout from analog memory cells in the presence of read threshold errors
A method includes storing data in a group of analog memory cells by writing respective analog values into the memory cells in the group. After storing the data, the analog values are read from the memory cells in the group one or more times using one or more respective read thresholds so as to produce readout results. Reliability measures are computed for the read analog values based on the readout results. An offset of the one or more read thresholds from an optimal read threshold position is estimated based on the reliability measures. The reliability measures are modified to compensate for the estimated offset, and the data stored in the analog memory cells in the group is decoded using the corrected reliability measures. |
| US09159403B2 |
Control circuit of SRAM and operating method thereof
A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage. |
| US09159401B2 |
Semiconductor device having hierarchical bit line structure
A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON. |
| US09159399B2 |
Data transmission circuit and semiconductor memory device having the same
A data transmission circuit includes first to fourth local lines, one or more first bit line sense amplifiers configured to correspond to the first local line, one or more second bit line sense amplifiers configured to correspond to the second local line, one or more third bit line sense amplifiers configured to correspond to the third local line, one or more fourth bit line sense amplifiers configured to correspond to the fourth local line, and a selection unit configured to select some first to fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to a first address in a first mode, and select some first and second bit line sense amplifiers or some third and fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to the first address and a second address in a second mode. |
| US09159398B2 |
Memory core and semiconductor memory device including the same
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages. |
| US09159397B2 |
Methods and apparatuses for refreshing memory
Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method further includes refreshing the memory at a first refresh rate after receiving the self refresh command. The method further includes refreshing the memory at a second refresh rate in response to a determination that each memory cell of the memory has been refreshed at the first refresh rate. The first refresh rate is greater than a second refresh rate. |
| US09159394B2 |
Ring-shaped magnetoresistive memory device and writing method thereof
A ring-shaped magnetoresistive memory device includes a ring-shaped magnetoresistive memory cell, a first conductor, and a second conductor. The first conductor is positioned on a first surface of the ring-shaped magnetoresistive memory cell for generating a first magnetic field pulse. The second conductor is positioned on a second surface of the ring-shaped magnetoresistive memory cell for generating a second magnetic field pulse. The first surface is opposite to the second surface. An extension direction of the first conductor is perpendicular to an extension direction of the second conductor. A time delay is between the first magnetic field pulse and the second magnetic field pulse. |
| US09159390B2 |
Domain crossing circuit of semiconductor apparatus
A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal. |
| US09159385B2 |
Memory architecture with local and global control circuitry
A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier. |
| US09159383B2 |
Signal management in a memory device
Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device. |
| US09159382B2 |
Method and apparatus for timing adjustment
A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section. |
| US09159377B2 |
Resistive memory apparatus, operating method thereof, and system having the same
A resistive memory apparatus includes a memory unit including a resistive memory cell array, a voltage generation unit suitable for receiving a radio frequency (RF) signal, and converting the RF signal into a direct current (DC) voltage, and a control unit suitable for controlling a refresh operation to be performed on the resistive memory cell array, wherein the boosted DC voltage is used as an operation voltage for the refresh operation. |
| US09159375B2 |
Selectively conducting devices, diode constructions, methods of forming diodes and methods of current modulation
Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods. |
| US09159372B2 |
Housing for receiving a removable hard disk, including a tilting cam for removing said hard disk
A box is provided for receiving a removable element. The box is a generally rectangular box fitted with a tilting cam of cut-out sheet metal situated in the rear portion of the box body, the tilting cam having an actuation end and an ejection end situated on either side of a central portion of said cam for the purpose of ejecting the removable element when the cam is tilted about its central portion. The box body has in the rear portion of its top face a tab including a base extended by a tongue that extends parallel to said top face while being spaced apart from said top face, together with a lug projecting from the top face and situated facing a free end of the tongue. The tilting cam is secured to the box body by snap-fastening, having its central portion engaged firstly between the tongue and the top face of the box body, and secondly between the lug and the base. |
| US09159371B2 |
Forensic video recording with presence detection
At a high level, embodiments of the invention relate to augmenting video data with presence data derived from one or more proximity tags. More specifically, embodiments of the invention generate forensically authenticated recordings linking video imagery to the presence of specific objects in or near the recording. One embodiment of the invention includes video recording system comprising a camera, a wireless proximity tag reader, a storage memory and control circuitry operable to receive image data from the camera receive a proximity tag identifier identifying a proximity tag from the proximity tag reader, and store an encoded frame containing the image data and the proximity tag identity in the storage memory. |
| US09159369B1 |
MR-offset change detection and compensation
A method, computer-readable medium, and storage device for detecting and compensating for a change in MR-offset in a disk-based storage device. A pattern is written to a track on a disk of the storage device utilizing a read/write head. The read channel of the storage device is then configured as a harmonic sensor and the pattern is read from the track at a specific off-track position of the read/write head. The magnitude of the harmonic sensor is measured during the read, and the change in MR-offset is calculated for the read/write head based on the measured magnitude value and a predetermined transfer function between off-track amount and harmonic sensor magnitude. The change in MR-offset may then be utilized by a servo mechanism of the storage device to correct head positioning during a write operation for the read/write head. |
| US09159345B1 |
Micrometer scale components
Micrometer scale components comprise a component body comprising an alloy of a first solder metal and a second solder metal, the alloy having a higher liquidus temperature than the second solder metal; and a base region of the structure body wetted to a substrate, wherein the component body has a molded surface profile. |
| US09159341B2 |
Systems and methods for protecting a sensitive device from corrosion
A product according to one embodiment includes a tape having an applicator portion for applying an organic coating to a magnetic head for reducing exposure of the head to oxidation promoting materials; the organic coating on the applicator portion of the tape; and a lubricant on a data portion of the tape. A product according to another embodiment includes a tape having a data portion along a portion of a length thereof, and a cleaning portion along another portion of the length of the tape, the cleaning portion being for removing an organic coating from a magnetic head. A magnetic storage system according to one embodiment includes a magnetic head having a removable organic coating thereon in an amount sufficient for reducing exposure of the head to oxidation promoting materials. |
| US09159340B1 |
Coil structure for write head
A write head having a main pole having a pole tip, the main pole having a leading side and a trailing side; and a coil structure around the main pole, the coil structure having no more than two active turns on the trailing side. A non-active, or dummy turn, may be present. |
| US09159339B2 |
Wire and wire lead designs for a wire-assisted magnetic write device
A magnetic device includes a write element having a write element tip that defines a medium confronting surface. The write element is operable to generate a first field at the medium confronting surface. A conductor is proximate the write element tip and first and second conductive leads are connected to the conductor and configured to deliver a current to the conductor to generate a second field that augments the first field. First and second side elements are disposed on opposite sides of the write element tip in a cross-track direction at the medium confronting surface. At least a portion of the first conductive lead is disposed adjacent the first side element on a side opposite the medium confronting surface, and at least a portion of the second conductive lead is disposed adjacent the second side element on a side opposite the medium confronting surface. |
| US09159338B2 |
Systems and methods of rendering a textual animation
Systems and methods of rendering a textual animation are provided. The methods include receiving an audio sample of an audio signal that is being rendered by a media rendering source. The methods also include receiving one or more descriptors for the audio signal based on at least one of a semantic vector, an audio vector, and an emotion vector. Based on the one or more descriptors, a client device may render the textual transcriptions of vocal elements of the audio signal in an animated manner. The client device may further render the textual transcriptions of the vocal elements of the audio signal to be substantially in synchrony to the audio signal being rendered by the media rendering source. In addition, the client device may further receive an identification of a song corresponding to the audio sample, and may render lyrics of the song in an animated manner. |
| US09159334B2 |
Voice processing device and method, and program
A voice processing device includes a voice pitch converting unit that performs a voice pitch converting process with respect to an input voice signal and converts voice pitch of the input voice signal, an error detecting unit that detects an error between the number of samples of an output voice signal, which is expected, and the number of samples of the output voice signal, which is actually output, and a time length control unit that controls adjustment of the time length in such a manner that the time length of the output voice signal is corrected by the amount of the error. |
| US09159331B2 |
Bit allocating, audio encoding and decoding
A bit allocating method is provided that includes determining the allocated number of bits in decimal point units based on each frequency band so that a Signal-to-Noise Ratio (SNR) of a spectrum existing in a predetermined frequency band is maximized within a range of the allowable number of bits for a given frame; and adjusting the allocated number of bits based on each frequency band. |
| US09159327B1 |
System and method for adding pitch shift resistance to an audio fingerprint
Systems and techniques for adding pitch shift resistance to an audio fingerprint are presented. In particular, an audio track for a media file is received. A first audio fingerprint for the audio track with a first pitch shift and an Nth audio fingerprint for the audio track with an Mth pitch shift are generated, where N is an integer greater than or equal to two and M is an integer greater than or equal to two. A combined audio fingerprint is generated from at least the first audio fingerprint and the Nth audio fingerprint. |
| US09159326B2 |
MDCT-based complex prediction stereo coding
The invention provides methods and devices for stereo encoding and decoding using complex prediction in the frequency domain. In one embodiment, a decoding method, for obtaining an output stereo signal from an input stereo signal encoded by complex prediction coding and comprising first frequency-domain representations of two input channels, comprises the upmixing steps of: (i) computing a second frequency-domain representation of a first input channel; and (ii) computing an output channel on the basis of the first and second frequency-domain representations of the first input channel, the first frequency domain representation of the second input channel and a complex prediction coefficient. The method comprises performing frequency-domain modifications selectively before or after upmixing. |
| US09159325B2 |
Pitch shifting frequencies
System and methods for audio editing are provided. In one implementation, a computer-implemented method is provided. The computer-implemented method includes presenting a visual representation of digital audio data as a frequency spectrum including a first visual region corresponding to a first time period and a first frequency range in the digital audio data. A first user input identifies a second visual region within the first visual region and corresponding to a second time period and a second frequency range. A second user input specifies one or more frequency modifications to the second visual region. The second time period and the second frequency range corresponding to the second visual region are modified creating a modified second visual region. The modified second visual region is mixed into the first visual region creating edited digital audio data. |
| US09159321B2 |
Lip-password based speaker verification system
A lip-based speaker verification system for identifying a speaker using a modality of lip motions; wherein an identification key of the speaker comprising one or more passwords; wherein the one or more passwords are embedded into lip motions of the speaker; wherein the speaker is verified by underlying dynamic characteristics of the lip motions; and wherein the speaker is required to match the one or more passwords embedded in the lip motions with registered information in a database. That is, in the case where the target speaker saying the wrong password or even in the case where an impostor knowing and saying the correct password, the nonconformities will be detected and the authentications/accesses will be denied. |
| US09159320B2 |
Endpoint detection apparatus for sound source and method thereof
An apparatus for detecting endpoints of sound signals when sound sources vocalized from a remote site are processed even if a plurality of speakers exists and an interference sound being input from a direction different from a direction of one speaker, and a method thereof, wherein in an environment in which a plurality of sound sources exists, the existence and the length of the sound source being input according to each direction is determined and the endpoint is found, thereby improving the performance of the post-processing, and speech being input from a direction other than a direction of speech from a speaker vocalized at a remote area from a sound source collecting unit is distinguished while the speech from the speaker is being recorded, thereby enabling a remote sound source recognition without restriction on the installation region of a microphone. |
| US09159319B1 |
Keyword spotting with competitor models
Keyword spotting may be improved by using a competitor model. In some embodiments, audio data is received by a device. At least a portion of the audio data may be compared with a keyword model to obtain a first score. The keyword model may model a keyword. The portion of the audio data may also be compared with a competitor model to obtain a second score. The competitor model may model a competitor word, which may be a word that is similar to the keyword. The device may compare the first score and the second score to determine if a keyword is spoken. |
| US09159316B2 |
Automatic language model update
A method for generating a speech recognition model includes accessing a baseline speech recognition model, obtaining information related to recent language usage from search queries, and modifying the speech recognition model to revise probabilities of a portion of a sound occurrence based on the information. The portion of a sound may include a word. Also, a method for generating a speech recognition model, includes receiving at a search engine from a remote device an audio recording and a transcript that substantially represents at least a portion of the audio recording, synchronizing the transcript with the audio recording, extracting one or more letters from the transcript and extracting the associated pronunciation of the one or more letters from the audio recording, and generating a dictionary entry in a pronunciation dictionary. |
| US09159312B1 |
Audio device with privacy mode
A device includes an audio processor, a first speaker, and a second speaker. The audio processor is configured to receive an audio signal. The first speaker is operatively coupled to the audio processor and is configured to produce a first sound wave. The first sound wave is associated with the audio signal. The second speaker is operatively coupled to the audio processor and is configured to produce a second sound wave. The second sound wave is configured to at least partially cancel the first sound wave. |
| US09159303B1 |
Slide guitar
Slide guitar for providing various improvements and advantages including instant accurate string height adjustments simultaneously at the nut and bridge. The slide guitar has a marked adjustment knob adjacent a graduated scale under the headstock to visually determine with repeated mathematical accuracy the exact distance between the bottom of the strings and the top of the first fret as a point of reference. The improved string musical instrument includes a leveling head embedded into portions of the headstock and neck wherein the leveling head contains a slide selector having a sloped surface for contacting the nut combined with a dual bridge for instantly changing the instrument's string height and bridge type. The slide guitar instantly changes from a conventional type guitar to a steel type guitar creating an improved variable string action slide guitar. |
| US09159300B2 |
Seat layout display apparatus, seat layout display method, and program thereof
A display apparatus includes: a location acquisition unit that acquires an image location designated by an operation of the user in the planar image of the user symbol; a direction setting unit that specifies an area to which the image location of the user symbol belongs from among a plurality of areas into which the planar image is divided and with which a predetermined direction is associated in advance, respectively, and sets, as a direction of eyes of the user, a direction that is associated in advance with the area specified; and a display control unit that displays the planar image in which the seat symbols and the user symbol are arranged in such a way of being associated with a seat layout in a room visually recognized when the user views in the direction of eyes. |
| US09159285B2 |
Display device having repair structure
A display device having a repair structure that makes a defective pixel operate as a normal pixel in a display panel. |
| US09159282B2 |
Display device and method of canceling offset thereof
A method of canceling an offset of display device includes coinciding offset directions of amplifiers with one another and canceling offsets of the amplifiers through a chopping operation. |
| US09159280B1 |
GOA circuit for liquid crystal displaying and display device
The present invention relates to a GOA circuit for liquid crystal displaying and a display device. The GOA circuit includes a plurality of cascaded GOA units and the nth-stage GOA unit includes a pull-up part (100), a key pull-down part (200), a pull-down holding part (300), a pull-up control part (400), and a boost capacitor (Cb). In operation, a nth-stage clock signal (CK(n)) and first and second clock signals (LC1 and LC2) are inputted. The frequencies of the first clock signal (LC1) and the second clock signal (LC2) are lower than the nth clock signal (CK(n)). The first clock signal (LC1) charging a first circuit point (P) and the second clock signal (LC2) charging a second circuit point (K) are alternately carried out. The present invention also provides a corresponding display device. The GOA circuit of the present invention precisely controls the voltage of the gate Q(n) that affects charging of a horizontal scan line by means of the low frequency clock signal and the high frequency clock signal, so as to ensure a stable output of the GOA charging signal. |
| US09159273B2 |
Display device and display method
Disclosed herein is a display device including: a liquid crystal display section adapted to display an image based on a video signal; a backlight; and a processing section adapted to correct the video signal and set the luminance of the backlight based on two pieces of information, a peak level of the video signal in a display screen or in each of a plurality of partial display areas into which the display screen is divided, and factor data obtained from a data map made up of a reference position on the display screen and the factor data that are associated with each other. |
| US09159271B2 |
Illumination device and liquid crystal display device
An illumination device includes a metal base substrate in a flat planar shape, a plurality of LED modules, and a driving unit which drives each of the LEDs arranged on the metal base substrate. The LED modules have an organic substrate, a plurality of LEDs which are arranged on the organic substrate, a metal member, LED control signal terminals which are set on the edge of the organic substrate, and voltage feed terminals which are set on the edge of the organic substrate. The metal member corresponds to each LED and to which the heat from the LEDs is conducted, and which is electrically connected via a switch element from an electrode of the LED, and which penetrates the organic substrate toward its width direction from the LED mounting surface of the organic substrate and is exposed from the opposite surface. |
| US09159269B2 |
Display device and illumination unit
A display device includes: a reflective image display unit having a display region provided with an array of pixels; an illumination unit that illuminates the display region of the image display unit; and a light control unit that controls the intensity of the illumination light from the illumination unit according to ambient illuminance. |
| US09159265B2 |
Pixel, display device including the same, and driving method thereof
A display device includes a plurality of pixels including a first capacitor connected between a data line and a first node, a switching transistor connecting the first node and a second node, a first light emitting transistor transmitting a first power source voltage to the second node, a driving transistor having one electrode connected to the second node and controlling a driving current flowing to an organic light emitting diode (OLED), and a reference voltage transistor transmitting a reference voltage to the first node, wherein, when the first power source voltage is applied to the second node through the first light emitting transistor such that a light emitting step in which the OLED emits light is simultaneously performed in a plurality of pixels. |
| US09159264B2 |
Organic light emitting display and method of driving thereof
An organic light-emitting display device and a method of driving the display device are disclosed. A pixel circuit used in the organic light-emitting display device includes a first switching transistor, a second switching transistor and a driving transistor. The first switching transistor switches a data voltage in response to a first control signal. The second switching transistor switches a compensation voltage in response to a second control signal. The driving transistor provides an electric current to an organic light-emitting device in response to the data voltage and the compensation voltage. |
| US09159261B2 |
Method of generating image compensation data for display device, image compensation device using the same, and method of operating display device
A method of generating image compensation data for a display device includes concurrently measuring, by a first image compensation device, first luminance values and first color coordinate values from an image displayed at a display panel in the display device, a number of the first color coordinate values being less than a number of the first luminance values; concurrently generating first luminance data and first color coordinate data associated with the image based on the first luminance values and the first color coordinate values, respectively; and generating first image compensation data for compensating the image based on the first luminance data, the first color coordinate data, a reference luminance value and a reference color coordinate value. |
| US09159252B2 |
Hanging luminous frame of a traffic sign plate
A hanging luminous frame of a traffic sign plate includes elementary frame sections, each being a long hollow enclosure which defines a luminous frame surface and a concave back side, wherein the concave back side is to be supported against the marking surface of the traffic sign plate. Connecting edges allow the elementary frame sections to be connected to each other and form a frame. Luminous through holes are distributed over the luminous frame surfaces. Waterproof transparent covers have a housing enclosure part, a transparent covering part and a fitting and positioning part. LED lighting components have a circuit base plate, LED components and conductor wires, wherein the LED lighting component is held inside the waterproof transparent cover. A waterproof layer is filled in the housing enclosure parts to seal the inside circuit base plate. Positioning and reinforcing edges provide a stable locking interface for the locking and positioning component. |
| US09159251B2 |
Magnetic fastener for competitive athletics
Embodiments of the invention affix numbering indicators to clothing of competitors during competitive events. A strong magnetic attraction in conjunction with an interaction between a projection on the bottom surface of a top magnetically attractive member and a hole in the bottom magnetically attractive member resists movement of the numbering indicator, while allowing lateral repositioning. The two magnetically attractive members can be encased in a water-resistant material to prevent degradation or discoloration by exposure to sweat. A graphical layer affixed to the upper surface of the top magnetically attractive member can display a custom visual depiction, such as a brand logo or advertisement. Additionally, a transparent layer can be affixed to the graphical layer to protect it from degradation while also permitting a substantially clear view of the visual depiction. |
| US09159248B2 |
Patient models for oral surgery
A model head including a jaw insert having layers of varying materials replicating the anatomical features of a human jaw. The jaw may include a mock nerve system that provides a signal to indicate the condition of the nerve. The jaw also may include a circulatory system including vessels that simulate the bleeding that occurs when a vessel in a human has been damaged. |
| US09159247B2 |
Dental patient models
A model head including a jaw insert having layers of varying materials replicating the anatomical features of a human jaw. The jaw may include a mock nerve system that provides a signal to indicate the condition of the nerve. The jaw also may include a circulatory system including vessels that simulate the bleeding that occurs when a vessel in a human has been damaged. |
| US09159245B2 |
Equestrian performance sensing system
Systems, devices, and methods for gathering data from a horse and rider and providing training to the rider are provided. In one aspect, for example, a method of training an equestrian rider can include performing a ride by an equestrian rider on a horse, and obtaining ride data from the ride, the ride data including video, inertial measurements, rider joint, head, torso, and/or limb information, horse joint, head, torso, and/or limb information, and at least one force measurement between the horse and the rider during the rider. The ride data can then be analyzed and at least one riding improvement to be made by the rider can be identified, and the at least one riding improvement to be made to the rider can be relayed to the rider to provide training for a subsequent ride. |
| US09159244B2 |
Simulation device for training equipment for a vehicle
The invention relates to a simulation device (110) for training equipment (100) for a real ground vehicle, comprising —a vehicle model (115) comprising a predetermined number of function models (130b; 131b; 132b) for simulation of corresponding physical function elements (130a; 131a; 132a) of said vehicle; —arrangements (399) for engaging physical function elements (130a; 131a; 132a) to the simulation device (110). The simulation device (110) is arranged such that a function model (130b; 131 b; 132b) concerning a determined function element (130a; 131a, 132a) is intended to be deactivated at engagement of corresponding physical function elements (130a; 131a; 132a) and such that the deactivated function model (130a; 131b; 132b) is reactivated at disengagement of said engaged function element (130a; 131a; 132a). The invention also relates to a computer program and a computer program product comprising a program code (P) for a computer (110; 300). |
| US09159242B2 |
Real-time fault detection in an instrument landing system
An electronic system with real-time fault detection is provided. In one embodiment, the system includes analog circuitry, having a first input coupled to receive an input signal and a second input coupled to receive a test signal. The test signal is at an edge of a selected band that contains the input signal. The test signal is used to identify faults in the electronic system during operation of the electronic system. The electronic system further includes an analog to digital (A/D) converter coupled to an output of the analog circuitry. The A/D converter generates digitized spectrum. Digital circuitry is coupled to the output of the A/D converter. The digital circuitry processes the input signal from the band to provide an output for the system and processes the test signal to detect faults in the analog circuitry, the digital circuitry and the A/D converter. |
| US09159238B2 |
Location-aware selection of public transportation
A mobile device such as a mobile phone, smart phone, personal music player, handheld game device and the like that is configured to be location-aware through GPS (Global Positioning System), cell tower positioning, or other means of determining location, is provided with a public transportation selector functionality that interfaces with one or more on-line public transportation schedule services. The public transportation selector passes the location of a user of the mobile device, the user's destination, and the targeted arrival time to the schedule services which responsively return information including, for example, station/stop location information, route identifier, departure and arrival times, and fare costs. The public transportation selector aggregates schedule information provided by the services for presentation to the user through a user interface on the mobile device. The user can then select the desired public transportation option and be provided with directions to the appropriate station or stop. |
| US09159236B2 |
Presentation of shared threat information in a transportation-related context
Techniques for ability enhancement are described. In some embodiments, devices and systems located in a transportation network share threat information with one another, in order to enhance a user's ability to operate or function in a transportation-related context. In one embodiment, a process in a vehicle receives threat information from a remote device, the threat information based on information about objects or conditions proximate to the remote device. The process then determines that the threat information is relevant to the safe operation of the vehicle. Then, the process modifies operation of the vehicle based on the threat information, such as by presenting a message to the operator of the vehicle and/or controlling the vehicle itself. |
| US09159229B2 |
Smart and scalable urban signal networks: methods and systems for adaptive traffic signal control
Scalable urban traffic control system has been developed to address current challenges and offers a new approach to real-time, adaptive control of traffic signal networks. The methods and system described herein exploit a novel conceptualization of the signal network control problem as a decentralized process, where each intersection in the network independently and asynchronously solves a single-machine scheduling problem in a rolling horizon fashion to allocate green time to its local traffic, and intersections communicate planned outflows to their downstream neighbors to increase visibility of future incoming traffic and achieve coordinated behavior. The novel formulation of the intersection control problem as a single-machine scheduling problem abstracts flows of vehicles into clusters, which enables orders-of-magnitude speedup over previous time-based formulations and is what allows truly real-time (second-by-second) response to changing conditions. |
| US09159227B2 |
Traffic congestion detection apparatus and vehicle control apparatus
A traffic congestion detection apparatus includes a traveling information acquisition unit for acquiring traveling information relating to a traveling state of a vehicle, and a traveling zone determination unit for determining which one of at least three zones including a central zone of a congestion area the vehicle is traveling in, based on current traveling information acquired by the traveling information acquisition unit. |
| US09159226B2 |
Electronic appliance cover adapted against infrared radiation
A cover of an electronic appliance capable of receiving infrared type signals from a remote monitoring device, the cover including a receiving area intended to be placed facing an infrared receiver of the electronic appliance, wherein the receiving area includes, placed at least partially in or on the receiving area, a filtering element configured to reduce the intensity of infrared signals received by the electronic appliance, the filtering element being constituted of an ink covering at least partially other areas of the cover. |
| US09159222B2 |
Method and apparatus for wireless remote control of an electric appliance
An electric appliance remote control apparatus includes a wireless module, a memory unit, a connection unit, a controlling module, a power supply unit, and a power input end. The wireless module can receive a remote control signal and convert the remote control signal into an enabling signal. The controlling module controls ON/OFF of power from the power supply unit to the connection unit according to the enabling signal. In a method using the electric appliance remote control apparatus, the connection unit is connected to an electric appliance. Monitoring programs corresponding to the electric appliance remote control apparatus are downloaded by and installed in a handheld device and provide an operation interface on a screen of the handheld device. The remote control signal is sent to the wireless module through the operation interface of the handheld device to control or monitor the electric appliance through the electric appliance remote control apparatus. |
| US09159216B2 |
Hand hygiene dispenser monitor
A monitor is located adjacent to a hand hygiene product dispenser and extends a sensor field adjacent to the hand hygiene product dispenser. The sensor senses activity adjacent to the hand hygiene product dispenser in the sensor field. The monitor determines whether sensed activity indicates a use of the hand hygiene product dispenser and reports a use of the dispenser to a monitoring system when a use is determined. |
| US09159213B1 |
Motion detection method and device
A motion detection method and device are introduced. The motion detection method is adapted to detect accelerations of an intended target along the x-axis, y-axis, and y-axis, respectively, and determine whether the intended target is in a fallen state or is undergoing a falling motion according to a signal strength algorithm and an average force field algorithm. The motion detection device includes an acceleration sensing unit for detecting acceleration along the x-axis, y-axis, and y-axis; a computing unit for determining a falling motion according to the acceleration along the x-axis, y-axis, and y-axis; and a transmitting unit for sending a message pertaining to the falling motion. |
| US09159211B2 |
Remote monitoring system with cellular gateway
A method for monitoring at least one ambient condition at a remote site, the method executed at least in part by a computer, configures at least one sensing device at the remote site according to one or more setup instructions transmitted wirelessly from a host processor at a first site, wherein the configuration associates the at least one sensing device with a personal communications device wherein the at least one sensing device is energizable to wirelessly transmit, to the personal communications device, a sensor signal that is indicative of the at least one ambient condition according to the setup instructions. In response to the transmitted sensor signal, information about the at least one ambient condition displays on the personal communications device that is associated with the at least one sensing device. |
| US09159210B2 |
Method and system for monitoring of friend and foe in a security incident
The present invention is directed to providing a method and system that enables a first responder security officer to take command and control of a building having a security incident. Using the method and system herein, the security officer is able to clearly distinguish the positions of his building entry teams in the building relative to the position of a suspect through a graphic display of friend and foe designation whereupon he can precisely direct a maneuver to close with the suspect. A group of motion sensors are mounted throughout the building to monitor various hallways for movement and collocated RFID readers are interrogated by the security alarm panel software to provide the intelligence for the security alarm control panel to distinguish a police building entry team (Friend) from the suspect (Foe). |
| US09159204B2 |
Cash drawer capable of preventing loss of banknotes
Provided is a cash drawer (10) including a drawer (70) having a banknote container (81) formed therein, and a cash drawer body (20). The cash drawer body (20) includes a drawer accommodating portion (21), a front opening portion (22), a top surface member (40) including a top surface section (41), and a front surface member (50) including a front frame section (51). The front surface member (50) and the top surface member (40) are coupled to each other without forming, at a position between the front surface member (50) and the top surface member (40), a seam extending in a direction being parallel to the top surface of the drawer accommodating portion (21) and intersecting a first direction (X). |
| US09159200B2 |
Progressive wagering game having symbol-triggering award feature
Gaming devices, gaming systems, methods of conducting a wagering game, and computer programs for initiating a wagering game are presented herein. A gaming device is presented that includes a wager input device, a display, and at least one controller. The controller executes the wagering game, which includes first and second progressive awards each associated with a respective symbol-based outcome. Each symbol-based outcome has a respective frequency of occurrence. The controller randomly determines an outcome of the wagering game. The controller initiates a progressive-award-determination sequence in response to displaying the first and/or second symbol-based outcomes. There is a first probability of awarding the first progressive award, and a second probability of awarding the second progressive award. The first initial-award amount is greater than the second initial-award amount, the first frequency of occurrence is lower than the second frequency of occurrence, and the first probability is greater than the second probability. |
| US09159197B2 |
Gaming machine
On a lower image display panel 141, a game result of a game of rearranging symbols 501 is randomly determined. When the game result is winning of a bonus game, a first bonus game in which an in-bonus game such as a free game is executed more than once is executed. When the game result of the in-bonus game in the first bonus game is bonus winning, an indication effect indicating the winning of a second bonus game is executed during the execution of the first bonus game. |
| US09159191B2 |
Mash-up wagering game system
There is provided a mash-up method, system and machine-readable medium. Data associated with a wagering game network is obtained, at a first location. A determination is made whether to mash up the data. A presentation associated with the obtained data is selectively obtained based on the determination. The obtained data is mashed-up with the obtained presentation. The mashed-up presentation is transmitted for display to a display device associated with one or more patrons. |
| US09159189B2 |
Mobile gaming device carrying out uninterrupted game despite communications link disruption
A mobile gaming device may be a player's own personal tablet, smartphone, PDA, etc., with an application program installed via the internet for carrying out a remote gaming session. All gaming functions are carried out by a stationary gaming terminal communicating with the mobile device, such as by using WiFi. The mobile device operates as a user interface. If the communications link is temporarily broken during a game, the mobile device will create the appearance that the game is continuous, such as by continuing to spin reels, until communications are reestablished. The reels will stop once the mobile device receives the final outcome from the gaming terminal. The player may pause the game to temporarily suspend the minimum game frequency rules. The mobile device may switch between gaming terminals. For 3D video, the original format is adjusted for the mobile device. The gaming terminal may be a gaming machine. |
| US09159176B2 |
Vehicle identification apparatus and method
A vehicle identification apparatus mounted in a vehicle provided with a detection unit configured to detect a speed of a first other vehicle and a communication unit configured to receive information indicative of a speed of a second other vehicle from the second other vehicle. In the apparatus, a calculation unit calculates an indicator value indicative of a likelihood that the first and second other vehicles are the same, where the indicator value is defined as a function of the speed of the first other vehicle detected by the detection unit and the speed of the second other vehicle indicated by the information received by the communication unit. A determination unit determines whether or not the first and second other vehicles are the same on the basis of the indicator value calculated by the calculation unit. |
| US09159172B2 |
Equipment system checking apparatus and method
An apparatus and system that ensures that defined equipment systems are monitored and checked before the equipment may be used is described. The invention includes apparatus that encourages the equipment operator to perform specified monitoring checks on specified systems at specified intervals, and requires that the check is done by the operator physically removing a check device such as a crankcase or transmission dipstick, radiator cap, air filter, and so on. Failure to perform the required monitoring task results in the equipment being disabled or locked out so that the operator is unable to use the equipment; for example, a starter motor may be locked out so that the engine cannot start until a specified monitoring check has been completed. |
| US09159170B2 |
System and method for optimal geometry configuration based on parts exclusion
System and method are provided for building and rendering a 3D graphics dataset of an object that consists of multiple parts, wherein the 3D graphics dataset includes a 3D geometry dataset and a configuration file, and in the configuration file each of the multiple parts is identified as used (e.g., visible, actionable) or unused (e.g., not visible, not actionable) in each of multiple display features (e.g., in display states, such as in animations, or in display relationships). The method determines which of the multiple parts are unused in each of the multiple display features and identifies those parts, which are unused in all of the display features, as excluded parts, and saves a list of the identified excluded parts in association with the object. In rendering the object on a display, the method does not load data directed to the excluded parts, to thereby speed up the loading/rendering process. |
| US09159169B2 |
Image display apparatus, imaging apparatus, image display method, control method for imaging apparatus, and program
In a message exchange system, when an imaging apparatus transmits a photograph-attached message, the imaging apparatus transmits a captured image, position and orientation information of the imaging apparatus, feature point information of an object included in the captured image, and three-dimensional structure information of the object to a server. When an image display apparatus receives the message from the server, the image display apparatus corrects the captured image in a direction corresponding to a position and orientation of the image display apparatus based on the position and orientation information of the imaging apparatus, the feature point information of the object, and the three-dimensional structure information of the object. |
| US09159168B2 |
Methods and systems for generating a dynamic multimodal and multidimensional presentation
A computerized method of creating a presentation of multidimensional objects in a multidimensional presentation space. The method comprises providing a core element which applies any of functions on a multidimensional object in a multidimensional presentation space, providing a plurality of adaptation components each contains instructions for converting any media object of another of different media types each to a multidimensional object in the multidimensional presentation space, receiving a media object, identifying a matching adaptation component from the adaptation components according to a respective media type of the media object, converting the media objects into a multidimensional object in the multidimensional presentation space using the matching adaptation component, and applying any of the functions on the multidimensional object, using the core element, according to a user selection. |
| US09159167B2 |
Method and apparatus for complementing an instrument panel by utilizing augmented reality
An approach is provided for complementing various devices and/or instruments by utilizing augmented reality and providing an adaptive user interface to a user at a user device. A user device determines one or more information items associated with at least one instrument panel of at least one vehicle. Then the user device determines one or more representations of the one or more information items and causes, at least in part, a presentation of the one or more information items at the user device, wherein the user device may complement and/or may be substituted for the at least one instrument panel. |
| US09159163B2 |
Top view site map generation systems and methods
Systems and methods for top view site map generation can include receiving a number of non-top view images of an area and generating a top view site map for the area utilizing the number of non-top view images. |
| US09159162B2 |
Method and system for generating a multi-dimensional surface model of a geometric structure
A method of constructing a bounding box comprises: acquiring a set of sensed data points; adding, for each sensed data point, at least one calculated data point; and defining a bounding box containing the sensed and calculated data points. A method of identifying voxels in a voxel grid corresponding to a plurality of data points comprises: calculating, for each data point, a distance between it and each voxel; creating a subset of voxels comprising voxels having a distance from one data point that is less than a predetermined distance; creating another subset comprising those voxels that neighbor a voxel in the first subset; computing, for each voxel in the second subset, a distance between it and each voxel in the first subset; and identifying each voxel in the first subset that is a distance away from each voxel in the second subset that exceeds a predetermined distance. |
| US09159156B2 |
Cull streams for fine-grained rendering predication
One embodiment of the present invention sets forth a technique to perform fine-grained rendering predication using an IGPU. A graphics driver divides a 3D object into batches of triangles. The IGPU processes each batch of triangles through a modified rendering pipeline to determine if the batch is culled. The IGPU writes bits into a bitstream corresponding to the visibility of the batches. Advantageously, this approach to rendering predication provides fine-grained culling without adding unnecessary overhead, thereby optimizing both hardware resources and performance. |
| US09159152B1 |
Mapping between a capture volume and a virtual world in a motion capture simulation environment
A motion capture simulation system can include a capture volume. A participant disposed in the capture volume can be motion captured and immersed into a virtual environment. The virtual environment may be larger in size than the capture volume. In the virtual environment, the participant may be represented by an avatar. The avatar in the virtual environment can be moved in a first direction based on a motion of the participant in the first direction in the capture volume. As the participant moves in the first direction in the capture volume, the participant may approach a boundary of the capture volume, while the participant's avatar may have space to move further in the first direction in the larger virtual environment. Approaching the boundary, the participant can change direction, for example turning around to avoid the boundary. The redirected participant can continue driving the avatar to move in the first direction. |
| US09159150B2 |
Bitmap array for optimally distributing map data content to wireless communications devices
A method of distributing map data from a map server to a wireless communications device entails generating a bitmap array representative of the vector map data for a given zoom level, computing attributes of the bitmap array to determine which map features to retain and which map features to suppress, and then transmitting to the wireless device only the map data for the map features to be retained. By counting the number of bitmap cells representing a polygonal map feature such as a park, lake, or island, the approximate area is quickly estimated. If the area falls below a threshold, the map data for the small polygon is discarded. Similarly, if a polyline map feature overlaps (or is too proximate to) another polyline map feature, one of the polyline map features is discarded. The map data actually transmitted is thus reduced, thereby economizing bandwidth without unduly sacrificing map detail. |
| US09159149B2 |
Visualizing data transfers in distributed file system
Data transfers within and between nodes in a distributed computing environment are visualized. In one aspect, the nodes are represented as geometrical shapes. The first part of the geometrical shape represents logic of the corresponding node. The second part of the geometrical shape represents storage of the corresponding node. A line connecting the first part and the second part represents data transfer between logic of a node and storage of a node. Both inter-node and intra-node transfers may be shown. |
| US09159147B2 |
Method and apparatus for personalized handwriting avatar
A computer-implemented process includes: receiving into a computer memory a response to a generic question not specifically related to handwriting style; converting the response into one or more tags representing handwriting characteristics; selecting a typeface having a handwriting characteristic of one of the tags; receiving a text string to display into a computer memory; and displaying the text string by rendering glyphs from a font file containing glyphs for the selected typeface, after applying random variations to simulate human handwriting variation. |
| US09159146B2 |
Image reconstruction device and image reconstruction method configured to perform iteratively reconstructed image using weight coefficient
To provide an image reconstruction device capable of creating an image with image quality matching the operator's request when a cross-sectional image is reconstructed through a repeated calculation, the image reconstruction device which performs a repeated calculation on the basis of a difference between calculated projection data and measured projection data, the calculated projection data being obtained by performing a forward projection calculation on a reconstructed image which is reconstructed based on the measured projection data, includes an input section to which an image quality parameter which is considered to be important by an operator is input, a weight calculation section that calculates a weighting coefficient on the basis of the image quality parameter, and a repeated calculation section that performs a repeated calculation on the basis of a value obtained by weighting and adding a pixel value obtained in the previous iteration to a pixel value obtained from now using the weighting coefficient. |
| US09159145B2 |
Fast dual contrast MR imaging
The invention relates to a method of MR imaging of at least a portion of a body (10) of a patient placed in an examination volume of a MR device (1). The method comprises the steps of: -subjecting the portion of the body (10) to a first imaging sequence for acquiring a first signal data set (31, 32) from a central portion of k-space, wherein magnetic resonance is excited by means of RF pulses having a large flip angle (α1); -subjecting the portion of the body (10) to a second imaging sequence for acquiring a second signal data set (33, 34) from the central portion of k-space, wherein magnetic resonance is excited by means of RF pulses having a small flip angle (α2); -subjecting the portion of the body (10) to a third imaging sequence for acquiring a third signal data set (35, 36) at least from a peripheral portion of k-space, wherein magnetic resonance is excited by means of RF pulses having an intermediate flip angle (α 3); -reconstructing a first MR image (37) from a combination of the first signal data set (31, 32) and the third signal data set (35, 36) and -reconstructing a second MR image (38) from a combination of the second signal data set (33, 34) and the third signal data set (35, 36). |
| US09159143B2 |
Apparatus and method for generating character collage message
A method and apparatus are provided for generating a character collage message. A character is recognized from an image. A region is extracted from the image to create a character image. The region includes the recognized character. The created character image is stored in a memory. At least the character image is output to an output unit as the character collage message in accordance with input of one or more characters through an input unit. At least one of the one or more characters corresponds to the character image, and the character image is output to the output unit as a substitute for the at least one of the one or more characters. |
| US09159138B2 |
Device and method for dynamic adaptation of spatial resolution for imager fourier transform spectrometers
A device and method for dynamically adapting spatial resolution for imager Fourier transform spectrometers makes it possible to acquire data in interferogram mode and image mode on survey points for an observed scene, each survey point being associated a matrix of macro-pixels and defined by a plurality of zones. For each survey point, analysis of the content of each zone is carried out on the basis of data of the image mode. Classification into clear zone or non-clear zone is carried out as a function of proportion of cloud, and clear-pixel data are generated on the basis of the sum of the data of the macro-pixels of the clear zone class. Survey point data are generated on the basis of the sum of the data of all the macro-pixels of the matrix associated with the survey point. The survey point and clear pixel data streams are transmitted to the ground. |
| US09159136B2 |
Temporal smoothing apparatus and method for synthesizing intermediate image
A temporal smoothing apparatus and method for synthesizing an intermediate image, the apparatus including a disparity vector estimator which receives a previous image and a present images and generates a previous disparity vector and a present disparity vector for every image block of a predetermined size, and a temporal smoothing unit which receives the previous and present images and the previous and present disparity vectors and generates a temporally-smoothed disparity vector. The temporal smoothing unit generates a distinct temporally-smoothed disparity vector for each frame on the basis of a mean absolute difference (MAD) between the previous image and the present image, so that a flickering phenomenon of an intermediate image can be removed without deterioration of image quality by adaptively performing a temporal smoothing process in accordance with types of an image. |
| US09159129B2 |
Generating image-based diagnostic tests by optimizing image analysis and data mining of co-registered images
A method for generating an image-based test improves diagnostic accuracy by iteratively modifying rule sets governing image and data analysis of coregistered image tiles. Digital images of stained tissue slices are divided into tiles, and tiles from different images are coregistered. First image objects are linked to selected pixels of the tiles. First numerical data is generated by measuring the first objects. Each pixel of a heat map aggregates first numerical data from coregistered tiles. Second objects are linked to selected pixels of the heat map. Measuring the second objects generates second numerical data. The method improves how well second numerical data correlates with clinical data of the patient whose tissue is analyzed by modifying the rule sets used to generate the first and second objects and the first and second numerical data. The test is defined by those rule sets that produce the best correlation with the clinical data. |
| US09159127B2 |
Detecting haemorrhagic stroke in CT image data
The invention relates to a system (100) arranged to delineate the acute intracerebral haematoma in non-contrasted CT images in two stages. The first stage, performed by the extraction unit (110), employs an analysis of gray values of the image data in order to extract the candidate region. The candidate region may comprise both an acute haematoma and other regions having similar gray values, e.g., regions resulting from partial volume effects at the interface of the bony structures of the skull and the brain. The novel second stage, performed by the classification unit (120), analyzes spatial features of the candidate region such as, for example, the size, shape, and connectedness to the skull bone of the candidate region. Using spatial features of the candidate region improves the correctness of classification of the candidate region as a true or false acute haematoma. |
| US09159125B2 |
Histogram stretching apparatus and method
There are provided a histogram stretching apparatus and a histogram stretching method. The histogram stretching apparatus includes: an image analyzing unit; a histogram generating unit; an extension level setting; and a histogram stretching unit, wherein the histogram generating unit adds a preset reference image level to the minimum image level to calculate the first image level and subtracts the preset reference image level from the maximum image level to calculate the second image level. |
| US09159124B2 |
Contrast to noise ratio (CNR) enhancer
A method includes enhancing a contrast to noise ratio (CNR) of image data, generating CNR enhanced image data, wherein the CNR enhanced image data has a substantially same image quality as the image data. A computing system (118) includes a computer readable storage medium (122) encoded with computer readable instructions for enhancing a contrast to noise ratio (CNR) of image data and one or more processors (120), which, when executing the computer readable instructions, causes the computing system to enhance the CNR of the image data. A method includes generating CNR enhanced image data, wherein CNR enhanced image data has a substantially same noise level, noise power spectrum, and spatial resolution of the image data. |
| US09159122B2 |
Image domain de-noising
An image data processing component (122) includes algorithm memory (212) including one or more image domain only iterative de-noising algorithms (214) based on the Huber roughness penalty minimization and a processor (206) which de-noises reconstructed image data solely in the image domain based on at least one of the Huber roughness penalty iterative minimization algorithms. |
| US09159120B2 |
Image processing apparatus, image processing method, and storage medium
An image processing unit of an image processing apparatus includes: a pixel value acquiring part that acquires pixel values of new pixels obtained by increasing resolution of a first image, using pixel values of multiple original pixels, of the first image, around a position at which each of the new pixels is disposed; a representative value acquiring part that acquires a representative value of the pixel values of the multiple new pixels arranged in an area in which each of the original pixels is disposed; a correction value acquiring part that acquires a correction value using the pixel value of each of the original pixels and the representative value; and a pixel value correcting part that corrects the pixel value of each of the original pixels using the correction value. The image processing unit performs correction processing for correcting the original pixels is repeated once or at least twice. |
| US09159116B2 |
Adaptive screen interfaces based on viewing distance
Voice commands and gesture recognition are two mechanisms by which an individual may interact with content such as that on a display. In an implementation, interactivity of a user with content on a device or display may be modified based on the distance between a user and the display. An attribute such as a user profile may be used to tailor the modification of the display to an individual user. In some configurations, the commands available to the user may also be modified based on the determined distance between the user and a device or display. |
| US09159106B1 |
Systems and methods for fabricating products on demand
Systems and methods are provided for fabricating products on demand. In some embodiments, a manufacturable model, which may include information about a three-dimensional representation of a product to be fabricated, is received by a user of an electronic system and may be validated by the electronic system. A prototype of the product can be generated based at least in part on the manufacturable model, and the manufacturable model and/or the product can be made available for selection by other users of the system. The product may be fabricated based at least in part on the manufacturable model using, for example, a three-dimensional printer, and may be delivered to users of the electronic system. |
| US09159104B1 |
Computer-implemented methods and computer systems for an electronic financial platform
In some embodiments, the instant invention provides for specifically programming a computer machine to perform at lease: receiving, from a trader, a passive indication of interest (IOI) for a financial instrument, where the passive IOI is a bid or an offer and a resting liquidity; classifying the trader as at least: a trading type that is subject to a decline ratio calculation for crossing the passive IOIs, where the decline ratio calculation identifies how many eligible aggressive IOIs have been previously declined by the trader out of a total number of all eligible aggressive IOIs that were offered to such trader; receiving, from another trader, another IOI that is an aggressive IOI, where the aggressive IOI is available to be immediately crossed at the price; and determining, in real-time, an allocation of the aggressive IOI to the trader submitted the passive IOI based on the decline ratio of the trader. |
| US09159100B2 |
System and method for dynamically managing business machine assets
Systems and methods for managing business machine assets are described. In one configuration, the system analyzes alternate cost structures and provides for alternate asset model replacement suggestions. The asset management system provides for asset comparison analysis. The system uses historical data for a current asset and charts potential replacement asset performance using those historical parameters or predicted or entered future parameters. In an alternative configuration, the compare and contrast report does not include the current asset, but only compares potential replacement assets. |
| US09159096B2 |
Vehicle rental transaction system and method
A vehicle rental transaction system and method which provide a vehicle lot owner with a choice of options for vehicle security and customer convenience. The vehicle rental transaction system includes a computer for identifying a customer as part of a rental transaction involving a vehicle, and for sending a wireless message to the vehicle containing instructions for preparing the vehicle for the customer. Example instructions include, but are not limited to, unlocking doors and a trunk of the vehicle, adjusting power seats and power mirrors in accordance with customer preferences, adjusting climate control settings in accordance with the customer preferences, adjusting radio station settings in accordance with the customer preferences, and adjusting GPS settings in accordance with the customer preferences. |
| US09159087B2 |
Digital flyer system with contextual information
A system for contextualizing a digital flyer is disclosed. The system includes a polygon mapping module for incorporating contextual information in the digital flyer using polygon mapping information, the polygon mapping information comprising a polygon for defining a polygonal area on a source flyer image of the digital flyer, the polygon being tagged with the contextual information, and a flyer data store for storing the tagged polygon. There is also disclosed for displaying the contextualized digital flyer and generating feedback using the contextualized digital flyer. |
| US09159086B1 |
System and method to install mobile applications from a desktop
Systems and methods for Desktop-To-Mobile (D2M) application installation that allows a publisher to extend their relationship with a consumer from the Desktop PC (PC) to a mobile device. In accordance with some implementations, a mobile application store may be used to offer apps on a user's mobile device as a result of a user acceptance of an offer(s) for the apps. The user may install a personal computer (PC)-based application that runs in the background. The PC-based application receives offers to install mobile applications and may use the mobile app store or a PC to install the mobile applications to the user's mobile device. |
| US09159084B2 |
Systems and methods to communication via a merchant aggregator
A computing apparatus configured to determine account numbers of account holders, determine merchant identifiers used to identify respective merchants in authorization requests for transactions between the respective merchants and the account holders, monitor transactions processed by a transaction handler to detect first transactions between the merchants and the account holders, and transmit information about each of the first transactions to a remote computing device in real time as the transaction handler processes the authorization of the respective detected transaction. |
| US09159082B2 |
Active and passive personalization techniques
A method for personalizing content for a particular user in a computing system comprising a user interface configured to display content. The method comprises identifying a long term profile having one or more features in a feature set and a long term level of importance associated with each term in the feature set, identifying a short term profile having one or more features in the feature set and a short term level of importance associated with each term in the feature set, identifying input related to the display of the one or more content items on the user interface, and using the input to modify the short term level of importance and the long term level of importance associated with each term in the feature set to form a modified user interest set. |
| US09159081B2 |
Content item type determination and selection
This specification describes methods, systems, and apparatus, including computer programs encoded on a computer-readable storage device, for determining content item environment types for content items rendered in a web based resource. |
| US09159079B2 |
Product discount system, apparatus and method
A product discount system, apparatus, and method are herein disclosed. A discount server may receive one or more product discounts from a use. A wireless device may retrieve product identification information from a product and generate a discount request message that is transmitted to a discount server. The discount server may identify potential discounts associated with the product identification information and transmit product availability data to the wireless device. The wireless device may notify a user of available product discounts based on the product availability data. Once notified, the user may proceed by redeeming one or more of the available product discounts. |
| US09159078B2 |
Managing identifiers
A method, system or computer usable program product for managing attributes including utilizing a processor to generate a unique mutable identifier in response to a request from an end entity; obtaining a selected set of attributes from the end entity; associating and storing in memory the set of attributes with the unique mutable identifier; and providing the set of attributes associated with the mutable identifier to any application in response to an inquiry utilizing the unique mutable identifier from that application. |
| US09159074B2 |
Tool for embedding comments for objects in an article
Embodiments are directed to managing viewer entered comments about a specific word, phrase, picture, or other multimedia content, such as a picture, sound, or video clip, in an article, document, and/or a web page. A document is presented to a viewer, wherein the document includes special highlighting (e.g., font type/size, underlining, colors, and the like) of certain portions of the document defining one or more target objects. The highlighted portions are determined for the viewer according to a plurality of unique lists of target objects defined by an author of the multimedia content. The viewer selects the target object and a list of recent comments related specifically to the selected target object is displayed. The viewer may also enter comments directly related to the same or a different target object. Advertisements related to the target objects may be displayed to the user when the user selects the target object. |
| US09159073B2 |
System and method for advertisement management
The present invention relates to systems and methods for optimizing and managing advertising campaigns. The method of the present invention comprises storing one or more advertisement data structures associated with an ad group data structure in the ad group data structure. One or more ad group data structures associated with a campaign data structure are stored in an ad campaign data structure. Additionally, one or more ad campaign data structures associated with an advertised property are stored in an account data structure. |
| US09159061B2 |
Method and system for securing payment transactions
A method for facilitating the widespread use of the PIN-Debit payment method for Internet “eCommerce” and mobile payments sales which requires little or no change for the cardholders, merchants, debit networks and card issuers based primarily on the introduction of a layer of middleware and wherein the Debit Networks and Issuing Banks may customize the implementation of the services based on individual strategy and cardholder preferences. |
| US09159055B2 |
Computational systems and methods for identifying a communications partner
Methods, apparatuses, computer program products, devices and systems are described that carry out accepting at least one social network message from at least one member of a network; disambiguating the at least one search term including associating the at least one search term with at least one of network-participation identifier data or device-identifier data; and presenting the sender profile in association with the at least one. |
| US09159052B2 |
Generalizing formats of business data queries and results
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for adapting formats of data queries into a generic format. A query requesting data stored in a business objects data source is received. The query has a generic format and includes parameters that describe a computer interface implementation configured to execute the query to identify the requested data. Based on the one or more parameters, the computer software interface implementation is identified. The interface implementation specifies an interface-specific query format. The query is converted from the generic query format into the interface-specific query format, and provided to the computer software interface implementation. The interface implementation executes the interface-specific query and obtains the requested data in an interface-specific results format. This data is converted into a generic results format, and provided in response to receiving the query. |
| US09159051B2 |
SEF parser and EDI parser generator
A SEF grammar is created to be used with the Java CC program to autogenerate a SEF parser. The SEF parser can be run with specially written X12 code on any SEF file to automatically create an EDI object model for that SEF file. A programmer can then write application code to use the EDI object model to parse an EDI document that the SEF file describes and generate in memory an EDI object model instance for that EDI document. The application code is also used to employ the EDI object model instance to efficiently process the EDI document's EDI transaction. In addition, the application code is used to employ the EDI object model on the EDI object model instance to emit an EDI document for further use. |
| US09159050B2 |
Providing atomicity for a unit of work
A method for providing atomicity for a unit of work involving a plurality of participants, the method comprising the steps of: sending a prepare request to at least one participant, wherein the request comprises data required for recovery purposes of the unit of work; and on recovery of the unit of work, recovering the unit of work comprising: obtaining the data from the at least one participant; and using the obtained data to recover and preserve the atomicity of the unit of work. |
| US09159032B1 |
Predicting arrival times of vehicles based upon observed schedule adherence
A method and system for determining real-time delay information in a transportation system. Historical operational information about the transportation system, including data related to a plurality of arrival events corresponding to one or more stops within the transportation system is received and a dependency graph is built based upon the historic information. The dependency graph defines relationships that exist in the transportation system between the plurality of arrival events, each of the relationships defining a specific dependent relationship between at least two of the arrival events. Delay dependency values are fitted into the dependency graph, each of the delay dependency values being associated with one of the plurality of relationships and defining a specific dependency value associated with that relationship. Predictive delay information is determined based upon the fitted dependency graph for one or more of the arrival events based upon current operating information. |
| US09159031B2 |
Predicting audience response for scripting
Various technologies described herein pertain to automatic prediction of an anticipated audience response for scripting. A sub-document unit can be received, where the sub-document unit can be part of a script. The sub-document unit, for example, can be a sentence, a paragraph, a scene, or substantially any other portion of the script. Content of the sub-document unit and a context of the sub-document unit can be analyzed to extract features of the sub-document unit. A predictive model can be employed to predict an anticipated audience response to the sub-document unit based upon the features of the sub-document unit. Moreover, the anticipated audience response to the sub-document unit predicted by the predictive model can be output. |
| US09159030B1 |
Refining location detection from a query stream
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for determining geographic locations of devices. One of the methods includes obtaining an estimated user location associated with each respective IP address block based on observed events from the IP address block; obtaining an estimate of a probability model p(ev|loc), the probability model p(ev|loc) including a respective probability distribution of interest locations for each of multiple user locations; wherein obtaining the estimate of the probability model p(ev|loc) includes calculating p(ev|loc) from a p(zone|loc) matrix and a p(ev|zone) matrix; and using the estimate for the probability model p(ev|loc) and the observed events to calculate an estimate for multiple probability distributions X(loc) associated with a respective IP address block. |
| US09159028B2 |
Computing regression models
Provided are techniques for computing a task result. A processing data set of records is created, wherein each of the records contains data specific to a sub-task from a set of actual sub-tasks and contains a reference to data shared by the set of actual sub-tasks, and wherein a number of the records is equivalent to a number of the actual sub-tasks in the set of actual sub-tasks. With each mapper in a set of mappers, one of the records of the processing data set is received and an assigned sub-task is executed using the received one of the records to generate output. With a single reducer, the output from each mapper in the set of mappers is reduced to determine a task result. |
| US09159027B2 |
Adaptive experimentation method and system
A computer-implemented adaptive experimentation method and system is described that automatically selects and executes information gathering actions. The adaptive experimentation method and system integrates value of information considerations, experimental design, and inferences from experimental results. The experimental results may include behaviors of users of a computer-based system. The process enables an automatic, adaptive process for attaining additional information and applying the attained information in making subsequent experiment decisions. |
| US09159026B2 |
Method and apparatus for model based decision making
The invention relates to an organization model and the method of generation of the same and use of the same, wherein the model is provided to be used to assess the current performance of an organization, or part thereof, with regard to its objectives and to guide future decision making by projecting likely future outcomes of proposed changes to the organization, based on cause-effect reasoning which can include a probabilistic layer, said model being constructed in part using available domain knowledge. The model can be also be used to check the validity and success of historical decisions against the current situation, to guide model review and future decision making. |
| US09159024B2 |
Real-time predictive intelligence platform
A real-time predictive intelligence platform comprises: receiving from a user through a meta API definitions for predictive intelligence (PI) artifacts that describe a domain of an online transaction system for least one business entity, each of the PI artifacts including types, component modules and behavior bundles; exposing an entity API based on the PI artifacts for receiving entity events from the online transaction system comprising records of interactions and transactions between customers and the online transaction system; responsive to receiving an entity event through the entity API, executing the component modules and behavior bundles to analyze relationships found between past entity events and metrics associated with the past entity events, and computing a probabilistic prediction and/or a score, which is then returned to the online transaction system in real-time; and processing entity event replicas using modified versions of the PI artifacts for experimentation. |
| US09159022B2 |
System, method and program product for automatically supplying missing parameters for matching new members of a population with analogous members
A population comparison system, method and a computer program product therefor. A stored list of population members, e.g., hydrocarbon reservoirs, includes parameters for corresponding known characteristics and analogous members for each member. A new population member input receives new member descriptions including parameters for each respective new member. A parameter extraction system automatically extracts an estimated value for each missing key parameter, providing a supplemented description. An analogous member selector automatically selects a subset of listed population members as analogous members for each new population member responsive to the supplemented description. |
| US09159021B2 |
Performing multistep prediction using spatial and temporal memory system
Embodiments relate to making predictions for values or states to follow multiple time steps after receiving a certain input data in a spatial and temporal memory system. During a training stage, relationships between states of the spatial and temporal memory system at certain times and spatial patterns of the input data detected a plurality of time steps later after the certain time steps are established. Using the established relationships, the spatial and temporal memory system can make predictions multiple time steps into the future based on the input data received at a current time. |
| US09159020B2 |
Multiplexing physical neurons to optimize power and area
Embodiments of the invention relate to a multiplexed neural core circuit. One embodiment comprises a neural core circuit including a memory device that maintains neuronal attributes for multiple neurons. The memory device has multiple entries. Each entry maintains neuronal attributes for a corresponding neuron. The core circuit further comprises a controller for managing the memory device and processing neuronal firing events targeting each neuron. The controller multiplexes computation and control logic for the neurons. In response to neuronal firing events targeting one of the neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates the firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron. |
| US09159018B2 |
Method of making conductive patterns
A method of forming an electrically-conductive pattern includes selectively electroplating the top portions of a substrate that corresponds to the pattern, and separating the conductive pattern from the substrate. The electroplating may also include electrically connecting the conductive pattern to an electrical component. Conductive ink, such as ink including carbon particles, may be selectively placed on the conductive substrate to facilitate plating of the desired pattern and/or to facilitate separation of the pattern from the substrate. An example of a conductive pattern is an antenna for a radio-frequency identification (RFID) device such as a label or a tag. One example of an electrical component that may be electrically connected to the antenna, is an RFID strap or chip. |
| US09159012B2 |
RFID condition latching
A passive radio-frequency identification (RFID) system has an RFID reader that communicates with and provides power to an RFID tag. The RFID tag has an RFID integrated circuit chip that contains a memory device for storing information to be transmitted to the RFID reader, and energy storage device that stores energy for powering the integrated circuit chip. In the event that the RFID tag is activated during periods when the RFID integrated circuit chip is not receiving sufficient energy from the RFID reader, then either an energy storage device is provided to allow the activation event to be recorded at the RFID integrated circuit chip, or a memory device is provided that senses and records the activation event and communicates this activation event once power has been restored. |
| US09159007B2 |
Network system, network apparatus and start indicating apparatus
A network apparatus transmits the completion notice of the start to a start indicating apparatus in a case of completing a start processing to be executed according to a start indication. In a case of monitoring and receiving the receipt of the completion notice of the start transmitted from the network apparatus, the start indicating apparatus transmits the completion notice of the start with respect to a terminal apparatus through a repeating apparatus. |
| US09159006B2 |
System and method for document transmission from a computing device to a portbale electronic device
The present disclosure provides methods and apparatus for managing a document. An example aspect provides a method of requesting a document to be displayed at a portable electronic device, including: installing at a computer a printer driver for displaying documents at the portable electronic device; creating an association of a portable account identifier with a unique identifier of the portable electronic device; using the printer driver and the association, to transmit the document to the portable electronic device over a network; and transmitting from the computer the document. |
| US09159004B1 |
Image forming apparatus that facilitates early elimination of failure
An image forming apparatus includes an internal device that executes a job, a controller, a user management unit, a lock requesting unit, and an unlock requesting unit. The controller suspends the execution of the job when the controller detects a predetermined failure in the internal device during the execution of the job, and resumes the suspended job or starts execution of a next job when the controller detects an elimination of the failure. The user management unit specifies identification information of a user mobile device associated with a user. The lock requesting unit transmits a lock request with the identification information to a predetermined server when the controller has suspended the job. The unlock requesting unit transmits an unlock request with the identification information to the predetermined server when the controller has resumed the suspended job or when the controller has started the execution of the next job. |
| US09159002B2 |
Recording sheet transport apparatus and printing system incorporating same
A relay transport apparatus (400) includes a first transport path, a plurality of first transport sections (63), a plurality of driving sections (64), and a drive transmission section (65). The first transport path is formed so as to couple a carry-in port and a carry-out port. The first transport path includes a plurality of segments (S2a and S2b). The plurality of first transport sections (63) are disposed along the first transport path. The first transport sections are configured to transport the paper sheet carried in from the carry-in port to the carry-out port along the first transport path. The plurality of driving sections (64) correspond to the respective segments. The plurality of driving sections (64) are configured to drive the first transport section in the corresponding segment. The drive transmission section (65) drives the plurality of first transport sections based on an output from a predetermined one driving section (64a) when only the predetermined one driving section operates among the plurality of driving sections. The drive transmission section (65) drives the plurality of first transport sections based on outputs from the corresponding driving sections when the plurality of driving sections operate. |
| US09158999B2 |
Printing apparatus, method of changing layout, and storage medium
Logical pages are laid out on a physical page according to setting of a multipage printing condition. When a user drags a logical page, a layout of logical pages is changed based on an area to which the logical page is dragged. |
| US09158998B2 |
Template processing program and template processing method
The disclosure discloses a non-transitory computer-readable recording medium, storing the template processing program for executing steps on a control device of an operation terminal. The terminal is connected with a print label producing apparatus using a template t, and with a server configured to store a plurality of language versions of mutually different language types for the template. The terminal comprises a display device, the control device, and a memory. The steps comprises a language selection receiving step for receiving a selection of at least one language type, a downloading step for downloading from the server at least one template that contains the language version of the language type, a combined file generating step for generating a combined file that combines a plurality of language versions using mutually different language types into a single file, and a storing step for storing the combined file in the memory. |
| US09158991B2 |
Image-feature detection
An embodiment is a method for detecting image features, the method including extracting a stripe from a digital image, the stripe including of a plurality of blocks; processing the plurality of blocks for localizing one or more keypoints; and detecting one or more image features based on the one or more localized keypoints. |
| US09158987B2 |
Image processing device that separates image into plural regions
An image processing device includes: a processor; and a memory storing computer-readable instructions therein. The computer-readable instructions, when executed by the processor, causes the image processing device to perform: a first separation to separate a target image represented by target image data into a plurality of regions that include a first region and a second region different from the first region; a second separation to separate the first region into a plurality of sub-regions and to separate the second region into a plurality of sub-regions; and generating a consolidated region by consolidating at least two sub-regions among the plurality of sub-regions separated from the first and second regions. |
| US09158985B2 |
Method and apparatus for processing image of scene of interest
A method for processing an image of a scene of interest includes receiving an original target image of a scene of interest at an image processing device from an image source device, the original target image exhibiting shadowing effects associated with the scene of interest when the original target image was captured, the original target image comprising a plurality of elements and representing an instantaneous state for the scene of interest, pre-processing the original target image using a modification identification algorithm to identify elements of the original target image to be modified, and generating a copy mask with a mask region representing the elements to be modified and a non-mask region representing other elements of the original target image. An image processing device for processing an image of a scene of interest and a non-transitory computer-readable medium are also provided. |
| US09158983B2 |
Microform word search method and apparatus
An apparatus for searching for expressions that appear on a microform medium, the apparatus comprising a microform imager including a sensor for generating digital microform images of one segment of the microform medium at a time, a display screen; and a processor programmed to, while the microform imager is generating a digital microform image: (i) use the digital microform image generated by the microform imager to drive the display screen, (ii) search the digital microform image presented via the display screen for instances of a search expression and (iii) visually distinguish the located search expressions in the digital microform image presented via the display screen. |
| US09158981B2 |
Method and system for evaluating the quality of a rendered image
Techniques for evaluating the quality of a an image on a printing surface. The techniques generally includes receiving a first signal corresponding to the original image and a second signal corresponding to the rendition of the original image. The techniques further include filtering both signals using a common set of filters to extract at least partial contours of the original image and of its rendition and to determine a quality value of the rendition of the original image based on a comparison between the filtered images in the frequency domain. |
| US09158979B2 |
Vehicle vicinity monitoring device
When a pedestrian candidate and an animal candidate that are detected from an image imaged by an imaging device mounted in a vehicle are in a specified relationship in said image (such as existing nearby), the animal candidate is considered to be an item related to the pedestrian candidate, in other words, a pair object. Attention-arousing output directed at the animal candidate configuring the pair object is not generated. Therefore, a vehicle vicinity monitoring device is provided that reduces the frequency of attention-arousing directed at an animal (for ex-ample, a small animal such as a dog) being walked by a human. |
| US09158978B2 |
Vehicle environment classifying safety system for a motor vehicle
A safety system for a motor vehicle having a sensing arrangement (11) providing sensor signals related to the surrounding environment of the vehicle, at least one safety means (13, 14, 15) for an occupant of the vehicle, and a control means (22) adapted to control the safety means (13, 14, 15) depending on signals from the sensing arrangement (11). The safety system (10) has an environment classifying means (23) adapted to classify the surrounding environment of the vehicle into different predetermined categories on the basis of signals from the sensing arrangement (11), and to adjust the control means (22) depending on the vehicle environment category determined by the environment classifying means (23). |
| US09158976B2 |
Efficient retrieval of anomalous events with priority learning
Local models learned from anomaly detection are used to rank detected anomalies. The local models include image feature values extracted from an image field of video image data with respect to different predefined spatial and temporal local units, wherein anomaly results are determined by failures to fit to applied anomaly detection module local models. Image features values extracted from the image field local units associated with anomaly results are normalized, and image feature values extracted from the image field local units are clustered. Weights for anomaly results are learned as a function of the relations of the normalized extracted image feature values to the clustered image feature values. The normalized values are multiplied by the learned weights to generate ranking values to rank the anomalies. |
| US09158973B1 |
Temporal constraint relationship for use in an image segregation for frames of a video
A soft, weighted constraint imposed upon image locations temporally spaced in frames of a video, can be used to provide a more accurate segregation of an image into intrinsic material reflectance and illumination components. The constraint is arranged to constrain all color band variations between the image locations into one integral constraining relationship. |
| US09158967B2 |
Systems and methods for mobile image capture and processing
In various embodiments, methods, systems, and computer program products for processing digital images captured by a mobile device are disclosed. Myriad features enable and/or facilitate processing of such digital images using a mobile device that would otherwise be technically impossible or impractical, and furthermore address unique challenges presented by images captured using a camera rather than a traditional flat-bed scanner, paper-feed scanner or multifunction peripheral. |
| US09158958B2 |
Signal strength enhancement in a biometric sensor array
A biometric imager may comprise a plurality of sensor element traces formed in or on a sensor substrate which may comprise at least a portion of a display screen defining a biometric sensing area and forming in-active pixel locations; an auxiliary active circuit formed in or on the sensor substrate on the periphery of the biometric sensing area and in direct or indirect electrical contact with the sensor element traces; and providing a signal processing interface to a remotely located controller integrated circuit. The sensor element traces may form a portion of one dimensional linear sensor array or pixel locations in a two dimensional grid array capacitive gap biometric imaging sensor. The auxiliary circuit may provide pixel location selection or pixel signal amplification. The auxiliary circuit may be mounted on a surface of the display screen. The auxiliary circuit further comprising a separate pixel location selection controller circuit. |
| US09158954B2 |
Systems and methods to read machine-readable symbols
Systems and methods of reading machine-readable symbols are provided. A method of reading a machine-readable symbol includes emitting by a first source outgoing electromagnetic energy comprising wavelengths in a first portion of the electromagnetic spectrum towards a target comprising the machine-readable symbol. Incoming electromagnetic energy comprising wavelengths in a second portion of the electromagnetic spectrum reflected or emitted by the machine-readable symbol are discerned by a global shutter sensor after transmission through at least a first portion of a color filter array having a plurality of portions. |
| US09158947B2 |
Mapping the determined RFID priority level of an RFID first network to a priority level corresponding to a second network to provide quality of service to RFID
Embodiments of the present invention include systems and methods for providing Quality of service to RFID. In one embodiment the present invention includes a method of providing quality of service in an RFID network comprising storing RFID priority information corresponding to the RFID network, wherein the RFID network comprises one or more tags and one or more readers mapping the RFID priority information into priority information corresponding to a second network. |
| US09158946B2 |
Locker system using barcoded wristbands
A locker system includes one or more banks of electronic lockers. Each locker has a door lock that releasably retains the door in the closed position. The locker system also includes at least one barcode scanner selectively unlocks the door of at least one of the lockers. A locker manager is coupled to each of the electronic lockers via an electronic network. The locker manager stores a list of unique barcodes that are each associated with a locker rental plan including at least one locker account. Each locker account includes an activation indication, a use indication, a locker type indication, and a duration. The unique barcodes are printed or otherwise included on wristbands, which may be scanned at the barcode scanner to gain access to one or more of the lockers. |
| US09158945B2 |
Defining a radio frequency identification read area
Defining a radio frequency identification read area includes a radio frequency identification (RFID) reader operable to read RFID tags within a specified read area. An RFID transmitter is coupled with the RFID reader and is operable to radiating a modulated carrier in an area adjacent to the specified read area. The RFID reader controls the RFID transmitter to transmit the modulated carrier during a preamble transmission of the RFID reader to prevent any RFID tags in the adjacent area from recognizing an interrogation signal from the RFID reader. |
| US09158942B2 |
Securing display output data against malicious software attacks
Systems, apparatus and methods are described including operations for securing display output data against malicious software attacks. |
| US09158936B2 |
Method of and apparatus for storing data
An electronic device for storing data content by storing at least a portion of the data content in a rewritable memory device by storing an n bit count value associated with the status of the data content in a one time programmable memory. The n bit count value is written to the secure memory device along with the corresponding data content. Then the n bit count value is incremented and stored in the one time programmable memory each time there is a modification of the data content in the rewritable memory device. The number of bits of the one time programmable memory may correspond to the number of potential modifications of the stored data content. |
| US09158934B2 |
System and method for network administration and local administration of privacy protection criteria
Cookie files are screened in a client machine, wherein a cookie file includes a cookie file source. A request from a subscriber is received at a server to send a list of untrusted cookie file sources to the client machine. The list of untrusted cookie file sources is downloaded from the server to the client machine. The downloaded list of untrusted cookie file sources is used to detect cookie files received at the client machine from cookie file sources on the downloaded list by comparing the cookie file source of any received cookie file to the untrusted cookie file sources on the downloaded list. |
| US09158928B2 |
Image management system and image management apparatus
According to an aspect of the present invention, an image management apparatus includes: an authentication processing unit which authenticates access according to an authentication request; an information-displayed-on-apparatus receiving unit which receives displayed-on-apparatus information acquired based on information transmitted to and displayed on an image recipient apparatus in association with transmission of the authentication request; a ticket processing unit which generates ticket link information by generating ticket information for identification of the authentication and linking a user identifier of an authenticated user and a device identifier, which is acquired using the displayed-on-apparatus information received in association with the authentication, of the image recipient apparatus to the ticket information; and an image providing unit which, upon receiving an image request from the image recipient apparatus, acquires the device identifier of the image recipient apparatus and checks an authentication status of the user based on the ticket information linked to the device identifier. |
| US09158924B2 |
Information processing apparatus and information processing method
An information processing apparatus that processes data to be protected is provided. The information processing apparatus includes a first storage unit, a second storage unit, and a cache control unit configured to cache data stored in the first storage unit into the second storage unit. The cache control unit is configured to lock a cache region in the second storage unit to thereby prevent cache data of the stored data from being written back into the first storage unit, the cache data being obtainable from the cache region in the second storage unit in which the stored data is cached, and write the data to be protected different from the stored data into the cache region in the second storage unit, after the cache region in the second storage unit is locked. |
| US09158922B2 |
Method, system, and computer-readable medium for automatically mitigating vulnerabilities in source code
A method for automatically mitigating vulnerabilities in a source code of an application is provided in the present invention. The method includes the following steps. First, the source code is complied, and a path graph is built according to the compiled source code. The path graph includes a plurality of paths traversing from sources to sinks, and each of the paths includes a plurality of nodes. Then, at least one tainted path is identified by enabling a plurality of vulnerability rules. Each of the at least one tainted path corresponds to a vulnerability, and each of the at least one vulnerability corresponds to a sanitization method. Then, the at least one vulnerability is determined if it is mitigable. If the at least one vulnerability is mitigable, the at least one vulnerability is mitigated automatically. Furthermore, the method may be implemented as a system and a computer program product. |
| US09158913B2 |
Managing virtual machines using owner digital signatures
A computer system is disclosed that includes a host operating system and a virtual hypervisor that operates under management of the host operating system to control operations of virtual machines operating under management of the virtual hypervisor. The virtual hypervisor provides an interface between the virtual machines and the host operating system. A signing component generates digital signatures which identify owners of the virtual machines and associates the digital signatures with the virtual machines. A signature validation component determines the owners of the virtual machines using the digital signatures and responsive to occurrence of defined events. Related methods and computer program products for operating computer systems are also disclosed. |
| US09158906B2 |
Authenticating a device and a user
A method of authenticating a device and a user comprises receiving a user input, generating a first key from the user input, performing a physical measurement of the device, obtaining helper data for the device, computing a second key from the physical measurement and the helper data, and performing an operation using the first and second keys. In a preferred embodiment, the method comprises performing a defined function on the first and second keys to obtain a third key. Additionally security can be provided by the step of receiving a user input comprising performing a biometric measurement of the user and the step of generating a first key from the user input comprises obtaining helper data for the user and computing the first key from the biometric measurement and the user helper data. |
| US09158905B2 |
Method for computer startup protection and system thereof
A method for computer startup protection, wherein the method includes steps that a computer powers up, and loads and executes a dynamic password computer startup protection program; the dynamic password computer startup protection program receives a password entered by a user; the password is obtained by the user via sending a dynamic password generating command to a dynamic password device; then the dynamic password computer startup protection program determines whether the password is valid, if so, the dynamic password computer startup protection program loads a computer startup program of the computer; otherwise the dynamic password computer startup protection program does not load the computer startup program of the computer. A system includes a computer and a dynamic password generating device. |
| US09158899B2 |
Terminal apparatus with DRM decoding function and DRM decoding method in terminal apparatus
Provided is a terminal apparatus with a DRM decoding function and a DRM decoding method in a terminal apparatus. The terminal apparatus with a DRM decoding function comprises a native unit which is provided with a local file memory for storing DRM media content data and an application program for driving a media device player using an operating system; and a DRM decoding unit which reads the DRM media content data from the local file memory using a URL path for web server, when it is required from the application program to reproduce the DRM media content data, and decodes the read DRM media content data, and provides the decoded DRM media content data to the media device player. Therefore, it is possible to reproduce the DRM media content data in the terminal apparatus without the exclusive DRM decoding module. |
| US09158896B2 |
Method and system for generating a secure key
A method, system on a chip, and computer system for generating more robust keys which utilize data occupying relatively small die areas is disclosed. Embodiments provide a convenient and effective mechanism for generating a key for use in securing data on a portable electronic device, where the key is generated from repurposed data and a relatively small amount. A multi-stage encryption algorithm may be performed to generate the key, where the first stage may include encrypting the secure data, and the second stage may include encrypting the result of a logical operation on the encrypted secure data with a unique identifier of the portable electronic device. A secret key may be used as the encryption key for each stage. The result of the second encryption stage may include the generated key which may be used to perform subsequent operations on the portable electronic device. |
| US09158895B2 |
Providing a managed browser
Methods, systems, computer-readable media, and apparatuses for providing a managed browser are presented. In various embodiments, a computing device may load a managed browser. The managed browser may, for instance, be configured to provide a managed mode in which one or more policies are applied to the managed browser, and an unmanaged mode in which such policies might not be applied and/or in which the browser might not be managed by at least one device manager agent running on the computing device. Based on device state information and/or one or more policies, the managed browser may switch between the managed mode and the unmanaged mode, and the managed browser may provide various functionalities, which may include selectively providing access to enterprise resources, based on such state information and/or the one or more policies. |
| US09158894B2 |
Apparatus and method for analyzing rule-based security event association
An apparatus for analyzing rule-based security event association includes a rule management unit to check whether an security event is a candidate security event requiring association analysis, and an event management unit to analyze the candidate security event and check whether the analyzed security event is the candidate security event requiring association analysis. An association processing unit analyzes whether an association event of a rule DB corresponding to a user ID of the candidate security event is matched with a user event list to generate an association analysis result. |
| US09158892B2 |
Cabinet with remote integration
Devices, systems, and methods are described for remotely managing items that are configured to be stored in at least one dispensing device. This includes receiving user identification information at a host computer system from an electronic device that is remotely located from the dispensing device. This also includes transmitting from the host computer system to the electronic device a disposition of at least one item, wherein the at least one item is associated with a patient. Further, this includes receiving, at the host computer system from the remote electronic device, information about the item originating from the dispensing device, wherein the information includes a further disposition of the item. |
| US09158890B2 |
Mobile applications and methods for conveying performance information of a cardiac pacemaker
Devices, systems, and methods are disclosed for relaying information from a cardiac pacemaker to an external device. Logic on the pacemaker modulates a heartbeat clock of the pacemaker to encode information onto a blood pressure sequence. This is accomplished by adding or subtracting a small subinterval to or from a pulse repetition interval of the pacemaker. A muscle stimulator beats the heart according to the modulated sequence. A monitoring device external to the body monitors the blood pressure to retrieve the encoded information, or message. The encoded information is then decoded to determine the information in the message. This information may concern the pacemaker as well as other devices within the body that are in communication with the pacemaker such as blood monitors, etc. Since the message is conveyed via simple modulation of the heart beat intervals, no separate transmitter is required in the pacemaker which would otherwise increase cost and decrease battery life. |
| US09158887B2 |
System and method for retrieving and processing metadata
A system and method of retrieving metadata, the method comprising: in response to a request from a client for metadata for a set of DICOM instances, loading n DICOM instances of the set of requested DICOM instances; comparing the metadata of the n loaded DICOM instances; generating a common set of values based on the comparison of the n loaded DICOM instances; streaming the common set of values to the client; determining per-instance data for each of the n loaded DICOM instances, the per-instance data being a difference between the metadata of a DICOM instance and the common set of values; transmitting the per-instance data of the loaded DICOM instances to the client; loading additional DICOM instances of the set of requested DICOM instances; determining per-instance data for each of the additional DICOM instances; and transmitting the per-instance data of the additional DICOM instances to the client. |
| US09158886B1 |
Method of designing fin-based transistor for power optimization
A method of designing a fin-based transistor for power optimization includes following steps. A planar field-effect transistor (planar-FET) design including a plurality of planar semiconductor devices is received. An initial fin field-effect transistor (FinFET) design including a plurality of fin-based semiconductor devices corresponding to the planar semiconductor devices is generated. A timing analysis is performed to the initial FinFET design to recognize at least a critical path and at least a non-critical path in the initial FinFET design. The non-critical path includes at least one of the fin-based semiconductor devices. The fin-based semiconductor device on the non-critical path is adjusted and thus a refined FinFET design is generated. A current required by the refined FinFET design is lower than a current required by the initial FinFET design. |
| US09158885B1 |
Reducing color conflicts in triple patterning lithography
Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable. |
| US09158884B2 |
Method and system for repairing wafer defects
A method of lithographic defect detection and repair is disclosed. In an exemplary embodiment, the method of patterning a workpiece comprises receiving a mask for patterning a workpiece. The mask is inspected for defects, and a mask defect is identified that is repairable in the workpiece. The workpiece is lithographically exposed using the mask, and a defect is repaired within the workpiece based on the identified mask defect. The method can further comprise comparing defects across the workpiece to determine repeating defects and determining a spacing between the repeating defects. A distance between a first focal point and a second focal point of a lithographic system can be configured to correspond to the spacing between the repeating defects. Thus, a first repeating defect and a second repeating defect can be repaired concurrently. |
| US09158882B2 |
Automatic pipelining of NoC channels to meet timing and/or performance
Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels. |
| US09158880B2 |
Layout method for printed circuit board
A layout method for a printed circuit board (PCB) is provided. A memory type of a dynamic random access memory (DRAM) to be mounted on the PCB is obtained. A module group is obtained from a database according to the memory type of the DRAM, wherein the module group includes a plurality of routing modules. A plurality of PCB parameters are obtained. A specific routing module is selected from the module group according to the PCB parameters. The specific routing module is implemented into a layout design of the PCB. The specific routing module includes layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip. |
| US09158878B2 |
Method and apparatus for generating circuit layout using design model and specification
According to one embodiment, a method is disclosed for designing an integrated circuit by a computer including an input unit, a memory unit, a calculating unit, and an output unit. The method can include storing a design model in the memory unit. The design model has parameters of physical quantities of active elements, passive elements, and an interconnection pattern included in the integrated circuit. The design model has an algorithm generating a circuit layout from values of the parameters. The method can include inputting the values of the parameters based on a first design specification of the integrated circuit by the input unit, generating a first circuit layout of the active elements, the passive elements, and the interconnection pattern by the calculating unit using the design model from the values of the parameters received by the input unit, and outputting the first circuit layout by the output unit. |
| US09158876B2 |
Optimizing lithography masks for VLSI chip design
In one embodiment, a computer-implemented method includes accessing mask input data. The mask input data includes a mathematical representation of a mask in a mask representation space, where the mask is configured to create an integrated circuit microprocessor. A set of values is obtained based on a derivative of the mask input data. The set of values is optimized, by a computer processor, in a derivative domain to obtain optimized mask data. The optimized mask data is transformed into the mask representation space to obtain printable mask output data. |
| US09158874B1 |
Formal verification coverage metrics of covered events for circuit design properties
A computer-implemented method and non-transitory computer readable medium for circuit design verification. A property defined for a circuit design is received, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property. Bounded reachability analysis is performed for the circuit design against a set of cover items. The set of cover items are classified into classified cover items based on results of the reachability analysis. Coverage information is generated indicating an amount of formal verification coverage provided by the property. The coverage information is generated based on a first set of the classified cover items that correspond to the cone of influence of the property and that are reached within a particular bound during the reachability analysis. |
| US09158872B2 |
Apparatus, systems, and methods for increasing airflow through induction motors
Induction motors may have a rotor core assembly that includes a plurality of rotor laminations having an arrangement of vents therein. The arrangement of vents may provide increased airflow through the induction motor without adversely affecting the electromagnetic properties of the motor. The arrangement of vents includes first and second circular rows of vents, wherein each vent of the first row may be radially aligned with a respective vent of the second row, and each radially aligned pair of first and second row vents may be radially aligned with a respective conductor bar slot in the rotor lamination. The number of rotor bar slots may equal the number of first row vents and the number of second row vents. Systems and methods of facilitating ventilation in an induction motor are provided, as are other aspects. |
| US09158870B2 |
Network element consolidation for rapid discrete network simulations
Systems and methods are provided for modeling and simulating a communication network operating under at least one communication protocol, which supports a Smart Grid electricity network. Communication performance data of the communication network are generated by a processor based on operating behavior of the Smart Grid with a plurality of assets under a first condition. Devices in the Smart grid are grouped in bins for rapid modeling. One or more different configurations of the communication network are entered into the processor and related performance data is also generated. Network configurations are compared based on the generated performance data which may include end-to-end delay and reception rate. Processor based systems to perform modeling methods are also provided. |
| US09158865B2 |
Process, program and apparatus for displaying an assembly of objects of a PLM database
This invention is directed to a process, computer program and apparatus for displaying an assembly of objects of a product lifecycle management database. The method according to the invention aims at providing an access to the database, selecting the assembly of objects in the database, identifying a plurality of viewpoints on said assembly, retrieving from the database a set of objects of said assembly according to the plurality of identified viewpoints, computing a model of said assembly for all the retrieved objects of the set of objects, and displaying a view of the model, any displayed views being computed locally starting from the objects retrieved at the retrieving step. |
| US09158859B2 |
Segment matching search system and method
A planning and search system are described wherein a graph search and segment matching are used to handle very large searches at a higher speed. |
| US09158858B2 |
System and method for managing XML document management server history
A method for managing an Extensible Markup Language (XML) Document Management (XDM) Server history is provided. The method includes receiving, by the XDM Server, XML Documents and Filtering Rules within a filter body in an XCAP request from a first XDM Client Device, wherein the Filtering Rules define operation information performed on specific XML Documents to store as history information and further define when to store the history information of the XML Documents; storing the XML Documents and the Filtering Rules on the XDM Server; and when a second XDM Client Device has access to perform one or more operations on the XML Documents stored in the XDM Server, storing, by the XDM Server, the history information of the XML Documents according to the Filtering Rules by the XDM Server and the one or more operations performed. |
| US09158857B2 |
Identifying landing pages for images
Methods, systems, and apparatus for identifying landing pages for images. In one aspect, a method includes, for each image of a plurality of images, identifying web pages that each include the image, and, for each of the web pages, receiving a web score generated by a ranking algorithm. The web page having a web score indicating a highest importance relative to other web pages is selected, sets of similar images are determined from the images included in the selected web pages, and each set of similar images includes different images. For each set of similar images, an image is selected based on the selected web page that includes the selected image having a highest web score of the set, and the selected web page that includes the selected image is identified as a landing page for an image search result. |
| US09158856B2 |
Automatic generation of tasks for search engine optimization
A method and a device for search engine optimization, that receives an identifier that identifies a domain, one or more keywords for analysis relative to a search engine, and search engine usage data, for each received keyword, gathering search engine results data, for at least one received keyword, mapping the at least one keyword to at least one web page within the identified domain, said mapping based on at least one of said search engine usage data and said search engine results data, and for at least one of the received keywords, generating at least one instruction to modify a web page element in a web page to which the at least one received keyword is mapped. |
| US09158853B2 |
Computerized internet search system and method
The present invention provides a system and method that can search social media and Internet websites, and can analyze and display the results according to a variety of criteria including virality on social media websites. The results are presented in a user friendly format such as a magazine, newsletter, newspaper, or scrapbook. |
| US09158852B2 |
Geographical area correlated websites
A system, method and/or software for using overlap between a first website area-of-interest map, associated with a first website, and a searcher area-of-interest map to help prioritize the websites returned by a search engine search. The area-of-interest maps are made up of geographic pixels respectively assigned with area-of-interest values. Overlap area is determined by comparing, on a pixel-by-pixel basis, corresponding pixels of the searcher area-of-interest map and the first website area-of-interest map to determine overlap pixels where the following conditions hold: (i) the first website area-of-interest map has a non-zero interest value, and (ii) the searcher area-of-interest map has a non-zero interest value. |
| US09158850B2 |
Personal trends module
A system and method for generating a personalized trends module includes steps of: for a given user, producing a social timeline by logging content posted on the given user's accounts on social media sites; analyzing the social timeline for recently posted content to derive an interim summary of first trending topics for the given user; receiving from a content personalization platform an in-stream feed of second trending topics based on the user's recent on-line activity including page views, queries, and clicks; augmenting the social timeline with the second trending topics from the in-stream feed to produce an interim list of third trending topics; ranking the third trending topics by source category using a frequency index; selecting the highest ranking third trending topics from each source category; and presenting a personalized trends module with positions allocated to the highest ranking third trending topics. |
| US09158849B2 |
Synthesis of webpage snippets using sub-pages of the webpage
A server device is configured to identify sub-pages corresponding to a particular webpage, where the particular webpage and the identified sub-pages may be associated with a same website; determine titles for the identified sub-pages; process the identified sub-pages to select a set of sub-pages, of the identified sub-pages, to use to generate a snippet for the particular webpage, where each webpage, in the set of sub-pages, may satisfy particular criteria, and a quantity of the set of sub-pages may be based on a length of a concatenation of the titles for the set of sub-pages; generate the snippet, for the particular webpage, using the titles for the set of sub-pages; and store the generated snippet in association with the particular webpage, where the generated snippet may be presented in a search result document when the particular webpage is identified as being relevant to a search query. |
| US09158847B1 |
Cognitive memory encoding networks for fast semantic indexing storage and retrieval
The invention provides a fast approximate as well as exact hierarchical network storage and retrieval system and method for encoding and indexing graphs or networks into a data structure called the Cognitive Signature for property based, analog based or structure or sub-structure based search. The system and method produce a Cognitive Memory from a multiplicity of stored Cognitive Signatures and are ideally suited to store and index all or parts of massive data sets, linguistic graphs, protein graphs, chemical graphs, graphs of biochemical pathways, image or picture graphs as well as dynamical graphs such as traffic graphs or flows and motion picture sequences of graphs. The system and method have the advantage that properties of the Cognitive Signature of the graph can be used in correlations to the properties of the underlying data making the system ideal for semantic indexing of massive scale graph data sets. |
| US09158845B1 |
Reducing latencies in web page rendering
A page structure may be used to begin validation of an embedded resource prior to the time a browser issues a request to validate the embedded resource. A page structure includes information indicating one or more embedded resources in the web page and, in some implementations, its corresponding cache characteristics. The page structure may be used to generate a validation message that indicates resources to be validated. The validation message may be sent to a server at substantially the same time that the browser begins rendering the web page. The server can then begin validating the resources indicated in the validation message by sending validation requests to an origin or other server storing the embedded resources. The server then may send the validation responses back to the client computer executing the browser so that the validation responses can be used to satisfy corresponding validation requests generated by the browser. |
| US09158839B2 |
Systems and methods for training and classifying data
A mechanism for training and classifying data is disclosed. The method includes receiving a data set having at least a first annotation and at least a second annotation. The first annotation and the second annotation represent characteristics within the data set. The method also includes determining a first identifier from the first annotation and a second identifier from the second annotation and associating the first identifier to the second identifier to generate a joined identifier. The method also includes computing feature weights and transition weights for the annotated data set based on the at least a first identifier, at least a second identifier, and at least a joined identifier and transitions between each of the first, the second and the joined identifiers. The method further includes receiving a second un-annotated data set and classifying the second data set based on the computed feature weights and the transition weights. |
| US09158836B2 |
Iterative refinement of search results based on user feedback
Provided are techniques for displaying search results in a first page, receiving feedback from the user that indicate which of the search results in the first page are at least one of relevant and irrelevant, re-ordering the search results in a second page based on the indications of the search results in the first page, and displaying the re-ordered search results in the second page. |
| US09158832B1 |
Method and computing device for maintaining dependencies among reference elements
The disclosure is generally directed to a method and computing device for maintaining dependencies among multiple reference elements (e.g., formulas of a table or spreadsheet). In various embodiments, prior to a reevaluation operation carried out on the reference elements, a computing device receives an input of a reference element via a user interface (e.g., receives a user's input of a formula), assigns the reference element to a group based on the dependency between the reference element and one or more other reference elements, and assigns the reference element to a location within a dependency graph to which the other reference elements are assigned. In response to an event that requires at least one of the reference elements to be reevaluated, the computing device reevaluates each group of reference elements in sequence a group at a time. |
| US09158830B2 |
Run-time engine implemented on a computing device allowing synchronization of records during application execution
A first database implemented on a remote device such as a handheld computer may be reconciled with a corresponding second database implemented on a host computer during execution of an application program on the handheld device. In addition, the application program may be executed according to program instructions stored in an application program file located in the remote device. The databases may be reconciled by first commencing execution of the application program. Then, during the course of program execution, a synchronization instruction located in said application program file is retrieved. The synchronization instruction is executed by establishing a communications link between the handheld computer and the host computer. Subsequently, any difference between the first database and the second database are reconciled. Furthermore embodiments of the invention contemplate that in addition to reconciling all of the databases located on the handheld and host computers, less than all of the databases may be reconciled to reduce the amount of time required to execute the reconciliation process. In addition, after reconciliation control may be returned to the calling application program, or to another application, as determined by the application designer. |
| US09158829B2 |
System and method of data security in synchronizing data with a wireless device
A system is disclosed. The system includes a server, a client application, and a first database. The first database is associated with the client application. The system further includes a second database to store data in an encrypted format, and a replicator to synchronize the data stored in the first and second databases. The system also includes a synchronizer to synchronize the data stored in the second database and the server based on a current security level. |
| US09158824B2 |
Incremental aggregation-based event pattern matching
Aspects of the present invention provide a solution for recognizing a pattern in a set of data, such as data streaming over a data communication system. In an embodiment, a set of data events is retrieved in the data stream. The retrieved objects each have a plurality of characteristics that can be matched to a predetermined desired characteristic, such as a key value. The retrieved data events can be evaluated with respect to a pattern, with a characteristic of data events being evaluated with respect to an aggregate value related to the pattern. This aggregate value can be updated incrementally based on the data in the characteristic. Based on the evaluation, a determination as to whether the set of data events received subsequent to the first object satisfies the pattern. |
| US09158822B2 |
System and method for pick-and-drop sampling
A database system includes an input to a database server configured to deliver a data stream formed of a sequence of elements, D={p1, p2, . . . , pm} of size m of numbers from {1, . . . , n} to the database server. The system further includes a computer program that causes a processor to approximate frequency moments (Fk) in the data stream, such that a frequency of an element (i) is defined as fi=|{j:pj=i}| and a k-th frequency moment of D is defined as F k = ∑ i = 1 n m i k in a single pass through the data stream. The processor is caused to carry out the steps of locating elements (i) with a frequency ΩFk in the data stream as heavy elements and approximating fi as ≧ a fraction of fi to limit memory resources used by the processor to estimate Fk to O(n1−2/k log(n)) bits. |
| US09158818B2 |
Facilitating identification of star schemas in database environments
Facilitating identification of star schemas in database environments. In an embodiment, queries directed to relational database tables (organized according to normalized schema) are examined to determine the relationships specified in the queries. A star schema is then generated by including the specified relationships. A data warehouse may be organized according to the generated star schema and the data previously stored in the database tables may be copied to the data warehouse. |
| US09158807B2 |
Fast distributed database frequency summarization
A mechanism is provided for computing the frequency packets in network devices. Respective packets are associated with entities in a vector, where each of the entities is mapped to corresponding ones of the respective packets, and the entities correspond to computers. Upon a network device receiving the respective packets, a count is individually increased for the respective packets in the vector respectively mapped to the entities, and computing a matrix vector product of a matrix A and the vector. The matrix A is a product of at least a first matrix and a second matrix. The first matrix includes rows and columns where each of the rows has a single random location with a one value and remaining locations with zero values. The matrix vector product is transmitted to a centralized computer for aggregating with other matrix vector products. |
| US09158806B2 |
Integrity checking and selective deduplication based on network parameters
An approach for managing a data package is provided. Network throughput is determined to exceed a threshold. A sender computer determines a hash digest of the data package by using a hash function selected based on central processing unit utilization. If the hash digest is in a sender hash table, then without sending the data package, the sender computer sends the hash digest and an index referring to the hash digest so that a recipient computer can use the index to locate a matching hash digest and the data package in a recipient hash table. If the hash digest is not in the sender hash table, then the sender computer adds the data package and the hash digest to the sender hash table and sends the data package and the hash digest to the second computer to check the integrity of the data package based on the hash digest. |
| US09158804B1 |
Method and system for efficient file-based backups by reverse mapping changed sectors/blocks on an NTFS volume to files
Changed files since a last backup are identified to be backed up by reverse mapping changed blocks to files. Block identifiers specifying blocks on a storage volume are received. A location of a file table zone is determined. The file table zone stores a file table of records. Each record stores a last modified timestamp for a file associated with the record. An intersection is created from the file table zone location and the block identifiers. The intersection includes a subset of records where each record in the subset is associated with a block from the file table zone that corresponds to a block identified by the block identifiers. The subset is parsed to extract timestamps. The timestamps are compared with the storage volume's last backup date. If the associated file was modified after the last backup date, a determination is made that the file should be backed up. |
| US09158800B2 |
Providing content items for non-standard content item slots
In some instances, a resource may have display space that is independent of the first-party content and which may be used for presenting third-party content items. The display of third-party content items may also depend on one or more device parameters. For a non-standard space, such as a content item slot having a non-standard ratio of height to width, a determination of the number of content items that can fill the non-standard content item slot may be made based on the height of the content item slot, the width of the content item slot, and a minimum content item size. The number of content items may be selected and formatted, such as by modifying a font size, based on the height and width of the content item slot and the minimum content item size. Data may be output to effect display of the formatted content items with the resource. |
| US09158798B2 |
Database large object reorganization
Embodiments of the invention relate to database large object (LOB) reorganization. An aspect of the invention includes calculating an activity of an inline LOB. The length of an inline LOB is redefined according to the activity of the inline LOB. LOB reorganization is performed based on the redefined length of the inline LOB. |
| US09158795B2 |
Compile-time grouping of tuples in a streaming application
A system and a method for initializing a streaming application are disclosed. The method may include initializing a streaming application for execution on one or more compute nodes which are adapted to execute one or more stream operators. The method may, during a compiling of code, identify whether a processing condition exists at a first stream operator of a plurality of stream operators. The method may add a grouping condition to a second stream operator of the plurality of stream operators if the processing condition exists. The method may provide for the second stream operator to group tuples for sending to the first stream operator. |
| US09158794B2 |
System and method for presentation of media related to a context
A system and method for presentation of media related to a context. A request is received over a network from a requesting device for media related to a context, wherein the request comprises at least one criteria. A query is formulated based on the context criteria so as to search, via the network, for user profile data, social network data, spatial data, temporal data and topical data that is available via the network and relates to the context and to media files so as to identify at least one media file that is relevant to the context criteria. A playlist is assembled via the network containing a reference to the media files. The media files on the playlist are transmitted over the network to the requesting device. |
| US09158790B2 |
Server, dictionary creation method, dictionary creation program, and computer-readable recording medium recording the program
A search server includes a category database that stores category information containing location information indicating a geographical location, a word assigned to the location, and a user ID identifying a user having assigned the word to the location in association with one another, and a dictionary registration unit that reads first input information indicating locations to which a first word is assigned by a first user and second input information indicating locations to which a second word is assigned by a second user, and when determining that the first and second users have assigned the words to a predetermined number or more of common locations based on those information, creates dictionary data containing the first and second words in association with each other and enters the dictionary data into a dictionary database. |
| US09158781B1 |
Version mapped incremental backups with version creation condition
A method to create a version map to represent the data state of a file at a particular point in time when an incremental backup is performed. In one embodiment, a logical memory backup file is created that is known as a cumulative data file. Changes to the cumulative data file according to one embodiment of the present invention include appending copies of modified data when the modified data meets a certain condition. A new version map may be created each time an incremental backup occurs. Locations of both modified and unmodified data in the backup data file are mapped for future reference to the data. |
| US09158780B2 |
Information storage device and information service system
The present invention provides an information storage device includes a first storage unit stores an arbitrary information file transmitted via a wide area information network, a second storage unit stores an information file in a predetermined form, which is derived from the first storage unit, an information file determination unit determines whether or not the information file in the first storage unit is the information file in the predetermined form, a file conversion unit converts an information file into the predetermined form, and a storage management unit manages the information file, and stores in the second storage unit. In the information storage device, if a copy of the information file in the first storage unit is not in the predetermined form when the copy is stored in the second storage unit, the copy converted into the information file in the predetermined form, and stored in the second storage unit. |
| US09158777B2 |
Augmented reality methods and apparatus
Augmented reality methods and apparatus are described according to some aspects of the disclosure. In one aspect, a method of experiencing augmented data includes using a source system, emitting a dynamic symbol which changes over time, using a consumption system, receiving the emission of the source system, using the consumption system, analyzing the emission which was received by the consumption system to determine whether the dynamic symbol is present in the emission, and using the consumption system, generating a representation of augmented data to be consumed by a user of the consumption system as a result of the analyzing determining that the dynamically changing symbol is present in the emission of the source system. |
| US09158775B1 |
Scoring stream items in real time
A system and method for generating a real-time stream of content from heterogeneous data sources and a real-time index. The heterogeneous data sources include search, entertainment, social activity and activity on third-party sites. A fetching unit retrieves recent content that is indexed in the real-time index according to keywords. A model generation engine generates a model based on user activities. The mixer compares candidate content items from the heterogeneous data sources and the real-time index to the model to generate scores for each item and generates a stream of content based on the scores. |
| US09158774B2 |
Interpersonal spacetime interaction system
The present innovation provides a method of establishing a connection between two individuals using an interpersonal spacetime interaction system, including enabling a first user to specify a spacetime event and to provide annotations for the spacetime event, maintaining a spacetime database comprising data objects, each data object corresponding to a spacetime event, querying a spacetime database, using a query that includes at least a specification of a desired spacetime event, said query being initiated by a second user, retrieving information from those data objects in the spacetime database whose corresponding spacetime events are proximate to the desired spacetime event, and providing the retrieved information to the second user. |
| US09158772B2 |
Partial and parallel pipeline processing in a deep question answering system
System, method, and computer program product to reduce an amount of processing required to generate a response to a first case by a deep question answering system, by, determining that a similarity score, of the first case relative to a second case, exceeds a similarity threshold, identifying a first feature of the second case having a first relevance score exceeding a relevance threshold, identifying a first candidate answer for the first case that does not have the first feature, and refraining from analyzing the first candidate answer in generating the response to the first case, thereby reducing the amount of processing of the deep question answering system. |
| US09158770B1 |
Memorytag hybrid multidimensional bar text code
An apparatus and method for cloud-based storage, retrieval and sharing of files tagged with barcodes and alphanumeric coding is provided. This application and method includes: either scanning a barcode by mobile device or inputting a code into a computer; decoding of the code or barcode provided, by installed application; accessing, by a cloud based storage system which hosts the associated or tagged file; and retrieving the file associated with the barcode or alphanumeric code. This method also includes a process by which: either by smart phone or personal computer; uploading or storing of files onto a cloud-based storage system; tagging of those stored files with a unique bar code and alphanumeric code; generating a barcode and alphanumeric code to associate with those tag files; and a method of transmitting barcodes or alphanumeric codes between smart phone users or computer uses for the purposes of sharing. |
| US09158769B2 |
Systems and methods for network content delivery
A content delivery system including a subscriber controller and cache, a source controller configured to transmit content to the subscriber controller and cache via a multicast transmission; and a network content delivery controller (NCDC) in communication with the subscriber controller and cache and source controller. A control plane is used to communicate the delivery of control information using Extensible Messaging and Presence Protocol (XMPP) between the subscriber controller and cache, source controller, and NCDC. |
| US09158766B2 |
Multi-touch interface for visual analytics
A system and method for facilitating adjusting a displayed representation of a visualization. An example method includes employing a touch-sensitive display to present a user interface display screen depicting a first visualization; and providing a first user option to apply touch input to a region of the user interface display screen coinciding with a portion of the first visualization to facilitate affecting an arrangement of data displayed via the first visualization, wherein the touch input includes a multi-touch gesture. In a more specific embodiment, the touch gesture includes a rotation gesture, and the method further includes displaying a visual indication of a change, e.g., a pivot operation, to be applied to a second visualization as a user performs the rotation gesture, and updating the second visualization as a user continues perform the rotation gesture. The first visualization is updated based on the second visualization upon completion of the rotation gesture. |
| US09158765B1 |
Managing content versions
Items of content may be available in any of a number of versions. Major aspects of each content version, such as overall plot and major characters, may generally overlap. However, minor aspects, such as level of description, minor characters, or sub-plots may vary between versions. Accordingly, systems and methods are provided for managing playback of multiple content versions, and enabling users to switch between such content versions. In some embodiments, a playback path including portions of multiple content versions may be provided, such that a user may consume only desired portions of each content version. In other embodiments, a determined playback path may be utilized to create a customized content version, which may be provided to a user. |
| US09158758B2 |
Retrieval of prefix completions by way of walking nodes of a trie data structure
Technologies pertaining to providing completions to proffered prefixes are disclosed herein. A suggested completion to a proffered prefix is retrieved by walking nodes of a trie data structure, wherein a node includes one or more characters that are used to extend a character sequence represented by its parent. Each node in the trie data structure is assigned a score, wherein the score maps to a best score assigned to its descendants. The nodes of the trie data structure are sorted based upon score, and the nodes are walked based upon scores assigned thereto. |
| US09158755B2 |
Category-based lemmatizing of a phrase in a document
A processor-implemented method, system, and/or computer program product lemmatizes a phrase for a specific category. An initial phrase, which is associated with a specific category, is received by a processor. The processor removes a last letter or set of letters from a word in the initial phrase to form an initial truncated version of the phrase, and then runs a term frequency-inverse document frequency (TF-IDF) algorithm on the initial truncated version of the phrase. The processor lemmatizes subsequent truncated versions of the initial phrase, and then runs the TF-IDF algorithm until a highest TF-IDF value is identified for a specific truncated version of the initial phrase when compared to TF-IDF values of other truncated versions of the initial phrase. The specific truncated version of the initial phrase that is associated with the highest TF-IDF value is then associated with the specific category. |
| US09158750B2 |
Method and system to process an electronic form
A method and system to process an electronic form is provided. The system may include a communications module to receive a request to digitally sign an electronic form, the electronic form being direct rendered, a suspend module to respond to the request by suspending direct rendering, and a signed content generator to generate a signed version of the electronic form. The signed version of the electronic form is to reflect a state of the electronic form at the time of the request digitally sign the electronic form. |
| US09158745B2 |
Optimization of media content using generated intermediate media content
An automatic graphics delivery system that operates in parallel with an existing Web site infrastructure is provided. The system streamlines the post-production process by automating the production of media through content generation procedures controlled by proprietary tags placed by an author within URLs embedded within Web documents. |
| US09158729B1 |
Client request processing using protocol abstraction
Described are techniques for processing a request. The request is sent from a command layer to a protocol abstraction layer. The request is to perform an operation on a first object of a first object type and the request includes one or more parameters. The protocol abstraction layer selects a first of a plurality of protocols and a first of a plurality of runtime paths for processing the request. The first protocol is selected in accordance with criteria including any one or more of the first object type, the operation being requested, and the one or more parameters. The request is processed in accordance with the first protocol and the first runtime path. |
| US09158728B2 |
Systems and methods for improved linking of master and slave devices
System and methods are provided. In one embodiment, a system includes a master device comprising a first serial peripheral interface (SPI) port having only a first four wires. The system further includes a slave device comprising a second SPI port having only a second four wires. The system additionally includes a galvanic isolation barrier communicatively coupling the first four wires to the second four wires. The master device is configured to use the first four wires to transmit a plurality of signals representative of a reset and of a first communications mode. The first communications mode is used to transfer data between the master device and the slave device. |
| US09158726B2 |
Self terminated dynamic random access memory
A method for operating a memory system and a memory buffer device. The method includes receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, and receiving an ODT signal from the CPU to a command port of the buffer device. Buffer device provides the self-termination information internally to the common data bus by automatically detecting the read or write command on the common command bus and adjust the termination resistor array in a pre-determined value and timing fashion so that information can be read from or write to a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface. All DIMM devices other than the DIMM device being read can be maintained in a termination state to prevent any signal from traversing to the common the common data bus interface. |
| US09158725B2 |
Flexible control mechanism for store gathering in a write buffer
A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address. |
| US09158724B2 |
Image forming apparatus performing arbitration of access requests from an IC chip to a memory
An image forming apparatus according to the present disclosure includes: a first IC chip; a second IC chip connected to the first IC chip via a serial bus; and a memory that is either connected to or included in the first IC chip. The first IC chip includes: a first internal bus; a memory controller of the memory; a first processing circuit which outputs an access request to the memory; plural buffers corresponding to plural arbitration priority degrees of the first internal bus, and a request classifying circuit which identifies an arbitration priority degree of a requester of the access request received from the second IC chip and causes a buffer corresponding to the identified arbitration priority degree to buffer the access request. The first internal bus performs arbitration of access requests from the first processing circuit and the plural buffers in accordance with the arbitration priority degrees. |
| US09158723B2 |
Expanded protocol adapter for in-vehicle networks
A protocol adapter for in-vehicle networks that provides diagnostics, analysis and monitoring. The protocol adapter has a pass-through feature (voltage translator)/smart mode that allows the protocol adapter to emulate older boxes. Visual indicators (LEDs) indicate the pass through feature is in operation. LEDs also indicate activity on the RS232 bus between the adapter and a PC. Single color and multiple color emitting LEDs indicate a program is being executed and identify the program that is being executed. The protocol adapter supports RP1202 and RP1210, J1708 and J1939 and J1939 Transport Layer. The protocol adapter has a Real Time Clock, Standard COMM port connection, 7-32 Volt Supply and is CE compliant. The adapter can be used wirelessly. |
| US09158721B2 |
Information processing apparatus, control method, and program
An information processing apparatus capable of USB-connecting a device compatible with USB connection, the apparatus has a management unit configured to manage driver information representing whether to activate a device driver when the device is USB-connected. The information processing apparatus also has a device information acquisition unit configured to acquire device information of the device. The information processing apparatus also has a setting unit configured to set up the driver under control of an USB core driver to control the device using a device driver corresponding to the driver information when the driver information matches the device information. |
| US09158711B2 |
Creating a program product or system for executing a perform frame management instruction
Creating a computer program product or a computer system to execute a frame management instruction which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. |
| US09158709B2 |
Power cycling event counters for invoking security action
Subject matter disclosed herein relates to memory devices and security of same. |
| US09158707B2 |
Statistical cache promotion
Storing data in a cache is disclosed. It is determined that a data record is not stored in a cache. A random value is generated using a threshold value. It is determined whether to store the data record in the cache based at least in part on the generated random value. |
| US09158706B2 |
Selective space reclamation of data storage memory employing heat and relocation metrics
Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation. Thus, data that otherwise may be evicted or demoted, but that meets or exceeds the utility metric threshold, is exempted from space reclamation and is instead maintained in the data storage memory. |
| US09158704B2 |
Virtual memory management system with reduced latency
A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses. |
| US09158703B2 |
Linear to physical address translation with support for page attributes
Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed. |
| US09158701B2 |
Process-specific views of large frame pages with variable granularity
The page tables in existing art are modified to allow virtual address resolution by mapping to multiple overlapping entries, and resolving a physical address from the most specific entry. This enables more efficient use of system resources by allowing smaller frames to shadow larger frames. A page table is selected. When a virtual address in a request corresponds to an entry in the page table, which identifies a next page table associated with the large frame, a determination is made that the virtual address corresponds to an entry in the next page table, the entry in the next page table referencing a small frame overlay for the large frame. The virtual address is mapped to a physical address in the small frame overlay using data of the entry in the next page table. The physical address in a process-specific view of the large frame is returned. |
| US09158700B2 |
Storing cached data in over-provisioned memory in response to power loss
A power loss condition is detected that affects volatile data that is cached in preparation for storage in a non-volatile, solid-state memory device. The volatile cached data is stored in an over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition. |
| US09158695B2 |
System for dynamically adaptive caching
The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space. |
| US09158691B2 |
Cross dependency checking logic
Systems and methods for maintaining an order of transactions in the coherence point. The coherence point stores attributes associated with received transactions in an input request queue (IRQ). When a new transaction is received by the coherence point, the IRQ is searched for other entries with the same request address or the same victim address as the new transaction. If one or more matches are found, the new transaction entry points to the entry storing the most recently received transaction with the same address. The new transaction is stalled until the transaction it points to has been completed in the coherence point. |
| US09158690B2 |
Performing zero-copy sends in a networked file system with cryptographic signing
A method and system for sending data in a file system that uses cryptographic signatures to protect data integrity. A computer system calculates a signature based on the content of a page of a memory. The memory is shared by processes that run on the computer system. The computer system write-protects the page while the page is used for calculation of the signature. When a first process attempts to modify the page, a page fault is triggered. In response to the page fault, the content of the page in memory is copied to a new page in the memory. The new page is accessible by the processes. Access to the page by the first process is redirected to the new page. Subsequent to the page fault, access to the page by the second process is also redirected to the new page. |
| US09158689B2 |
Aggregating cache eviction notifications to a directory
Technologies are described herein generally relate to aggregation of cache eviction notifications to a directory. Some example technologies may be utilized to update an aggregation table to reflect evictions of a plurality of blocks from a plurality of block addresses of at least one cache memory. An aggregate message can be generated, where the message specifies the evictions of the plurality of blocks as reflected in the aggregation table. The aggregate message can be sent to the directory. The directory can parse the aggregate message and update a plurality of directory entries to reflect the evictions from the cache memory as specified in the aggregate message. |
| US09158682B2 |
Cache memory garbage collector
A method for managing objects stored in a cache memory of a processing unit. The cache memory includes a set of entries corresponding to an object. The method includes: checking, for each entry of at least a subset of entries of the set of entries of the cache memory, whether an object corresponding to each entry includes one or more references to one or more other objects stored in the cache memory and storing the references; determining among the objects stored in the cache memory, which objects are not referenced by other objects, based on the stored references; marking entries as checked to distinguish entries corresponding to objects determined as being not referenced from other entries of the checked entries, and casting out, according to the marking, entries corresponding to objects determined as being not referenced. |
| US09158680B2 |
Numeric representation to improve life of solid state storage devices
Technologies and implementations for improving life of a solid state storage device are generally disclosed. |
| US09158678B2 |
Memory address management system and method
According to one embodiment, a memory system includes a nonvolatile memory including first blocks configured to store an address indicating a data storage position, and second blocks configured to store the data, a first table configured to store a first address including first information and second information, the second information indicating a data storage position in the first block, and a second table configured to convert the first information into third information, the first information having a first data size by which one entry of the second table can be identified, the third information having a second data size which is larger than the first data size and by which one of the first blocks and the second blocks can be identified. |
| US09158675B2 |
Architecture for storage of data on NAND flash memory
Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs. |
| US09158670B1 |
System and method for dynamically adjusting garbage collection policies in solid-state memory
Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection in solid state devices to efficiently maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. In one embodiment, the controller selects for garbage collection a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. One or more of the pools have minimum thresholds that can be dynamically adjusted according to an observed usage condition, such as a change of an over-provisioning amount in the storage state device. |
| US09158666B2 |
Computer system and computer system information storage method
If simultaneous replacement main system and standby system of a management module was necessary due to a failure, fault or other problem in a structure containing redundant management modules, then the management information retained in the management module will be lost. A computer system contains an external storage device that is outside the manager module. This external storage device stores the same information as the management information held by the main system management module, and after replacing the management modules the management information held in the external storage device is restored in the management module. A switch is further included between the external storage device and the management module, and controlling this switch from the management module allows the plurality of management modules to exclusively access the external memory device. |
| US09158648B2 |
Reporting product status information using a visual code
A system facilitates reporting product status information using a visual code. The system includes a code generator and a communication device. The code generator reports a product status with aggregate information in a visual code. In order to achieve this functionality, the code generator recognizes a status event trigger for a product. The code generator also compiles the aggregate information in response to the status event trigger for the product. The aggregate information includes product status information and product identification information. The code generator also generates the visual code representative of the aggregate information. The communication device facilitates communication of the visual code to a user. |
| US09158647B2 |
Formatting system monitoring information
Embodiments disclosed herein relate to formatting system monitoring information. In one embodiment, a processor formats information related to monitoring a system. The formatted information may be related to components in a system. In one embodiment, the processor formats received information related to the system. The processor may output the formatted information. |
| US09158645B2 |
Continuously transferring data using a USB mass storage device
A method for continuous data transfer when a USB mass storage device is disconnected and reconnected is provided. The method may include monitoring state information from one or more mass storage devices, using a software driver to detect a change in state of the mass storage device on the computer. Active I/O transfers using the USB mass storage device are paused when the software driver detects that the USB mass storage device is detached from the computer. A configurable timer is started. The software drive may detect the attaching of a USB device. If, prior to the expiration of the timer, the software driver verifies that the USB mass storage device is the same that was previously attached to the computer, active I/O transfers are continued. |
| US09158639B2 |
Method and apparatus for correlating input and output messages of system under test
A method and apparatus for determining correlation between input and output messages in a system under test (SUT) is provided in the present invention. The SUT is provided with preset watch-points, and the running of the SUT is detected by triggering watch-points in a test platform at its run time. The method includes the steps of: upon detecting a message input operation, finding a variable that stores an input message, associating the variable with a tag of the input message, and adding a watch-point for the variable in the test platform; as well as, upon detecting network output operation, finding a variable that stores an output message of the SUT; and determining correlation between the output message and an input message according to a tag associated with the variable that stores the output message. |
| US09158632B1 |
Efficient file browsing using key value databases for virtual backups
A method, article of manufacture, and apparatus for protecting data. This includes using a directory to identify keys in a key value database, walking through each identified key to identify values, identifying a file based on the walk through, and restoring the identified file to a storage device. |
| US09158628B2 |
Bios failover update with service processor having direct serial peripheral interface (SPI) access
Certain aspects direct to systems and methods of BIOS failover update with a service processor (SP) having direct serial peripheral interface (SPI) access to a basic input/output system (BIOS) chip of a host computer. In certain embodiments, the SP receives a failover backup image from a BIOS being executed at a CPU of the host computer through a system interface, and stores the failover backup image in the volatile memory. Then the SP monitors operation of the BIOS by receiving, from the BIOS, a notification signal. When the SP detects an error in the operation of the BIOS based on the notification signal, the SP sends a copy of the failover backup image to the BIOS chip of the host computer through the SPI to replace a current BIOS image stored in the BIOS chip of the host computer with the copy of the failover backup image. |
| US09158625B2 |
Acquiring a trusted set of encoded data slices
A method for execution by a computing device, the method begins in response to a data segment access request, generating a set of access requests regarding a set of encoded data slices. The method continues by sending a subset of the access requests to storage units of a dispersed storage network (DSN) and sending an access request of the set of access requests to a trusted storage unit of the DSN. The method continues by receiving a trusted encoded data slice from the trusted storage unit and receiving a subset of encoded data slices from the storage units, wherein the trusted encoded data slice is utilized to authenticate the subset of encoded data slices and when the subset of encoded data slices are authenticated, the trusted encoded data slice and the subset of encoded data slices are decoded to recover the data segment. |
| US09158623B2 |
Flash subsystem organized into pairs of upper and lower page locations
A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. |
| US09158621B2 |
System and method of copying data
A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die. |
| US09158612B2 |
Refresh of non-volatile memory cells based on fatigue conditions
In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block. |
| US09158611B2 |
Telecommunications methods for increasing reliability of early termination of transmission
An embodiment of the invention provides a telecommunications method performed by a second telecommunications device. According to the embodiment, the second telecommunications device first tries to use a received part of a data block to decode the data block, wherein the received part is received from a first telecommunications device. Next, the second telecommunications device determines whether a code metric derived based on the received part indicates that the data block is decodable. If the code metric indicates that the data block is decodable, the second telecommunications device further determines whether a set of confirmation criteria is satisfied. |
| US09158609B2 |
Universal serial bus testing device
A USB testing device is provided for an electronic device having a USB port. The USB testing device includes a first USB control unit, a second USB control unit, and a micro-processor. When the first USB control unit has received power, the first USB control unit processes a connection test via a first data port. When the second USB control unit has received the power, the second USB control unit processes a connection test via a second data port. When the USB testing device is connected to the USB port, the micro-processor provides power to the first USB control unit. When the first USB control unit receives power, the first USB control unit provides power to the second USB control unit after waiting for a predetermined period of time. The electronic device determines whether the first and second data ports are operating properly. |
| US09158605B2 |
Method, system and device for validating repair files and repairing corrupt software
A system and method for repairing corrupt software components of a computer system. Corrupt software is detected and repaired utilizing an automated component repair service. Repair files are downloaded from an external storage location and used to repair the corruption. The downloaded files are preferably the smallest amount of data necessary to repair the identified corruption. The process of repairing corrupt files is used in conjunction with a software updating service to resolve problems that occur when corrupt software is updated by allowing a corrupt component to be repaired and then uninstalled such that an updated component can be properly installed. |
| US09158603B2 |
Message processing method and device
The present invention provides a message processing method and device, wherein the method comprises: creating a message queue by an application; taking out all current messages from a message queue created by an operating system; performing order adjustment for the taken-out messages and placing them in the message queue created by the application; performing delivery-processing for each message according to an order of messages in the message queue created by the application. Through the present invention, the messages in the message queue may be processed more flexibly. |
| US09158599B2 |
Programming framework for applications
An application comprises program code that includes API tags, which during execution of the application may be resolved to reference-able data objects. The data objects may be objects in a knowledge base. The API tags decouple the program code from the specific data contained in the knowledge base, allowing for applications that access the knowledge base to be written independently of the knowledge base; even before the knowledge base is loaded with data. |
| US09158588B2 |
Flexible task and thread binding with preferred processors based on thread layout
Embodiments of thread binding are provided. An aspect includes generating a thread layout for an application. Another aspect includes determining a task count for the application; determining a task rank for each task of the task count; determining a thread count for each task associated with the application, wherein a thread count for a first task associated with the application is unequal to a thread count of a second task associated with the application; and indicating one or more preferred processors of a plurality of processors for each task associated with the application. Another aspect includes allocating system for each of the tasks of the application based on the thread layout. Another aspect includes affinitizing the tasks by generating child threads for each of the tasks, wherein a number of threads generated for each task corresponds to the thread count for the task in the thread layout. |
| US09158587B2 |
Flexible task and thread binding with preferred processors based on thread layout
Embodiments of thread binding are provided. An aspect includes generating a thread layout for an application. Another aspect includes determining a task count for the application; determining a task rank for each task of the task count; determining a thread count for each task associated with the application, wherein a thread count for a first task associated with the application is unequal to a thread count of a second task associated with the application; and indicating one or more preferred processors of a plurality of processors for each task associated with the application. Another aspect includes allocating system for each of the tasks of the application based on the thread layout. Another aspect includes affinitizing the tasks by generating child threads for each of the tasks, wherein a number of threads generated for each task corresponds to the thread count for the task in the thread layout. |
| US09158586B2 |
Systems and methods for managing cloud computing resources
Systems and methods for managing cloud computing resources are provided. A plurality of available cloud computing servers may be identified by a cloud computing resource manager (“CCRM”). The CCRM may include one or more computers. The initiation of one or more processes on one or more servers included in the plurality of cloud computing servers may be directed by the CCRM. Operational data associated with the operation of the one or more processes and network data associated with network timing delays between the one or more servers and one or more client devices in communication with the one or more servers may be obtained by the CCRM. Based at least in part upon the operational data and the network data, the distribution of resources among the plurality of cloud computing servers may be managed by the CCRM. |
| US09158585B2 |
Method and apparatus for workflow validation and execution
A computer program product comprising: a non-transitory computer readable medium; and a description of a first block comprising: a definition of one or more output port groups each comprising one or more output ports; a definition of two or more input ports, the input ports receive object streams of identical length; one or more instructions for processing input data received in the input ports and for outputting processed data in the output port groups, wherein the instructions are operative to output a same number of output objects to each output port in a same output port group, whereby the output ports of the output port group are operative to output objects stream of identical length, and wherein the instructions are operative to receive a same number of input objects from each input port, whereby the input ports are operative to receive object streams of identical length; and an indication of whether there is a constant ratio between a number of items in input streams received by the first block and a number of items in output streams outputted by the first block; and wherein said description of a first block is stored on said non-transitory computer readable medium. |
| US09158584B2 |
Distributed application execution in a heterogeneous processing system
A method for distributing execution of a computer program to a plurality of hardware architectures of different types including: analyzing the computer program to identify a plurality of execution boundaries; selecting one or more execution boundaries from the plurality of execution boundaries; linking the computer program to the selected one or more execution boundaries; executing the computer program with linked execution boundaries; saving a hardware agnostic state of the execution of the computer program, when the execution encounters a boundary from the selected one or more execution boundaries; and transmitting the hardware agnostic state to a remote hardware architecture to be executed on the remote hardware architecture, responsive to the hardware agnostic state. |
| US09158583B1 |
Management of computing devices processing workflow stages of a resource dependent workflow
Systems and method for the management of resource dependent workflows are provided. One or more resource control devices monitor usage of a computing resource by server computing devices. Each resource control device may direct a server computing device to proceed with a workflow or to pause processing a workflow. A resource control device may further direct a server computing device to take resource conserving actions. When a computing resource is determined to be available, a resource control device may direct a paused server computing device to resume a workflow. |
| US09158582B2 |
Method for managing the threads of execution in a computer unit, and computer unit configured to implement said method
A method of managing execution threads launched by processes being executed in a computer unit having at least one calculation core connected to a shared memory. The method includes the steps of: using a zone of the shared memory that is accessible to all of the processes and execution threads for the purpose of managing calculation tokens; when a thread seeks to execute, that thread verifies that a calculation token is available; if a calculation token is available, the thread allocates the calculation token to itself by updating the shared memory and it continues its execution, and then releases the calculation token at the end of its execution; and each execution thread has a priority index allocated thereto, and each thread having a task that is being executed is caused periodically to verify that a thread has not been put on standby that has a priority index higher than its own, and where appropriate, causing the thread that is executing to stop executing and release the corresponding calculation token. A computer unit for performing the method. |
| US09158581B2 |
Continuous optimization of archive management scheduling by use of integrated content-resource analytic model
A method and associated system for continuously optimizing data archive management scheduling. A flow network is modeled. The flow network represents data content, software programs, physical devices, and communication capacity of the archive management system in various levels of vertices such that an optimal path in the flow network from a task of at least one archive management task to a worker program of the archive management system represents an optimal initial schedule for the worker program to perform the task. |
| US09158579B1 |
System having operation queues corresponding to operation execution time
A system and method for prioritized queues is provided. A plurality of queues are organized to enable long-running operations to be directed to a long running queue operation, while faster operations are directed to a non-long running operation queue. When an operation request is received, a determination is made whether it is a long-running operation, and, if so, the operation is placed in a long-running operation queue. When the processor core that is executing long-running operations is ready for the next operation, it removes an operation from the long-running operation queue and processes the operation. |
| US09158578B1 |
System and method for migrating virtual machines
A method, computer program product, and computing system for receiving an indication that a target virtual machine is going to be migrated from a first operating environment to a second operating environment. The target cache system is associated with target virtual machine. An auxiliary virtual machine is generated within the second operating environment. An auxiliary cache system is associated with the auxiliary virtual machine. The target virtual machine and the auxiliary virtual machine are connected. IO requests for the target virtual machine are mirrored to the auxiliary virtual machine. At least a portion of cache data included within a target memory system associated with the target cache system is copied to an auxiliary memory system associated with the auxiliary cache system. The target virtual machine is migrated from the first operating environment to the second operating environment. |
| US09158575B2 |
Multithreaded processor array with heterogeneous function blocks communicating tokens via self-routing switch fabrics
A shared resource multi-thread processor array wherein an array of heterogeneous function blocks are interconnected via a self-routing switch fabric, in which the individual function blocks have an associated switch port address. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. Thread queue empty flags are grouped using programmable circuit means to form self-synchronised threads. Data from different threads are passed to the various addressable function blocks in a predefined sequence in order to implement the desired function. The separate port queues allows data from different threads to share the same hardware resources and the reconfiguration of switch fabric addresses further enables the formation of different data-paths allowing the array to be configured for use in various applications. |
| US09158573B2 |
Dynamic predictor for coalescing memory transactions
A transactional memory system predicts the outcome of coalescing outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction, the method comprising. A processor of the transactional memory system determines whether a first plurality of outermost transactions from an associated program that were coalesced experienced an abort, the first plurality of outermost transactions including a first instance of a first transaction. The processor updates a history of the associated program to reflect the results of the determination. The processor coalesces a second plurality of outermost transactions from the associated program, based, at least in part, on the updated history. |
| US09158570B2 |
Method and system for facilitating quality of service in edge devices in a fibre channel network
One embodiment of the present invention provides a system that facilitates quality of service (QoS) in a Fiber Channel (FC) host bus adaptor (HBA). In this system the bandwidth on an FC link between the HBA and the FC switch can be allocated into a plurality of logical channels, and a respective logical channel can transport data frames of variable length. Furthermore, a respective logical channel is associated with a dedicated buffer. During operation, the HBA communicates to an FC switch the HBA's capability of receiving or sending a data flow over a logical channel that couples the HBA to the FC switch. The HBA further receives logical-channel allocation information from the FC switch. Furthermore, the HBA associates data frames with a logical channel and transmits data frames to the FC switch on the corresponding logical channel. |
| US09158568B2 |
Input/output operations at a virtual block device of a storage server
Example embodiments disclosed herein relate to input/output (I/O) operations at a virtual block device of a storage server. Example embodiments include requesting an input/output (I/O) operation at an offset of a virtual block device of a storage server in response to a virtual machine request for an I/O operation at a virtual disk. |
| US09158566B2 |
Page mapped spatially aware emulation of computer instruction set
Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. |
| US09158565B2 |
Predictable computing in virtualizated distributed computer systems based on partitioning of computation and communication resources
The invention relates to a method for providing guaranteed quality of service in distributed computing platforms for execution of distributed applications, by combining: i) a partitioned operating system (POS) or a hypervisor (101) executed on at least two computers (300,301); where said POS/hypervisor allocates the CPU, memory and I/O hardware resources to computer partitions in said computers; where said computers are capable of executing different computer partitions (104, 105, 106) with different application tasks within one said computer partition or executing different operating systems (in case of hypervisor) within one said computer partition; wherein the said POS/hypervisor ensures that the application tasks executed in different partitions within the same said computer get their allocated hardware resources; wherein said POS/hypervisor performs a time-driven scheduling for a subset of computer partitions based on a given configuration (136), ii) means, for example network communication technology, for implementing partitioning of Ethernet communication resources and creating virtualized networks out of one physical network. |
| US09158562B2 |
Method and apparatus for supporting virtualization of loadable module
Disclosed herein is a method and apparatus for supporting virtualization. In the method, conversion of source code of a loadable module is initiated. A virtualization-sensitive instruction is searched for during the conversion of the source code. If the virtualization-sensitive instruction has been found, a virtualization-sensitive instruction table is generated based on the found virtualization-sensitive instruction. The virtualization-sensitive instruction is substituted with an instruction recognizable in a privileged mode, based on the generated virtualization-sensitive instruction table. The loadable module is loaded and executed in a kernel. Accordingly, the present invention supports virtualization, thus minimizing overhead occurring in full virtualization, and guaranteeing the high performance provided by para-virtualization without modifying a source. |
| US09158561B2 |
Systems and methods for modifying an operating system for a virtual machine
Systems, methods, and software are described herein for operating a data management system, including executing an attached application and application data on a first virtual machine running a first operating system, separating the attached application and application data from the first virtual machine, and dynamically attaching the application and application data to a second virtual machine running an updated version of the first operating system. |
| US09158558B1 |
Methods and systems for providing application manifest information
A computer-implemented method for providing application manifest information may include analyzing source code of a software application. The method may also include detecting that the source code is programmed to access a computer resource and determining a security implication of the source code being programmed to access the computer resource. Determining the security implication may include providing a notification of the security implication of the source code to a developer of the source code. Determining the security implication may also include providing information about the security implication in an application manifest. Systems and computer-readable-media for creating and editing application manifests are also disclosed. |
| US09158557B2 |
Method of deriving web service interfaces from form and table metadata
A system and method of deriving web service interfaces from form and table metadata is disclosed. The method uses a discovery subsystem to discover services that are available on an application server, retrieves the metadata descriptions of the services on the application server and uses the services discovered and the metadata descriptions to create web services interfaces such that the service is available using web services description language. |
| US09158552B2 |
Adaptive device driver method and system
Aspects of the present invention provide a method of specifying a device driver design for a board device. The method includes receiving a board device with various functional elements and on-board storage to be operatively coupled to a computing device through an interconnect. The device driver design is specified through the identification of one or more device driver parameters. The device driver parameters are to be used subsequently to customize an adaptive device driver that interfaces with the board device and each of the one or more functional elements. Device driver parameters are stored in a predetermined storage construct allocated from the board device. These device driver parameters remain stored in the storage construct until there is a need for the board device and corresponding device driver. Customizing the adaptive device driver is done after the device driver parameters have been stored and typically when a computer device starts or ‘boots”. Initially, aspects of the present invention may receive an indication that a board device and one or more functional elements associated with the board device have been attached to an interconnect and requires a device driver. Next, aspect of the present invention retrieve device driver parameters from the storage constructs and customizes the adaptable device driver into a device driver for the board device in accordance with the device driver parameters. |
| US09158551B2 |
Activating and deactivating Operating System (OS) function based on application type in manycore system
An apparatus and method for dynamically reconfiguring an Operating System (OS) for a manycore system are provided. The apparatus may include an application type determining unit to determine a type of an executed application, and an OS reconfiguring unit to activate only at least one function in an OS, based on the determined type of the application, and to reconfigure the OS. |
| US09158547B2 |
Methods and apparatus for scalable array processor interrupt detection and response
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. |
| US09158545B2 |
Looking ahead bytecode stream to generate and update prediction information in branch target buffer for branching from the end of preceding bytecode handler to the beginning of current bytecode handler
A bytecode interpreter is provided. The interpreter assists in branch prediction by a host processor reducing branch misprediction and achieving high performance. The bytecode branch processor includes an interpreter configured to process a program in a bytecode format in a virtual machine, a branch information generator configured to obtain, while a predefined number of bytecodes are read prior to a current bytecode being processed by the interpreter, a branch address and a target address of a predicted path of a branch corresponding to a preceding bytecode, the branch address being of a branch code included in a preceding handler that processes the preceding bytecode, and the target address being of a current handler that processes the current bytecode to which the preceding handler branches, and a branch target buffer updater configured to update a branch target buffer in the bytecode branch processor with the obtained branch address and target address. |
| US09158542B2 |
Data processing device and method, and processor unit of same
A processor unit (200) includes: cache memory (210); an instruction execution unit (220); a processing unit (230) that detects fact that a thread enters an exclusive control section which is specified in advance to become a bottleneck; a processing unit (240) that detects a fact that the thread exits the exclusive control section; and an execution flag (250) that indicates whether there is the thread that is executing a process in the exclusive control section based on detection results. The cache memory (210) temporarily stores a priority flag in each cache entry, and the priority flag indicates whether data is to be used during execution in the exclusive control section. When the execution flag (250) is set, the processor unit (200) sets the priority flag that belongs to an access target of cache entries. The processor unit (200) leaves data used in the exclusive control section in the cache memory by determining a replacement target of cache entries using the priority flag when a cache miss occurs. |
| US09158541B2 |
Register renamer that handles multiple register sizes aliased to the same storage locations
A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry. |