| Document | Document Title |
|---|---|
| US09160382B2 |
Phase noise mitigation for wireless communications
A method and apparatus for tracking and mitigating phase noise in a communication receiver are disclosed. The phase noise tracking and mitigation apparatus operates in a recursive manner and includes a quantizer for determining data symbols from noise-compensated input values, a phase noise estimator for determining raw phase noise values from the data symbols and a first sequence of uncompensated input values, an error concealment module for removing unreliable samples from the raw phase noise values, a filter operable to filter the raw phase noise values to produce filtered phase noise values, and a phase-noise compensator for determining noise-compensated output values dependent upon the filtered phase noise values and the first sequence of uncompensated input values. Filter coefficients, and initial noise-compensated input values are determined from one or more second sequences of uncompensated input values corresponding to known symbols corrupted by phase noise. |
| US09160378B2 |
Control method and equipment for radio-frequency signal
The present invention describes a RF signal control method and device that changes the gain attenuation in real time and uses the changed gain attenuation to adjust the RF input signal. The RF signal control method and device also uses determined linear filter parameters for linearity improvement on the digital signal that results from a down-conversion and analog-to-digital converter on the RF input signal. The adjusted and improved signal is output after a digital pre-distortion and power amplification operation. In comparison with existing technologies, the adjusted gain attenuation is used to make adjustment on the RF input signal and improve linearity the RF input signal such that the resulting RF signal has better quality. Thus, the current application improves the linearity effect of a digital pre-distorter and the dynamic effect of a power amplifier for the RF signal, thereby enhancing coverage of the RF output signal. |
| US09160377B2 |
Multi-mode multi-band power amplifiers
Exemplary embodiments are directed to an amplifier module which may comprise a transmit path including a first amplifier and a second amplifier. The exemplary amplifier module may further include a transformer coupled between the first amplifier and the second amplifier and switchably configured for coupling the first amplifier in series with the second amplifier in a first mode and coupling the first amplifier to bypass the second amplifier in a second mode. |
| US09160373B1 |
Systems and methods for joint decoding of sector and track error correction codes
Systems and methods are provided for decoding data stored on a storage device. A decoding method is described for retrieving data from the storage device, wherein the retrieved data are encoded using a product code having a first dimension and a second dimension. The decoding method includes processing at least one codeword from the first dimension to form detector soft information, decoding the at least one codeword from the first dimension based on the detector soft information to form a first decoder soft information, and decoding at least one codeword from the second dimension based on the first decoder soft information to form a second decoder soft information. |
| US09160367B2 |
Integrated-interleaved low density parity check (LDPC) codes
Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H0 of a sparse parity check matrix H1 to obtain at least a first codeword; truncating the at least first data element to obtain at least a first truncated data element; systematically encoding the at least second data element and the at least first truncated data element using the sparse parity check matrix H1 to obtain a nested codeword; and generating a second codeword based at least in part on a combination of the first codeword and the nested codeword. Integrated-interleaved LDPC decoding is also provided. |
| US09160355B2 |
Printed circuit board and signal timing control method thereof
A printed circuit board includes a sending element, a plurality of receiving elements, and a control unit. The sending element is configured to generate a sending signal. The receiving elements are configured to receive a control signal respectively. The control unit is coupled to the sending element through a first wire and to the receiving elements through a plurality of second wires. The control unit is provided with a comparison table that stores related information of the second wires. When receiving the sending signal, the control unit generates the control signals according the related information of the second wires. At least one of the control signals is transmitted to the corresponding receiving element, and the rest of the control signals are delayed for a preset time and then transmitted to the rest of the receiving elements. |
| US09160353B2 |
Phase frequency detector and charge pump for phase lock loop fast-locking
The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques. |
| US09160350B2 |
Integrated circuit comprising a delay-locked loop
Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry. |
| US09160345B1 |
Phase interpolator
Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. |
| US09160343B2 |
Heater device and oscillation apparatus
A heater device includes a temperature detector, a heater control circuit, a heater, a voltage supply path, and an overheat prevention circuit. The overheat prevention circuit includes a positive-temperature-coefficient thermistor and a pull-up resistor. The positive-temperature-coefficient thermistor is interposed on the voltage supply path in a position for being heated by the heater. The pull-up resistor that includes: one end connected between the heater and the positive-temperature-coefficient thermistor, and another end connected to a direct current power source. The control voltage to be applied to the heater is restricted to a voltage at a connection point between the positive-temperature-coefficient thermistor and the pull-up resistor when the control voltage from the heater control circuit is abnormally decreased. |
| US09160342B2 |
Non-binary decoder architecture and control signal logic for reduced circuit complexity
A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log2X inputs for receiving the clock signal inputs. |
| US09160334B2 |
Semiconductor device
A semiconductor device includes: a transistor circuit including a power supply terminal and a back gate terminal; a variable resistance connected between a first voltage terminal and the power supply terminal; and a control circuit controlling the variable resistance based on a digital signal in which a difference voltage is converted when an absolute value of the difference voltage between a voltage of the first voltage terminal and a voltage of the back gate terminal is lower than a threshold value. |
| US09160332B2 |
Method and system for mechanical coupling of flexible printed circuit to a sensor
In one embodiment, a system includes a touch sensor comprising a set of electrodes and a set of one or more connection pads electrically coupled to the set of electrodes. The system also includes a circuit electrically coupled to the one or more connection pads such that signals may be communicated from the set of one or more connection pads to the circuit. The system further includes the circuit mechanically coupled to the touch sensor via friction welding. |
| US09160330B2 |
Boost capacitor sharing architecture for power supply active balancing systems
An apparatus includes multiple first channels configured to be coupled to a first boost capacitor and multiple second channels configured to be coupled to a second boost capacitor. Each channel includes a transistor switch and a gate driver configured to drive the transistor switch. The gate drivers in the first channels include switch sub-arrays configured to control which transistor switch in the first channels is driven using a voltage from the first boost capacitor. The gate drivers in the second channels include switch sub-arrays configured to control which transistor switch in the second channels is driven using a voltage from the second boost capacitor. The transistor switch in each channel may include first and second transistors having their sources coupled together, and each of the channels may further include a pull-down switch configured to pull the sources of the first and second transistors to ground. |
| US09160329B2 |
Circuit control device
A circuit control device controlling a switching circuit which has a semiconductor switching element, having a main controller, a drive signal output portion and an obtaining portion. The main controller outputs a drive control signal. The drive signal output portion receives the drive control signal and outputs a drive signal to the switching element, the switching element acting on the basis of the drive signal. The obtaining portion obtains circuit information on status of the switching circuit in synchronization with the drive control signal. |
| US09160328B2 |
Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches
Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs. |
| US09160327B2 |
Semiconductor device and information processing apparatus
A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point. |
| US09160325B2 |
Systems and methods for fast kilovolt switching in an X-ray system
Various of the disclosed embodiments contemplate systems and methods in an X-ray imaging system, such as a CT system, facilitating more crisp switching between high and low voltages at an X-ray tube. Certain embodiments circuits which store and discharge energy to improve voltage rise and fall times. These circuits may mitigate the effects of losses, hysteresis cycles, and leakage currents. More controlled voltage rise and fall times may improve X-ray emission and detection synchronization. |
| US09160321B2 |
Power efficient multiplexer
A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs. |
| US09160320B2 |
Apparatus, system, and method for voltage swing and duty cycle adjustment
Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time. |
| US09160318B2 |
Data processing circuit and solid-state imaging device
A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal. |
| US09160309B2 |
Area efficient baseband filter
An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter. |
| US09160306B2 |
Duplexer and method for increasing the isolation between two filters
A duplexer includes an antenna terminal, a transmission amplifier terminal and a reception amplifier terminal. The transmission amplifier terminal is coupled to the antenna terminal via a transmission filter. The reception amplifier terminal is coupled to a reception filter and the reception filter is coupled to the antenna terminal via a band-stop filter. |
| US09160305B1 |
Capacitively and piezoelectrically transduced micromechanical resonators
In one embodiment, a hybrid micromechanical resonator includes a capacitive resonator element and a piezoelectric resonator element, wherein the resonator can be capacitively and piezoelectrically transduced. |
| US09160302B2 |
Acoustic wave band reject filter
A method and system for an acoustic wave band reject filter are disclosed. According to one aspect, an acoustic wave band reject filter includes a substrate and a plurality of acoustic wave band reject filter circuit blocks. The substrate includes bonding pads formed on the substrate. Each one of the plurality of acoustic wave band reject filter circuit blocks is fixed on a separate die. Each separate die has solder balls on a side of the die facing the substrate. The solder balls are positioned to electrically connect the bonding pads formed on the substrate to electrodes of the dies. |
| US09160301B2 |
Acoustic wave device
An acoustic wave device includes: a multilayer structure that has plural surfaces which principal surfaces of plural layers provide; a chip including an acoustic wave filter and mounted on a first surface; a resin unit sealing the chip; a wiring pattern that is formed on a second surface and electrically connected to at least one of resonators; a ground pattern that is formed on the second surface along a part of the wiring pattern, and is away from the wiring pattern; and an external terminal that is formed on a third surface and electrically connected to the wiring pattern and the ground pattern, the third surface being disposed on an opposite side of the first surface with respect to the second surface; wherein a part of the wiring pattern that comes closest to the ground pattern is substantially formed in parallel with the ground pattern. |
| US09160297B2 |
Common mode filter
Disclosed herein is a common mode filter having improved insertion loss characteristics. The common mode filter includes: first and second coil electrode patterns formed at an upper layer and alternately disposed; and first and second coil electrode patterns formed at a lower layer and alternately disposed, wherein the outermost pattern of the upper layer and the outermost pattern of the lower layer are coil electrode patterns having the same order. |
| US09160287B2 |
Linearization circuits and methods for multilevel power amplifier systems
Circuits and methods for achieving high linearity, high efficiency power amplifiers, including digital predistortion (DPD) and pulse cancellation in switched-state RF power amplifier systems are described. |
| US09160286B2 |
Radio frequency power amplifiers
A radio frequency power amplifier amplifies an input signal at an input port, and produces an output signal at an output port. The power amplifier may include one or more amplifier stages. An amplifier stage may include an active device, and a feedback network. The feedback network may include one or more reactive elements configured to resonate at a predetermined frequency, to provide an impedance match at the input to the amplifier stage, and to provide an impedance match at the output of the amplifier stage. In some example implementations, the input and output impedance matching is caused by biasing the active device to produce a transconductance at least one of equal to or greater than a critical transconductance. |
| US09160284B2 |
Systems and methods for biasing amplifiers using adaptive closed-loop control and adaptive predistortion
Various embodiments described herein provide systems and methods for improved performance for power amplifiers, particularly GaN power amplifiers. According to some embodiments, a power amplifier (e.g., GaN power amplifier) utilizes adaptive predistortion and adaptive closed-loop control of the drain current of the power amplifier to achieve improved power amplifier performance. |
| US09160283B2 |
Integrated pulse shaping biasing circuitry
Integrated pulse shaping biasing circuitry for a radio frequency (RF) power amplifier includes a square wave signal generator and an inverted ramp signal generator. The square wave signal generator and the inverted ramp signal generator are coupled in parallel between an input node and current summation circuitry. The square wave signal generator generates a square wave signal. The inverted ramp signal generator generates an inverted ramp signal. The current summation circuitry receives the generated square wave signal and the inverted ramp signal, and combines the signals to generate a pulse shaped biasing signal for an RF power amplifier. The square wave signal generator, the inverted ramp signal generator, and the current summation circuitry are monolithically integrated on a single semiconductor die. |
| US09160281B2 |
Semiconductor integrated circuit and radio communication terminal including the same
A semiconductor integrated circuit includes an operational amplifier that amplifies a voltage difference between an input voltage supplied to an inverting input terminal and a reference voltage supplied to a non-inverting input terminal and outputs an amplified signal, a feedback resistor that performs negative feedback of the amplified signal to the inverting input terminal of the operational amplifier, and a variable resistor unit that sets a current path with a first resistance value in accordance with a control signal between an external input terminal and the inverting input terminal of the operational amplifier, and sets a first alternative path with a second resistance value in accordance with the control signal between a node on the current path and a reference voltage terminal to which the reference voltage is supplied. |
| US09160277B2 |
High efficiency and high linearity adaptive power amplifier for signals with high PAPR
One embodiment of the present invention provides a system for controlling operations of a power amplifier in a wireless transmitter. During operation, the system receives a baseband signal to be transmitted, and dynamically switches an operation mode of the power amplifier between a high power back-off mode having a first power back-off factor and a normal mode having a second power back-off factor based on a level of the baseband signal. |
| US09160276B1 |
Adaptive impedance translation circuit
The present invention relates to an adaptable RF impedance translation circuit that includes a first group of inductive elements cascaded in series between an input and an output without any series switching elements, a second group of inductive elements cascaded in series, and a group of switching elements that are capable of electrically coupling the first group of inductive elements to the second group of inductive elements. Further, the adaptable RF impedance translation circuit includes at least one variable shunt capacitance circuit electrically coupled between a common reference and at least one connection node in the adaptable RF impedance translation circuit, which includes control circuitry to select either an OFF state or an ON state associated with each of the switching elements and to select a capacitance associated with each variable shunt capacitance circuit to control impedance translation characteristics of the adaptable RF impedance translation circuit. |
| US09160273B2 |
Universal end clamp
Universal End and Mid Clamps are used to connect 2 things together and are designed so that when the clamp fastener is properly tightened the piece being clamped will resist loads in 3 directions and will resist sliding. |
| US09160268B2 |
System for controlling a voltage inverter supplying power to a multiphase electrical motor of a motor vehicle
A system for controlling a voltage inverter, or supplying power to a multiphase electric motor of an automobile vehicle, including: a mechanism generating values of power supply voltages for each phase of the electric motor, together with an amplitude value of the power supply voltages; a phase-splicing determination mechanism; and a controller controlling the phase splicing cooperating to control transmission to the voltage inverter of duty cycles generated by determining the duty cycles, as a function of values of power supply voltages for each phase of the electric motor, and also of the amplitude value of the power supply voltages. |
| US09160259B2 |
Start and control method for a single-phase induction motor, a start and control system for a single-phase induction motor and an electronic start and control device applied to a single-phase induction motor
The present invention relates to a method, a system and an electronic device (15), especially designed for start and control of the functioning of a single-phase induction motor (12). Said motor (12) comprises a run winding (10) and a start winding (11), the start winding (11) is electrically associated to an electronic start device (15), the run winding (10) and the electronic start device (15) are electrically associated to an alternating voltage source (F) configured to supply feed energy to the motor (12), the start winding (11) is kept de-energized at a first operation instant (Top1) of the motor (12). More particularly, the present invention is configured to energize the start winding (11) through the electronic start device (15) in the condition in which a first voltage signal (Vsamp1), sampled from the alternating voltage source (F), through a sensor element (7), is lower than or equal to a first voltage reference (V1), or higher than or equal to a second voltage reference (V2), so as to initiate a start period of the motor (12). |
| US09160256B1 |
Soft-start control for electromechanical devices using a resistor-capacitor circuit
A system for controlling an electromechanical device includes a motor drive, a main controller, a voltage regulator and a resistor-capacitor circuit. The motor drive controls an electric motor of the electromechanical device. The main controller provides motor commands to control the motor drive that are provided by providing command voltage on at least one command line. The voltage regulator circuit receives the command voltage and provides a motor voltage to power the motor drive. A capacitor of the resistor-capacitor circuit is charged by the command voltage, and the motor voltage is controlled based upon charge of the capacitor. |
| US09160254B2 |
Piezoelectric device and electronic apparatus
A piezoelectric device includes an insulating substrate, a piezoelectric vibration device that is mounted on a device mounting pad, a metal lid member that seals the piezoelectric vibration device in an airtight manner, an external pad that is arranged outside the insulating substrate, an oscillation circuit, a temperature compensation circuit, and a temperature sensor. The lid member and the temperature sensor or the lid member and the IC component are connected to each other so as to be heat-transferable, and a heat transfer member having thermal conductivity higher than that of the material of the insulating substrate is additionally included. |
| US09160247B2 |
Alternating current/direct current adaptor and self-adaptive voltage output method
An alternating current (AC)/direct current (DC) adaptor is to be coupled electrically with an electronic device having an electrical property, and includes a DC/DC converter that receives a DC voltage signal and a control signal, and that adjusts the DC voltage signal according to the control signal to obtain an output DC voltage signal. A device discriminator receives the output DC voltage signal, and generates, according to the output DC voltage signal and the electrical property, a device indication signal set. A controller obtains a target value according to the device indication signal set, and outputs the control signal according to an initial value or the target value to control voltage value of the output DC voltage signal provided to the electronic device. |
| US09160245B2 |
Method for operating a converter in a system for generating electrical energy
Described is a method for operating a converter for a system for generating electrical energy. In an embodiment of the method, the output voltage of the converter is converted to a d, q coordinate system, wherein the d, q coordinate system is assigned to the frequency of the voltage for the energy supply grid. A desired value is furthermore specified in the d, q coordinate system, several momentary or future values are determined from the output voltage in the d, q coordinate system for different switch positions of the converter, deviations between the desired value and the momentary or future values are determined in the d, q coordinate system, and the converter is switched to one of the switch positions in dependence on these deviations. |
| US09160244B2 |
Magnetic integration double-ended converter
A magnetic integration double-ended converter with an integrated function of a transformer and an inductor includes an integrated magnetic member having a magnetic core with three magnetic columns having at least three windings (NP, NS1, NS2) and at least one energy storage air gap, where a primary winding (NP) and a first secondary winding (NS1) are both wound around a first magnetic column or are both wound around a second magnetic column and a third magnetic column, and a second secondary winding (NS2) is wound around the second magnetic column; an inverter circuit with double ends symmetrically working, acting on the primary winding (NP); and a group of synchronous rectifiers (SR1, SR2), gate electrode driving signals of which and gate electrode driving signals of a group of power switch diodes (S1, S2) of the inverter circuit with the double ends symmetrically working complement each other. |
| US09160243B2 |
Control circuit and interleaved power supply including that control circuit
In a control circuit that controls an interleaved power supply, a clock generator generates a clock pulse having a predetermined frequency. A signal doubler generates a master switch on-interval pulse signal indicating information concerning an on-interval of the master switch based on the clock pulse and a master drive pulse signal that drives the master switch, and generates a doubled duty pulse signal having a duty that is double that of the master switch on-interval pulse signal. An edge pulse generator generates a first edge pulse signal based on the master drive pulse signal, and generates a second edge pulse signal based on the doubled duty pulse signal. A slave drive pulse signal generator generates, based on the first and second edge pulse signals, a slave drive pulse signal that drives the slave switch so that an on-interval of the slave switch is identical to that of the master switch. |
| US09160242B2 |
Electric power conversion device
A switching circuit is configured to switch on/off a current that flows through a resonance circuit constituted by a primary winding of a transformer, a capacitance element, and an inductor that are connected in series. Electric power that is induced in a secondary winding of the transformer is rectified by a rectifier circuit. A switch is connected in parallel with the capacitance element. A control unit is configured to control the switching circuit and the switch. The control unit is configured to select a first operation in which an operation frequency of the switching circuit is controlled by switching off the switch, and select a second operation in which a period during which a current flows from the switching circuit to the primary winding of the transformer is controlled by switching on the switch. |
| US09160240B2 |
DC power supply device, and control method for DC power supply device
A phase of the pulse control signal upon restarting is synchronized with the phase of the pulse control signal upon suspending, thereby suppressing fluctuations of output voltage in each phase of the inverter upon restarting and further suppressing fluctuations of voltage supplied to the load. Upon supplying DC power to a plasma generator, when arc discharge occurs in the plasma generator, supplying of the DC power is suspended to reduce damage on the electrodes and substrate, and further upon extinguishing of the arc discharge, supplying of the DC power is restarted. In suspending and resuming the DC output, the current flowing in the chopper upon suspending is held in the form of circulating current, and upon restarting the inverter, this circulating current is supplied to the load. Accordingly, it is possible to reduce a delay in supplying the DC power to the load, upon resuming the DC output. |
| US09160237B2 |
Electric power converter
An electric power converter has a switching circuit section, a transformer, a rectifier, and a noise filtering element. The rectifier is connected to a secondary coil of the transformer. A closed circuit where the noise current flows is formed by the secondary coil, the rectifier, and the noise filtering element. The transformer and the noise filtering element are disposed in a position next to each other. The secondary coil and the noise filtering element are electrically connected to each other through a terminal for a coil that is a terminal of the secondary coil and a terminal for a filter that is a terminal of the noise filtering element. The terminal for the coil and the terminal for the filter are disposed in a position between the transformer and the noise filtering element. |
| US09160236B2 |
Burst-mode control method for low input power consumption in resonant converters and related control device
An effective method enhances energy saving at low load in a resonant converter with a hysteretic control scheme for implementing burst-mode at light load. The method causes a current controlled oscillator of the converter to stop oscillating when a feedback control current of the output voltage of the converter reaches a first threshold value, and introduces a nonlinearity in the functional relation between the frequency of oscillation and said feedback control current or in a derivative of the functional relation, while the control current is between a lower, second threshold value and the first threshold value, such that the frequency of oscillation remains equal or smaller than the frequency of oscillation when the control current is equal to the second threshold value. Several circuital implementations are illustrated, all of simple realization without requiring any costly microcontroller. |
| US09160232B2 |
Efficient regulation of capacitance voltage(s) in a switched mode multilevel power converter
A power conversion circuit uses smaller, cheaper, and faster analog and digital circuits, e.g., buffers, comparators, and processing circuits, to provide the information necessary to control a multilevel power converter faster, cheaper, and with a smaller footprint than conventional techniques. For example, a current detection circuit indirectly measures a direction of a current through an inductor connected between midpoint node and an output node of a multilevel power converter based on comparisons between voltages associated with the multilevel power converter. A capacitor voltage detection detects a capacitor voltage across the flying capacitor to generate a logic signal based on a comparison between the capacitor voltage and a first reference voltage. A control circuit selects an operating state of the multilevel power converter to regulate a first capacitor voltage across the first capacitor based on the indirectly measured direction of the inductor current, the logic signal, and an input command signal. |
| US09160229B2 |
DC-DC converter
A DC-DC converter, having an output voltage and including at least one electronic switch; first circuitry controlling the output voltage by adjusting a switching frequency of the electronic switch, and second circuitry adjusting the switching frequency toward a target switching frequency when the switching frequency significantly deviates from the target switching frequency. |
| US09160228B1 |
Integrated tri-state electromagnetic interference filter and line conditioning module
This disclosure describes systems, methods and articles of a passive EMI filter integrated with an active boost converter for low-side line transients and/or an active clipper for high-side line transients. During steady-state operation, the active circuitry is disabled so the circuit functions as a passive EMI filter. Inductive and capacitive components used in the passive EMI filter during steady-state operation may serve a dual role and become part of a boost converter when input voltage is below a low-line steady-state and, in some variations, the inductive and capacitive components may become part of a transient clipper when the input voltage is above a high-line steady-state level. The transient clipper may be implemented as a linear pass element or as a switch-mode converter (e.g., buck converter). |
| US09160224B2 |
Load control device for high-efficiency loads
A load control device for controlling the power delivered from an AC power source to an electrical load includes a thyristor, a gate coupling circuit for conducting a gate current through a gate of the thyristor, and a control circuit for controlling the gate coupling circuit to conduct the gate current through a first current path to render the thyristor conductive at a firing time during a half cycle. The gate coupling circuit is able to conduct the gate current through the first current path again after the firing time, but the gate current is not able to be conducted through the gate from a transition time before the end of the half-cycle until approximately the end of the half-cycle. The load current is able to be conducted through a second current path to the electrical load after the transition time until approximately the end of the half-cycle. |
| US09160217B2 |
Busbar unit and motor
A busbar unit is arranged on an axial end portion of a stator and electrically connected with a plurality of coil wire terminals arranged to project in an axial direction above the axial end portion of the stator. The busbar unit includes a plurality of busbars each including a body portion defined by an electrically conductive wire having an annular or “C” shape, the body portion being arranged around an axis of the stator; a holder member arranged on the axial end portion of the stator to hold the busbars; and a plurality of terminal members each including a busbar connection portion connected with the body portion of one of the busbars, and a coil connection portion connected with one of the coil wire terminals. |
| US09160214B2 |
Cooling structure for electric vehicle
Provided is an electric motorcycle including a traveling motor, and a power supply circuit of an inverter and the like, in which a non-conducting cooling oil is supplied to be brought into direct contact with at least one of an electromagnetic coil of the traveling motor and a circuit board of the inverter. A radiator is disposed outside cases of a power plant and a power control controller so as to allow a traveling wind to pass by. Cooling oil is circulated between the radiator and a case of at least one of the power plant and power control controller. A cooling structure for an electric motor and the like that can obtain a higher cooling efficiency than a conventional art while having a simple structure which hardly causes increases in size, weight, cost, and the like can be provided. |
| US09160211B2 |
Work machine and brushless motor
An electric grasscutter includes a motor (50) which drives a rotary blade (42). The motor (50) is a brushless motor accommodated in a motor housing (51) and including a rotor (53) provided integrally with an output shaft (52), and a stator (54) fixed to the motor housing (51). A motor control circuit which drives the motor (50) is accommodated in the motor housing (51). The motor control circuit includes an inverter having FETs (81-86) as switching elements, and a control section to control the FETs (81-86). The FETs (81-86) are fixed in contact with the motor housing (51). |
| US09160208B2 |
Generator motor and work machine
A generator motor connected to an output shaft of an engine mounted in a work machine includes a terminal box for connecting an exterior electric-power-supplying cable to the generator motor. The terminal box includes a casing having an inner space in communication with an inside of a housing of the generator motor. A casing of the terminal box is detachably provided to the housing of the generator motor. |
| US09160207B2 |
High power brushless DC motor and control box structure with heat dissipation arrangement
A motor, including: a motor body, the motor body including two ends; a damping ring, the damping ring including a bottom; a mounting bracket; a locking device; a control box; and a connection housing, the connection housing including two ends, and a sidewall. The damping ring is disposed on each end of the motor body. The bottom of the damping ring is supported by the mounting bracket. The damping ring is fixed on the mounting bracket by the locking device. One end of the connection housing is connected to a bottom of the motor body; the other end of the connection housing is connected to a top of the control box. A plurality of heat dissipation holes is arranged on the sidewall of the connection housing. |
| US09160204B2 |
Bidirectional wireless power transfer device
The present invention relates to a bidirectional wireless power transfer device, which includes: a first transfer unit; a second transfer unit; a selector that includes a first signal terminal, a second signal terminal, and a power input terminal; a power supply unit, which is electrically connected to the power input terminal of the selector and is also electrically connected to the first transfer unit and the second transfer unit; and a circuit board, on which the first transfer unit, the second transfer unit, the selector, and the power supply unit are mounted. |
| US09160198B2 |
Battery charging method and device using the same
The battery charging method includes: defining first to third charging regions according to a first predetermined voltage and the charging saturation voltage of a battery; determining a charging region of the battery according to the initial voltage of the battery, and determining a threshold charging current according to the charging regions of the battery; charging the battery according to the threshold charging current; continuously measuring a plurality of voltages in the battery during a predetermined period and determining an average voltage of the battery; determining if the previously determined charging region of the battery has changed according to the average voltage of the battery; and when the charging region of the battery has changed and the average voltage of the battery is lower than the charging saturation voltage, then lowering the threshold charging current and repeating the above steps. |
| US09160196B2 |
Communication apparatus and operation method thereof
A communication apparatus includes a communication coil, a power receiving portion, a charge control portion, a first switch portion, a second switch portion, a communication circuit, and a processor. A voltage detection circuit of the power receiving portion generates first control signal of first state when a terminal voltage of the communication coil exceeds power supply threshold voltage. The first switch portion is controlled to turn on between first terminal and third terminal in response to first control signal. The voltage detection circuit generates second control signal of third state when a terminal voltage of the communication coil exceeds first and second charge threshold voltages during a period to charge the secondary cell. The second switch portion is controlled to turn off in response to second control signal. |
| US09160195B2 |
Charging device
A charging device used for charging a storage battery includes a first circuit that generates a current which depends on a charging current of the storage battery; a second circuit in which charge is accumulated by periodical supply of the current which depends on the charging current; and a third circuit that outputs a signal indicating completion of charge of the storage battery when the potential of the second circuit reaches a reference potential. The second circuit includes a capacitor and a transistor in which an oxide semiconductor is used for a channel formation region. The transistor is turned on or off in response to a pulse signal input to a gate of the transistor. The capacitor accumulates charge when the current depending on the charging current flows through the transistor. |
| US09160191B2 |
Battery pack and method for minimizing cell voltage deviations
In one aspect, a battery pack and a method of minimizing voltage deviations between battery cells within the battery pack is disclosed. The battery pack comprises a plurality of battery racks where each of the battery racks in turn comprises a plurality of battery cells. The battery pack also comprises a bidirectional inverter and a plurality of switch sets, where each of the switch sets are connected to one of the battery racks and is configured to electrically connect the bidirectional inverter and the battery racks. The battery pack additionally comprises a plurality of battery rack management systems, where each of the battery rack management systems is electrically connected to one of the battery racks and is configured to minimize voltage deviations between the battery cells. The battery rack management systems are also connected to a main battery management system configured to minimize voltage deviations between the battery racks. |
| US09160190B2 |
System and method for assessing ADC operation and voltage of a battery pack
Systems and methods for assessing operation of analog digital converters (ADCs) of a battery pack supplying power to a vehicle are disclosed. One example system comprises, a first ADC for determining a voltage of at least one battery cell; a second ADC for determining a voltage of a plurality of battery cells; and a controller performing an action in response to comparing an output of said first ADC to an output of said second ADC. |
| US09160188B2 |
Apparatus and method for displaying strength of power and expected charge completion time during wireless charging
Provided is an apparatus and method for displaying a strength of power and an expected charge completion time during wireless charging. To this end, a first electronic device, upon receiving a power request message, converts stored or wirelessly supplied power into a wirelessly-transmittable form and transmits the converted power. A second electronic device, upon receiving a charging command, determines whether being located in a distance and a position which allow charging with the first electronic device, transmits the power request message to the first electronic device, receives the converted power from the first electronic device to measure the strength of the received power, and calculates an expected charge completion time by using the detected strength of power, if the second electronic device is located in the distance and position which allow charging. |
| US09160187B2 |
Optical charger with light receivers and light emitters
An optical charger includes a fixing block, a number of light receivers, a substrate, and a number of light emitters. The fixing block is used for receiving a battery. The light receivers are fixed on the fixing block. The battery is electrically connected to the light receivers. The substrate has a loading surface for loading the fixing block. The light emitters are positioned on the substrate and face the light receivers. The light emitters are electrically connected to an external power supply, and are used for converting electrical energy from the external power supply into optical energy and emitting light rays. The light receivers are used for receiving the light rays from the light emitters, and converting optical power of the light rays into electric energy. The battery receives and stores the electric energy. |
| US09160186B2 |
Battery charger for providing battery protection from over discharge from voltage or current and shipping mode
A battery charger includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery and at least one output terminal, a switch arranged in the electrical path between the battery terminal and at least one output terminal, an element configured to store an information representative of an alarm condition of the battery and to open the switch when the alarm condition occurs, with the supply signal being absent and the battery supplying the at least one output terminal, and to close the switch when the supply signal is received at the input supply terminal. |
| US09160185B2 |
Apparatus and method for active balancing of series cells and series packs in a battery system
An active balancing and battery charging system for a battery including a plurality of packs made up of cells. An H-bridge circuit having a nominal system voltage as an input generates a square wave output to a plurality of step-down transformers each associated with a pack, where the plurality of step-down transformers provide an active balancing voltage of about the nominal pack voltage. Each pack may include a balancing transformer including a common primary coil receiving the active balancing voltage from the associated step-down transformer or the pack itself. The balancing transformer also includes a plurality of secondary coils each associated with the respective plurality of cells of the pack. A voltage induced in the secondary coils causes a discrete charge current to flow to any cells in the pack that are undercharged relative to other cells. |
| US09160180B2 |
Charging apparatus for charging a secondary battery with a wireless feeding method
A charging apparatus including a mounting portion on which a plurality of information processing apparatuses are mounted, a power transmission unit that transmits power in a non-contact manner to each of the plurality of information processing apparatuses placed on the mounting portion, and a control unit that receives a charge order instruction from at least one of the plurality of information processing apparatuses, and controls the power transmission unit to transmit power to each of the plurality of information processing apparatuses in an order determined based on the received charge order instruction. |
| US09160178B2 |
Energy storage system
An energy storage system that includes a battery module including a plurality of battery cells, a battery management module connected to the battery cells through a plurality of first wires, detecting voltages of the battery cells and performing first cell balancing operations of the battery cells, and an external balancing module connected to the battery cells through a plurality of second wires, discharging the battery cells to a predetermined voltage and performing second cell balancing operations of the battery cells. |
| US09160177B2 |
Semiconductor circuit, battery monitoring system, and control method
A semiconductor circuit includes a drive component that includes first switching elements connected to discharge switching elements and resistive elements; and a drawing component. The first switching elements interconnect, in accordance with a drive time of the discharge switching elements, drive current sources that supply charge to control signal lines and the control signal lines. The drawing component draws charge with draw current sources in accordance with a draw time in which the drawing component draws the charge supplied from the drive component. |
| US09160176B2 |
Wireless power feeder, wireless power receiver, and wireless power transmission system
To increase efficiency of wireless power feeding to a moving object in wireless power feeding. A wireless power feeder 116 feeds power by wireless from a plurality of feeding coils L2 to an EV 108 including a receiving coil L3. The feeding coils L2 are arranged along a moving direction of the EV 108 and receive power from a power supply circuit including a plurality of power transmission control circuits 200. The power supply circuit 102 makes a first feeding coil L2 supply AC power to the EV 108 when the EV 108 passes through the first feeding coil L2 and, at the same time, prepares power feeding from a second feeding coil L2 through which the EV 108 has not passed. |
| US09160169B2 |
Scheduling to maximize utilization preferred power sources (SMUPPS)
A power utilization scheduling system and methods are disclosed. A prioritized energy consumption schedule is determined based on a prioritized energy consumption. A per-process energy consumption model is determined based on an energy consumption model, and an operation is scheduled based on the prioritized energy consumption schedule and the per-process energy consumption model. |
| US09160168B2 |
Smart electrical outlets and associated networks
A control system (300) allows recognized standard premise electrical outlets, for example NEMA, CEE and BS, among others to be remotely monitored and/or controlled, for example, to intelligently execute blackouts or brownouts or to otherwise remotely control electrical devices. The system (300) includes a number of smart receptacles (302) that communicate with a local controller (304), e.g., via power lines using the TCP/IP protocol. The local controller (304), in turn, communicates with a remote controller (308) via the internet. |
| US09160167B2 |
Power supply device
A power supply device includes a fuel-cell power device which supplies a direct current (DC) power to one or more load devices using fuel cells as an input source; and a control unit which controls an output from the fuel-cell power device. In the power supply device, when a load current supplied to the load device is changed, an output characteristic of the fuel-cell power device is shifted so that a rate of change in an output current of the fuel-cell power device becomes lower than a preset value. With the power supply device, even though the fuel-cell is used as a power source, a DC power supplied to the load devices can be gradually changed and therefore reduce environmental load. |
| US09160164B2 |
Method and apparatus for fault detection of series diodes in rectifiers
A method and apparatus for fault detection of series diodes in rectifiers is disclosed, wherein the voltages across one or both of the individual diodes, and/or the voltage across the pair of diodes are measured to determine a ratio between two of those voltages. The ratio is then analyzed to determine if a fault (e.g., a short circuit or an open circuit) is present. In some embodiments, circuitry can be included to compensate for the normal variations in diode characteristics (e.g., reverse leakage current, reverse recovery charge) between the pair of series diodes to minimize the potential for erroneous fault detection. |
| US09160163B2 |
Battery management system, motor vehicle and battery system
The present disclosure relates to a battery management system for at least one battery cell, for example a lithium-ion battery cell, and to a motor vehicle and to a battery system. A battery management system for at least one battery cell is configured in such a way that, in reaction to a triggering signal, said battery management system can make available a current path between poles of the at least one battery cell. In this context, the current path is configured in such a way that by making available the current path a light arc in a fuse of the at least one battery cell after the triggering of the fuse is prevented or ended. This increases the protection against hazards which can arise from a battery cell in hazardous situations for a vehicle. |
| US09160159B2 |
Circuit breaker and method of controlling a power transistor with a circuit breaker
An embodiment of an apparatus, such as a circuit breaker, includes an input node, an output node, and a digital circuit. The input node is configured to receive an input voltage, and the output node is coupled to the input node and is configured to carry an output current. And the digital circuit is configured to uncouple the output node from the input node in response to a power drawn from the input node exceeding a threshold. |
| US09160157B2 |
Electronic circuit
An electronic circuit is provided that has a function of protecting an IC element (10) from excess current cause by latch-up. The electronic circuit includes an IC element (10) having a terminal (N1) connecting to power voltage (VCC) and a terminal (N2) connecting to ground voltage, and an automatic reset fuse (11) that is connected to either of the terminals. |
| US09160153B2 |
Side-open wet-location electrical box and cover
An electrical box includes a back wall and a front wall, configured to be essentially parallel to a mounting surface when the base is installed to the mounting surface, and a pair of interchangeable top and bottom walls. Each interchangeable top and bottom wall is connected to the back wall and the front wall. The electrical box includes a side wall connected to each of the other walls and an open end opposite the side wall that is configured to receive an electrical device therein. A standoff extends laterally from the back wall. The standoff is configured to provide a mounting structure and to position the electrical box away from the mounting surface. The electrical box is configured to receive a top-mounted hood to cover the open end when the base is installed with the open end positioned to face either of the right side or the left side. |
| US09160148B2 |
Method of manufacturing spark plug
A method for manufacturing a spark plug includes: a preparation step of preparing a specimen provided with a center electrode, an insulator, a metal shell, and a ground electrode; and an inspection step of applying a predetermined voltage between the ground electrode and the center electrode of the prepared specimen, and determining whether dielectric breakdown is caused in the insulator. The inspection step includes a calculation step and a judgment step. The calculation step involves receiving an oscillating wave generated from the specimen upon application of the predetermined voltage to the specimen, obtaining a power spectrum by subjecting an oscillating wave signal representing the oscillating wave to fast Fourier transform, and then calculating an integral of a predetermined frequency range in the power spectrum. In the judgment step, whether discharge is caused by dielectric breakdown of the insulator is judged by utilizing the integral. |
| US09160147B2 |
Spark plug and manufacturing method for same
A spark plug having excellent load life performance, and a method of manufacturing the same, the spark plug having a connecting portion which electrically connects a center electrode and a metallic terminal within the axial hole of an insulator, the connecting portion including a resistor whose porosity is 5.0% or less. |
| US09160146B2 |
Spark plug
A spark plug includes an electrode wherein a plurality of fusion regions are formed by melting to each other a circular noble metal tip having a diameter of not less than 2 mm and a base material disposed around an outer periphery of the noble metal tip. In a particular tip cross section, a total length of the portions passing the fusion region on the circumference of a circle A concentric to an outline of the tip and having a diameter of 90% of the length of the tip is not less than 30% of the length of the circumference of the concentric circle A, and a total length of the portions on which a circumference of a concentric circle B, having the same diameter as that of the outline passes, is not less than 30% of the length of the circumference of the concentric circle B. |
| US09160144B2 |
Spark plug with internal resistor having Ti and Zr components
A spark plug with both improved load life performance and improved radio-noise-preventing property, wherein the spark plug has a resistor containing a Ti component. The spark plug includes a circular columnar insulator having a through hole; a center electrode; a terminal shell; and a resistor provided in the through hole and between the terminal shell and the center electrode. The resistor contains glass, a Ti component, a Zr component, and a non-metallic electrically conductive material. |
| US09160141B2 |
Method for controlling wavelength-tunable laser
The method for controlling a wavelength-tunable laser comprises a first step of acquiring a driving condition of the wavelength-tunable laser for laser oscillation at a first wavelength, and a second step of calculating according to the driving condition of the first wavelength and a wavelength difference between the first wavelength and a second wavelength different from the first wavelength a control value or target value of a wavelength characteristic of the second wavelength in the wavelength detection unit, so as to calculate a driving condition for driving the wavelength-tunable laser, the second step including a step of selecting according to the wavelength difference one of etalon slopes having respective gradients identical and opposite to a gradient of an etalon slope used for controlling the first wavelength. |
| US09160140B2 |
Optical pulse transmitter
It is disclosed a method for driving a laser diode such as to enable mitigation or elimination of so called spiking effects related to the number of injected carriers in the laser overshooting the equilibrium value at the beginning of the lasing process. In this manner, among other things, the efficiency of a master oscillator power amplifier that may be utilized in range finding applications will be improved. It is further disclosed an optical pulse transmitter comprising such a laser diode. |
| US09160138B2 |
Light-emitting element array
A light-emitting element array includes light-emitting elements that emit light in a direction perpendicular to a substrate. Each light-emitting element includes the substrate, a first nitride semiconductor layer on the substrate and having a mesa portion, an active layer made of a nitride semiconductor disposed on the surface of the mesa portion of the first semiconductor layer opposite the substrate, a second nitride semiconductor layer on the active layer, and a heat radiation layer disposed so that the surface formed by projecting the heat radiation layer on a plane perpendicular to the optical axis of the light-emitting element does not overlap with the surface formed by projecting the mesa portion on the same plane when viewed in the optical axis direction. When the light-emitting element is projected on a plane perpendicular to the optical axis, the surface has an area in a specific range. |
| US09160136B1 |
External diffusion amplifier
A first amplification structure uses a single pass external diffusion amplifier wherein the picosecond beam cross-sectional area is matched to the cross-sectional area of the gain medium. A half waveplate between the gain medium and the incoming beam optimizes the polarization of the beam diameter to the polarization of the gain medium. A second amplification structure uses a double pass external diffusion amplifier wherein the beam cross-sectional area is matched to the cross-sectional area of the gain medium and passed twice therethrough. A half waveplate and a rotator create a right circular polarized beam through the gain medium and a maximum “R” coated reflector resides beyond the external diffusion amplifier and reflects a left circular polarized beam back through the gain medium, the rotator and the half waveplate where it becomes horizontally polarized and is then transmitted out of the amplification structure by the polarization sensitive beam splitter. |
| US09160135B2 |
Optical amplifying apparatus and optical transmission system
An optical amplifying apparatus that amplifies a wavelength-division multiplexed (WDM) optical signal includes an input section, a laser light source, a double-clad optical fiber, a gain equalizer, and a residual pump light attenuating section that attenuates a residual pump light outputted from the double-clad optical fiber. The residual pump light attenuating section is disposed such that the residual pump light of the laser light is incident on the residual pump light attenuating section before being incident on an isolator. |
| US09160134B2 |
Laser
A laser includes a total reflective mirror, an output mirror, a discharge lamp, and an active laser medium. The total reflective mirror, the output mirror, and the discharge lamp define a resonant cavity. The active laser medium is filled in the resonant cavity. The total reflective mirror includes a microstructure. The microstructure is convex ring-shaped structure. The convex ring-shaped structure has a height and a width, and both the height and the width are in a range from about 0.5λ to about 2λ, while λ is a working wavelength of the laser. |
| US09160132B2 |
Laser apparatus, light therapy apparatus, exposure apparatus, device manufacturing method, and object inspection apparatus
The present invention greatly reduces the likelihood that fiber fusion will occur. A laser apparatus comprises an excitation light source and an optical amplifier unit, which optically amplifies by receiving excitation light that is output from the excitation light source and that transits an optical fiber. A monitor unit monitors the power level of the excitation light transmitted from the excitation light source to the optical amplifier unit side via the optical fiber. At the initial start of the output of the excitation light from the excitation light source, once the excitation light is being output at the prescribed power level by the excitation light source, the control unit performs control such that the excitation light at a power level higher than the prescribed power level is output if the power level monitored by the monitor unit is greater than or equal to a prescribed value when the excitation light at the prescribed power level is being output from the excitation light source and such that the output of the excitation light is stopped if the power level monitored by the monitor unit is less than the prescribed value when the excitation light at the prescribed power level is being output from the excitation light source. |
| US09160125B2 |
Battery adapter
A battery adapter can include a plurality of machine-side-connecting sections capable of being connected to a plurality of battery-connecting ports provided on an electric machine, and a battery-side-connecting section(s) to which a battery or batteries can be connected. The number of the machine-side-connecting sections is preferably configured to be larger than the number of the battery-side-connecting section(s). Further, the electric machine is preferably connected to the machine-side-connecting sections of the battery adapter through its battery-connecting ports. The electric machine can be driven by the battery or batteries connected to the battery-side-connecting section(s) of the battery adapter. |
| US09160122B2 |
Electrical connector
An electrical connector includes a fixed housing, a movable housing, and socket terminals. Each of the socket terminals includes a movable portion, a base, a front contact-point portion, and a rear contact-point portion. The movable portion includes a first extension, a hairpin portion, and a second extension, and elastically supports the movable housing so as to be displaceable relative to the fixed housing. The base is fixed to the movable housing and continuous with the second extension. The front contact-point portion and the rear contact-point portion extend from the base in an insertion/extraction direction and contact the plug terminal. A cutout portion, which faces the second extension and the hairpin portion, is formed is a side surface of the base adjacent to the movable portion, and at least part of the movable portion is disposed in a recess formed by the cutout portion. |
| US09160121B2 |
High frequency coaxial connector
The invention relates to a high frequency coaxial connector (1) having a first and a second connector part (2, 3). The first connector part (2) comprises an outer conductor (5) and an inner conductor (4) held relative to said outer conductor by means of an insulator (6) and disposed in an opening (11) of the insulator (6). The inner conductor (4) comprises an end piece (8) that is electrically conductively and operatively connected to a connector sleeve (10). The connector sleeve (10) is mechanically operatively connected to the insulator (6) by means of first operative connection means (12, 13), so that the connector sleeve (10) can be tilted relative to the inner conductor (4). An axial displacement can be made possible by means of the active connection to the second connector part (3). |
| US09160117B2 |
Telecommunications patching system that facilitates detection and identification of patch cords
A telecommunications patching system includes a patch panel comprising a plurality of connector ports and a plurality of patch cords configured to selectively interconnect pairs of the connector ports. Each patch cord has opposite ends and a respective connector secured to each end that is configured to be removably secured within a connector port. The connectors of a respective patch cord have the same unique identifier associated therewith. A first sensor is located at each connector port and detects when a patch cord connector is inserted within, and removed from, a respective connector port. A second sensor is located at each connector port and reads the identifier of a patch cord connector inserted within a respective connector port. The first and second sensors are in communication with a controller that monitors and logs patch cord interconnections with the connector ports. |
| US09160113B2 |
Electrical connector with engaging arms formed on cover
An electrical connector includes an insulative housing, a number of contacts retained in the insulative housing and a cover shielding the insulative housing. The insulative housing includes a top wall, a pair of side walls and a plug-receiving cavity formed thereby. Each contact includes a resilient contacting portion extending into the plug-receiving cavity. The cover includes a top plate covering the top wall and a pair of side plates respectively covering the pair of side walls. Each side plate includes an engaging arm extending inwardly therefrom. The insulative housing defines a pair of cutouts formed at boundaries of the top wall and the pair of side walls. The pair of engaging arms extend into the plug-receiving cavity through the pair of cutouts, respectively. |
| US09160112B2 |
Arrangement for protecting against incorrect plugging of plug-in modules
An arrangement for protecting against incorrect plugging of plug-in modules on the front side and rear side of a backplane comprises pairs of guide pin elements with guide pins pointing in opposite directions that extent along a common longitudinal axis perpendicular to the backplane. The guide pin elements engage positively in corresponding guide receptacles of the plug-in modules when they are plugged on in the correct orientation relative to the guide pins. The arrangement comprises means for non-rotatably mounting the guide pin elements on the front side and rear side of the backplane in a predetermined angular position. The two guide pin elements are identical. Arranged between the guide pin elements is a central connecting member that can be inserted in a non-rotatable manner into an attachment hole of the backplane. The connecting member has two molded sections that point in opposite directions and engage positively in commensurately embodied recesses, thus establishing the angular position of the guide pins relative to the backplane. |
| US09160111B2 |
Fully embedded electronic plug-in card
A fully embedded electronic plug-in card pluggable into a slot of a plug-in socket having a plurality of elastic guide arms includes a main body, a plurality of conductive plates and a recessed structure. The main body can be wholly plugged into the plug-in socket without protruding out from the plug-in socket. The conductive plate is mounted onto the main body, and exposed from a side of the main body, and each conductive plate is electrically coupled to each respective elastic guide arm. The recessed structure is disposed on the main body and at a position corresponding to the slot of the plug-in socket. The electronic plug-in card can be plugged into the plug-in socket all the time to save the trouble and inconvenience of plugging the card for use or unplugging the card for removal. |
| US09160110B2 |
Flexible electrical power connection
A motor drive unit including an enclosure, a bus bar supported by the enclosure, at least one modular power unit, and a flexible connector for electrically coupling the modular power unit with the bus bar. The flexible connector includes mating male and female connector portions each mounted to a respective one of the bus bar and the modular power unit, the connector portion mounted to the modular power unit being supported by a housing mounted to the modular power unit for movement relative thereto. |
| US09160108B2 |
Lever connector
A fitting lever (30) includes a pair of lever bodies (31), shaft fitting holes (32) which are formed on opposed inner surface (31a) of a pair of lever bodies (31) and in which lever supporting shafts (11) of a firs connector housing (10) are pivotably fitted, cam grooves (34) which are formed to open at the end edges of the lever bodies (31) at the side of a second connector housing (20) and which act a moving force in a fitting direction on action receiving shafts (23) with the pivoting of the lever bodies (31) when the fitting lever (30) is pivoted while the connector housings are aligned at a fitting start position. |
| US09160104B2 |
Plug-in connector and a plug-in module system
The invention relates to a plug-in connector (1) and a plug-in module system having a first contact casing (10) with a first receptacle (14) and a second contact casing (7) with a second receptacle (8), the first receptacle (14) being designed to receive a socket contact (12) and the second receptacle (8) being designed to receive a plug contact (13), the first receptacle (14) and the second receptacle (8) being formed identically. |
| US09160103B2 |
Terminal device for grounding direct current electrical component
A terminal device used in grounding direct current electrical components, such as audio amplifiers, having a metal contact plate provided with a first opening sized to receive a securing screw and having a second opening sized to receive a locking screw used to attach the terminal device to a metal member of another structure, wherein the first opening is positioned relative to the second opening so that with the securing screw attaching the metal contact plate to a grounding surface, the head of the locking screw will contact and apply anti-rotational forces against the head of the securing screw when the locking screw is also screwed into the grounding surface. |
| US09160102B1 |
Magnetic, self-retracting, auto-aligning electrical connector
Embodiments of the present invention provide an apparatus, a system, and a method of manufacturer for a magnetic, self-retracting, auto-aligning electrical connector. The apparatus includes a first conductor and a first magnet configured to magnetically couple with a second magnet, wherein magnetic coupling causes a change in a magnetic field of a magnetically coupled combination of the first magnet and the second magnet and wherein the change in the magnetic field causes electrical coupling of the first conductor and a second conductor. The system includes a first connector comprising a first magnet and a first conductor and a second connector comprising a second magnet and a second conductor, wherein magnetic coupling causes a change in a magnetic field of a magnetically coupled combination of the first magnet and the second magnet and wherein the change in the magnetic field causes electrical coupling of the first conductor and the second conductor. |
| US09160096B2 |
High speed connector
A connector assembly includes a shell, an insulator held by the shell and a center contact held by the insulator. The center contact has a terminating segment. The connector assembly also includes a compound dielectric surrounding the terminating segment. The compound dielectric is positioned between the terminating segment and the shell. The compound dielectric includes a first dielectric layer that at least partially surrounds the center contact. The compound dielectric also includes a second dielectric layer at least partially surrounding the first dielectric layer. The second dielectric layer has a different dielectric constant than the dielectric constant of the first layer. |
| US09160095B2 |
Connector assembly with connector position assurance stabilizer
A connector assembly having a first connector portion, a second connector portion, and connector position assurance structure. An anti-deflection tab and an anti-deflection protrusion are employed in the connector assembly to control movement of the connector position assurance structure relative to the remainder of the connector assembly. |
| US09160086B2 |
Electrical connectors for use with printed circuit boards
A connector for electrically connecting a first printed circuit board (PCB) with a second PCB wherein, in one example, the connector includes a housing having a keyed feature adapted to mate with a correspondingly keyed feature provided to each of the first and second PCBs and at least one connecting terminal carried by the housing having at least partially exposed opposed ends each of which electrically engages a contact pad formed on an underside of the respective PCBs. The connecting terminal may be arranged to accept a conductor and to thereby electrically couple the conductor to the first and second PCBs. |
| US09160085B2 |
Electrical connector and a connector assembly
A connector assembly and an electrical connector for electrically coupling at least two electrical conductors is provided whereby the connector assembly comprises a support structure wall separating the assembly into a first and a second portion; a conductive wall for providing electrical connectivity between the first and second portions; a first biasing member disposed in the first portion, the first biasing member being adapted to deflect upon a first electrical conductor being inserted into the first portion, the first biasing member being further adapted to bias the first electrical conductor against the conductive wall; and a second biasing member disposed in the second portion, the second biasing member being adapted to deflect upon a second electrical conductor being inserted into the second portion, the second biasing member being further adapted to bias the second electrical conductor against the conductive wall to electrical couple the first and the second electrical conductors. |
| US09160084B2 |
Connector
A housing structure is prevented from becoming complicated. A connector (A) includes: a housing (10) having a terminal accommodation chamber (11); a terminal fitting (20) inserted into the terminal accommodation chamber (11); a lance (14) which can lock the terminal fitting (20) in a detachment prevention state; a front retainer (30); a mold removal space (19) which serves to mold the lance (14); and a detection hole (35) formed in the front retainer (30), allowing insertion of a probe P from the front side and communicating with the terminal accommodation chamber (11) via the mold removal space (19). |
| US09160080B2 |
Electric cable, method for producing an electric cable, and welding device for producing an electric cable
Electric cable 16 having an inner conductor 16a, a primary isolation 16b surrounding the inner conductor 16a, an electric shield 18 surrounding the primary isolation 16b, and a secondary isolation 16c surrounding the shield, wherein at least at one end 22 of the cable 16 the secondary isolation 16c is removed so that the shield 18 is stripped. A contacting of the shield to a vehicle body is electrically and mechanically ensured in that a sleeve 2 is pushed over the stripped shield 18, in that a part of the shield 18 protruding beyond the sleeve 2 in the direction of the end 22 of the cable 16 is put over the sleeve 2, and in that the part of the shield 18 that is put over the sleeve 2 is intermetallically connected to the sleeve 2. |
| US09160076B2 |
Method for direct connection of MMIC amplifiers to balanced antenna aperture
A MMIC amplifier is directly connected to the balanced feed points at the aperture of an antenna to eliminate the distance between electronics coupled to the antenna and the antenna itself, such that interfaces, components and connection lines which introduce losses and parasitic effects that degrade system performance are eliminated due the direct connection. Expanding the aperture of the antenna to accommodate the direct connection of a MMIC amplifier to balanced feed points of an antenna has been found to have no deleterious effects on antenna performance. Moreover, when coupling the MMIC amplifier to an unbalanced coaxial line, any associated ripple is minimized due to the direct connection. |
| US09160073B2 |
Antenna device
An antenna device includes an antenna unit, a power supply terminal and a time constant circuit. The antenna unit includes an antenna element and a variable capacitance element that is variable in capacitance in accordance with a voltage applied to the variable capacitance element, and resonates in such a manner that the antenna element and the variable capacitance element cooperate with each other. The power supply terminal supplies the voltage applied to the variable capacitance element. The time constant circuit gradually increases the voltage applied to the variable capacitance element when a voltage applied to the power supply terminal is changed from an off state to an on state. |
| US09160071B2 |
Active antenna for filtering radio signal in two frequency bands
An active antenna system comprises a coupling block adapted to sample a portion of a first telecommunication signal and a compensation block. The compensation block is coupled to the coupling block and is adapted to apply at least a phase compensation to the portion of the first telecommunication signal, thereby obtaining a first compensation signal. The coupling block is further adapted to combine the first telecommunication signal and the first compensation signal into a compensated first telecommunications signal to be fed into an antenna arrangement. |
| US09160070B2 |
Radiation-hardened RFID tags
RFID tags that must operate in the presence of ionizing radiation need to be radiation hardened in order to achieve reliable operation. This disclosure teaches several RFID tags that achieve radiation hardening without requiring the use of special-purpose radiation-hardened electronic devices. RFID tags typically use an antenna made of metal for achieving reliable radio communications. Radiation hardening is achieved by shaping the antenna such that the metal of the antenna acts as a shield for the radio circuits. |
| US09160069B2 |
Grounded antenna with cross-shaped high-impedance surface metal strips and wireless communication device having said antenna
A grounded antenna may include cross-shaped high-impedance surface metal strips and a wireless communication device having said antenna. The antenna may include an antenna radiation unit and a ground plate and may be set inside of a housing. Multiple high-impedance surface units may be arranged on the ground plate in intervals. |
| US09160068B2 |
Systems and methods for antenna arrangements in an electronic device
Systems and methods are provided for arranging antennas in an electronic device (200). According to one aspect, the electronic device includes a housing (202) and an antenna arrangement. The antenna arrangement includes a first volume (206) positioned adjacent to an edge (212) of the housing, the first volume enclosing a first antenna structure (230) shaped substantially according to a geometry of the edge; a second volume (208) positioned adjacent to a first corner (216) of an opposing edge (214) of the housing, the second volume including a second antenna structure (232) shaped substantially according to a geometry of the first corner; and a third volume (210) adjacent to a second corner (218) of the opposing edge, the third volume including a third antenna structure (234) shaped substantially according to a geometry of the second corner, wherein the first, second, and third volumes do not overlap and are discontinuous. |
| US09160064B2 |
Spatially diverse antennas for a headset computer
The invention presented relates to wireless handsfree head worn headset computing devices including a microdisplay device and spatially diverse antenna system. The spatially diverse antenna system provides an effective headset computing device radiation pattern that enables arbitrary user movement and promotes freedom of mobility. Disclosed is a headset computing device including a head worn frame having a profile relatively low in height with respect to a user's head, the user's head creating a RF shadow region along the headset profile by blocking line-of-sight RF propagation paths, the headset includes two or more antennas integrated with the headset frame to sufficiently maintained its low profile. Each antenna has a radiation pattern and are collectively arranged to form an omnidirectional radiation pattern, where at least a first radiation pattern provides coverage in the line-of-sight propagation path while the at least second radiation antenna pattern is in the RF shadow region. |
| US09160063B2 |
Wearable device assembly having solder mask
A wrist-worn device monitors movements of a user. A curvilinear body of the wrist-worn device includes a plurality of flex areas, and an internal spine member of the wrist-worn device extends through the curvilinear body. A flexible circuit member is wrapped around and connected to the spine member. The flexible circuit member interconnects a controller and one or more sensors of a sensor assembly within the body. A solder mask applied to the flexible circuit member includes a curvilinear edge that distributes stress caused by flexing of the flexible circuit member. |
| US09160061B2 |
Mobile device cover including at least one antenna
Embodiments of systems and methods for providing in-mold laminate antennas are generally described herein. Other embodiments may be described and claimed. |
| US09160059B2 |
Antenna device and mobile terminal
The disclosure provides an antenna device and mobile terminal including such an antenna device. The antenna device includes a coil including a conductor wound around a plate-shaped magnetic core. A flat conductor is positioned adjacent to the coil, and the coil is positioned such that it is closer than the flat conductor to an antenna of a communication partner positioned near the antenna device. The coil conductor includes a first conductor portion adjacent to a first main surface of the magnetic core and a second conductor portion adjacent to a second main surface thereof. The magnetic core and the coil conductor form an antenna coil. A circuit substrate includes a ground electrode formation area and a ground electrode non-formation area. The antenna coil is mounted on the ground electrode non-formation area of the circuit substrate with the first main surface of the magnetic core facing the circuit substrate. |
| US09160058B2 |
Portable communication device
A portable communication device includes an appearance, a substrate and a switchable resonant antenna. The substrate is disposed in the appearance, and the substrate has a ground plane. The switchable resonant antenna comprises a first connection portion, a switching unit, a first metal element and a second metal element, where the first connection portion is electrically coupled between the ground plane and the switching unit, the switching unit is configured to electrically couple the first connection portion to the first metal element or the second metal element according to a control signal generated corresponding to a detecting result, in order to generate a first resonant mode. |
| US09160056B2 |
Multiband antennas formed from bezel bands with gaps
Electronic devices are provided that contain wireless communications circuitry. The wireless communications circuitry may include radio-frequency transceiver circuitry and antenna structures. An inverted-F antenna may have first and second short circuit legs and a feed leg. The first and second short circuit legs and the feed leg may be connected to a folded antenna resonating element arm. The antenna resonating element arm and the first short circuit leg may be formed from portions of a conductive electronic device bezel. The folded antenna resonating element arm may have a bend. The bezel may have a gap that is located at the bend. Part of the folded resonating element arm may be formed from a conductive trace on a dielectric member. A spring may be used in connecting the conductive trace to the electronic device bezel portion of the antenna resonating element arm. |
| US09160055B2 |
Wireless device
According to one embodiment, a wireless device is provided with a semiconductor chip, a substrate, an antenna, and a sealing material. The chip includes a wireless circuit. The substrate has a plurality of terminals arranged on a first surface and the chip arranged on a second surface. The antenna includes a radiation element and is electrically connected to the chip. The sealing material seals the chip and the antenna. A distance between a first wall of the sealing material substantially parallel to the second surface and the radiation element is equal to or more than a distance between a second wall of the sealing material substantially perpendicular to the second surface and the radiation element. |
| US09160054B2 |
Radio frequency identification tag and diaper, absorber and sensing system using the same
A radio frequency (RF) identification tag including a substrate, a planar antenna, an RF chip, a plurality of signal conductors and a plurality of ground conductors is provided. The RF chip receives an RF signal from the planar antenna to generate an identification code. The signal conductors are coupled to the planar antenna. The ground conductors, interlaced on two opposite sides of the signal conductors, and the signal conductors are adjacent to each other and disposed on the substrate to form a coplanar waveguide structure which includes an impedance match portion and a transmission portion. The impedance match portion has an input end coupled to the signal conductors and a ground plane coupled to the ground conductors. The RF chip is disposed between the input end and the ground plane. The transmission portion is connected between the impedance match portion and the planar antenna. |
| US09160049B2 |
Antenna adapter
An antenna adapter, for an antenna with a recessed adapter seat with a feed bore is provided as a base with a feed aperture, the base dimensioned to seat within the adapter seat, the feed aperture aligned coaxial with the feed bore. The base may be provided with interlock cavities dimensioned to receive retaining elements of the adapter seat as the base is inserted into the adapter seat, retaining the base within the adapter seat. The base may include a coupler cavity, coupling the feed aperture to two or more output ports. The coupler cavity may have sidewall slots. |
| US09160047B2 |
Coupling apparatus for dividing receiving and transmitting signals and control method thereof
The present invention is directed to a coupling apparatus for dividing a radio frequency (RF) transmitting signal and an RF receiving signal in a transceiver with a transmitting unit and a receiving unit sharing an antenna, comprising: a four-port circuit having ports 1-4; a through path formed between the port 1 and the port 2; a first signal input to the port 1 being coupled to the port 4; a second signal input to the port 2 being coupled to the port 3; an isolation path formed between the port 1 and the port 3 and between the port 2 and the port 4; an attenuator attenuating a signal output from the port 4; and wherein the RF transmitting signal is input to the port 1, the RF receiving signal is input to the port 2, and outputs of the port 3 are provided to the receiving unit. |
| US09160045B2 |
Reconfigurable bandpass filter based on a planar combline filter comprising varactor diodes
A reconfigurable bandpass filter including at least a tunable planar combline filter including varactor diodes arranged on a carrier board. For automatic calibration of adjustment of blocking voltage during operation, the reconfigurable bandpass filter includes a filter control offering an external abstracted interface. A memory is connected with the filter control. The memory stores calibration data. For approximating of the best possible filter characteristic, the filter control determines, based on memorized data, the best configuration of tuning voltages.The reconfigurable bandpass filter can be used in the field of secondary radar systems. |
| US09160044B2 |
Millimeter waveband filter and method of manufacturing the same
A transmission line which allows electromagnetic waves in a predetermined frequency range of a millimeter waveband to propagate in a TE10 models formed by a first waveguide and a second waveguide. A resonator is formed by electric wave half mirrors fixed to the first waveguide and the second waveguide. The second waveguide has a structure in which a first transmission line forming body has a plate shape and has a square hole forming the first transmission line formed to pass therethrough from one surface toward an opposite surface, a second transmission line forming body has a plate shape and has a square hole forming the second transmission line formed to pass therethrough from one surface toward an opposite surface, and the first transmission line forming body and the second transmission line forming body are connectable and separable. |
| US09160041B2 |
Battery heating circuits and methods using resonance components in series and bridging charge storage components
According to certain embodiments, a battery heating circuit is provided, comprising a first switch unit 11, a second switch unit 12, a third switch unit 13, a fourth switch unit 14, a switching control module 100, a damping component R1, a current storage component L1, and a charge storage component C1; the damping component R1 and the current storage component L1 are configured to connect with the battery in series to form a branch; the first switch unit 11 and the second switch unit 12 are connected in series with each other and then connected in parallel with the branch; the third switch unit 13 and the fourth switch unit 14 are connected in series with each other and then connected in parallel with the branch. |
| US09160038B2 |
Battery assembly
A battery module of the present invention is adaptable to be utilized in various configurations including and not limited to an overlapping battery cell packaging configuration and a vertical stack battery cell packaging configuration used in an automotive vehicle. The battery module has a plurality of battery heatsink assemblies with the cells disposed therebetween. A plurality of rods extend through the each heatsink assemblies to secure the heatsink assemblies and the cell with one another to form the battery module. |
| US09160034B2 |
Method for producing sulfide solid electrolyte material and method for producing lithium solid state battery
A method for producing a sulfide solid electrolyte material having a small amount of hydrogen sulfide generation and a high Li ion conductivity. To achieve the above, a method for producing a sulfide solid electrolyte material is provided, including steps of: a providing step for providing a crystallized sulfide solid electrolyte material prepared by using a raw material composition containing Li2S and P2S5; and an amorphizing step for applying amorphization treatment to the crystallized sulfide solid electrolyte material. |
| US09160029B2 |
Secondary battery including a can having first and second stepped portions having different depths
A secondary battery includes an electrode assembly; a can having an opening configured to receive the electrode assembly, wherein the can includes a first stepped portion and a second stepped portion on an inner surface adjacent to the opening and wherein the first and second stepped portions have different depths; a cap assembly comprising a cap plate hermetically sealing the opening of the can; and an insulation case located between the electrode assembly and the cap assembly. |
| US09160026B2 |
Gas flow passage forming member, method of manufacturing the gas flow passage forming member, and device for forming the gas flow passage forming member
An MEA 15 is arranged between frames 13, 14. A first gas flow passage forming member 21 is arranged between an anode electrode layer 17 of the MEA 15 and a first separator 23 fixed to an upper surface of the frame 13. A second gas flow passage forming member 22 is arranged between a cathode electrode layer 18 of the MEA 15 and a second separator 24 fixed to a lower surface of the frame 14. The gas flow passage forming members 21, 22 are each formed by a metal lath 25. The metal lath is formed by forming a plurality of through holes 26 in a thin metal plate in a mesh-like manner and forming the thin metal plate in a stepped shape. The gas flow passage forming members 21, 22 each include a plurality of annular portions 27 forming the through holes 26. Each of the annular portions 27 has a flat surface portion 28a in a first contact portion 28, which contacts a carbon paper 19, 20. |
| US09160025B2 |
Flow battery systems
Embodiments of the invention generally provide for flow battery cells and systems containing a plurality of flow battery cells, and methods for improving metal plating within the flow battery cell, such as by flowing and exposing the catholyte to various types of cathodes. In one embodiment, a flow battery cell is provided which includes a cathodic half cell and an anodic half cell separated by an electrolyte membrane, wherein the cathodic half cell contains a plurality of cathodic wires extending perpendicular or substantially perpendicular to and within the catholyte pathway and in contact with the catholyte, and each of the cathodic wires extends parallel or substantially parallel to each other. In some examples, the plurality of cathodic wires may have at least two arrays of cathodic wires, each array contains at least one row of cathodic wires, and each row extends along the catholyte pathway. |
| US09160022B2 |
Systems and methods providing a wearable power generator
A wearable, hybrid power generation system includes a rechargeable battery, a solid fuel cell power generator coupled to the rechargeable battery, and a cartridge with fuel for the solid fuel cell power generator. The cartridge is removeably coupled to the solid fuel cell power generator. The rechargeable battery, the solid fuel cell power generator, and the cartridge may be housed in a form factor conforming to a shape and size of a standard battery. |
| US09160020B2 |
Fuel cell
An electrode structure 15 is received in a joint portion of frames 13, 14. A first gas diffusion layer 19 and a first gas passage forming member 21 are arranged on a first surface of the electrode structure 15. A second gas diffusion layer 20 and a second gas passage forming member 22 are formed on a second surface of the electrode structure 15. A separator 23 is joined with a surface of the frame 13 and a surface of the gas passage forming member 21. A separator 24 is joined with a surface of the frame 14 and a surface of the gas passage forming member 22. A water passage 28 is formed between a flat plate 25 of the gas passage forming member 22 and the separator 24. The water passage 28 has a depth set to a value smaller than depth of a gas passage T2 of the gas passage forming member 22. Generated water is introduced from the gas passage T2 of the gas passage forming member 22 to the water passage 28 through capillary action via communication holes 29. The generated water in the water passage 28 is moved to a downstream side of the water passage 28 by pressure caused by oxidization gas. This prevents corrosion of the cathode side electrode catalyst layer and improves durability of the anode side gas passage forming member. As a result, a fuel cell capable of preventing decrease of power generation is provided. |
| US09160017B2 |
Fuel cell startup apparatus comprising emergency air supplier and method
Disclosed is a fuel cell startup apparatus and method, particularly, a fuel cell startup method, by which in an emergency situation such as when a high-voltage battery mounted on a fuel cell vehicle is completely discharged, fuel cell startup can be achieved without assistance of a high-voltage power source. To this end, an air supply port, which is connected to an emergency air supplier, is formed on an air supply line configured to supply air to a cathode of a fuel cell stack, and the emergency air supplier supplies the air to the fuel cell stack when complete discharge of a high-voltage battery and is removably engaged to the air supply port. |
| US09160015B2 |
Humidifier for fuel cell
Disclosed is a humidifier for fuel cell including a membrane housing including a first end, a second end positioned at an opposite side of the first end, and plural holes provided along the outer circumferential surface of the second end; hollow fiber membranes having both ends respectively potted into the first and second ends of the membrane housing, wherein the hollow fiber membranes are positioned inside the membrane housing; and a cap including an inlet for moisture-containing unreacted gas, wherein the cap is installed at the second end of the membrane housing, and an inner surface of the cap is provided with plural projections enabling the moisture-containing unreacted gas supplied through the inlet to be uniformly distributed to the plural holes. |
| US09160009B2 |
Compact and low-volume mechanical igniter and ignition systems for thermal batteries and the like
An ignition system for a thermal battery where the ignition system includes: a base plate for connection to the thermal battery; and two or more inertial igniters formed on the base plate, each of the two or more inertial igniters having a striker mass which ignites one or more pyrotechnic materials upon a predetermined acceleration profile, the base plate having an opening corresponding to each of the two or more inertial igniters for allowing a generated spark to pass into the thermal battery. |
| US09160002B2 |
Lead-acid battery
In a valve-regulated lead-acid battery in which charging is performed intermittently on every short time and high rate discharging to a load is performed in a partial state of charge (PSOC), a valve-regulated lead-acid battery improved for the charge acceptance and the life characteristic under PSOC than usual is provided. A positive electrode plate having a specific surface area of an active material of 5.5 m2/g or more is used. A valve-regulated lead-acid battery is manufactured by using a negative electrode plate improved for the charge acceptance and the life performance by adding a carbonaceous electroconductive material and a formaldehyde condensate of bisphenols aminobenzene sulfonic acid to a negative electrode active material and setting the specific gravity of an electrolyte to 1.30 or more and 1.35 or less. |
| US09160000B2 |
Active material for battery, and battery
An active material for a battery, which has high thermal stability and low electric potential. According to the invention, an active material for a battery including an M element in Group III, a Ti element, an O element, and an S element and having an M2Ti2O5S2 crystalline phase is provided to solve the problem. |
| US09159998B2 |
Positive electrode active material for lithium secondary battery, and use thereof
A positive electrode active material provided in the present invention is characterized in that it is substantially formed of a lithium nickel cobalt manganese composite oxide and that a molar content ratio (NiIII/NiII) of bivalent nickel atoms (NiII) and trivalent nickel atoms (NiIII) of nickel atoms constituting the composite oxide is 0.15≦(NiIII/NiII)≦0.95. |
| US09159997B2 |
Nonaqueous electrolyte battery, electrode for the same, and battery pack
According to one embodiment, there is provided an electrode for a nonaqueous electrolyte battery. The electrode includes an active material layer. The active material layer includes a monoclinic β-type titanium composite oxide. When the electrode is subjected to an X-ray diffraction measurement using a Cu-Kα ray source, a ratio of a reflection intensity I(020) of a peak derived from a plane (020) of a crystal of the monoclinic β-type titanium composite oxide to a reflection intensity I(001) of a peak derived from a plane (001) of the crystal of the monoclinic β-type titanium composite oxide being in the range from 0.6 to 1.2. |
| US09159990B2 |
High capacity lithium ion battery formation protocol and corresponding batteries
Battery formation protocols are used to perform initial charging of batteries with lithium rich high capacity positive electrode to result a more stable battery structure. The formation protocol generally comprises three steps, an initial charge step, a rest period under an open circuit and a subsequent charge step to a selected partial activation voltage. The subsequent or second charge voltage is selected to provide for a desired degree of partial activation of the positive electrode active material to achieve a desired specific capacity while providing for excellent stability with cycling. The formation protocol is particularly effective to stabilize cycling for compositions with moderate lithium enrichment. |
| US09159989B2 |
All-solid battery and method of manufacturing the same
The all-solid battery has two electrode layers of a positive electrode and a negative electrode interposing a solid electrolyte layer therebetween, in which at least one of the electrode layers is composed of a sintered body of a mixed material including at least one or more types of electrode active material particles comprising electrode active material and solid electrolyte particles comprising solid electrolyte, and a portion of at least 30% by area of a grain boundary surrounding the electrode active material particles has a coating layer with a thickness of 1 to 200 nm. |
| US09159979B2 |
Nonwoven fabric having cross-linking material
A layer includes a main body having a plurality of first pores and at least one crosslinked binder. |
| US09159974B2 |
Battery pack and electric bike having the same
Provided is an food packing material, manufacturing method. A battery pack and a electrical bike having the same are further provided. In particular, the battery pack may include a battery pack, battery array, a protecting circuit module, and a connection terminal section. The battery case may be formed as cylindrical or polygon. The battery array may include a plurality of batteries formed as multi-stage within the battery pack. The protecting circuit module may be provided between an upper portion of the battery array and an upper surface of the battery pack. A connection terminal portion may be formed at the lower stage of the battery pack and may include a power terminal and a control terminal. By providing the battery pack as bottle shape, the electrical bike can selectively accommodate the bottle for the bike and the battery pack. |
| US09159970B2 |
Battery pack and electrically powered vehicle including the battery pack
Provided is a battery pack that can uniformly cool a plurality of electric cells, prevent a breakdown of the electric cells, and provide high performance of all electric cells. The battery pack includes a packaging case in which: each adjacent ones of a plurality of electric cells in the first direction define a ventilation space; first and second passages are defined that extend in the first direction and that are arranged to have the plurality of electric cells located between the first and second passages in a second direction intersecting the first direction, wherein gas supplied to the first passage flows through the ventilation spaces to the second passage; and a flow rate limitation device is provided that is arranged in an upstream area of the first passage and that limits a flow rate of the gas flowing through one of the plurality of ventilation spaces, which leads to the upstream area of the first passage, to a predetermined flow rate. |
| US09159969B2 |
Laminate strengthened battery pack and method of manufacturing the same
A battery pack and a method of manufacturing the same. The battery pack includes: a package member formed of a laminate strengthened sheet; and a support plate coupled to at least a portion of the package member to form a case having a space for receiving an electrode assembly. The manufacturing method of the battery pack includes: forming an electrode assembly; forming a case for receiving the electrode assembly by coupling a solid support plate to at least a portion of a package member formed of a laminate strengthened sheet; inserting the electrode assembly into the case; and electrically connecting the electrode assembly to a terminal assembly. |
| US09159964B2 |
Solid state battery having mismatched battery cells
A solid-state, mismatched battery comprises a first battery cell having a first internal resistance, and a second battery cell having a second internal resistance, the second internal resistance being a predefined resistance that is less than the first internal resistance. One or more of electrical connectors electrically couple the first and second battery cells. A casing encloses the first and second battery cells. A pair of terminals is electrically coupled to the first and second battery cells to output electrical power to an external load. |
| US09159961B2 |
Case of secondary battery including a bead
A secondary battery includes a case, the case including a first side having a bead thereon, the bead having a height h and a width w, a ratio of the height h to the width w satisfying 2 % ≤ ( h w × 100 ) ≤ 50 % , h and w being in a same unit of measure, and an electrode assembly in the case, the electrode assembly including a first electrode, a second electrode, and a separator disposed between the first and second electrodes. |
| US09159955B1 |
Method and apparatus for patterning an organic device
A method for patterning an organic device includes providing a patterned product substrate and pre-defined patterned source substrate. The product substrate has a product principal surface having destination regions. The source substrate has a source principal surface having optically reflecting regions and absorbing regions arranged adjacent to each other. The source principal surface includes plurality of source regions defined at the reflecting regions. The plurality of source regions has organic materials disposed thereon. The product principal surface and the source principal surface are aligned such that each of the plurality of source regions is aligned to exactly one destination region. At least one of the product principal surface and the source principal surface includes support(s) to maintain a substantially uniform gap between them. Then temperature of the source substrate is raised above the sublimation temperature of the organic materials to redeposit at a nearest destination region. |
| US09159951B2 |
Organic electroluminescence display device and method of manufacturing organic electroluminescence display device
The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer. |
| US09159949B2 |
Organic electroluminescent display device and method of fabricating the same
An organic electroluminescent display device includes a first electrode on a substrate, an organic layer including a light-emitting layer on the first electrode, a second electrode including lower and upper conductive layers sequentially stacked on the organic layer, and an insulating pattern extending into the organic layer through the lower conductive layer. |
| US09159947B2 |
Organic light-emitting device
An organic light-emitting device, including a first electrode, the first electrode having a smaller absolute value of a work function energy level than an absolute value of a work function energy level of ITO, a second electrode facing the first electrode, and an organic layer between the first electrode and the second electrode. |
| US09159945B2 |
System and method for matching electrode resistances in OLED light panels
Provided are an OLED device and a method of manufacturing the OLED device that may provide improved luminance uniformity. The disclosed OLED may have a first electrode that has a first sheet resistance Rs, and a second electrode that has a second sheet resistance, wherein the second sheet resistance may be in the range of 0.3Rs-1.3Rs. In addition, the disclosed OLED may have a plurality of equal potential difference between points on a first electrode and a second electrode. The equal potential difference may be provided by a gradient resistance formed on at least one of the electrodes. |
| US09159944B2 |
White organic light-emitting diodes
In an embodiment of the present disclosure, a white organic light-emitting diode is provided. The white organic light-emitting diode includes an anode, a cathode, and a composite light-emitting layer formed between the anode and the cathode, the composite light-emitting layer including a first host layer, a second host layer, and a dye layer formed between the first host layer and the second host layer, and the dye layer including at least two dyes. |
| US09159939B2 |
Photoelectric conversion device
Provided is a photoelectric conversion device with high conversion efficiency in which the light loss due to light absorption in a window layer is significantly reduced by using a light-transmitting semiconductor layer comprising an organic compound and an inorganic compound. Specifically, the photoelectric conversion device includes: over one surface of a crystalline silicon substrate, a first silicon semiconductor layer; a light-transmitting semiconductor layer; a second silicon semiconductor layer which is partially formed on the light-transmitting semiconductor layer; and a first electrode. The photoelectric conversion device further includes: a third silicon semiconductor layer on the other surface of the crystalline silicon substrate; a fourth silicon semiconductor layer formed on the third silicon semiconductor layer; and a second electrode formed on the fourth silicon semiconductor layer. The light-transmitting semiconductor layer is formed using an organic compound and an inorganic compound, which contributes to the high light-transmitting property of the window layer. |
| US09159936B2 |
Organic electroluminescent material containing iridium, preparation method thereof and organic electroluminescent element
Organic electroluminescent material containing iridium of the following general formula, in which R is C1-C8 alkyl, is provided. The preparation method of the above organic electroluminescent material containing iridium and the organic electroluminescent element using the above organic electroluminescent material containing iridium are also provided. |
| US09159931B2 |
Aromatic amine derivative and electroluminescence device using the same
Provided are a novel aromatic amine derivative having a specific structure and an organic electroluminescence device in which an organic thin layer comprising a single layer or plural layers including a light emitting layer is interposed between a cathode and an anode, wherein at leas one layer of the above organic thin layer contains the aromatic amine derivative described above in the form of a single component or a mixed component. Thus, the organic electroluminescence device is less liable to be crystallized in molecules, improved in a yield in producing the organic electroluminescence device and extended in a lifetime. |
| US09159930B2 |
Formulations and electronic devices
The present invention relates to a formulation comprising at least one solvent and at least two functional compounds of the general formula (I) where A is a functional structural element, B is a solubility-promoting structural element and k is an integer in the range from 1 to 20, the molecular weight of the functional compound is at least 550 g/mol and the solubility-promoting structural element B conforms to the general formula (L-I) where Ar1, Ar2 is each, independently of one another, an aryl or heteroaryl group, which may be substituted by one or more radicals R of any desired type, X is in each case, independently of one another, N or CR2, preferably CH, R1, R2 is each, independently of one another, hydrogen, a straight-chain alkyl, alkoxy or thioalkoxy group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkoxy group having 3 to 40 C atoms or is a silyl group or a substituted keto group having 1 to 40 C atoms, an alkoxycarbonyl group having 2 to 40 C atoms, an aryloxycarbonyl group having 7 to 40 C atoms, a cyano group (CN), a carbamoyl group (C(═O)NH2), a haloformyl group (C(═O)—X, in which X represents a halogen atom), a formyl group (C(═O)—H), an isocyano group, an isocyanate group, a thiocyanate group or a thio-isocyanate group, a hydroxyl group, a nitro group, a CF3 group, Cl, Br, F, a crosslinkable group or a substituted or unsubstituted aromatic or heteroaromatic ring system having 5 to 60 ring atoms, or an aryloxy or heteroaryloxy group having 5 to 60 ring atoms, or a combination of these systems, where one or more of the groups R1 and/or R2 may form a mono- or polycyclic, aliphatic or aromatic ring system with one another and/or with the ring to which the group R1 is bonded; and l is 0, 1, 2, 3 or 4; where the dashed bond indicates the bond to the functional structural element A. The present invention furthermore relates to electronic devices which comprise mixtures of these compounds. |
| US09159928B2 |
Amine-oxide-group-containing conjugated polymer photoelectric material and use thereof
Disclosed are an amine-oxide-group-containing conjugated polymer photoelectric material and application thereof. The amine-oxide-group-containing conjugated polymer photoelectric material consists of conjugated main chains and a side chain containing an amine oxide unit, and is applied in an organic photoelectric device. The material has desirable alcohol/water solubility and photoelectric properties, is suitable for making a multi-layer solution for machining a device, and meanwhile can prevent an adverse effect incurred by freely moving counter ions in a common polyelectrolyte to the device. The material may be used as a cathode interface modification layer applied in organic photoelectric devices such as light-emitting and photovoltaic devices, so as to improve performance of the devices. |
| US09159925B2 |
Process for imprint patterning materials in thin-film devices
The present disclosure provides a method for patterning materials that are or are on top of chemically sensitive organic semiconductors. The method employs imprint lithography and a bilayer resist structure that simultaneously protects lower layers from harmful solvents and allows for cleaner liftoff by producing an undercut geometry to the resist pattern. |
| US09159921B2 |
Resistive memory cell
Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions. |
| US09159919B2 |
Variable resistance memory device and method for fabricating the same
A variable resistance memory device includes vertical electrodes vertically projecting from a substrate, first horizontal electrodes stacked along the vertical electrodes, second horizontal electrodes stacked along the vertical electrodes, and a variable resistance layer interposed between the vertical electrodes and the first and second horizontal electrodes, wherein the first and second horizontal electrodes are arranged in directions crossing with each other. |
| US09159917B2 |
Nonvolatile memory element and method of manufacturing nonvolatile memory element
A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer between the first and second electrodes. The variable resistance layer having a resistance value that reversibly changes according to an electrical signal provided between the electrodes. The variable resistance layer includes a first variable resistance layer and a second variable resistance layer. The first variable resistance layer comprises a first metal oxide. The second variable resistance layer is planar and includes a first part and a second part. The first part comprises a second metal oxide and is planar. The second part comprises an insulator and is planar. The second metal oxide has a lower oxygen deficient degree than that of the first metal oxide. The first and second parts are in contact with different parts of a main surface of the first variable resistance layer which faces the second variable resistance layer. |
| US09159915B2 |
Phase change memory with threshold switch select device
An ovonic threshold switch may be formed of a continuous chalcogenide layer. That layer spans multiple cells, forming a phase change memory. In other words, the ovonic threshold switch may be formed of a chalcogenide layer which extends, uninterrupted, over numerous cells of a phase change memory. |
| US09159914B2 |
Nonvolatile memory devices and methods of forming the same
A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen. |
| US09159910B2 |
One-mask MTJ integration for STT MRAM
A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit. |
| US09159907B2 |
Hybrid film for protecting MTJ stacks of MRAM
A method includes patterning a plurality of magnetic tunnel junction (MTJ) layers to form a MTJ stack, and forming a first dielectric cap layer over a top surface and on a sidewall of the MTJ stack. The step of patterning and the step of forming the first dielectric cap layer are in-situ formed in a same vacuum environment. A second dielectric cap layer is formed over and contacting the first dielectric cap layer. |
| US09159905B2 |
Electronic device, electronic apparatus, mobile unit, and method of manufacturing electronic device
A vibrating element as an element on which a base part, a supporting part extending from the base part, and adjustment electrodes as mass adjustment parts are provided and a semiconductor substrate as a circuit element are provided, and the adjustment electrodes are placed in locations not overlapping with the semiconductor substrate in a plan view, the supporting part and the semiconductor substrate are connected, and thereby, the vibrating element is mounted on the semiconductor substrate. |
| US09159904B2 |
Piezoelectric ceramic composition
This invention provides for a piezoelectric ceramic composition having a lead-free alkaline niobate piezoelectric ceramic composition with a favorable piezoelectric property. This invention refers to a piezoelectric ceramic composition 10 that is described as composition formula {Lix(K1-yNay)1-x}(Nb1-zSbz)O3 including the additives of the metallic elements Bi and Fe within the range of the following relational expressions: 0.03≦x≦0.045; 0.5≦y≦0.58; 0.03≦z≦0.045; and 0.006≦v≦w≦0.010 whereof v is the additive amount of Bi (molar ratio), and w is the additive amount of Fe (molar ratio). |
| US09159901B2 |
Composite substrate and elastic wave device
A composite substrate 10 is a substrate formed by bonding a piezoelectric substrate 12 and a support substrate 14 having a coefficient of thermal expansion lower than that of the piezoelectric substrate 12. The support substrate 14 has a first surface 14a bonded to the piezoelectric substrate 12 and a second surface 14b opposite to the first surface 14a. The coefficient of thermal expansion of the support substrate 14 is decreased along a thickness direction from the second surface 14b to an intermediate position 14c located between the first surface 14a and the second surface 14b. |
| US09159896B2 |
Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods
Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials. |
| US09159892B2 |
LED light source device and manufacturing method for the same
An object of the invention is to provide an LED light source device and a manufacturing method for the same that can maintain high reflectance over an extended period of time notwithstanding the interaction between light and heat. More specifically, the invention provides an LED light source device that includes a substrate, an electrode formed on the substrate, a white inorganic resist layer deposited over the substrate so as to cover a surface thereof everywhere except where the electrode is formed, and an LED element connected to the electrode, wherein the white inorganic resist layer contains fine white inorganic particles dispersed or mixed into an inorganic binder, and a method for manufacturing such an LED light source device. |
| US09159890B2 |
Optoelectronic semiconductor component
An optoelectronic semiconductor component includes one or more light-emitting diode chips. The light-emitting diode chip has a main radiation side. A diaphragm is arranged downstream of the main radiation side along a main radiation direction of the light-emitting diode chip. The diaphragm is mounted on or in a component housing. The main radiation side has a mean edge length of at least 50 μm. The diaphragm can be switched from light-impervious to light-pervious. The diaphragm comprises precisely one opening region for radiation transmission. The semiconductor component can be used as a flashlight for a mobile image recording device. |
| US09159888B2 |
Wafer level phosphor coating method and devices fabricated utilizing method
Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods. |
| US09159885B2 |
Remote phosphor LED device with broadband output and controllable color
A broadband light source includes a phosphor layer excited by light from multiple LEDs. A dichroic reflector reflects light from the LEDs onto the phosphor layer. First and second LEDs are responsible for first and second broadband portions respectively of a broadband output light of the source, each such broadband portion being broadband and nominally white. The device components are configured and arranged so that the first and second broadband light portions have different CIE color coordinates. These portions combine to yield a resultant color for the overall broadband light output of the source, which resultant color is a function of the relative amounts of the first and second broadband light portions. An open-loop or closed-loop controller can independently drive the LEDs to provide a desired mix of the broadband light portions so that the overall broadband light output has a color in a desired design space. |
| US09159880B2 |
Semiconductor light emitting device and method for manufacturing the same
According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. |
| US09159877B2 |
Nano-structured light-emitting device and methods for manufacturing the same
A nano-structured light-emitting device including a first semiconductor layer; a nano structure formed on the first semiconductor layer. The nano structure includes a nanocore, and an active layer and a second semiconductor layer that are formed on a surface of the nanocore, and of which the surface is planarized. A conductive layer surrounds sides of the nano structure, a first electrode is electrically connected to the first semiconductor layer and a second electrode is electrically connected to the conductive layer. |
| US09159875B2 |
Nitride semiconductor light emitting device and manufacturing method thereof
A semiconductor light emitting device includes a first conductive semiconductor layer including a V-shaped recess in a cross-sectional view. An active layer is disposed on the first conductive semiconductor layer, conforming to the shape of the V-shaped recess. An intermediate layer is disposed on the active layer and is doped with a first impurity. A second conductive semiconductor layer is disposed on the intermediate layer. The intermediate layer includes a first intermediate layer and a second intermediate layer. The first intermediate layer is disposed on the active layer, conforming to the shape of the V-shape recess. The second intermediate layer is disposed on the first intermediate layer and includes a protrusion to fill the V-shaped recess. |
| US09159874B2 |
Light emitting diode and method of manufacturing the same
A light emitting diode includes a conductive substrate and a light emitting structure which includes a first semiconductor layer disposed on the conductive substrate, an active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the active layer, a semi-transmissive layer which is disposed on the light emitting structure, and a hole which is defined in the light-emitting structure, and filled with a light emitting material which emits light having a color different from a color of light emitted from the active layer. |
| US09159866B2 |
Photo sensor, method of manufacturing photo sensor, and display apparatus
A photo sensor, a method of manufacturing the photo sensor, and a display apparatus, the photo sensor including a substrate; a light receiving unit on the substrate, the light receiving unit including an amorphous semiconductor material; a first adjacent unit and a second adjacent unit formed as one body with the light receiving unit, the first adjacent unit and the second adjacent unit being separated from each other by the light receiving unit; a first photo sensor electrode electrically connected to the first adjacent unit; and a second photo sensor electrode electrically connected to the second adjacent unit, wherein at least one of the first adjacent unit and the second adjacent unit includes a crystalline semiconductor material. |
| US09159864B2 |
Back contact paste with Te enrichment and copper doping control in thin film photovoltaic devices
Methods for forming a back contact on a thin film photovoltaic device are provided that include applying a conductive paste onto a surface defined by a p-type absorber layer (e.g., comprising cadmium telluride) of a p-n junction and curing the conductive paste to form a conductive coating on the surface defined by a p-type absorber layer of the p-n junction. The conductive paste can include a conductive material, a solvent system, and a binder such that during curing an acid from the conductive paste reacts to enrich the surface with tellurium while copper is deposited onto the Te enriched surface. The acid is then substantially consumed during curing. |
| US09159863B2 |
Method of forming chalcopyrite thin film solar cell
In a method of forming a CIGS film absorption layer, a first precursor is provided including a first substrate having a major process precursor film formed thereon, the major process precursor film containing two or more of Cu, In, Ga, and Se. A second precursor is provided including a second substrate having an element supplying precursor film formed thereon, the element supply precursor film containing two or more of Cu, In, Ga and Se. The precursors are oriented with the major process precursor film and element supplying precursor film facing one another so as to allow diffusion of elements between the films during annealing. The oriented films are annealed and then the precursors are separated, wherein the CIGS film is formed over the first substrate and either a CIGS film or a precursor film containing two or more of Cu, In, Ga, and Se remains over the second substrate. |
| US09159862B2 |
Solar cell and manufacturing method thereof
A solar cell is formed to have a silicon semiconductor substrate of a first conductive type; an emitter layer having a second conductive type opposite the first conductive type and formed on a first surface of the silicon semiconductor substrate; a back surface field layer having the first conductive type and formed on a second surface of the silicon semiconductor substrate opposite to the first surface; and wherein the emitter layer includes at least a first shallow doping area and the back surface field layer includes at least a second shallow doping area, and wherein a thickness of the first shallow doping area of the emitter layer is different from a thickness of the second shallow doping area of the back surface field layer. |
| US09159860B2 |
Avalanche photodetector element
An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array. |
| US09159859B2 |
Solar cell module
Disclosed is a solar cell module including: a plurality of solar cell units each including a supporting substrate 30 and an even number of solar cells 20 disposed on the supporting substrate 30; and a conductor 10 configured to electrically connecting surfaces of adjacent solar cells 20 that have opposite surface polarities and are formed in respective solar cell units adjacent to each other. The solar cells 20 having the opposite surface polarities are alternately arranged in each of the solar cell units so that the surface polarities of the adjacent solar cells 20 are opposite to each other, and the solar cell unit has one or more sets of two solar cells electrically connected to each other on the supporting substrate 30. |
| US09159855B2 |
Solid-state imaging device with channel stop region with multiple impurity regions in depth direction
Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate. |
| US09159854B2 |
Nano particle, nano particle complex having the same and method of fabricating the same
Disclosed are a nano particle, a nano particle complex and a method of fabricating the nano particle. The nano particle includes a compound semiconductor having a first metal element and a second metal element. The property of the nano particle is readily controlled depending on the composition of the first and second metal elements. |
| US09159852B2 |
Image sensor device and method
A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration. |
| US09159849B2 |
Semiconductor detector head and a method for manufacturing the same
A semiconductor detector head comprises a detector chip having a front side and a back side, and a substrate on the back side of said detector chip. Contact points are located on at least one of said substrate and said detector chip. A first set of contact pins protrude on an opposite side of said substrate than said detector chip. At least one of the contact pins of said first set is conductively coupled to at least one of said contact points. A base plate holds a second set of contact pins that protrude from said base plate towards the contact pins of said first set. Electric connections are made between matching pairs of contact pins of said first and second sets. |
| US09159841B2 |
Method for manufacturing semiconductor device
A thin film transistor having low off-state current and excellent electrical characteristics can be manufactured. In an inverted staggered thin film transistor including a semiconductor film in which at least a microcrystalline semiconductor region and an amorphous semiconductor region are stacked, a conductive film and an etching protective film are stacked over the semiconductor film; a mask is formed over the etching protective film; first etching treatment in which the etching protective film, the conductive film, and the amorphous semiconductor region are partly etched is performed; then, the mask is removed. Next, second etching treatment in which the exposed amorphous semiconductor region and the microcrystalline semiconductor region are partly dry-etched is performed using the etched etching protective film as a mask so that the microcrystalline semiconductor region is partly exposed to form a back channel region. |
| US09159836B2 |
Thin film transistor, method for manufacturing same, and display device
According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively. |
| US09159835B2 |
Two-dimensional condensation for uniaxially strained semiconductor fins
Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded. |
| US09159833B2 |
Fin structure of semiconductor device
A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized. |
| US09159831B2 |
Multigate field effect transistor and process thereof
A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures. |
| US09159820B2 |
Buried gate static induction thyristor
A semiconductor device contains a semiconductor substrate, a cathode, an anode, and a gate electrode. The semiconductor device has a cathode segment disposed in a portion corresponding to at least the cathode, an anode segment disposed in a portion corresponding to the anode, a plurality of embedded segments disposed in a portion closer to the cathode segment than to the anode segment, a takeoff segment disposed between the gate electrode and the embedded segments to electrically connect the gate electrode to the embedded segments, and a channel segment disposed between the adjacent embedded segments. |
| US09159816B2 |
PNP bipolar junction transistor fabrication using selective epitaxy
Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base. |
| US09159815B2 |
Semiconductor device and method for manufacturing the same
An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized. |
| US09159814B2 |
Memory structure and method for forming same
A memory structure and a method for forming the same are provided. The memory structure comprises: a substrate; a plurality of channel structures formed on the substrate, in which the plurality of channel structures are parallel with each other, each channel structure comprises a plurality of single crystal semiconductor layers and a plurality of oxide layers alternately stacked in a direction perpendicular to the substrate, and at least one of the plurality of oxide layers is a single crystal oxide layer; and a plurality of gate structures matched with the plurality of channel structures, in which each gate structure comprises a gate dielectric layer immediately adjacent to the plurality of channel structures and a gate electrode layer immediately adjacent to the gate dielectric layer. |
| US09159809B2 |
Multi-gate transistor device
A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other. |
| US09159808B2 |
Selective etch-back process for semiconductor devices
A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process. |
| US09159806B2 |
Semiconductor device and method for manufacturing the same
A highly reliable semiconductor device is provided. A semiconductor device is manufactured at a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, an oxide semiconductor film containing indium, and an insulating layer provided on and in contact with the oxide semiconductor film so as to overlap with the gate electrode layer are stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the insulating layer, the chlorine concentration and the indium concentration on a surface of the insulating layer are lower than or equal to 1×1019/cm3 and lower than or equal to 2×1019/cm3, respectively. |
| US09159804B2 |
Vertical gate LDMOS device
Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region. |
| US09159802B2 |
MOS devices with mask layers and methods for forming the same
A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask. |
| US09159799B2 |
Method of fabricating a merged P-N junction and schottky diode with regrown gallium nitride layer
A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer. |
| US09159796B2 |
Method for protecting a semiconductor device against degradation and a method for manufacturing a semiconductor device protected against hot charge carriers
A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided. |
| US09159795B2 |
High side DMOS and the method for forming thereof
A high side DMOS provides high breakdown voltage with small termination area. The high side DMOS has three parts which may comprise a stair-field plate in the termination part of the poly gate. |
| US09159793B2 |
P-type semiconductor material and semiconductor device
An oxide semiconductor material having p-type conductivity and a semiconductor device using the oxide semiconductor material are provided. The oxide semiconductor material having p-type conductivity can be provided using a molybdenum oxide material containing molybdenum oxide (MoOy (2 |
| US09159791B2 |
Semiconductor device comprising a conductive region
A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer. |
| US09159787B2 |
Semiconductor devices with germanium-rich active layers and doped transition layers
Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers. |
| US09159779B2 |
Method of fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a metal layer over a substrate, forming a capping layer over the metal layer, and densifying the metal layer through a heat treatment. |
| US09159778B2 |
Silicon process compatible trench magnetic device
A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench. |
| US09159776B2 |
Organic light emitting diode display
An organic light emitting diode (OLED) display includes: a substrate; and a plurality of pixels positioned on the substrate. Each pixel includes a thin film transistor positioned on the substrate, an interlayer insulating layer and a light path control layer positioned on the thin film transistor, a first electrode positioned on the light path control layer and connected to the thin film transistor, an organic emission layer positioned on the first electrode, and a second electrode positioned on the organic emission layer, and the light path control layer includes a first control layer, a second control layer having a larger refractive index than the first control layer, and a middle layer having the same refractive index as the first control layer. |
| US09159767B2 |
Methods of manufacturing magnetoresistive random access memory devices
In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed. |
| US09159764B2 |
Solid-state imaging device and method of manufacturing the same
A solid-state imaging device with a semiconductor substrate; a pixel formation region in the substrate and including a pixel made of a photoelectric conversion element; and an element isolation portion in the substrate and including an element isolation insulating layer and an impurity element isolation region. The element isolation insulating layer is positioned in a surface of the substrate. The impurity element isolation region is positioned under the element isolation insulating layer and within the substrate. The impurity element isolation region has at least a portion with a width that is narrower than that of the element isolation insulating layer. The photoelectric conversion element extends to a position under the element isolation insulating layer of the element isolation portion. |
| US09159760B2 |
Solid-state imaging device with layered microlenses and method for manufacturing same
A solid-state imaging device with microlenses having a first lens layer and a second lens layer, the second lens layer being formed at least at a periphery of each microlens with either a portion of the second lens layer present at a central portion of each of the microlenses being thinner than a portion of the second lens layer present at the periphery of the microlens or no portion of the second lens layer being present at the central portion of each of the first microlenses. Between first pixel portions there is an interpixel gap, and the solid-state imaging device includes light blocking layers in alignment with the gaps. |
| US09159755B2 |
Image sensor and method for fabricating the same
An image sensor includes a photoelectric conversion region formed in a substrate, an interlayer insulation layer formed over a front side of the substrate, a carbon-containing layer doped with impurities and formed over a back side of the substrate, and a color filter and a micro-lens formed over the carbon-containing layer. |
| US09159749B2 |
Oxide semiconductor devices, methods of manufacturing oxide semiconductor devices, display devices having oxide semiconductor devices, methods of manufacturing display devices having oxide semiconductor devices
An oxide semiconductor device includes a gate electrode on a substrate, a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode, a source electrode on a first portion of the gate insulation layer, a drain electrode on a second portion of the gate insulation layer, and an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure. |
| US09159747B2 |
Display device, thin film transistor, method for manufacturing display device, and method for manufacturing thin film transistor
According to one embodiment, a display device includes a substrate unit, a thin film transistor, a pixel electrode and a display layer. The substrate unit includes a substrate, a first insulating layer provided on the substrate, and a second insulating layer provided on the first insulating layer. The thin film transistor is provided on the substrate unit and includes a gate electrode provided on the second insulating layer, a semiconductor layer of an oxide separated from the gate electrode, a gate insulation layer provided between the gate electrode and the semiconductor layer, a first conductive portion, a second conductive portion, and a third insulating layer. The pixel electrode is connected to one selected from the first and second conductive portions. The display layer is configured to have a light emission or a change of optical characteristic occurring according to a charge supplied to the pixel electrode. |
| US09159743B2 |
Radio-frequency switches having silicon-on-insulator field-effect transistors with reduced linear region resistance
Disclosed are devices and methods related to radio-frequency (RF) switches having silicon-on-insulator (SOI) field-effect transistors (FETs). In some embodiments, an RF switch can include an FET with shaped source, drain, and gate selected to yield a reduced per-area value of resistance in linear operating region (Rds-on). In some implementations, a plurality of such FETs can be connected in series to allow use of SOI technology in high power RF switching applications while maintaining a relatively small die size. |
| US09159738B2 |
Semiconductor memory device
Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T1, a source of a second transistor element T2, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element T1 and a drain of the second transistor element T2. Each memory cell MC arranged in the same column includes the control node Nc connected to a shared first control line CL extending in a column direction, the first transistor element T1 having a source connected to a shared data signal line DL extending in the column direction, the second transistor element T2 having a gate connected to an individual first selection line WL, and the capacitive element Cm having the other end connected to an individual second selection line GL, and a switching element SE having one end connected to the first control line CL, and the other end connected to a voltage supply line VL is provided with respect to each first control line CL. |
| US09159735B2 |
Architecture to improve cell size for compact array of split gate flash cell with buried common source structure
Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head. |
| US09159734B2 |
Antifuse element utilizing non-planar topology
Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region. |
| US09159729B2 |
Capacitor of semiconductor device and method of fabricating the same
Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes. |
| US09159728B2 |
Meander line resistor structure
A system comprises a first transistor comprising a first active region and a second active region, a first resistor comprising a plurality of first vias connected in series, wherein the first resistor is over the first active region, a second resistor comprising a plurality of second vias connected in series, wherein the second resistor is over the second active region, a second transistor comprising a third active region and a fourth active region, a capacitor having a terminal electrically coupled to the fourth active region and a bit line electrically coupled to the third active region. |
| US09159727B2 |
Nonvolatile memory device and method for fabricating the same
Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer. |
| US09159723B2 |
Method for manufacturing semiconductor device and semiconductor device
A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer. |
| US09159720B2 |
Semiconductor module with a semiconductor chip and a passive component and method for producing the same
A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip. |
| US09159712B2 |
Light emitting device-light receiving device assembly, and manufacturing method thereof
A light emitting device-light receiving device assembly includes: a mount substrate having first and second surfaces, and including a first base as a raised portion on the first surface; a light receiving device having first and second surfaces, the first surface of the light receiving device being anchored on the first base; and a light emitting device, the light receiving device including a light passage portion allowing for passage of light emitted by the light emitting device, the light emitted by the light emitting device emerging to outside through the light passage portion, the first base, and the mount substrate, the light receiving device receiving externally incident light through the mount substrate and the first base, the light receiving device including an annular second base as a raised portion on the second surface of the light receiving device, and the light emitting device being anchored on the second base. |
| US09159710B2 |
Structures and methods for electrically and mechanically linked monolithically integrated transistor and NEMS/MEMS device
A device including a NEMS/MEMS machine(s) and associated electrical circuitry. The circuitry includes at least one transistor, preferably JFET, that is used to: (i) actuate the NEMS/MEMS machine; and/or (ii) receive feedback from the operation of the NEMS/MEMS machine. The transistor (e.g., the JFET) and the NEMS/MEMS machine are monolithically integrated for enhanced signal transduction and signal processing. Monolithic integration is preferred to hybrid integration (e.g., integration using wire bonds, flip chip contact bonds or the like) due to reduce parasitics and mismatches. In one embodiment, the JFET is integrated directly into a MEMS machine, that is in the form of a SOI MEMS cantilever, to form an extra-tight integration between sensing and electronic integration. When a cantilever connected to the JFET is electrostatically actuated, its motion directly affects the current in the JFET through monolithically integrated conduction paths (e.g., traces, vias, etc.). In one embodiment, devices according to the present invention were realized in 2 μm thick SOI cross-wire beams, with a MoSi2 contact metallization for stress minimization and ohmic contact. In this embodiment, the pull-in voltage for the MEMS cantilever was 21V and the pinch-off voltage of the JFET was −19V. |
| US09159709B2 |
Semiconductor chip and stacked semiconductor package having the same
A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure. |
| US09159708B2 |
Stackable molded microelectronic packages with area array unit connectors
A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant can overlie the first surface of the substrate and at least a portion of a face of the microelectronic element remote from the substrate, and may have a major surface above the microelectronic element. A plurality of package contacts can overlie a face of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses, substantially rigid posts, can be electrically interconnected with terminals of the substrate, such as through the conductive elements. The package contacts can have top surfaces at least partially exposed at the major surface of the encapsulant. |
| US09159707B2 |
Flexible display
A flexible display includes a plurality of pixel chips, chixels, provided on a flexible substrate. The chixels and the light emitters thereon may be shaped, sized and arranged to minimize chixel, pixel, and sub-pixel gaps and to provide a desired bend radius of the display. The flexible substrate may include light manipulators, such as filters, light converters and the like to manipulate the light emitted from light emitters of the chixels. The light manipulators may be arranged to minimize chixel gaps between adjacent chixels. |
| US09159706B2 |
Semiconductor device and a method of manufacturing the same
A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement. |
| US09159702B2 |
Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package. |
| US09159696B2 |
Plug via formation by patterned plating and polishing
Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line. |
| US09159695B2 |
Elongated bump structures in package structure
A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2. |
| US09159693B2 |
Hybrid substrate with high density and low density substrate areas, and method of manufacturing the same
Provided is a hybrid substrate with high density and low density substrate areas and a method of manufacturing the same. The hybrid substrate with high density and low density substrate areas includes a low density substrate layer having a cavity and a low density area, a high density substrate layer mounted in the cavity of the low density substrate layer and formed of a high density area having a higher pattern density than that of the low density area, an insulating support layer comprising a deposition area formed on upper portions, lower portions and the upper and lower portions of the high density substrate layer and the low density substrate layer, insulating layer vias passing through the deposition area of the insulating support layer and connected to patterns of the high density substrate layer and the low density substrate layer, and an outer pattern layer. |
| US09159690B2 |
Tall solders for through-mold interconnect
Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. A package can include a chip package situated below a lower surface of a first substrate, the package including a die situated on a top surface of a second substrate, a molding disposed over the upper surface of the second substrate, the molding extending over the second die and including an opening extending from an upper surface of the molding towards an upper surface of the second substrate, wherein the opening is configured to admit at least a portion of the solder ball, and a solder column electrically and mechanically coupled to the second substrate, situated in the opening, conforming to the cylinder, and including at least two layers of solder with flux therebetween. |
| US09159688B2 |
Semiconductor device including a solder and method of fabricating the same
A semiconductor device includes a bonding pad on a semiconductor substrate, a bump on the bonding pad, a solder on the bump, and an anti-wetting layer between the bump and the solder extending along a sidewall of the bump, the anti-wetting layer having a first thickness T1 along the sidewall of the bump closer to the solder and a second thickness T2 along the sidewall of the bump closer to the bonding pad, wherein T2 |
| US09159683B2 |
Methods for etching copper during the fabrication of integrated circuits
Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H3PO4 in a volume percentage of about 0.07 to about 0.36, H2O2 in a volume percentage of about 0.1 to about 0.7, and a remainder of H2O, and optionally NH4OH. |
| US09159677B2 |
Methods of forming semiconductor device structures
A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described. |
| US09159673B2 |
Forming interconnect structures using pre-ink-printed sheets
A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate. |
| US09159671B2 |
Copper wire and dielectric with air gaps
Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. |
| US09159669B2 |
Nanotube structure based metal damascene process
In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes. |
| US09159667B2 |
Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure
An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor. |
| US09159663B2 |
Semiconductor device with respective electrode pad rows and respective external electrodes electrically connected and arranged in the respective end portions of the substrate
A semiconductor device comprises a substrate, pluralities of first and second external electrodes formed in two end portions of one surface of the substrate, a first semiconductor chip mounted on the other surface of the substrate, the first semiconductor chip having an electrode pad row formed in one end portion of one surface of the first semiconductor chip and electrically connected to the first external electrodes, the first semiconductor chip being disposed so that the one end portion of the first semiconductor chip is positioned on an end portion on which the first external electrodes of the substrate are formed, and a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip having an electrode pad row formed in one end portion of one surface of the second semiconductor chip and electrically connected to the second external electrode, the second semiconductor chip being disposed so that the one end portion of the second semiconductor chip is positioned on an end portion on which the second external electrodes of the substrate are formed. |
| US09159662B2 |
Semiconductor structures having adhesion promoting layer in cavities
High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close of the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom. |
| US09159661B2 |
Integrated circuits with close electrical contacts and methods for fabricating the same
Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point. |
| US09159656B2 |
Semiconductor die package and method for making the same
Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. |
| US09159653B2 |
Copper interconnect structures and methods of making same
A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires. |
| US09159651B2 |
Semiconductor packages having TSV and adhesive layer
A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through the adhesive layer and are connected to the TSVs and the active layer. Side surfaces of the adhesive layer are aligned with side surfaces of the second semiconductor chip. |
| US09159649B2 |
Microelectronic package and stacked microelectronic assembly and computing system containing same
A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE1 for the second electrically insulating layer is greater than CTE1 for the first. CTE2 for the third electrically insulating layer is less than CTE2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package. |
| US09159643B2 |
Matrix lid heatspreader for flip chip package
A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312). |
| US09159641B2 |
Nanocrystalline diamond three-dimensional films in patterned semiconductor substrates
An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate. |
| US09159639B2 |
Power electronic system with a cooling device
A power electronic system with a cooling device, and a method for producing the system, comprising a plurality of submodules, each submodule having a first planar insulating material body, one first conductor track cohesively connected thereto, one power switch arranged on the conductor track, at least one internal connecting device composed of an alternate layer sequence of at least one electrically conductive film and at least one electrically insulating film, wherein at least one electrically conductive layer forms at least one second conductor track, and comprising external connection elements. In this case, the submodules are arranged cohesively or in a force-locking manner and in a manner spaced apart from one another with their first main surface on the cooling device. At least one second conductor track at least partially covers first conductor tracks of two submodules, electrically connects them to one another and covers an interspace between the submodules. |
| US09159636B2 |
Semiconductor device, semiconductor device storage method, semiconductor device manufacturing method, and semiconductor manufacturing apparatus
A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view. |
| US09159635B2 |
Flexible electronic structure
Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate. |
| US09159633B2 |
Test macro for use with a multi-patterning lithography process
A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region and forming a first and second source/drain regions in the active area. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region. The method further includes determining if an overlay shift has occurred during the formation of the active area by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. |
| US09159624B1 |
Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves laminating a polymeric mask layer onto a front side of the semiconductor wafer by dry film vacuum lamination, the polymeric mask layer covering and protecting the integrated circuits. The method also involves patterning the polymeric mask layer with a laser scribing process to provide gaps in the polymeric mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the polymeric mask layer to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing the polymeric mask layer. |
| US09159623B2 |
Wafer processing method for removing organic debris
After performing a dividing step to divide a wafer into individual chips, an irradiation step is performed to apply ultraviolet radiation or plasma to the mount side of each chip, thereby generating ozone and active oxygen, which functions to remove organic matter sticking to the mount side of each chip. Accordingly, it is possible to remove from the mount side of each chip not only foreign matter sticking to the wafer during handling the wafer, but also foreign matter generated in dividing the wafer, so that faulty mounting of each chip can be reduced. |
| US09159612B2 |
Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole. |
| US09159610B2 |
Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same
A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed. |
| US09159609B2 |
Semiconductor device with air gap spacer and capping barrier layer and method for fabricating the same
A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion. |
| US09159607B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm. |
| US09159603B1 |
Integrated circuit package strip support assembly
An integrated circuit (“IC”) package strip support assembly for a saw table including a first material having a first hardness and having a surface adapted to engage a first surface of an IC package strip during sawing; and a second material having a second hardness and having a surface adapted to engage the first surface of the IC package strip during sawing wherein the second hardness is less than the first hardness. |
| US09159602B2 |
Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers
Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. |
| US09159601B2 |
Workpiece transfer apparatus
A workpiece transfer apparatus includes a stationary base, an elevation base, first and second arms, a workpiece-holding hand, and a driving mechanism for the hand. The first arm is supported on the elevation base so as to be rotatable about a first vertical axis. The second arm is supported on the distal end of the first arm such that the second arm is rotatable about a second vertical axis. The hand is supported on the distal end of the second arm so as to be rotatable about a third vertical axis. A motor is arranged in the first arm, whereas a transmission is arranged to extend in a region from the interior of the first arm through the interior of the second arm. |
| US09159600B2 |
Wafer transport apparatus
The wafer transport apparatus prevents contaminant deposited on an unprocessed wafer from adhering to a processed wafer. Carrying-in load port 2A is loaded with a FOUP 1 storing an unprocessed wafer W1. Carrying-in chamber 3A has a transport robot 4A which takes out the unprocessed wafer W1 from the FOUP 1. Carrying-in load lock 5A is accessed by the transport robot 4A from the carrying-in chamber 3A side. Carrying-out load port 2B is loaded with the FOUP 1 that can store a processed wafer W2. Carrying-out chamber 3B has a transport robot 4B which passes the processed wafer W2 to the FOUP 1. Carrying-out load lock 5B is accessed by the transport robot 4B from the carrying-out chamber 3B side. The carrying-in chamber 3A and carrying-out chamber 3B are separated from each other. The carrying-in load lock 5A and carrying-out load lock 5B are arranged on different stages. |
| US09159595B2 |
Thin wafer carrier
An improved wafer carrier device for carrying and holding semiconductor wafers that have a thickness of below 100 micrometers includes a transportable wafer chuck having an enclosed vacuum reservoir and a top surface configured to support a wafer. The top surface has one or more through-openings extending from the top surface to the vacuum reservoir and the wafer is held onto the top surface via vacuum from the vacuum reservoir drawn through the through-openings. |
| US09159589B2 |
Bump structural designs to minimize package defects
A method of forming a chip package includes providing a chip with a plurality of first copper post bumps having a first height of copper post. The method also includes providing a substrate with a plurality of second copper post bumps having a second height of copper post. The method further includes bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package. The first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1. |
| US09159583B2 |
Methods of manufacturing nitride semiconductor devices
Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer. |
| US09159580B2 |
Method of making a semiconductor device using multiple layer sets
A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer. |
| US09159576B2 |
Method of forming finFET having fins of different height
A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer. |
| US09159574B2 |
Method of silicon etch for trench sidewall smoothing
Methods of silicon etch for trench sidewall smoothing are described. In one embodiment, a method involves smoothing a sidewall of a trench formed in a semiconductor wafer via plasma etching. The method includes directionally etching the semiconductor wafer with plasma generated from a fluorine gas to smooth the sidewall of the trench, the trench having a protective layer formed by plasma generated by a second process gas such as oxygen or a polymerization gas. In another embodiment, a method involves etching a semiconductor wafer to generate a trench having a smooth sidewall. The method includes plasma etching the semiconductor wafer with one or more first process gases including a fluorine gas, simultaneously performing deposition and plasma etching the semiconductor wafer with one or more second process gases including a fluorine gas and a polymerization gas mix, and performing deposition with one or more third process gases including a polymerization gas. |
| US09159573B2 |
Systems and methods for monitoring and controlling particle sizes in slurries
Systems and methods are provided for preparing a plurality of slurry particles. The system includes: a tank configured to contain and provide the slurry particles, a sampling module configured to sample at least one slurry particle within the tank and obtain at least one parameter related to a particle size, and a controller coupled to the tank and the sampling module, configured to vibrate the slurry particles within the tank based on the at least one parameter. |
| US09159566B2 |
Replacement metal gates to enhance transistor strain
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. |
| US09159562B2 |
Trench type Schottky junction semiconductor device and manufacturing method thereof
A Schottky junction type semiconductor device in which the opening width of a trench can be decreased without deteriorating the withstanding voltage. The cross sectional shape of a trench has a shape of a sub-trench in which the central portion is higher and the periphery is lower at the bottom of the trench, and a p type impurity is introduced vertically to the surface of the drift layer thereby forming a p+ SiC region, which is formed in contact to the inner wall of the trench having the sub-trench disposed therein, such that the junction position is formed more deeply in the periphery of the bottom of the trench than the junction position in the central portion of the bottom of the trench. |
| US09159561B2 |
Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning
A method of patterning a semiconductor device using a tri-layer photoresist is disclosed. A material layer is formed over a substrate. A tri-layer photoresist is formed over the material layer. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive layer disposed over the middle layer. A lithography process is performed to pattern the photo-sensitive layer into a mask having one or more openings. Undesired portions of the mask are removed via a first etching process. Thereafter, the middle layer is patterned via a second etching process. The second etching process includes forming a coating layer around the mask while the middle layer is being etched. In some embodiments, the second etching process includes a continuous plasma etching process. The plasma etching process is performed using at least a CxHyFz gas and an H2 gas. |
| US09159557B2 |
Systems and methods for mitigating print-out defects
The present disclosure provides methods and systems for mitigating print-out defects that result during semiconductor simulation and/or fabrication. One of the methods disclosed herein includes steps of receiving a first desired sub-layout and a second desired sub-layout and of optimizing the first desired sub-layout and the second desired sub-layout to generate a first optimized sub-layout and a second optimized sub-layout. The method further includes simulating the first optimized sub-layout and the second optimized sub-layout and of identifying one or more print-out defects in the simulated first optimized sub-layout and the simulated second optimized sub-layout. By comparing the simulated first optimized sub-layout and the simulated second optimized sub-layout it may be determined whether or not print-out defects in the simulated second optimized sub-layout are covered by the first desired sub-layout such that the first optimized sub-layout may be used to pattern material layers. |
| US09159554B2 |
Structure and method of forming metamorphic heteroepi materials and III-V channel structures on si
Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A <111> surface may be formed on a substrate and a Group III-V material may be grown from the <111> surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure. |
| US09159552B2 |
Method of forming a germanium-containing FinFET
A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched. |
| US09159551B2 |
Methods of forming capacitors
A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO2 and the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuO2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed. |
| US09159548B2 |
Semiconductor processing system including vaporizer and method for using same
A method for using a system, which includes a film formation apparatus for forming a high-dielectric constant thin film on target substrates together and a gas supply apparatus for supplying a process gas. The method includes a preparatory stage of determining a set pressure range of pressure inside a vaporizing chamber for a liquid material cooled at a set temperature. The preparatory stage includes obtaining a first limit value of pressure at which vaporization of the liquid material starts being inhibited due to an increase in the pressure, obtaining a second limit value of pressure at which vaporization of the liquid material starts being unstable and the pressure starts pulsating movement due to a decrease in the pressure, and determining the set pressure range to be defined by an upper limit lower than the first limit value and a lower limit higher than the second limit value. |
| US09159542B2 |
Apparatus and method for inhibiting ionization source filament failure
An ion source apparatus for a mass spectrometer comprises a refractory metal filament operable to provide a flow of electrons by thermionic emission; an electrical current source electrically coupled to the filament for heating the filament; a vacuum chamber enclosing the filament; an ionization volume within the vacuum chamber capable of receiving the flow of electrons; a source of an oxygen-providing gas or gases; a restrictive fluidic coupling to the source of oxygen-providing gas or gases; and a gas conduit fluidically coupled to the restrictive fluidic coupling, the restrictive fluidic coupling and conduit operable to provide a flow of the oxygen-providing gas or gases into the vacuum chamber so as to maintain a partial pressure of said gas or gases within the vacuum chamber that is sufficiently high so as to inhibit the otherwise formation of a carbonaceous growth on the filament in the presence of a gaseous carbon-containing material. |
| US09159541B2 |
Aperture gas flow restriction
A mass spectrometer is disclosed comprising two vacuum chambers maintained at different pressures. The two vacuum chambers are interconnected by a differential pumping aperture. The effective area of the opening between the two vacuum chambers may be varied by rotating a disk having an aperture in front of the differential pumping aperture so as to vary the gas flow rate through the opening and between the two chambers. |
| US09159540B2 |
Systems and methods for transfer of ions for analysis
The invention generally relates to systems and methods for transferring ions for analysis. In certain embodiments, the invention provides a system for analyzing a sample including an ionizing source for converting molecules of a sample into gas phase ions in a region at about atmospheric pressure, an ion analysis device, and an ion transfer member operably coupled to a gas flow generating device, in which the gas flow generating device produces a laminar gas flow that transfers the gas phase ions through the ion transfer member to an inlet of the ion analysis device. |
| US09159538B1 |
Use of mass spectral difference networks for determining charge state, adduction, neutral loss and polymerization
A mass spectrometric analysis method comprises: (1) processing a mass spectrum to reduce the signals to monoisotopic values; (2) creating a list of differences between the monoisotopic values; (3) creating one or more lists of theoretical mass-to-charge differences among known adducts, charge states and polymerization states whose formation may be expected from various analyte molecules; (4) comparing the theoretical differences (line or edge in the network) to the list of differences from the mass spectrum and, where applicable, make and tabulate tentative species assignments; and (5) assigning the mass spectral peaks to respective ion species in accordance with the redundancy of each assignment based on multiple independent calculated mass-to-charge differences pertaining to each peak. |
| US09159537B2 |
Method for analyzing sample components
Described herein is a method and system for on-line coupling of capillary isoelectric focusing (cIEF) to high-resolution mass spectrometry in which a sheath flow buffer comprising polar organic solvent and organic acid is used as both an immobilization solution for (cIEF) and an ionization solution for electrospray ionization (ESI). |
| US09159533B2 |
Charged particle beam apparatus permitting high-resolution and high-contrast observation
A lower pole piece of an electromagnetic superposition type objective lens is divided into an upper magnetic path and a lower magnetic path. A voltage nearly equal to a retarding voltage is applied to the lower magnetic path. An objective lens capable of acquiring an image with a higher resolution and a higher contrast than a conventional image is provided. An electromagnetic superposition type objective lens includes a magnetic path that encloses a coil, a cylindrical or conical booster magnetic path that surrounds an electron beam, a control magnetic path that is interposed between the coil and sample, an accelerating electric field control unit that accelerates the electron beam using a booster power supply, a decelerating electric field control unit that decelerates the electron beam using a stage power supply, and a suppression unit that suppresses electric discharge of the sample using a control magnetic path power supply. |
| US09159531B2 |
Sample carrier for an electron microscope
The invention relates to a sample carrier for a transmission electron microscope. When using state of the art sample carriers, such as half-moon grids in combination with detectors detecting, for example, X-rays emitted at a large emittance angle, shadowing is a problem. Similar problems occur when performing tomography, in which the sample is rotated over a large angle.The invention provides a solution to shadowing by forming the parts of the grid bordering the interface between sample and grid as tapering parts. |
| US09159530B2 |
Electron microscope sample holder and sample observation method
The present invention makes it possible, even when using an ordinary electron beam device (not an environment-controlled electron beam device), to create locally a low vacuum condition in the vicinity of a sample and cool said sample by means of a sample holder alone, without modifying the device or adding equipment such as a gas cylinder. The sample to be observed is placed in a sample holder provided with: a vessel that can contain a substance to serve as a gas source; and a through-hole in the bottom of a sample mount on said vessel. Via the through-hole, gas evaporating or volatilizing from the vessel is supplied to the sample under observation, thereby creating a localized low-vacuum state at or in the vicinity of the sample. Also, the heat of vaporization required for volatilization can be used to cool the sample. |
| US09159524B2 |
X-ray generating apparatus
The X-ray generating apparatus 100 applies an electron beam e1 onto a target 150 to generate X-rays x1, and includes a permanent magnet lens 120 configured to focus the electron beam e1, a correction coil 130 provided on a side of the electron beam e1 with respect to the permanent magnet lens 120 and configured to correct a focus position formed by the permanent magnet lens 120 in a traveling direction of the electron beam e1, and a target 150 onto which the focused electron beam is applied. Accordingly, the apparatus configuration can be extremely compact and lightweight in comparison with general apparatuses. Furthermore, by the correction coil 130, the intensity of the magnetic field can be finely adjusted and the focus position in the traveling direction of the electron beam e1 can be finely adjusted. |
| US09159520B2 |
Microwave driven electrodeless lamp comprising magnetron without forced convective cooling
A LUWPL luminaire has a housing with a lower transparent closure and a heat dissipating top of cast aluminum. This has a suspension eye. The housing has an upper flange via which it is bolted with the interposition of a seal to a underside rim of the top. Within the rim, the underside is substantially flat, with a magnetron attachment boss and other attachment points. A magnetron is supported by being clamped by a saddle to the attachment boss at the magnetron's anode. The magnetron is fast with a transition box and a crucible support block. A bracket fixed to certain of the attachment points extends down from the top is screwed to the transition box. Thus the LUWPL parts are securely supported below the top. |
| US09159519B2 |
Paste for electron emission source, and electron emission source
Disclosed are: a paste for an electron emission source, which enables omission of an activation process and is capable of emitting electrons at a low voltage, while exhibiting excellent adhesion to a cathode substrate; and an electron emission source which uses the paste for an electron emission source. Specifically disclosed is an electron emission source which is produced by subjecting a paste for an electron emission source containing the components (A)-(C) described below to a heat treatment. The electron emission source has cracks and carbon nanotubes project from the surfaces of the cracks. (A) carbon nanotubes (B) glass powder (C) at least one substance selected from the group consisting of metal salts, metal hydroxides, organic metal compounds, metal complexes, silane coupling agents and titanium coupling agents. |
| US09159510B2 |
Fixed contact structure
There is provided a fixed contact structure, including: a substrate; at least one fixed contact which is disposed on the substrate; a movable contact which slides on the corresponding fixed contact in a sliding direction; a resist layer which is consecutively disposed on the substrate outside both ends of the fixed contact with respect to the sliding direction; and gaps which are formed outside both ends of the fixed contact with respect to a direction orthogonal to the sliding direction. |
| US09159505B2 |
Electric storage device
An electric storage device, including: an electrode assembly having at least one protrusion portion, the protrusion portion being formed of an end portion of any one of a positive electrode foil and a negative electrode foil and protruding in a laminated state from a side end of the other electrode foil of the both electrode foils; a current collector having a contact portion in contact with the protrusion portion; and a metal material that joins the protrusion portion by interposing the protrusion portion between the contact portion of the current collector and the metal material, wherein at least an end region in one direction along the opposing face is displaced in a direction away from the contact portion of the current collector than a central region of the opposing face is. |
| US09159504B2 |
Apparatus for storing electric energy and method of manufacturing the same
Disclosed herein is an apparatus for storing an electric energy, the apparatus including: an electrode stack in which a cathode and an anode in which a cathode lead and an anode lead are respectively formed are alternately stacked; and collector plates disposed at both sides of the electrode stack, connected to the cathode lead and the anode lead, and provided with external terminals and one or more electrolyte flow holes. |
| US09159503B2 |
Supercapacitor and method for manufacturing electrode thereof
The present invention relates to a method for manufacturing an electrode of a supercapacitor, comprising: (A) providing a carbon substrate and a phosphorus-containing precursor, and mixing the carbon substrate and the phosphorus-containing precursor at a ratio of 1:100 to 1000:1 by weight; (B) heating the mixture of the carbon substrate and the phosphorus-containing precursor to a temperature between 300° C. and 1100° C. to obtain a P-doped carbon substrate; and (C) forming an electrode of a supercapacitor by using the P-doped carbon substrate. The present invention also relates to a supercapacitor which comprises: a first electrode; a second electrode; and an electrolyte that is interposed between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode is prepared by the above-mentioned method. |
| US09159502B2 |
Supercapacitor with hexacyanometallate cathode, activated carbon anode, and non-aqueous electrolyte
A supercapacitor is provided with a method for fabricating the supercapacitor. The method provides dried hexacyanometallate particles having a chemical formula AmM1xM2y(CN)6.pH2O with a Prussian Blue hexacyanometallate, crystal structure, where A is an alkali or alkaline-earth cation, and M1 and M2 are metals with 2+ or 3+ valance positions. The variable m is in the range of 0.5 to 2, x is in the range of 0.5 to 1.5, y is in the range of 0.5 to 1.5, and p is in the range of 0 to 6. The hexacyanometallate particles are mixed with a binder and electronic conductor powder, to form a cathode comprising AmM1xM2y(CN)6.pH2O. The method also forms an activated carbon anode and a membrane separating the cathode from the anode, permeable to A and A′ cations. Finally, an electrolyte is added with a metal salt including A′ cations. The electrolyte may be aqueous. |
| US09159501B2 |
Electric storage device
An electric storage device includes an electrode assembly, in which a positive electrode and a negative electrode in the shape of a sheet are wound with a separator sandwiched therebetween. The electrode assembly has a flat shape and includes a first flat portion and a second flat portion, which are opposed to each other, and a first curved portion and a second curved portion which connect end portions of the first and second flat portions together. One of the positive electrode and the negative electrode covers an inner-circumferential end portion of the other electrode and is disposed on an innermost circumference of the electrode assembly. An inner-circumferential end portion of the one of the electrodes causes an elastic force to act outwardly on the other electrode. |
| US09159498B2 |
Preparation of electrode compositions
The invention relates to processes for the preparation of electrode compositions, especially those intended for use in supercapacitors. A process is provided for preparing lithium sulphite comprising the steps of:—a) introducing H2SO3 (aq) into a reaction vessel; b) reacting the H2SO3 (aq) with an aqueous suspension of Li2CO3 in the vessel to form an aqueous solution of Li2—CO3; and c) evaporating the solution to recover Li2CO3(s), wherein at least steps a) and b) are conducted under an inert atmosphere. Preferably, in step b) H2SO3 (aq) and Li2CO3 (aq) are reacted with each other in substantially equimolar amounts. There is also provided a process for forming an electrode material comprising a complexing step of causing lithium sulphite to form SO3 complexes at active N sites of a nitrogen-carbon structure, in the presence of a selected amount of a sink that absorbs the liberated lithium, so as to form the N:SO3 complexed electrode material. Preferably, the nitrogen-carbon structure is thermally restructured polyacrylonitrile (TR-PAN) or a copolymer thereof. |
| US09159491B2 |
Multilayer ceramic electronic component and mounting board therefor
There is provided a multilayer ceramic electronic component including a ceramic body including dielectric layers, and first and second internal electrodes formed within the ceramic body and disposed to face each other having the respective dielectric layers interposed therebetween, wherein in a cross-section of the ceramic body in a length-thickness (L-T) direction, when an area of non-electrode regions in cover part internal electrodes among the first and second internal electrodes is defined as Acover and an area of non-electrode regions in center part internal electrodes among the first and second internal electrodes is defined as Acenter, a ratio of Acenter to Acover satisfies 0.33≦Acenter/Acover≦0.95. |
| US09159490B2 |
Solid electrolytic capacitor package structure and method of manufacturing the same, and conductive unit
A solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes at least one first conductive terminal and at least one second conductive terminal. The first conductive terminal includes a first core layer and a first enclosing layer. The first core layer has a first top exposed surface exposed from the first enclosing layer, and the first top exposed surface has a first top covering area covered by the package body. The second conductive terminal includes a second core layer and a second enclosing layer. The second core layer has a second top exposed surface exposed from the second enclosing layer, and the second top exposed surface has a second top covering area covered by the package body. |
| US09159489B2 |
Method of producing powder magnetic core and method of producing magnetic core powder
The invention includes: powder preparation step of obtaining magnetic core powders by mixing, of magnetic powders with thermosetting resin powders in hot state; powder filling step of filling the obtained magnetic core powders into a die; a compaction step of compacting magnetic core powders; and compact heating step of heating, compacts to the elevated temperature state at which the thermosetting resin hardens after compaction. |
| US09159483B2 |
Reactor device
A reactor device formed by containing a reactor body comprising a plurality of cores joined with each other within a case in a floating state. The reactor body is placed on a case by using leaf spring bodies and a movement of the reactor body in the horizontal direction is allowed, thereby absorbing a difference in expansion resulting from a difference in the thermal expansion coefficient between the reactor body and the case due to a heat stress. Further, a resin mold is inserted into a concave portion of the case so as to allow the movement in the horizontal direction so that the movement of the reactor body along a slope surface can be achieved, thereby absorbing the difference in expansion. |
| US09159481B2 |
Non-contact torque sensor with permanent shaft magnetization
A device for magnetizing an object includes first and second electrode for contacting the object to be magnetized as well as a current generator. The generator is configured to apply a current having a raising current slope and a falling current slope. The falling current slope is steeper than the raising current slope. |
| US09159480B2 |
Method for actuating an electromagnetic load and a corresponding circuit
A method is proposed for actuating an electromagnetic load (3) which can be switched between at least two switching states, particularly a magnetic valve, wherein switching between a first and a second of the switching states takes place as a result of a current flowing through the load (3) by means of applying an electrical voltage to said load (3). Provision is thereby made for the voltage to be clocked upon application thereof to said load (3) if due to the applied voltage the switching process would occur without clocking outside of a current ramp-up. The invention furthermore relates to an electrical circuit for actuating an electromagnetic load (3). |
| US09159477B2 |
Laminated chip composite resistor combining thermistor and varistor and preparation method thereof
Provided are a laminated chip composite resistor combining a thermistor and a varistor, and a preparation method thereof. The composite resistor comprises a varistor part, a transition layer part and a thermistor part overlapped sequentially, wherein the varistor part is formed by alternately laminating a ceramic layer of a varistor, a first electrode layer, another ceramic layer of a varistor and a second electrode layer; the thermistor part is formed by alternately laminating a ceramic layer of a thermistor, a third electrode layer, another ceramic layer of a thermistor and a fourth electrode layer; and the transition layer part is located between the thermistor part and the varistor part. Co-firing is employed and the base metal Ni is the main material of inner electrodes, which can reduce costs, simplify the preparation process, and improve the reliability. |
| US09159471B2 |
Communication cable with improved crosstalk attenuation
Embodiments of the present invention relate to methods and apparatuses directed towards communication cables and barrier tapes for use in communication cables. In an embodiment, the present invention employs conductive segments within the communication cables and/or on the barrier tape. |
| US09159466B2 |
Aromatic polycarbonate composition
The present invention relates to a polymer composition comprising the following components: a) 76.6-99.9 mass % of aromatic polycarbonate, b) 0.5-20 mass % of laser direct structuring additive, c) 0-2.4 mass % of rubber like polymer, and d) 0.01-1 mass % of acid and/or acid salt wherein the mass % is calculated relative to the sum of a), b), c) and d). The invention also relates to a moulded part containing this composition, to a circuit carrier containing such molded part and to a process for producing such circuit carrier. |
| US09159459B2 |
Heat pipe nuclear fission deflagration wave reactor cooling
Illustrative embodiments provide systems, applications, apparatuses, and methods related to nuclear fission deflagration wave reactor cooling. Illustrative embodiments and aspects include, without limitation, nuclear fission deflagration wave reactors, methods of transferring heat of a nuclear fission deflagration wave reactor, methods of transferring heat from a nuclear fission deflagration wave reactor, methods of transferring heat within a nuclear fission deflagration wave reactor, and the like. |
| US09159457B2 |
Non-volatile memory device for storing write data having different logic levels
A non-volatile memory device includes a plurality of bit lines; a plurality of page buffers corresponding to the bit lines, respectively, and configured to each store a write data; and a control circuit configured to control at least one page buffer of the plurality of page buffers to store the write data of a first logic level and control other ones of the plurality of page buffers to store the write data of a second logic level, wherein the control circuit is further configured to select the at least one page buffer based on an address inputted to the control circuit. Since write data of diverse patterns may be generated within a non-volatile memory device by using a portion of the bits of the address, a test operation of the non-volatile memory device may be performed within a short time. |
| US09159448B2 |
Shift register unit, shift register and scanning method thereof, and display device
A shift register unit, a shift register and the scanning method thereof, and a display device are disclosed. Bidirectional scanning can be achieved while the number of the switches used in the shift register could be reduced, and the spaces are saved. Furthermore, the problem of large coupled noise voltage is solved, and the performance of the shift register is improved. The circuit comprises: a second switch connected with a first switch; a fourth switch connected with a third switch; a fifth switch connected with a sixth switch; a first input and a eighth switch connected with a seventh switch; a output end and a ninth switch connected with the eighth switch; an eleventh, a twelfth, and a thirteenth switch connected with a tenth switch; a fourteenth switch connected with the thirteenth switch; a fifteenth switch connected with the fourteenth switch; a capacitor positioned between a first node and a second nodes. |
| US09159446B2 |
Methods and apparatus for in-pixel filtering in focal plane arrays including apparatus and method for counting pulses representing an analog signal
Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal. |
| US09159441B2 |
Method of operating memory device assuring reliability and memory system
A method of operating a memory device to guarantee program reliability and a memory system using the same are provided. The method includes backing up data stored in the memory cells connected to a first word line, performing a dummy program operation on memory cells connected to a second word line adjacent to the first word line, and performing a recharge program operation on the memory cells connected to the first word line. |
| US09159437B2 |
Device and method for resolving an LM flag issue
The reliability with which data can be read from a storage medium, such as flash memory storage medium, is enhanced by updating an upper limit of a reading threshold voltage window for a respective portion of the storage medium. For each memory cell in the respective portion of the storage medium, a memory controller is configured to perform a plurality of sensing operations and obtain results from the plurality of sensing operations, where the plurality of sensing operations includes sensing operations using a predefined range of offsets from a previously established reading threshold voltage. The memory controller is further configured to determine the updated upper limit of the reading threshold voltage window based on the-results from the plurality of sensing operations, and store the updated upper limit of the reading threshold voltage window for the respective portion of the storage medium. |
| US09159434B2 |
Bit line bias circuit with varying voltage drop
A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read. |
| US09159433B2 |
Semiconductor memory device and method of operating the same
A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block. |
| US09159431B2 |
Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. |
| US09159429B2 |
Data storage system and method of operating the same
A data storage system and a method of operating the same are provided. The method includes performing a program operation on a first page of the pages of a memory block, deciding, when power is switched on after a sudden power-off is generated while the program operation is performed, whether to skip the program operation on a first erase page of the pages based on a second page on which the program operation is performed subsequent to the first page, and performing the program operation on the second page. |
| US09159426B1 |
Three dimensional memory device having stacked conductive channels
A method includes forming a first group of memory cells coupled to a first conductive channel. The first conductive channel is substantially perpendicular relative to a surface of a substrate. The method further includes forming a second group of memory cells coupled to a second conductive channel. The second conductive channel is electrically coupled to the first conductive channel and is substantially perpendicular relative to the surface of the substrate. |
| US09159425B2 |
Non-volatile memory with reduced sub-threshold leakage during program and erase operations
A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. |
| US09159424B2 |
Three dimensional semiconductor memory device with line sharing scheme
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks, wherein word lines of the memory blocks are coupled to each other and a pair of the memory blocks are arranged vertically adjacent to each other and share bit lines. |
| US09159423B1 |
Robust erase page detection logic for NAND flash memory devices
The present invention provides a method and system to reduce the impact of errors introduced in flash devices while providing improved system performance through optimized activities with limited impact to overhead using a predetermined threshold value or threshold device value. In an embodiment, a device threshold value is compared with the cumulative number of data bits having a zero value of a target page and an error type of the target page is assessed to determine whether the target page is available to be written to. Therefore for a highly effective method for is provided for determining the availability of a page, having a block address and page address, to be identified, in one instance, as being an erased page that is available to be written to. |
| US09159421B2 |
Longest prefix match internet protocol content addressable memories and related methods
Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein. |
| US09159420B1 |
Method and apparatus for content addressable memory parallel lookup
Systems and methods are provided for a content addressable memory. A system includes a common memory module configured to store a plurality of entries, ones of the entries being defined by a string of bits. A first parallel compare logic unit is configured to compare a first lookup key against a plurality of entries stored in the memory module in a first memory operation cycle and to output a match indication indicating a match between the first lookup key and the string of bits of an entry from among the plurality of entries. A second parallel compare logic unit is configured to compare, in the first memory operation cycle, a second lookup key against the plurality of entries stored in the memory module and to output a match indication indicating a match between the second lookup key and the string of bits of an entry from among the plurality of entries. |
| US09159417B2 |
Deletable nanotube circuit
Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. |
| US09159414B1 |
Programmable impedance element circuits and methods
An integrated circuit may can include a memory section that stores data in programmable impedance elements arranged at cross points of select lines and sub bit lines, groups of sub bit lines each being connected to a different main bit line, the elements being formed above a substrate surface. |
| US09159410B1 |
Accessing a resistive memory storage device
Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines. |
| US09159408B2 |
Memory element with a reactive metal layer
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays. |
| US09159404B2 |
Nonvolatile memory device
A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors. |
| US09159400B2 |
Semiconductor memory having staggered sense amplifiers associated with a local column decoder
A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines. |
| US09159393B2 |
Memory decoding
Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal line connected to the gate of the sense circuitry, a second signal line connected to the program circuitry, and an output selectively connected to the memory cell. The decoder is configured to selectively connect the output to the first signal line responsive to a first control signal and to selectively connect the output to the second signal line responsive to the first control signal and a second control signal. The sense circuitry is configured to selectively activate the gate responsive to a third control signal. |
| US09159389B2 |
Semiconductor memory apparatus
A semiconductor memory apparatus may include a clock buffer configured to receive an external clock signal, buffer the external clock signal in response to an activation control signal, and the clock buffer configured to output an internal clock signal in response to an activation control signal. The semiconductor memory apparatus may also include a delay-locked loop block configured to receive the internal clock signal outputted from the clock buffer and compare phases of the internal clock signal and a feedback clock signal, and responsively generate a delay-locked clock signal. The semiconductor memory apparatus may also include an operation control block configured to responsively generate the activation control signal which is received by the clock buffer in accordance with a result of comparing the phases of the internal clock signal and the feedback clock signal, in response to receiving a read signal. |
| US09159386B2 |
Semiconductor devices and reduction of operation times
The semiconductor device includes a command decoder and a voltage generation circuit. The command decoder may be suitable for decoding external command signals to generate a preparation signal and a voltage control signal. The voltage generation circuit may be suitable for generating a read voltage signal used in a read operation and a program voltage signal used in a program operation in response to the preparation signal. In addition, the voltage generation circuit may terminate generation of the read voltage signal and the program voltage signal in response to the voltage control signal. |
| US09159381B2 |
Tunable reference circuit
A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements. |
| US09159380B2 |
Bridge device architecture for connecting discrete memory devices to a system
A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto. |
| US09159379B2 |
Switching circuit and semiconductor memory device
A switching circuit includes a first well and a second well formed in a semiconductor substrate; a first transistor being connected with a first node at one end, and the first transistor being formed in the first well; a second transistor being connected with another end of the first node at one end, and connected with a second node at another end, and the second transistor being formed in the second well; and a potential control circuit that connects the second well with the first node during a predetermined period including a period for the first transistor and the second transistor to transition from off to on in a state where potential of the second node is lower than potential of the first node, and connects the second well with the second node after the predetermined period. |
| US09159374B2 |
Flash memory module and memory subsystem
A mass storage memory module system including a memory module having memory holding members which can be connected to each other, and removably connected to a memory controller. One or more modular memory holding members can be connected to each other to expand the overall storage capacity of the memory module. The presently described expandable memory module does not have a storage capacity limit. A memory holding member includes a plate, a plane, a board and another material having at least one memory device, or, on which at least one memory device is held or to which at least one memory device is mounted. |
| US09159373B2 |
Enhanced block copy
Methods and apparatuses for an enhanced block copy. One embodiment is reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts. |
| US09159370B2 |
Distributing media using a portable digital device compatible with optical drive devices
A media distribution system is provided in which a primary means of transport for digital media is through a device with housing shaped as an optical disc and insertable into various current and future optical disc drive devices. Media travels from different digital sources such as a personal media library and other networked resources to embedded memory on the optical disc shaped device via a capable personal computer or electronic device. This media is then able to be presented in the most appropriate format in a number of different types of current and legacy devices with optical drives such as CD audio devices and DVD players. |
| US09159368B2 |
Recording and reproducing apparatus and method thereof
In a recording and reproducing apparatus and a recording and reproducing method for the recording and reproducing apparatus for recording and reproducing image information on a scene obtained through photographing, relative to a predetermined first recording medium and being capable of setting one or more chapters to each scene, a face recognizing process is executed for a photographed image based on the image information, an importance level of each chapter is set in accordance with a result of the face recognizing process for a very important person (VIP) set by a user, and each chapter having a relevant importance level among importance levels of respective chapters is selectively reproduced. A user can therefore find an object chapter and scene quickly and easily. |
| US09159365B2 |
Method and apparatus for creating a custom track
A method and system for creating and editing video and/or audio tracks is described. The method includes providing at least one artist, venue, and track available for selection and providing at least one clip associated with the at least one artist, venue, and track. The method also includes allowing a user to create a custom track from the at least one clip. The system includes a plurality of video cameras for recording a live performance at a plurality of positions. The system also includes at least one server for storing a plurality of video clips created from the plurality of video cameras and an application stored on the at least one server for allowing a user to access the plurality of video clips via the Internet. |
| US09159364B1 |
Aggregation of related media content
Systems and methods for media aggregation are disclosed herein. The system includes a media system that can transform media items into one aggregated media item. A synchronization component synchronizes media items with respect to time. The synchronized media items can be analyzed and transformed into an aggregated media item for storage and/or display. In one implementation, the aggregated media item is capable of being displayed in multiple ways to create an enhanced and customizable viewing and/or listening experience. |
| US09159363B2 |
Systems and methods for adjusting audio attributes of clip-based audio content
Systems and methods are disclosed to adjust the loudness or another audio attribute for one or more audio clips. Intra-track audio levels can automatically be equalized, for example, to achieve a homogeneous audio level for all clips within an audio track. Information about such audio adjustments may be identified and stored as information without destructively altering the underlying clip content. For example, keyframes may define changes to a fader that will be applied at different points along a track's timeline to achieve the audio adjustments when the track is played. An audio editing application can provide a feature for automatically determining appropriate keyframes, allow manual editing of keyframes, and use keyframes to display control curves that represent graphically the time-based adjustments made to track-specific faders, play test audio output, and output combined audio, among other things. |
| US09159361B2 |
System and method for distributed trick play resolution using user preferences
Distributed trick play resolution in a distributed video viewing group network includes determining trick play preferences for each device of a plurality of nodes in the distributed video viewing group network with respect to a video item. Conflicting trick play preferences between the nodes is determined based on one or more of a group consisting of: user rankings, user voting, trick play ranking, and owner resolution. The determined conflicting trick play preferences are resolved. |
| US09159360B2 |
Servo pattern by microwave assisted magnetic recording, perpendicular magnetic recording medium, magnetic storage device and method for manufacturing the same
Disclosed is a technique of providing a perpendicular magnetic recording medium in which high-quality servo information enabling high-density recording of 500 kTPI or more is recorded, and a magnetic storage device of an adaptive track formatting type having large capacity, high reliability and high performance with high device manufacturing yield. At a servo area of the perpendicular magnetic recording medium, a servo sequence such as a burst pattern for positioning in a servo track is recorded in a seamless manner without big recording footprint (several times longer than the servo bit) and in a magnetization pattern such that a total amount of the recording magnetization is substantially zero. |
| US09159359B2 |
Tape media kiss-contact read verification
A supplemental module that includes one or more read elements periodically engages a magnetic recording medium, and the read elements generate an electrical signal corresponding to transitions written to the magnetic recording medium by a write element. A computer receives information representative of the electrical signal and determines if a quality metric of the magnetic recording medium derived from the electrical signal is within a defined range. If the quality metric is not within the defined range, a defined action is performed by the computer. |
| US09159358B1 |
Asynchronous asymmetry compensation for data read from a storage medium
According to one embodiment, a system for processing data includes a processor and logic integrated with and/or executable by the processor, the logic being configured to read data from a magnetic data storage medium using a read channel, detect and track positive peak amplitudes and negative peak amplitudes of a readback waveform during the data reading using a tracking threshold module, and perform asymmetry compensation on the data using an asymmetry compensator based on input from the tracking threshold module in an asymmetry compensation loop, wherein the asymmetry compensator does not rely on an input from path metrics in order to perform the asymmetry compensation. Other systems, such as magnetic tape drives, and methods for processing data, and specifically for asynchronously providing asymmetry compensation for data read from a magnetic tape, are described in more embodiments. |
| US09159353B2 |
Plasma polish for magnetic recording media
Fabrication methods for magnetic recording media that use a plasma polish are disclosed. For one exemplary method, a film of a magnetic recording medium is deposited, and a top surface of the film is polished utilizing a plasma formed by a noble gas to smoothen the top surface of the film. A subsequent layer is then deposited onto the polished top surface of the film. A top surface of the subsequent layer has a reduced roughness by being deposited on the polished top surface of the film. |
| US09159351B2 |
Perpendicular magnetic recording medium and method of manufacturing the same
A perpendicular magnetic recording medium includes a substrate, a soft magnetic layer, a pre-underlayer, an underlayer, and a main recording layer serving as a magnetic recording layer. The pre-underlayer contains seed crystal grains that serve as a base for crystal grains of the underlayer, and an addition substance that is added between the seed crystal grains and composed of an element having an atomic radius smaller than that of an element forming the seed crystal grains. |
| US09159349B2 |
Writer core incorporating thermal sensor having a temperature coefficient of resistance
A writer core of a transducer is configured to interact with a magnetic recording medium and comprises an upper core and a lower core. At least one of the upper and lower cores comprises a return pole having a return shield. The apparatus also comprises a writer pole between the upper and lower cores, and a writer gap defined between the writer pole and the return shield. The apparatus further comprises a sensor element within one of the upper and lower cores that includes the writer gap. The sensor element has a temperature coefficient of resistance and is configured to sense for a change in temperature indicative of one or both of a change in spacing and contact between the transducer and the magnetic recording medium. |
| US09159347B1 |
Usage of state information from state-space based track-follow controller
A method according to one embodiment includes generating track following controller state information based on a positional signal of a head relative to a medium. One or more portions of the state information corresponding to particular frequencies are used to determine at least one of: lateral tape movement, tape skew, vibration operation conditions, and roller performance. |
| US09159343B2 |
Copper residual stress relaxation reduction means for hard disk drive slider gimbals
A hard drive gimbal trace circuit includes: a stainless steel gimbal strut (SGST) configured to support a transducer and nullify a natural pitch angle of a flexure from mechanical-coarse adjustment of the SGST; traces forming a trace structure, and being plastically deformed at a high strain region from the mechanical-coarse adjustment of the SGST; and a first protrusion and a second protrusion being at least partially disposed under the high strain region. The SGST has an edge which is disposed on the transducer side to be spaced apart from the traces in the high strain region and extends substantially parallel to the traces. The first protrusion and the second protrusion extend from the edge in an orthogonal direction to an extending direction of the traces and across the traces, and are disposed side by side in the extending direction of the traces. |
| US09159342B2 |
Magnetic recording apparatus
According to an embodiment, a magnetic recording apparatus includes following elements. The spin torque oscillator generates a first oscillating magnetic field. The recording medium unit includes one or more recording medium layers which are stacked, each of the one or more recording medium layers including a recording medium and spin-wave lines each of which generates a second oscillating magnetic field. The write magnetic field source generates a write magnetic field. The controller is configured to control the spin torque oscillator, the spin-wave lines, and the write magnetic field source to simultaneously apply the write magnetic field, and the first and second oscillating magnetic fields to target medium magnetization in the recording medium. |
| US09159329B1 |
Statistical post-filtering for hidden Markov modeling (HMM)-based speech synthesis
A method and system for improving the quality of speech generated from Hidden Markov Model (HMM)-based Text-To-Speech Synthesizers using statistical post-filtering techniques. An example method involves: (a) determining a scale factor that, when applied to a synthesized reference spectral envelope, minimizes a statistical divergence between a natural reference spectral envelope and the synthesized reference spectral envelope, where the synthesized reference spectral envelope is generated by a state of an HMM; (b) for a given synthesized subject spectral envelope generated by the state of the HMM, determining an enhanced synthesized subject spectral envelope based on the determined scale factor; and (c) generating, by a computing device, a synthetic speech signal including the enhanced synthesized subject spectral envelope. |
| US09159324B2 |
Identifying people that are proximate to a mobile device user via social graphs, speech models, and user context
Techniques are provided to improve identification of a person using speaker recognition. In one embodiment, a unique social graph may be associated with each of a plurality of defined contexts. The social graph may indicate speakers likely to be present in a particular context. Thus, an audio signal including a speech signal may be collected and processed. A context may be inferred, and a corresponding social graph may be identified. A set of potential speakers may be determined based on the social graph. The processed signal may then be compared to a restricted set of speech models, each speech model being associated with a potential speaker. By limiting the set of potential speakers, speakers may be more accurately identified. |
| US09159315B1 |
Environmentally aware speech recognition
Examples of methods and systems for implementing environmentally aware speech recognition are described. In some examples, a method may be performed by a computing device within a system to adapt an acoustic model for a particular language to one or more environmental conditions. A device may receive one or more spoken utterances and based on the utterances, a system containing the device may determine an acoustic model for the particular language. The system may adapt the acoustic model using one or more data sets depending on the environmental conditions at the location of the device or may obtain another acoustic model that is adapted to the environmental conditions. In some examples, the system may also adapt the acoustic model using one or more data sets based on the voice characteristics of the speaker of the one or more spoken utterances. |
| US09159313B2 |
Playback control apparatus, playback control method, and medium for playing a program including segments generated using speech synthesis and segments not generated using speech synthesis
A playback control apparatus includes a playback controller configured to control playback of first content and second content. The first content is to output first sound which is generated based on text information using speech synthesis processing. The second content is to output second sound which is generated not using the speech synthesis processing. The playback controller causes an attribute of content to be played back to be displayed on the screen, the attribute indicating whether or not the content is to output sound which is generated based on text information using speech synthesis processing. |
| US09159311B2 |
Unrestricted mounting of ultrasonic transducers
An ultrasonic processing apparatus is disclosed that supports an ultrasonic rod transducer without restricting the transmission of ultrasonic vibrations from the rod transducer to liquid in a processing tank. A support structure supports one or both converter heads of the rod transducer without restricting its vibration. |
| US09159302B2 |
Piano extended soft pedal/CIP
A piano selectively playable in normal and soft modes has multiple piano keys and actions, including a wippen assembly, and multiple piano hammers. A soft pedal system includes a soft pedal and a hammer rest rail mounted for movement between normal and soft mode positions. A piano key lift rail is mounted for movement between a normal mode position spaced from lifting contact with the keys and a soft mode position in contact with and lifting the keys and the wippen assemblies. A soft pedal linkage assembly between the soft pedal and the hammer rest rail and piano key lift rail, upon actuation of the soft pedal, causes movement of hammer rest rail and piano hammers, and movement of the piano keys and the wippen assemblies, between normal and soft mode positions, in gap-closing motion. |
| US09159301B2 |
Slanted map
A display device generates a combined display that is viewable by the driver of a vehicle. The combined display may be composed of a plurality of displays, wherein one or more overlaying displays appear partially or completely in front of a first display, each overlaying display having an opaque portion that conveys information and a substantially transparent portion through which the first display is viewable. One or more monitors may generate the first display and overlaying displays. A monitor may be divided into multiple screens to generate a plurality of the displays. A screen that generates the first display may be directly viewable by the driver, while the screens the generate the overlaying displays may be outside the driver's line of sight. The display device may include one or more reflecting surfaces and one or more refracting surfaces for directing the overlaying displays into the driver's line of sight. |
| US09159298B2 |
Terminal and contents sharing method for terminal
Disclosed is a terminal and corresponding control method, one embodiment of the terminal including a display unit; a wireless communication unit configured to form a network with at least one external terminal; and a controller configured to set up at least two second display regions displayed on a first display region of the external terminal, and control the wireless communication unit to transmit information corresponding to the second display regions to the external terminal. |
| US09159296B2 |
Synchronizing views during document presentation
An application synchronizes views during document presentation. The application detects a selection of a section of a portion of presented content at a presenter view. The application shifts the portion of the content displayed at an attendee view to bring to focus the selection. Alternatively, the application displays the selection in a pop-out view pane within the attendee view to bring to focus the selection. The application also shifts content in the attendee view according to an offset ratio calculated from comparing a non-displayed section of a page of the document and a displayed section of a page of the document within the presenter view. |
| US09159295B2 |
Organic light emitting display device
An organic light emitting display device includes a plurality of pixels, each of the plurality of pixels including: a first sub-pixel configured to emit light of a first color; a second sub-pixel configured to emit light of a second color that is different from the first color; a third sub-pixel configured to emit light of a third color that is different from the first and second colors; and a transmission sub-pixel configured to selectively transmit external light in response to an electrical signal. |
| US09159294B2 |
Buttonless display activation
In one example, a method includes determining, by a first motion module of a computing device and based on first motion data measured by a first motion sensor at a first time, that the mobile computing device has moved, wherein a display operatively coupled to the computing device is deactivated at the first time; responsive to determining that the computing device has moved, activating a second motion module; determining, by the second motion module, second motion data measured by a second motion sensor, wherein determining the second motion data uses a greater quantity of power than determining the first motion data; determining a statistic of a group of statistics based on the second motion data; and responsive to determining that at least one of the group of statistics satisfies a threshold, activating the display. |
| US09159293B2 |
Electronic device, control method, and storage medium storing control program
According to an aspect, an electronic device includes a first face, a second face, a display unit arranged on the first surface, a notification unit arranged on the second surface, an attitude detecting unit, and a control unit. The attitude detecting unit detects whether attitude of the electronic device is a first attitude, in which the first surface faces upward in the vertical direction, or a second attitude, in which the first surface faces downward in the vertical direction. When the attitude detecting unit detects the second attitude, the control unit prevents displaying on the display unit and enables the notification unit to give a notification. |
| US09159292B2 |
Display panel and display apparatus having the same
A display panel includes setting gate lines to which a setting gate signal is applied, charging gate lines to which a charging gate signal is applied; data lines to which a data voltage is applied, and pixels connected to the setting gate lines, the charging gate lines and the data lines, where each of the pixels includes a first switching element connected to a corresponding setting gate line and a corresponding data line, a control capacitor configured to charge an output voltage of the first switching element, an amplifying part configured to amplify the output voltage of the first switching element charged at the control capacitor, a power supplying part connected to a corresponding charging gate line and configured to supply power to the amplifying part, and a liquid crystal capacitor configured to charge an output voltage of the amplifying part. |
| US09159289B2 |
Liquid crystal display and the driving method thereof
A liquid crystal display and the driving method thereof are disclosed. The liquid crystal display includes a plurality of pixels, data lines for transmitting data driving signals to the pixels, a scanning driver for generating scanning driving signals, a waveform shaping circuit for connecting with the scanning driver, a plurality of scanning lines for transmitting the shaped scanning driving signal to the pixels. The waveform shaping circuit shapes the waveforms of the scanning driving signal along a rising edge. In this way, the voltage difference between the pixel electrodes is eliminated. Thus, the color shift is reduced, and the display performance of the liquid crystal display is enhanced. |
| US09159286B2 |
Display panel, liquid-crystal display device and drive method
The present invention includes, in addition to transistors each (Mm,n) provided at the intersection of a gate bus line (GLn) with a data bus line (DLm): block potential applying transistors (DMn) connected to respective ends of gate bus lines (GLn) which ends are not connected to a gate driver (11); a potential supply line (VLL) connected to the gate bus lines (GLn) via the block potential applying transistors (DMn); and a blocking signal supplying section (131) for, immediately after the gate driver (11) supplies a first conduction signal for bringing the transistors (Mm,n) into conduction, supplying to the block potential applying transistors (DMn), a second conduction signal for bringing the block potential applying transistors (DMn) into conduction. |
| US09159284B2 |
Liquid crystal display device using corrected moving picture data
A liquid crystal display device includes a liquid crystal panel including a plurality of signal lines, a liquid crystal panel driving unit configured to provide a driving voltage to the plurality of signal lines, an image data judging unit configured to judge whether input image data is still image data or moving picture data, an image data correcting unit configured to correct moving picture data to output corrected moving picture to the liquid crystal panel driving unit, a plurality of light sources configured to provide a light to the liquid crystal panel, and a light source driving unit configured to detect a display region having a motion value larger than a reference value from among an image of which frame data is displayed, based on a comparison of current frame data of the moving picture data with previous frame data of the moving picture data. |
| US09159283B2 |
Switch circuit, pixel element and display panel for using in refreshing memory in pixel
A switch circuit, a pixel element and a display panel are provided. The switch circuit is for the pixel element, and includes switches. A switch is turned on to perform a sample operation on the pixel element. Another switch has a control terminal coupled to an image data storage capacitor of the pixel element via the switch, a data terminal to a corresponding source line, and another data terminal to the image data storage capacitor. During the sample operation, the second switch stores an image data of the image data storage capacitor in a parasitic gate capacitor existing on its control terminal. The parasitic gate capacitor maintains its stored data from the sample operation to a refresh operation in which the pixel element is refreshed. The second switch selectively electrically connects its two data terminals with each other according to stored image data in the parasitic gate capacitor. |
| US09159279B2 |
Liquid crystal display device and display control method thereof
The present invention provides a liquid crystal display device and display control method thereof. Each sub-pixel of the liquid crystal display device includes multiple display regions and multiple control switches for controlling the display regions to receive corresponding data voltages, wherein, the multiple control switches includes a first control switch set and a second control switch set, and the first control switch set and the second control switch set are connected in parallel with the same data line. Through the above way, the present invention can increase the pixel aperture ratio of the wide-viewing-angle liquid crystal display device and decrease the power consumption. |
| US09159278B2 |
Overdrive method, apparatus, and display device
In one embodiment of the present invention, an overdrive (OD) method includes: acquiring a display grayscale value of a current frame within a display grayscale range; obtaining a target grayscale value of the current frame within a target grayscale range according to the display grayscale value of the current frame, where a minimum target grayscale value is larger than a minimum display grayscale value, and/or a maximum target grayscale value is smaller than a maximum display grayscale value, and each display grayscale value within the display grayscale range correspond one by one to one target grayscale value within the target grayscale range; and obtaining a system grayscale value of the current frame according to the target grayscale value of the current frame and a display grayscale value or a system grayscale value of a previous frame, and outputting a corresponding gamma voltage according to the system grayscale value. |
| US09159276B2 |
Method for creating bit planes using a digital signal processor and double index addressing direct memory access
According to one embodiment of the present invention, a method for creating bit planes from frame data for a digital mirror device is disclosed including forming data elements comprising bits of equal significance from a plurality of pixel data in the frame data, the forming including using dual index direct memory address operations. |
| US09159275B2 |
Display device and driving method thereof
A method for reducing afterimages in a device for displaying images by application of an electric field to a charged substance is provided. A plurality of pixels each include a display element including a pixel electrode, a charged layer, and a counter electrode. The display device has a function of applying different potentials to pixel electrodes that are adjacent to each other in a period during which the pixels are initialized. Thus, electric fields are generated not only in a direction perpendicular to the pixel electrodes but also in a direction parallel to the pixel electrodes (the end-face direction of the pixel electrodes), so that charged substances in the charged layer stir. Accordingly, aggregation can be prevented. |
| US09159274B2 |
Driver for page transitions in an electronic paper device
A system and a method for updating an electronic paper display are disclosed. A memory includes a waveform table and a transition matrix including multiple pixels, each representing a pixel of the electronic paper display. A page transition display system is coupled to the memory and identifies waveforms from the waveform table associated with multiple transition matrix pixels by processing multiple transition matrix pixels in parallel. For example, the page transition display system loads multiple transition matrix pixels into a register and accesses the waveform table using the contents of the register. Using the identified waveforms, the page transition display system generates control signals used to modify the electronic paper device. |
| US09159270B2 |
Ambient black level
Techniques for operating a display system in a wide range of ambient light conditions are provided. An intensity of ambient light on a display panel may be detected. The display panel may be illuminated by light sources in addition to the ambient light. An individual light source may be individually settable to an individual light output level. If it is determined that the luminance level of the ambient light is above a minimum ambient luminance threshold, an ambient black level may be calculated using the intensity of ambient light. Light output levels of one or more of the light sources may be elevated to first light output levels. Here, the one or more light sources may be designated to illuminate one or more dark portions of an image. The first light output levels may create a new black level equaling the determined ambient black level. |
| US09159268B2 |
Organic light emitting diode display and its driving method
An organic light emitting diode display and its driving method, in which gate signals input to transistors may be input to one pixel at an interval corresponding to ½ period of a gate shift clock. The organic light emitting diode display comprises a panel including a plurality of pixels formed by crossings of gate lines and data lines, each pixel including an organic light emitting diode and transistors; a timing controller configured to generate a gate shift clock; and a gate driver configured to receive the gate shift clock and output a plurality of gate signals to the transistors of each of the pixels based on the gate shift clock, the gate driver outputting at least one of the gate signals to a corresponding one of the transistors shifted by a time interval of one half of a period of the gate shift clock. |
| US09159266B2 |
Pixel, display device including the same, and driving method thereof
A pixel, a display device including the same, and a driving method thereof are provided. The display device includes: a display unit including pixels connected to corresponding scan lines and corresponding data lines; a scan driver sequentially generating and transmitting scan signals respectively corresponding to the pixels; a data driver generating and transmitting data voltages according to corresponding image data signals to a plurality of data lines during one frame; a first power source voltage driver respectively applying a first power source voltage to the pixels; a second power source voltage driver respectively applying a second power source voltage to the pixels; and a signal controller controlling the operation of the drivers, wherein a predetermined reference voltage is transmitted through data lines during a remaining period of one frame other than a period in which the data voltage is transmitted. |
| US09159263B2 |
Pixel with enhanced luminance non-uniformity, a display device comprising the pixel and driving method of the display device
A pixel, a display device including the same, and a driving method thereof. The display device includes: a data driver transmitting data signals; a scan driver generating and transmitting scan signals; a display panel including pixels, each emitting light with a driving current according to the data signals; a compensation signal unit generating and transmitting a compensation control signal for controlling simultaneous transmission of a predetermined bias voltage to each of the pixels before a data voltage according to the data signals is applied to each of the pixels; a power controller controlling voltage levels of the first power source voltage and the second power source voltage and supplying the level-controlled first and second power source voltages; and a timing controller generating the data signals by processing an external image signal and generating a plurality of driving control signals. |
| US09159262B2 |
Display apparatus
A display apparatus includes pixels arranged in a two-dimensional matrix pattern, each of which including a light-emitting unit and a drive circuit that drives the unit and includes a comparator circuit that compares a control pulse with potential based on signal voltage and outputs predetermined voltage based on the result, a transistor driving the unit in response to the predetermined voltage, and a current source that supplies current to the unit during driving of the transistor, includes a current-source transistor, a capacity unit connected to a gate electrode of the current-source transistor, a differential amplifier that detects a differential between voltage based on reference constant current and reference voltage, and a transistor controlling the voltage based on reference constant current depending on current flowing through the current-source transistor, and controls gate potential of the current-source transistor on the basis of output of the amplifier in synchronization with a scanning signal. |
| US09159256B2 |
Apparatus for marketing a brand
An apparatus for marketing a brand may generally comprise coupling members and an advertising member. The advertising member may serve as a marketing tool upon which a marketer can display information to a potential consumer, thereby making a commercial impression upon an end user. Each coupling member is configured to be placed upon a hook, or to receive a hook from a hanger. For example, a coupling member may be configured to receive a plurality of hooks. Said coupling members may also be equipped with adjustors, such as to allow for the apparatus to be secured to a hook, and for the plurality of hangers to be secured to the apparatus. |
| US09159255B2 |
Three-dimensional information presentation device using slit viewing
Provided is a device which can present three dimensional information by a simple structure and in which the information can be viewed with the naked eye. A plurality of rotary line-light-source units are arranged. The line-light-source units provide different pieces of image information in different directions, in order to produce a parallax between both eyes. A three-dimensional image control unit performs a control to provide thinned image information at corresponding positions to the plurality of line-light-source units and successively present the entire three-dimensional image information by scrolling. As a result, a viewer can recognize the three-dimensional image moved and presented by the scroll control. |
| US09159254B2 |
Truck mounted flag and pole assembly
A flag and pole mounting assembly for attaching a flagpole to a vehicle includes a middle shaft extending substantially between two sidewalls of the vehicle and adjustable endshafts for extending the total length of the mounting assembly. Posts at each end of the middle shaft engage with stake pockets located in the two sidewalls of the vehicle. A flagpole attachment member couples to the middle shaft and defines a cavity for receiving and securing the flagpole to the middle shaft. A light source connected to the flagpole attachment member illuminates the flagpole or an associated flag when the flagpole is coupled to the flagpole attachment member. A solar panel or other power source is electrically connected to the light source for powering the light source. The mounting assembly may only utilize one stake pocket or may engage with the sidewalls of the vehicle without use of any stake pockets. |
| US09159253B2 |
Lighting display having animated effect
A decorative lighting display including at least one string of lighting elements positioned within a display housing having a plurality of distinct regions, and wherein, when the lighting display is activated, one or more lighting elements positioned in a first region of the housing intermittingly illuminate a first portion of the display and one or more lighting elements positioned in a second region intermittingly illuminate a second portion of the display, the intermittent illumination of the first and second portions of the display cooperating to produce a dynamic or animated visual effect. |
| US09159246B2 |
Science, technology, engineering and mathematics based cyber security education system
According to one aspect, a science, technology, engineering and mathematics (STEM) based cyber security education system is provided. A training component, a knowledge component, and a collaborative component are interfaced to a distance learning component to form a STEM-based cyber security education system interface on an educational content server. The educational content server is coupled to a content database configured to access STEM-based cyber security educational content associated with one or more of: the training component, the knowledge component, and the collaborative component. Asynchronous delivery of the STEM-based cyber security educational content is provided to an end user computer in response to a user request. An interactive session is established between one or more experts and the end user computer to provide synchronous delivery of STEM-based cyber security materials. |
| US09159243B2 |
Control assistance device, control assistance method and computer readable record medium with program recorded thereon
An approach detector (20) detects the range in which a conflict will occur between an aircraft whose route is being searched and all other aircrafts on the basis of flight information acquired by a flight information acquirer (10). A first position detector (30) detects the position furthest from a position of entry in controlled airspace that the aircraft whose route is being searched can navigate to until the occurrence of the conflict. A second position detector (40), if the aircraft whose route is being searched maintains an altitude other than a set altitude, detects a position closest to a position of entry into controlled airspace that is beyond the position to which the altitude was changed from the set altitude, and that allows withdrawal from controlled airspace without the occurrence of the conflict. An altitude change detector (50) on the basis of the above described detection results detects an altitude change range that is a range in which the aircraft whose route is being searched can change altitude to avoid conflict. |
| US09159241B1 |
Methods, systems, and apparatus for synthetic instrument landing system (SILS)
Methods, systems, and apparatus for Synthetic Instrument Landing System (SILS) are disclosed. By optimally integrating new SILS capabilities on existing aircraft systems and equipment, the systems, methods, and apparatus of this disclosure affect primarily one system, the MMR, and certain aircraft wiring reconfiguration and leave most of the other airplane systems as well as pilot (flight crew) training substantially unaffected. Unlike existing solutions that are based on a classical approach of new capability integration by providing associated new landing modes that are uniquely identified, the disclosure provides only a single mode to the pilot by moving all mode-specific functionality to onboard computers such as MMRs. |
| US09159240B2 |
Methods and systems for tailored allocation of arrivals
A tailored arrival allocation system (TAAS) for determining a descent profile for an aircraft is described. TAAS includes a gateway operable for establishing communications between TAAS and aircraft, and for establishing communications between TAAS and at least one of a source of weather data, an air traffic services facility, and an airlines operations center. A processing device communicatively coupled to the gateway calculates a descent profile based on data received from a plurality of an air traffic services coordination function, an airline operations center function, data from the aircraft, and data received from a weather station that allows the aircraft to meet the required time at one or more metering fixes during the descent. Output interfaces provide data relating to the calculated descent profile to the processing device. The gateway communicates with a flight management computer for the aircraft to incorporate the calculated descent profile onto the flight management computer. |
| US09159237B2 |
Vehicle early warning system and vehicle early warning method
A vehicle early warning system and a vehicle early warning method are provided. The vehicle early warning system comprises an inter-vehicle communication device, a processor and a notice device. The inter-vehicle communication device receives an other-vehicle message package having an other-vehicle identification code and an other-vehicle sense message. The processor determines whether the other-vehicle identification code is valid. The processor determines whether the other-vehicle sense message is valid when the other-vehicle identification code is valid. The processor determines whether a driving location is on a predicated collision path according to the other-vehicle sense message when the other-vehicle sense message is valid. The notice device outputs a notice signal when the driving location is on a predicated collision path. |
| US09159231B2 |
Method for transmitting traffic information using vehicle to vehicle communication
A method for transmitting traffic information includes detecting an occurrence event by a first vehicle terminal; generating a traffic information message including information for the occurrence event by the first vehicle terminal; transmitting the traffic information message through vehicle to vehicle (V2V) communication by the first vehicle terminal; receiving and analyzing the traffic information message by the second vehicle terminal which drives in an opposite direction as compared to the first vehicle terminal; retransmitting the traffic information message to a third vehicle terminal located behind the first vehicle terminal depending on an analysis result of the traffic information message by the second vehicle terminal; and outputting an alert based on the event occurrence information of the traffic information message transmitted from the second vehicle terminal to the third vehicle terminal. |
| US09159230B2 |
Vehicle communication system
A vehicle communication system including a communications link and optionally a vehicle position indicator provided at a facility. A visual indicator is provided that is attachable to or usable in a non-official passenger vehicle to alert other road users that a vehicle is traveling in an emergency situation. A communications link and optionally a vehicle position locator are also attachable to or usable in a non-official passenger vehicle to communicate with the facility to alert the facility that the vehicle is traveling to the facility in an emergency situation. The visual indicator may be a flashing light, or a lighted warning message or symbol, and may be a one-time use light or may be operable only after receipt of an activation code from the facility. |
| US09159225B2 |
Gesture-initiated remote control programming
A method and system for configuring a universal remote control (URC) to control a remote-controlled device includes establishing a communication link between the URC and the remote-controlled device in response to detecting a gesture motion of the URC. Device information may be received from the remote-controlled device and used by the URC to program the URC to control the remote-controlled device. The URC may be configured to control a plurality of remote-controlled devices. The communication link may be a near field wireless communication link. |
| US09159224B2 |
Wireless power and data apparatus, system and method
Wireless data communication is implemented using respective carrier frequencies. As may be implemented in accordance with one or more embodiments and apparatuses herein, wireless communications are effected using a resonant circuit having a resonant frequency susceptible to detuning. Radio frequency power is transmitted to a remote transponder circuit, and wireless communications are effected with the remote transponder circuit via at least one of first and second different carrier frequencies, using the resonant circuit and the radio frequency power. The first and second carrier frequencies are respectively sufficiently proximate to the resonant frequency, such that signals communicated based on the resonant frequency can be acquired by demodulating based on the resonant frequency. One of the first and second carrier frequencies is selected based upon a signal sent from the transponder circuit. |
| US09159223B2 |
User monitoring device configured to be in communication with an emergency response system or team
A user monitoring device has one or more monitoring sensors and a unique user ID. The one or more sensors acquire user information selected from of at least one of, a user's activities, behaviors and habit information, and user monitoring. ID circuitry is at the user monitoring device. The ID circuitry includes ID storage, a communication system that reads and transmits the unique ID from an ID storage, a power source and a pathway system to route signals through the circuitry. The monitoring device is configured to be in communication with a telemetry system. The telemetry system includes a database of user ID's. The telemetry analyzes telemetry data based on at least one of, user's activities, behaviors and habit information. The telemetry system in operation is in communication with and sends a notification to an emergency response team or system when a monitored parameter is of a certain value. |
| US09159221B1 |
Steering wheel with remote control capabilities
Integrated touch sense controls installed at a steering wheel, steering wheel cover or decorative pieces installed at the steering wheel in order to capture the hands movements interpreter the finger gestures and control various devices in the car without distracting the driver while operating the vehicle. The steering wheel controls may also incorporate one or multiple displays for feedback and driver assistance. The display is located such that is always at the direct line of sight of the driver. |
| US09159209B2 |
Conductive fabric seal
Disclosed are several examples of a system and method for detecting if an article is being tampered with. Included is a covering made of a substrate that is coated with a layer of an electrically conductive material that forms an electrically conductive surface having an electrical resistance. The covering is configured to at least partially encapsulate the article such that the article cannot be tampered with, without modifying the electrical resistance of the electrically conductive surface of the covering. A sensing device is affixed to the electrically conductive surface of the covering and the sensing device monitors the condition of the covering by producing a signal that is indicative of the electrical resistance of the electrically conductive surface of the covering. A measured electrical resistance that differs from a nominal electrical resistance is indicative of a covering that is being tampered with and an alert is communicated to an observer. |
| US09159203B2 |
Automated teller machine comprising at least one camera that produces image data to detect manipulation attempts
An automated teller machine is proposed having at least one camera to detect manipulation attempts that captures images of one or more elements arranged in the control panel, such as a keypad, cash-dispensing drawer, card entry slot and generates image data from a plurality of individual image recordings (F1, F2, F3). The at least one camera is connected to a data processing unit that preprocesses the image data generated (individual image data) into a resulting image (R). The preprocessed image data of the resulting image (R) can be computed, for example, by exposure blending from the individual images (F1, F2, F3) and represent a very good data base for data evaluation to detect manipulation. |
| US09159202B2 |
Gaming system, gaming device and method providing a first game and a plurality second wagering games each associated with a separate activatable component of the first game
A gaming system having a first skill, partial skill, or pseudo skill based game having a plurality of individually activatable designated components and a plurality of second chance based games each respectively associated with a different one of the individually activatable components of the skill based game. When each designated component of the first game is activated through one or player inputs, a corresponding chance based game associated with that designated component is activated. Each chance based game randomly determines whether the player wins an award. In one embodiment, the likelihood of activating each designated component is different and the chance based game associated with each different designated component is different. |
| US09159201B2 |
Slot machine including a plurality of video reel strips
On the slot machine, a slot game including a base game and free games is caused to proceed on a display. On the base game reel strips, on all of a plurality of reels, symbols whose each kind is the same, other than feature symbols and wild symbols, are arranged in succession. On the free game reel strips, on all of a plurality of reels, symbols whose each kind is the same, other than the feature symbols and the wild symbols, are arranged in succession and in addition thereto, only in a case of top symbols whose payout multiplying factor is the highest, the top symbols whose number is larger than a number of top symbols displayed on the base game reel strips are arranged in succession. |
| US09159198B2 |
Method and system for providing electronic multiplayer tournaments with real-money prizes during tournament play
An electronic multiplayer tournament is provided in which participating players can win real-money prizes during tournament play, that is, prizes that can be redeemed for value outside of the context of the tournament prize, in addition to overall tournament prizes at the close of tournament play. The real-money prizes may include any one or more of a jackpot prize, a progressive jackpot prize or a wide-area progressive jackpot prize. A portion of a tournament entry fee can be utilized to fund the cost of the real-money prize, in direct proportion to the probability of the real-money prize being won by a participating player. |
| US09159195B2 |
Interactive gaming among a plurality of players systems and methods
A system for interactive gaming among a plurality of players includes a host computer system and a plurality of player terminals communicably coupled to the host computer system via a network. The plurality of player terminals are located at a plurality of licensed gaming locations. The plurality of player terminals are configured to engage the plurality of players in a common interactive game operated by the host computer system. The plurality of player terminals include means for dispensing player winnings from the player terminal. |
| US09159193B2 |
Method and apparatus for gaming with alternate value payouts
Systems and methods are provided for permitting a player to play a game at a gaming device. The gaming device provides a payout for the game. The payout is redeemable for one of a plurality of values, and at least two of the plurality of values are different from each other. The values typically have different corresponding forms of payout, such as cash or merchandise credits. |
| US09159188B2 |
Data generating method, gaming method, and gaming machine
A method of generating data for controlling an operation of a gaming machine is provided. The gaming machine includes a reel, a first driver for driving the reel, a rendering device, and a second driver for driving the rendering device. A data sheet including a plurality of rows and a plurality of columns is provided. Columns include a trigger field, a reel field being predefined to be associated with the first driver, and an effect field being predefined to be associated with the second driver. When a first command for controlling the first driver is input to in the reel field of the first set of rows, and at least one second command for controlling the second driver is input to the effect field of the first set of rows, the second command is executed in synchronization with the first command. |
| US09159186B2 |
Method and apparatus for providing a complimentary service to a player
Systems and methods are provided for providing a service to a player using a player device. A indication of a player identifier which corresponds to a player of a gaming device is received. A player device is provided to the player. A service to provide the player is determined based on a gaming activity of the player, and the service is then provided to the player using the player device. |
| US09159184B2 |
Peripheral device and method of detecting illegal action
A peripheral device (sandwiched device) to be installed adjacent to a gaming machine, including an imaging unit (CCD camera) configured to image a player who is playing a game with the gaming machine and output face image data for identifying the face of the player obtained by imaging, and a CPU configured to: obtain information about a game the player played with the gaming machine; determine whether or not an illegality condition is met based on the obtained information about the game; and set whether or not to activate the imaging unit based on the determination result. |
| US09159180B2 |
Media conveying
A method and apparatus are disclosed for conveying at least one item of media. The apparatus includes a user interface comprising a media port and a user display. The apparatus also includes a shuttle carriage supporting a presentation platform and movable along a shuttle drive rail between a first end region thereof in which the presentation platform can be aligned at the media port and a further end region in which the presentation platform can be selectively aligned with a selected one of a plurality of possible handling ports of a multi-media station. |
| US09159178B2 |
In-vehicle control system and in-vehicle control apparatus
An in-vehicle control system includes an in-vehicle control apparatus and a different in-vehicle apparatus communicably connected with each other. The different in-vehicle apparatus outputs detection data including a vehicle signal, result information indicating a diagnostic result of a self-diagnostic process, and time information indicating elapsed time measured from an appearance of an abnormal symptom in the vehicle signal. The in-vehicle control apparatus stores at least the vehicle signal as preliminary analysis data in a first storage in time series, and reads out, from the first storage, one preliminary analysis data upon a confirmation of an abnormality detection data including the result information indicating abnormality occurrence. The readout data is stored prior to a confirmation time of the abnormality detection data by the measured elapsed time. Then, the in-vehicle control apparatus stores the readout data in a second storage as an analysis data. |
| US09159177B2 |
Device for monitoring the process of driving a vehicle
Device for monitoring the process of driving a vehicle consisting of at least the following: a first means of processing a signal; a second means of detecting the vehicle movement; a means for providing an HMI type of interactive display of information for the user; and a means configured for knowing the consumption characteristics of the vehicle and its technical characteristics as far as optimum theoretical behaviour; where the means for processing are configured for calculating the optimum consumption according to the characteristics of the vehicle, establishing the driving parameters required for equating the actual consumption to the optimum consumption, displaying this information to the user in the means available for display. |
| US09159171B2 |
Integration of position and road charging data
A method and apparatus are disclosed wherein positioning data and road charging data depending on a vehicle position may be inserted into a combined data stream. The positioning data and road charging data may be provided with the same protocol type such as a national marine electronics association, NMEA, protocol or NMEA 0183 protocol. The combined data stream therefore comprises a mixed sequence of positioning data protocol messages and road charging data protocol messages. |
| US09159166B2 |
Coordinate geometry augmented reality process for internal elements concealed behind an external element
Embodiments of the invention include a method, a system, and a mobile device that incorporate augmented reality technology into land surveying, 3D laser scanning, and digital modeling processes. By incorporating the augmented reality technology, a 3D digital model of internal elements concealed behind an external element can be visualized on a live view, aligned to the orientation and scale of the scene displayed on the mobile device. In an embodiment, a marker can be placed at a predetermined set of coordinates on the external element, determined by surveying equipment. The 3D digital model of the internal elements can be retrieved by the mobile device and overlaid in relation to the marker position, orientation, and size so that it is seen at a calculated distance in depth behind the external element as they would exist hidden behind the external element in the real environment. |
| US09159165B2 |
Position-dependent gaming, 3-D controller, and handheld as a remote
Methods and systems for using a position of a mobile device with an integrated display as an input to a video game or other presentation are presented. Embodiments include rendering an avatar on a mobile device such that it appears to overlay a competing user in the real world. Using the mobile device's position, view direction, and the other user's mobile device position, an avatar (or vehicle, etc.) is depicted at an apparently inertially stabilized location of the other user's mobile device or body. Some embodiments may estimate the other user's head and body positions and angles and reflect them in the avatar's gestures. |
| US09159161B1 |
Systems and methods for creating a two-dimensional representation of a model
A method of creating a two-dimensional representation of a model. The method includes receiving data corresponding to a first component and at least one second component of the model, defining a first component representation, defining the at least one second component representation, determining a visibility of the plurality of graphics of the first component representation, determining a visibility of the plurality of graphics of the at least one second component representation, defining a structure of the first component representation, defining a structure of the at least one second component representation, defining one or more display rules, and generating an illustration file. |
| US09159157B2 |
Apparatus and method for tile binning
An apparatus and method for tile binning are provided. The tile binning apparatus may include a determination unit to determine whether a triangle obtained as a result of geometric processing includes an abnormal edge, an overlap test unit to perform an overlap test with respect to each edge of the triangle when the abnormal edge is absent from the triangle, and to sort three vertices of the triangle according to Y-axis values and perform the overlap test with respect to each edge of the triangle based on a sorting result when the triangle includes the abnormal edge, and a bin array update unit to update a bin array based on an overlap test result. |
| US09159155B2 |
Image rendering
Systems, methods, and computer program products receive an image request identifying an image having a width and a height. A number of interleaved buffers is identified, each of the interleaved buffers operable to store data associated with the image. The image is split into each of the interleaved buffers on a computing device. An interleaved image is displayed corresponding to at least one of the interleaved buffers, where the interleaved image having substantially the same width and height of the image. |
| US09159153B2 |
Method, system and apparatus for providing visual feedback of a map view change
Methods, systems and apparatus are described to provide visual feedback of a change in map view. Various embodiments may display a map view of a map in a two-dimensional map view mode. Embodiments may obtain input indicating a change to a three-dimensional map view mode. Input may be obtained through the utilization of touch, auditory, or other well-known input technologies. Some embodiments may allow the input to request a specific display position to display. In response to the input indicating a change to a three-dimensional map view mode, embodiments may then display an animation that moves a virtual camera for the map display to different virtual camera positions to illustrate that the map view mode is changed to a three-dimensional map view mode. |
| US09159144B2 |
Color adjustors for color segments
A non-transitory machine readable medium that has a computer program for adjusting color values of an image represented in a color space. The image includes a set of pixels. Each pixel has a set of color values. The computer program receives a user input on a user interface (UI) item for adjusting color values of an image that are associated with a type of content. The computer program identifies a subset of pixels having color values that fall within a range of color values associated with the type of content. The computer program performs a color adjustment operation on the identified subset of pixels. |
| US09159140B2 |
Signal analysis for repetition detection and analysis
Techniques described herein use signal analysis to detect and analyze repetitive user motion that is captured in a 3D image. The repetitive motion could be the user exercising. One embodiment includes analyzing image data that tracks a user performing a repetitive motion to determine data points for a parameter that is associated with the repetitive motion. The different data points are for different points in time. A parameter signal of the parameter versus time that tracks the repetitive motion is formed. The parameter signal is divided into brackets that delineate one repetition of the repetitive motion from other repetitions of the repetitive motion. A repetition in the parameter signal is analyzed using a signal processing technique. Curve fitting and/or autocorrelation may be used to analyze the repetition. |
| US09159133B2 |
Adaptive scale and/or gravity estimation
Systems, apparatus and methods for estimating gravity and/or scale in a mobile device are presented. A difference between an image-based pose and an inertia-based pose is using to update the estimations of gravity and/or scale. The image-based pose is computed from two poses and is scaled with the estimation of scale prior to the difference. The inertia-based pose is computed from accelerometer measurements, which are adjusted by the estimation for gravity. |
| US09159130B2 |
Alignment of an ordered stack of images from a specimen
The present invention relates to the field of alignment of an ordered stack of images from a sliced specimen. According to the present method and apparatus, the ordered stack of images is aligned by successively determining, for at least two already aligned images of the ordered stack, the respective misalignments with an unaligned image which is to be aligned next, selecting from the at least two aligned images as a reference image that aligned image with which the unaligned image has the smallest amount of misalignment, and aligning the unaligned image with the selected reference image. This is intended to provide a robust and computationally cheap aligning method and apparatus. |
| US09159126B2 |
System and method for analyzing and processing food product
Systems and methods are described that provide a fast and simple way of processing meat or food products. Information is compiled and analyzed regarding the condition of a carcass, meat product, styling of the meat product and associated tray or package. Information is used in various processes, including determining which further processing steps are required. The information is also stored for future reference and analysis. |
| US09159118B2 |
Image processing apparatus, image processing system, and non-transitory computer-readable medium
An aspect of the present invention provides an image processing apparatus including: a people detecting unit that detects image portions of faces of a plurality of people in an image; and an image converting unit that enlarges a portion below a horizontal line segment of the image in a manner that locates the horizontal line segment at a top end of the enlarged image based on upper end positions of the detected faces. The horizontal line segment is on or above the extracted faces and has a lateral width equal to or larger than a lateral width of the faces. The image processing apparatus performs enlargement with reference to the faces so as not to warp the faces. |
| US09159117B2 |
Drawing data generation apparatus, drawing data generation method, program, and drawing data generation system for changing magnification of displayed images
A drawing data generation apparatus includes an image acquiring unit, a magnification acquiring unit, and a generation unit. In this case, the generation unit generates the drawing data in a first layout and in a second layout, and, in the first layout, a partial area in the display image is displayed with the first magnification at a position where the partial area has been displayed and, in the second layout, a partial area in the display image is displayed with the second magnification at a position where the partial area has been displayed, the partial area and a surrounding area of the partial area are displayed with a lower magnification than the second magnification, and the partial area with the second magnification and the partial area with the low magnification do not overlap. |
| US09159115B1 |
Processing vectorized elements associated with IT system images
There is disclosed a technique for use in processing vectorized elements on a mobile computing device. A vector list is received, wherein the list comprises a set of vectors having positional and magnitude values associated with identified markers. A first test angle and stride size is determined. Vectors falling within a boundary defined by the first test angle and first stride size are analyzed and a likelihood the vectors form a line is determined. An increment size is adjusted if a positive determination result occurs. Vectors that intersect with a line are identified, wherein the vectors include vectors determined to fall with the boundary defined by the first test angle and first stride size. Based on a first policy, vectors that intersect the line are identified. A report including anchor information associated with the identified vectors is created. |
| US09159111B2 |
Method for reporting and relating firearm discharge data to a crime reporting database
A method for utilizing firearm discharge data in a crime reporting and tracking database, includes: recording one or more discharges of a firearm; transmitting information from the discharging firearm to a crime reporting and tracking database; utilizing the transmitted information to establish relationships between the discharged firearm, committed crimes, and missing persons within the crime reporting and tracking database; and wherein the recording and transmitting is carried out by devices within the firearm. |
| US09159110B2 |
System and method for propagating inquiries and answers thereto through on-line human network
Disclosed is a method for sharing reliable information or knowledge with regard to a question using an on-line human network. The on-line human network-based knowledge sharing method is to share knowledge based on an acquaintance information database. The database stores the IDs of a plurality of users, and the correspondence relationships of the user IDs, which represent acquaintanceships between the users on the on-line human network. The method includes allowing a first user to write a question message in a form that can be forwarded through the network, generating a question ID for identifying the question message and storing the generated question ID, causing the ID of the first user to correspond to the question ID, allowing a second user who is acquainted with the first user to receive the message, and causing the ID of the second user to correspond to the question ID. |
| US09159108B2 |
Facilitating revenue generation from wholesale electricity markets
The apparatus, systems and methods herein facilitate generation of energy-related revenue for an energy customer of an electricity supplier. The apparatuses and methods herein can be used to generate operating schedules for a controller of the energy assets. When implemented, the generated operating schedules facilitates derivation of the energy-related revenue, over a time period T, associated with operation of the energy assets according to the generated operating schedule. The energy-related revenue available to the energy customer over the time period T is based at least in part on a wholesale electricity market. |
| US09159103B2 |
System and method for dynamically determining quantity for risk management
A system and method for dynamically determining quantity for risk management are described. According to one example embodiment, as a trader positions an order icon at a desired price or price-derivative value on a graphical interface, an order quantity for the order is dynamically determined based on the order price and a selected risk management formula. A trader can change the price or the price-related value for one or more orders by moving the order icons relative to a price axis on a graphical interface. In such an embodiment, the initially calculated order quantity for each order will be dynamically recalculated based on the modified orders for the trading strategy. |
| US09159099B2 |
Exception notification system and method
A system and method for distributing prepaid cash alternatives and resolving exceptions related to the sale of prepaid cash alternatives such as traveler's cheques or prepaid cards. Reports of sales may be reviewed to identify exceptions, and information explaining the exceptions may be made available electronically. Sellers may be notified of exceptions by e-mail, which may include a link or address to information explaining the exceptions. The information may be provided in real time through a secure site on a network, such as the Internet. A company may contract with business partners to sell the prepaid cash alternatives to customers, and the business partners may report the sales to the company via reports. After being notified of exceptions, business partners may provide corrected information or new information to resolve the exceptions. |
| US09159098B2 |
System for clearing financial transactions
A system is provided for clearing financial transactions as between banking institutions optionally by way of one or more clearing houses. A plurality of banking institutions are each enabled to communicate directly with each other and with at least one clearing house. Each banking institution has a computerized server programmed to address clearance requests to at least some of the plurality of banking institutions in the system by way of a particular route. The computerized server of at least one banking institution in the system is programmed to route clearance requests selectively and, as may be necessary, sequentially directly to one or more of the other banking institutions and clearing house in the alternative. Selection means associated with the computerized server are provided for selecting a particular one of said at least one other banking institution and clearing house according to a predetermined sequence and typically according to least cost. |
| US09159097B2 |
System and method for communicating with an electronic exchange in an electronic trading environment
System and methods for a connection proxy server are described. According to an example method described herein, a connection proxy server stores subscription, product tables as well as other downloads that are provided to a client terminal during initialization stage as well as later during a trading session. Upon detecting that a connection between the client terminal and a gateway is lost, the connection proxy maintains a communication session created for the client terminal at the gateway and receives data intended for the client terminal. If the connection is re-established between the client terminal and the gateway during a predetermined period of time, the connection proxy provides the stored data to the client terminal thus avoiding a surge in processing resources at the gateway due to the necessary downloads. |
| US09159095B1 |
Database driven computer systems providing real-time updatable graphical user interfaces to track real-time value of airings
In some embodiments, the present invention is directed to database driven computer systems providing real-time updatable graphical user interfaces to track real-time value of airings, including: a specifically programmed server; a database accessible by the server, where the server includes a plurality of modules configured to perform: electronically and periodically obtaining media data, web tracking transaction data, call center transaction data, and fulfillment transaction data; associating, in real time, media data records of airings of creatives to fulfillment transaction records by matching records among database tables having media data, web tracking transaction data, call center transaction data, and fulfillment transaction data; continuously calculating, in real-time, a current value of a particular airing of a particular creative; and displaying a graphical user interface, including real-time updated look-up items, outputting one or more real-time report based at least on the continuously calculating the current value of the particular airing. |
| US09159091B2 |
Method and apparatus for personalized content-sharing and gifting via a communication medium
The present disclosure describes one or more apparatuses and methods to allow users to generate a greeting card by defining a theme, a personalized message, content, and optionally a gift. |
| US09159083B1 |
Content evaluation based on user's browsing history
A computerized method and apparatus for evaluating content on a computer network. The method includes obtaining a quality score of content configured for display with a web page, wherein the quality score is based at least in part on keywords associated with the content and either a search query or metadata associated with the web page. The method also includes identifying a user metric of a computing device associated with the search query or the metadata. The method further includes generating an adjusted quality score of the content based on the quality score and the user metric. The method also includes selecting a parameter for an auction based on the adjusted quality score, wherein the parameter indicates a relation between a bid value based auction and a content quality based auction. |
| US09159080B2 |
Providing city services using mobile devices and a sensor network
Apparatus and methods related providing city services, such as parking, are described. A mobile device can be configured to receive information from parking sensor nodes in the vicinity of the mobile device. In a parking application, the mobile device located in a moving vehicle can be configured to locate available parking based upon the information received from the parking sensor nodes. After an available parking space is obtained, the mobile device can be configured to initiate a purchase of parking and receive information related to parking enforcement. The mobile device can be configured to receive other types of information from local sensor nodes, such as transportation related sensor nodes and merchant provided sensor nodes. Based upon the information received from the local sensor nodes, a transportation application executing on the mobile device can be utilized to formulate a transportation solution involving one or more transportation modes. |
| US09159075B2 |
System and method for distribution and redistribution of electronic content
A system and method for enabling the recordation of electronic content that has been published via a network, such as the Internet, so that the electronic content may be stored, retrieved, shared, and manipulated by individual users. Furthermore, the system and method of the present invention enable the content publisher of the electronic content to analyze activity associated with its storage and sharing. |
| US09159072B2 |
Systems and methods for marking collectibles to increase their uniqueness
According to an embodiment of the present invention, a method for marking collectible items to increase their collectible uniqueness includes creating a multiplicity of unique date codes, each of the multiplicity of unique date codes including a representation of a calendar month and a representation of a day in the calendar month, randomly selecting one of the multiplicity of unique date codes, and affixing the randomly selected one of the multiplicity of unique date codes to a collectible item. According to other embodiments, a system with a computer and a marking device may apply a date code to a collectible item. According to yet other embodiments, a method for marking collectibles includes creating at least three hundred sixty-five collectibles in a time period shorter than a year, and marking each with a unique date code combination such that no two visually identical collectibles share the same date code. |
| US09159069B1 |
System for encoding customer data
A rules engine stores a first rule, a second rule, and customer data. The rules engine transforms a portion of the customer data into a first code segment by applying the first rule and transforms a portion of the customer data into a second code segment by applying the second rule. In addition, the rules engine combines at least the first code segment and the second code segment to form a customer profile code. The generated customer profile code is associated with a customer identifier. A decision engine communicatively coupled to the rules engine matches the customer identifier of the customer profile code to third party data associated with a request for customer information. An interface engine communicatively coupled to the decision engine communicates the customer profile code to a third party if the customer identifier of the customer profile code matches the third party data. |
| US09159068B2 |
Service management using user experience metrics
A method, system, and computer usable program product to determine a first mood of the user, where the first mood is based on a characteristic of the user at a first time during the providing of an online service and to determine a second mood of the user, where the second mood is based on a characteristic of the user at a second time during the providing of the online service. The first mood of the user and the second mood of the user are compared to determine a delta or change in mood of the user. |
| US09159066B2 |
Method and system for adaptive offer determination
The optimization system monitors a mobile phone user's behavior in response to an offer for a reward and determines a good level for a product promotion. The determination may be made based upon the user's current response, past response patterns to various reward levels or a correlation between a user's behavior and the behavior corresponding to a class of users. The system can determine an offer level that maximizes the return on the profit or revenue from a potential purchase for which the offer applies. |
| US09159063B1 |
Systems and methods for rapidly provisioning functionality to one or more mobile communication devices
Systems and methods for rapidly provisioning functionality to one or more mobile communication devices are disclosed. The method may comprise transmitting, by a mobile communication device, a request to receive application functionality, receiving, by the mobile communication device, a preformed perso-script, wherein the perso-script comprises a file that includes customer information and is prepended by a key rotation portion, processing, by the mobile communication device, the key rotation portion to rotate to a new set of encryption keys, and/or transmitting, by the mobile communication device and to an application service provider, a result of the key rotation. |
| US09159060B2 |
Paperless receipt device
A process and apparatus provide a paperless electronic receipt. A storage device stores a communication identifier prior to a transaction at a point of transaction. Further, a transmitter sends the communication identifier to a point of transaction receipt transmission device at a point of transaction so that the point of transaction receipt transmission device sends an electronic receipt of a transaction at the point of transaction to the communication identifier based upon a selection being received at the point of transaction receipt transmission device to send the electronic receipt to the communication identifier. In addition, the electronic receipt is received and stored at the storage device based upon a selection being received at the point of transaction receipt transmission device to store the electronic receipt at the storage device. |
| US09159058B2 |
Online payment transfer and identity management system and method
A payment transfer method for transferring funds from a payer to payee is provided, including designating a payee and specifying a payment amount and an account; debiting the funds from the account and crediting a first trust account; and identifying the payee by verifying responses received in response to one or more challenge-response questions defined by the payer. If the one or more responses are verified, a second trust account may be debited and a payee account credited with the payment amount. The first and second trust accounts may then be reconciled. There is also provided a payment transfer facility for transferring funds, comprising an application server for storing payment data relating to a transfer of funds and a notification server for providing a notification of the transfer of funds. |
| US09159056B2 |
System and method for determining the value of a crowd network
The present invention proposes that the value of a crowd network comes from network entropy and a very well engaged crowd has more value than a poorly engaged crowd. The engagement (and the resultant value generated from the engagement) of a crowd network can be measured in terms of the entropy of the network. The entropy is calculated as a function of the probability distribution of incoming and outgoing messages, which represents the entropy or uncertainty in the activity over the network. In this way, the activity occurring over a network in terms of message exchange is translated as a measure of the value of the network. An evolutionary algorithm is presented to optimize the entropy of a network by successively changing the network topology. Results indicate that the value of a crowd network very closely relate to its small world-ness, sparsity, and connectedness. |
| US09159049B2 |
System and method for managing publications
A system and method of managing publications is disclosed. A system that incorporates teachings of the present disclosure may include, for example, a Address Book System (ABS) having a controller element to adjust publication privileges of a publisher of a portion of an address book stored in the ABS responsive to detecting that a number of recipients of an invitation to subscribe to the portion of the address book have declined the invitation and the number of declined invitations exceeds a first threshold. Additional embodiments are disclosed. |
| US09159048B2 |
Knowledge gathering system based on user's affinity
A system, method, and processor readable medium for processing data in a knowledge management system gathers information content and transmits a work request for the information content gathered. The information content may be registered with a K-map and assigned a unique document identifier. A work queue processes the work requests. The processed information may then be transmitted to another work queue for further processing. Further processing may include categorization, full-text indexing, metrics extraction or other process. Control messages may be transmitted to one or more users providing a status of the work request. The information may be analyzed and further indexed. A progress statistics report may be generated for each of the processes performed on the document. The progress statistics may be provided in a record. A shared access to a central data structure representing the metrics history and taxonomy may be provided for all work queues via a CORBA service. |
| US09159046B2 |
Systems and methods for implementing supply chain visibility policies
Methods, storage medium and systems for implementing visibility policies within a supply chain include storing event data on a computer-readable storage medium of a first partner, the event data corresponding to at least one event associated with an item while the item was in possession of the first partner, the item having traveled through the supply chain, transferring evidence of possession between the plurality of partners as the item travels through the supply chain, and requesting access to the event data by a second partner. Implementations further include determining that the item traveled through a portion of the supply chain based on the evidence, authenticating an identity of the second partner, and authorizing the second partner to access the first event data, when it is determined that the item traveled through the portion of the supply chain and when the identity of the second party is authenticated. |
| US09159045B2 |
Systems and methods for receiving shipment parcels
Disclosed are various embodiments of systems and methods for receiving shipment parcels at, for example, materials handling facilities. In some embodiments, a parcel monitoring system detects an exception for a shipment parcel. The parcel monitoring system identifies a vendor associated with the shipment parcel. In response to the exception being detected, the parcel monitoring system controls a conveyor system in accordance with an action specified by an exception handling rule for the vendor. |
| US09159044B2 |
Notification system based on intelligent mail barcodes
An approach is provided to notify an addressee of postal mail. The approach is performed by reading an enhanced mail barcode affixed to the postal mail. The enhanced mail barcode identifies a contents of the postal mail. The approach further retrieves an electronic contact address that corresponds to the addressee of the postal mail. Finally, the approach transmits an electronic notification, such as an email, text message, voice message, etc. to the retrieved electronic contact address that corresponds to the addressee. |
| US09159039B2 |
Complexity reduction of user tasks
An exemplary method for reducing complexity of at least one user task includes steps of calculating a complexity metric for the at least one user task; identifying one or more usability issues having a measurable impact on the complexity metric for the at least one user task; determining one or more recommendations for addressing at least one of the one or more usability issues; and displaying a representation of at least one of the one or more usability issues and of at least one of the one or more recommendations. In an illustrative embodiment, implementing any one of the one or more recommendations reduces the impact of the usability issue on the complexity metric of the at least one user task and thereby reduces a complexity of the at least one user task. |
| US09159038B2 |
Pre-paid service system and method
A pre-paid service system configured to provide a subscriber interface to a Subscriber and receive a service level selection from the subscriber, wherein the service level selection includes a capacity limit and/or a time limit. Upon authorization of a payment, the system activates the Subscriber's service. The system also monitors the Subscriber's usage data and time of activation. When the Subscriber's usage data amount or time of activation meets or exceeds the selected service level, the system may deactivate the Subscriber's service. |
| US09159037B2 |
Context aware interaction
A network-connected server for meeting initiation has software executing on the server from a non-transitory physical medium, the software providing a function allowing a user to schedule a meeting and to configure availability conditions, a function for informing scheduled participants of the scheduled meeting, a function for receiving indications of availability for the scheduled meeting from communication appliances associated with scheduled participants, and a function for connecting the communication appliances to communicate when the configured availability conditions are met. |
| US09159035B1 |
Framework for computer application analysis of sensitive information tracking
A method is described that involves generating one or more machine learned rules with a machine learning system. The method also involves generating a representation of an application that describes various states and state transitions of the application. The method also involves referring to the one or more machine learned rules and the representation to identify a region of interest of the application. The method also involves configuring one or more monitors for the application to be enabled in a run time environment of the application. The method also involves setting conditions of the application within the run time environment to drive the application's execution to the region of interest. The method also involves observing behaviors of the application and determining whether the region of interest corresponds to improperly behaving code. |
| US09159034B2 |
Geographically localized recommendations in a computing advice facility
The present disclosure provides a geographically localized recommendation to a user through a computer-based advice facility, comprising collecting a recommendation from an Internet source, wherein the recommendation is determined to have an interestingness aspect and a geographic location aspect, comparing the collected recommendation to a derived user taste and the user's current geographic location, determining at least one recommendation for the user based on processing on the comparison, and delivering at least one recommendation to a user's mobile communications device, wherein the user is enabled to at least one of view, save, and share the recommendation via an application at least in part resident on the computer-based advice facility. |
| US09159023B2 |
System for predicting a driver's intention to change lanes
Provided is a system for predicting a driver's intention to change lanes at a high accuracy involving a minimum amount of time delay. A driver's intention to change lanes is predicted by a prediction unit (9) by comparing motivators and inhibitors (7, 8) which may be determined from the speed of the traffic in particular the vehicle traveling ahead of the vehicle and the traffic in the adjacent lanes in relation to the traveling speed of the ego vehicle by using an ego vehicle sensor (1) and an environmental sensor (3, 4, 5) that may comprise a radio wave, optical or acoustic radar. The criteria for the motivators and inhibitors may be empirically or statistically determined, preferably by conducting a large number of tests on roads. As they can be determined before the vehicle operator starts a lane changing maneuver, the prediction made by the prediction unit may be used on a real time basis in a warning system or steering/acceleration assist system. |
| US09159019B2 |
Antenna and wireless tag
An antenna (1) in accordance with the present invention includes a ground plate (11) and an antenna element (12) provided on an identical plane or on different planes parallel to each other, and is suitable for use in a wireless tag (2). The antenna (1) in accordance with the present invention further includes a shortening capacitor (14) that bridges the ground plate (11) and an end part (12B) of the antenna element (12), the end part (12B) being opposite to the power feed-side end part. |
| US09159017B2 |
Passive, metal mount, UHF, RFID tag capable of a long read range
A passive, metal mount, UHF RFID tag with a high antenna efficiency is provided. The passive, metal mount, UHF RFID tag has a first securing surface and second securing surface which are both hinged at sides of a main body of the tag and which allow the tag to be secured to flat objects, round objects having various circumferences or to objects having unusual exterior surfaces. A pressure sensitive adhesive (PSA) tape secures the tag to the object. The tag allows the main body (or “form factor”) to be offset from a metallic asset which is tracked without the metallic object negatively interfering with the RFID. The metallic surface of the asset being tracked is used to activate the Patch antenna duality of the custom design inlay, thus increasing the radiation efficiency of the driven element (integrated circuit) and ultimately the read range. |
| US09159014B2 |
Active control secure transaction card with tuned coil
A secure transaction card does not interact with an interrogating radio frequency field without user interaction. The user interaction may include pressing on the card to cause a smartcard chip to connect to a coil on the card. The user interaction may also include exposing the card to light, motion, touch, or the like. Control of the secure transaction card may be active or passive. |
| US09159013B2 |
Mobile device with RFID capability and corresponding boot sequence
An electronic device (100) includes a control circuit (108) that is operable with a memory or storage device (120). The electronic device includes an RFID tag (113) having a second memory (118). The RFID tag can be read from, or written to, by a RFID communication device (114) when the electronic device is OFF. Device personalization can be achieved when the control circuit accesses the second memory to retrieve the device configuration data during a boot sequence and configures the electronic device in accordance with the device configuration data retrieved from the second memory during the boot sequence. Device information can be made available when the electronic device is OFF by writing the device information to the second memory. |
| US09159011B2 |
Information broadcast using color space encoded image
Embodiments of the present disclosure can include systems, methods, and non-transitory computer program products for using color space encoded images to perform image-based information broadcasting. In certain aspects, the information broadcasting can include using the encoded images to broadcast information to multiple devices within view of the encoded images. Embodiments can also include broadcasting information independent of network availability. In certain aspects, a public display having a camera can register or capture a color space encoded image from a remote device, where the encoded image encodes a request for information from a user. The public display can send the encoded image to be decoded, and receive the decoded request for information. The public display can encode an encoded image representing a response, and display the encoded image representing a response for decoding by the user. |
| US09159005B2 |
Method and apparatus for optimizing memory usage in an imaging device
A system including a communication interface, a memory, and a processor. The communication interface is configured to receive data. The memory is divided into a first retention region and a second retention region, wherein the first retention region is configured to store data for a first predetermined period of time, and the second retention region is configured to store data for a second predetermined period of time. The processor is configured to i) initially store, within the first retention region of the memory, the data that is received, and ii) in response to the data that is received having been stored in the first retention region of the memory for a time limit that exceeds the first predetermined period of time, transfer the data that is received from the first retention region of the memory to the second retention region of the memory. |
| US09159003B2 |
Optimized font subsetting for a print path
Subject matter described herein is directed to providing font-rendering information (e.g., XPS file) that is usable to print a document. For example, a font file is received that defines a font type included in the document. A determination is made that a quantity of pages of the document does not exceed a subsetting-optimization threshold. When the quantity of pages does not exceed the threshold, a subsetted font file of the font type is generated. The subsetted file is provided, such as via the spool file, to a print subsystem. |
| US09159001B2 |
Device, method, and recording medium for controlling image forming apparatus
In the case where a request for printing is mage during execution of a continuous calibration, it is possible to interrupt a job without impairing the quality of printing by performing printing after executing an effective calibration in accordance with the kind of job, however, there is no mechanism to cancel each calibration in the standby state, and in order to make cancellation, it is necessary to wait until execution of each calibration is started, and therefore, the printing chances are lessened. There is provided a mechanism to display kinds of jobs in which printing is recommended at the point of time of end of each calibration and to enable cancellation of the calibration function of calibrations other than effective calibration after the effective calibration is executed. |
| US09158995B2 |
Data driven localization using task-dependent representations
A computer implemented method for localization of an object, such as a license plate, in an input image includes generating a task-dependent representation of the input image based on relevance scores for the object to be localized. The relevance scores are output by a classifier for a plurality of locations in the input image, such as patches. The classifier is trained on patches extracted from training images and their respective relevance labels. One or more similar images are identified from a set of images, based on a comparison of the task-dependent representation of the input image and task-dependent representations of images in the set of images. A location of the object in the input image is identified based on object location annotations for the similar images. |
| US09158994B2 |
Apparatus and method for real-time capable disparity estimation for virtual view rendering suitable for multi-threaded execution
An apparatus for estimating a disparity map based on at least two images is provided. The apparatus includes at least two processing units, which include a pixel recursion unit configured to determine a disparity value as a pixel recursion disparity candidate based on a plurality of pixel values of the at least two images and a selector configured to select a selected disparity candidate to determine at least one of the disparity map values of the disparity map. The selector is adapted to select the selected disparity candidate from a candidate group assigned to the selector. The candidate group assigned to the selector includes the pixel recursion disparity candidate, a second disparity candidate and a third disparity candidate. Moreover, the selector is adapted to select the selected disparity candidate independently from a different selector of a different processing unit of the at least two processing units. |
| US09158993B2 |
Video comparison using color histograms
Methods, apparatus and articles of manufacture for video comparison using color histograms are disclosed. Example methods disclosed herein to compare video sequences include determining a color histogram corresponding to an input video sequence based on color values of pixels sampled from a plurality of video frames of the input video sequence. Such example methods also include adjusting the color histogram corresponding to the input video sequence based on a first reference color histogram corresponding to a first reference video sequence to determine a first adjusted color histogram corresponding to the input video sequence. Such example methods further include comparing the adjusted color histogram and the first reference color histogram to determine whether the first reference video sequence matches the input video sequence. |
| US09158989B1 |
Color pure scale-spaced pyramid arrangement for use in an image segregation
A method and system comprising image processing techniques is provided that utilize spatio-spectral information relevant to an image, derived from multiple sets of selectively varied representations of the image to accurately and correctly identify illumination and material aspects of the image. In an exemplary embodiment of the present invention, a scale-spaced pyramid arrangement is provided to preserve the purity of color from scale to scale, to insure accuracy in the identification of illumination and material aspects of the image. |
| US09158986B2 |
Character segmentation device and character segmentation method
A character segmentation section, for segmenting characters of a character line may include a minimum pixel-value curve creating section configured to extract a smallest pixel value in pixels composing a pixel line arranged in a direction orthogonal to a character line direction in said multi-level image data and create a minimum pixel-value curve, a character partitioning position determining section configured to determine partitioning positions of said characters, based on said minimum pixel value curve, a binarization processing section configured to detect a minimum pixel value indicating said linear drawing from said minimum pixel-value curve, acquires a binarization threshold based on said minimum pixel value, and binarizes said multi-level image data using said binarization threshold, and a character segmentation implementing section configured to extract the image data of each character. |
| US09158980B1 |
Use of relationship between activities of different traffic signals in a network to improve traffic signal state estimation
Methods and devices for using a relationship between activities of different traffic signals in a network to improve traffic signal state estimation are disclosed. An example method includes determining that a vehicle is approaching an upcoming traffic signal. The method may further include determining a state of one or more traffic signals other than the upcoming traffic signal. Additionally, the method may also include determining an estimate of a state of the upcoming traffic signal based on a relationship between the state of the one or more traffic signals other than the upcoming traffic signal and the state of the upcoming traffic signal. |
| US09158977B2 |
Method for estimating ego motion of an object
A method for estimating ego motion of an object moving on a surface, the method including generating at least two composite top view images of the surface on the basis of video frames provided by at least one onboard video camera of the object moving on the surface; performing a region matching between consecutive top view images to extract global motion parameters of the moving object; calculating the ego motion of the moving object from the extracted global motion parameters of the moving object. |
| US09158971B2 |
Self-learning object detectors for unlabeled videos using multi-task learning
A system and method enable generating a specific object detector for a category of interest. The method includes identifying seed objects in frames of a video sequence with a pre-trained generic detector for the category. An appearance model is iteratively learned for each of the seed objects using other frames in which the seed object is identified. The appearance models are learned jointly to optimize a loss function which accounts for the loss of incorrectly labeling sub-images and a regularization term which measures a distance between the appearance models. The loss of incorrectly labeling sub-images is determined using a motion model which predicts the location of the seed object in the subsequent frames so that sub-images outside the location that the current appearance model contribute to the loss. The specific object detector is then generated by aggregating the optimized appearance models. |
| US09158970B2 |
Devices, systems, and methods for visual-attribute refinement
Systems, devices, and methods for generating attribute scores obtain a plurality of object images; generate a respective first attribute score of a first attribute for each object image in the plurality of object images based on the object images; calculate a respective pairwise object-similarity measure for pairs of object images in the plurality of object images; and refine the first attribute score of an object image in the plurality of object images based at least in part on the attribute scores of other object images in the plurality of object images and on the object-similarity measures of the pairs of object images in the plurality of object images. |
| US09158969B2 |
Information processing device, server system, image processing system, and information storage device
An information processing device (first processing device) includes a captured image acquisition section that acquires a captured image from an imaging section (imaging device), a trimming range setting section that sets a trimming range to the captured image acquired by the captured image acquisition section, the trimming range corresponding to an image processing target area that is processed by a server system (second processing device), and a communication section that transmits image information to the server system via a network, the image information being information about an area of the captured image that has been set as the trimming range by the trimming range setting section. |
| US09158968B2 |
Apparatus for extracting changed part of image, apparatus for displaying changed part of image, and computer readable medium
An apparatus for extracting a changed part of an image includes a separate graphic-element acquisition unit configured to acquire separate graphic-elements included in each of a first image and a second image and an integrative graphic-element acquisition unit configured to associate the separate graphic-elements with one another based on geometric relation thereamong, and to acquire integrative graphic-elements each including the separate graphic-elements associated with one another. The apparatus further includes a correspondence relation acquisition unit configured to acquire correspondence relation between the integrative graphic-element included in the first image and the integrative graphic-element included in the second image and a changed part extraction unit configured to extract a changed part between the first image and the second image based on the correspondence relation. |
| US09158966B1 |
Character count determination for a digital image
An image processing system or electronic device may implement processing circuitry. The processing circuitry may receive an image, such as financial document image. The processing circuitry may determine a character count for the financial document image or particular portions of the financial document image without recognizing any particular character in the financial document image. In that regard, the processing circuitry may determine a top left score for pixels in the financial document, the top left score indicating or representing a likelihood that a particular pixel corresponds to a top left corner of a text character. The processing circuitry may also determine top right score for image pixels. Then, the processing circuitry may identify one or more text chunks using the top left and top rights scores for pixels in the financial document image. The processing circuitry may determine a character count for the identified text chunks. |
| US09158965B2 |
Method and system for optimizing accuracy-specificity trade-offs in large scale visual recognition
As visual recognition scales up to ever larger numbers of categories, maintaining high accuracy is increasingly difficult. Embodiment of the present invention include methods for optimizing accuracy-specificity trade-offs in large scale recognition where object categories form a semantic hierarchy consisting of many levels of abstraction. |
| US09158964B2 |
Object recognizing apparatus and method
An object recognizing apparatus and method are provided. The apparatus may include: a viewing direction estimating device configured for respectively estimating a first viewing direction of a first object captured by a first camera and a second viewing direction of a second object captured by a second camera; a feature extracting device configured for extracting one or more features respectively from an image containing the first object captured by the first camera and an image containing the second object captured by the second camera; and an object matching device configured for allocating a weight for each of the one or more features according to the first viewing direction and the second viewing direction, and calculating a similarity between the first object and the second object based on the one or more weighted features, to determine whether the first object and the second object are the same object. |
| US09158963B2 |
Fitting contours to features
Various embodiments of methods and apparatus for feature point localization are disclosed. An object in an input image may be detected. A profile model may be applied to determine feature point locations for each object component of the detected object. Applying the profile model may include globally optimizing the feature points for each object component to find a global energy minimum. A component-based shape model may be applied to update the respective feature point locations for each object component. |
| US09158956B2 |
Reader, reading method and computer program product
According to an embodiment, a reader includes an acquiring unit configured to acquire an image containing a code; a detecting unit configured to detect a plurality of local regions containing parts of the code from the image; an integrating unit configured to integrate the local regions to obtain an integrated region; and a reading unit configured to read the code on the integrated region. |
| US09158955B2 |
Code symbol reading apparatus, code symbol reading method and medium
A code symbol reading apparatus, that reads a code symbol on an object to be read by scanning the object, repeats trial to read the code symbol until the apparatus succeeds in reading, while changing a transmission frequency of a filter that processes a signal representing a light intensity variation obtained through the scan and in which transmittance depends on a frequency of the signal. |
| US09158952B2 |
Terminal having illumination and exposure control
There is set forth herein an indicia reading terminal having a first illumination and exposure control configuration and a second illumination and exposure control configuration, the first illumination and control configuration having a first associated illumination control and a first associated exposure control, the second illumination and exposure control configuration having a second associated illumination control and a second associated exposure control, wherein with the first illumination control active an average energization level of the illumination subsystem during exposure of one or more frames is higher than with the second illumination control active, and wherein with the first exposure control active an average exposure period of the image sensor array is shorter than with the second exposure control active. |
| US09158951B2 |
Laser scanning modules embodying silicone scan element with torsional hinges
A laser scanning module employs a scan mirror and magnet rotor subassembly supported by a stationary stator structure. The scan mirror and magnet rotor subassembly includes: a silicone frame having a pair of silicone torsional hinges (i.e. posts) aligned along a scan axis and a supported by a pair of support elements associated with the stator structure, to support the scan mirror and magnet rotor subassembly. When the scan mirror and magnet rotor subassembly is rotated about its scan axis, by forces generated by an electromagnetic coil structure acting on the permanent magnet mounted on silicone frame, the silicone torsional hinges are elastically distorted and generate linear restoring forces which return the rotor subassembly back to its home position about the scan axis. |
| US09158943B2 |
Encryption and decryption device for portable storage device and encryption and decryption method thereof
An encryption and decryption device for a portable storage device and an encryption and decryption method thereof are provided. The encryption and decryption device includes a storage element, a control element and an encryption and decryption circuit. The control element receives a password, saves the password to the storage element and provides an encryption and decryption command. The encryption and decryption circuit is electrically connected to a portable storage device, receives the encryption and decryption command, reads the password stored in the storage element according to the encryption and decryption command, and encrypts or decrypts data stored in the portable storage device by utilizing the password according to whether the data have been encrypted. After the data are encrypted or decrypted, the encryption and decryption circuit clears the password in the storage element. |
| US09158941B2 |
Managing access to content in a data processing apparatus
A data processing apparatus and method are provided for managing access to content within the data processing apparatus. The data processing apparatus has a secure domain and a non-secure domain and comprises at least one device which is operable when seeking to access content stored in memory to issue a memory access request pertaining to either the secure domain or the non-secure domain. Further, writeable memory is provided which can store content required by the at least one device, with the writeable memory having at least one read only region whose content is stored therein under control of a secure task, the secure task being a task executed by one of the devices in the secure domain. Protection logic is then used in association with the writeable memory, which on receipt of a memory access request seeking to access content in the at least one read only region, prevents access to that read only region if that memory access request pertains to the non-secure domain and is seeking to write content to the read only region. This enables the speed, power and flexibility benefits of placing content in writeable memory to be achieved without prejudicing the security of that content, by ensuring that that content cannot be modified from the non-secure domain. |
| US09158938B1 |
Secure data entry based on a request in an electronic document
In some embodiments, techniques for secure data entry comprise receiving a request for secure data entry in an electronic document, presenting a data field in a spoof-resistant manner, receiving field data, and securing field data. |
| US09158937B2 |
Information processing device and information processing program
An information processing device manages the protection state of original data by long-term signature data in storage-target data obtained by combining the long-term signature data and the original data. Management information having a management-target value for each management item obtained from the storage-target data recorded therein is acquired. A management-target value of a predetermined management item is acquired from the acquired management information. The acquired management-target value is compared with a value acquired from the storage-target data or a value acquired from the outside to determine the state of management. A result corresponding to the determined state of management is outputted. |
| US09158933B2 |
Protection of encryption keys in a database
System, method, computer program product embodiments and combinations and sub-combinations thereof for protection of encryption keys in a database are described herein. An embodiment includes a master key and a dual master key, both of which are used to encrypt encryption keys in a database. To access encrypted data, the master key and dual master key must be supplied to a database server by two separate entities, thus requiring dual control of the master and dual master keys. Furthermore, passwords for the master and dual master keys must be supplied separately and independently, thus requiring split knowledge to access the master and dual master keys. In another embodiment, a master key and a key encryption key derived from a user password is used for dual control. An embodiment also includes supplying the secrets for the master key and dual master key through server-private files. |
| US09158929B2 |
Cell level data accessibility
Methods, systems, and computer-readable media for determining access rights for stored data are presented. Data tables may store data that is accessible to users. A request for explicit access to data may be received from a user. The system may determine the user's identity and further determine combined access rights based on the request for explicit access to data and the identity of the user. For example, implicit access rights for a user may be based on the identity. Based on the determined access rights, the system may retrieve data from the data tables. In an embodiment, the access rights may define that a first portion of a column is to be retrieved while a second portion of the column is to be restricted, or that a first portion of a row is to be retrieved while a second portion of the row is to be restricted. |
| US09158926B2 |
Engine control unit configuration security
An engine control unit configuration security system receives a request with a serial number associated with an engine control unit and a requested engine control unit change. The system determines that the requested engine control unit change is approved and in response generates a code including a serial number associated with the engine control unit and an instruction that causes the engine control unit to implement the requested engine control unit change. |
| US09158923B2 |
Mitigating security risks via code movement
A method includes performing on a computing system a source-to-sink reachability analysis of code of an application. The reachability analysis is performed using a static analysis of the code and determines flows from sources of information to sinks that use the information. The method includes determining scopes for corresponding security sensitive operations using the determined flows, each of the security sensitive operations corresponding to statements in the code and one or more flows. A scope for a security sensitive operation includes a block of statements in the code that correspond to a set of one or more flows ending at a sink. The method includes, for each of one or more selected scopes, moving statements in a corresponding block of statements that are independent of a security sensitive operation in the block to code before or after the block. Apparatus and program products are also disclosed. |
| US09158918B2 |
Method and apparatus for determining malicious program
Various embodiments provide methods, apparatus, and computer readable medium for determining a malicious program. In an exemplary method, a specific application programming interface (API) within an application program can be obtained. Call logic for calling the specific API can be determined. The call logic can include a triggering event to trigger the specific API to be called, a feedback path provided after the specific API is called, or a combination thereof. Whether the application program is a malicious program can be determined according to the call logic. |
| US09158917B2 |
Methods, apparatuses and computer program products for auditing protected health information
An apparatus is provided for auditing protected health information of one or more patients. The apparatus includes at least one memory and at least one processor configured to detect a query to access information stored in a database including patient-related information. The processor is further configured to save the query in an event file. The processor is further configured to capture query-related information associated with the query and save the query-related information in the event file. The processor is further configured to determine that the query involves protected health information. The processor is further configured to transmit, in response to determining that the query involves protected health information, the query-related information to be used in a reporting table. Corresponding computer program products and methods are also provided. |
| US09158914B2 |
Executable component injection utilizing hotpatch mechanisms
Techniques for causing a component loader associated with a hotpatch mechanism to execute a user-mode component which, when executed, creates a user-mode process, thread, or held reference are described herein. The component may further indicate to the component loader that it lacks hotpatch data, causing the component loader to unload the component. In some implementations, a kernel-mode module may initially provide the component to the hotpatch mechanism with an entrypoint of the component set to zero and with hotpatch data for the component loader. The hotpatch mechanism may apply the hotpatch data, modifying the component loader such that the component loader requests execute rights for a section object for the component. The kernel-mode module may then set the entrypoint such that the component becomes executable, and provides the section object and component to the hotpatch mechanism to cause the component loader to execute the component. |
| US09158912B2 |
Method and apparatus for a virtual machine hosting network with user devices
A simple to customize secure IT infrastructure architecture. The IT infrastructure architecture includes a secure general purpose virtualized architecture platform. The IT infrastructure architecture is well suited for delivering simple pre-packaged software solutions to the small business segment as plug and play type appliances. In certain embodiments, the IT infrastructure architecture includes a secure virtual appliance device such as a virtual appliance universal serial bus (USB) key. The IT infrastructure architecture uses embedded server virtualization technology to host applications as a virtual appliance. |
| US09158908B2 |
Power source for in-transit electronic media
Exemplary methods, systems and components are implemented on a multipassenger transit vehicle to provide passenger access to a pre-assigned interactive electronic media device associated with a passenger identification (ID) code or associated with an on-board situs location. The electronic media device may include a storage component, and a battery module that can periodically be replaced or recharged. Security techniques may provide protection against unauthorized usage of each electronic media device, and also help prevent unauthorized removal of the electronic media device from its approved location in the transit vehicle. Selective content may be accessible or downloaded via a communication node, wherein such content may include application programs or informational data specifically correlated with a media device location or a designated vehicle passenger. Selective content and/or operation capability for the electronic media device may be varied based on predetermined qualifications or passenger request. |
| US09158907B2 |
Alternative unlocking patterns
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for receiving, by a computing system that is locked, input from a user that provides an unlocking pattern. During entry of the unlocking pattern, a display of the computing system does not provide a visual indication of an action that will be performed upon the user completing the unlocking pattern. The computing system compares the provided unlocking pattern to a plurality of stored unlocking patterns to determine whether the provided unlocking pattern matches any of the stored unlocking patterns. The stored unlocking patterns are associated with respective actions that are performed upon completion of the respective unlocking patterns. The unlocking patterns are associated with a same level of unlocked security access to the computing system. The computing system responds by unlocking the computing system and performing the action that is associated with the matching unlocking pattern. |
| US09158904B1 |
Facial recognition
An example method includes capturing, by an image capture device of a computing device, an image of a face of a user. The method further includes detecting, by the computing device, whether a distance between the computing device and an object represented by at least a portion of the image is less than a threshold distance, and, when the detected distance is less than a threshold distance, denying authentication to the user with respect to accessing one or more functionalities controlled by the computing device, where the authentication is denied independent of performing facial recognition based at least in part on the captured image. |
| US09158901B2 |
Glitch resistant device
A system and method for device security is described, the system and method including at least one integrated circuit including a CPU, a key register storing a hardware enabling key, the key including a large number of bits, such that each bit of the large number of bits has a correct value, and if any one bit of the large number of bits is set to an incorrect value the key will not function correctly a combination circuit for performing a function, ƒ, the function ƒ being essential for correct functionality of the CPU, such that the combination circuit is activated by the key, the combination circuit only performing function ƒ if each of the large number of bits of the key is set to the correct value, and there exists no set of intermediate or output bits derived from the large number of bits of the key, which determine if the combination circuit performs function ƒ, the set intermediate or output bits including fewer bits than are included in the key. Related apparatus, methods, and systems are also described. |
| US09158898B2 |
System and method for managed distribution of publication assets
A system and method is disclosed for managed distribution of publication assets. The method discloses: protecting a set of assets, retrieved from the server system, in a publication component; transferring the publication component with the protected assets from the server to client computers; previewing the publication component on one client computer based on the set of protected assets; and producing the publication component on another client computer based on the set of protected assets. The system discloses: a server system; a publication management module for: applying a set of fonts to a publication component; and transferring the publication component with the protected fonts from a server to client computers; a preview module for previewing the publication component on one client computer based on the set of protected fonts; and a production module for producing the publication component on another client computer based on the set of protected fonts. |