| Document | Document Title |
|---|---|
| US09143117B2 |
Soft error protection device
A soft error protection device includes a soft error resilient latch (SERL) and a latch coupled to a detection device and receiving a soft error pulse and a clock (CLK) signal respectively outputted by an electronic element and a CLK generator. The SERL delays the soft error pulse. In the period of a negative level of the CLK signal, the SERL stores the delayed soft error pulse corresponding to the negative level and used as a first detection data. Meanwhile, the latch stores the soft error pulse as a second detection data. The detection device receives the CLK signal, the first and second detection datum, and compares the first and second detection datum to send out a detection signal when the CLK signal rises from the negative level to a positive level. |
| US09143116B2 |
Short current-free effective capacitance test circuit and method
A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path. |
| US09143113B2 |
Resonator element, resonator, oscillator, electronic apparatus, and moving object
A resonator element includes a piezoelectric substrate including a vibrating section and a thick section having a thickness larger than that of the vibrating section. The thick section includes a first thick section provided along a first outer edge of the vibrating section, a second thick section provided along a second outer edge, and a third thick section provided along a third outer edge. A first inclined outer edge section that is inclined with respect to both of an X axis direction and a Z′ axis direction is provided in a corner section of the piezoelectric substrate where the second thick section and the third thick section are connected to each other. |
| US09143112B2 |
Circuits and methods for providing an impedance adjustment
An apparatus includes a signal generator and a control circuit. The signal generator includes a control terminal and includes a current electrode coupled to a terminal that is configured to couple to a power line to receive direct current (DC) power from a power generator. The control circuit is coupled to the current electrode and the control terminal of the signal generator. The control circuit determines an impedance associated with the power generator and applies a control signal to the control terminal of the signal generator to produce an impedance adjustment signal on the current electrode for communication to the power generator through the power line in response determining the impedance. |
| US09143111B2 |
Signal processor, signal processing method and communication device
Disclosed herein is a signal processor including: a plurality of parallel-connected variable gain amplification sections with variable gains; and a control section adapted to control the potentials of control terminals of each of the variable gain amplification sections and make transitions in the control terminal potentials according to different input signal levels. |
| US09143107B2 |
System and method for dynamically mixing audio signals
A system and method for dynamically mixing audio signals may calculate a signal amplitude for each of two or more audio signals. The signal amplitude may be the absolute value of the audio signal. A signal sum may be calculated using each of the two or more signal amplitudes. Each of the two or more signal amplitudes may be smoothed. The signal sum may be smoothed. The smoothing may be a filter or a leaky integrator. A respective mixing gain may be calculated for each of the two or more audio signals using a respective ratio of each of the two or more smoothed signal amplitudes and the smoothed signal sum. Each of the two or more audio signals may be gain adjusted responsive to the respective mixing gain. Each of the two or more gain adjusted audio signals may be mixed to create an output signal. |
| US09143105B2 |
Sigma-delta modulator approach to increased volume resolution in audio output stages
A variable gain analog amplifier is described that uses pulse-density modulation in the form of a sigma-delta modulator (SDM) to produce a gain by modulating the selection of a switch that selects the amount of resistance in a negative feedback loop of the amplifier. The output of the SDM is dithered to increase the gain resolution of the analog amplifier, wherein the increased resolution produces a quiet, inaudible transition between changes in gain setting at an output of the variable gain amplifier and in addition produces a quiet, inaudible mixing and merging of audio signals. |
| US09143098B2 |
Systems and methods for biasing amplifiers with adaptive closed loop control
Various embodiments described herein provide systems and methods for improved performance for power amplifiers, particularly GaN power amplifiers. According to some embodiments, a power amplifier (e.g., GaN power amplifier) utilizes an adaptive closed loop control of the drain current of the power amplifier to achieve improved performance for the power amplifier. |
| US09143097B2 |
RF power amplifier and operating method thereof
A multiband RF power amplifier includes a first band RF amplifier circuit, a second band RF amplifier circuit and a second band power detection circuit. The second band RF amplifier circuit subjects an RF input signal having a frequency band to power amplification and generates an RF amplifier output signal. The input terminal of the second band power detection circuit is coupled to the output of the second band RF amplifier circuit. The second band power detection circuit detects a harmonic component that is a whole number multiple of a fundamental wave component of the RF amplifier output signal, and generates a detected signal indicating the fundamental wave component. The second band power detection circuit includes an input circuit, which detects the harmonic component, and an output circuit, which generates the detected signal. |
| US09143093B2 |
Impedance matching system that has a transformer and method for tuning a system using a transformer
A system that includes an amplification circuit; a resonant circuit that is arranged to receive the amplified signal and to output an resonant circuit output signal; wherein the resonant circuit comprises a continually tuned variable capacitor; a transformer that is arranged to receive the resonant circuit output signal and to output a transformer output signal; a coupler that is arranged to sample the transformer output signal and a reflected signal and to output a first signal that represents the transformer output signal and a second signal that represents a reflected signal; a detector that is arranged to receive the first and second signals and to output an impedance indicative signal a control circuit that is arranged to generate the resonant circuit tuning signal in response to the impedance indicative signal and for compensating for the impedance mismatch. |
| US09143090B2 |
Output voltage stabilization circuit of display device driving circuit
The present invention relates to an output voltage stabilization circuit. Specifically, the present invention relates to an output voltage stabilization circuit of a display device driving circuit, which generates a reference current dependent on a high source voltage using a current source independent of a magnitude of the high source voltage, generates a reference current dependent on a low source voltage using a current source independent of a magnitude of the low source voltage, and then generates a control signal by comparing the magnitudes to each other, whereby the output voltage stabilization circuit may stabilize an output voltage regardless of an order in which the low source voltage and the high source voltage are turned off in a circuit using both the low source voltage and the high source voltage. |
| US09143088B2 |
Control modules
A circuit is provided comprising detector circuitry, calculating circuitry, and determining circuitry. The detector circuitry is figured to generate an I data signal magnitude value of a sampled I data signal and a Q data signal magnitude value of a sampled Q data signal. The calculating circuitry is configured to calculate a phase shift angle φI between first and second equal and constant or substantially equal and constant envelope constituents of the sampled I data signal and to calculate a phase shift angle φQ between first and second substantially equal and substantially constant envelope constituents of the sampled Q data signal. The determining circuitry is configured to determine in-phase and quadrature amplitude information of the substantially equal and substantially constant envelope constituents of the sampled I signal and to determine in-phase and quadrature amplitude information of the first and second substantially equal and substantially constant envelope constituents of the sampled Q signal. |
| US09143087B2 |
Adaptive FM demodulator supporting multiple modes
Methods, systems, and devices are described for an adaptive demodulator that supports multiple modes. An FM signal may be received at a demodulator and parameters corresponding to the FM signal may be identified. Connections between multiple modules within the demodulator may be configured, based at least in part on the parameters, to select one of multiple demodulation modes supported by the demodulator to demodulate the FM signal. The modes may include a phase differencing mode, a phase-locked loop (PLL) mode, a frequency-compressive feedback (FCF) mode, and/or a quadrature detector mode. The parameters may include one or both of a signal strength of the FM signal and a maximum frequency deviation of the FM signal. Based on the parameters, one or more signals may be generated to configure the connections within the demodulator. A switch from one mode to another may occur when one of the parameters breaches a threshold value. |
| US09143086B2 |
Power-efficient multi-frequency resonant clock meshes
Power-efficient resonant clock meshes and multiple frequency resonant clock distribution networks. |
| US09143083B2 |
Crystal oscillator emulator with externally selectable operating configurations
A crystal oscillator emulator having a plurality of predetermined operating configurations. The crystal oscillator emulator includes a measurement circuit configured to measure a value of an impedance connected to a select pin of the crystal oscillator emulator, wherein the impedance is external to the crystal oscillator emulator, and generate an output having a value corresponding to the value of the impedance. The storage circuit is configured to store a plurality of values corresponding to the plurality of predetermined operating configurations and select one of the plurality of values based on the output of the measurement circuit. A controller is configured to set an output frequency of the crystal oscillator emulator based on the selected one of the plurality of values. |
| US09143082B2 |
Solar power generation system, control device used for solar power generation system, and control method and program for same
In a light power generation system, a control device, a control method, and a program, efficient power can be supplied. The maximum power detection unit operates a MOSFET in a power converter circuit and open-circuits both ends of a solar cell panel in the maximum power detection mode. After that, the maximum power detection unit short-circuits both ends of the solar cell panel, detects a maximum power by monitoring the output power of the solar cell panel during a period from the open state to the short-circuited state, and defines the voltage of the solar cell panel as an optimal voltage when detecting the maximum power. In a tracking operation mode, the control unit performs PWM control with respect to the MOSFET by defining the optimal voltage to be a reference signal. Operations are repeated between the maximum power detection mode and the tracking operation mode. |
| US09143079B2 |
Power converter
A power converter includes an output circuit and a control circuit. The output circuit has an upper switching device connected to a direct-current power source and a lower switching device connected in series with the upper switching device. The output circuit supplies power to a load from a connection point between the switching devices. The control circuit supplies pulse-modulated control signals to the switching devices to turn ON and OFF the switching devices. The control circuit variably sets a switching speed and a dead-time of the switching devices in such a manner that as the switching speed becomes slower, the dead-time becomes longer. |
| US09143078B2 |
Power inverter including SiC JFETs
A power inverter includes a reference line operably provided with a reference potential and a supply line operably provided with a DC supply voltage with respect to the reference potential. A first half bridge includes a high-side switch and a low-side switch. The high-side switch is coupled between the supply line and a middle tap of the half bridge and the low-side switch is coupled between the middle tap and the reference line. The low-side switch is formed by a normally-on silicon carbide junction field effect transistor and the high-side switch is formed by a series circuit of a normally-on silicon carbide junction field effect transistor and a normally-off metal oxide field effect transistor. |
| US09143074B2 |
Controlling method of synchronous motor
A method is for controlling a synchronous motor includes a stator, a rotor with a position and a speed, a direct axis and a quadrant axis. The method includes: providing a position control, a speed control and a current control programs; executing either the position control program or the speed control program to produce a quadrant axis current; executing the current control program; detecting the synchronous motor to obtain a first, a second and a third phase currents, and digitizing the three phase currents; using the three phase currents and the quadrant axis current to calculate a direct axis current; converting the direct axis current and quadrant axis current to a direct axis voltage command and quadrant axis voltage command; executing a pulse width modulation for the direct axis and the quadrant axis voltage commands, to get a trigger signal for controlling the synchronous motor. |
| US09143072B2 |
Tap changer with an improved drive system
An on-load tap changer is provided having a plurality of modules, each of which is operable to change taps in a winding of a transformer. A transmission shaft is connected to the modules and is operable upon rotation to effectuate tap changes in the windings. A servo motor rotates the transmission shaft. The servo motor includes a feedback device operable to generate a feedback signal containing information relating to the position of the motor shaft. A servo drive is connected to the servo motor to receive the feedback signal. The servo drive uses the feedback signal to determine and store a total angular displacement of the motor shaft. The servo drive uses the feedback signal and the total angular displacement of the motor shaft to control the operation of the servo motor. |
| US09143071B2 |
Method for controlling a wind turbine
The present invention concerns a method of controlling a wind power installation having a generator with a stator, a pole wheel with at least two rotor poles with a respective pole winding for producing a magnetic field guided in the respective rotor pole, and an air gap between the stator and the pole wheel, including the steps—controlling a respective exciter current through each pole winding,—varying at least one of the exciter currents relative to at least one further one of the exciter currents, and/or—varying at least one of the exciter currents in dependence on the position of the pole wheel in relation to the stator. |
| US09143062B1 |
Direct current regeneration system
The system includes an electric alternating/direct current motor, a stepping motor, and a converter/inverter. The stepping motor is operatively coupled to the electric alternating/direct current motor. The electric alternating/direct current motor is located between the converter/inverter and the stepping motor. The stepping motor includes a gear assembly formed of a first gear and an axially aligned second gear and an intermediate gear operatively coupled between the first and second gears. A lever selectively couples and uncouples the first and second gears. |
| US09143061B1 |
Bicycle power generation device
A bicycle power generation device includes a seat tube unit to which a power generation unit is connected. Two rails are clamped between a press plate and a top plate. The top plate has a pressing face in which a recess is defined. A bottom plate has a contact face located corresponding to the pressing face. A protrusion protrudes from the contact face and is located corresponding to the recess. The power generation unit has at least one power generation plate and an output member. The at least one power generation plate is located on the contact face of the bottom plate and electrically connected to the output member. The vibration from the seat activates at least one power generation plate to generate electric power. |
| US09143053B1 |
Microinverters for employment in connection with photovoltaic modules
Microinverters useable in association with photovoltaic modules are described. A three phase-microinverter receives direct current output generated by a microsystems-enabled photovoltaic cell and converts such direct current output into three-phase alternating current out. The three-phase microinverter is interleaved with other three-phase-microinverters, wherein such microinverters are integrated in a photovoltaic module with the microsystems-enabled photovoltaic cell. |
| US09143051B2 |
Load control device for high-efficiency loads
A two-wire load control device (such as, a dimmer switch) is operable to control the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) and has substantially no minimum load requirement. The load control device includes a bidirectional semiconductor switch (such as thyristor), which may be operable to remain conductive independent of the magnitude of a load current conducted through the thyristor and to conduct the load current to and from the load during a single half-cycle. The dimmer switch comprises a power supply that conducts a charging current through the load in order to generate a supply voltage. The dimmer switch comprises a control circuit that controls a gate coupling circuit for rendering the thyristor conductive each half-cycle. The control circuit may provide a constant gate drive to the thyristor after the thyristor is rendered conductive each half-cycle. |
| US09143049B2 |
Three-level power conversion apparatus
Wiring between semiconductor modules and a direct current power supply circuit, which construct a three-level power conversion apparatus, is made to be low inductance, so reduction in size and cost can be attained easily. In cases where a connection is made between direct current power supplies (electrolytic capacitors) and IGBT modules of a three-level inverter, a wiring conductor for a bi-directional switch part is divided into three conductors or two conductors on a same surface, and these conductors are sandwiched by a P conductor and an N conductor, which are arranged at outer sides thereof, respectively, through insulating materials, so a three-layer wiring structure of a sealed structure is formed. As a result, wiring inductance can be made small even with a small number of laminated layers, so that the reduction in size and cost of the apparatus as a whole is achieved. |
| US09143044B2 |
Apparatus and method for pulse width modulation control for switching power converters
An embodiment apparatus comprises a first two-piecewise linear approximation generator and a second two-piecewise linear approximation generator coupled to an output of the first two-piece wise linear approximation generator. The second two-piecewise linear approximation generator generates a dead time inversely proportional to the output of the first two-piece wise linear approximation generator. A gate drive generator is configured to generate a primary switch drive signal and an auxiliary switch drive signal complementary to the primary switch drive signal. In addition, the dead time between the primary switch drive signal and the auxiliary switch drive signal is adjustable when the power converter operates in a light load condition. |
| US09143042B2 |
High efficiency power converter
A power converter nearly losslessly delivers energy and recovers energy from capacitors associated with controlled rectifiers in a secondary winding circuit, each controlled rectifier having a parallel uncontrolled rectifier. First and second primary switches in series with first and second primary windings, respectively, are turned on for a fixed duty cycle, each for approximately one half of the switching cycle. Switched transition times are short relative to the on-state and off-state times of the controlled rectifiers. The control inputs to the controlled rectifiers are cross-coupled from opposite secondary transformer windings. |
| US09143041B2 |
Magnetic circuit, power-supplying device and power-receiving device for non-contact charging apparatus, and non-contact charging apparatus
A magnetic circuit for a non-contact charging apparatus comprising a coil, a coil yoke disposed on the rear surface side of the coil, and a magnetic attraction means disposed in a hole of the coil yoke with a magnetic gap in plane and/or thickness directions. |
| US09143039B2 |
Systems and methods for reducing electromagnetic interference by adjusting switching processes
System and method for regulating a power conversion system. An example system controller for regulating a power conversion system includes a signal generator and a driving component. The signal generator is configured to receive a feedback signal associated with an output signal of a power conversion system and a current sensing signal associated with a primary current flowing through a primary winding of the power conversion system and generate a modulation signal based on at least information associated with the feedback signal and the current sensing signal. The driving component is configured to receive the modulation signal and output a drive signal to a switch based on at least information associated with the modulation signal. |
| US09143036B2 |
Systems and methods for enhanced efficiency auxiliary power supply module
Provided is a power supply for use in a solar electric production system, including: a first stage having an input connected to a voltage from a photovoltaic panel and an output providing a first voltage different from the voltage from the photovoltaic panel; and a second stage connected to the output of the first stage, the second stage supplying power at a second voltage to a micro-controller, where the output of the first stage is turned on and stable for a period of time before the second stage is turned on to supply the power at the second voltage to the micro-controller. |
| US09143035B2 |
Switching power supply device with on and off width generating circuits
Aspects of the invention include a switching power supply device that includes a zero current detecting circuit that detects zero current of electric current flowing through the inductor to turn ON the switching element, an ON width generating circuit that determines the ON width of the switching element to turn OFF the switching element, and an OFF width detecting circuit that detects the OFF width of the switching element based on the output of the ON width generating circuit and the output of the zero current detecting circuit, and holds the OFF width until the next operating cycle. Aspects of the invention also include an ON width adjusting circuit that is included in the ON width generating circuit and adjusts the ON width of the switching element in the next operation cycle according to the width detected by the OFF width detecting circuit. |
| US09143032B2 |
Apparatus, systems, and methods for providing a hybrid power regulator
The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor. |
| US09143031B2 |
Power factor control of a cyclo-converter
A three-phase resonant cyclo-converter comprising a power control module, wherein the power control module is arranged to develop a plurality of repeating switching periods within a cycle, the power control module further arranged to: control the length of a first switching period in the cycle to adjust the power flow, and control the relative length of two or more further switching periods in the cycle to adjust the power factor, wherein the relative length is controlled based on a cross-product of voltage and current values associated with the further switching periods. |
| US09143028B2 |
Power supply systems and methods
One example of generating a clock signal via an oscillator system includes increasing a first comparison voltage at a first comparison node from a first magnitude to a second magnitude in response to a clock signal. A second comparison voltage is increased at a second comparison node from the first magnitude to the second magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage increasing to a magnitude that is greater than the first comparison voltage. The first comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The second comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage decreasing to a magnitude that is less than the first comparison voltage. |
| US09143026B2 |
Method and apparatus for regulating high voltage
A method for regulating output of a high voltage generator includes monitoring a voltage output of the generator and comparing it to a voltage setpoint to generate an error signal. A load on the generator is monitored to generate a load signal. The load signal is conducted to a feedforward signal generator. The feedforward signal generator is configured to produce a feedforward signal corresponding to the load and to at least one parameter related to an output impedance of the high voltage generator. The error signal is conducted to a high voltage regulation loop. The control loop output and the feedforward signal generator output are coupled to a driver for the high voltage generator. |
| US09143025B2 |
Magnetic gear mechanism including a plurality of rotors or stators
A magnetic gear mechanism including a simplified assembly of a magnetic flux modulating section in the magnetic gear mechanism which improves the strength thereof. In the magnetic flux modulating section of the magnetic gear mechanism, the magnetic flux modulating section being formed of a magnetic member and a non-magnetic member, a piece of the magnetic member and a piece of the non-magnetic member are separately produced. The piece of the magnetic member is sandwiched between circumferential projections provided in pieces of the non-magnetic member, and the magnetic member and the non-magnetic member and bearing holding sections form a structure in which the magnetic member and the non-magnetic member are fitted into the bearing holding sections by using recessed portions provided in the bearing holding sections and axial projections provided in the pieces of the non-magnetic member. This structure simplifies production and improves strength. |
| US09143023B1 |
Electromagnetic propulsive motor
The invention provides an electromagnetic propulsive motor having a rotor capable of rotation around a shaft and having a plurality of radially disposed blades including blade tip portions for compressing a working fluid. The invention further provides a stator having a case frame, and a plurality of radially disposed vanes extending generally between said case frame and said shaft for directing the working fluid. A plurality of electromagnetic elements disposed within said rotor blades proximate the tip portions thereof interact electromagnetically with a plurality of electromagnetic elements disposed in said stator case frame to drive said rotor. |
| US09143022B2 |
System and method for rebalancing generator rotor in-situ
A Wye ring system for a rotor of a generator includes a replacement Wye ring configured to replace an existing Wye ring serving as a floating neutral connection in the rotor. The replacement Wye ring is positioned radially inside the existing Wye ring and co-axial with the rotor. A fastening system is configured for mechanically and electrically connecting the replacement Wye ring to a plurality of connection lugs. The plurality of connection lugs are electrically connected to the rotor windings. The replacement Wye ring replaces the floating neutral connection of the existing Wye ring. |
| US09143017B2 |
Motor structure
A motor structure includes a housing having a shaft tube receiving a shaft retaining assembly. The shaft tube includes a positioning member on an outer periphery thereof. A rotor includes a shaft rotatably extending through the bearing. A stator is mounted around the shaft tube, couples with the positioning member, and includes a bobbin having an abutting portion pressing a top face of the shaft retaining assembly by a free end thereof. Specifically, the positioning member is distant from the top face by a first distance in an axial direction of the shaft tube, the abutting portion is made of elastic material, the positioning member is distant from the free end by a second distance in an axial direction of the assembling hole is defined, and the second distance is smaller than the first distance when the stator is separate from the shaft tube. |
| US09143015B2 |
Brush holder for a brush assembly for a power tool motor
A power tool is provided including a tool housing in which an electric motor is disposed. The electric motor includes a stator and an armature rotatably received within the stator. The armature has an armature shaft on which a commutator is mounted. The power tool further includes at least one brush assembly disposed around the commutator, the brush assembly including: a brush having two grooves on opposites surfaces therein; a brush holder comprising two support plates arranged defining guiderails that extend into the grooves of the brush to facilitate movement of the brush along a single axis; and a spring contacting the brush that urges the brush radially inwardly along the axis. |
| US09143014B2 |
Rotor, dynamo-electric machine having the rotor and rotor manufacturing method
A cover is configured into a tubular form and is fitted to a radially outer surface of each of projections of a rotor core and a radially outer surface of each of permanent magnets. A circumferential center portion of the radially outer surface of each projection contacts a radially inner surface of the cover. Circumferential end portions of the radially outer surface of each projection are radially inwardly spaced from the radially inner surface of the cover. |
| US09143008B2 |
Power demand and supply scheduling apparatus
A power demand and supply scheduling apparatus a includes a transceiver that mutually exchanges power supply reservation information including at least information of a total suppliable power amount, a suppliable state start time, a suppliable state end time, and a maximum suppliable amount per unit time zone, and power request reservation information including at least information of a total request power amount, a receivable state start time, a receivable state end time, and a maximum receivable amount per unit time zone, with scheduling apparatuses for other energy management systems each of which manage other power equipment, and a plan creating unit that plans a power reception amount and a power supply amount in each of the unit time zone which are delivered to and received from the other power equipment, and creates a power delivery and reception plan. |
| US09143004B2 |
Method and circuit arrangement for charging an intermediate circuit capacitor
A method for charging an intermediate circuit capacitor in a precharging unit includes charging the intermediate circuit capacitor via a current source and adjusting the supplied current in such a manner that a constant power loss is produced in the current source during the entire charging operation. A circuit arrangement includes a battery which is connected to a current source which is connected to an intermediate circuit capacitor via a switch. An adjusting circuit is arranged in parallel with the current source and can be used to adjust the current for charging the intermediate circuit capacitor. The current is adjusted in such a manner that a constant power loss is produced in the current source during the entire charging operation. |
| US09143002B2 |
Wireless electric power receiver for wirelessly regulating electric power using switch
A wireless electric power receiver for receiving wireless electric power from a wireless electric transmitter is provided. The wireless electric power receiver includes an electric power receiving unit that receives wireless electric power from the wireless electric power transmitter; a rectifying unit that rectifies wireless electric power in the form of alternating current output from the wireless electric power receiving unit and outputs rectified electric power; and an electric power regulation unit that receives an input of the rectified electric power, outputs first electric power which has a lower value of a first voltage than that of the rectified electric power for a first period, and does not output electric power for a second period, so as to output electric power with a predetermined voltage value. |
| US09142999B2 |
Systems, methods, and apparatus for small device wireless charging modes
Systems, methods, and apparatus are disclosed for wirelessly charging devices that may not be able to communicate with a wireless charger. In one aspect, a wireless charging device is provided including a transmitter configured to wirelessly transmit power via a wireless field at a power level sufficient to charge one or more electronic devices according to one or more charging modes including at least a first charging mode in which the transmitter is configured to vary the power level of the transmitter based on feedback received from one of the one or more electronic devices and a second charging mode in which the power level is constant. The wireless charging device includes a sensor configured to obtain input for switching between the charging modes. The wireless charging device further includes a controller configured to switch between the first charging mode and the second charging mode in response to the input. |
| US09142996B2 |
Portable device and wireless power charging system for portable device
A portable device is provided. The portable device includes a power receiving unit configured to receive a first energy or a second energy from a wireless power transmitter, the first energy being used to perform a communication function and a control function, the second energy being used to charge a battery, and the wireless power transmitter being configured to wirelessly transmit a power, a voltage generator configured to generate a wake-up voltage from the first energy, or to generate a voltage for charging the battery from the second energy, a controller configured to perform the communication function and the control function, the controller being activated by the wake-up voltage, and a communication unit configured to perform a communication with the wireless power transmitter based on a control of the controller. |
| US09142993B2 |
Charge circuit, and battery-charger assemblage with the charge circuit
A charge circuit is composed of a first circuit and a second circuit. Said second circuit is provided at a battery pack in which a secondary battery is comprised. Said first circuit is provided at a charger for charging said secondary battery. Said charge circuit comprises: an output power supply section; a control section configured to control said output power supply section to perform a charging operation; a memory provided at said second circuit and storing a number of charging; and a threshold current setting section. Said control section is configured to, in said charging operation, perform firstly a constant current charging operation, and then perform a constant voltage charging operation, and finish the charging operation when a charging current reaches a charge stop current value. Said threshold current setting section is configured to decrease said charge stop current value along with the increase of said number of charging. |
| US09142991B2 |
Current regulation system
A current regulation system for generating a charging current curve for charging a rechargeable battery is provided, the system including a current regulation module coupled to a power converter to output a conversion current in a constant current mode and a constant voltage mode, a voltage-to-current regulation module coupled to the rechargeable battery to output a voltage conversion current in the constant voltage mode, a temperature-to-current regulation module and a resistance. The temperature-to-current regulation module outputs a temperature conversion current in the constant current mode and the constant voltage mode. The resistance is coupled to the current regulation module, the voltage-to-current regulation module and the temperature-to-current regulation module to regulate the voltage conversion current or the temperature conversion current, the conversion current is weakened by maintain a constant value so the charging current curve is regulated when the power of the rechargeable battery is full. |
| US09142990B2 |
Method of multi-coil operation and optimization
This disclosure provides systems, methods and apparatus for wireless power transfer and particularly wireless power transfer to remote systems such as electric vehicles. In one aspect, a system comprises substantially co-planar first and second receiver coils. The system further comprises a third receiver coil. The system further comprises a controller configured to determine a current of the co-planar first and second receiver coils, a current of the third receiver coil, and a duty cycle of the wireless power transfer receiver device. The controller is configured to enable the co-planar first and second receiver coils, the third receiver coil, or the co-planar first and second receiver coils and the third receiver coil based on a comparison of the current of the co-planar first and second receiver coils, the current of the third receiver coil, and the duty cycle. |
| US09142989B2 |
Method of minimizing interruptions to implantable medical device recharging
A system and method of controlling the charging of the battery of a medical device using a remote inductive charger, with the method utilizing both a relatively fast closed-loop charging control based on a proxy for a target power transmission value in conjunction, and a slower closed-loop control based on an actual measured transmission value to control a charging power level for charging the medical device. |
| US09142981B2 |
Cell balance control unit
A cell balance control unit is provided, including: a discharge circuit connected to each of a plurality of battery cells constituting a battery in parallel; a voltage detecting circuit that detects a voltage of each of the battery cells; and a control device that controls each of the switching elements of the discharge circuit so that the voltage of each of the battery cells is made uniform based on voltage detection results of each of the battery cells, wherein the control device controls the switching elements of the discharge circuits connected to the adjacent battery cells in each different duty ratio, and detects disconnection of wirings extracted from both ends of each battery cell based on a potential difference between the adjacent battery cells. |
| US09142977B1 |
Method of controlling battery state using constant-voltage discharge
A battery is rendered to a consistent discharged state in a two-phase battery discharge operation. In a first of the two discharge phases, a constant discharge current is drawn from the battery until a threshold battery voltage is reached. In the second of the two discharge phases, executed after the threshold battery voltage is reached during the first-phase, a time-varying discharge current is drawn from the battery at a constant battery voltage until a threshold discharge current is reached. |
| US09142975B2 |
Discharge system and electric vehicle
In a discharge system that outputs DC power from a vehicle battery to the outside, improved safety is obtained during discharge of the battery. A discharge system includes an electric car having a battery unit mounted thereon, and a discharge device that discharges the battery unit. The electric car includes a connector to which the discharge device is connected, and a power line that connects the connector and the battery unit to each other. In the power line, switches and switching elements are provided. The switches render the power line conducting upon permission from the discharge device and a battery management unit. The switching elements adjust a current flowing in the power line when the battery unit is discharged. |
| US09142974B2 |
Configurable power supply system
A configurable power supply system is disclosed. The configurable power supply system comprises a power source for providing input power, a switch, coupled to the power source, for enabling a bypass path for outputting the input power to an output node as an output power when turned on; a rechargeable battery module for storing the input power for outputting a battery power; a charging unit, coupled between the power source and the rechargeable battery module, for charging the rechargeable battery module with the input power; a converting unit, coupled to the rechargeable battery module, for converting the battery power to generate the output power; and a control unit, coupled to the switch, the charging unit, and the converting unit, for controlling functions of the switch, the charging unit, and the converting unit. |
| US09142972B2 |
Power reception equipment for resonance-type non-contact power supply system
Power reception equipment (20) is provided with: a secondary side resonance coil (21b) which receives power from a primary side resonance coil (13b) of power supply equipment (10); and a rectifier (23) which rectifies the received power. The power reception equipment is further provided with: a secondary matching unit (22) which is provided between the secondary side resonance coil (21b) and the rectifier (23); a charger (24) to which rectified electric power is supplied; a power storage device (25) which is connected to the charger; and a control unit (26) which adjusts the secondary matching unit when the power storage device is being charged. The control unit stores, as data on a storage device (33), the relationship between the charge power from the power supply equipment during the power ascension phase and the matching status of the secondary matching unit (22) when charging. During the phase in which the power output from the supply equipment is reduced, the control unit adjusts, on the basis of the data stored in the storage device during the power ascension phase, the secondary matching unit (22) so as to reach a suitable status corresponding to the charge power. |
| US09142970B2 |
Power on and off testing device and method
A power on and off testing device includes a control module, a switch module, an alternating current and direct current converter module, an input module, and a detecting module. The switch module is connected to an alternating current source. The alternating current and direct current converter module is connected to a motherboard of a computer. The input module is connected to the control module to input testing references to the control module. The detecting module is connected between the control module and the motherboard. The detecting module detects a power status of the motherboard and sends the power status to the control module. The control module controls the switch module to be switched on according to the power status after receiving the testing references, thereby controlling the alternating current source to supply power to the motherboard. |
| US09142966B2 |
Method for controlling a grid-connected power supply system
A method for controlling a grid-connected power supply system having multiple power supply modules, a relay commonly connected to output terminals of the power supply modules and connected between the power supply modules and a mains power grid, and a controller controlling each power supply module and the relay. The method is performed by the controller after the grid-connected power supply system is started and has steps of determining if each power supply module outputs power, activating each power supply module and charging an energy storage capacitor of the power supply module, and activating the relay when the stored voltages of the energy storage capacitors of all the power supply modules are greater than a preset peak voltage of the mains power. Accordingly, required number of relays is reduced and the size of the system can thus be more compact. |
| US09142953B2 |
Electrostatic discharge protection apparatus and associated method
An electrostatic discharge (ESD) protection apparatus, coupled between a first rail line and a second rail line, includes a clamp circuit and a detection circuit. The detection circuit includes an electronic element having an equivalent capacitance value, and a transistor having a gate, a first input and a second input respectively coupled to a first node, the first rail line and a drive terminal of the clamp circuit. In response to an ESD event, leakage currents pass between the first input and the gate and between the second input and the gate to equivalently form parasitic resistance therein, respectively. The parasitic resistances and the electronic element form a delay circuit to provide a drive voltage between the gate and the first input, and to provide a trigger current for conducting the clamp circuit, so that the first and second rail lines perform an ESD operation via the clamp circuit. |
| US09142951B2 |
Electronic device for protecting against a polarity reversal of a DC power supply voltage, and its application to motor vehicles
Disclosed herein is a device comprising a protection circuit configured to protect against a polarity reversal of the input DC power supply voltage, the protection circuit comprising an N-channel main transistor having a source coupled to an input terminal and having a drain coupled to an output terminal, a command circuit configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and a control circuit configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions. |
| US09142950B2 |
Circuit arrangement having an overload protection for galvanic isolation units
A circuit arrangement having an overload protection for galvanic isolation units for galvanic isolation from one another is described. The galvanic isolation units each have two regions galvanically isolated from one another and one of the regions has a control signal terminal and a base terminal. The circuit arrangement have at least two such galvanic isolation units. From at least two of the galvanic isolation units the base terminals of a region are electrically conductively connected to one another and are connected to a base potential via a common fuse connected in series. |
| US09142946B2 |
Cable retention system
A cable retention system for securing one or more cables or hoses to a structure or frame includes a base plate, a first sidewall, a second sidewall, a top plate and at least one modular block. The cable retention system is customizable such that additional cables may be added or removed to the system as needed. |
| US09142943B2 |
Electrical junction box
An object of the present invention is to provide an electrical junction box allowing a hollow cavity portion and a component receiving portion to be easily distinguished from each other so that the workability upon inserting components is improved. The electrical junction box includes a cassette block. Electronic components such as relay or fuse are mounted on an upper surface of the cassette block, and a bus bar and a terminal are inserted into a lower surface of the cassette block. The lower surface of the cassette block is provided with a bus bar receiving portion into which the bus bar is inserted, a terminal receiving portion into which the terminal is inserted, and a plurality of hollow cavity portions adjacent to the bus bar receiving portion and the terminal receiving portion and into which no component is inserted. |
| US09142941B2 |
Buffering device for the operating mechanism of a switchgear, and method of lubrication thereof
A piston rod (15) and a first piston (13) are arranged in the interior of an external cylinder (11) and internal cylinder (12); a second piston for absorbing the change of volume of operating fluid (24) is also arranged therein. Also, a first return spring (18) for returning the piston rod (15) to the interruption position is provided and a second return spring (20) for returning the operating fluid 24 into the high-pressure chamber (25) by pressurizing the second piston (14) is provided. In addition, the air in the interior of the buffering device (10) is withdrawn by a vacuum pump (38), and operating fluid (24) is thus introduced in a degassed condition. |
| US09142939B2 |
Method and apparatus for mounting a power converter
The present invention provides a power converter mounting system including a flange that cooperates with a power converter and an enclosure. The flange includes a through hole that cooperates with an opening in the enclosure to permit the power converter to extend therethrough. A number of fasteners connect to the flange and overhang a portion of the power converter. The fasteners are configured to be manipulated from a front side of the power converter. An outer perimeter of the flange extends beyond the opening in the enclosure. The flange is secured to the enclosure with a number of fasteners that are also operable from the front side of the power converter. The power converter mounting assembly is configured to secure a power converter to an enclosure so as to satisfy a variety of sealing requirements as well as allowing convenient servicing of the power converter system. |
| US09142937B2 |
Wavelength referencing by monitoring a voltage across a laser diode
A lasing wavelength of a laser diode is determined by applying a forward current to the p-n junction of the laser diode and measuring a voltage across the p-n junction. The lasing wavelength can be determined by performing a simple wavelength calibration of the laser diode. This allows one to stabilize the lasing wavelength, and also to use the laser diode as a reference wavelength source. |
| US09142936B2 |
Laser light source device and method for manufacturing laser light source device
The present invention is a laser light source device having: a silicon substrate having a first flat surface and a second flat surface which is formed at a position lower than the first flat surface by a level difference in the thickness direction; a first junction having a microbump structure comprising Au formed on the first flat surface; a second junction having a microbump structure comprising Au formed on the second flat surface; a first optical element and a second optical element for emitting laser light, which are joined to the first junction by a surface activation technique; a reflective member for reflecting the laser light from the first optical element toward a multiplexer, the reflective member being joined to the second junction by the abovementioned technique; and a multiplexer for directly receiving the laser light from the second optical element and multiplexing the laser light from the first optical element and the laser light from the second optical element, the multiplexer being joined to the second junction by the abovementioned technique; a configuration being adopted whereby the distance between the first optical element and the reflective member is different from the distance between the second optical element and the multiplexer, and the length of the optical path from the first optical element to the multiplexer is equal to the length of the optical path from the second optical element to the multiplexer. |
| US09142928B2 |
Bulb socket
A bulb socket for receiving a bulb therein. The bulb socket includes a first portion and a second portion. The first portion has a bulb receiving opening. The second portion extends from the first portion. The second portion has first outside surfaces which are tapered inward, such that the perimeter of the second portion proximate the first portion is less than the perimeter of the second portion spaced from the first portion. The second portion does not obstruct the performance of the bulb, allowing approximately all of the light capacity of the bulb to be utilized. |
| US09142926B2 |
Electrical connector for bidirectional plug insertion
An electrical connector, into which a male plug, having an insulation base, a metal housing covering the base and a connection space therebetween, may be inserted in a bidirectional manner. The connector includes a plastic base, a tongue, a connection slot and two rows of connection points. The tongue is projectingly disposed at a front end of the plastic base. The slot disposed at the front end of the plastic base covers the tongue. When the plug is inserted and positioned within the slot, the tongue is inserted into the connection space. The connection points are exposed from two surfaces of the tongue. Each connection point is electrically connected to a pin extending out of the plastic base. Spaces of the slot beside the two surfaces of the tongue allow the plug to be bidirectionally inserted and positioned. When the plug is positioned within the slot, the metal housing does not touch the connection point to avoid a short circuit as the plug is inserted. |
| US09142917B2 |
Connector assembly with a receptacle connector and a plug connector with stable structures
A connector assembly includes a receptacle connector and a plug connector. The receptacle connector includes a receptacle insulative housing and a plurality of female contact groups each of which includes first and second female contacts combined together. Each of the first and second female contacts includes a retaining portion including a first locking portion and a second locking portion. Each first locking portion includes a slit. Each second locking portion includes a positioning portion and an engaging arm. The retaining portions of the first female contact and the second female contact are of the same configuration after rotating 180 degrees. When the first female contact is combined in position with the second female contact, the positioning portion and the slit of the first female contact engage with the slit and the positioning portion of the second female contact, simultaneously. |
| US09142914B2 |
Push lock electrical connector
An inline multi-pin connector includes cylindrical male and female connector members which are electrically connected together by pushing the two members together end-to-end. Either the male or the female connector member has a metal cylinder disposed about its conductive pins or sockets, which are adapted for mutual engagement, while the other connector member is provided with inner threads. The metal cylinder includes plural resilient, spaced arms, or tabs, disposed about its outer periphery and urged radially outward and into engagement with the other member's threads to connect the two connector members. Coaxial seals are disposed between and in contact with the two members as is a compressible O-ring seal. The outer periphery of the inner member's cylindrical insulator is provided with alternating peaks and valleys, while the other member's metal cylinder is provided with inwardly extending resilient arms which are adapted for positioning within a respective facing valley to prevent vibration-induced disconnection. |
| US09142913B2 |
Magnetically connected universal computer power adapter
A magnetically connected universal computer power adapter is presented. The computer power adapter provides a power supply, a power cord, a cord connector, and a charging plug. The cord connector and charging plug each contain a magnet that magnetically couple the cord connector to the charging plug. The cord connector may couple with more than one type of charging plug, allowing the universal computer power adapter to be used with many different computer models. |
| US09142910B2 |
Electrical connector with improved spacer for heat dissipation
An electrical connector includes a housing, a number of contacts received in the housing and a spacer for holding the contacts. The housing includes a mating portion and a pair of extensions extending from the mating portion. The pair of extensions and the mating portion jointly form a receiving space to receive the spacer. The spacer includes a horizontal portion and a vertical portion perpendicular to the horizontal portion. The horizontal portion defines a slot through which the contacts extend. The vertical portion includes an inner wall, an outer wall and a channel extending through the inner wall and the outer wall. The outer wall defines a recess opening in communication with the channel. When the contacts are associated with the spacer, the contacts are partly exposed to the recess opening via the channel for robust heat dissipation. |
| US09142906B2 |
Power plug capable of simple assembly
A power plug for connecting with a power outlet includes at least two metal connecting poles, two outputting cavities, and two conductive resilient sheets. The two outputting cavities are defined in a lower case of the power plug to connect an external device. The two conductive resilient sheets are received within an inner space of the power plug. The at least two metal connecting poles pass through an exterior surface of the power plug into the internal space to form two connecting terminals. Each of the conductive resilient sheets is connected between one of the two connecting terminals and a corresponding outputting cavity to transport electrical power from the power jack to the external device. |
| US09142904B2 |
Electrical connector with terminal position assurance
An electrical connector is provided that includes a housing that has a mating end and a carrier receiving end. The housing includes a rail that extends through the carrier receiving end into a chamber defined by the housing. The electrical connector also includes a carrier configured to be loaded into the chamber from the carrier receiving end. The carrier has terminal channels that are configured to receive terminals therein, and retention latches configured to retain the terminals in the terminal channels. The carrier also has a groove that is configured to receive the rail of the housing when the carrier is loaded within the housing. When a terminal is not fully inserted within a terminal channel, the retention latch in the terminal channel is deflected outward into the groove. The retention latch interferes with the rail of the housing and prevents further advancement of the carrier into the chamber. |
| US09142903B2 |
High performance multiport connector system using LIGA springs
A multiport zero insertion force (ZIF) connector can include a multiport connector housing defining an opening and an interior space for receiving a multi-path circuit device having multiple types of electrical connection paths therethrough and multiple LIGA springs positioned within the interior space to apply pressure to the multi-path circuit device while in a first position. A locking component can be configured to cause the LIGA springs to move to a second position responsive to a user pressing the locking component, wherein the LIGA springs do not apply pressure to the multi-path circuit device while in the second position. |
| US09142901B2 |
Female terminal
An elastic contact member (21) formed as a member separate from an electrical connector (11) for a male terminal to be inserted, installed in the electrical connector (11), and gets into contact with the male terminal inserted in the electrical connector (11). The elastic contact member (21) includes: first elastic contact pieces (22) formed with a space (S) in between in a widthwise direction (Y), cantilevered at one end side, in the insertion direction (X), of a surface of the elastic contact member (21) extending in the insertion direction (X), and configured to get into contact with the male terminal inserted into the electrical connector (11); and a second elastic contact piece (23) disposed in the space (S) and configured to get into contact with the male terminal inserted into the electrical connector (11). |
| US09142895B2 |
Coaxial connector assembly
A coaxial connector assembly includes an outer housing holding an outer contact, a dielectric holder received in the outer contact, and a center contact received in the dielectric holder. The dielectric holder has a front and a cavity extending axially along the dielectric holder bounded by a cavity wall. The dielectric holder has an expansion slot formed in the cavity wall offset from, and proximate to, the front. The center contact has a socket at a mating end configured to receive a pin contact of a mating connector assembly. The center contact has deflectable beams at the mating end configured to deflect outward when mated with the pin contact. The center contact has flared tip ends at the distal ends of the beams. The flared tip ends are received in the expansion slot when the deflectable beams are deflected outward during mating with the pin contact. |
| US09142894B2 |
Permanent electrical contact applicable to the web of rails and the like
A permanent electrical contact applicable to the web of rails. The contact comprises a bush in electrically conductive material having a tubular stem suitable for inserting in a hole in the web of a rail, a flanged head radially widened compared to the stem and suitable for engaging in abutment with a portion surrounding the hole, and an axial through hole in which a punch can be inserted to expand the tubular stem radially and join a radially outer surface of the stem closely with the hole. At least a portion of the outer surface of the stem is substantially made of a first conductive metal and at least a portion of the flanged head is substantially made of a second conductive metal different from the first conductive metal. |
| US09142893B2 |
Polarizer rotating device for multi polarized satellite signal and satellite signal receiving apparatus having the same
There are provided a polarizer rotating device and a satellite signal receiving apparatus having the same. The satellite signal receiving apparatus includes a feedhorn that receives a satellite signal; a low noise block down converter that processes the signal received by the feedhorn; a skew compensating device that is provided at the low noise block down converter or the feedhorn and rotates the low noise block down converter or the feedhorn to compensate for a skew angle when the satellite signal received by the feedhorn is a linearly polarized wave; a polarizer that receives a linearly polarized signal and a circularly polarized signal of the satellite signal; and a polarizer rotating device that rotates the polarizer when the satellite signal received by the polarizer is a circularly polarized wave. In such a simple structure, the linearly polarized wave and the circularly polarized wave are all received to be processed. |
| US09142890B2 |
Antenna assembly
An antenna assembly includes a carrier, a metal sheet, and an antenna. The metal sheet is attached to the carrier and defining at least one notch. The antenna is connected to the metal sheet and includes a radio body for receiving and transmitting wireless signals. The radio body is positioned above the metal sheet. The length of current path in a peripheral wall of the at least one notch is in a predetermined proportion to the wavelength of the wireless signals, enabling the metal sheet to resonate with the radio body to increase the bandwidth of the antenna. |
| US09142877B2 |
Control of a transmitter output power
Disclosed are various embodiments for controlling an output power of a transmitter. Adjustment amounts for a transmitter to transmit at a desired power level are determined. For a predetermined time period, an actual power level of the transmitter is adjusted at a first adjustment rate. Upon an expiration of the predetermined time period, the actual power level is adjusted at a second adjustment rate, wherein the second adjustment rate is slower than the first adjustment rate. |
| US09142876B2 |
Planar antenna and handheld device
A planar antenna and a handheld device are provided. The handheld device includes the planar antenna and a system ground plane. The planar antenna has a first feed point, a first ground point, a second feed point, and a second ground point. The first ground point and the second ground point are located between the first feed point and the second feed point. The system ground plane is electrically connected to the first feed point, the first ground point, the second feed point, and the second ground point. Thereby, the performance in radio signal transceiving is improved. |
| US09142873B1 |
Wireless communication antennae for concurrent communication in an access point
One or more access points in a wireless communication system, wherein at least one of those access points includes a set of more than one antennae capable of concurrent communication, and at least one of those more than one antennae is isolated from a remainder of that set of antennae during concurrent communication. Isolation includes one or more of disposed a first antenna in a null region of a second antenna, disposing a first antenna to communicate polarized and substantially orthogonal to a second antenna, disposing a set of antennae to communicate at two or more carrier frequencies, wherein each first antenna adjacent to a second antenna operate at distinct such carrier frequencies, or disposing a set of antennae to communicate using two or more substantially distinct protocols, wherein substantially each first antenna adjacent to a second antenna operate at substantially distinct such protocols. |
| US09142872B1 |
Realization of three-dimensional components for signal interconnections of electromagnetic waves
Example three-dimensional signal interconnections for electromagnetic waves and methods for fabricating the interconnections are described. An example apparatus may include a first conducting layer including a plurality of through-holes, and a first layer between the first conducting layer and a second conducting layer. The first layer may include a plurality of through-holes, and the second conducting layer may also include a plurality of through-holes. The plurality of through-holes of the first layer may at least partially be aligned with the plurality of through-holes of the first conducting layer and the plurality through-holes of the second conducting layer. The apparatus may further include a second layer between the second conducting layer and a third conducting layer. The second layer may have a first waveguide channel and a second waveguide channel substantially perpendicular to and intersecting with the first waveguide channel. |
| US09142868B2 |
Charge/discharge control circuit and battery device
Provided are a charge/discharge control circuit having a self-test function, which can dispense with a complicated test device, and a battery device. The battery device includes the charge/discharge control circuits each including a pull-up/pull-down circuit provided at a terminal to which a secondary battery is to be connected. When a self-test start signal is input so as to enter a self-test state, a self-test control circuit controls the pull-up/pull-down circuit, to thereby perform a test on a voltage detection circuit provided at the terminal to which the secondary battery is to be connected. When the self-test is finished, a self-test start signal is output to a next-stage charge/discharge control circuit, to thereby perform a test sequentially on the voltage detection circuits of the cascade-connected charge/discharge control circuits. |
| US09142865B2 |
Cable-type secondary battery
The present disclosure provides a cable-type secondary battery, comprising: an inner electrode supporter; and a sheet-form laminate of inner electrode-separation layer-outer electrode, spirally wound on the outer surface of the inner electrode supporter, wherein the laminate of inner electrode-separation layer-outer electrode is formed by carrying out compression for the integration of an inner electrode, a separation layer for preventing a short circuit, and an outer electrode. In the cable-type secondary battery of the present disclosure, since the electrodes and the separation layer are adhered to each other and integrated, the separation layer coming into contact with the electrodes absorbs an electrolyte solution to induce the uniform supply of the electrolyte solution into the outer electrode active material layer, thereby enhancing the stability and performances of the cable-type secondary battery. |
| US09142860B2 |
Mixed metal oxide and sodium secondary battery
A sodium secondary battery capable of reducing the amount used of a scarce metal element such as lithium and cobalt and moreover, ensuring a larger discharge capacity after repeating charge/discharge as compared with conventional techniques, and a mixed metal oxide usable as the positive electrode active material therefor. The mixed metal oxide comprises Na, Mn and M1 wherein M1 is Fe or Ni, with a Na:Mn:M1 molar ratio being a:(1−b):b wherein a is a value falling within the range of more than 0.5 and less than 1, and b is a value falling within the range of from 0.001 to 0.5. Another mixed metal oxide is a mixed metal oxide represented by the following formula (1): NaaMn1−bM1bO2 (1) wherein M1, a and b each have the same meaning as above. The positive electrode active material for sodium secondary batteries comprises the mixed metal oxide above. |
| US09142858B2 |
Non-aqueous electrolyte secondary battery, negative electrode, negative electrode material, and preparation of Si—O—Al composite
A Si—O—Al composite comprising silicon, silicon oxide, and aluminum oxide exhibits a powder XRD spectrum in which the intensity of a signal of silicon at 28.3° is 1-9 times the intensity of a signal near 21°. A negative electrode material comprising the Si—O—Al composite is used to construct a non-aqueous electrolyte secondary battery which is improved in 1st cycle charge/discharge efficiency and cycle performance while maintaining the high battery capacity and low volume expansion upon charging of silicon oxide. |
| US09142856B2 |
Liquid hydrophobic phase transition substance, and battery comprising same
A liquid hydrophobic phase transition substance is provided that may improve the safety of a battery and restrain the deterioration in performance of the battery without deteriorating the properties of the battery. The liquid hydrophobic phase transition substance includes a hydrophobic salt having a melting point of 80° C. or more and a hydrophilic salt of an alkali or an alkaline earth. |
| US09142852B2 |
Bicarbonate and carbonate as hydroxide carriers in a biological fuel cell
The present invention relates generally to a process that helps alleviate the pH gradient between anode and cathode compartments in any biological fuel cell or electrolytic cell configuration in which a pH gradient between anode and cathode is limiting the voltage efficiency. By providing acid to the cathode compartment in the form of CO2, the pH gradient is reduced and voltage efficiency and power output are increased. In one embodiment, carbon dioxide produced in the anode chamber is recycled to the cathode chamber. |
| US09142851B2 |
Composite membranes having a hydrophilic material and a conductive material susceptible to dehydration and their use in electrochemical cells
A composite membrane suitable for use in an electrochemical cell, comprises layers of a hydrophilic material and of a second material having relatively high conductivity and which is also relatively susceptible to dehydration. |
| US09142847B2 |
Fuel cell load controller
A method for distributing power includes identifying a value of a variable in a fuel cell system, where the fuel cell system is configured to provide electrical power to a load. Based at least in part on the identified value of the variable, it is determined that the variable has exceeded a threshold. A first portion of the electrical power is determined for use in correcting the variable, and the first portion of the electrical power is used to correct the variable. |
| US09142844B2 |
Power system for a telecommunications network
A reliable, end-to-end power supply solution for components of a telecommunications network provides either a primary source or a backup source of electrical power at various telecommunications sites for reliable operation of telecommunications equipment. One subsystem of the power supply solution includes one or more proton exchange membrane type fuel cells and an energy storage device for storing DC electrical power produced by the fuel cells. Another subsystem includes one or more microturbine generators, one or more rectifiers for converting AC electrical power produced by the microturbine generators to DC electrical power, and one or more proton exchange membrane type fuel cells for producing DC electrical power. The power supply solution ensures that voice and data traffic is reliably handled by a telecommunications network in situations where commercial electric utilities fail to supply power at certain points along the network. |
| US09142839B2 |
Electrochemical battery integrated in a piece of clothing and using a physiological fluid as an electrolyte
The invention relates to an electrochemical battery that comprises at least two electrodes (21, 22) each made of a different conducting material, characterized in that said electrodes are woven or sewn in the fabric of the piece of clothing (1), said fabric containing between 60 and 90% of an animal or vegetal natural fiber and between 10 and 40% of a textile fiber of a chemical elastic material, and using a physiological fluid as an electrolyte. The invention also relates to a piece of clothing equipped with such a battery. |
| US09142834B2 |
Magnesium ion batteries and magnesium electrodes employing magnesium nanoparticles synthesized via a novel reagent
Electrodes employing as active material magnesium nanoparticles synthesized by a novel route are provided. The nanoparticle synthesis is facile and reproducible, and provides magnesium nanoparticles of very small dimension and high purity for a wide range of metals. The electrodes utilizing these nanoparticles thus may have superior capability. Magnesium ion electrochemical cells employing said electrodes are also provided. |
| US09142832B2 |
Graphite material for negative electrodes of lithium ion secondary battery, manufacturing method for said material, and lithium ion secondary battery using same
A graphite material for a negative electrode is provided which can suppress capacity degradation due to repeated charging and discharging cycles, storage in a charged state, and floating charging.A method of manufacturing a graphite material for a negative electrode of a lithium ion secondary battery is provided in which an atomic ratio H/C of hydrogen atoms H and carbon atoms C in the raw coke composition is in a range of 0.30 to 0.50 and a microstrength of the raw coke composition is in a range of 7 wt % to 17 wt %. |
| US09142831B2 |
Nonaqueous electrolyte secondary battery
According to one embodiment, there is provided a nonaqueous electrolyte secondary battery. A positive electrode current collector comprises a coated portion on which the positive electrode active material layer is provided and a noncoated portion which is adjacent to the coated portion in a direction parallel to the first surface, in which the positive electrode active material layer is not present. A density of the positive electrode active material layer is within a range of 3.1 g/cc to 3.4 g/cc. A ratio W1/W2 of a mass of the coated portion per unit area (W1) to a mass of the noncoated portion per unit area (W2) is from 0.997 to 1. |
| US09142826B1 |
Battery pack
A battery pack is disclosed. In one aspect, a battery pack includes a plurality of battery units arranged in a first direction, each battery unit including first and second side surfaces opposing each other and a third side surface crossing the first and second side surfaces. The battery pack also includes a lower cover placed on the third side surfaces, wherein the lower cover includes a bottom plate facing the third side surfaces, a plurality of first ribs extending from the bottom plate toward the first side surfaces, and a plurality of second ribs extending from the bottom plate toward the second side surfaces and separate from each other, wherein the first rib extends in the first direction so as to at least partially cover the first side surfaces. |
| US09142823B2 |
Rechargeable battery and module of the same
A rechargeable battery includes an electrode assembly that performs charging and discharging, a case in which the electrode assembly is located, a cap plate coupled to an opening of the case, and electrode terminals located in the cap plate and insulated from the cap plate by insulation members located at terminal holes of the cap plate, the electrode terminals being connected to electrodes of the electrode assembly and extending outside the cap plate and the electrode terminals including a fastening portion that receives at least a part of a bus bar to be welded. |
| US09142820B2 |
Lithium secondary battery cell structure
A lithium secondary battery that has a battery cell structure, with improved electrochemical stability between an electrode and an electrolyte. In addition, the lithium secondary battery improves ion conductivity while applying a solid electrolyte. More specifically, a lithium secondary battery comprising a separator formed by an electrolyte between the cathode and the anode, wherein a composite coated layer of lithium-lanthanum-titanate (LixLayTiO3) and lithium-lanthanum-zirconium-oxide (Li7La3Zr2O12) is formed on the interface of the anode and the electrolyte. |
| US09142815B2 |
Method for manufacturing a porous nanoweb
Disclosed is a porous nanoweb including first and second nanofilaments, which facilitates to perform heat resistance simultaneously with a shutdown function for preventing a battery explosion caused by an abnormal heat generation, and to realize small thickness and easy control of porosity, wherein, if the porous nanoweb is used as a battery separator for a secondary battery, it allow the good battery efficiency and good safety owing to the low resistance, the porous nanoweb comprising the first nanofilament having a melting temperature not more than 200° C.; and the second nanofilament having a melting temperature not less than 210° C. |
| US09142814B2 |
Rechargeable battery
A rechargeable battery including an electrode assembly, the electrode assembly including an anode, a cathode, and a separator therebetween; a case accommodating the electrode assembly, the case having an opening; a cap plate coupled to the opening of the case, the cap plate having a discharge hole; and a vent plate coupled to the discharge hole, wherein the vent plate includes a main notch part corresponding to the discharge hole, and a sub-notch part separated from the main notch part. |
| US09142813B2 |
Secondary battery
A secondary battery includes an electrode assembly having a first electrode plate, a second electrode plate and a separator interposed between the first and second electrode plates; a lower case accommodating the electrode assembly therein; and a cap assembly sealing the lower case. In the secondary battery, the lower case has the electrode assembly and a vent portion, and includes a surface facing the cap assembly. The vent portion includes an intersecting portion formed inside the surface, first and second curved portions curved to extend from the intersecting portion, and an extending portion extended in a straight line from the intersecting portion. The thickness of the intersecting portion includes the minimum thickness of the surface. |
| US09142810B2 |
Rechargeable battery
In a rechargeable battery, a case is combined with an upper surface of a bare cell by being fixed to a lead plate electrically coupling a protection circuit board of a protection circuit module to the bare cell. Alternatively, the case is combined with the bare cell by being fixed to the protection circuit board so as not to be separated from the bare cell, thereby improving the reliability of the products. |
| US09142799B2 |
Light emitting structure having sub-pixel regions, organic light emitting layers, and a blocking member for emitting different color lights, display device including a light emitting structure and method of manufacturing a display device including a light emitting structure
A light emitting structure includes a first hole injection layer, a first organic light emitting layer, a charge generation layer, a second hole injection layer, a second organic light emitting layer, an electron transfer layer, and a blocking member. The light emitting structure has first, second, and third sub-pixel regions. The first organic light emitting layer may be on the first hole injection layer. The charge generation layer may be on the first organic light emitting layer. The second hole injection layer may be on the charge generation layer. The second organic light emitting layer may be on the second hole injection layer. The electron transfer layer may be on the second organic light emitting layer. The blocking member may be at at least one of the first to the third sub-pixel regions. |
| US09142797B2 |
Gas barrier substrate and organic electro-luminescent device
A gas barrier substrate including a first gas barrier layer, a substrate, and a second gas barrier layer is provided. The first gas barrier layer has a central bonding surface bonded with the substrate and a peripheral boding surface surrounding the central bonding surface. The second gas barrier layer entirely covers the substrate and the first gas barrier layer. The second gas barrier layer is bonded with the substrate and the peripheral boding surface of the first gas barrier layer, wherein a minimum distance from an edge of the substrate to an edge of the first gas barrier layer is greater than a thickness of the first gas barrier layer. |
| US09142796B2 |
Organic light emitting diode display device
Disclosed is an organic light emitting diode display device in which at least one lateral surface of an encapsulation substrate is inclined to prevent disconnection of a film connected to a pad, thereby achieving a narrow bezel and enhanced reliability. The display device includes a substrate, an organic light emitting diode array including a thin film transistor arranged on the substrate and an organic light emitting diode connected to the thin film transistor, a pad disposed on the substrate and configured to receive a drive signal to drive the organic light emitting diode array, an encapsulation substrate bonded to the substrate to face each other so as to cover the organic light emitting diode array, and a film connected to the pad and provided with a drive chip thereon. At least one lateral surface of the encapsulation substrate is inclined. |
| US09142790B2 |
PhotoSensor and photodiode therefor
According to example embodiments, a photodiode includes a photoelectric layer on a first electrode, a second electrode on the photoelectric layer, and a first phosphorescence layer on the second electrode. |
| US09142789B2 |
Photodiode device containing a capacitor for controlling dark current or leakage current
An organic photodiode, including a first electrode forming an anode, an active layer, a second electrode, and at least one third electrode, forming a capacitance with another electrode, to trap at least part of dark current or leakage current. |
| US09142779B2 |
Patterning of OLED materials
A method of making a patterned OLED layer or layers. The method uses a shadow mask having, for example, a free-standing silicon nitride membrane to pattern color emitter material with a feature size of less than 10 microns. The methods can be used, for example, in the manufacture of OLED microdisplays. |
| US09142775B2 |
Method of manufacturing semiconductor memory device
A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer. |
| US09142769B2 |
Magnetic field-partitioned non-volatile memory
A non-volatile memory cell and a magnetic field-partitioned non-volatile memory for multi-bit storage are provided. The non-volatile memory cell for multi-bit storage includes a bottom electrode. A resistance-changing memory material covers the bottom electrode. A top electrode including a high-mobility material is disposed on the resistance-changing memory material. The top electrode has two post portions supporting a bar-shaped portion. At least two bits are stored in portions of the resistance-changing memory material connecting to the top electrode when an external magnetic field is applied along different directions. |
| US09142768B2 |
Resistive memory with small electrode and method for fabricating the same
Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process. |
| US09142767B2 |
Resistive memory cell including integrated select device and storage element
Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode. |
| US09142765B2 |
Manufacturing method of non-volatile memory element, non-volatile memory element, and non-volatile memory device
A method of manufacturing a non-volatile memory element includes forming a first electrode; forming a variable resistance layer; and forming a second electrode. Forming the variable resistance layer includes forming a third metal oxide layer having a third metal oxide, forming a second metal oxide layer having a second metal oxide, and forming a first metal oxide layer e having a first metal oxide; wherein the variable resistance layer reversibly changes its resistance value in response to an electric signal applied between the first electrode and the second electrode; the first metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the second metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the third metal oxide is an oxygen-deficient metal oxide; and the first metal oxide layer is different in density from the second metal oxide layer. |
| US09142762B1 |
Magnetic tunnel junction and method for fabricating a magnetic tunnel junction
An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode. |
| US09142761B2 |
Method for fabricating a magnetic tunnel junction device
A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer. |
| US09142760B2 |
Electrical device having magnetically doped topological insulator quantum well film
A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3. 0.05 |
| US09142756B2 |
Tunneling magnetoresistive element having a high MR ratio
A magnetoresistive element includes a first ferromagnetic layer formed on a base substrate, a tunnel barrier layer formed on the first ferromagnetic layer, and a second ferromagnetic layer containing B formed on the tunnel barrier layer. The second ferromagnetic layer includes at least one of H, F, Cl, Br, I, C, O, and N, and a concentration of molecules of the at least one of H, F, Cl, Br, I, C, O, and N included in the second ferromagnetic layer is higher in a central portion in a depth direction of the second ferromagnetic layer than in an upper surface and a lower surface thereof. |
| US09142753B2 |
Piezoelectric actuator and liquid jetting apparatus
There is provided a piezoelectric actuator, including: first and second piezoelectric layers; a driving electrode arranged between the first and second piezoelectric layers; a second electrode maintained at a predetermined first electrical potential; and a third electrode maintained at a second electrical potential. A neutral plane of the piezoelectric actuator is positioned at a side opposite to the second piezoelectric layer relative to a center plane of the first piezoelectric layer in a direction of stacking of the first and second piezoelectric layers. A first portion of the first piezoelectric layer is sandwiched between the driving electrode and the second electrode, and a second portion of the second piezoelectric layer is sandwiched between the driving electrode and the third electrode. The first and second portions are polarized parallel to the stacking direction such that they are polarized in mutually opposite directions. |
| US09142752B2 |
Low frequency broad band ultrasonic transducers
Low frequency pulse-echo ultrasonic transducers are provided especially suited for use in downhole cement bond evaluation, but usable for various applications. One frequency pulse-echo ultrasonic transducer comprises a transducer stack having alternating layers of a piezoceramic element and an ultrasonic attenuating element that is preferably acoustic impedance matched to the piezoceramic elements in order to reduce the Q of the transducer stack. Another low frequency pulse-echo ultrasonic transducer comprises an assembly having the present transducer stack disposed on an acoustic attenuating backing and a front face. Yet another low frequency pulse-echo ultrasonic transducer comprises a transducer composite made from a lead metaniobate. Still another frequency pulse-echo ultrasonic transducer comprises a composite stack. A further low frequency pulse-echo ultrasonic transducer comprises a composite stack, wherein multiple drive elements allow driving individual elements at different times. The transducers may be driven in a multiple-pulse time delayed manner. |
| US09142749B2 |
Thermoelectric conversion module
A thermoelectric conversion module includes: a first substrate having water permeability and thermal conductivity; a thermoelectric conversion element provided on the first substrate; a heat insulator having water permeability provided around the thermoelectric conversion element on the first substrate; and a second substrate disposed on the thermoelectric conversion element and the heat insulator and having water permeability and thermal conductivity. |
| US09142748B2 |
Light emitting device, display device, and manufacturing method for light emitting device
A light emitting device in which a plurality of LED chips are arranged. Each of the plurality of LED chips include a light emitting region that is formed on a substrate, a first pad electrode that is formed on the substrate, and a through-hole that penetrates the substrate. First wiring that passes through the through-hole of one LED chip and the through-hole of an adjacent LED chip, and electrically connects the first pad electrode of the one LED chip and the first pad electrode of the adjacent LED chip is provided. The tip-end parts of the first wiring that have passed through the through-holes have, at a cross section cut at a plane that is parallel with a principal surface of the substrate, a larger cross-sectional area than the cross-sectional area of the first wiring inside the through-holes. |
| US09142747B2 |
Light emitting device package and backlight unit comprising the same
Disclosed is a light emitting element package having excellent heat radiation performance and high luminance, and a backlight unit including the same. The light emitting element package includes a package including a lead frame, a light emitting element provided on the lead frame, and a molded material combined with the lead frame and having an opening for emitting light generated by the light emitting element, and a reflection structure having an opening corresponding to the opening of the molded material, and contacting the molded material. |
| US09142743B2 |
High temperature gold-free wafer bonding for light emitting diodes
A vertical GaN-based LED is made by growing an epitaxial LED structure on a silicon wafer. A silver layer is added and annealed to withstand >450° C. temperatures. A barrier layer (e.g., Ni/Ti) is provided that is effective for five minutes at >450° C. at preventing bond metal from diffusing into the silver. The resulting device wafer structure is then wafer bonded to a carrier wafer structure using a high temperature bond metal (e.g., AlGe) that melts at >380° C. After wafer bonding, the silicon is removed, gold-free electrodes (e.g., Al) are added, and the structure is singulated. High temperature solder (e.g., ZnAl) that is compatible with the electrode metal is used for die attach. Die attach occurs at >380° C. for ten seconds without melting the bond metal or otherwise damaging the device. The entire LED contains no gold, and consequently is manufacturable in a high-volume gold-free semiconductor fabrication facility. |
| US09142742B2 |
Thin-film LED with P and N contacts electrically isolated from the substrate
A thin-film light emitting diode includes an insulating substrate, a reflective metal electrode on the insulating substrate forming a current spreading layer, and an epitaxial structure on the electrode. |
| US09142736B2 |
LED (light-emitting diode) encapsulation and manufacturing method thereof
The present invention provides an LED encapsulation and a manufacturing method thereof. The LED encapsulation includes: a first frame (10), a plurality of LED elements (20), encapsulant (30), and the quantum dot rail (40). The first frame (10) includes a PCB (12) and four sidewalls (14). The four sidewalls (14) surround and circumferentially delimit an accommodation space (18). The plurality of LED elements (20) is mounted on the PCB (12) and in electrical connection therewith. The encapsulant (30) is filled in the accommodation space (18). The four sidewalls (14) each have a top end portion forming a mounting section (16). The quantum dot rail (40) is mounted in the mounting sections (16) so that the quantum dot rail (40) is located above the encapsulant (30). The first frame (10), the plurality of LED elements (20), and the quantum dot rail (40) are collectively and integrally encapsulated so as to be fixedly assembled together. |
| US09142735B2 |
Light emitting device
Disclosed is a light emitting device including a light emitting structure comprising a first semiconductor layer, an active layer and a second semiconductor layer, a phosphor plate disposed on the second semiconductor layer, and a bonding portion disposed between the light emitting structure and the phosphor plate, the bonding portion bonding the phosphor plate to the light emitting structure. |
| US09142730B2 |
Method of manufacturing semiconductor light emitting device
A method of manufacturing a semiconductor light emitting device is performed on a light emitting structure including a sequential stack of a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. The second conductivity-type semiconductor layer and the active layer are mesa-etched to expose a portion of the first conductivity-type semiconductor layer therethrough. A conductive layer is formed on the second conductivity-type semiconductor layer and the portion of the first conductivity-type semiconductor layer exposed by mesa-etching. In turn, the conductive layer is dry etched such that an upper surface of the first conductivity-type semiconductor layer is partially etched to have uneven portions formed thereon. The resulting semiconductor light emitting device has improved external light extraction efficiency while being easily manufactured. |
| US09142729B2 |
Light emitting element
A light emitting element includes a semiconductor laminate structure including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type, a part of the second semiconductor layer and the light emitting layer being removed to expose a part of the first semiconductor layer, a first reflecting layer located on the semiconductor laminate structure and including an opening, the opening being formed in the exposed part of the first semiconductor layer, a transparent wiring electrode for carrier injection into the first semiconductor layer or the second semiconductor layer through the opening, and a second reflecting layer formed on the transparent wiring electrode and covering a part of the opening so as to reflect light emitted from the light emitting layer and passing through the opening back to the first semiconductor layer. |
| US09142728B2 |
Semiconductor light emitting device and method for manufacturing the same
According to one embodiment, a semiconductor light emitting device includes a structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes an electrode layer provided on the second semiconductor layer side of the structure. The electrode layer includes a metal portion with a thickness of not less than 10 nanometers and not more than 100 nanometers. A plurality of openings pierces the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. The device includes an inorganic film providing on the metal portion and inner surfaces of the openings, the inorganic film having transmittivity with respect to light emitted from the light emitting layer. |
| US09142720B2 |
Thin-film light emitting diode chip and method for producing a thin-film light emitting diode chip
A thin-film light-emitting diode chip with a layer stack having a first emission surface and an opposite second emission surface, so that the thin-film light-emitting diode chip has at least two main emission directions. Measures for improving the outcoupling of the light generated in the layer sequence are provided on both the first and the second main emission surface. A method is disclosed for manufacturing a thin-film light-emitting diode chip. |
| US09142719B2 |
Patterned substrate and light-emitting diode having the same
A patterned substrate for epitaxially forming a light-emitting diode includes: a top surface; a plurality of spaced apart recesses, each of which is indented downwardly from the top surface and each of which is defined by a recess-defining wall, the recess-defining wall having a bottom wall face, and a surrounding wall face that extends from the bottom wall face to the top surface; and a plurality of protrusions, each of which protrudes upwardly from the bottom wall face of the recess-defining wall of a respective one of the recesses. A light-emitting diode having the patterned substrate is also disclosed. |
| US09142717B2 |
Semiconductor light emitting device and wafer
According to one embodiment, a semiconductor light emitting device includes: a foundation layer, a first semiconductor layer, a light emitting part, and a second semiconductor layer. The foundation layer includes a nitride semiconductor. The foundation layer has a dislocation density not more than 5×108 cm−2. The first semiconductor layer of a first conductivity type is provided on the foundation layer and includes a nitride semiconductor. The light emitting part is provided on the first semiconductor layer. The light emitting part includes: a plurality of barrier layers; and a well layer provided between the barrier layers. The well layer has a bandgap energy smaller than a bandgap energy of the barrier layers and has a thickness larger than a thickness of the barrier layers. The second semiconductor layer of a second conductivity type different from the first conductivity type, is provided on the light emitting part and includes a nitride semiconductor. |
| US09142715B2 |
Light emitting diode
An exemplary embodiment of the present invention relates to a light emitting diode (LED) including a substrate, a first nitride semiconductor layer arranged on the substrate, an active layer arranged on the first nitride semiconductor layer, a second nitride semiconductor layer arranged on the active layer, a third nitride semiconductor layer disposed between the first nitride semiconductor layer or between the second nitride semiconductor layer and the active layer, the third nitride semiconductor layer comprising a plurality of scatter elements within the third nitride semiconductor layer, and a distributed Bragg reflector (DBR) comprising a multi-layered structure, the substrate being arranged between the DBR and the third nitride semiconductor layer. |
| US09142708B2 |
Glass composition and conductive paste for aluminum electrode wiring, electronic component provided with that aluminum electrode wiring and method for producing this electronic component
Disclosed is a constitution formed from an oxide of an element having a smaller work function than aluminum. This oxide is comprises an oxide of vanadium (V), an oxide of an alkaline earth metal and an oxide of an alkali metal. The elements for the alkaline earth metal are comprise one or more elements out of the elements calcium (Ca), strontium (Sr) and barium (Ba) and at least contain barium. The elements for the alkali metal include at least one or more of sodium (Na), potassium (K), rubidium (Rb) and cesium (Cs). When the element vanadium is included as vanadium pentoxide (V2O5), the vanadium pentoxide content is 40-70 wt %. Thus, a glass composition for aluminum electrode wiring with an apparent work function for electrode wiring that is smaller than the work function for aluminum (Al) can be provided without the inclusion of lead. |
| US09142707B2 |
System and method for improved epitaxial lift off
An apparatus, system and method for performing ELO are disclosed. Device assemblies are contemporaneously etched in a stacked arrangement. Each device assembly may be placed in a respective tray, where the trays are overlapped and spaced apart from one another. In this manner, more device assemblies can be etched per unit area compared to conventional systems. Further, by stacking device assemblies during etching, the yield can be improved and/or the cost of the etch tank and associated hardware can be reduced. |
| US09142700B2 |
Assembly for supporting and grounding solar panels
In various representative aspects, an assembly for supporting and penetrating metallic solar panel frames to provide a grounding path between the panels, holding ballast of various masses to stabilize the solar panels, and allowing the solar panels to tilt to an adjustable angle is disclosed herein. The assembly has a support member with a pair of vertical components, a ballast holder and a mounting member with at least a raised portion to penetrate a surface of a solar panel and form a grounding path between the assembly and the solar panel. The mass of ballast is adjustable by placing various number of ballast blocks in the ballast holder to stabilize the attached solar panel. The mounting member is pivotally coupled to at least one of the vertical components of the support member so that the angle between the solar panel and the assembly may be adjusted. |
| US09142698B1 |
Integrated electro-absorption modulator
An integrated optical device includes an electro-absorption modulator disposed on a top surface of an optical waveguide. The electro-absorption modulator includes germanium disposed in a cavity between an n-type doped silicon sidewall and a p-type doped silicon sidewall. By applying a voltage between the n-type doped silicon sidewall and the p-type doped silicon sidewall, an electric field can be generated in a plane of the optical waveguide, but perpendicular to a propagation direction of the optical signal. This electric field shifts a band gap of the germanium, thereby modulating the optical signal. |
| US09142694B2 |
Focal plane array packaging using isostatic pressure processing
A method for bonding a first semiconductor body having a plurality of electromagnetic radiation detectors to a second semiconductor body having read out integrated circuits for the detectors. The method includes: aligning electrical contacts for the plurality of electromagnetic radiation detectors with electrical contacts of the read out integrated circuits; tacking the aligned electrical contacts for the plurality of electromagnetic radiation detectors with electrical contacts of the read out integrated circuits to form an intermediate stage structure; packaging the intermediate stage structure into a vacuum sealed electrostatic shielding container having flexible walls; inserting the package with the intermediate stage structure therein into an isostatic pressure chamber; and applying the isostatic pressure to the intermediate stage structure through walls of the container. The container includes a stand-off to space walls of the container from edges of the first semiconductor body. |
| US09142690B2 |
Semiconductor device having a bonding pad and shield structure and method of manufacturing the same
A method of fabricating a semiconductor device includes providing a device substrate having a front side and a back side corresponding to a front side and a back side of the semiconductor device, forming, on the front side of the device substrate, a metal feature, forming, on the back side of the device substrate, an insulating layer, forming, on the back side of the semiconductor device, a trench exposing the metal feature, forming a bonding pad in the trench in electrical communication with the metal feature, and forming, on the insulating layer, a metal shield, in which the metal shield and the bonding pad have different thicknesses relative to each other. |
| US09142688B2 |
Gallium nitride-based diode and method of fabricating the same
A GaN-based diode may include an intrinsic GaN-based semiconductor layer, GaN-based semiconductor layers configured to have a first conductivity type and bonded to the intrinsic GaN-based semiconductor layer. A first electrode made of metal is placed on a surface opposite a surface bonded to the GaN-based semiconductor layers of the intrinsic GaN-based semiconductor layer; a second electrode is placed on a surface opposite to a surface bonded to the intrinsic GaN-based semiconductor layer of the GaN-based semiconductor layers of the first conductivity type. Voltage-resistant layers configured to have a second conductivity type are formed in regions of the intrinsic GaN-based semiconductor layer that come in contact with edges of the first electrode. |
| US09142686B2 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). |
| US09142685B2 |
Nonvolatile semiconductor memory device provided with charge storage layer in memory cell
A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion located on the semiconductor portion, a silicon-containing portion located on the first oxygen-containing portion, a first film located on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion located on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion located on the first high dielectric insulating portion, a second high dielectric insulating portion located on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion located on the second high dielectric insulating portion, and a second film located on the third oxygen-containing portion. |
| US09142682B2 |
Thin film transistor and manufacturing method thereof
A thin film transistor and a manufacturing method thereof. The thin film transistor includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a first semiconductor disposed on the gate insulating layer; a second semiconductor disposed on the first semiconductor and having a different plane shape from the first semiconductor; and a source electrode and a drain electrode that are disposed on the second semiconductor and face each other. |
| US09142681B2 |
Semiconductor device and method for manufacturing the same
A metal oxide layer is in contact with an interlayer insulating layer covering a transistor, and has a stacked-layer structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. In the first metal oxide layer, there are no crystal grain boundaries, and grid intervals are wide as compared to those in a metal oxide layer in a crystalline state; thus, the first metal oxide layer easily traps moisture between the lattices. In the second metal oxide layer having a polycrystalline structure, crystal parts other than crystal grain boundary portions have dense structures and extremely low moisture permeability. Thus, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture permeation into the transistor. |
| US09142680B2 |
Thin film transistor array panel having improved aperture ratio and method of manufacturing same
A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate. |
| US09142678B2 |
Semiconductor device having fin structure and method of manufacturing the same
In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film. |
| US09142667B2 |
Semiconductor device and method for manufacturing same
According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode. |
| US09142664B2 |
Semiconductor device
A superjunction semiconductor device is disclosed in which the tradeoff relationship between on-resistance and breakdown voltage is improved greatly so that reverse recovery capability is improved. A drain drift portion substantially corresponds to a portion just under p-base regions serving as an active region and forms a first parallel pn structure in which a first n-type region and a first p-type region are joined to each other alternately and repeatedly. A drain drift portion is surrounded by edge termination region including a second parallel pn structure. Edge termination region is formed such that second n-type and p-type regions oriented consecutively to the first parallel pn structure of the drain drift portion are joined to each other alternately and repeatedly. N-buffer layer is provided between first and second parallel pn structures and n+ drain layer. P-buffer layer is provided selectively inside n-buffer layer in edge termination region. |
| US09142663B2 |
Silicon carbide devices having smooth channels
Methods of forming silicon carbide power devices are provided. An n− silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n− silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n− region is provided on the channel region and a portion of the n− region is removed from the channel region so that a portion of the n− region remains on the channel region to provide a reduction in a surface roughness of the channel region. |
| US09142662B2 |
Field effect transistor devices with low source resistance
A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region. |
| US09142660B2 |
Method to fabricate a vertical transistor having an asymmetric gate with two conductive layers having different work functions
A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate. |
| US09142658B2 |
Compound semiconductor device and method of manufacturing the same
A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons. |
| US09142655B2 |
Semiconductor device
A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center. |
| US09142651B1 |
Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device
One method disclosed includes, among other things, covering a top surface and a portion of the sidewalls of a fin with etch stop material, forming a sacrificial gate structure above and around the fin, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, forming a counter-doped region in the fin below an upper surface of the fin and below the channel region of the device, wherein the counter-doped region is doped with a second type of dopant material that is of an opposite type relative to the first type of dopant material, and forming a replacement gate structure in the replacement gate cavity. |
| US09142650B2 |
Tilt implantation for forming FinFETs
Methods for fabrication of fin devices for an integrated circuit are provided. Fin structures are formed in a semiconductor material, where the fin structures include sidewalls and tops. Dopant implantation is performed at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, where the semiconductor material is maintained at an elevated temperature during the dopant implantation. The elevated temperature prevents amorphization of the fin structures during the dopant implantation. A field effect transistor is formed from the fin structures. The field effect transistor has a threshold voltage that is based on the dopant implantation. |
| US09142648B2 |
Semiconductor device and manufacturing method thereof
Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer. |
| US09142645B2 |
Method for producing semiconductor device and semiconductor device
A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. |
| US09142641B1 |
Method for manufacturing finFET
A method for manufacturing a FinFET includes forming a merging spacer, through a plurality of sidewall pattern-transferring processes, and modifying a first interval between adjacent first mandrels as shorter than twice of thicknesses of a nitride layer, which is formed on the first mandrels and contoured thereto, followed by a first spacer being formed on a sidewall thereof, so that a FinFET composed of a plurality of fin-shaped structures having a non-integral multiple of pitches as well as an integral multiple of pitches can be manufactured. |
| US09142640B1 |
Containment structure for epitaxial growth in non-planar semiconductor structure
A non-planar transistor is fabricated with dummy or sacrificial epitaxy and a structure for subsequent replacement or final epitaxy containment is created around the sacrificial epitaxy. The dummy epitaxy is then removed and replaced with the replacement epitaxy. The containment structure allows for uniform growth of the replacement epitaxy and prevents merger. Where n-type and p-type structures are present, the replacement epitaxy process is performed for each type, while protecting the other type with a mask. Optionally, one of the replacement epitaxies, i.e., the one for n-type or p-type, may be used as the dummy epitaxy, resulting in the need for only one mask. |
| US09142637B2 |
III-nitride monolithic IC
III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures. |
| US09142635B2 |
Graphene electronic device and method of fabricating the same
The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer. |
| US09142633B2 |
Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin. |
| US09142632B2 |
Liquid crystal display device
It is an object to provide a liquid crystal display device including a thin film transistor with high electric characteristics and high reliability. As for a liquid crystal display device including an inverted staggered thin film transistor of a channel stop type, the inverted staggered thin film transistor includes a gate electrode, a gate insulating film over the gate electrode, a microcrystalline semiconductor film including a channel formation region over the gate insulating film, a buffer layer over the microcrystalline semiconductor film, and a channel protective layer which is formed over the buffer layer so as to overlap with the channel formation region of the microcrystalline semiconductor film. |
| US09142628B2 |
Metal oxide thin film transistor
A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode. |
| US09142626B1 |
Stepped field plate wide bandgap field-effect transistor and method
A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist. |
| US09142625B2 |
Field plate assisted resistance reduction in a semiconductor device
Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described. |
| US09142622B2 |
Method of growing nitride semiconductor layer, nitride semiconductor device, and method of fabricating the same
Exemplary embodiments of the present invention provide a method of growing a nitride semiconductor layer including growing a gallium nitride-based defect dispersion suppressing layer on a gallium nitride substrate including non-defect regions and a defect region disposed between the non-defect regions, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer. |
| US09142620B2 |
Power device packaging having backmetals couple the plurality of bond pads to the die backside
The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside. |
| US09142613B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region. |
| US09142609B2 |
MIM capacitor device
A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film. |
| US09142608B2 |
Manufacturing method of semiconductor device and semiconductor device
A step of forming a stacked film serving as a lower electrode, a step of forming an insulating film serving as a capacitive film on the stacked film, and a step of patterning the insulating film and the stacked film are performed. In the step of forming the stacked film, a film containing titanium, a film containing titanium and nitrogen, a main conductive film containing aluminum, a film containing titanium, and a film containing titanium and nitrogen are sequentially formed from below. The ratio of the surface roughness of the upper surface of the stacked film to the thickness of the insulating film is 14% or less. |
| US09142607B2 |
Metal-insulator-metal capacitor
A capacitor suitable for inclusion in a semiconductor device includes a substrate, a first metallization level, a capacitor dielectric, a capacitor plate, an interlevel dielectric layer, and a second metallization level. The first metallization level overlies the substrate and includes a first metallization plate overlying a capacitor region of the substrate. The capacitor dielectric overlies the first metallization plate and includes a dielectric material such as a silicon oxide or silicon nitride compound. The capacitor plate is an electrically conductive structure that overlies the capacitor dielectric. The interlevel dielectric overlies the capacitor plate. The second metallization layer overlies the interlevel dielectric layer and may include a second metallization plate and a routing element. The routing element may be electrically connected to the capacitor plate. The metallization plates may include a fingered structure that includes a plurality of elongated elements extending from a cross bar. |
| US09142605B2 |
Display panel and panel inspection apparatus
Disclosed herein is a display panel based on active matrix driving having a display area made up of N pixel control lines, M video signal lines orthogonally intersecting the N pixel control lines, and pixel circuits arranged at intersections between the N pixel control lines and M video signal lines, wherein positional identification patterns are arranged on every k (k being a natural number) pixel control lines inside each of the pixel circuits. |
| US09142603B2 |
Organic light-emitting diode (OLED) display and method of manufacturing the same
An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the OLED display comprises a driving thin-film transistor (TFT), a data line electrically connected to the driving TFT and having a first color, an OLED, and a light absorption layer. The OLED is electrically connected to the driving TFT. The light absorption layer is formed over the data line and has a second color different from the first color. |
| US09142598B2 |
Light-emitting panel, light-emitting device using the light-emitting panel, and method for manufacturing the light-emitting panel
To provide a light-emitting panel in which the occurrence of crosstalk is suppressed. To provide a method for manufacturing a light-emitting panel in which the occurrence of crosstalk is suppressed. The light-emitting panel includes a first electrode of one light-emitting element, a first electrode of the other light-emitting element, and an insulating partition which separates the two first electrodes. A portion with a thickness A1 smaller than a thickness A0 of a portion of the layer containing a light-emitting organic compound, which overlaps with a side surface of the partition, is included. The ratio (B1/B0) of a thickness B1 of a portion of the second electrode, which overlaps with a side surface of the partition, to a thickness B0 of a portion of the second electrode, which overlaps with the first electrode, is higher than the ratio (A1/A0). |
| US09142591B2 |
Method for measuring electronic multiplication factor
In an electron multiplying imaging device 1 with a solid-state image pickup device 10, a first multiplied image of incident light with a first light amount and a second multiplied image of incident light with a second light amount are acquired at a predetermined electron multiplication factor set in advance, and a luminance average value and a luminance variance average value of pixels included in the first multiplied image and a luminance average value and a luminance variance average value of pixels included in the second multiplied image are calculated. By using the calculated luminance average values and luminance variance average values, a conversion factor of the first and second multiplied images is calculated, and by using the calculated conversion factor and a conversion factor at a reference electron multiplication factor held in advance, an actual electron multiplication factor of the solid-state image pickup device 10 is calculated. |
| US09142590B2 |
Image sensor device and manufacturing method thereof
A method for manufacturing a transfer gate transistor of an image sensor device is disclosed. The transistor includes a substrate, a gate oxide layer on the substrate and a gate electrode portion on the gate oxide layer. The gate electrode portion has a trench or an insulating layer used for accurately defining a first region and a second region in the gate electrode portion, wherein the first region has a first conductivity type, and the second region has a second conductivity type or is an undoped region. |
| US09142584B2 |
Solid-state imaging device with pixel isolation portion, method for manufacturing solid-state imaging device, and electronic apparatus
A solid-state imaging device with a pixel region in which a plurality of pixels with photoelectric conversion films are arrayed and pixel isolation portions are interposed between the plurality of pixels. The photoelectric conversion film is a chalcopyrite-structure compound semiconductor composed of a copper-aluminum-gallium-indium-sulfur-selenium based mixed crystal or a copper-aluminum-gallium-indium-zinc-sulfur-selenium based mixed crystal, and is disposed on a silicon substrate in such a way as to lattice-match the silicon substrate concerned. The pixel isolation portion is a compound semiconductor subjected to doping concentration control or composition control so as to become a potential barrier between the photoelectric conversion films. |
| US09142580B2 |
Image pickup apparatus and image pickup system
An image pickup apparatus includes a pixel portion in which pixels are arranged, the pixels each including a first semiconductor region of first conductivity type having signal charges as majority carriers and a second semiconductor region of second conductivity type having signal charges as minority carriers, the second semiconductor region being contiguous to the first semiconductor region, the first semiconductor region being disposed between a surface of a semiconductor substrate. The pixel portion includes a class I pixel and a class II pixel located near a reference contact. A distance between the surface of the semiconductor substrate and the second semiconductor region of the class I pixel is smaller than a distance between the surface of the semiconductor substrate and the second semiconductor region of the class II pixel. |
| US09142579B2 |
Photoelectric conversion cell and array, reset circuit and electrical signal sense control circuit therefor
In order to achieve a photoelectric conversion cell and an array of high sensitivity and high dynamic range, there is a need for a photoelectric conversion cell and an array in which combination of an amplified photoelectric conversion element and a selection element are resistant to external noise, and the combination is resistant to effects from address selection pulse noise at array readout time. In the present invention, in order to solve the problem, a photoelectric conversion cell has been configured with a combination of an amplified photoelectric conversion element (100) and a selection element (10 and the like) which are resistant to external noise, and various means of solution of the combination are provided which are resistant to the effects of address selection pulse noise at array readout time. As a result, a dynamic range of 6 to 7 orders of magnitude for light detection has become possible. |
| US09142576B2 |
Solid-state image sensor, method for the same, and electronic device
There is provided a solid-state image sensor including a photoelectric conversion part which generates a charge corresponding to received light and accumulates the charge therein, a charge holding part in which before the charge accumulated in the photoelectric conversion part is transferred to a floating diffusion region, the charge is held for a predetermined time, a first transfer gate which transfers the charge accumulated in the photoelectric conversion part to the charge holding part, a second transfer gate which transfers the charge held in the charge holding part to the floating diffusion region, and a charge discharging gate which discharges the charge in the photoelectric conversion part. Before charge accumulation in the photoelectric conversion part for the next frame is started, part of the charge accumulated in the charge holding part is discharged. |
| US09142571B2 |
Display device and electronic equipment
A display device includes a pixel array section, the pixel array section having pixels arranged in a matrix form, at least one of the pixels including an electro-optical element, a write transistor, a capacitor, a drive transistor, and a switching transistor. A write scan line is disposed for each pixel row of the pixel array section and adapted to convey a write signal to be applied to a gate electrode of the write transistor. The wiring structure of the write scan line does not cross a wiring pattern connected to a gate electrode of the drive transistor. |
| US09142566B2 |
Method of forming different voltage devices with high-K metal gate
A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each DGO transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers. |
| US09142561B2 |
Nonvolatile semiconductor memory device and method for manufacturing same
According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions; a plurality of control gate electrodes; a charge storage layer; a first insulating film provided between the charge storage layer and first semiconductor regions; a second insulating film provided between the charge storage layer and control gate electrodes; and an element isolation region provided between the plurality of first semiconductor regions, and the element isolation region being in contact with the first insulating film and a first portion of the charge storage layer on the first insulating film side. Each of the plurality of control gate electrodes is in contact with a second portion other than the first portion of the charge storage layer. The charge storage layer includes a silicon-containing layer in contact with the first insulating film and a silicide-containing layer provided on the silicon-containing layer. |
| US09142560B2 |
Layout to minimize FET variation in small dimension photolithography
A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell. |
| US09142559B2 |
Semiconductor integrated circuit device
A semiconductor integrated circuit device includes a pair of complementary signal lines, a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being coupled to one of the pair of the complementary signal lines, and a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of the first transistor, one of a source and a drain of the second transistor coupled to an other of the source and the drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to the other of the pair of the complementary signal lines. A direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor. |
| US09142558B2 |
Semiconductor device having supporter and method of forming the same
A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %. |
| US09142557B2 |
Cost effective method of forming embedded DRAM capacitor
A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers. |
| US09142552B2 |
Semiconductor array having temperature-compensated breakdown voltage
A semiconductor array is described whose breakdown voltage has only a very low temperature coefficient or none at all and therefore there is little or no temperature-dependent voltage rise. The voltage limitation is achieved by a punch-through effect. |
| US09142551B2 |
Semiconductor device having a pair of transistors that are directly coupled and capacitively coupled
According to one embodiment, a semiconductor element includes a first transistor section, a second transistor section, a contact region, and a capacitive element section. The first transistor section includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, the third semiconductor region, and the third semiconductor region being connected to the second electrode, and a third electrode. The second transistor section includes a fourth electrode, a fifth electrode, a fourth semiconductor region, a fifth semiconductor region, a sixth semiconductor region, and the sixth semiconductor region being connected to the fifth electrode, and a sixth electrode, the second transistor section being arranged adjacent to the first transistor section. The contact region includes a seventh electrode, electrically connecting the fifth electrode and the first electrode. The capacitive element section is connected between the second electrode and the fourth electrode. |
| US09142548B2 |
FinFET compatible capacitor circuit
A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin. |
| US09142547B2 |
Methods of manufacturing resistors and structures thereof
A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material. |
| US09142546B2 |
Method of making bipolar junction transistor by forming base epitaxy region on etched opening in DARC layer
A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region. |
| US09142545B2 |
Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise
The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region. |
| US09142544B2 |
Semiconductor device
A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source. |
| US09142543B2 |
Semiconductor device having an ESD protection circuit
An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal. |
| US09142542B2 |
Semiconductor device with protective diode
A semiconductor device (1) includes an n type epitaxial layer (8), body regions (12) formed in the surface layer part of the n type epitaxial layer (8), n type source regions (16) formed in the surface layer parts of the body regions (12), a gate insulating film (19) formed on the n type epitaxial layer (8), and a gate protection diode (30) and gate electrodes (20) formed on the gate insulating film (19). The gate protection diode (30) includes a first p type region (31), an n type region (32), and a second p type region (33). A first diode (30A) is formed of the first p type region (31) and the n type region (32). A second diode (30B) is formed of the n type region (32) and the second p type region (33). The first p type region (31) is connected to the gate electrode (20). The second p type region (33) is connected to a source electrode (27). |
| US09142538B1 |
Three-dimensional semiconductor device
A 3D semiconductor device is provided, comprising memory layers, a selection line, bit lines, strings, memory cells defined by the strings, the selection line, and the bit lines, wherein the memory cells are arranged in a plurality of rows having a first direction, and a stair contact structure including stair contacts and conductive lines, wherein the stair contacts are arranged in a plurality of columns having a fourth direction. The 3D semiconductor device satisfies the following condition: 1 |
| US09142536B2 |
Semiconductor device and method for fabricating the same
A method for manufacturing the semiconductor device may include forming a capping layer including a bit line contact hole on a substrate, forming a spacer on inner walls of the bit line contact hole, forming a bit line contact in the bit line contact hole, forming a bit line layer on the substrate, exposing the spacer by etching the bit line layer, and etching the spacer. |
| US09142534B2 |
Light-emitting device
A light-emitting device is provided that is capable of being directly connected to an alternative current source, including at least one electronic element; at least one light-emitting diode array chip; at least one bonding pad, a conductive trace, and a submount for supporting the electronic element, the light-emitting diode array chip, the bonding pad, and the conductive trace. The conductive trace is electrically connected to the electronic element, the light-emitting diode array chip, and bonding pad. |
| US09142530B2 |
Coreless integrated circuit packaging system and method of manufacture thereof
A system and method for manufacturing an integrated circuit packaging system includes: forming a base substrate including: providing a sacrificial carrier: mounting a metallic sheet on the sacrificial carrier, applying a top trace to the metallic sheet, forming a conductive stud on the top trace, forming a base encapsulation over the metallic sheet, the top trace, and the conductive stud, the top trace exposed from a top surface of the base encapsulation, and removing the sacrificial carrier and the metallic sheet; mounting an integrated circuit device on the base substrate; and encapsulating the integrated circuit device and the base substrate with a top encapsulation. |
| US09142529B2 |
Chip package with improved heat dissipation and manufacturing method thereof
A chip package includes: a semiconductor chip having an upper surface and a lower surface opposite to each other, the semiconductor chip including an image sensor circuit; a metal heat conductive layer formed on the lower surface, for conducting or absorbing heat generated by the semiconductor chip; a bond pad formed on the upper surface, for electrically connecting with the image sensor circuit in the semiconductor chip, wherein the metal heat conductive layer conducts or absorbs heat generated by the semiconductor chip, to thereby reduce temperature of the image sensor circuit in the semiconductor chip and improve the performance of the circuit, wherein the metal heat conductive layer entirely covers the lower surface. |
| US09142528B2 |
Semiconductor device with an interlocking structure
In one embodiment, a semiconductor device having a die attach pad, a semiconductor die and an adhesive material is disclosed. The adhesive material may be configured to adjoin the semiconductor die and the die attach pad. The die attach pad may be sandwiched between the semiconductor die and the die attach pad. In another embodiment, a device having a semiconductor die, a die attach glue and a die attach pad is disclosed. The device may comprise an interlock structure formed integrally with the die attach pad. In yet another embodiment, a light-emitting device comprising an interlock structure is disclosed. |
| US09142523B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a carrier, a die including a first surface and a second surface, a plurality of first conductive bumps disposed between the second surface of the carrier and the die, wherein the die is flip bonded on the carrier, and a molding disposed over the carrier and surrounding the die, wherein the molding includes a recessed portion disposed on the first surface of the die thereby leaving a portion of the first surface is uncovered by the molding. Further, a method of manufacturing a semiconductor device includes providing a carrier, flip bonding a die on the carrier, disposing a rubber material on a first surface of the die and within the first surface of the die, and forming a molding surrounding the rubber material and covering the carrier. |
| US09142518B2 |
Junction and electrical connection
A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor. |
| US09142517B2 |
Hybrid bonding mechanisms for semiconductor wafers
The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers. |
| US09142513B2 |
Middle-of-the-line constructs using diffusion contact structures
An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions. |
| US09142512B2 |
Semiconductor memory device having a wiring in which a step is provided
A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region. |
| US09142509B2 |
Copper interconnect structure and method for forming the same
A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer. |
| US09142508B2 |
Single exposure in multi-damascene process
Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed. |
| US09142507B1 |
Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device
An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal layers may disrupt the functionality of the IC device if the vacancies migrate to the vias interconnecting the metal layers. To mitigate vacancy migration, stressor elements are formed at the metal traces to form stress effects in the metal traces that, depending on type, either serve to repel migrating vacancies from the via contact area or to trap migrating vacancies at a portion of the metal trace displaced from the contact area. The stressor elements may be formed as stress-inducing dielectric or conductive material overlying the metal traces, or formed by inducing a stress memory effect in a portion of the metal trace itself. |
| US09142505B2 |
Method and apparatus for back end of line semiconductor device processing
Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). A barrier layer comprising a bottom part and a side part is formed within an opening for a metal contact, wherein the bottom part comprises a graphene material, the side part comprises an amorphous carbon material and covers a sidewall of the opening, and the bottom part and the side part are formed at a same time. A capping layer comprising a first part and a second part is formed on a dielectric layer and a metal contact, wherein the first part comprises a graphene material, the second part of the capping layer comprises an amorphous carbon material on the dielectric layer, and the first part and the second part are formed at a same time. |
| US09142495B2 |
Lead frame and semiconductor package manufactured by using the same
The present invention provides a lead frame having excellent solder wettability and solderability, that is well-bonded to a copper wire, and manufactured with low cost, and a semiconductor package manufactured by using the same. The lead frame includes: a base material; a first metal layer formed on at least one surface of the base material, the first metal layer comprising nickel; a second metal layer formed on a surface of the first metal layer, the second metal layer comprising palladium; and a third metal layer formed on a surface of the second metal layer, the third metal layer comprising silver. |
| US09142494B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102. |
| US09142493B2 |
Semiconductor device
The semiconductor device includes; a semiconductor element in which a metallization layer is formed on the backside side; a metallic lead frame that is arranged in parallel, with a distance spaced apart from the semiconductor element; a first bonding layer that is provided between the semiconductor element and the lead frame, and is bonded to the metallization layer; and a second bonding layer that is provided between the semiconductor element and the lead frame, and bonds the first bonding layer to the lead frame. The first bonding layer is expanded at a central portion toward the lead frame. |
| US09142491B2 |
Semiconductor package with corner pins
There are provided semiconductor packages having corner pins and methods for their fabrication. Such a semiconductor package includes a leadframe and a die paddle, the leadframe having first and second edge sides meeting to form a first corner. The semiconductor package also includes edge pins arrayed substantially parallel to the first edge side and edge pins arrayed substantially parallel to the second edge side. In addition, the semiconductor package includes a first corner pin situated at the first corner, the first corner pin being electrically isolated from the die paddle. |
| US09142489B2 |
Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern
Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided. |
| US09142488B2 |
Manganese oxide hard mask for etching dielectric materials
A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process. |
| US09142487B2 |
Packaging structural member
A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. |
| US09142485B2 |
Contactless object with integrated circuit connected to circuit terminals by capacitive coupling
The invention relates to integrated circuits (1) that comprise, on the active surface thereof, a first dielectric layer defining a passivation layer (6) and contact pads (5) flush through openings (7) in said passivation layer, wherein said integrated circuits are to be incorporated in contactless portable objects (10) for connection by capacitive coupling to the terminals (13) of an antenna-forming circuit (11) mounted on a substrate (12) of said object. The invention also relates to contactless portable objects including such circuits. The invention is characterized in that the capacitive coupling is carried out using connection plates (8) of the integrated circuits, positioned at the surface of the passivation layer and electrically connected to the contact pads. The invention can particularly be used in UHF RFID objects. |
| US09142474B2 |
Passivation structure of fin field effect transistor
A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material. |
| US09142473B2 |
Stacked type power device module
The disclosure relates to a stacked type power device module. May use the vertical conductive layer for coupling the stacked devices, the electrical transmission path may be shortened. Hence, current crowding or contact damages by employing the conductive vias or wire bonding may be alleviated. |
| US09142469B2 |
Semiconductor device
A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge. |
| US09142467B2 |
Etch rate detection for anti-reflective coating layer and absorber layer etching
A method and apparatus for etching a photomask substrate with enhanced process monitoring is provided. In one embodiment, a method of determining an etching endpoint includes performing an etching process on a first tantalum containing layer through a patterned mask layer, directing a radiation source having a first wavelength from about 200 nm and about 800 nm to an area uncovered by the patterned mask layer, collecting an optical signal reflected from the area covered by the patterned mask layer, analyzing a waveform obtained the reflected optical signal reflected from the substrate from a first time point to a second time point, and determining a first endpoint of the etching process when a slope of the waveform is changed about 5 percent from the first time point to the second time point. |
| US09142466B2 |
Using spectra to determine polishing endpoints
Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described. |
| US09142465B1 |
Precise annealing of focal plane arrays for optical detection
Precise annealing of identified defective regions of a Focal Plane Array (“FPA”) (e.g., exclusive of non-defective regions of the FPA) facilitates removal of defects from an FPA that has been hybridized and/or packaged with readout electronics. Radiation is optionally applied under operating conditions, such as under cryogenic temperatures, such that performance of an FPA can be evaluated before, during, and after annealing without requiring thermal cycling. |
| US09142458B2 |
Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness. |
| US09142453B1 |
Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer. |
| US09142451B2 |
Reduced capacitance interlayer structures and fabrication methods
Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure. |
| US09142448B2 |
Method of producing a silicon-on-insulator article
A method of producing a silicon-on-insulator article, the method including: forming a first aluminum nitride layer thermally coupled to a first silicon substrate; forming a second aluminum nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminum nitride layers of the first and second substrates together so that the first and second aluminum nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminum nitride layers. |
| US09142443B2 |
Method of manufacturing semiconductor device
To provide a semiconductor device having improved reliability at an improved production yield.After forming an insulating film on the main surface of a semiconductor substrate as an oxide film, form a silicon nitride film on the insulating film. Then, form an element isolating trench by plasma dry etching, form an insulating film made of silicon oxide so as to fill the trench by using HDP-CVD, and remove the insulating film outside the trench by CMP, while leaving the insulating film in the trench. Then, remove the silicon nitride film, followed by removal of the insulating film by wet etching to expose the semiconductor substrate. At this time, the insulating film is wet etched while applying light of 140 lux or greater to the main surface of the semiconductor substrate. |
| US09142439B2 |
Laminated structure, member for semiconductor manufacturing apparatus, and method for producing laminated structure
A laminated structure 10 includes a first structure 12 containing a main phase of magnesium-aluminum oxynitride, a second structure 14 containing a main phase of aluminum nitride and grain boundary phases of a rare-earth aluminum composite oxide having a garnet-type crystal structure, and a reaction layer 15 formed between the first structure 12 and the second structure 14. The reaction layer 15 is an aluminum nitride layer containing a smaller amount of grain boundary phases 18 of the rare-earth aluminum composite oxide than the second structure 14. The reaction layer 15 of the laminated structure 10 has a thickness of 150 μm or less. The reaction layer 15 is formed during the sintering by diffusing the grain boundary phases 18 into the first structure 12. |
| US09142430B2 |
High-voltage packaged device
Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described. |
| US09142424B2 |
Cleaning system and cleaning method
Provided are a system and method capable of providing a sulfuric acid solution containing peroxosulfuric acid for use in cleaning even in an installation-limited space such as a clean room while suppressing the fluid pressure in a heating part such as a rapid heating heater.The system comprises: an electrolytic part for electrolyzing a sulfuric acid solution to produce peroxosulfuric acid; a first reservoir for storing the sulfuric acid solution; a circulation line for circulating the sulfuric acid solution between the electrolytic part and the first reservoir; a cleaning apparatus for cleaning a cleaning object by use of the sulfuric acid solution containing peroxosulfuric acid; a supply line for sending the sulfuric acid solution electrolyzed in the electrolytic part to the cleaning apparatus; a heating part for heating the sulfuric acid solution to be used in the cleaning apparatus, the heating part being interposed in the supply line on the upstream side of the cleaning apparatus; and a second reservoir which is interposed in the supply line on the upstream side of the heating part. Since the second reservoir and the heating parts are positioned spatially above the level of the first reservoir, the electrolytic part and the circulation line, the device can be disposed with good space efficiency while preventing application of a high fluid pressure to the heating part or the like. |
| US09142423B2 |
Semiconductor mask blanks with a compatible stop layer
Provided is a method for creating a mask blank that includes a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detection of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer. |
| US09142413B2 |
Methods for growing a non-phase separated group-III nitride semiconductor alloy
Systems and methods for MBE growing of group-III Nitride alloys, comprising establishing an average reaction temperature range from about 250 C to about 850 C; introducing a nitrogen flux at a nitrogen flow rate; introducing a first metal flux at a first metal flow rate; and periodically stopping and restarting the first metal flux according to a first flow duty cycle. According to another embodiment, the system comprises a nitrogen source that provides nitrogen at a nitrogen flow rate, and, a first metal source comprising a first metal effusion cell that provides a first metal at a first metal flow rate, and a first metal shutter that periodically opens and closes according to a first flow duty cycle to abate and recommence the flow of the first metal from the first metal source. Produced alloys include AlN, InN, GaN, InGaN, and AlInGaN. |
| US09142407B2 |
Semiconductor structure having sets of III-V compound layers and method of forming the same
A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping. |
| US09142395B2 |
Parallel ion mass and ion mobility analysis
The present invention relates to a parallel IMS and MS measurement method where a sample flow is split and delivered to an IMS and a MS in parallel. A parallel acquisition MS/IMS method is used to supplement LC-MS and or MS data by using a synchronized MS/IMS acquisition. |
| US09142393B2 |
Method for cleaning reaction chamber using pre-cleaning process
A method for cleaning a reaction chamber is conducted after depositing an oxide, nitride, or oxynitride film on a substrate in a reaction chamber having interior surfaces on which oxide, nitride, or oxynitride is accumulated as a result of the deposition, said oxide, nitride, or oxynitride being selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, and metal oxynitride. The method includes: oxidizing or nitriding the oxide, nitride, or oxynitride is accumulated on the interior surfaces of the reaction chamber, by RF-excited plasma of an oxygen- or nitrogen-containing gas in the absence of halide gas as a pre-cleaning step; and cleaning the interior surfaces of the reaction chamber, by RF-excited plasma of a halide cleaning gas. |
| US09142391B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device is provided by performing plasma processing on a substrate to be processed by using a plasma processing apparatus including a processing chamber, a lower electrode, an upper electrode, a plurality of lifter pins, a focus ring, a lifter pin for focus ring and an electrical connection mechanism. |
| US09142390B2 |
Cathode interface for a plasma gun and method of making and using the same
Interchangeable or standard electrode interface for a thermal spray plasma gun includes an interchangeable electrode having a first connecting section and a first annular coupling surface. A second connecting section is arranged in a plasma gun and includes a second annular coupling surface. An annular seal is spaced or axially spaced from an annular interface formed between the first and second annular coupling surfaces. |
| US09142385B1 |
Charged particle beam treatment apparatus and method of adjusting path length of charged particle beam
A charged particle beam treatment apparatus includes: an accelerator configured to emit a charged particle beam by accelerating charged particles; an irradiation portion configured to irradiate an irradiation object with the charged particle beam through a scanning method; a transport line configured to transport the charged particle beam emitted from the accelerator to the irradiation portion; an energy adjusting portion configured to adjust energy of the charged particle beam; an electromagnet which is provided in the irradiation portion or the transport line; an electromagnet power source which is connected to the electromagnet; and a control portion. Semiconductors are connected between the electromagnet power source and the electromagnet in series. When switching a layer of the irradiation object to be irradiated with the charged particle beam, the control portion reduces the energy of the charged particle beam by controlling the energy adjusting portion and increases a resistance of the semiconductors. |
| US09142382B2 |
X-ray source with an immersion lens
An x-ray source is described. During operation of the x-ray source, an electron source emits a beam of electrons. This beam of electrons is focused to a spot on a target by a magnetic focusing lens. In particular, the magnetic focusing lens includes an immersion lens in which a peak in a magnitude of an associated magnetic field occurs proximate to a plane of the target. Moreover, in response to receiving the beam of focused electrons, the target provides a transmission source of x-rays. |
| US09142380B2 |
Sensor system comprising stacked micro-channel plate detector
A multilayer electronic imaging module and sensor system incorporating a micro-lens layer for imaging and collimating a received image from a field of regard, a photocathode layer for detecting photons from the micro-lens layer and generating an electron output, a micro-channel plate layer for receiving the output electrons emitted from the photocathode in response to the photon input and amplifying same and stacked readout circuitry for processing the electron output of the micro-channel plate. The sensor system of the invention may be provided in the form of a Cassegrain telescope assembly and includes electromagnetic imaging and scanning means and beam-splitting means for directed predetermined ranges of the received image to one or more photo-detector elements which may be in the form of the micro-channel imaging module of the invention. |
| US09142378B2 |
Ion generating device and electrical apparatus which can easily be reduced in size and thickness
An arrangement area of a transformer drive circuit, an arrangement area of a high-voltage transformer, and an arrangement area of an ion generating unit are two-dimensionally divided from each other in a casing. A connection terminal is electrically connected to the transformer drive circuit and is formed of a conductive film arranged to be exposed to the outside of the casing. Accordingly, an ion generating device whose size and thickness can be easily reduced and an electrical apparatus including the ion generating device can be provided. |
| US09142375B2 |
Solid state switching device
Switching device comprising: a switching unit comprising, for each electric pole, a first disconnection contact, a second disconnection contact and one or more solid state switches; a supporting frame comprising, for each electric pole, a third disconnection contact and a fourth disconnection contact, which are coupled/separated respectively with/from the first and second disconnection contacts, when the switching unit is in an insertion/withdrawn position with respect to the supporting frame; actuating means for moving the switching unit between the insertion position and said the withdrawn position, and viceversa; a control unit comprising control means that are configured to coordinate the operation of the actuating means and the solid state switches, when an insertion/withdrawn operation of the switching unit has to be performed, so that the actuating means move the switching unit only when the solid state switches are in an off-state. |
| US09142374B1 |
Solenoid linear actuator and method of making same
A solenoid linear actuator comprises a unibody soft magnetic core with a central body and an upper disk and narrower end extrusions, and a pair of soft magnetic bodies on the two ends of the solenoid. When the solenoid is energized, unibody core is magnetized and attracted to the soft magnetic plates from below, pulling unibody core downward. The extrusions on the two ends of unibody core actuate external mechanisms (pushers and cantilevers, respectively) to accomplish various electrical switching operations. A permanent magnet can be added to the upper side to assist the actuation. |
| US09142373B2 |
Electromagnetic relay
An electromagnetic relay has a fixed touch piece having a fixed contact, a movable touch piece having a movable contact contactably and separably opposed to the fixed contact, and configured to elastically deform, an auxiliary member configured to energize the movable touch piece to the fixed contact piece side, an electromagnet, and an intermediate member configured to be operated by magnetization of the electromagnet and elastically deform the movable touch piece. |
| US09142371B2 |
Actuator for contactor
An actuator for a contactor comprises an electromagnet having a closing coil, a holding coil, fixed cores wound with the closing coil and the holding coil respectively, a movable core provided on one side of the fixed cores, and a yoke. A main contact movable member operates to perform closing or interrupting by attraction or release of the movable core with respect to the fixed core. The actuator has a trip spring, energy-stored during the closing, that performs the interrupting upon stopping energization to the holding coil and thereby releasing the stored-energy. The actuator has an auxiliary contact operating with the operation of the movable core and performing energization switching with respect to the closing coil and the holding coil. The trip spring is provided on one side of the electromagnet in a horizontal direction while the auxiliary contact is provided on the other side. |
| US09142368B2 |
Push switch
Provided is a push switch that can be made thin without requiring that a notch be made into a mounting board. The push switch includes a substrate having a L-shaped cross section and wherein the substrate has a front surface, a back surface and a side face, an accommodating recess provided on the front surface, a center contact provided so as to be substantially centralized in the accommodating recess, a pair of peripheral contacts each provided at a circumferential edge of the accommodating recess, a movable contact spring constructed so as to extend across the pair of peripheral contacts and designed to be brought into contact with the center contact when pressed, a connection pad provided on the back surface and electrically connected to the mounting substrate, and an electrode provided on the side face and electrically connected to the connection pad. |
| US09142366B2 |
Illumination-type push button device
An illumination-type push button device including a board for light source, a diffusing lens having a dome shape, a first light source portion and a second light source portion, and a light guide member, where the diffusing lens is configured such that light of the second light source portion enters the diffusing lens from a back surface, and is diffused from a front surface of the diffusing lens, thereby being irradiated to an outside of the device, and the light guide member is configured such that light of the first light source portion enters the light guide member from an incident surface opposed to the first light source portion on the one end side of the light guide member to be guided inside the light guide member, and exits from an outgoing surface on the other end side of the light guide member, thereby being irradiated to the outside. |
| US09142363B2 |
Method for forming a sensor electrode for a capacitive sensor device
A sensor electrode (SE) for a capacitive sensor device is designed such that the width of the sensor electrode decreases towards the center such that the capacity between the sensor electrode and an object (F) with constant distance between the sensor electrode and the object (F) substantially is equal in size for each position of the object (F) relative to the sensor electrode along a longitudinal axis of the sensor electrode. The sensor electrode may consist of a plurality of segments arranged in a strip with decreasing width towards the center of the electrode. |
| US09142361B2 |
Electric storage cell
An electric storage cell includes a film-like casing configured to house a layered charge collector and electrolyte, and an electrode terminal connected to the charge collector and exposed to an outside of the film-like casing, the electric storage cell being chargeable/dischargeable using the electrode terminal, wherein bending portions of the film-like casing are formed in parallel. |
| US09142360B2 |
Mesoporous titania bead and method for preparing the same
The present invention relates to a mesoporous titania bead and the preparation method thereof, wherein said mesoporous titania bead has a diameter of 200-1000 nm, specific surface area of 50-100 m2/g, porosity of 40-60%, pore radius of 5-20 nm, pore volume of 0.20-0.30 cm3/g, and the titania comprised in the bead is anatase titania. |
| US09142354B2 |
High energy density and low leakage electronic devices
A magnetic capacitor includes two electrode layers, an insulator layer, and one or more magnetized layers. The insulator layer is located between the first electrode layer and the second electrode layer. The one or more magnetized layers include one or more ferro-magnetic elements that are magnetized. The one or more magnetized layers are located so that the one or more ferro-magnetic elements apply a magnetic field to the insulator layer to improve an electrical property of the insulator layer. Magnetic fields applied perpendicular to the electrode layers increase the capacitance and electrical energy storage of the insulator layer. Magnetic fields applied parallel to the electrode layers decrease the leakage current and increase the breakdown voltage of the insulator layer. The one or more ferro-magnetic elements used can include ferro-magnetic plates or magnetic nanodots. The one or more magnetized layers can be located between or outside of the electrode layers. |
| US09142349B2 |
Method for achieving converter transformer for DC magnetic bias
A method for achieving converter transformer for suppressing DC bias magnet comprises increasing the seaming width of the transformer core lamination, which comprises in detail calculating the width and the height of each stage of lamination according to the reserved seaming width of the lamination, the sectional area of the core, the space between columns, and the height of the window, shearing the lamination based on the width and the height of the lamination obtained by calculating, overlapping two pieces of laminations into one piece of lamination according to the order of stages, placing them on the core frame alternately by stages, and after overlapping all the laminations, fastening each stage of lamination. |
| US09142348B2 |
Antenna with a concentrated magnetic field
An antenna with a concentrated magnetic field has a main coil and at least one pair of auxiliary coils. Each of the main coil and each auxiliary coil has at least one coil conductor. Each one of the at least one coil conductor has a virtual reference plane. The at least one pair of auxiliary coils are mounted around the main coil and an included angle is formed between the virtual reference plane of each coil conductor of each auxiliary coil and that of each coil conductor of the main coil. Lines of magnetic field generated by each coil conductor of each auxiliary coil concentrate the lines of magnetic field of the main coil to orient to a corresponding virtual reference plane of the main coil, thereby solving the magnetic leakage and EMI easily occurring outside the zone of active transmission for conventional coils using electromagnetic induction. |
| US09142346B2 |
Transformer
A transformer includes a pair of first coils and at least one second coil. The first and second coils are stacked so that the at least one second coil is interposed between the first coils in a common winding axial direction of the first and second coils. Each of the first coils is covered by insulating films and integrated with the insulating films into an integrated body, so that the first coils are electrically insulated from the at least one second coil. |
| US09142345B2 |
Bent conduction sheet member, covering member and conductive winding assembly combining same
A conductive winding assembly combining a bent conduction sheet member and a covering member is provided. The bent conduction sheet member has a channel. The covering member includes a connection part, a first lateral plate, a second lateral plate, and a hollow part. A first groove is arranged between the first lateral plate and the connection part. A second groove is arranged between the second lateral plate and the connection part. The bent conduction sheet member is inserted into the covering member through the first groove and the second groove, and the connection part is inserted into the channel. The bent conduction sheet member is partially accommodated within the hollow part, and the bent conduction sheet member is partially exposed outside the covering member through the hollow part. |
| US09142344B2 |
Electronic component
An electronic component having a laminate having a plurality of insulator layers. A coil is provided consisting of a plurality of coil conductors that are connected by via-conductors piercing through the insulator layers, the coil winding helically about an axis along a direction of lamination. External electrodes are provided on surfaces of the laminate, in which at least some pairs of the coil conductors that neighbor each other with one of the insulator layers provided therebetween have parallel sections that overlap each other when viewed in the direction of lamination. The parallel sections are connected in parallel by the via-conductors or the external electrodes, and each pair of the coil conductors that neighbor each other with one of the insulator layers provided therebetween do not overlap each other when viewed in the direction of lamination, except for the parallel sections, and connections between the coil conductors and the via-conductors. |
| US09142343B2 |
Coil component
A coil component 1 includes a substrate 2, a planar spiral conductor 10a formed on a top surface 2t of the substrate 2, a lead conductor 11a connected to an outer peripheral end of the planar spiral conductor 10a, a dummy lead conductor 15a formed on the top surface of the substrate 2 and between an outermost turn of the planar spiral conductor 10a and an end 2X2 of the substrate 2 and free from an electrical connection with another conductor within the same plane, external electrodes 26a and 26b arranged in parallel with the top surface of the substrate 2, and a bump electrode 25a formed on a surface of the lead conductor 11a and connects the lead conductor 11a with the external electrode 26a. The external terminals 26a and 26b have a larger area than the bump electrodes 15a and 15b for securing a bonding strength. |
| US09142342B2 |
Compact-area capacitive plates for use with spiral inductors having more than one turn
A method and an apparatus are described for constructing a compact inductive-capacitive circuit, using a spiral inductor of more than one turn, plus a capacitive plate. This method includes duplicating the layout of the spiral, and then offsetting the duplicate so that the trace pattern of the spiral overlaps its duplicate at an insulating distance away, with the duplicate as an underlying capacitive plate. The plate's trace pattern includes at least one gap, plus an extension of its trace to span the region under the terminals of the spiral inductor. For the case where the spiral inductor has more than one turn—plus an underpass—the capacitive plate may also have more than one turn and may also have an underpass. The resulting pair of underpasses may be either overlapping or nonoverlapping. If overlapping, the full circuit requires at least four metal layers, and at least three if the underpasses are nonoverlapping. |
| US09142339B2 |
Compact optical transconductance varistor
A compact radiation-modulated transconductance varistor device having both a radiation source and a photoconductive wide bandgap semiconductor material (PWBSM) integrally formed on a substrate so that a single interface is formed between the radiation source and PWBSM for transmitting PWBSM activation radiation directly from the radiation source to the PWBSM. |
| US09142335B2 |
Cable with offset filler
The present invention relates to cables made of twisted conductor pairs. More specifically, the present invention relates to twisted pair communication cables for high-speed data communications applications. A twisted pair including at least two conductors extends along a generally longitudinal axis, with an insulation surrounding each of the conductors. The conductors are twisted generally longitudinally along the axis. A cable includes at least two twisted pairs and a filler. At least two of the cables are positioned along generally parallel axes for at least a predefined distance. The cables are configured to efficiently and accurately propagate high-speed data signals by, among other functions, limiting at least a subset of the following: impedance deviations, signal attenuation, and alien crosstalk along the predefined distance. |
| US09142333B2 |
Differential signal transmission cable and method of making same
A differential signal transmission cable includes two core wires, and a foamed insulation that collectively covers the two core wires by foaming extrusion molding. The foamed insulation is not more than 5% in a dispersion of foaming degree defined below in a cut surface when the cable is cut orthogonally to a longitudinal direction of the cable. In the cut surface, five regions are determined according to a predetermined procedures and a foaming degree (%) of the respective regions is measured. The dispersion of the foaming degree is defined by a difference between a foaming degree (%) in the region with a maximum foaming degree and a foaming degree (%) in the region with a minimum foaming degree. |
| US09142332B2 |
Transparent conductive film
A transparent conductive film comprises: a film substrate having two main surfaces; and a transparent conductor layer formed on one main surface of the film substrate. The transparent conductor layer is composed of three layers in which a first indium tin oxide layer, a second indium tin oxide layer, and a third indium tin oxide layer are laminated in this order from the film substrate side. The first indium tin oxide layer has a smaller tin oxide content than the second indium tin oxide layer has. The third indium tin oxide layer has a smaller tin oxide content than the second indium tin oxide layer has. |
| US09142329B2 |
Transparent conductive ink compositions and the use thereof in electro-active optical systems
The present application relates generally to conductive compositions that are transparent to visible light and their use in various optical applications, such as ophthalmic products. Embodiments of the invention include transparent conductive ink compositions that comprise a conductive polymer and one or more of a lithium salt or a high boiling point solvent. Embodiments of the invention further include electro-active ophthalmic products, such as electro-active ophthalmic lenses, comprising one or more conductive structures (e.g., contacts, wires, and the like) that are at least partially composed of said transparent conductive ink compositions. |
| US09142327B2 |
Canister for transporting and/or storing radioactive materials comprising radially stacked radiological protection components
A canister for transporting/storing radioactive materials, comprising two concentric shells between which is housed a radiological protection device forming a barrier against gamma radiation, comprising a first and a second metal radiological protection components superimposed along a radial direction of the canister, the first component being supported against the outer shell and the second component being supported against the inner shell. In addition, the components are in contact with each other along an interface taking, in section along any plane integrating the longitudinal axis, the form of a straight line segment inclined in relation to this axis. |
| US09142326B2 |
Radioactive waste storage
Radioactive waste may be stored in storage containers that are suitable for long-term disposal, but do not provide adequate shielding. By assembling an overpack from metal plates, the metal plates each being substantially flat, and the overpack providing sufficient shielding for the radioactive waste, and enclosing the storage container that contains radioactive waste in the overpack, the storage container can then be stored safely in a weatherproof enclosure. The enclosure does not need to provide radiation shielding. The plates can be stored as a flat-pack, and assembled into the overpack when required. |
| US09142324B2 |
Bad block reconfiguration in nonvolatile memory
When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors. |
| US09142323B1 |
Hardware acceleration of DSP error recovery for flash memory
A method for correcting a cell voltage driftage in a NAND flash device is disclosed. An indicator indicating a cell voltage driftage in a memory unit of a NAND flash device is monitored by a processor. A cell voltage driftage in the NAND flash device is detected based at least in part on the indicator. One or more NAND commands correcting the cell voltage driftage are generated. The one or more NAND commands include a NAND command associated with changing a configuration setting of the NAND flash device. |
| US09142322B2 |
Memory manager
An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold. |
| US09142321B2 |
Testing of non-volatile memory arrays
A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for VT testing for reading at least some memory cells. A second test stage including at least one second stage read uses an adjusted step size less in magnitude than the first step size for reading at least some memory cells. Provided no bit pattern match by the second test stage and/or the adjusted step size does not meet a predetermined minimum resolution (PMR), one or more additional test stages including additional array searching are added using a fixed step size less in magnitude than the adjusted step size including at least one read until a final read determines the predetermined bit pattern is matched and a fixed step size for the final read meets the PMR. |
| US09142318B2 |
Method for controlling the breakdown of an antifuse memory cell
A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time. |
| US09142313B2 |
Memory system and programming method thereof
A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell. |
| US09142308B2 |
Semiconductor memory device, memory system including the same, and operating method thereof
Disclosed are a semiconductor memory device, a memory system including the same, and an operation method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; and a plurality of page buffers configured to supply currents to bit lines when a sensing operation is performed and sense currents of the bit lines to sense data of the plurality of memory cells and generate current paths between the bit lines and a ground according to program states of the plurality of memory cells. |
| US09142306B2 |
Selecting memory cells using source lines
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals. |
| US09142304B2 |
Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current
An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively. |
| US09142300B2 |
Memory system including nonvolatile memory
According to one embodiment, a memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a storage area having a plurality of memory cells configured to store data. The control circuit determines whether data write to the storage area is possible or impossible. |
| US09142299B2 |
Semiconductor memory device which stores plural data in a cell
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. |
| US09142296B2 |
Nonvolatile memory device and method for driving the same
A nonvolatile memory includes a memory cell array including a plurality of nonvolatile memory cells connected to bit lines and word lines crossing the bit lines, a voltage driver configured to provide a word line voltage to the word lines and provide a first voltage during a precharging operation and a second voltage during a sensing operation, based on a voltage setting signal, and a page buffer unit configured to adjust a precharging level of a sensing node connected to a bit line of a page included in a selected memory block of the memory cell array using the first voltage and adjust a sensing level of the sensing node using the second voltage. |
| US09142293B2 |
Resistance change type memory
According to one embodiment, a resistance change type memory includes a memory cell including a first resistance change element as a memory element; a reference cell including a second resistance change element and a first element having a resistance value which is not higher than a resistance range of the first and second resistance change elements; and a read circuit including a first input terminal connected to the memory cell, and a second input terminal connected to the reference cell. |
| US09142291B2 |
High voltage generating circuit for resistive memory apparatus
A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate. |
| US09142290B2 |
Nonvolatile semiconductor device and method for driving same
According to one embodiment, a nonvolatile memory device includes: a memory cell array including first wirings, second wirings, and a memory cell connected between the first wirings and the second wirings; and a control circuit unit configured to select a selected memory cell from the memory cells, perform a first operation of changing a resistance state of the selected memory cell between a first resistance state and a second resistance state, and determine whether the first operation has been properly performed or not and perform retry operation such as applying a retry pulse when the first operation has not been properly performed. The control circuit unit regards the selected memory cell as excessive retry operation and inhibits the selected memory cell in accordance with the number of times of the excessive retry operation when the number of times of the retry operation is over k times. |
| US09142289B2 |
Method for driving variable resistance element, and nonvolatile memory device
A driving method for driving a variable resistance element and a nonvolatile memory device, which achieves stable storage operation. In a low resistance write process, a low resistance writing voltage pulse having the negative polarity is applied once to a variable resistance layer included in a variable resistance element while in a high resistance write process, a high resistance writing voltage pulse having the positive polarity is applied more than twice to the same variable resistance layer. Here, when a voltage value of one of the high resistance writing voltage pulses is VH1 and a voltage value of the other high resistance writing voltage pulse applied subsequently is VH2, VH1>VH2 is satisfied. |
| US09142288B2 |
Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line. |
| US09142286B2 |
Integrated circuit memory device with read-disturb control
A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver. |
| US09142279B2 |
DRAM refresh method and system
A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times. |
| US09142278B2 |
Asymmetric write scheme for magnetic bit cell elements
A first write driver applies a first voltage above a fixed potential to a first terminal. A second write driver applies a second voltage that is higher above the fixed potential than the first voltage to a second terminal. There is at least one magnetic tunnel junction (MTJ) structure coupled at the first terminal at a first side to the first write driver and coupled at the second terminal at a second side to the second write driver. The first side of the MTJ structure receives the first voltage and the second side of the MTJ structure receives a ground voltage to change from a first state to a second state. The second side of the MTJ structure receives the second voltage and the first side of the MTJ structure receives the ground voltage to change from the second state to the first state. |
| US09142264B2 |
Techniques for refreshing a semiconductor memory device
Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region. |
| US09142263B2 |
Power management control and controlling memory refresh operations
A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by logically ORing, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation. |
| US09142261B2 |
Smart bridge for memory core
An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface. |
| US09142260B2 |
Universal disk shipper
Systems, methods, and components include an improved universal disk container for use in transporting, storing and processing data storage disks or other disk-shaped articles. A disk shipping system and method for shipping disks allows stocking a minimal number of components while still allowing packaging and shipment of different thickness of disks and different capacities of disks in a container. A universal disk cassette includes slots having a narrowed lower portion configured for handling different disks of the same diameter but different thicknesses while preventing disk to disk contact when the disks are tilted. A universal top cover is configured for cassettes loaded with different thicknesses of disks. The universal top cover can readily accommodate disks that are tilted in the cassette, and with vacuum bagging, more securely fix the disks in place in the container. |
| US09142259B2 |
Editing device, editing method, and program
Provided is an editing device including an input material timeline area display control unit that executes control such that an input material timeline in which an event is arranged is displayed, using a material which is an element of selected content as the event, and an output material timeline area display control unit that executes control such that an output material timeline in which an event which is being edited or has been edited is arranged is displayed. The input material timeline and the output material timeline have a same time axis, and the input material timeline area display control unit controls a display of the input material timeline such that the event arranged in the input material timeline is expressed by the same time axis as the event arranged in the output material timeline. |
| US09142256B2 |
Method and apparatus for creating a custom track
A method and system for creating and editing video and/or audio tracks is described. The method includes providing at least one artist, venue, and track available for selection and providing at least one clip associated with the at least one artist, venue, and track. The method also includes allowing a user to create a custom track from the at least one clip. The system includes a plurality of video cameras for recording a live performance at a plurality of positions. The system also includes at least one server for storing a plurality of video clips created from the plurality of video cameras and an application stored on the at least one server for allowing a user to access the plurality of video clips via the Internet. |
| US09142255B2 |
Method and apparatus for creating a custom track
A method and system for creating and editing video and/or audio tracks is described. The method includes providing at least one artist, venue, and track available for selection and providing at least one clip associated with the at least one artist, venue, and track. The method also includes allowing a user to create a custom track from the at least one clip. The system includes a plurality of video cameras for recording a live performance at a plurality of positions. The system also includes at least one server for storing a plurality of video clips created from the plurality of video cameras and an application stored on the at least one server for allowing a user to access the plurality of video clips via the Internet. |
| US09142250B2 |
System and method for preventing illegal copy
Disclosed herein is an illegal copy prevention system and method. In short, an anti-copy prevention system of the present invention includes, a chipless RFID disk having a print layer distributed with metal fibers; an Optical Disk Drive (ODD) reading, recorded information when mounted with the chipless RFID disk; and a reader installed in the disk drive to sense whether metal fibers distributed at the printed layer exists and a unique ID contained in the metal fiber. |
| US09142249B1 |
Disk drive using timing loop control signal for vibration compensation in servo loop
A disk drive is disclosed comprising a timing loop configured to generate a clock synchronized to a rotation of a disk and a servo loop configured to control an actuator to actuate a head over the disk. A timing signal generated by the timing loop is filtered with a pre-compensation filter (PCF) comprising an inverse transfer function from a delta in a rotation velocity of the disk (Δω) due to a vibration affecting the disk drive to the timing signal, and the actuator is controlled to actuate the head over the disk based on an output of the PCF. |
| US09142248B2 |
Motor drive device, magnetic disk storage device, and electronic device
A motor drive device has a spindle motor driver adapted to receive electric power from a power supply line to drive a spindle motor; an isolation switch adapted to connect and disconnect an application terminal of a power supply voltage to and from the power supply line, and a current monitor adapted to monitor a first current flowing into the isolation switch. The current monitor includes a mirror switch arranged to connect a first terminal of the mirror switch to the application terminal of the power supply voltage and adapted to be turned on and off by the same control signal as the isolation switch; a bias generator adapted to bias a second terminal of the mirror switch to the same voltage as the power supply line; a resistor which converts a second current flowing into the mirror switch into a first voltage; and a current limit signal generator adapted to compare at least one of the first voltage, a second voltage obtained by level-shifting the first voltage, and a third voltage obtained by dividing the first voltage with a predetermined threshold voltage to generate a current limit signal. |
| US09142247B2 |
Spindle motor with turntable fixing member
A spindle motor is disclosed, the spindle motor including a turntable coupled to the rotation shaft to rotate along with the rotation shaft and accommodating a disk, and a turntable fixing member coupled at an upper surface of the turntable to the rotation shaft to fix the turntable. |
| US09142244B2 |
Near-field transducer efficiency monitoring system
A system may have a data storage medium that contains at least one data bit that is accessed by a transducing head that has a near-field transducer. A controller can be connected to the transducing head and store a plurality of near-field transducer operating currents in a memory. The controller may identify a change in efficiency of the near-field transducer from the plurality of near-field transducer operating currents. |
| US09142233B1 |
Heat assisted magnetic recording writer having a recessed pole
A heat assisted magnetic recording (HAMR) write transducer has an air-bearing surface (ABS) configured to reside in proximity to a media during use and is coupled with a laser that provides energy. The HAMR transducer includes a main pole, at least one additional pole adjacent to the main pole in a down track direction, a waveguide and at least one coil for energizing the main pole. The main pole is configured to write to a region of the media and is recessed from the ABS by a first distance. The additional pole(s) are recessed from the ABS by a second distance greater than the first distance. The waveguide is optically coupled with the laser and directs a portion of the energy toward the ABS at an acute angle from the ABS. A portion of the waveguide resides between the additional pole(s) and the ABS. |
| US09142232B2 |
Magnetic stack with separated contacts
An apparatus for two dimensional reading may be constructed, in accordance with some embodiments, with a number of magnetic stacks respectively configured to engage adjacent data tracks of a data storage media. Each magnetic stack can be disposed between top and bottom shields while each shield is segmented into a number of contacts different than the number of magnetic stacks. |
| US09142230B2 |
Magnetic devices including low thermal conductivity portion
A device including a magnetic transducer; top and bottom magnetic shields, wherein the top and bottom magnetic shields are adjacent the magnetic transducer on opposite surfaces thereof; a heating element configured to provide heating along a heating path towards the first and second magnetic shields; and a low thermal conductivity structure, wherein at least a portion of the low thermal conductivity structure is positioned along the heating path between the heating element and the magnetic transducer. |
| US09142226B2 |
Thin film with tuned grain size
An apparatus and associated method provides a magnetic writing element that may have at least a write pole tuned to a predetermined first grain size with a cryogenic substrate temperature. A magnetic shield can be formed with a predetermined second grain size that is tuned with the cryogenic substrate temperature. |
| US09142224B2 |
Magnetic-tape drive and magnetic-tape head compatible with multiple tape formats
Embodiments of the present invention are directed to the design and implementation of backward-compatible magnetic tape drives (102) that are read/write compatible with a current magnetic-tape format (1820) as well as one or more previous magnetic-tape formats (1802 and 1804). Embodiments of the present invention include read/write tape-head configurations (1902, 1904, 1906, 1908-1923, 1930, 1932, 1934, 2102) and corresponding magnetic-tape-drive-component features (518) that allow a magnetic-tape drive to read and write magnetic tapes formatted according to different formats. |
| US09142222B2 |
Apparatus and method of enhancing quality of speech codec
An apparatus and method of improving the quality of a speech codec are provided. In the method, a first energy of a signal decoded by a low-band codec is calculated, and a second energy of a signal decoded by a low-band enhancement mode is calculated. Then, when the first energy is less than a first threshold value or less than a product of the second energy and a second threshold value, a size of the decoded signal is scaled. Accordingly, generation of a quantization error with respect to a silence segment is reduced. |
| US09142221B2 |
Noise reduction
A signal processor for estimating noise power in an audio signal includes a filter unit for generating a series of power values, each power value representing the power in the audio signal at a respective one of a plurality of frequency bands; a signal classification unit for analysing successive portions of the audio signal to assess whether each portion contains features characteristic of speech, and for classifying each portion in dependence on that analysis; a correction unit for estimating a minimum power value in a time-limited part of the audio signal, estimating the total noise power in that part of the audio signal and forming a correction factor dependent on the ratio of the minimum power value to the estimated total noise power, the correction unit being configured to estimate the minimum power value and the total noise power over only those portions of the time-limited part of the signal that are classified by the signal classification unit as being less characteristic of speech; and a noise estimation unit for estimating noise in the audio signal in dependence on the power values output by the filter unit and the correction factor formed by the correction unit. |
| US09142219B2 |
Background speech recognition assistant using speaker verification
In one embodiment, a method includes receiving an acoustic input signal at a speech recognizer. A user is identified that is speaking based on the acoustic input signal. The method then determines speaker-specific information previously stored for the user and a set of responses based on the recognized acoustic input signal and the speaker-specific information for the user. It is determined if the response should be output and the response is outputted if it is determined the response should be output. |
| US09142218B2 |
System and method for detecting synthetic speaker verification
Disclosed herein are systems, methods, and tangible computer readable-media for detecting synthetic speaker verification. The method comprises receiving a plurality of speech samples of the same word or phrase for verification, comparing each of the plurality of speech samples to each other, denying verification if the plurality of speech samples demonstrate little variance over time or are the same, and verifying the plurality of speech samples if the plurality of speech samples demonstrates sufficient variance over time. One embodiment further adds that each of the plurality of speech samples is collected at different times or in different contexts. In other embodiments, variance is based on a pre-determined threshold or the threshold for variance is adjusted based on a need for authentication certainty. In another embodiment, if the initial comparison is inconclusive, additional speech samples are received. |
| US09142214B2 |
Light socket cameras
A security system can be used to trigger appliances. The security system can comprise a light socket camera that can be rotatably attached to a light socket of a building. The light socket camera can receive an audible instruction from a user, and in response to receiving the audible instruction from the user, the security system can trigger the appliance to perform an operation. |
| US09142212B2 |
Apparatus and method for recognizing voice command
An apparatus and method for recognizing a voice command for use in an interactive voice user interface are provided. The apparatus includes a command intention belief generation unit that is configured to recognize a first voice command and that may generate one or more command intention beliefs for the first voice command. The apparatus also includes a command intention belief update unit that is configured to update each of the command intention beliefs based on a system response to the first voice command and a second voice commands. The apparatus also includes a command intention belief selection unit that is configured to select one of the updated command intention beliefs for the first voice command. The apparatus also includes an operation signal output unit that is configured to select a final command intention from the selected updated command intention belief and to output an operation signal based on the selected final command intention. |
| US09142209B2 |
Data pattern analysis
A method and apparatus receive multiple data pattern analysis requests from a controller and substantially simultaneously perform, with multiple data pattern analysis units, multiple data pattern analyses on one or more portions of a data stream. |
| US09142208B2 |
Ultrasonic probe and ultrasonic diagnostic equipment using same
An ultrasonic diagnostic equipment of the present invention includes: an ultrasonic transducer body transmitting and receiving ultrasonic waves; a swing shaft (4) attached integrally to the ultrasonic transducer body; a swing shaft pulley (5) provided on the swing shaft; a motor having an output shaft (7); an output shaft pulley (8) provided on the output shaft; a belt (9) wound around the swing shaft pulley and the output shaft pulley; a plurality of belt fixing screws (11, 12) fixing the belt to the swing shaft pulley and the output shaft pulley. The belt is divided into two regions at the belt fixing screws so as to allow the regions to have different natural frequencies.With this configuration, it is possible to provide a highly reliable ultrasonic probe and an ultrasonic diagnostic equipment using the ultrasonic probe. |
| US09142207B2 |
Oversight control of an adaptive noise canceler in a personal audio device
A personal audio device, such as a wireless telephone, includes an adaptive noise canceling (ANC) circuit that adaptively generates an anti-noise signal from a reference microphone signal and injects the anti-noise signal into the speaker or other transducer output to cause cancellation of ambient audio sounds. An error microphone is also provided proximate the speaker to measure the ambient sounds and transducer output near the transducer, thus providing an indication of the effectiveness of the noise canceling. A processing circuit uses the reference and/or error microphone, optionally along with a microphone provided for capturing near-end speech, to determine whether the ANC circuit is incorrectly adapting or may incorrectly adapt to the instant acoustic environment and/or whether the anti-noise signal may be incorrect and/or disruptive and then take action in the processing circuit to prevent or remedy such conditions. |
| US09142199B1 |
Length-adjustable strap
A length-adjustable strap has two plies joined together to form a channel therebetween. The channel generally does not extend the entire length of the strap. At least one extender slidably engages in the channel. The extender may have holes therethrough or recesses that engage elements of one or more fasteners at or near the proximal end of the strap in an adjustment region outside of the channel. Mating screws are joined to the fastener(s) to secure the extender in place. Optionally, the fastener(s) and mating screws are replaced by a tie that threads through holes formed through the first ply and optionally the second ply as well as the hole(s) formed through the extender to secure the extender in place. Multiple fastening connections more evenly distribute the load. |
| US09142196B2 |
Light box effect for viewing digital radiographic images
Devices for presentation of digital radiographic images. One device includes a memory for storing at least one radiographic image and a computer connected to the memory. The computer includes a processor and a user interface module. The user interface module is configured to generate a graphical user interface and to cause the at least one radiographic image to be displayed on a display in a first mode and in a light box mode that simulates the appearance of a physical light box. |
| US09142195B2 |
Data forwarding circuit, data forwarding method, display device, host-side device, and electronic apparatus
The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated. |
| US09142192B2 |
Simulation of web applications and secondary devices in a web browser, web application development tools, and methods using the same
Device simulators and methods for using the same are disclosed. In some embodiments, the device simulators are capable of permitting accurate pixel to pixel and inch to inch mapping between a simulated display and a display of a target device. Web application development tools utilizing such simulators are also disclosed. In some embodiment, such web application development tools provide a convenient method to convert electronic document source files to interactive document web applications for multiple operating systems and form factors. |
| US09142190B2 |
Method for compensating large view angle mura area of flat display panel
A method for compensating large view angle Mura area of a flat display, comprising the steps of: 1) providing a flat panel including a number of main pixels, and a Mura area and a normal area; 2) setting two or more than two main pixels as a set of Mura area brightness adjustment units; 3) providing a driving circuit for driving the number of main pixels within the flat panel, and the driving circuit supplying a number of gamma voltages; and 4) using the driving circuit to apply two or more than two different gamma voltages to the set of main pixels within the Mura area brightness adjustment units such that the gray scales of Mura area within a center view area and the large view angle area are closer to the gray scales of the normal area thereby achieving a uniform brightness across the flat panel. Accordingly, with the method provided, the gray scales of the central view and the large view angle of the Mura area are substantially closer to the gray scales of the normal area. The yield of the flat panel is increased, and the quality of the flat display using such a flat panel is also guaranteed. |
| US09142184B1 |
Speed function module and numerical minimization module for an active contour model
A device receives an image for an active contour model, where the active contour model includes a first module and a second module. The device receives an initial contour for the image and the active contour model, and executes a speed function of the first module, based on the image and the initial contour, to generate a speed function result. The device executes a numerical minimization method of the second module, based on the image and the speed function result, to generate a final contour, and provides the image and the final contour for display. |
| US09142182B2 |
Device and control method thereof
A device and a control method for the device are disclosed. A device and a control method for the device according to the present invention comprises a sensing unit; and a controller, if at least one of a second control command is received through the sensing unit while carrying out a control operation based on at least one of a first control command received through the sensing unit, generating a display signal based on a control command selected according to a predetermined criterion from the received multiple control commands of the first and the second control command. According to the present invention, a control command for generating a display signal can be effectively selected in the case that another control command is received while a particular control command is carried out. |
| US09142179B2 |
Display device, liquid crystal display device and electronic device including the same
A liquid crystal display device includes a pixel having a first to nth (n is a natural number of 2 or more) subpixels and a circuit. To the circuit N (N is a natural number of 2 or more) wirings for supplying a digital signal with N bits and first to nth wiring groups having M (M is a natural number of 2 or more) wirings for supplying M different voltages are electrically connected. The liquid crystal display device has a function of converting the digital signal into n analog signals by using the M voltages supplied to the first to nth wiring groups and inputting the n analog signals to first to nth subpixels. The first to nth subpixels each include an electrode for driving a liquid crystal element. |
| US09142178B2 |
Liquid crystal display device
In one embodiment, first and second driver circuits are arranged interposing a matrix of pixels. A timing control circuit is electrically connected with the first and second driver circuits. The first driver circuit including a first sequential circuit is electrically connected with the odd scanning lines, and supplies scanning signals to the odd signal lines in order. The second driver circuit including a second sequential circuit is electrically connected with the even scanning lines, and supplies the scanning signals to the even scanning lines in order. The timing control circuit generates first and second synchronization signals, and supplies the first synchronization signal to the first driver circuit and the second synchronization signal to the second driver circuit. The first and second driver circuits supply the scanning signals to the scanning lines in order for every line upon receiving the first synchronization signal and the second synchronization signal from the timing control circuit. |
| US09142176B2 |
Stereoscopic image display apparatus
A stereoscopic image display apparatus which reduces flicker and crosstalk, provides a viewing screen of high brightness without decreased resolution. The stereoscopic image display apparatus includes a liquid crystal display which has first and second image forming areas having horizontal rows of pixels, and an optical unit in which first and second polarizing areas associated with the first and second image forming areas are arranged. A right eye image is displayed on the first image forming areas and a left eye image is displayed on the second image forming areas, and these areas are alternately replaced or overwritten every time a frame is switched. Phase difference states are replaced between the first polarizing areas and the second polarizing areas of the optical unit, synchronized with replacement of the first and second image forming areas. |
| US09142175B2 |
Liquid crystal pixel correction using pixel boundary detection
A video processing circuit detects a risk boundary that is a part of a boundary between a dark pixel and a bright pixel, and is determined in accordance with the tilt azimuth of liquid crystal molecules from a boundary changed over the previous frame to the current frame and, for at least one side of dark pixels and bright pixels brought into contact with the detected risk boundary, corrects a video signal designating the application voltage of a liquid crystal element corresponding to the pixel of the frame brought into contact with the risk boundary out of a plurality of frames from the current frame to k frames (here, k is a natural number) following the current frame such that a lateral direction electric field generated between the dark pixel and the bright pixel decreases. |
| US09142173B2 |
Liquid crystal display apparatus
The liquid crystal display apparatus includes a liquid crystal modulation element including first and second electrode, a liquid crystal layer disposed between the first and second electrodes, a first alignment film disposed between the first electrode and the liquid crystal layer, and a second alignment film disposed between the second electrode and the liquid crystal layer. The apparatus further includes a controller that respectively provides first and second electric potentials to the first and second electrodes such that a sign of an electric field generated in the liquid crystal layer is cyclically inverted in a modulation operation state. The controller respectively provides third and fourth electric potentials to the first and second electrodes such that the sign of the electric field is fixed in a state other than the modulation operation state. The apparatus can avoid an influence by cumulated charged particles without adding a new member. |
| US09142172B2 |
Liquid crystal display device
An operation of floating charged particles and an operation of dispersing charged particles in a liquid crystal layer are controlled by determining strengths of electric fields to be applied to a liquid crystal element in accordance with a length of elapsed time from a point turning on the liquid crystal display device. |
| US09142169B2 |
Digital to analog converter and source driver chip thereof
A digital to analog converter for a source driver chip of a liquid crystal display device is disclosed. The digital to analog converter comprises an output terminal for outputting an output voltage, a plurality of receiving terminals for receiving a plurality of Gamma voltages, and a plurality of transmission paths comprising a plurality of first-type transistors coupled between the plurality of receiving terminals and the output terminal, respectively, for outputting one of the plurality of Gamma voltages as the output voltage according to a digital select signal; wherein a first transmission path corresponding to a first receiving terminal receiving a first Gamma voltage closest to a middle voltage among the plurality of Gamma voltages has lower on-resistance than other transmission paths among the plurality of transmission paths when a same source-to-gate voltage is applied. |
| US09142166B2 |
Liquid crystal display device and TV receiver
Provided is a liquid crystal display device capable of improving motion blur and preventing excessive current flow into a light source with a desired balance in a structure where the light intensity of a backlight device is properly changed in conjunction with the ambient illuminance. If the ambient illuminance (S1) of a liquid crystal display device is lower than a preliminarily set predetermined illuminance, a backlight scanning process (intermittent lighting process) is implemented (Yes of S2, S3), while if the ambient illuminance is not lower than the predetermined illuminance, the backlight scanning process (intermittent lighting process) is terminated (No of S2, S21). The light intensity of the backlight device is changed in conjunction with the high and low ambient illuminance by changing the drive current supplied to the light source, depending on the ambient illuminance of the liquid crystal display device and whether or not to implement the backlight scanning process (intermittent lighting process) (S4, S22). |
| US09142161B2 |
Display apparatus and a method for driving the same
In a display apparatus, selection signals are supplied sequentially to scanning lines in each subframe period including a frame period for performing a display scan to write display data to a plurality of data lines into pixel circuits in a first interval of a selection period. Selection signals are also supplied sequentially to scanning lines in at least two successive subframe periods including a frame period for performing an erase scan to write erase data to the plurality of data lines into pixel circuits in a second interval of the selection period. There is an overlapping period between two erase scan periods in the at least two successive subframe periods. During the overlapping periods, selection signals for performing the display scan and erase scan are supplied simultaneously to the scanning lines. |
| US09142159B2 |
Method for uneven light emission correction of organic EL panel and display correction circuit of organic EL panel
A correction method for correcting uneven light emission of an organic EL panel, the correction method includes the steps of: supplying a predetermined signal to the organic EL panel to detect the brightness of the panel at horizontal and vertical scan positions; forming, based on a detection output thereof, correction data adapted to correct uneven brightness of the organic EL panel at a horizontal or vertical display position of the panel; storing the correction data in a memory; and reading the correction data from the memory during viewing to correct the level of a video signal supplied to the organic EL panel. |
| US09142155B2 |
Display device, signal converter for the display device, and method of operating the display device
A display device includes a display panel including pixels for displaying four colors including a white color. The display device further includes a signal converter for generating four output signals pertaining to the four colors using three input signals pertaining to three non-white colors of the four colors. The display device further includes a signal processor for processing the output signals to generate data signals and to provide the data signals to the display panel for the pixels to display an image. The signal converter includes at least one adder and a plurality of bit shifters for calculating a white-signal candidate using signals related to the input signals. The signal converter may determine a white-related output signal of the output signals using the white-signal candidate. |
| US09142151B2 |
Robotic smart sign system and methods
Described are robotic signs comprising: a sign post; an arm movably attached to the sign post, the arm having a positioning apparatus configured to allow the arm to rotate independently and contiguously around the sign post, the arm having at least one face comprising an electronic display configured to present display items; and a communication element configured to receive display item information from a remote administration application, the display item information comprising a direction and a description; wherein upon presenting a display item, an arm rotates to indicate the direction and displays the description. Also described are software applications for configuring the robotic signs, networks of the robotic signs, and advertising systems utilizing the robotic signs. |
| US09142146B2 |
Cranial bone surrogate and methods of manufacture thereof
A surrogate multilayered material includes a first fiber reinforced layer; the first reinforced layer including a crosslinked polymer and fibers; a second fiber reinforced layer; the second reinforced layer including the crosslinked polymer and the fibers; a foam layer; the foam layer disposed between the first fiber reinforced layer and the second fiber reinforced layer; where opposite faces of the foam layer are in direct contact with the first fiber reinforced layer and the second fiber reinforced layer; the foam layer having a compressive strength of about 3.5 to about 4.5 MPa, when measured as per ASTM-D-1621-73, and a shear strength of 1.50 to about 2.15 MPa, when measured as per ASTM-C-273. |
| US09142143B2 |
Tactile graphic display
A tactile graphic display for providing a display representation of a graph or image generated by a graphic device for visually impaired users or other users who wish to access tactile information. The tactile graphic display includes a control and interface module in communication with a dot matrix, which is associated with pin nut assemblies including caps that serve as dots in the dot matrix. The control and interface module provides motor drive signals that raise selected dots above the top surface of a top panel to form the dot matrix display. Proximity sensors in or associated with the top panel sense touching of one or more dots and/or proximate presence of a finger or hand near the top surface of the top panel. The proximity sensors provide dot matrix engagement signals to the control and interface module for processing. |
| US09142140B2 |
Muscle memory training device
A muscle memory training device for attaching to a joint of a user, such as, for example, a wrist joint. The training device includes a pair of opposing circuit boards for overlying first and second elements of the joint. The pair of circuit boards are pivotally connected with a pivot point configured to be placed over the joint. The circuit boards include individual contact traces which are configured and arranged such that when said traces are rotated past each other, the traces sequentially complete one of a sequence of circuits, providing a signal at each one of a plurality of contact positions depending on opposing circuit board rotation positions. In this manner, sensory input is provided to a user while practicing a movement. |
| US09142137B1 |
System and method for deriving questions, answers and grammars from texts and summarizing textual information
A system and computer-implemented method that includes analyzing content of textual information, automatically deriving a plurality of questions from the analyzed content, presenting the plurality of questions derived, to a user via a user interface, determining, via the user, a validity of the plurality of questions, and generating at least one valid question as determined by a user along with a corresponding answer to at least one valid question. The method further includes generating a summary of the textual information using the answers generated. The method further includes the ability of generate grammars for parsing natural language phrases. |
| US09142136B2 |
Systems and methods for a logging and printing function of an online proctoring interface
An online test platform facilitates automatic scrolling of test materials in a web browser while maintaining a text prompt associated with the test materials. The platform also facilitates development, delivery, and management of educational tests with interactive participation by students, teachers, proctors, and administrators even when some or all of them are remotely located. The platform may include administrator interfaces, test proctor interfaces, and test taker (e.g. student) interfaces to allow each participant to view, navigate, and interact with aspects of the online test platform that are intended to meet their needs. |
| US09142133B2 |
System and method for maintaining aircraft separation based on distance or time
A system and method are provided for displaying an enhanced longitudinal scale providing user interface and awareness for executing the Next Gen Flight Deck Interval Management (FIM) and the Cockpit Display of Traffic Information (CDTI) application Enhanced Visual Separation on Approach (VSA) to provide a required spacing between aircraft based on distance and time. An own-ship and a reference aircraft are displayed in relation to a desired flight path. A symbol indicates the desired separation of the own-ship from the aircraft. |
| US09142124B2 |
Vehicle-mounted communication device and navigation device equipped with this vehicle-mounted communication device, communication device for pedestrians and navigation device equipped with this communication device for pedestrians, and pedestrian-to-vehicle communication system
Disclosed is a vehicle-mounted communication device that carries out radio communications with a communication device for pedestrians which is carried by a pedestrian, the vehicle-mounted communication device including: a receiver that receives pedestrian information showing whether the pedestrian belongs to a pedestrian group formed of the pedestrian and a plurality of pedestrians in the vicinity of the pedestrian from the communication device for pedestrians; a controller that judges the pedestrian information received by the receiver and issues a command to present pedestrian attention information when the pedestrian information shows that the pedestrian does not belong to a pedestrian group; and an information outputter that presents the pedestrian attention information according to the command from the controller. Therefore, the vehicle-mounted communication device enables the driver to certainly recognize the existence of a pedestrian not belonging to a pedestrian group. |
| US09142119B1 |
Audio monitoring and sound identification process for remote alarms
In a computer-implemented method for remote monitoring of one or more alarms, a set of one or more audio test signals is sensed. The set of audio test signals is processed to generate alarm identification data, and/or the set of audio test signals is recorded, and an indication of a type of the alarm device and/or a location of the alarm device, is received. An audio signal generated by the alarm device in response to detecting an alarm condition is sensed, and processed using an audio recognition technique to identify the alarm device. The alarm device is identified using the generated alarm identification data and/or the recorded set of audio test signals, and using the received indication. A user is caused to be notified that the identified alarm device has been triggered. |
| US09142118B2 |
Emergency notification device and system
An audio warning monitoring device, system and method including an audio detector, one or more audio screens to determine if monitored sound is an alarm, a processor or logic device to potentially analyze sound data and then instruct a transmitter to send a message with the monitoring device identification and signals representing sound detected by the audio detector to a server. The computer server analyzes the message and authenticates the audio detector, looks up user data associated with the detector, and contacts a user from previously stored user data in order to notify of the alert and then relay the audio signals in an audio file. At the user's option, the server may contact a staffed or automated monitoring center. Here a human operator may listen to the signals in the audio file and take appropriate action, such as calling the location of the alarm for verification or contacting a professional first responder(s). |
| US09142113B2 |
Smoke detector with external sampling volume using two different wavelengths and ambient light detection for measurement correction
In accordance with certain embodiments, a smoke detector determines the presence of smoke particles outside its housing based on measurements of light detected at different wavelengths and corrected based on an ambient light level. |
| US09142111B2 |
Flare network monitorng system and method
A flare monitoring system that receives real-time data associated with the release of a processing facility's combustible fluids to a flare stack and analyzes the data in conjunction with parameters of the processing facility's flare-through elements such as manual valves, control valves, restriction orifices, flow meters, and the like. The results of the analysis are provided to operators in the form of reports that indicate: whether flaring events are of a routine or non-routine nature; the flared volume; the contribution of the flare-through elements to the flared volume; and so forth. The results can aid operators in reducing combustible fluid losses due to flaring and in mitigating emissions of sulfur, nitrogen and carbon dioxide. |
| US09142108B2 |
Security apparatus and method
A security method and apparatus is disclosed. In one embodiment, a security method comprises storing one or more data points representing an alarm condition in a memory, generating an electronic signal from a motion sensor in response to movement of the door or window, comparing the electronic signal to the data points, and detecting an alarm condition of the door or window if the electronic signal substantially matches the data points. |
| US09142107B2 |
Wireless tracking and monitoring electronic seal
An electronic security seal (e-Seal) is disclosed. The e-Seal monitors security of shipments including intermodal containers, reports tampers in real-time, monitors environmental status of goods and reports exceptions in real-time, and reports the location of the shipment with high frequency. The security monitoring complies with the ISO 17712 standard, adding electronic real-time reporting of tamper time and location and LED tamper indication. The e-Seal can be manufactured and operated at low cost due to diagnostic and logistic features. The e-Seal supports low cost upgrades due to a modular architecture allowing a plug-in update of separate functions. The e-Seal allows flexible usage across supply chain tradelanes, due to highly programmable operation including over-the-air remote programming via wireless communications. The e-Seal provides low power operation to save battery usage and lower costs. |
| US09142106B2 |
Tailgating detection
Methods, systems, and computer-readable media for tailgating detection are described herein. One method includes collecting, via a computing device, access log data associated with a profile; processing, by a processor coupled to the computing device, the access log data to obtain a statistical access model; detecting, by the processor, a tailgating sequence based on the statistical access model; and providing, by the processor, a notification that the tailgating sequence has occurred. |
| US09142104B2 |
Haptic information presentation system and method
A system and method are disclosed in which in a conventional non-grounding man-machine interface having no reaction base on the human body and for giving the existence of a virtual object and the impact force of a collision to a person, a haptic sensation of a torque, a force and the like can be continuously presented in the same direction, which cannot be presented by only the physical characteristic of a haptic sensation presentation device. In a haptic presentation device, the rotation velocity of at least one rotator in the haptic presentation device is controlled by a control device, and a vibration, a force or a torque as the physical characteristic is controlled, so that the user is made to conceive various haptic information of the vibration, force, torque or the like. |
| US09142102B2 |
Method and apparatus for visualizing network security alerts
A method and apparatus can be configured to perform the steps of displaying, on a display, a first visual representation of volume in three-dimensional space. The method can also display, on the display, a visual representation of a network security alert. The network security alert can correspond to a notification of a network attack, a network intrusion, or an unwanted activity. The representation of the network security alert can be positioned within the first visual representation of volume. The position of the representation of the network security alert within the first visual representation of volume reflects at least one characteristic of the network security alert. |
| US09142101B2 |
Automated teller machine with EPP guard cave
The present invention relates to an automated teller machine having an EPP guard cave formed therein. More particularly, the present invention relates to an automated teller machine having an EPP guard cave formed therein, in which the EPP guard cave is recessively formed on the front surface of the automated teller machine toward the inside thereof and an encrypting pin pad (EPP) is installed inside the EPP guard cave formed as such, so that a user may conveniently use the automated teller machine without anxiety by effectively preventing the procedure of inputting personal information by the user from being exposed to surroundings or other people through a concaved structure without a separate structure such as an EPP guard plate since the user may put a hand into the EPP guard cave and input the personal information through the EPP when the user inputs the personal information through the EPP for a banking transaction. |
| US09142099B2 |
Method of gaming, a gaming system and a game controller
A method of gaming comprising: selecting a set of symbols for display to a player in a set of display positions corresponding to respective ones of a plurality of reels; determining a game round outcome based on the selected symbols; determining that a feature game round should occur; and determining a feature game round outcome by determining an optimal winning combination of symbols from a feature subset of the set of symbols comprising more symbols than the number of reels. |
| US09142098B2 |
Managing cashless wagering game systems
This document discusses, among other things, systems and methods for managing of cashless wagering game systems. An apparatus comprises a control module to debit, via a first system access technique, a debit amount from a first cashless wagering system in a financial transaction and credit, via a second system access technique different from the first system access technique, a credit amount to a second cashless wagering system in the same financial transaction, the first and second cashless wagering game systems being different from one another coupled over a network. |
| US09142096B2 |
Methods and devices for authentication and licensing in a gaming network
Methods and devices are provided for managing licenses in gaming networks. Some aspects of the invention are provided as a license manager module that operates as part of a server-based system for provisioning and configuring gaming machines. Security and authentication techniques are provided to prevent unauthorized gaming software usage. Such gaming software may be, for example, downloaded to gaming machines in the network under the control of a gaming establishment's game management server that is in communication with a license manager device. In preferred implementations, a gaming machine is prevented from executing software for a game of chance unless the license for that game is valid and has not expired. |
| US09142094B2 |
Gaming system and method providing a group bonus event for liked gaming devices
A gaming system and method provides a competitive group bonus event for a plurality of players playing at linked gaming devices. Upon activation of the group bonus event, a first one of the players playing at one of the gaming devices can challenge one or more other players to participate in the group bonus event. Players who accept the challenge agree to compete for one or more awards associated with the group bonus event. The players play the primary games of their respective gaming devices independently of the group bonus event. The first player to trigger a bonus game on his or her gaming device wins the group bonus event and is provided with an award. The winner of the group bonus event additionally has the opportunity to play the triggered bonus game. |
| US09142093B2 |
Gaming system having re-awarding of stored awards
A gaming system for conducting a wagering game includes a wager input device for receiving a wager to play a wagering game, at least one display for displaying the wagering game, and at least one controller. The controller is operative to display a first outcome of the wagering game and award a first award associated with the first outcome, store the first award in a stored awards group, cause the at least one display to display the stored awards group, and re-award one or more awards in the stored awards group upon the occurrence of a triggering event. |
| US09142092B2 |
Gaming system with casino chip tracking
A gaming system includes: an IC chip reader configured to read chip identification information which uniquely identifies a specific casino chip; journal data generation unit configured to generate journal data corresponding to a transaction of the chip operated during the reading, based on the chip identification information; a journal data DB configured to accumulate the journal data and capable of generating, based on accrual accounting, balance sheet data to be reflected onto a balance sheet in real time by using data indicating a financial condition and a profit-or-loss condition of a casino, based on the accumulated journal data; and a controller configured to control a process of a game and issue an instruction to a dealer based on the data read by the IC chip reader. |
| US09142089B2 |
Gaming system having wagering features funded by extra-casino activities
A method of funding features of a wagering game, comprises receiving a first sum of money generated from extra-casino activity associated with at least one person and depositing the first sum into a feature fund. The method further comprises allocating the first sum to at least one account of the feature fund in accordance with a first rule set. The method further comprises, in response to a triggering event, withdrawing a second sum of money from the at least one account. The method further comprises funding at least one feature associated with the wagering game from the second sum of money and activating the funded feature. |
| US09142088B2 |
Gaming system, gaming devices, and method for providing an enhanced multiple-player bonus redemption game
A gaming system and methods provide a plurality of gaming devices configured to operate a multiple-player bonus or secondary game. Each gaming device of the gaming system generates targets upon occurrences of target-generation events. Each gaming device also generates collectors upon occurrences of collector-generating events. The collectors may be used in conjunction with the aforementioned targets to obtain awards in a bonus sequence as described. Upon the occurrence of a redemption event at one of the plurality of gaming devices, the gaming device provides all players playing at one of the gaming devices in the gaming system the opportunity to redeem all accumulated collectors and targets in a bonus sequence. In the bonus sequence, the gaming system determines any awards associated with the redemption of accumulated collectors and targets and provides them to the players. |
| US09142086B2 |
Method and system for enabling gaming via a mobile device
A method and system for enabling gaming via a mobile device are provided. A request is received from the mobile device to participate in gaming. Primary location information determined by the mobile device for the location of the mobile device is received with the request. The primary location information is verified with secondary location information for the geolocation of the mobile device determined using a location system external to said mobile device. Participation of the mobile device in a game is enabled if the primary location information is verified and if the mobile device at the location identified by the primary location information is eligible for the game. |
| US09142084B2 |
Wager recognition system
A gaming table apparatus has a gaming table with a gaming table support surface. At least two token sensors are provided, which are electrically connected in series to a token sensor controller. The at least two token sensor units are physically restrained by the table support surface. The game controller is in communication with the token sensor controller, wherein the game controller is configured to associate player position data with transmitted wager data received from the token sensor controller. |
| US09142077B2 |
Sheet processing apparatus and sheet processing method
According to one embodiment, a sheet processing apparatus includes a feeding unit including a support surface inclined with respect to a vertical direction and a stacking surface substantially perpendicular to the support surface, a plurality of paper sheets being stacked on the stacking surface in such a manner that the paper sheets are inclined along the support surface, a pick up mechanism configured to pick up the paper sheets from a side of the stacking surface of the feeding unit, a conveying path configured to convey the picked up paper sheets, an inspection device configured to inspect the conveyed paper sheet, and an accumulation unit configured to accumulate the inspected paper sheets. |
| US09142075B1 |
Apparatus and system for imaging currency bills and financial documents and method for using the same
A batch of bills is received, transported, and imaged to produce image data. The image data is reproducible as a visually readable image of at least a portion of each of the plurality of currency bills. Each currency bill includes a respective serial number. The serial numbers are extracted from the image data for each of the currency bills. Each extracted serial number is compared with a plurality of serial numbers in a currency bill database to determine if a currency bill associated with an extracted serial number is a suspect currency bill. One of the plurality of currency bills is determined to be a suspect currency bill based on the comparing. In response to determining the suspect currency bill, at least a portion of the produced image data is displayed as a visually readable image of the suspect currency bill on a display unit of the document processing system. |
| US09142074B2 |
System for and method of paper note authentication and tracking through NFC
A system for and method of paper note authentication and tracking through NFC is presented. The system and method includes utilizing an authenticating device to receive paper note data using an NFC reader, transmit the paper note data to an authenticating party, receive an authentication determination and/or additional paper note data, and authenticate the paper note where the authentication determination indicates accordingly. The system and method may further include updating the paper note data upon authentication to prevent duplicate authentication attempts. |
| US09142072B2 |
Information shared between a vehicle and user devices
Methods and systems for a vehicle system that include configuring a vehicle based upon information from devices accessed by a user. The vehicle system may include a vehicle and a configuration unit. The information may be based on a search performed by a user. The information accessed or generated by the user may be automatically sent to the vehicle for configuration of the vehicle. |
| US09142066B2 |
Multi-stage diagnostic system and method
A multi-stage diagnostic system and related method which seeks diagnostic information from a secondary information source when a first information source does not yield sufficient data for producing a diagnostic result. In particular, diagnostic process includes a first stage of communicating with an onboard vehicle computer to retrieve diagnostic trouble codes therefrom. If no diagnostic trouble codes are retrieved from the onboard computer, the diagnostic process proceeds to a second stage wherein symptomatic diagnostic information is solicited from the user. A series of symptomatic questions may be presented to the user on a smartphone. The answers from the symptomatic questions may be used to identify a most likely solution, which may be associated with a repair part(s). The corresponding repair part(s) may be identified by an associated universal part number(s) based on vehicle identification information associated with the vehicle needing repair. |
| US09142063B2 |
Positioning system utilizing enhanced perception-based localization
A positioning system and method for determining a position of a machine on a worksite are disclosed. The method may store a map of the worksite which includes one or more known objects in the worksite. The method may determine whether a locating device associated with the machine is accurately providing the position of the machine. The method may also include detecting one or more objects in the worksite. The method may further determine an unmatched object from among the detected objects that does not match the one or more known objects stored in the map. The method may also store the unmatched object in the map as a known object of the worksite. |
| US09142057B2 |
Processing unit with a plurality of shader engines
A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (L1) data cache, coupled to and positioned between the first and second shader engines. |
| US09142053B2 |
Systems and methods for compositing a display image from display planes using enhanced bit-level block transfer hardware
Systems and methods for compositing an image from display planes are disclosed. An internal matrix having transparency data indicating transparency of a macro block of a digital representation of a display is accessed. An external matrix is accessed if the internal matrix indicates the macro block includes a transparent and opaque pixel, wherein the external matrix has transparency data indicating transparency of each pixel in the macro block. A first display plane is read based on the transparency data indicating opaque pixels and the first display plane data is sent to a first buffer. Second display plane data of a second display plane is read and sent to a second buffer if the transparency data indicates transparent pixels. Control data is inserted into the first buffer accordingly such that an image is generated based on at least one of the first and second display plane data and the control data. |
| US09142050B2 |
Effective arrangement of data elements
A plurality of data elements are analyzed, in one or more computers, to optimize an arrangement of slices in a pie chart, wherein a value for each of the data elements represents an area of a corresponding one of the slices in the pie chart, and the data elements are ordered by their values, so that labels and lines on placed on the pie chart without overlap. |
| US09142049B2 |
Proactive monitoring tree providing distribution stream chart with branch overlay
The disclosed embodiments relate to a system that displays performance data for a computing environment. During operation, the system first determines values for a performance metric for a plurality of entities that comprise the computing environment. Next, the system displays the computing environment as a set of nodes representing the plurality of entities. While displaying the nodes, the system displays a chart with a line illustrating how a value of the performance metric for the selected node varies over time, wherein the line is displayed against a background illustrating how a distribution of the performance metric for a reference subset of the set of nodes varies over time. |
| US09142048B2 |
System and method for placing cluster groupers in a visual display
A system and method for placing cluster groupers in a visual display is provided. Groupers of document clusters are obtained. One of the groupers is placed into a center of a display. A further grouper is selected, and a size of the further grouper is determined. An angle for placement of the further grouper and a radius from the center of the display for placement of the further grouper are also determined based on the grouper size to minimize overlap with the placed grouper. The further grouper is positioned in the display in relation to the grouper based on the determined angle and radius. |
| US09142042B2 |
Methods and systems to produce continuous trajectories from discrete anatomical shapes
A method of estimating changes in an anatomical structure over time. The method includes steps of obtaining a plurality of shapes of an anatomical structure from a plurality of points in time, wherein the plurality of shapes of the anatomical structure includes a baseline shape of the anatomical structure; continuously deforming the baseline shape of the anatomical structure using a growth model parameterized by acceleration; fitting the deformed baseline shape to at least one of the plurality of shapes of the anatomical structure; and using the deformed baseline shape to estimate at least one shape of the anatomical structure at a time corresponding to a time that is different than any of the plurality of points in time. |
| US09142039B2 |
Method and apparatus for improving speed of rasterizing transparent images
A method for improving a speed of rasterizing transparent images, comprising determining, from P graphic entity objects on a transparent page, M transparent images and N nontransparent images. Each of the N nontransparent images includes an intersecting area with one of the M transparent images, P is an integer larger than 0, M is an integer larger than 0 and smaller than or equal to P, N is an integer larger than or equal to 0 and smaller than P, and P=M+N. The method also comprises determining a page-level transparent area and a page-level de-transparentizing area of the P graphic entity objects. Contributions of the transparent images and the nontransparent images to the page-level transparent area and the page-level de-transparentizing area are calculated using different methods. The methods further comprises assembling the M transparent images according to the page-level transparent area and the page-level de-transparentizing area. |
| US09142038B2 |
Rendering a digital element
Rendering a digital element is disclosed. An indication that a device is within a region associated with the digital element is received. It is determined that the digital element is to be rendered. A representation of the digital element is generated in a rendered view of the region. The digital element is provided upon receiving an indication that the digital element has been selected. |
| US09142037B2 |
Methods of and apparatus for encoding and decoding data
When encoding a set of texture data elements 30 for use in a graphics processing system, the direction along which the data values of the set of texture data elements in question exhibit the greatest variance in the color space is estimated by using one or more infinite planes 41 to divide the texture data elements in the color space. For each such plane, texture data element values on each side of the plane are added up to give respective sum points 48, 49, and the vector 50 between these two sum points determined. The direction in the data space of one of the determined vectors 50 is then used to derive endpoint color values to use when encoding the set of texture data elements. |
| US09142035B1 |
Item dimension verification at packing
This disclosure describes systems and methods for automatically verifying stored item dimension values and package utilization at packing. In some implementations, an image(s) of a package that includes items of a shipment set is captured at a pack station and analyzed to determine an actual package utilization. The actual package utilization is compared to an expected package utilization. If a difference between the expected package utilization and the actual package utilization is identified, it may be determined that the stored item dimension values may be inaccurate. |
| US09142034B2 |
Center of mass state vector for analyzing user motion in 3D images
Techniques described herein determine a center of mass state vector based on a body model. The body model may be formed by analyzing a depth image of a user who is performing some motion. The center of mass state vector may include, for example, center-of-mass position, center-of-mass velocity, center-of-mass acceleration, orientation, angular velocity, angular acceleration, inertia tensor, and angular momentum. A center of mass state vector may be determined for an individual body part or for the body as a whole. The center of mass state vector(s) may be used to analyze the user's motion. |
| US09142030B2 |
Systems, methods and computer readable storage media storing instructions for automatically segmenting images of a region of interest
Systems, methods, and computer-readable storage media relate to segmenting an image series of at least one image of a region of interest of a subject. The methods, systems, and computer readable storage media can automatically segment interior and exterior boundaries relative to the region of interest (e.g., epicardial and endocardial boundaries with respect to a right ventricle) from an image series by combining sparse matrix transform, a training model, and a localized region based level set function. |
| US09142028B2 |
Image analysis for making animal measurements
A computer-implemented image analysis process, including: accessing image data representing an image including an animal object representing an animal; selecting one more start points on a boundary of the animal object using an intensity gradient of the image; and generating boundary data, representing at least a portion of the boundary, starting at each of the selected one or more start points, using the intensity gradient. |
| US09142026B2 |
Confidence map, method for generating the same and method for refining a disparity map
A method for generating a confidence map comprising a plurality of confidence values, each being assigned to a respective disparity value in a disparity map assigned to at least two stereo images each having a plurality of pixels, wherein a single confidence value is determined for each disparity value, and wherein for determination of the confidence value at least a first confidence value based on a match quality between a pixel or a group of pixels in the first stereo image and a corresponding pixel or a corresponding group of pixels in the second stereo image and a second confidence value based on a consistency of the corresponding disparity estimates is taken into account. |
| US09142024B2 |
Visual and physical motion sensing for three-dimensional motion capture
A system includes a visual data collector for collecting visual information from an image of one or more features of an object. The system also includes a physical data collector for collecting sensor information provided by at one or more sensors attached to the object. The system also includes a computer system that includes a motion data combiner for combining the visual information the sensor information. The motion data combiner is configured to determine the position of a representation of one or more of the feature in a virtual representation of the object from the combined visual information and sensor information. Various types of virtual representations may be provided from the combined information, for example, one or more poses (e.g., position and orientation) of the object may be represented. |
| US09142018B2 |
Method for three-dimensional localization of an object from a two-dimensional medical image
A method for determining the three-dimensional location of an object in real-time from a two-dimensional medical image obtained with a medical imaging system is provided. For example, the three-dimensional location of an interventional medical device or a marker positioned on such a device may be determined from a two-dimensional x-ray image obtained with an interventional x-ray imaging system. Template images corresponding to the object under different imaging geometries and orientations are produced and are compared to images acquired with the medical imaging system. Similarity measures, such as normalized cross correlation and normalized similarity integral, are used to determine the similarity between a selected template image and the medical images in different stages of refining the position information for the object. |
| US09142016B2 |
Methods for image processing
An image processing method includes: obtaining an image that includes a ball image and a cone image; obtaining an estimate of a center of the ball image; converting the image to a converted image using a processor based at least in part on the estimate of the center of the ball image, wherein the converted image comprises a converted ball image that looks different from the ball image in the image, and a converted cone image that looks different from the cone image in the image; identifying the converted ball image in the converted image; and analyzing the converted ball image to determine a score that represents an accuracy of the estimate of the center of the ball image. |
| US09142012B2 |
Systems and methods for chroma noise reduction
Systems and methods for reducing chrominance (chroma) noise in image data are provided. In one example of such a method, image data in YCC format may be received into logic of an image signal processor. Using the logic, noise may be filtered from a first chrominance component or a second chrominance component, or both, of the image data, using a sparse filter and a noise threshold. The noise threshold may be determined based at least in part on two of the components of the YCC image data. |
| US09142010B2 |
Image enhancement based on combining images from multiple cameras
Provided are systems and methods for image enhancement based on combining multiple related images, such as images of the same object taken from different imaging angles. This approach allows simulating images captured from longer distances using telephoto lenses. Initial images may be captured using simple cameras equipped with shorter focal length lenses, typically used on camera phones, tablets, and laptops. The initial images may be taken using two different cameras positioned a certain distance from each other. An object or, more specifically, a center line of the object is identified in each image. The object is typically present in the foreground portion of the initial images. The initial images may be cross-faded along the object center line to yield a combined image. Separating of the foreground and background portions of each image may be separated and separately processed, such as blurring the background portion and sharpening the foreground portion. |
| US09142002B2 |
FPGA packet processing engine
A graphic processor device is implemented on a field programmable gate array (“FPGA”) circuitry comprises a pipeline formatter that sets graphic commands and vertex data into structures, and a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein output of the rasterizer is a stream of fragments that become pixels. The graphic processor device further includes a frame buffer that receives a stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer, and an output processor configured to retrieve a plurality of fragments from the frame buffer and transmits a plurality of pixels according to a predefined resolution. |
| US09142001B2 |
Performance allocation method and apparatus
In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit. |
| US09141996B2 |
Dynamic auto insurance policy quote creation based on tracked user data
A system and method may create auto insurance quotes using data collected from a device that tracks vehicle usage data and other data. Usage data may be tracked by an On Board Diagnostic (OBD) device or other portable computing device such as a smart phone. Based on a received coverage type, the usage data and other data may be analyzed to determine auto insurance quotes. A potential customer may then purchase an auto insurance policy. Once the purchased policy has been determined to have expired, new usage data will be collected, and new quotes will be created for the customer. |
| US09141992B2 |
Data feed acceleration
The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields. |
| US09141987B2 |
System, method, and medium for generating a map of a geographic region based on client location data
Described herein are technologies pertaining to presenting a map to a user that comprises graphical icons that are representative of retail stores. The user has provided a shopping list, wherein the shopping list includes a plurality of products that are desirably purchased by the user. Inventories of retail stores in a geographic region of interest to the user are searched, and a map is generated that includes graphical icons representative of the retail stores, data that indicates that product(s) in the shopping list are available at the retail stores, and price data that indicates prices of product(s) in the shopping list at the respective retail stores. |
| US09141982B2 |
Method and apparatus for collaborative upload of content
A collaborative cloud DVR system (ccDVR), which includes a cloud storage system and a plurality of participating DVR client devices, acts collaboratively as a single communal entity in which community members authorize each other to upload, remotely store and download licensed content for time shifted viewing, in a manner which rigorously protects legal rights of the content owners while overcoming the potential physical obstacles of limited bandwidth, power failures, incomplete uploads/downloads of content, limited cloud storage capacity, etc. The collaborative cloud DVR community collaboratively shares bandwidth and cloud storage capacity among DVR viewer/users with each owner/user of a DVR client device authorizing his or her individual DVR client device to be utilized by a cloud storage system server and any other owner/user of a DVR client device in the respective service community, and receiving similar permission in return to promote the convenience of cloud storage in an authorized manner. |
| US09141981B2 |
Method, system, and computer program product for long-term on-line comparison shopping
A method, system, and computer-program product for automatically monitoring websites (e.g., web-based shopping sites, catalogs, auction sites, etc.) for acquisition parameters (e.g., prices, rental amounts, trading/barter requirements, etc.) on one or more commodities, for a predetermined time period. |
| US09141979B1 |
Virtual stand-in computing service for production computing service
Provided are methods of providing a virtual service that may provide partial real time service to clients of a production computing service that is unavailable. Methods may include generating, based on transaction data corresponding to a production computing service that is available, a production computing service model that includes multiple request types and multiple confidence values that correspond to ones of the request types. Methods may include responding to a request received from a client of the production computing service with a model-generated response to the request in response to the production computing service being unavailable. The production computing service is updated with the request received from the client and the model-generated response responsive to the production computing service being available after being unavailable. |
| US09141975B2 |
Inferring user risk profile from travel patterns
A method for estimating a risk profile of a user of a personal digital assistant (PDA) includes collecting, using the PDA, data indicative of a travel pattern of the user of the PDA. The risk profile of the user of the PDA is inferred from the travel pattern. The risk profile to is output an external system, so as to enable the external system to provide to the user a commercial offer based on a risk level which is indicated by the risk profile. |
| US09141972B2 |
Peer-to-peer access of personalized profiles using content intermediary
A method for personalizing content for a particular user in a computing system comprising a user interface configured to display content. The method comprises identifying a content item accessed by a user, identifying features associated with the content item; using the features of the content item to identify one or more third party profiles that substantially match a content profile of the content item, and displaying a list of the identified third party profiles. |
| US09141971B2 |
Method for performing real-time click fraud detection, prevention and reporting for online advertising
The present invention provides a method of detecting fraudulent clicks in an online environment to reduce fraudulent paid clicks for online advertisers. The method includes server side and client side code which combined enables a click verification web site to identify valid and invalid clicks and in real-time prevents advertisers from getting billed for fraudulent activity. |
| US09141965B2 |
Database usage trends based on database lock requests
An enterprise locking service coordinates multiple cooperating applications to ensure that one and only one user is modifying a database record at a given time. The database records may be stored in multiple databases having potentially different database record locking protocols. Through monitoring and tracking requests for database locks, the enterprise locking service is also able to determine database usage trends under various metrics. |
| US09141963B2 |
System and method for providing advertisement to wireless network service user
Provided are a system and method for providing a wireless network service to a user terminal free of charge, by providing a doorway page for exposing an advertisement on the user terminal provided with the wireless network service through an access point. Accordingly, the user terminal may be provided with the wireless network service free of charge, other than the cost of viewing the advertisement exposed on the doorway page. An advertiser and a proprietor may expose the advertisement at the cost of providing the free wireless network service. |
| US09141961B2 |
Management of dynamic mobile coupons
Providing for network-based management of dynamic mobile coupons (DMCs) employed in mobile device-related commerce is described herein. Management can include mitigating processing load involved in processing dynamic characteristics of a set of DMCs, facilitating post-transaction evaluation of DMCs, or facilitating a virtual shopping experience in conjunction with redeeming DMCs in a mobile-commerce environment. Communicative association between a mobile device and network components can be implemented to leverage data collected by the mobile device with communication and processing capabilities of the network. Dynamic DMC states are determined from the collected data, which are implemented to facilitate the mobile-commerce. The disclosure provides an integrated mechanism for efficient utilization of DMCs to enhance user experience and satisfaction with mobile commerce. |
| US09141952B2 |
EGM authentication mechanism using multiple key pairs at the bios with PKI
Executable applications on a gaming machine are verified before they can be executed, for security purposes and to comply with jurisdictional requirements. Unlike in prior systems for authenticating the executable applications, embodiments allow for new executable applications to be provided and verified over time with different private and public key pairs, even after the operating code of the gaming machine is certified by the jurisdiction and deployed in the field. |
| US09141948B2 |
Control system arrangements and methods for disparate network systems
Electronic transaction data sets are processed for a multitude of disparate transactions using a plurality of autonomous payment networks. Consistent with one example system, a software-programmed computer type system receives and processes point-of-sale transaction data to select one of the payment networks associated with a participant ID (e.g., for a buyer or seller) in the transaction data. The system includes a plurality of network-specific interface modules, each associated with a specific payment network for interfacing therewith. For point-of-sale transaction data, the interface module corresponding to the selected payment network communicates payment data to the selected payment network to effect electronic payment for the point-of-sale transaction data. |
| US09141946B2 |
Dynamic payment service
Systems and methods may provide for implementing a dynamic payment service. In one example, the method may generate a request communication including purchase detail information relating to an item to request credit from a vendor to conduct a transaction relating to the item, determine a scope of credit to be issued to conduct the transaction relating to the item based on the purchase detail information, and generate a payment communication including the transaction information to complete the transaction relating to the item. |
| US09141942B2 |
Event scheduler based on real-time analytics and business rules
Scheduling a given event, in one aspect, may include obtaining a set of one or more business rules, obtaining analytics, and obtaining an event specification. The event specification may include at least one content specification and two or more transmission modes. The event may be scheduled based on the event specification, the analytics and the business rules. The scheduling may be indicated by a tuple comprising event content, one or more communication modes selected from the two or more transmission modes, and timing of the scheduled event. |
| US09141941B2 |
Information processing apparatus and method
A computer determines whether destination information is included in permission target information. The destination information indicates a destination to which a file stored in a storage device is transferred. The permission target information includes information indicating a target permitted to access the file. The computer prompts before the file is transferred, upon determining that the destination information is not included in the permission target information, a user to input whether to permit the transfer. The computer adds the destination information to the permission target information upon receiving, via an input device, a permission input for permitting the transfer. The computer transfers the file upon receiving the permission input. |
| US09141940B2 |
Checking electronic messages for compliance with user intent
Intention data is used to determine an intent of a sender of a message, or other participant, in an electronic communication system such as an email system. For example, a message that is designated for sending can be compared to the sender's intention data and if a discrepancy or deficiency is detected between the sender's determined intent and the actual message then an action is taken such as providing an alert to the sender or to another person, process or device; requiring an action by the sender such as confirming the message, making an edit, checking information, etc. |
| US09141935B2 |
Service operation data processing using checklist functionality in association with inspected items
In one embodiment, a system is provided for performing at least one service operation in association with at least one inspected item. The system includes a service data device configured for displaying at least one data screen including at least one checklist configured for operative use in connection with performance of the service operation on the inspected item, the data device being portable and being configured for processing at least one communication; a service administrator having at least one data storage medium configured for storing at least one of the checklists displayed on the data device, the service administrator further having at least one server for enabling at least one communication between the service administrator and the data device; at least a portion of at least one of the checklists being customizable by at least the service administrator; and, at least a portion of at least one of the checklists being electronically interactive in association with performance of the service operation on the inspected item. |
| US09141926B2 |
Smart mobile application development platform
A method includes receiving user input defining a workflow comprising one or more activities and one or more rules; receiving user input defining a user interface (UI) configured to facilitate a user performing the workflow at least in part using a processor of a mobile device; and generating a mobile software application based on the workflow and the UI. In another embodiment, a method includes: instantiating a mobile application on a mobile device; launching a workflow within the mobile application, the workflow comprising one or more activities and one or more rules; rendering one or more user interfaces based at least in part on the workflow; displaying at least one of the user interfaces on a display of the mobile device; receiving user input via at least one of the user interfaces; and modifying the workflow based at least partially on user input. Systems and computer program products are also disclosed. |
| US09141925B2 |
System and method for creating building information modeling geometry breakdown structure
Disclosed herein is a system and method for generating a BIM geometry breakdown structure. The system includes a geometry breakdown system (GBS) range setting module, a GBS geometric object coding module, and a GBS geometric object coding module. The GBS range setting module sets the range of a GBS based on BIM framework variables. The GBS element definition module generates “standard information breakdown property information” that is used to manage work-type breakdown and location breakdown, “project numbering system (PNS) property information” that is used to manage a work breakdown system (WBS), a cost breakdown structure (CBS), and a standard-method-of-measurement (SMM) breakdown structure (MBS), and “GBS property information” that is used to define geometric information. The GBS geometric object coding module matches geometric objects to the “standard information breakdown property information” and the “PNS property information”, and assigns numbers corresponding to the “GBS property information” to the matched geometric objects. |
| US09141924B2 |
Generating recommendations for staffing a project team
A processor-implemented method, system, and/or computer program product generates a recommendation for a worker to be included in a project team. A requisite skill set that is not presently needed, but will be needed in the future, by a project team is determined. Historical data that describe antecedent conditions, which caused a historical worker to obtain the requisite skill set, is received. A candidate worker's current skill set data is adjusted with skill set enhancers, which are available to members of the project team, to generate a predicted future skill set of the candidate worker. In response to the needed requisite skill set matching the predicted future skill set of the candidate worker, a recommendation is generated for adding that candidate worker to the project team. |
| US09141923B2 |
Optimizing contractual management of the total output of a fleet of fuel cells
A fuel cell fleet has a plurality of fuel cell systems each connected to a data server. The data server may be configured to obtain operational data from of the plurality of fuel cell systems. An efficiency controller operably connected to the data server and is configured to predict an efficiency and a power output of the fleet from the operational data and optimize the efficiency of the fleet to minimize the fleet fuel consumption while maintaining a desired fleet output power. The efficiency may be determined by a ratio of the fleet output current or output power to the fleet fuel consumption. |
| US09141920B2 |
Project modeling using iterative variable defect forecasts
Project modeling is conducted using variable defect arrival rate or variable defect rate density parameters. These defect rates may be updated on an iteration by iteration basis and may be used to provide remediation and further project modeling, remediation, and prediction. |
| US09141918B2 |
User contribution based mapping system and method
A computer-implemented user contribution method is provided. The method includes retrieving event data posted by a plurality of users related to a first user, the event data including indications of at least one geographic area. The event data is compared with predetermined trigger data. A quality value of the at least one geographic area is determined based on the comparison of the event data with predetermined trigger data, and an indication of the quality value of the at least one geographic area is transmitted to a second user. A user contribution based mapping system is further provided. |
| US09141917B2 |
Computing system operating environments
Techniques for optimizing an operation environment include receiving, from a first computing system, an optimization task at a second computing system; processing the optimization task in an initial optimization environment to obtain one or more initial optimization results; for each of the one or more initial optimization results, generating an optimization data record that comprises the optimization task, the initial optimization environment, and the initial optimization result; for each of the optimization data records: varying one or more parameters of the initial optimization environment to generate an updated optimization environment; processing the optimization task in the updated optimization environment to obtain an updated optimization result; storing the initial optimization results and updated optimization results in a repository that is part of or communicably coupled to the second computing system; and sorting the stored optimization results to determine one or more best optimization results of the stored optimization results. |
| US09141915B2 |
Method and apparatus for deriving diagnostic data about a technical system
A method and apparatus for deriving diagnostic data about a technical system utilizing learning metrics gained by at least one data driven learning process while generating and updating soft sensor models of said technical system. |
| US09141911B2 |
Apparatus and method for automated data selection in model identification and adaptation in multivariable process control
A computer-based apparatus and method for automated data screening and selection in model identification and model adaptation in multivariable process control is disclosed. Data sample status information, PID control loop associations and internally built MISO (Multi-input, Single-output) predictive models are employed to automatically screen individual time-series of data, and based on various criteria bad data is automatically identified and marked for removal. The resulting plant step test/operational data is also repaired by interpolated replacement values substituted for certain removed bad data that satisfy some conditions. Computer implemented data point interconnection and adjustment techniques are provided to guarantee smooth/continuous replacement values. |
| US09141908B1 |
Dynamic information assembly for designated purpose based on suitability reasoning over metadata
A reasoning system is configured to interact with data processing elements of an information processing system. The reasoning system includes a reasoning module configured to perform one or more reasoning operations on metadata. The metadata characterizes data sets associated with the data processing elements in order to identify at least selected portions of one or more of the data sets as being suitable for use in achieving a designated purpose. The reasoning system also includes a dynamic information assembly module configured to utilize results of the one or more reasoning operations to assemble at least a subset of the selected portions so as to achieve the designated purpose. The reasoning system and associated data processing elements may be implemented, by way of example, in cloud infrastructure of a cloud service provider, or on another type of processing platform. |
| US09141906B2 |
Scoring concept terms using a deep network
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scoring concept terms using a deep network. One of the methods includes receiving an input comprising a plurality of features of a resource, wherein each feature is a value of a respective attribute of the resource; processing each of the features using a respective embedding function to generate one or more numeric values; processing the numeric values to generate an alternative representation of the features of the resource, wherein processing the floating point values comprises applying one or more non-linear transformations to the floating point values; and processing the alternative representation of the input to generate a respective relevance score for each concept term in a pre-determined set of concept terms, wherein each of the respective relevance scores measures a predicted relevance of the corresponding concept term to the resource. |
| US09141903B2 |
Indicating ultrasonic data tag movement
Indicating a movement of an ultrasonic tag is accomplished by a transducer operable to provide electrical signals caused by the movement. The movement can cause mechanical vibrations, sound vibrations, or pressure in the transducer, to generate the electrical signals. A controller can detect the electrical signal from the transducer generated by the movement, whereupon the controller obtains tag data and modulates the tag data to be supplied to a powered up emitter. The emitter transmits the modulated tag data in a transmission to an ultrasonic tag reader using an ultrasonic carrier sound wave. |
| US09141902B2 |
Smart card module for a smart card
A smart card module for a smart card, comprising a chip having electrical contacts at a front side; a first laminate layer, wherein a rear side of the chip is connected to the first laminate layer, the rear side of the chip opposite the front side; a second laminate layer; a first conductive layer, wherein the electrical contacts of the chip are connected to the first conductive layer and the first conductive layer is arranged between the chip and the second laminate layer; and an adhesive material arranged between the chip and the conductive layer and/or the second laminate layer. |
| US09141900B2 |
Progressive barcode
A method and apparatus for encoding, in a simultaneous multiple security application, independently encrypted security data elements within a single matrix of blocks in a progressive barcode. The method and apparatus including, encoding information of a first data element within the matrix using black modules and, encoding information of a second data element within the matrix using color modules. The barcode being configured to be overprinted as it progresses through progressive states. The progressive barcode, resulting from the overprinting through the progressive states, masking the ability to conclusively determine the barcode in a previous state. |
| US09141899B2 |
Two-dimensional identification pattern, article including such a pattern, and methods for marking and identifying such a pattern
A method for marking an article with an identification pattern which may include information relating to the article and/or to the use thereof, the method including: defining an alphabet of a plurality of symbols; defining, for each symbol, at least two valid states and at least one invalid state; developing a reference pattern including a set of symbols from the alphabet; developing at least one representation of the reference pattern by allocating a specific valid state to each symbol of the reference pattern; and applying a marking, reproducing the representation of the reference pattern, onto the article. |
| US09141897B2 |
Image forming apparatus and method of controlling same
A signal generation portion of an image forming apparatus generates a different level of signal according to an output value of a pyroelectric sensor. A recognition portion determines a measurement value on the speed of change of the signal and recognizes which of a first range and a second range the measurement value is. In a power supply portion, when the measurement value falls within the first range in a mode other than a power-saving mode, and the image forming apparatus is brought into the power-saving mode, and, when the measurement value falls within the second range in the power-saving mode, the power-saving mode is cancelled. |
| US09141896B2 |
Apparatus, job management method, and storage medium storing program for notifying processing result of a job
If the processing result of the job which has not been notified is stored in the memory when a state of the apparatus has transited from a state incapable of communication with the job management apparatus to a state capable of communication in accordance with a user instruction, the processing result is read out from the memory and is notified to the job management apparatus. |
| US09141895B2 |
Information processing apparatus, data editing method, and computer program product
An information processing apparatus includes a first controller, a data editor, and a second controller. The first controller is configured to display a data editable preview window based on job data created from input data and receive data editing operation through the preview window. The data editor is configured to edit the job data in accordance with the data editing operation received through the preview window. The second controller is configured to transmit, to an output device, output data converted from the edited job data and request the output device to execute job processing. |
| US09141890B2 |
Data processing apparatus, data processing method, data processing program for implementing the method, and image processing apparatus
A data processing apparatus that enables a client to identify services which can be provided under a current status of the data processing apparatus by reflecting dynamically changing status information, such as equipment information, in a WSDL file. An equipment information acquisition device 1211 acquires status information relating to the status of an image processing apparatus 100. A WSDL generator 1212 generates service description information containing information pertaining to at least one service provided by the image processing apparatus 100 and described in a predetermined language, in accordance with the status information acquired by the equipment information acquisition device 1211. The service description information is referred to by a host computer 200 to use the at least one service. A Web server 1213 transmits the service description information generated by the WSDL generator 1212 to the host computer 200. |
| US09141888B2 |
Method and apparatus for generating labels
A method including selecting a type of label to be printed, inputting information for the label to be printed, wherein the information includes label data defining content of an image to be printed, and parameter data defining at least one parameter of the label to be printed, saving the information for the label to be printed as a file in a memory, and providing the file with a file extension name indicative of the type of label. |
| US09141884B2 |
Method of automatic management of images in a collection of images and corresponding device
The present invention relates to the field of management of image data in data storage. In particular, the present invention relates to a method and device for automatic detection of duplicate images in data storage and corresponding device while taking into account user perception of what he considers to be duplicate images, which method and device are particularly efficient with regard to the personalized, automatic management of large amounts of image data. |
| US09141882B1 |
Clustering of text units using dimensionality reduction of multi-dimensional arrays
Methods, systems, and apparatuses, including computer programs encoded on computer-readable media, for tokenizing n-grams from a plurality of text units. A multi-dimensional array is created having a plurality of dimensions based upon the plurality of text units and the n-grams from the plurality of text units. The multi-dimensional array is normalized and the dimensionality of the multi-dimensional array is reduced. The reduced dimensionality multi-dimensional array is clustered to generate a plurality of clusters that each cluster includes one or more of the plurality of text units. |
| US09141878B2 |
Detecting facial similarity based on human perception of facial similarity
Similar faces may be determined within images based on human perception of facial similarity. The user may provide an image including a query face to which the user wishes to find faces that are similar. Similar faces may be determined based on similarity information. Similarity information may be generated from information related to a human perception of facial similarity. Images that include faces determined to be similar, based on the similarity information, may be provided to the user as search result images. The user then may provide feedback to indicate the user's perception of similarity between the query face and the search result images. |
| US09141874B2 |
Feature extraction and use with a probability density function (PDF) divergence metric
An image of real world is processed to identify blocks as candidates to be recognized. Each block is subdivided into sub-blocks, and each sub-block is traversed to obtain counts, in a group for each sub-block. Each count in the group is either of presence of transitions between intensity values of pixels or of absence of transition between intensity values of pixels. Hence, each pixel in a sub-block contributes to at least one of the counts in each group. The counts in a group for a sub-block are normalized, based at least on a total number of pixels in the sub-block. Vector(s) for each sub-block including such normalized counts may be compared with multiple predetermined vectors of corresponding symbols in a set, using any metric of divergence between probability density functions (e.g. Jensen-Shannon divergence metric). Whichever symbol has a predetermined vector that most closely matches the vector(s) is identified and stored. |
| US09141873B2 |
Apparatus for measuring three-dimensional position, method thereof, and program
An information processing apparatus includes an input unit configured to input a plurality of images captured from a plurality of viewpoints, an extraction unit configured to extract a region of an object from each of the plurality of images, an acquisition unit configured to obtain a contour from the region of the object, a smoothing unit configured to perform smoothing of the contour based on a point group on the obtained contour, a correlation unit configured to correlate regions of the object extracted from respective ones of the plurality of images, and a calculation unit configured to calculate a position of the object based on information of regions correlated by the correlation unit and the point group obtained by the smoothing unit. |
| US09141872B2 |
Automated and scalable object and feature extraction from imagery
Feature extraction of image data using feature extraction modules. The feature extraction modules may be provided in an architecture that allows for modular, decoupled generation and/or operation of the feature extraction modules to generate feature data corresponding to image data. In this regard, the feature extraction modules may communicate with a file system storing image data and feature data by way of a common interface format. Accordingly, regardless of the nature of the execution of the feature extraction module, each feature extraction module may be communicative by way of the common interface format, thereby providing a modular approach that is highly scalable, flexible, and adaptive. |
| US09141871B2 |
Systems, methods, and software implementing affine-invariant feature detection implementing iterative searching of an affine space
Feature-matching methods for attempting to match visual features in one image with visual features in another image. Feature-matching methods disclosed progressively sample the affine spaces of the images for visual features, starting with a course sampling and iteratively increasing the density of sampling. Once a predetermined threshold number of unambiguous matches has been satisfied, the iterative sampling and matching can be stopped. The iterative sampling and matching methodology is especially, but not exclusively, suited for use in fully affine invariant feature matching applicants and can be particularly computationally efficient for comparing images that have large differences in observational parameters, such as scale, tilt, object-plane rotation, and image-plane rotation. The feature-matching methods disclosed can be useful in object/scene recognition applications. The disclosed methods can be implemented in software and various object/scene recognition systems. |
| US09141870B2 |
Three-dimensional object detection device and three-dimensional object detection method
A three-dimensional object detection device includes an image capturing unit, an image conversion unit, a three-dimensional object detection unit, a three-dimensional object assessment unit and a control unit. The image conversion unit converts images obtained by the image capturing unit to create bird's-eye view images. The three-dimensional object detection unit detects a presence of a three-dimensional object within a detection area based on differential waveform information or edge information. The stationary three-dimensional object assessment unit assesses whether the detected three-dimensional object is a shadow of a tree along a road traveled by the host vehicle. The three-dimensional object assessment unit assesses whether the three-dimensional object detected is a vehicle within the detection area. The control unit suppresses the assessment that the three-dimensional object is a vehicle when the detected three-dimensional object was determined to be a shadow of a tree along the road traveled by the host vehicle. |
| US09141869B2 |
Method of identifying anomalies in images
A method of identifying anomalies in images produced using an imaging device (70). The method comprises receiving (10), (12) first and second pluralities of candidate anomalies, the candidate anomalies being identified in subsequent images produced with an imaging device. A constellation match (14), (16), (18), (19) is carried out between the first and second pluralities of candidate anomalies to identify a correlation therebetween, represented by a constellation match value. A plurality of constellation match values is determined with a different relative x-y shift between the first and second pluralities of candidate images. If a good correlation is found at a particular x-y shift then the candidate anomalies are common between the first and second images, which is indicative of the first and second images including anomalies. |
| US09141866B2 |
Summarizing salient events in unmanned aerial videos
A method for summarizing image content from video images received from a moving camera includes detecting foreground objects in the images, determining moving objects of interest from the foreground objects, tracking the moving objects, rating movements of the tracked objects, and generating a list of highly rated segments within the video images based on the ratings. |
| US09141864B2 |
Remote gaze control system and method
The present invention provides techniques for directing the gaze of a subject whose image is captured by a camera, including the direction in which the subject looks, or the distance between the subject and the camera, in such a way that a visually appealing image can be captured by the camera, where a media professional (e.g., an interviewer or a director) or other person knowledgeable in media best practices is non co-located with the subject. The techniques enable the media professional to provide visual hints both manually and automatically to the remotely located subject. |
| US09141863B2 |
Managed biometric-based notification system and method
A managed biometric-based notification system and method is provided. The system includes at least one image acquiring system adapted to capture a first content comprising a feature set, a comparison module including at least one processor, at least one database comprising a second content, the second content comprising a feature set, at least one search engine operatively coupled with the at least one image acquiring system and the at least one database, a memory, the at least one processor operatively coupled with the at least one image acquiring system and the at least one search engine, programmed to execute a series of instructions, stored on the memory, to process the feature set of the first content and a feature set of the second content, at least one notification component including at least one transmitted data point, a content management module, and at least one pre-selected receiving node. |
| US09141860B2 |
Method and system for segmenting and transmitting on-demand live-action video in real-time
A method and system for producing video-segments of a live-action event involving monitoring a live-action event for detection of event-segments, detecting one or more event-triggers with detectors, determining if an event-segment occurred based on the detected event-triggers, and editing one or more video feeds into a video-segment to encompass the event-segment. |
| US09141859B2 |
Method and system for segmenting and transmitting on-demand live-action video in real-time
A method and system for producing video-segments of a live-action event involving monitoring a live-action event for detection of event-segments, detecting one or more event-triggers with detectors, determining if an event-segment occurred based on the detected event-triggers, and editing one or more video feeds into a video-segment to encompass the event-segment. |
| US09141856B2 |
Clothing image analysis apparatus, method, and integrated circuit for image event evaluation
In an image evaluation apparatus, a clothing recognition unit performs, for each person appearing in each of images included in an image group generated by an image group generation unit, recognition of clothing that the person is wearing. An image event evaluation unit, according to types of clothing recognized by the clothing recognition unit and a frequency of appearance of each type of clothing in the images in the image group, collectively evaluates the images included in the image group. |
| US09141850B2 |
Electronic device and photo management method thereof
A photo management method implemented by an electronic device having a first camera and a second camera includes capturing a first photo by the first camera and capturing a simultaneous second photo by the second camera of the face of a user. Facial characteristics are extracted from the second photo and the characteristics are added to attribute information of the first photo. When the user wants to browse photos showing or including himself/herself, a third photo of the user is captured and facial characteristics extracted. One or more first photos are determined according to the facial characteristics of the third photo, and the one or more first photos showing or including the user are collected in one group and displayed. |
| US09141849B2 |
Monitoring apparatus, method, and program
A suspicious person determination unit determines whether the face image of a matching target person is registered in a biological information DB by a matching result of a matching unit. When the face image of the matching target person is registered, area storage stores a specified area while correlating the specified area with a personal ID. A provisional registration unit makes a provisional registration of a suspicious person flag while correlating the suspicious person flag with the personal ID when a pattern of the specified area is a behavioral pattern of a suspicious person. A definitive registration unit makes a definitive registration of the suspicious person flag while correlating with the personal ID, when the provisional registration of the suspicious person flag is made for the face image of the matching target person, and when the face image of the matching target person is captured at a premium exchange counter. |
| US09141837B2 |
RFID skier monitoring systems and methods
A system and method monitor skier behavior. An identifier is read from a lift access product when the lift access product is in the vicinity of a lift boarding area and a scan record containing the identifier, location information of the lift boarding area and a time stamp if generated. The scan record is processed to generate a location event record that is stored within a location database. The location database is processed to determine skier behavior based upon the location event records. |
| US09141832B2 |
Multiway lossless power combining and outphasing incorporating transmission lines
A power combining and outphasing system and related techniques for simultaneously providing both wide-bandwidth linear amplification and high average efficiency is described. Providing linear amplification encompasses the ability to dynamically control an RF output power level over a wide range while still operating over a wide frequency bandwidth. The system and techniques described herein also operate to maintain high efficiency across a wide range of output power levels, such that a high average efficiency can be achieved for highly modulated output waveforms. |
| US09141831B2 |
Scheduler, security context cache, packet processor, and authentication, encryption modules
An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed. |
| US09141829B2 |
Secure processor and a program for a secure processor
The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. |
| US09141828B2 |
Mobile device management apparatus and method based on security policies and management server for mobile device management
A mobile device management apparatus has a policy storage unit that receives a plurality of security policies, which are classified into a plurality of profiles assigned priorities of activation and in which operating states of functions of a mobile device are defined. A management server supplies the profiles and the security policies to the mobile device. A policy implementation unit selectively activates the profiles so that control of the mobile device functions can be carried out with minimal communication, and also in response to changing events. |
| US09141820B2 |
Network-based service content protection
Network-based service content protection techniques are described. In one or more implementations, content is edited locally by a computing device. The edited content is automatically encrypted without any user intervention by the computing device using an encryption credential, e.g., encryption key or other secret. The automatic encryption is performed responsive to a request to store the content at a network-based service provider such that the encrypted content can only be decrypted and accessed with the encryption credential and the encrypted content is uploaded to the network-based service provider. |
| US09141800B2 |
Method and apparatus for detecting intrusions in a computer system
The present invention provides a method and apparatus for detecting intrusions in a processor-based system. One embodiment of the method includes calculating a first checksum from first bits representative of instructions in a block of a program concurrently with executing the instructions. This embodiment of the method also includes issuing a security exception in response to determining that the first checksum differs from a second checksum calculated prior to execution of the block using second bits representative of instructions in the block when the second checksum is calculated. |
| US09141797B1 |
Detection of fake antivirus in computers
Detection of fake antivirus includes classifying text content of a user interface of an application program and scanning files associated with the application program for suspicious code. The user interface may be a graphical user interface (GUI) window of the application program. The text content may be obtained from a painted portion of the GUI window and by intercepting text changing operations performed on the GUI window. The text content may be input to a learning model to determine whether or not the application program belongs to the antivirus category. The application program is deemed to be fake antivirus when the application program is classified as belonging to the antivirus category and has a file with suspicious code. |
| US09141796B2 |
System and method for detecting malware in file based on genetic map of file
A method for detecting whether a file includes malware is performed on a device. The method includes extracting information of at least two predetermined items in the file; creating a genetic map for the file by altering the extracted information into a previously set format; comparing the created genetic map with a previously stored malware genetic map to obtain a similarity between the created genetic map and the previously stored malware genetic map; and determining that the file is a malware when the similarity is higher than a reference value. |
| US09141793B2 |
Method for securing a microprocessor, corresponding computer program and device
A method is provided for securing a microprocessor containing at least one main program, which operates with at least one memory. The method includes implementing counter-measures, during which additional operations, that are not required for the main program, are implemented so as to modify the consumption of current and/or the processing time of the microprocessor. The method also includes: identification of at least one address or one memory zone of the memory(ies), called critical addresses, and which contain, or which may contain, critical data for said main program; monitoring the addressing ports of the memory(ies), so as to detect the access to the critical address(es); and activation of the step of implementing counter-measures, when an access to the critical address(es) is detected. |
| US09141789B1 |
Mitigating denial of service attacks
Several methods are disclosed for detecting and mitigating Distributed Denial-of-Service (DDoS) attacks that are intended to exhaust network resources. The methods use DDoS mitigation devices to detect DDoS attacks using operationally based thresholds. The methods also keep track of ongoing attacks, have an understanding of “protected IP space,” and activate appropriate mitigation tactics based on the severity of the attack and the capabilities of the DDoS mitigation devices. |
| US09141788B2 |
Software self-checking systems and methods
Software self-checking mechanisms are described for improving software tamper resistance and/or reliability. Redundant tests are performed to detect modifications to a program while it is running. Modifications are recorded or reported. Embodiments of the software self-checking mechanisms can be implemented such that they are relatively stealthy and robust, and so that it they are compatible with copy-specific static watermarking and other tamper-resistance techniques. |
| US09141786B2 |
Malicious mobile code runtime monitoring system and methods
Protection systems and methods provide for protecting one or more personal computers (“PCs”) and/or other intermittently or persistently network accessible devices or processes from undesirable or otherwise malicious operations of Java TN applets, ActiveX™ controls, JavaScript™ scripts, Visual Basic scripts, add-ins, downloaded/uploaded programs or other “Downloadables” or “mobile code” in whole or part. A protection engine embodiment provides for monitoring information received, determining whether received information does or is likely to include executable code, and if so, causes mobile protection code (MPC) to be transferred to and rendered operable within a destination device of the received information. An MPC embodiment further provides, within a Downloadable-destination, for initiating the Downloadable, enabling malicious Downloadable operation attempts to be received by the MPC, and causing (predetermined) corresponding operations to be executed in response to the attempts. |
| US09141785B2 |
Techniques for providing tenant based storage security and service level assurance in cloud storage environment
Techniques for tenant-bases storage security and service level assurances in a cloud environment are presented. A Tenant Storage Machine (TSM) for each tenant uses a unique identifier. The TSM is dynamically allocated with operating system resources to run processes based on agreed service level assurances. The service level assurances are stored in a Service Level Assurance (SLA) policy store. The TSM communicates with the SLA policy store via a TSM bus to acquire a SLA policy configured for the tenant and based on which resources are dynamically allocated. Processes running under the TSM run with root privileges to provide security. |
| US09141783B2 |
Systems, methods and apparatuses for the application-specific identification of devices
The systems, methods and apparatuses described herein provide a computing environment that manages application specific identification of devices. An apparatus according to the present disclosure may comprise a non-volatile storage storing identifier (ID) base data and a processor. The processor may be configured to validate a certificate of an application being executed on the apparatus. The certificate may contain a code signer ID for a code signer of the application. The processor may further be configured to receive a request for a unique ID of the application, generate the unique ID from the code signer ID and the ID base data and return the generated unique ID. |
| US09141782B2 |
Authentication using a wireless mobile communication device
An authentication scheme may be used to decide whether to permit access to a user account access to which is controlled by a network resource server. An initial portion of a password is received at a mobile communication device, and a remaining portion of the password is received at a password client installed in or otherwise coupled to the network resource server. The initial portion is communicated from the mobile communication device to the network resource server, where it is passed to the password client, which combines it and the remaining portion to produce a complete password. A value calculated by the password client from the complete password is sent to a password server, which generated the password and sent the initial portion and remaining portion. If the value matches a value calculated by the password server from the complete password in the same manner, authentication has succeeded. |
| US09141781B2 |
Card device
According to one embodiment, a card device includes an authentication unit, a wireless communication unit, and a control unit. The authentication unit performs an authentication process with an external device via wired communication. The wireless communication unit performs wireless communication with the external device. The control unit controls the wireless communication unit to reduce radio waves radiated from the wireless communication unit when the control unit detects that the authentication process is being performed. |
| US09141780B2 |
Method and system for authenticating communication
Embodiments of the present disclosure provide a method and system for authenticating communication between a plurality of accessory devices or services and one or more media devices by using a single authentication processor. The method includes the steps of establishing a communication of a media device attached to an accessory device with an authentication processor through an authentication processor manager, authenticating the accessory device by the media device based on a digital certificate and a digital signature; and authenticating the media device by the accessory device based on verification of the digital certificate and the digital signature. |
| US09141778B2 |
Controlling access to an accessible object with an online access control list
Software on a router receives configuration data that specifies a social networking service as a source for authentication according to an authentication protocol. Subsequently, the router software receives packet data from a client device for a destination other than the social networking service. The router software causes software on the client device to display a login view for the social networking service. The router software transmits the login data entered in the login view to the social networking service. And the router software receives an authorization code following a successful login by a user identified on an access control list (ACL). Then the router software transmits the packet data to the destination. |
| US09141775B2 |
Mashup service support method and apparatus
A mashup service support method includes externally receiving a mashup service application, acquiring and managing an authentication key corresponding to the received mashup service application, and executing the received mashup service application using the acquired authentication key. A user can use a variety of web services by normally operating a mashup service application through Open API due to the storing and managing of an authentication key. |
| US09141774B2 |
Method and system for controlling access to applications on mobile terminal
Various embodiments provide methods and systems for controlling an access to applications on a mobile terminal. In an exemplary method, an opened application can be scanned and an application identification can be obtained. The application identification can be compared with a pre-stored target application identification. When the application identification is compared to be consistent with the pre-stored target application identification, an unlock interface can be displayed. An unlock command can be obtained to run the application on the mobile terminal. An exemplary system for controlling an access to an application on a mobile terminal can include a scanning module, a comparing module, a displaying module, and an executing module. |
| US09141773B2 |
Zone migration in network access
The present disclosure is directed to providing a network user the ability to travel between different zones or locations within a network environment, such as, for example, a hospitality location, without requiring a user to re-login to the new location, while requiring a user to re-login to other locations within the network environment. |
| US09141770B1 |
Entitlement transfer during a repair activity
Embodiments of the present invention disclose a method, computer program product, and system for managing activation keys associated with a computing system. In one embodiment, in accordance with the present invention, the computer implemented method includes the steps of detecting a repair activity on a computing system, determining whether at least one system identifier (ID) associated with a component of the computing system has changed in comparison to system IDs associated with components of the computing system before the detected repair activity, responsive to determining that at least one system ID associated with a component of the computing system has changed, retrieving one or more activation keys that correspond to the determined at least one system ID, and determining whether the one or more retrieved activation keys are associated with a system ID that does not match any system ID associated with a component of the computing system. |
| US09141769B1 |
Secure transfer and use of secret material in a shared environment
Aspects related to the secure transfer and use of secret material are described. In one embodiment, public vendor and provider keys are provided to a customer and encrypted secret material is received in return. The encrypted secret material may include a customer secret material encrypted by the public vendor and provider keys. The encrypted secret material is imported into a trusted execution environment and decrypted with private provider and vendor keys. In this manner, a provider of cryptographic processes is not exposed to the secret material of the customer, as the customer secret material is decrypted and stored within the trusted execution environment but is not accessed by the provider in an unencrypted form. In turn, the provider may receive various instructions to perform cryptographic operations on behalf of the customer, and those instructions may be performed by the trusted execution environment. |
| US09141768B2 |
Terminal and control method thereof
A mobile terminal includes a display unit for displaying an electronic book, a user interface for selecting a specific portion to be extracted from the electronic book, a controller for extracting the selected specific portion and copyright information related to the extracted specific portion, and a memory for storing the extracted specific portion and the copyright information. The controller applies the extracted specific portion to an application such that the specific portion is displayed within the application and the copyright information is displayed on the display unit when the specific portion is applied to the application. When the extracted specific portion is applied to the application, the copyright information is automatically included in the applied specific portion. The display unit of the mobile terminal includes an electronic paper display and a liquid crystal display (LCD) and the electronic book is displayed on the electronic paper display. |
| US09141765B2 |
Distribution of infusion pumps
Some embodiments described herein provide for a number of portable infusion pumps to be distributed to a pump user via a pharmacy system or like. |
| US09141763B2 |
Method and system for patient-specific computational modeling and simulation for coupled hemodynamic analysis of cerebral vessels
A method and system for patient-specific computational modeling and simulation for coupled hemodynamic analysis of cerebral vessels is disclosed. An anatomical model of a cerebral vessel is extracted from 3D medical image data. The anatomical model of the cerebral vessel includes an inner wall and an outer wall of the cerebral vessel. Blood flow in the cerebral vessel and deformation of the cerebral vessel wall are simulated using coupled computational fluid dynamics (CFD) and computational solid mechanics (CSM) simulations based on the anatomical model of the cerebral vessel. |
| US09141760B2 |
System and method for selection of stored dialysis therapy prescriptions
In an embodiment, an automated peritoneal dialysis (“APD”) machine includes at least one pump, a logic implementer storing a plurality of therapy prescriptions by which to operate the at least one pump, each therapy prescription pre-approved for a particular patient, and an input device operating with the logic implementer to allow the patient to select one of the therapy prescriptions for a particular therapy. In another embodiment, the input device operating with the logic implementer allows a doctor/clinician to select or approve one of the therapy prescriptions to be run on the APD machine. In a further embodiment, the logic implementer is programmed to select or suggest one of the therapy prescriptions to be run on the APD machine. |
| US09141759B2 |
Group performance monitoring system and method
The present invention provides group performance monitoring systems and methods. In one exemplary embodiment, a group monitoring device includes a display configured to display, during an athletic activity, a plurality of individual performance metrics relating to a plurality of individuals engaged in the athletic activity, each individual performance metric relating to one of the plurality of individuals; and an input to manipulate the display. |
| US09141754B2 |
Generating a semiconductor component layout
A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further comprises selecting a layout generation configuration for generating the layout of semiconductor components. The method additionally comprises generating the layout of semiconductor components based on the selected layout generation configuration. |
| US09141750B2 |
Charged particle beam writing apparatus and irradiation time apportionment method of charged particle beams for multiple writing
A beam writing apparatus includes a unit to obtain a specific value by calculating an integer by dividing a total irradiation time by a multiplied value of a region number and a repeating times number, and by multiplying the integer by the repeating times number, to add the repeating times number to the specific value when a region is in the multiple writing unit regions and is not a specific region and when a region number of the multiple writing unit region, defined excluding the specific region, is below or equal to a value obtained by dividing the total irradiation time by the multiplied value of the region number and the repeating times number, to obtain a first remainder, and dividing the first remainder by the repeating times number, and to treat an added value of the repeating times number and the specific value, as a total irradiation time. |
| US09141747B1 |
System level tools to support FPGA partial reconfiguration
Various embodiments of the present disclosure provide techniques for enabling a user to efficiently design a programmable logic device (PLD) capable of partial reconfiguration. In some implementations, a processor is configured to run a system level design tool and accepts, as inputs from a user, an identification of at least two personas to be used within a reconfigurable region of the PLD. The design tool defines one or more boundaries of a partial reconfig (PR) domain, the PR domain including a partitioned reconfigurable region of the PLD that is selectably configurable as any of the at least two personas. In some implementations, the PR domain includes at least one IP component configured to safely shut down at least one signal, the at least one signal originating from or directed toward an element of the PLD outside of the PR domain. |
| US09141744B2 |
Method for generating layout pattern
A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns. |
| US09141743B1 |
Methods, systems, and articles of manufacture for providing evolving information in generating a physical design with custom connectivity using force models and design space decomposition
Disclosed are methods, systems, and articles of manufactures for providing evolving information in generating a physical design with custom conductivity using force models and design space decomposition by first presenting a layout area in an interface. The interface then displays the evolution of the physical design in the interface to reflect temporal states of the physical design during generation of the physical design after the system receives an input for the physical design and a request for creating the physical design. |
| US09141742B2 |
Priori corner and mode reduction
Systems and techniques are described for performing a priori corner and mode reduction. Some embodiments create a synthetic corner in which (1) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple temperature corners, and/or (2) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple parasitic corners. Some embodiments can identifying, for a given corner, a portion of the circuit design that is common across multiple modes, and then replace the multiple modes with a single mode for optimizing and verifying timing constraints of the portion of the circuit design that is common across the multiple modes. The circuit design can then be optimized over the reduced set of modes and/or corners. |
| US09141735B2 |
Circuit device reliability simulation system
The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device. |
| US09141730B2 |
Method of generating a recipe for a manufacturing tool and system thereof
A computer creates a recipe for a manufacturing tool based on design data. The computer obtains the design data, which includes basic elements and hierarchical levels corresponding to the basic elements. The computer selects one or more basic elements of interest and generates one or more sets of simple array cells corresponding to a level of interest. The computer uses the sets of simple array cells to identify periodical areas in level-of-interest coordinates to enable automated recipe creation. The periodical areas are identified with respect to one or more basic elements. |
| US09141726B1 |
Computerized systems and methods for providing mobile-device updates of electronic health records
A system, method, and computer-readable media are provided for facilitating clinical decision making, and in particular, decision making based on a third party's clinical situation by determining and providing useful, up-to-date information, such as patient-related information to a decision maker. In one embodiment, a user first identifies an information item concerning a patient. Based on that item, a set of related information items is determined and prioritized, and a reference pointer, which identifies the set of related information, is generated. The reference pointer is communicated to the user's mobile device. Subsequently, the user's mobile device requests information from the set of information items associated with the reference pointer, and provides information authorization information. Following authentication of the user's credentials, updates of information from the set of information items is communicated to the user's mobile device as they become available. |
| US09141723B2 |
Caching sliding window data
Disclosed are methods, systems, paradigms and structures for caching data associated with a sliding window in computer systems. A sliding window can include a time window that progresses with time, and the data can include time series data. As time progresses, the sliding window changes bringing in new data. The cache is updated with new data as and when the sliding window moves. The sliding window data is cached at various granularity levels. The method includes storing a first portion of the data at a first granularity level and a second portion at a second granularity level. The data is cached at various granularity levels in order to effectively use the cache considering at least cache updating criteria such as (i) number of times a storage unit is queried to retrieve the data for updating the cache, (ii) the day/date/time at which the storage unit is queried. |
| US09141722B2 |
Access to network content
A method and system for improving access to network content are described. Aspects of the disclosure minimize the delay between a navigation event and a network response by prerendering the next navigation event. For example, the method and system may predict a likely next navigation event during web browsing to preemptively request content from the network before the user selects the corresponding link on a web page. The prediction operation may identify correlations between metadata associated with a navigation history. The metadata may include the relationship of the selected navigation events to a web page. By making predictions using link page relationships links may be accurately predicted in circumstances where two links share common relationships to their source page but different destination addresses. |
| US09141713B1 |
System and method for associating keywords with a web page
A web page optimization engine for optimizing a web page is described. The web page optimization engine includes a keyword mapping engine configured to generate a keyword map including a listing of keywords, where each keyword is associated with one or more web pages. The web page optimization engine further includes a map reversal engine configured to generate a web page map including a listing of web page subject matters, where each web page subject matter is associated with one or more keywords based on the associations from the keyword map. The web page optimization engine yet further includes a web page generation engine configured to generate a web page for a web page subject matter in the web page map to include at least one of the one or more keywords for that web page subject matter. |
| US09141711B2 |
Persisting annotations within a cobrowsing session
A request to navigate to a Uniform Resource Identifier (URI) can be received within a cobrowsing session. The cobrowsing session can be associated with a unique session identifier of a cobrowsing application. The cobrowsing application can be part of a collaboration software. An annotation previously associated with the URI from a historic cobrowsing session can be retrieved. Content associated with the URI can be obtained and presented within an interface associated with the cobrowsing session. The annotation can be presented within the content associated with the URI of the interface. |
| US09141708B2 |
Methods for generating selection structures, for making selections according to selection structures and for creating selection descriptions
A real-time system receives a selection structure formed by weighted rules joined by links, each of the weighted rules including a condition part, a conclusion part and a weight. The selection structure is an Algebraic Decision Diagram (ADD) that includes internal nodes, each representing a decision point and terminal nodes, each representing a subset of candidate results having an accumulated weight. In response to a query that specifies a set of conditions, the ADD is traversed by making a series of decisions at decision points of the ADD to reach at least one terminal node having a maximum accumulated weight among terminal nodes that satisfy the set of conditions. The subset of candidate results represented by the at least one terminal node is selected as the output for responding to the query. |
| US09141704B2 |
Data management in social networks
Architecture that monitors interaction data (e.g., search queries, query results and click-through rates), and provides users with links to other users that fall into similar categories with respect to the foregoing monitored activities (e.g., providing links to individuals and groups that share common interests and/or profiles). A search engine can be interactively coupled with one or more social networks, and that maps individuals and/or groups within respective social networks to subsets of categories associated with searches. A database stores mapped information which can be continuously updated and reorganized as links within the system mapping become stronger or weaker. The architecture can comprise a social network system that includes a database for mapping search-related information to an entity of a social network, and a search component for processing a search query for search results and returning a link to an entity of a social network based on the search query. |
| US09141700B2 |
Search engine optimization with secured search
One example includes a method of attributing revenue to keywords for an entity having an entity website. The method may include obtaining the keywords used in a secured search on a search engine that result in a visit to an entity website and determining a position or rank of a webpage of the website on a search results page resulting from searching the keyword. The method may further include estimating, based on the rank of the webpage, a number of visits to the website that result from secured searches of the keyword. |
| US09141698B2 |
Semantic note taking system
A semantic note taking system and method for collecting information, enriching the information, and/or binding the information to services is provided. User-created notes are enriched with labels, context traits, and relevant data to minimize friction in the note-taking process. In other words, the present invention is directed to collecting unscripted data, adding more meaning and use out of the data, and binding the data to services. Mutable and late-binding to services is also provided to allow private thoughts to be published to a myriad of different applications and services in a manner compatible with how thoughts are processed in the brain. User interfaces and semantic skins are also provided to derive meaning out of notes without requiring a great deal of user input. Linking physical objects to notes are also provided, such as through QR codes. |
| US09141695B2 |
System and method for creating, managing, and publishing audio microposts
A system and method for creating, managing, and publishing audio microposts is provided. An audio micropost comprises a short audio segment recorded and/or captured based on voice, speech, and/or other sound, which may be shared with and/or published to subscribers and/or other users. The system may enable creating a discussion and playlist based on the audio microposts. The discussion may be generated by identifying and/or selecting an audio micropost that may pose a question and/or topic for a discussion and/or debate. The system may further enable granting the ability to participate in the discussion to a selected group of participants. The playlist of audio microposts may be created by adding individual posts into the playlist and/or by using hashtags and/or keywords to search for audio microposts of interest. |
| US09141688B2 |
Search in network management UI controls
A network search function is disclosed. A network administrator enters a search term. The search function determines whether any items or network devices listed in a network control user interface match the search term. The network administrator can stipulate whether the match be either an explicit match or an implicit match. All of the matches, if any, are automatically highlighted and selected. Thereby, the network administrator can perform an operation on these matches based on the search function, without having to manually locate and then manually click to select the desired items or network devices. |
| US09141686B2 |
Risk analysis using unstructured data
Unstructured data is received from a plurality of sources to facilitate risk analysis. The unstructured data comprises a plurality of bodies of text. Each body of text from the unstructured data is deconstructed into individual terms. The individual terms from each body of text are converted into a structured form. The individual terms in the structured form are categorized according to a comparison of the structured form to another structured form. The individual terms in the structured form are quantified according to at least the categorization of the individual terms. |
| US09141685B2 |
Front end and backend replicated storage
An existing primary data copy can be maintained on an existing primary front end server node. One or more existing secondary data copies can be maintained on one or more existing secondary front end server nodes to minor the existing primary data copy (such as by making synchronous changes to the secondary data copies). One or more existing backup data copies can be maintained on an existing backend server node to mirror the existing primary data copy (such as by making asynchronous changes to the one or more backup data copies). The existing backend server node can be accessible by one or more of the front end nodes. In response to detecting a failure of the existing primary data copy, one of the one or more secondary data copies can be designated as a new primary data copy in place of the existing primary data copy. |
| US09141682B1 |
Resolving conflicts within saved state data
Disclosed are various embodiments for synchronizing application state information across devices. More specifically, embodiments of the disclosure are related to resolving conflicts between application state information. A synchronization rule, an event name and/or event value are embedded within application state information obtained from devices associated with a user, from which conflicts can be resolved by an application synchronization service. |
| US09141679B2 |
Cloud data storage using redundant encoding
Cloud data storage systems, methods, and techniques partition system data symbols into predefined-sized groups and then encode each group to form corresponding parity symbols, encode all data symbols into global redundant symbols, and store each symbol (data, parity, and redundant) in different failure domains in a manner that ensures independence of failures. In several implementations, the resultant cloud-encoded data features both data locality and ability to recover up to a predefined threshold tolerance of simultaneous erasures (unavailable data symbols) without any information loss. In addition, certain implementations also feature the placement of cloud-encoded data in domains (nodes or node groups) to provide similar locality and redundancy features simultaneous with the recovery of an entire domain of data that is unavailable due to software or hardware upgrades or failures. |
| US09141678B2 |
Distributed query cache in a database system
A distributed query system includes a distributed collection of dynamically created compiled queries. As each client submits a query, a parameterized query skeleton is identified, which identifies the general form of the query, and the parameters associated with the particular query. If a compiled form of the skeletal query is available within the distributed system, it is executed with the parameters of the current query. If the compiled form of the skeletal query is not available within the distributed system, a compiled form is created, and the location of this compiled skeletal query is stored for subsequent access by this client, or other clients. The executable compiled skeletal queries may be stored at each client system, or in a commonly available server storage system. |