| Document | Document Title |
|---|---|
| US09136893B2 |
Receiver
A receiver includes a local signal generator, a power phase adjuster, and a frequency converter so as to perform frequency conversion on signals included in a plurality of radio frequency bands. The local signal generator supplies a plurality of local signals. The power phase adjuster adjusts local signals in terms of signal power or relative phases. The frequency converter performs frequency conversion on radio frequency bands by use of local signals adjusted with the power phase adjuster, thus sorting them in a desired frequency range. |
| US09136891B2 |
Adaptive data decoding
This application presents a direct data recovery from subspaces or parameters subranges of a received OFDM signal preidentified as corresponding to specific data symbols, by applying adaptive data decoding (ADD) method for reversing both original data coding and deterministic and random distortions introduced by a transmission channel, wherein both reversals are achieved by the same conversion of the subspaces or parameter subranges into data transmitted originally in order to eliminate an intermediate recovery of signals or parameters transmitted originally within the received OFDM signal. The ADD includes using both amplitudes and gradients of amplitudes of OFDM tone signals. |
| US09136889B2 |
Mixer biasing for intermodulation distortion compensation
To compensate for second-order intermodulation (IM2), it is determined whether a blocking signal is present at a receiver. A biasing differential is applied across downconverting mixers in the receiver that minimizes cross-correlation of quadrature signal components of a signal produced by the receiver in the presence of the blocking signal. |
| US09136885B2 |
Antennae system
Embodiments of the invention relate to wireless communications networks, and more specifically to an antenna apparatus for cellular wireless systems. Increasing data capacity of cellular wireless systems places increasing demands on the capacity of the two way connection, known as backhaul, between a cellular base station and a telecommunications network such as the PSTN backhaul, since this is the connection that has to convey the wireless-originating traffic to its destination, often in an entirely different network. Known backhaul links include leased lines, microwave links, optical fiber links or radio resources for relaying backhaul traffic between base stations. The fixed line solutions are expensive to implement and maintain, while the radio solutions antenna configurations that are not ideal for relaying data between base stations. In embodiments of the invention, communication between base stations occurs in a first timeslot by use of a first antenna system and communication between a given base station and a user equipment occurs in a second timeslot using a second antenna system. The benefit of this method is that the first antenna system can be optimized for use in communication between base stations, whereas the second antenna system can be optimized for communication with user equipment which preferably occurs within the area of cellular wireless coverage of the sector served by the second antenna system. |
| US09136882B2 |
Uplink channel estimation for a software defined radio
A system and method for uplink channel estimation for a software defined radio is disclosed. The method comprises dividing an allocated bandwidth for a received signal on the uplink channel into N segments. The uplink channel estimation is processed for each of the N segments as a separate process. The uplink channel estimation includes pre-processing each of the N segments of the received signal; Wiener filtering the pre-processed segments of the received signal in the frequency domain; and Wiener filtering each of the frequency filtered segments in the time domain to determine a channel estimate for each of the N segments for use in equalizing the received signal. |
| US09136880B2 |
Method for stopping iteration in an iterative turbo decoder and an iterative turbo decoder
The present document discloses a method for stopping iteration in an iterative Turbo decoder and an iterative Turbo decoder. Hard decisions from the two convolutional decoders of the iterative Turbo decoder are used simultaneously to determining when to stop the iteration in the iterative Turbo decoder. |
| US09136877B1 |
Syndrome layered decoding for LDPC codes
The various implementations described herein include systems, methods and/or devices for enhancing the performance of error control decoding. The method includes receiving at an LDPC decoder data from a storage medium corresponding to N variable nodes. The method further includes: updating a subset of the N variable nodes; updating all check nodes logically coupled to the updated subset of the N variable nodes; and generating check node output data for each updated check node including at least an updated syndrome check. Finally, the method includes: stopping decoding of the read data in accordance with a determination that the syndrome checks for all the M check nodes are valid syndrome checks or initiating performance of the set of operations with respect to a next subset of the N variable nodes in accordance with a determination that the syndrome checks for all the M check nodes include one invalid syndrome check. |
| US09136874B2 |
Method and apparatus for transmission and reception of in-band on-channel radio signals including complementary low density parity check coding
A method of transmitting digital information includes: receiving a plurality of information bits representing audio information and/or data; encoding the information bits using complementary low density parity check coding to produce a composite codeword and a plurality of independently decodable semi-codewords; modulating at least one carrier signal with the forward error corrected bits; and transmitting the carrier signal(s). Transmitters that implement the method, and receivers that receive signals produced by the method, are also provided. |
| US09136873B2 |
Reduced uncorrectable memory errors
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively. |
| US09136871B2 |
High-performance ECC decoder
Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. |
| US09136870B2 |
Method and apparatus with error correction for dimmable visible light communication
An apparatus and method using error correcting for visible light communication are provided. The error correction includes generating an encoded message from an original message by using a predetermined coding method, puncturing the encoded message based on a determined dimming value or rate, and/or puncturing rate, generating a scrambled message by scrambling the punctured message, and providing the scrambled message to a visible light source. |
| US09136869B2 |
High-rate reverse-order run-length-limited code
A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control. |
| US09136867B2 |
ΔΣ-modulator and ΔΣ-A/D converter
The present invention relates to a delta-sigma-modulator and a delta-sigma-A/D converter. By speeding up the settling time constant of an integrator at the last stage with a simple configuration, the sampling frequency is sped up in the delta-sigma-modulator as a whole. Specifically, in the delta-sigma-modulator including multiple integrators connected in cascade, the integrator positioned at the last stage is a passive integrator not using an amplifier circuit, and one or more integrators positioned at stages preceding the last stage by one or more stages are active SC integrators using amplifier circuits and switched capacitor circuits, respectively. Also, each of the integrators performs integral calculation by alternately repeating a first operation phase to charge a sampling capacitor by sampling an input signal, and a second operation phase to perform a summing integration by transferring an electric charge charged in the sampling capacitor to an integration capacitor. |
| US09136866B2 |
Digital-to-analog converter and a method of operating a digital-to-analog converter
A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section. |
| US09136865B2 |
Multi-stage digital-to-analog converter
A circuit includes a first digital filter H(z), a second digital filler 1 1 + H ( z ) , a third digital filter, a first and a second digital modulators, and a gain block. The first digital filter generates a first output based on a digital input and a first digital output signal. The first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. The gain block amplifies the first error output by a predetermined ratio, thereby generating a second error output. The second digital modulator generates a second output and a third error output based on the second error output. The second digital filter generates a second digital output signal based on the second output. The third filter generates the feedback error output based on the third error output. |
| US09136864B1 |
Method for trimming segment currents in current steering DAC based on most back gate voltage modulation
A digital-to-analog converter (DAC) system includes a DAC and a current trimming module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers, receives segment currents from a respective one of a plurality of segment current sources, and generates an output current based on the driver signals and the segment currents. The current trimming module stores a plurality of trim coefficients and adjusts respective threshold voltages associated with the plurality of segment current sources based on the plurality of trim coefficients. |
| US09136859B2 |
Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs)
An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. |
| US09136856B1 |
Background DAC calibration for pipeline ADC
A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current. |
| US09136855B2 |
Ad converter
In one embodiment, an AD converter includes a first (second) oscillation circuit, a first (second) counter, a first (second) arithmetic circuit, a first (second) subtracting circuit, an adder circuit, and a feedback circuit. The first oscillation circuit generates a first pulse signal having a frequency corresponding to a level of a first analog signal. The first counter counts the first pulse signal. The first arithmetic circuit generates a first signal corresponding to a change amount of a count value. The first subtracting circuit outputs a digital signal corresponding to a difference between the signals generated by the first and second arithmetic circuits. The adder circuit generates a sum signal of the signals generated by the first and second arithmetic circuits. The second subtracting circuit generates a difference signal between the sum signal and a reference signal. The feedback circuit inputs the difference signal to the first oscillation circuit. |
| US09136852B2 |
Multi-stage parallel super-high-speed ADC and DAC of logarithmic companding law
Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error. |
| US09136851B2 |
Atomic oscillator, method of detecting coherent population trapping resonance and magnetic sensor
An atomic oscillator includes an alkali metal cell encapsulating an alkali metal atom; a light source that emits laser light; a light detector that detects light which has passed through the alkali metal cell; and a polarizer arranged between the alkali metal cell and the light detector. A modulation frequency in the light source is controlled, according to a coherent population trapping resonance which is a light absorption characteristic of a quantum interference effect for two kinds of resonant lights, by modulating the light source to generate sidebands and injecting laser lights with the sidebands into the alkali metal cell. A magnetic field is applied on the alkali metal cell in a direction parallel to a propagating direction of the laser light, and the laser light entering the alkali metal cell has a linear polarization, which is not parallel to a polarization direction of the polarizer. |
| US09136850B2 |
Phase aligner with short lock time
A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal. |
| US09136849B2 |
Integer frequency divider and programmable frequency divider capable of achieving 50% duty cycle
An integer frequency divider capable of achieving a 50% duty cycle includes a source clock input end that provides a source clock, and two or more latches connected in series according to a connection order. Each of the latches includes: a signal input stage, configured to receive an input signal; a clock receiving stage, configured to treat the source clock as an input clock and an inverted clock of the source clock as an inverted signal of the input clock when the latch corresponds to an odd number in the connection order, and to treat the inverted clock as the input clock and the source clock as the inverted signal of the input clock when the latch corresponds to an even number in the connection order; and a signal output stage, configured to output an output signal according to the input signal and the source clock. |
| US09136848B2 |
High speed precessionally switched magnetic logic
High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. |
| US09136843B2 |
Through silicon via repair circuit of semiconductor device
TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate. |
| US09136842B2 |
Integrated circuit device with embedded programmable logic
Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like. |
| US09136840B2 |
Proximity switch assembly having dynamic tuned threshold
A method of activating a proximity switch is provided. The method of activating the proximity switch includes the step of sensing a signal associated with a proximity sensor and sensing a dynamic parameter. The method also includes the step of tuning a threshold value based on the sensed dynamic parameter. The method further includes the step of activating the switch based on the signal and the threshold value. |
| US09136837B2 |
Switching circuit and power supply device including switch circuit
A switching circuit includes first and second MOS transistors of the same conductive type. The second MOS transistor has a drain connected to a first terminal, a source connected to a load connecting terminal, a gate connected to a gate of the first MOS transistor, and a back gate connected to a source of the first MOS transistor. The switching circuit includes a circuit that controls a current flowing between the source of the first MOS transistor and a resistor connecting terminal so that the potential of the source of the first MOS transistor and the potential of the source of the second MOS transistor are equal. This switching circuit further includes a circuit that outputs a control signal to the gate of the first MOS transistor and the gate of the second MOS transistor and controls the operations of the first MOS transistor and the second MOS transistor. |
| US09136836B2 |
Converter including a bootstrap circuit and method
In accordance with an embodiment, a converter includes a circuit and method for charging a bootstrap capacitor. The circuit monitors a voltage across the bootstrap capacitor and enables charging the bootstrap capacitor in response to the voltage across the bootstrap capacitor being less than a threshold voltage. |
| US09136835B2 |
Switch circuit
According to one embodiment, a switch circuit includes a transmission unit configured to transmit a signal through a transistor, in which a back gate and a source are connected by way of a resistor; and a back gate control unit configured to connect the back gate of the transistor to a fixed potential when the transistor is turned OFF, and to separate the back gate of the transistor from the fixed potential when the transistor is turned ON. |
| US09136832B2 |
Level shift circuit
A level shift circuit includes a first pair of transistors of the first conductive type (M1, M4) with sources coupled to a pair of input nodes (in, inB) and gates coupled to the first power supply (GND) in common; a second pair of transistors of the second conductive type (M2, M5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (M3, M6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (V2) in common; and a pair of capacitative elements (C1, C2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors. |
| US09136831B2 |
Frequency to voltage converter
According to the invention, there is provided a frequency to voltage converter for generating an output voltage proportional to the frequency of input signal. It comprises a switched capacitor circuit for receiving input signal and generating an input current proportional to said frequency, the switched capacitor having a capacitor charging and discharging at said frequency; an operational transconductance amplifier (OTA) for receiving at least one control voltage representative of the input current and generating current proportional to the at least one control voltage; at least one negative feedback circuit connecting input and output of the OTA, each negative feedback circuit comprising: a control transistor coupled to a node of the OTA; a diode connected transistor coupled to the control transistor for sensing current flowing through the control transistor; and a feedback transistor coupled to another node of the OTA. |
| US09136830B1 |
Data signal receiver, transceiver system and method of receiving data signal
A data signal receiver includes a clock signal filter, a falling pulse signal generator, a mixing block, and a sampler. The clock signal filter generates a first filtered clock signal and a second filtered clock signal by filtering a clock signal. The falling pulse signal generator generates a falling pulse signal based on the first filtered clock signal. The mixing block generates a mixed data signal by mixing a data signal and the falling pulse signal. The sampler generates a recovered data signal by sampling the mixed data signal in response to the second filtered clock signal. |
| US09136829B2 |
Method and apparatus for implementing a programmable high resolution ramp signal in digitally controlled power converters
A system and method for controlling a power converter includes a digital-to-analog converter (DAC) and ramp generator for generating a reference current command. The DAC is configured to decrement (or increment) to a next state after a fixed number of clock pulses have occurred. The reference current command controls an output of the power converter. Means are provided for delaying an output of the DAC for a number of clock pulses less than the fixed number to increase a resolution of the DAC. |
| US09136828B2 |
Current mode logic latch
A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor. |
| US09136825B2 |
Method and device for implementing tracking filters and RF front end of software defined radios
A tracking circuit has first and second filters controlled by clock signals and a combiner. Each filter has N paths in parallel between an input and an output, each path comprising a respective first/second sub-circuit and a switch (N is an integer >1). The clock signals selectively control each of the N switches of the first and second filters at a same frequency, and in variously described embodiments the first and second on-time durations may be different, the first and second sub-circuits may be different, or both first/second on-time durations and first/second sub-circuits may be different. Signals output from the first and second filter are added at a combiner. In certain examples each path in the first and second filter is controlled by same-phase clock signals, and every path on either filter are controlled with different-phase clock signals. |
| US09136822B2 |
Microelectromechanical system with a micro-scale spring suspension system and methods for making the same
Integrated Microelectromechanical System (“MEMS”) devices and methods for making the same. The MEMS devices comprise a substrate (200) and a MEMS filter device (100) mechanically suspended above a major surface of the substrate. A first gas gap (202) exists between the major surface of the substrate and the MEMS filter device. An isolation platform (600) is provided to absorb vibrations from an external environment prior to reaching the MEMS filter device. In this regard, the isolation platform comprises: a frame structure (610) framing a periphery of the MEMS filter device; and at least one resilient component (612-618) coupled between the frame structure and the MEMS filter device. The frame structure is mechanically connected to the substrate. Electronic circuitry is connected to the MEMS filter device via a resilient interconnection (204, 206) that is movable in at least one direction of the vibrations. |
| US09136821B2 |
Surface mount device-type low-profile oscillator
A surface mount device-type low-profile oscillator is provided. A main surface of an IC chip unit is joined to a bottom surface where the external terminals of a crystal unit section are formed. An integrated circuit portion includes a circuit forming, together with the crystal unit of the crystal unit section, an oscillator circuit on the main surface of the IC chip unit, and IC terminals formed with a plurality of IC electrode terminals, and two connection terminals connecting the external terminals of the crystal unit section are provided. The IC electrode terminals and mounting terminals are electrically connected with electrical columns provided in via holes penetrating in the direction of thickness of a silicon plate of a bare chip. The crystal unit section and the IC chip unit are joined with an anisotropic conductive adhesive applied to the main surface of the IC chip unit. |
| US09136816B2 |
Wide-band common mode filtering apparatus
A wide-band common mode filtering apparatus includes at least two cascaded common mode filters with different noise-filtering responses, wherein the cut-off frequency of the wide-band common mode filtering apparatus is at the lowest cut-off frequency of the common mode filters, and the noise-filtering response of the wide-band common mode filtering apparatus is the superposition of the noise-filtering responses of the common mode filters. In one embodiment of the present invention, the wide-band common mode filtering apparatus includes a first common mode filter having a first filtering band, and a second common mode filter having a second filtering band different from the first filtering band. The disclosure of the present technique allows the cascaded common mode filters with different filtering bands to form the wide-band common mode filtering apparatus having an overall filtering band to meeting a new demand. |
| US09136812B2 |
Devices for automatic adjustment of gain and attenuation factors
A device for the automatic adjustment of a gain and/or attenuation factor of several amplification or attenuation elements connected in a cascade comprises respectively a detector for measuring a signal level of a signal disposed at the input of the respective amplification or attenuation element and respectively a downstream control unit for determining the gain and/or attenuation factor respectively associated with each amplification or attenuation element. The control unit is a forward control unit for determining the gain and/or attenuation factor respectively associated with each amplification or attenuation element dependent upon the measured signal level of the signal disposed at the input of each amplification or attenuation element. |
| US09136808B2 |
Signal processing apparatus and method
A signal processing apparatus and method are disclosed. A common mode signal extraction unit is configured to extract a common mode signal from input signals inputted to a differential amplifier. A common mode signal adjustment unit is configured to adjust a gain and a phase of the common mode signal and to output the adjusted common mode signal to the differential amplifier. An optimal set determination unit is configured to determine an optimal gain and phase to be applied to the common mode signal based on an output signal from the differential amplifier. |
| US09136801B2 |
Semiconductor integrated circuit device, electronic device, and radio communication device
In an embodiment, a semiconductor integrated circuit device includes a driver circuit that drives a transmission line, an output terminal coupled to the output of the driver circuit, and a variable-impedance circuit. The variable-impedance circuit is coupled, for example, between the driver circuit and the output terminals for series-termination of the transmission line. |
| US09136796B2 |
Negative audio signal voltage protection circuit and method for audio ground circuits
Self-grounded circuitry (10) includes a signal channel conducting an output voltage (VOUT1). A charge pump (2) powered by a reference voltage (VDD) produces a control voltage (VCP). The control signal is at a low level if the reference voltage is low and is boosted to a high level if the reference voltage is high. A ground switch circuit (15) includes a depletion mode transistor (MP1) having a source coupled to the output voltage, a gate coupled to the control voltage, and a drain coupled to ground. The transistor includes a well region (4-1) and a parasitic substrate diode (D3-1). A negative voltage protection circuit (17-1) includes a depletion mode first protection transistor (MP3-1) having a drain coupled to the well region, a source coupled to a source of a depletion mode second protection transistor (MP4-1) having a drain coupled to the output voltage, the first and second protection transistors each having a gate coupled to the control voltage, and also includes a diode (MN1) coupled to charge the well region from the control voltage conductor to prevent distortion of the output voltage. |
| US09136794B2 |
Bipolar microelectronic device
An apparatus, system, and method are disclosed for modulating electric current. An electron source electrode provides a flow of electrons in a partial vacuum environment. An ionizable gas in the partial vacuum environment forms positively charged ion particles in response to impact with the electrons from the electron source electrode. Application of a bias voltage differential between a first bias electrode and a second bias electrode in the partial vacuum environment forms an electric field gradient in a path of the flow of electrons. A collector electrode in the partial vacuum environment collects more electrons than ion particles when a collector electrode input voltage is above a threshold, and collects more ion particles than electrons when the collector electrode input voltage is below the threshold. |
| US09136791B2 |
Motor driving device, integrated circuit device, motor apparatus and motor driving system
A motor driving device includes a communication path selection unit, to which operation command information for controlling driving of a motor is input in a serial data format or a parallel data format via a common input path, a communication unit which includes a serial interface unit for the serial data format and a parallel interface unit for the parallel data format, and outputs a control signal based on the operation command information input via the communication path selection unit, and a driving control unit which controls driving of the motor based on the control signal. The communication path selection unit selects between outputs path to the serial interface unit and the parallel interface unit, which corresponds to the data format of the input operation command information, and outputs the input operation command information to the serial interface unit or the parallel interface unit through the selected output path. |
| US09136789B2 |
Synchronous motor control apparatus
A control apparatus includes, a first calculating unit which calculates first d-phase and q-phase current limit candidate values, a second calculating unit which calculates second d-phase and q-phase current limit candidate values, a q-phase unit which, when the absolute value of the first d-phase current limit candidate value is smaller than that of the second d-phase current limit candidate value, sets the first q-phase current limit candidate value as a q-phase current limit value, but otherwise sets the second q-phase current limit candidate value as the q-phase current limit value, and a d-phase unit which, when the absolute value of the first d-phase current limit candidate value is smaller than that of the second d-phase current limit candidate value, sets the first d-phase current limit candidate value as a d-phase current limit value, but otherwise sets the second d-phase current limit candidate value as the d-phase current limit value. |
| US09136786B2 |
Measurement circuit
A measurement circuit in a motor circuit generates signals for use in a motor control strategy for an electric motor. The measurement circuit comprises a first current sensing means which produces an output signal indicative of the current flowing in a di/dt path connecting the phases of the motor to a ground or a common positive supply voltage, and further comprises a second current sensing means which produces an output signal indicative of the rate of change of current flowing in the ground line, and in which the second current sensing means comprises a Rogowski coil. |
| US09136783B2 |
Vehicle, power supply system, and method for controlling power supply system
When an ECU disconnects a second power storage device BAT2 from a drive device 90 while a hybrid vehicle is traveling, ECU disconnects one of a contact point B1 and a contact point G2 of a system main relay SMR2 and causes the vehicle to continue traveling using electric power supplied from a first power storage device BAT1 to drive device. After the vehicle finishes traveling, ECU performs a discharging operation for discharging a charge remaining in a first capacitor C1 and a second capacitor C2 with the one contact point of system main relay SMR2 being disconnected. If the charge is not discharged appropriately, ECU determines that welding occurs in at least one of system main relay SMR1 and system main relay SMR2. |
| US09136781B2 |
Synchronous control unit for synchronizing two shafts with each other
In the first synchronous system of the synchronous control unit (1), movement commands of the first motor (23) and the second motor (13) made by the movement command making section (9), which are synchronized with each other, are respectively supplied to the first amplifier (22) and the second amplifier (12) through the first communication path (11) and the second communication path (21). In the second synchronous system switched from the first synchronous system, the first motor (23) is decelerated by a deceleration command made by the deceleration making section (29) and the second motor (13) is decelerated synchronously with the first motor by a movement command made by the position feedback value controlled by the first motor (23) supplied to the second amplifier (12) through the third communication path (31). |
| US09136778B2 |
Non-magnetic high-speed piezoelectric rotary motor
A piezoelectric motor including a rotor and a piezoelectric actuator positioned relative to the rotor in such manner that a working end of the actuator is in linear, frictional, resilient and forced contact with a working surface of the rotor. The actuator includes a piezoelectric a longitudinal prism shaped resonator with a trapezoidal cross-section and the working end of the actuator is a flat pusher insert set at an angle to the plane of the resonator base. An electronic generator is connected to electrodes of the piezoelectric actuator to excite periodic mechanical oscillations in the actuator wherein the electrodes are applied onto the longitudinal lateral trapezoidal surfaces of the resonator and the piezoelectric resonator is polarized across its width and the electronic generator outputs an alternating electrical voltage signal at a frequency matching the frequency of the first-order natural longitudinal mode of mechanical oscillation along the length of the resonator. |
| US09136777B2 |
Capacitively coupled power supply system
A power supply system (200) is provided which comprises a first input (206), an output (218), a DC-DC converter (204), a rectifying circuit (212) and a voltage limiter (214). An AC voltage is received by the first input. Power is supplied to a load (216) via the output. The DC-DC converter comprises a second input (203) which is capacitively coupled to the first input, and the DC-DC converter provides power to the output. The rectifying circuit is capacitively coupled to the first input and is arranged between the first input and the output. The rectifying circuit provides a rectified output voltage to the output. The voltage limiter is coupled to the output and limits the rectified voltage to a predefined voltage. |
| US09136771B2 |
Digital control for controlling and linearizing an AC impedance
An apparatus for regulating AC power of a power source in a power circuit is provided. The apparatus includes a full-wave bridge rectifier, a power transistor array, and a controller. The full-wave bridge rectifier is configured to receive an AC input put from the power source. The power transistor array is connected to the full-wave bridge rectifier. The power transistor array is configured to receive the AC input from the full-wave bridge rectifier and to generate an AC signal. The power transistor array may include only a single transistor or a plurality of transistors connected in series, for example. The controller is connected to the power transistor array. The controller is configured to receive the AC signal from the power transistor array, or the output of the AC regulator in some embodiments, and to determine a correction output to send to the power transistor array to control an AC impedance of the power circuit to generate an AC output. |
| US09136769B2 |
Load change detection for switched mode power supply with low no load power
A pulse scheme is used for load change detection in a switching mode power supply with low no-load power consumption. The pulse scheme includes a measurement pulse for determining a load condition or a no-load condition at the output. Generation of the measurement pulse results in sufficient energy transfer to the secondary side to accurately measure the output voltage via a reflected voltage on the primary side. Once in no-load operation mode, a reference pulse having a lower energy transfer than the measurement pulse is used to determine a baseline reflected voltage value that corresponds to a no-load condition. Successive detection pulses are then generated and corresponding reflected voltage measured and compared to the baseline reflected voltage. A change in the reflected value that exceeds a threshold value is indicative of a change in the no-load condition. |
| US09136764B2 |
Apparatuses and system and method for auto-configuration of a power control system
Power control systems and power control devices may include a power control chip having a power control module configured to generate a power stage control signal, and an external power stage having a timing control module. The timing control module may be configured to receive the power stage control signal and generate a timing control signal controlling at least one switch to regulate an output voltage of the external power stage. The power control device further includes an auto-configuration module configured to communicate with the external power stage and request auto-configuration information from the external power stage. A related method of auto-configuring a power control system includes communicating auto-configuration information between at least one external power stage of a power control system and a power control chip, and configuring a setting of the at least one external power stage of the power control system based on the auto-configuration information. |
| US09136758B2 |
Voltage converting LED circuit with switched capacitor network
A Voltage Converting LED Circuit with Switched Capacitor Network contains a 2-way MOSFET switch that connects a capacitor network to the output of an error amplifier, thereby enabling the error amplifier to resume operation quickly after the off-time segment of a PWM cycle. The switch is controlled synchronously with current sinks controlling brightness and color levels. In a preferred embodiment, multiple serially connected strings of LED's can be controlled simultaneously via one switch. |
| US09136757B2 |
Power converter and refrigerating and air-conditioning apparatus
A power converter includes step-up means for varying a voltage applied by a power supply to a predetermined voltage, commutating means for performing a commutation operation for allowing a current flowing through the step-up means to flow through a second path, smoothing means for smoothing a voltage related to outputs of the step-up means and the commutating means to produce power and supplying the power to a load side, and control means for performing control related to voltage varying, such as stepping up, by the step-up means and controlling the commutation operation of the commutating means on the basis of at least one of a voltage and a current related to the step-up means. |
| US09136756B2 |
System and methods for two-stage buck boost converters with fast transient response
Various embodiments of the invention provide for single and dual phase charge pump, two stage DC/DC buck-boost converters having fast line and load transient control irrespective of load conditions. In certain embodiments of the invention, this is accomplished by controlling a desired output voltage with an error amplifier that controls a plurality of hysteresis comparators. A dual phase charge pump architecture eliminates ripple currents and mode transitions and increases efficiency by splitting the total current between two paths. Certain embodiments allow to use low voltage semiconductor devices, which significantly reduces switching losses and further increases efficiency. |
| US09136750B2 |
Motor capable of adjusting phase difference between output signals
A motor capable of performing mechanical position adjustment of a magnetic detection unit to thereby adjust a phase difference between signals output from respective two magnetosensitive pole pieces. A rotor includes a magnet having an axial end surface magnetized to have circumferentially alternately different poles. A stator has two outer magnetic pole portions opposed to an outer peripheral surface of the magnet. Two coils are energized to excite the outer magnetic pole portions. A magnetic sensor is opposed to an axial end surface of the magnet. The magnetosensitive pole pieces of the magnetic sensor detect a magnetic field change caused by rotation of the magnet. The magnetosensitive pole pieces are arranged side by side in a direction orthogonal to a diametrical direction of the magnet. The position of the magnetic sensor can be adjusted in the diametrical direction of the magnet. |
| US09136745B2 |
Electric vehicle driving system
A side cover 82 which covers a side surface portion of an electric motor 7 is formed of a resin, and a lubricant is ejected from plural ejecting holes 95 of an oil path 90 formed in the side cover 82 to a stator 71 of the electric motor 7 so as to cool the stator. |
| US09136742B2 |
Rotor gear mounting assembly for a generator and method
A rotor gear mounting assembly for a generator includes a rotor shaft comprising a first end and a second end. Also included is a magnetic member arrangement operatively coupled to the rotor shaft proximate at least one of the first end and the second end. Further included is a hub portion of the magnetic member arrangement. Yet further included is a rotor gear operatively coupled to the hub portion. |
| US09136735B2 |
Rotary electric machine laminated core
In a rotary electric machine laminated core, a rotating shaft portion is disposed closer to an outer circumferential surface than an inner circumferential surface of a back yoke portion. A notch portion is disposed on at least one of first and second end portions of the back yoke portion so as to form a gap between a vicinity of the rotating shaft portion of a projecting portion and a recess portion when core segments are arranged in an annular shape or a circular arc shape. The first end portion and the second end portion of the back yoke portion are configured such that a predetermined gap that connects from the outer circumferential side to the inner circumferential side is formed between adjacent projecting portions and recess portions when the core segments are expanded rectilinearly such that magnetic pole tooth portions are parallel to each other. |
| US09136732B2 |
Distributed energy storage and power quality control in photovoltaic arrays
A solar electric system comprises photovoltaic elements having integrated energy storage and control, ideally on each PV-panel. The energy storage media may be primary or secondary cylindrical cells interconnected into a battery and/or an array of capacitors (or super-capacitors) and are accompanied by an electronic control circuit which may perform a variety of functions, including but not limited to: power quality control, load following, pulse powering, active line transient suppression, local sensing, remote reporting, wireless or wired communications allowing two way programmable control through local or remote operation. The operation of the system may yield direct current or with the integration of bidirectional micro-inverters create distributed alternating current generation enhanced with energy storage and control two way energy flows between the solar system and the grid. |
| US09136730B2 |
Energy storage system
An energy storage system includes: a new renewable energy unit generating a new renewable energy power; a DC link connected to the new renewable energy unit and generating a DC link power; a power system connected to the DC link and generating a power system power; a battery connected to the DC link and generating a battery power; an auxiliary power generator connected to the power system, the new renewable energy unit, the DC link, and the battery, respectively, and generating an auxiliary power; and an integrated controller connected to the auxiliary power generator and receiving the auxiliary power. The auxiliary power is selected from one of the power system power, the new renewable energy power, the DC link power, and the battery power. |
| US09136726B2 |
Battery system for movable object and controlling method for the same
A battery system for a movable object is mounted on the movable object having a charger and a load unit including a plurality of loads electrically driven for different purposes. The battery system is provided with a plurality of battery packs, a power control circuit for changing a connection state between the battery packs and the charger and a connection state between the battery packs and the load unit, a memory unit for storing operation information, an estimation unit for estimating a power consumption pattern in the operation cycle based on the operation information and a controller for switching the power control circuit to cover the power consumption by the load unit according to the power consumption pattern. |
| US09136718B2 |
Charge and discharge control circuit, and charge and discharge control method
In a charge and discharge control circuit, a mode control part manages a normal mode in which voltages at a power terminal and an overcurrent detection terminal are monitored, a time-shortening mode in which predetermined delay times for detecting an overcharge, an overdischarge, and an overcurrent are shortened, and a protection mode in which a signal to stop a charge current or a discharge current is output when an abnormality is detected in the normal mode. A transition is made from the normal mode to the time-shortening mode when the voltage at the power terminal exceeds a predetermined value, and a transition is made from the time-shortening mode to the protection mode when one of the overcharge, overdischarge, and overcurrent is detected. |
| US09136713B1 |
Proactive and highly efficient active balance apparatus for a battery power system
An apparatus for actively balancing a cell group in a battery power system comprises a main cell unit further comprising a first local cell module and a second local cell module in parallel creating a parallel cell module. The main cell unit is electrically coupled to a system control unit and the system control unit is communicatively coupled to the first local cell module and the second local cell module. A compensation cell and a power switch unit is communicatively connected to the main cell unit and communicatively connected to the system control unit. The compensation cell and the power switch unit further comprise a plurality of compensation cells. The plurality of compensation cells is paired with the parallel cell module to become the cell group with optimized total capacity. |
| US09136711B2 |
System and method for synchronizing multiple generators with an electrical power distribution system
Systems and method for synchronizing power generators with a power grid are provided. One system among various implementations includes a plurality of synchronization modules, wherein each synchronization module corresponds to one power generator. The synchronization modules are configured to output a control signal to adjust a frequency of the respective power generator to correspond with the frequency of the existing power grid. The system also includes a central controller in communication with the plurality of synchronization modules. The central controller is configured to determine a propagation delay with respect to each synchronization module. The propagation delay is a measure of time for a signal to propagate from the respective synchronization module to the central controller. The central controller is further configured to send a control signal to each synchronization module to control when each synchronization module connects the respective power generator to the existing power grid. |
| US09136708B2 |
Simultaneous distribution of AC and DC power
A system and method for the transport and distribution of both AC (alternating current) power and DC (direct current) power over wiring infrastructure normally used for distributing AC power only, for example, residential and/or commercial buildings' electrical wires is disclosed and taught. The system and method permits the combining of AC and DC power sources and the simultaneous distribution of the resulting power over the same wiring. At the utilization site a complementary device permits the separation of the DC power from the AC power and their reconstruction, for use in conventional AC-only and DC-only devices. |
| US09136707B2 |
Multimode distribution systems and methods for providing power from power sources to power consuming devices
Multimode distribution systems and methods are described. A multimode distribution system includes a first source interface for coupling to a first power source, a second source interface for coupling to a second power source, and a first selection device to be coupled via a first connection matrix and the first source interface with the first power source to provide main power to one or more power consumption devices. The multimode distribution system includes a second selection device to be coupled via a second connection matrix and the first source interface with the first power source to provide main power to one or more additional power consumption devices. The second selection device is to be coupled via the second connection matrix and the second source interface with the second power source to provide alternative power to the additional power consumption devices. |
| US09136704B2 |
Architecture for power plant comprising clusters of power-generation devices
Various techniques are employed alone or in combination, to reduce the levelized cost of energy imposed by a power plant system. Solar energy concentrators in the form of inflated reflectors, focus light onto photovoltaic receivers. Multiple concentrators are grouped into a series-connected cluster that shares control circuitry and support structure. Individual concentrators are maintained at their maximum power point via balance controllers that control the flow of current that shunts this series connection. DC current from clusters is transmitted moderate distances to a centralized inverter. The inductance of transmission lines is maximized using an air-spaced twisted pair, enhancing the performance of boost-type three phase inverters. Cluster outputs are separate from individual inverters in massively interleaved arrays co-located at a central location. Step-up transformers convert inverter voltages to grid voltages, and small transformers provide isolation and voltage step-up only on receiver-to-receiver imbalance currents, typically <20% of the total current. |
| US09136701B2 |
High voltage discharge protection device and radio frequency transmission apparatus using the same
A high voltage discharge protective device for an RF device having a signal port, includes a blocking capacitor arranged at the signal port of the RF device, a circuit board for mounting the blocking capacitor, and a metal conductor grounded and partially bare. The blocking capacitor includes a main body and two leads connected to the main body and secured to the circuit board. The bottom portion of the main body is bare to form an exposed portion. The exposed portion is spaced apart from the circuit board to form an interval. The metal conductor is disposed within the interval and corresponds to the exposed portion of the blocking capacitor. When the passing voltage within the blocking capacitor reaches a predetermined value, the exposed portion of the blocking capacitor sparkly discharges to the metal conductor. An RF device is also provided. |
| US09136699B2 |
Dynamic damper and lighting driving circuit comprising the dynamic damper
A dynamic damper in a lighting driving circuit for limiting an inrush current includes a damper circuit and a timing circuit comprising capacitor. The damper circuit is connected to the timing circuit. When an input voltage is provided to the dynamic damper, the capacitor begins to be charged and the capacitance-voltage of the capacitor rises. The damper circuit enters to a first working state and generates a dynamic damper resistor value. When the capacitance-voltage of the capacitor is greater than a first threshold voltage, the damper circuit enters to a second working state and the dynamic damper resistor value begins to decrease. When the capacitance-voltage of the capacitor is greater than a second threshold voltage, the damper circuit enters to a short-circuit state, and the dynamic damper resistor value decreases to zero to facilitate the normal work of the power source converter. |
| US09136698B2 |
Power supply selector and method for minimizing an inrush current in a power supply selector
A method for minimizing an inrush current in a power supply selector and a power supply selector system is provided. The power supply selector includes a plurality of power input nodes, a power output node, a first transistor and a second transistor. Each of the power input nodes may be coupled to a first switch having a first on-resistance and to a second switch having a second on-resistance. The second on-resistance is greater than the first on-resistance. The first switch and the second switch are preferably coupled in parallel. The power supply selector may be configured to couple a selected one of the power input nodes to the source of the first transistor and to the gate of the second transistor so as to sense a sense voltage at the selected power input node. |
| US09136696B2 |
Early break inverter bypass safety switch
An early break bypass switch provides a modular system for bypassing an inverter when needed without allowing switching induced damage to the inverter. In an embodiment of the invention, a shaft-mounted switch provides rotatable cams and sliding followers for positive opening contacts while providing an auxiliary switch section for breaking and making contact to an inverter controller in a specific sequence relative to inverter power. In this way, the inverter is both isolated from the line power and also protected during switching from being damaged by switching-induced spikes and transient signals and surges. |
| US09136693B1 |
Generator with selectively bonded neutral connection
A generator which is self-configurable to selectively bond the neutral lead to the ground lead of the generator. The generator includes a sensor configured to detect current flow on the ground lead of the generator. The sensor generates a signal corresponding to the current flow which is, in turn, provided to a controller present on the generator. A switch device, such as a relay selectively connects the neutral conductor to the ground conductor at the generator. The controller outputs a signal to control the switch device in response to the signal from the current sensor. If the controller detects current flowing on the ground lead, it opens the switch between the neutral and ground conductors; however, if the controller detects no current on the ground lead, it closes the switch between the neutral and ground conductors. |
| US09136692B2 |
Low fault current isolator system
A low fault current isolation arrangement senses a loss of voltage and automatically isolates and de-energizes a down live primary wire if overcurrent protection devices have not cleared the high impedance fault in an electric power distribution network. Incorporating an operator selectable time delay response, the low fault current isolation arrangement permits overcurrent protection devices to attempt to detect and shut down the affected conductor, and then isolates and shuts down the low current fault if the overcurrent devices are not successful. The isolation arrangement continuously monitors AC voltage as remotely provided by smart meters even after a fault location is de-energized, and serves as a back up, and not as a replacement, for existing overcurrent protection schemes. A host computer operates in conjunction with plural smart meters each coupled to an associated customer distribution transformer in conjunction with the fault isolator to detect and shut down high impedance faults. |
| US09136690B1 |
Front-end circuit with electro-static discharge protection
A termination circuit configured to provide electrostatic discharge (ESD) protection is provided. Termination sub-circuits are coupled in parallel, each including respective pull-up and pull-down circuits. Each pull-up circuit has two transistors of a first type coupled in series between a data input and Vdd, a gate of one of the two transistors being coupled to a control input and a gate of the other one of the two transistors being coupled to a first enable input of the termination sub-circuit. Each pull-down circuit has two transistors of a second type coupled in series between the data input and Vss or ground, a gate of one of the two transistors being coupled to the control input and the gate of the other one of the two transistors being coupled to a second enable input of the termination sub-circuit. |
| US09136686B2 |
Sealing element and connecting housing having a sealing element
A sealing element for sealing a cable inserted into a connecting housing, having a passage opening for the cable to pass through, is disk-shaped having at least one first disk having substantially u-shaped circumference, and a second disk having a substantially u-shaped circumference and resting on the first disk. The first disk has two opposite side flanks which extend parallel to each other, and the second disk has a first pair of flanks having two opposite side flanks, which are formed conically with respect to each other. On the top side of the first disk has a sealing lip which is connected to the side flanks respectively via a chamfered connecting region. |
| US09136684B2 |
Vehicle block heater cord winder
A license plate electrical cord winding apparatus with a housing, an inner cavity, a generally cylindrical spindle affixed to said housing within said inner cavity, a reel assembly mounted to the housing within the inner cavity circumferentially about the spindle. There is also an urging member connected to the reel assembly, and an extension cord, wound around the reel assembly. A guiding roller mounted within the inner cavity guides the cord as it winds or unwinds about the reel assembly. |
| US09136681B1 |
Stabilized bracket for holding conductors a fixed distance from a wall surface
A bracket for holding conductors at a selected distance from the surface of a wall board to be mounted to a building stud. The bracket has a channel formed between a pair of plates and a bendable strap for closing the channel. The strap has an angularly oriented return to engage a side wall and a locking tab to hold the strap in closed position. The channel width is adjustable to accommodate different sized conductors. One of the plates has a bend line for adjusting the total width of the bracket for mounting on a narrower stud. |
| US09136678B2 |
Protector
A protector includes a bottom plate part on which a plurality of electric wires is placed on the same plane, a pair of side parts that is provided to erect from the bottom plate part so that the electric wires is interposed between the pair of the side parts, a distance between the pair of the side parts corresponding to crank-shaped curved parts of the electric wires being larger than a distance between the pair of the side parts corresponding to front and rear linear parts of the crank-shaped curved parts of the electric wires, and a protector fixing part that is provided on the bottom plate part so that the protector fixing part is positioned between the crank-shaped curved parts provided next to each other. |
| US09136675B2 |
Buffering device for the operating mechanism of a switchgear, and method of lubrication thereof
A piston rod (15) and a first piston (13) are arranged in the interior of an external cylinder (11) and internal cylinder (12); a second piston for absorbing the change of volume of operating fluid (24) is also arranged therein. Also, a first return spring (18) for returning the piston rod (15) to the interruption position is provided and a second return spring (20) for returning the operating fluid 24 into the high-pressure chamber (25) by pressurizing the second piston (14) is provided. In addition, the air in the interior of the buffering device (10) is withdrawn by a vacuum pump (38), and operating fluid (24) is thus introduced in a degassed condition. |
| US09136666B1 |
Mode-hop tolerant semiconductor laser design
Described herein are methods, systems, and apparatuses to utilize a laser device comprising a gain section, a wavelength filter, a first reflector, and a second reflector to form a laser cavity with the first reflector, the laser cavity to include the gain section and the wavelength filter. The wavelength filter is temperature stabilized to a predetermined temperature range and the remaining portions of the laser cavity are not temperature stabilized. The wavelength filter, when at the predetermined temperature range, comprises a plurality of adjacent longitudinal modes such that a difference in modal gain values associated with each of the adjacent longitudinal modes is within a predetermined delta. Thus, the cavity of the laser device is designed to experience some mode hops when the device temperature changes; however, because the wavelength filter is stabilized in temperature, the cavity drift due to these mode hops is within a limited range. |
| US09136665B1 |
Using tunnel junction and bias for effective current injection into terahertz magnon
An apparatus comprising a ferromagnetic conductive material including a magnon gain medium (MGM) and a tunnel junction coupled to the ferromagnetic conductive material are provided. The magnon gain medium (MGM) further comprises a conduction band that is split into two sub bands separated by an exchange energy gap, a first sub band having spin up, and a second sub band having spin down. The applied bias voltage is configured to shift the Fermi level of the external metallic contact with respect to the Fermi level of the ferromagnetic conductive material so that the injected electrons are configured to tunnel into the second sub band having spin down. |
| US09136662B2 |
Method for manufacturing a connection between two ceramic parts, especially parts of a pressure sensor, and a ceramic product, especially a ceramic pressure sensor
A method for manufacturing a connection between two ceramic parts comprises: providing a first ceramic part and a second ceramic part; providing an active hard solder, or active braze, on at least one surface section of at least one of the ceramic parts; and heating the active hard solder, or active braze, in a vacuum soldering, brazing process. The entire active hard solder, or active braze, for connecting the first and second ceramic parts is provided in such a manner that at least one surface section of at least one of the ceramic parts, preferably both ceramic parts, is coated by means of gas phase deposition of the alloy of the active hard solder, or active braze. |
| US09136661B1 |
Storage device
A storage device including a storage module and a sheath member is provided. The storage module has a substrate, a first terminal set and a second terminal set, and the first and the second terminal sets are disposed on opposite sides of the substrate. The sheath member has an opening and a third terminal set. A portion of the third terminal set is exposed out of the sheath member. At least a portion of the storage module is sheathed into the sheath member, and the first terminal set is exposed out of the sheath member through the opening. The second terminal set is electrically connected to the third terminal set, and an connection interface is formed by the first terminal set exposed out of the sheath member and the portion of the third terminal set exposed out of the sheath member. |
| US09136657B2 |
Annular signal feed module
An annular signal feed module is composed of a jack and a plug. The annular signal feed module includes the signal feed function of the traditional headphone. Besides, there is no jack hole in construction so that the moisture, water and dust intrusion are incapable to corrode and immerse the contacts and internal circuit parts, therefore, prolong the durability of the headphone signal feed device and the related electronic apparatuses such as televisions, stereos, cell phones and so forth. The present annular signal feed module is designed to integrate the features pertaining to no jack hole in construction of previous model patent certification no. M419356, and simplify the structural complexity, more than those, less modifications from traditional molds make it easier and convenient to be manufactured than product of patent no. M419356. |
| US09136656B2 |
Ethernet over coaxial coupling system, method and apparatus
A device that incorporates teachings of the present disclosure may include, for example, a controller to provide low loss connectivity to a plurality of coaxial ports over a wide range of frequencies from D.C. to 2 GigaHertz in a coaxial network providing Ethernet networking, detune secondary coaxial splitters in the coaxial network that reduces an output-to-output isolation loss among secondary coaxial splitter output ports, and enable re-distribution of modulated radio frequency video signals from any point on the coaxial network to any alternative point on the coaxial network. Other embodiments are disclosed. |
| US09136654B2 |
Quick mount connector for a coaxial cable
A post-less coaxial cable connector includes a body, a shell, a compression ring, and a coupling portion. The shell has a collapsible groove that, when the post-less coaxial cable connector is axially compressed, collapses and engages the coaxial cable. This provides pull strength and electrical communication in the post-less coaxial cable connector. The compression ring has projections, that when the post-less coaxial cable connector is axially compressed, engage the coaxial cable jacket, providing sealing at the back end and rotation torque. |
| US09136649B2 |
HDMI type-D connector
The present invention provides a HDMI type-D connector with a shield; a housing having a tongue with first terminal slots disposed on a first side and second terminal slots disposed on an opposing second side; a shield component; a first conductive set of pins disposed in the first terminal slots; and a second conductive set of pins disposed in the second terminal slots, wherein each of the conductive terminals of the first conductive set of pins and the second conductive set of pins has a contact portion, a bend portion, and a soldering portion, where contact portions of the first conductive set of pins are disposed in the first terminal slots and the second conductive set of pins are disposed in the second terminal slots wherein the bend portions extend from the contact portions, bend multiple times, and end at coplanar soldering portions. |
| US09136648B2 |
Din or panel ground integral to connector body
An electronics module housing includes an external recess adapted to receive an associated DIN rail or other associated mounting structure. A latch mechanism is associated with the external recess and is adapted to engage the DIN rail. An electronics circuit board is located in the housing. An electrical connector is physically and electrically connected to the circuit board. The electrical connector includes: (i) a connector body; (ii) a plurality of electrical contacts secured to said connector body and comprising contact pins physically and electrically connected to the circuit board; and (iii) a ground contact secured to the connector body and including a ground pin physically and electrically connected to said circuit board. The ground contact includes a ground contact body that extends from the connector body into the housing recess. The ground contact body includes a ground contact face located adjacent the recess and adapted to contact the associated DIN rail to which the module is mounted. |
| US09136647B2 |
Communication connector with crosstalk compensation
A communication connector comprising plug interface contacts having a plurality of conductor pairs, and corresponding cable connector contacts. A printed circuit board connects the plug interface contacts to respective cable connector contacts. The printed circuit board includes circuitry between a first conductor pair and a second conductor pair. The circuitry has a first mutually inductive coupling between a first conductor of the first conductor pair and a first conductor of the second conductor pair, a first capacitive coupling between the first conductor of the first conductor pair and the first conductor of the second conductor pair. The first capacitive coupling is approximately concurrent with the first mutually inductive coupling. A shunt capacitive coupling connects the first conductor of the second conductor pair to a second conductor of the second conductor pair. |
| US09136641B2 |
Single element wire to board connector
A single element electrical connector includes a single conductive contact element formed into a cage structure having a wire insert end and a wire contact end along a longitudinal centerline axis of the connector. The cage structure defines an upper pick-up surface having a surface area suitable for placement of a suction nozzle of a vacuum transfer device, as well as a pair of contact tines biased towards the centerline axis to define a contact pinch point for an exposed core of a wire inserted into the connector. A contact surface is defined by a member of the cage structure for electrical mating contact with a respective contact element on a component on which the connector is mounted. |
| US09136637B2 |
Electrical connector comprising a sealing element and assembly process
An electrical connector includes a connector body, the connector body having a plurality of seats for a plurality of terminal contacts. The electrical connector also includes at least one sealing element received in the connector body in a plane transverse to conductors associated with the plurality of terminal contacts, so as to provide a seal around the conductors. The connector body is provided with a guide passage for slidingly mounting a sealing layer within the connector body, by moving the sealing layer parallel to a plane thereof, in such a way that the sealing layer can be inserted into the connector body after the plurality of terminal contacts along with the respective conductors have been received in the connector body. The sealing layer engages slidingly around the conductors until a final mounting position is reached. |
| US09136636B2 |
Connector
A connector is provided that includes an insulation body and a plurality of contacts. The insulation includes a plurality of contact receiving grooves arranged in a row and the plurality of contacts are disposed in the plurality of contact receiving grooves. The plurality of contacts include a first group of contacts and a second group of contacts with a first pair of differential signal contacts and a second pair of differential signal contacts disposed at both sides of the first group of contacts, respectively. |
| US09136635B2 |
Terminal
For obtaining a terminal capable of being soldered to a substrate without causing trouble such as a short circuit or poor connection, a lead part 13 is plated with tin in a state joined to a joining part 42 of a carrier, and a notch part 44, whose thickness is thinned, cut by a cutter 51 from a soldering surface side for making connection to a conductor pattern is formed between the lead part 13 and the joining part 42. The notch part 44 is provided with a guide part for guiding the cutter 51 to a side of the joining part 42 and forming a fillet forming piece 17 made of a part of the notch part 44 on a side of the lead part 13 after cutting by the cutter 51. |
| US09136632B2 |
Electrical connector with reliable assembly effect
A connector includes a housing and a contact module received in the housing. The housing defines a receiving cavity for accommodating a complementary connector, a mounting space communicating with the receiving cavity, and a pair of mounting blocks located at opposite lateral sides of the mounting space. The contact module includes a base and a number of contacts fixed in the base. The base includes a pair of lateral side edges. Each contact includes a retaining portion fixed in the base and a contacting portion extending slantly from the retaining portion into the receiving space of the housing. The contacts include a pair of side contacts located at opposite outmost sides thereof. The retaining portion of each side contact is disposed with a protruding section protruding laterally beyond corresponding lateral side edge of the base to engage with respective mounting block formed on the housing. |
| US09136627B2 |
Flat circuit connector configured to provide enhanced connector stabilization
A flat circuit connector includes a first connector which is resin molded at an end part of a flat circuit body and a second connector including a terminal. The first connector includes a block part made of resin and a flange part. The flange part is integrally formed at a rear side in a direction in which the block part is fitted. A projecting wall is provided on a surface of the flange part which is parallel to a main surface of the flat circuit body. The second connector includes a first peripheral wall with which the block part is fitted, and a second peripheral wall which is integrally formed at the rear side of the first peripheral wall. The second peripheral wall is formed with a cut part in which the projecting wall is fitted. |
| US09136625B2 |
Connector assembly with plate for contact nesting and effective heat dissipation path
A connector assembly includes a plug connector and a receptacle connector mateable with each other. The plug connector includes a plug insulative housing and a pair of plug power contacts. The plug insulative housing includes a first plug cavity, a first plate cantileveredly extending into the first plug cavity, and upper and lower plug contact slots in communication with the first plug cavity. The pair of plug power contacts are respectively received in the upper and lower plug contact slots. Each plug power contact includes a flat contacting section exposed to the first plug cavity and a first soldering section. The flat contacting sections are positioned on upper and lower surfaces of the first plate, respectively. The plug connector and the receptacle connector define heat dissipation channels in communication with each other in order that generating heat can be effectively dissipated to the air. |
| US09136616B2 |
Electrical connector assembly with improved metallic cover
An electrical connector assembly (100) includes a securing box (3) and a electrical connector (2). The securing box (3) includes a box portion (31) for receiving the electrical connector (2). The electrical connector (2) includes an insulative housing (20), a number of terminals (21) retained in the insulative housing (20) and a metallic cover (22) covering the insulative housing (20). The metallic cover (22) includes a pair of cantilever arm (225) extending forwardly and outwardly from two sides thereof. The box portion (31) includes corresponding an extraction slot (317) and a locating slot (314) for receiving the cantilever arm (225), the extraction slot is used to remove the electrical connector by a tool inserted thereof and therefore, the electrical connector (100) can be easily assembled or replaced from an electronic equipment. |
| US09136615B2 |
Shelf lighting connector assembly
A shelf lighting connector assembly provides an electrical connection between a power strip on a wall and a light mounted on the underside of a shelf mounted on the wall. |
| US09136614B2 |
Conductor connection tool and relay unit using the same
A conductor connection tool includes a terminal platform base, a conduction fitting accommodated in a fitting recessed part of the terminal platform base. The conduction fitting is formed in a substantially U shape and includes a bottom plate portion, a vertical portion bent vertically upward from one end of the bottom plate portion, and an attachment portion extending from an upper end of the vertical portion in parallel to the bottom plate portion, and having a terminal portion extending in the opposite direction to the attachment portion. A plate spring bent in a substantially V shape with one side serving as an attachment piece to be fixed to the attachment portion of the conduction fitting with the other side serving as a locking piece whose front end is to be brought into pressure contact with the bottom plate portion of the conduction fitting. |
| US09136612B2 |
Front-end apparatus of wireless transceiver using RF passive elements
Disclosed is a front-end apparatus of an RF transceiver connected with an antenna in a wireless communication system. The front-end apparatus of an RF transceiver using radio-frequency passive elements includes: a plurality of band pass filters configured a transmission signal and a reception signal; a first circulator configured to output a first transmission signal to a second terminal and output a second reception signal input; a second circulator configured to output a second transmission signal input into the first terminal to the second terminal and output a first reception signal input into the second terminal to the third terminal; a passive directional double pole and double throw switch configured to process a route to be changed depending on directions of an input and an output; a first antenna configured to transmit the first transmission signal; and a second antenna configured to transmit the second transmission. |
| US09136611B2 |
Blade antenna array
A directional antenna system for an aircraft is disclosed. The directional antenna system may include an enclosure, a linear antenna array disposed within the enclosure and a controller. The linear antenna array may include a plurality of antenna elements physically oriented in the same orientation. The plurality of antenna elements may be positioned along a longitudinal axis of the aircraft and spaced apart from each other by a predetermined distance center-to-center. The controller may be in communication with each of the plurality of antenna elements of the linear antenna array. The controller may be configured for independently controlling a RF phase angle of each of the plurality of antenna elements based on a position of the aircraft and at least one ground station available to the aircraft, allowing the linear antenna array to concentrate RF radiations in a particular wavelength toward a general direction. |
| US09136606B2 |
Electrically large stepped-wall and smooth-wall horns for spot beam applications
Electrically large, stepped-wall or smooth-wall, direct-radiating horn antenna apparatus that may preferably be used in satellite spot beam applications. Exemplary electrically large smooth-wall horn antenna apparatus comprises one or more input ports, an electrically large output port, and a smooth-wall or stepped-wall tapered section having a spline-shaped profile extending from the input port(s) to the output port of the apparatus. The spline-shaped profile is preferably monotonic and is preferably configured to generate a spot beam. The spline-shaped profile may be configured to support multiple frequency bands, and dual simultaneous polarization having either linear or circular polarization. The spline-shaped profile is defined by spline knots, and, the knot radii form a nondecreasing sequence. Preferably, the spline-shaped profile comprises a piecewise cubic Hermite interpolating polynomial spline that interpolates the shape of curves between the spline knots. |
| US09136604B2 |
Antenna and wireless communication apparatus
An antenna comprises a medium substrate and grounding units attached on the medium substrate. The antenna further comprises a metal structure attached on the medium substrate. The metal structure comprises an electromagnetic response unit, a metal open ring enclosing the electromagnetic response unit and a feeding point connected to an end of the metal open ring. The electromagnetic response unit comprises an electric-field coupling structure. This design increases the physical length of the antenna equivalently, so an RF antenna operating at an extremely low frequency can be designed within a very small space. This can eliminate the physical limitation imposed by the spatial area when the conventional antenna operates at a low frequency, and satisfy the requirements of miniaturization, a low operating frequency and broadband multi-mode services for the mobile phone antenna. Meanwhile, a solution of a lower cost is provided for design of the antenna of wireless communication apparatuses. |
| US09136599B2 |
Broadband antenna and wireless communication device empolying same
A broadband antenna for wireless communication device is disclosed. The broadband antenna includes a main radiator, a grounding unit, a feeding unit, and a resonating unit. The main radiator includes a main radiating portion, a first radiating arm extending from the main radiating portion, and a second radiating arm extending from the main radiating arm, the first radiating arm forms a first current path to generate a first high frequency mode; the second radiating arm forms a second current path to generate a second high frequency mode. The resonating unit is connected to the grounding unit, the resonating unit surrounds and is positioned separate from the second radiating arm, the resonating unit resonates with the main radiator to generate two different low frequency bands corresponding to two coupling currents. |
| US09136597B2 |
Mat based antenna system to detect transponder tagged objects, for example during medical procedures
A mat based antenna system allows medical personnel to ascertain the presence or absence of objects (e.g., medical implements, medical supplies) tagged with transponders in an environment in which medical procedures (e.g., surgery) are performed, and may allow reading of information from the transponders, writing information to the transponders and/or controlling or commanding the transponders. In use, the mat based antenna system may be positioned beneath a patient, such as during surgery or child birth. A controller is coupled to the antennas to transmit signals (e.g. interrogation signals) to the transponders and to receive signals (e.g., response signals) from the transponders. |
| US09136595B2 |
Diversity antenna module and associated method for a user equipment (UE) device
A diversity antenna module comprising a first radiating element adapted to operate with a first transceiver circuit operating in at least one band and a second radiating element adapted to operate with a second transceiver circuit operating in at least one band. The first radiating element is disposed along a first side of a substrate and the second radiating element is disposed along a second side of the substrate, wherein the first and second sides are substantially parallel to each other, the first and second radiating elements being spatially dispersed from each another by a distance. |
| US09136592B2 |
Ink for printing a mobile phone antenna pattern, method for manufacturing a synthetic resin part for a mobile phone on which an antenna pattern is printed using the ink, and synthetic resin part for a mobile phone on which an antenna pattern is printed
The ink for printing an antenna pattern for a mobile phone according to an embodiment of the present invention includes a mixture of one of silver (Ag) powder, nickel (Ni) powder, copper (Cu) powder, and gold (Au) powder, liquid acrylonitrile, liquid polystyrene, liquid butadiene, and methyl ethyl ketone (MEK) as a diluent. The present invention does not include a plating process, and thus allows a significant improvement in productivity. |
| US09136590B2 |
Electronic device provided with antenna device
In an electronic device, a first housing for receiving a wireless circuit unit and a ground part, a second housing in which a ground part, a hinge mechanism which connects the first and second housings to each other to allow the first and second housings to be rotated, and first and second antennas which resonate for the same frequency band. The first and second antennas are provided in an intermediate portion of the hinge mechanism, and arranged side by side and apart from each other by a predetermined distance in a longitudinal direction of the mechanism. In the mechanism, one of end portions of the mechanism is made electrically conductive, and the other end portion is decreased in electrical conductivity. |
| US09136589B2 |
Antenna apparatus, electronic apparatus having an antenna apparatus, and method of manufacturing the same
An antenna apparatus, an electronic apparatus having an antenna apparatus, and a method of manufacturing the same. The antenna apparatus includes a window, an antenna pattern, a first contact structure, a substrate and a second contact structure. The antenna pattern is embedded in the window. The first contact structure is electrically connected to the antenna pattern. The substrate is disposed under the window. The second contact structure is disposed on the substrate and is electrically connected to the first contact structure. The second contact structure includes a first contact, a second contact spaced apart from the first contact in a direction substantially perpendicular to the top surface of the substrate and a buffer member having a predetermined elasticity and electrically connecting the first contact with the second contact. |
| US09136578B2 |
Recombinant waveguide power combiner / divider
In an example embodiment, an in-phase recombinant waveguide combiner/divider device can comprise: a single waveguide input; N waveguide outputs, wherein N is an integer greater than 2; a first waveguide dividing portion; a second waveguide dividing portion; a third waveguide dividing portion; and a waveguide combining portion. The waveguide combining portion can be configured to combine two signals that are each respectively received from the second waveguide dividing portion and third waveguide dividing portion. In general an in-phase recombinant waveguide combiner/divider can comprise more junctions than output ports of a conservative power divider network structure. In an example embodiment, for a N-way waveguide power divider, there can be at least N+1 waveguide junctions. |
| US09136571B2 |
Driver assistance device for a vehicle, vehicle and method for operating a radar apparatus
The invention relates to a driver assistance device (2) for a vehicle (1), having a radar apparatus (3, 4) for detecting objects which are external to the vehicle, which radar apparatus (3, 4) has an antenna unit (14) for irradiating and/or receiving electromagnetic waves (S0, SE) and a damping element (24, 25, 26) which is coupled to the antenna unit (14) and has the purpose of directing and damping the electromagnetic waves (S0, SE), by means of which damping element (24, 25, 26) the antenna unit (14) can be coupled to a transmitter and/or receiver device (16, 17) of the radar apparatus (3, 4), wherein the damping element (24, 25, 26) has a branching unit (31) with a first line branch (32) for directing the damped electromagnetic waves (S0, SE) between the transmitter and/or receiver device (16, 17), on the one hand and the antenna unit (14) on the other, as well as a second line branch (33) which is coupled to the first line branch (32) and is terminated with a reflection-free terminating element (35, 37). The invention also relates to a corresponding method. |
| US09136562B2 |
Multiple electrolyte electrochemical cells
Electrode assemblies for use in electrochemical cells are provided. The negative electrode assembly comprises negative electrode active material and an electrolyte chosen specifically for its useful properties in the negative electrode. These properties include reductive stability and ability to accommodate expansion and contraction of the negative electrode active material. Similarly, the positive electrode assembly comprises positive electrode active material and an electrolyte chosen specifically for its useful properties in the positive electrode. These properties include oxidative stability and the ability to prevent dissolution of transition metals used in the positive electrode active material. A third electrolyte can be used as separator between the negative electrode and the positive electrode. |
| US09136559B2 |
Non-aqueous electrolyte and lithium secondary battery including the same
A non-aqueous electrolyte including a lithium salt, an organic solvent, and an electrolyte additive is provided. The electrolyte additive is a meta-stable state nitrogen-containing polymer formed by reacting Compound (A) and Compound (B). Compound (A) is a monomer having a reactive terminal functional group. Compound (B) is a heterocyclic amino aromatic derivative as an initiator. A molar ratio of Compound (A) to Compound (B) is from 10:1 to 1:10. A lithium secondary battery containing the non-aqueous electrolyte is further provided. The non-aqueous electrolyte of this disclosure has a higher decomposition voltage than a conventional non-aqueous electrolyte, such that the safety of the battery during overcharge or at high temperature caused by short-circuit current is improved. |
| US09136544B2 |
Dual layer solid state batteries
Methods for fabrication of electronic systems and systems therefrom are provided. An electronic system includes a first substrate (202) having a first surface (202a) and a second substrate (208) having a second surface (208a) facing the first surface. The system also includes a plurality of battery cell layers (106-112) disposed on a plurality of laterally spaced areas on the first and second surfaces (203, 209). In the system, portions of the battery cell layers on the first surface are in physical contact with portions of the battery cell layers on the second surface and the battery cell layers on the first surface and the second surface form a plurality of electrically interconnected battery cells (206, 212) on the first and the second surfaces that are laterally spaced apart and that define one or more batteries (200). |
| US09136543B2 |
Battery system having battery module, thermal switch, heating source and pin structure
A battery system (100) having a heating element (124), a thermal switch (130), a battery module (140), and a pin structure (170) is disclosed. The battery system (100) comprises: a battery case (110) forming an internal space; a battery module (140) located in the battery case and including a battery; a heating element structure (120) located in the battery case (110) and increasing the temperature of the battery System by heat generated by an impact; and a pin structure (170) for concentrating and transferring an external impact to a pre determined region of the heating element structure. |
| US09136538B2 |
Rechargeable battery having current collection plate with protrusion
A rechargeable battery including an electrode assembly including first and second electrode plates, each of which includes an electrode uncoated portion and a separator interposed between the first and second electrode plates, and at least one current collector plate, each current collector plate contacting one of the electrode uncoated portions of the first and second electrode plates, wherein each current collector plate includes a protrusion protruding toward the electrode assembly and having a contact portion contacting one of the electrode uncoated portions, and a slit in the contact portion disposed at a predetermined angle with respect to the direction of the electrode assembly. |
| US09136536B2 |
Method of making cohesive carbon assembly and its applications
Cohesive carbon assemblies are prepared by obtaining a functionalized carbon starting material in the form of powder, particles, flakes, loose agglomerates, aqueous wet cake, or aqueous slurry, dispersing the carbon in water by mechanical agitation and/or refluxing, and substantially removing the water, typically by evaporation, whereby the cohesive assembly of carbon is formed. The method is suitable for preparing free-standing, monolithic assemblies of carbon nanotubes in the form of films, wafers, discs, fiber, or wire, having high carbon packing density and low electrical resistivity. The method is also suitable for preparing substrates coated with an adherent cohesive carbon assembly. The assemblies have various potential applications, such as electrodes or current collectors in electrochemical capacitors, fuel cells, and batteries, or as transparent conductors, conductive inks, pastes, and coatings. |
| US09136532B2 |
Active material for battery, nonaqueous electrolyte battery, and battery pack
According to one embodiment, there is provided a active material for a battery including a complex oxide containing niobium and titanium. A ratio MNb/MTi of a mole of niobium MNb to a mole of titanium MTi in the active material satisfies either the following equation (I) or (II). 0.5≦MNb/MTi<2 (I) 2 |
| US09136529B2 |
Method of charging and discharging a non-aqueous electrolyte secondary battery
Good cycle performance is obtained with a non-aqueous electrolyte secondary battery having a positive electrode, a negative electrode, and a non-aqueous electrolyte. The positive electrode contains as positive electrode active material a mixture of a lithium-manganese composite oxide and a lithium-transition metal composite oxide containing at least Ni and Mn as transition metals. The negative electrode contains as a negative electrode active material a material capable of intercalating and deintercalating lithium. Charging of the non-aqueous electrolyte secondary battery is controlled so that the end-of-charge voltage becomes higher than 4.3 V. |
| US09136525B2 |
Negative-electrode active material, and method for production of negative-electrode active material
A negative-electrode active material characterized by containing a silicon oxide represented by a general formula SiOx (0 |
| US09136524B2 |
Secondary battery
A secondary battery includes an electrode assembly, a case configured to accommodate the electrode assembly, a cap plate configured to seal the case, the cap plate including openings, first and second terminals electrically connected to the electrode assembly and inserted through respective openings of the cap plate, an insulating member between the cap plate and at least one of the first and second terminals, the insulating member including a penetration hole, and a fuse in the penetration hole of the insulating member, the fuse electrically connecting the cap plate and the first terminal. |
| US09136523B2 |
Rechargeable battery
A rechargeable battery includes an electrode assembly inside a case, a terminal post located entirely outside of, and protruding outwardly from, the case, a connection terminal having a portion that passes through the case, the connection terminal electrically coupling the electrode assembly and the terminal post; and a sealing member enveloping the portion of the connection terminal that passes through the case and electrically insulating the connection terminal from the case. |
| US09136520B2 |
Battery module
A battery module according to the present invention includes rechargeable batteries that include a first terminal and a second terminal which protrude outward, the first terminal including differentiation portions formed of an indentation or a protruding portion to differentiate the first terminal from the second terminal; and connection members that electrically connect the rechargeable batteries, fixed to the first and second terminals of adjacent rechargeable batteries, including verification portions which fit the differentiation portions so as to improve assemblability and minimize contact resistance. |
| US09136519B2 |
Cap assembly and battery pack having the same
A cap assembly and a battery pack having the same. The cap assembly includes: a cap plate including: a first surface; and a second surface opposite to the first surface, wherein a first hole penetrates through the cap plate from the first surface to the second surface; a first electrode terminal including: an upper terminal on the first surface of the cap plate; a lower terminal on the second surface of the cap plate; and a connection part that connects the upper terminal to the lower terminal through the first hole; a temperature protection device on an upper surface of the upper terminal; and an insulation part interposed between the cap plate and the first electrode terminal and including a first groove. Here, the upper terminal and the temperature protection device are in the first groove. |
| US09136518B2 |
Terminal for accumulator cells
A terminal (3a . . . 3h) for the electrical connection of a plurality of electrochemical cells (2) of a accumulator, which terminal comprises a U-shaped outer rail (4a . . . 4f) and an actuating element (5a . . . 5g), is described. According to the invention, the actuating element (5a . . . 5g) is coupled to a clamping element (6a . . . 6f . . . 6h) in such a way that the clamping element (6a . . . 6f . . . 6h) is pressed against at least one limb (4a′ . . . 4f′) of the outer rail (4a . . . 4f) on actuation of the actuating element (5a . . . 5g). |
| US09136513B2 |
Battery pack
A battery pack includes one or more battery cells arranged in one direction and electrically connected to one another, a battery management system (BMS) substrate connected to electrode terminals of the battery cells and configured to control charging and discharging of the battery cells, a housing with a space to receive the battery cells, an upper cover connected to an upper part of the housing, and a connector connected to the BMS substrate, the connector protruding above and extending along an upper surface of the upper cover. |
| US09136512B2 |
Battery pack having parallel connector
Provided is a battery pack including a plurality of battery cells including at least one row of battery cells, an electrode tab connecting the plurality of battery cells to each other in parallel, and a bus bar coupled to the electrode tab, wherein the electrode tab includes a main plate extending parallel to the at least one row of battery cells, welding parts protruding from the main plate towards the battery cells, the welding parts being connected to electrode terminals of the battery cells, and connecting parts protruding opposite the welding parts, the connecting parts being connected to the bus bar. |
| US09136510B2 |
Sealing and folding battery packs
In a first embodiment, a battery pouch is provided with a pouch edge positioned to project from an underside of the battery. The pouch edge is sealed and folded toward the underside of the battery. The folded pouch edge increases a vertical dimension of the resulting battery assembly, but not a horizontal dimension. In a second embodiment, a battery pouch is provided with a first pouch edge positioned on a first edge of the battery and a second pouch edge positioned on a second edge of the battery. The battery pouch is configured such that at least one cut-out portion is positioned between either the first and second edge of the battery or between the first and second pouch edges. When the first and second ouch edges are sealed and folded upward, the folding does not cause creases that increase a horizontal dimension of the battery assembly. |
| US09136509B2 |
Battery cell with an integrated pouch metal foil terminal
A battery includes a battery cell having a pair of cell electrodes that are encased in a laminated pouch. The laminated pouch has a conductive moisture barrier layer that is sandwiched between respective electrically insulating layers. Several terminals are integrated with the pouch, including a first terminal and a second terminal that are directly connected to the first and second cell electrodes, respectively, and a third terminal that is directly connected to the conductive moister barrier layer. Other embodiments are also described and claimed. |
| US09136507B2 |
Can and lithium secondary battery using the same
A can for a lithium secondary battery and a lithium secondary battery using the same, where guide slots are formed in a bottom wall and a sidewall of the can of the lithium secondary battery so that the can is symmetrically bent about a longitudinal axis thereof when the lithium secondary battery is compressed in a direction orthogonal to the longitudinal axis, thus preventing a short circuit from occurring between electrode plates of the of the electrode assembly located within the can resulting in improved safety of the lithium secondary battery. Alternatively, embossing portions are formed in a bottom wall of the can for the lithium secondary battery while protruding toward an inner portion of the can, so that the bottom wall of the can is outwardly bent when the lithium secondary battery is subject to compression in a direction orthogonal to the longitudinal axis, resulting in improved safety of the lithium secondary battery. |
| US09136506B2 |
Thin-film transistor array substrate, organic light-emitting display having the same, and method of manufacturing the organic light-emitting display
A thin-film transistor array substrate, an organic light-emitting display having the same, and a method of manufacturing the organic light-emitting display are disclosed. In one embodiment, the thin-film transistor array substrate includes a buffer layer formed on a substrate, a first insulating layer formed on the buffer layer, a pixel electrode formed on the first insulating layer using a transparent conductive material, an intermediate layer that covers an upper side and outer side-surfaces of the pixel electrode and includes a organic light-emitting layer, a gap formed by etching the first insulating layer and the buffer layer at a peripheral of the pixel electrode, and a facing electrode that is formed on an upper side and outer side-surfaces of the pixel electrode to cover the intermediate layer and the gap. |
| US09136505B2 |
Light-emitting device, electronic device, and lighting device
Provided is a light-emitting device having a light-emitting portion having a light-emitting element in a space surrounded by a support substrate, a metal substrate, and a sealing material, in which the sealing material is provided to surround the periphery of the light-emitting portion, the light-emitting element has a first electrode, a layer having a light-emitting organic compound, and a second electrode, the support substrate and the first electrode are each capable of transmitting light emitted from the light-emitting organic compound, and the space contains gas inert to the light-emitting element or is in a vacuum. The light-emitting device has, over the second electrode, a first high-emissivity layer that has higher emissivity than the second electrode and is thermally connected to the second electrode, and a low-reflectivity layer with which a metal substrate surface facing the support substrate is provided and which has lower reflectivity than the metal substrate. |
| US09136504B2 |
Organic electroluminescent device
An organic electroluminescent device comprising: a transparent substrate; a first electrode disposed over the substrate for injecting charge of a first polarity; a second electrode disposed over the first electrode for injecting charge of a second polarity opposite to said first polarity; an organic light-emitting layer disposed between the first and the second electrode, wherein the second electrode is reflective, the first electrode is transparent or semi-transparent, and one or more intermediate layers of dielectric material with a refractive index greater than 1.8 or a metal material is disposed between the substrate and the first electrode forming a semi-transparent mirror whereby a microcavity is provided between the reflective second electrode and the semi-transparent mirror, all the intermediate layers disposed between the substrate and the first electrode having a surface nearest the organic light-emitting layer not more than 150 nm from a surface of the first electrode nearest the organic light-emitting layer. |
| US09136500B2 |
Display panel and method for fabricating the same
A display panel and a method for fabricating the same are provided. The display panel includes a substrate, a transparent film, and a light-gathering film. The substrate includes organic light emitting diode (OLED) elements. The transparent film is disposed on the substrate. The light-gathering film is disposed on the transparent film. In the fabrication method of the display panel, a substrate is first provided, in which the substrate includes OLED elements. Then, a transparent film is provided, in which the transparent film has a first surface and a second surface opposite to the first surface. Thereafter, a light-gathering material is coated to form a light-gathering film on the first surface of the transparent film. Then, a sensing layer is disposed on the second surface of the transparent film. Thereafter, the transparent film is disposed on the substrate to sandwich the sensing layer between the transparent film and the substrate. |
| US09136498B2 |
Apparatus and method for modulating photon output of a quantum dot light emitting device
An apparatus is provided for modulating the photon output of a plurality of free standing quantum dots. The apparatus comprises a first electron injection layer (210, 310, 410) disposed between a first electrode (212, 312, 412) and a layer (208, 308, 408) of the plurality of free standing quantum dots. A hole transport layer (206, 306, 406) is disposed between the layer (208, 308, 408) of the plurality of quantum dots and a second electrode (204, 304, 404). A light source (224, 324, 424) is disposed so as to apply light to the layer (208, 308, 408) of the plurality of free standing quantum dots. The photon output of the layer (208, 308, 408) of the plurality of free standing quantum dots is modulated by applying a voltage to the first and second electrodes (212, 312, 412, 204, 304, 404). Electrons excited to a higher energy state within layer (208, 308, 408) of the free standing quantum dots by the light source (224, 324, 424) are prevented from returning to a lower state by electrons from the electric field of the applied voltage, and therefore the free standing quantum dots are prevented from emitting a photon. The voltage source (216, 316, 416) may be modulated to vary the photon output. |
| US09136497B2 |
Organic electroluminescence generating devices
An electroluminescence generating device comprising a channel of organic semiconductor material, said channel being able to carry both types of charge carriers, said charge carriers being electrons and holes; an electron electrode, said electron electrode being in contact with said channel and positioned on top of a first side of said channel layer or within said channel layer, said electron electrode being able to inject electrons in said channel layer; a hole electrode, said hole electrode being spaced apart from said electron electrode, said hole channel and positioned on top of within said channel layer, said hole electrode being able to inject holes into said channel; a control electrode positioned on said first side or on a second side of said channel; whereby light emission of said electroluminescence generating device can be acquired by applying an electrical potential difference between said electron electrode and said hole electrode. |
| US09136495B2 |
Organic light-emitting device
An organic light-emitting device including a first electrode, a plurality of hole transport layers, a plurality of intermediate layers, an emission layer, a plurality of electron transport layers, and a second electrode. The emission layer may include a host, an emitting dopant, and an auxiliary dopant. The host and the auxiliary dopant are able to transport different types of carriers. |
| US09136494B2 |
White light emitting material
A white light emitting material comprising a polymer having an emitting polymer chain and at least one emitting end capping group. |
| US09136491B2 |
Organic electroluminescent element and method for producing the same
The problem to be solved by the present invention is to prolong the luminance half life of an organic EL element. A means for solving the problem is a method for producing an organic electroluminescent element comprising a first electrode that is formed first, a second electrode that is formed later, and a light-emitting layer that is formed between the first electrode and the second electrode, the method comprising the steps of applying a solution containing a light-emitting organic material to a surface of a layer located below to form an applied film; calcining the applied film in an inert gas atmosphere or in a vacuum atmosphere to form a light-emitting layer; holding the surrounding of the formed light-emitting layer in an inert gas atmosphere or in a vacuum atmosphere; and forming a layer located on the light-emitting layer in an inert gas atmosphere or in a vacuum atmosphere. |
| US09136487B2 |
Flexible display device and method of manufacturing the same
A flexible display device is discussed. The flexible display device according to an embodiment includes an insulating and flexible substrate on which an adhesive layer is formed, a support layer adhered to the substrate via the adhesive layer, a cell array formed above the support layer, defining a plurality of pixel regions, and including a ground line connected to a ground voltage source of an external circuit, a light emitting array including a plurality of light emitting structures formed on the cell array, a sealing layer formed on the cell array, and a buffer layer, a shielding layer, and a bottom insulating layer formed between the support layer and the cell array. The light emitting array emits light toward the sealing layer, and the ground line is connected to the shielding layer through a contact hole to partially expose the shielding layer. |
| US09136486B2 |
Composition for organic semiconductor insulating films, and organic semiconductor insulating film
The purpose of the invention is to provide: a composition for an organic semiconductor insulating film, which is capable of forming an insulating film that exhibits excellent hydrophobicity and smoothness of the surface, while having excellent electrical stability; and an organic semiconductor insulating film obtained by using the composition for an organic semiconductor insulating film. The present composition contains a polysiloxane and an organic polymer compound. The polysiloxane is a polyhedral silsesquioxane having an oxetanyl group and/or an oxetanyl group containing silicon compound represented by the following formula (1). In the formula (1), each of R1-R3 independently represents a monovalent organic group (provided that at least one of R1-R3 is a monovalent organic group having an oxetanyl group); and each of v, w, x and y independently represents 0 or a positive number (provided that w and at least one of v, x and y are positive numbers). |
| US09136485B2 |
Compound and organic light-emitting diode, display and illuminating device using the compound
According to one embodiment, there is provided a compound represented by Formula (1): where Cu+ represents a copper ion, each of R1 and R2 represents a linear, branched or cyclic alkyl group or an aromatic cyclic group which may have a substituent, each of R3, R4, R5 and R6 represents a halogen atom, a cyano group, a nitro group, a linear, branched or cyclic alkyl group or H, and X− represents a counter ion where X is selected from the group consisting of F, Cl, Br, I, BF4, PF6, CH3CO2, CF3CO2, CF3SO3 and ClO4. |
| US09136481B2 |
Compound for an organic photoelectric device, organic photoelectric device including the same, and display device including the organic photoelectric device
A compound for an organic photoelectric device, an organic photoelectric device including the same, and a display device including the organic photoelectric device, the compound being represented by the following Chemical Formula 1: |
| US09136479B2 |
Organic compound, anthracene derivative, and light-emitting element, light-emitting device, and electronic device using the anthracene derivative
Objects of the present invention are to provide novel anthracene derivatives and novel organic compounds; a light-emitting element that has high emission efficiency; a light-emitting element that is capable of emitting blue light with high luminous efficiency; a light-emitting element that is capable of operation for a long time; and a light-emitting device and an electronic device that have lower power consumption. An anthracene derivative represented by a general formula (1) and an organic compound represented by a general formula (17) are provided. A light-emitting element that has high emission efficiency can be obtained by use of the anthracene derivative represented by the general formula (1). Further, a light-emitting element that has a long life can be obtained by use of the anthracene derivative represented by the general formula (1). |
| US09136475B2 |
Organic EL element and method for producing same
The present invention is to provide a method of favorably forming an organic EL device with the inverted structure by the wet process. On that account, an organic EL device includes a cathode, an electron injection layer, a light emitting layer, a hole transport layer, a hole injection layer, an anode are formed in this order on a substrate. The electron injection layer is formed by applying ink between banks and drying the ink. The ink is formed by dissolving a polymer compound having an organic phosphine oxide skeleton in an alcohol solvent. The light emitting layer is formed by applying ink between components of the bank and the drying the ink. The ink is formed by dissolving material for light emitting layer such as polyphenylene vinylene (PPV) derivative or polyfluorene derivative in a nonpolar solvent. |
| US09136474B2 |
Method of fabricating phase-change random access memory device
A method of fabricating a semiconductor device is provided. The method includes forming semiconductor patterns on a semiconductor substrate, such that sides are surrounded by a lower interlayer insulating layer. A lower insulating layer is formed that covers the semiconductor patterns and the lower interlayer insulating layer. A contact structure is formed that penetrates the lower insulating layer and the lower interlayer insulating layer and is spaced apart from the semiconductor patterns. The contact structure has an upper surface higher than the semiconductor patterns. An upper insulating layer is formed covering the contact structure and the lower insulating layer. The upper and lower insulating layers form insulating patterns exposing the semiconductor patterns and covering the contact structure, and each of the insulating patterns includes a lower insulating pattern and an upper insulating pattern sequentially stacked. After the insulating patterns are formed, metal-semiconductor compounds are formed on the exposed semiconductor patterns. |
| US09136470B2 |
Memory element with ion conductor layer in which metal ions diffuse and memory device incorporating same
The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions. |
| US09136468B2 |
Nonvolatile semiconductor memory device
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other. |
| US09136466B2 |
Phase-change random access memory device and method of manufacturing the same
A phase change random access memory device includes a bottom electrode contact formed within a bottom electrode contact hole, a phase-change material pattern formed to surround a side of an upper portion of the bottom electrode contact, and an insulating layer buried within the phase-change material pattern and formed on an upper surface of the bottom electrode contact. |
| US09136463B2 |
Method of forming a magnetic tunnel junction structure
In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) structure including a conductive layer on a substrate. The method also includes depositing a sacrificial layer on the conductive layer before depositing a patterning film layer. |
| US09136458B2 |
Elastic wave element
An elastic wave element includes a piezoelectric substrate, an IDT electrode, and a first dielectric film. The IDT electrode includes a first bus bar electrode, a second bus bar electrode, first electrode fingers, and second electrode fingers. The piezoelectric substrate includes a bus bar electrode region, an alternately disposed region, and an intermediate region. The first dielectric film is formed in at least a part of the intermediate region, and formed of a medium in which acoustic velocity of a transverse wave propagating in the first dielectric film is lower than acoustic velocity of a main elastic wave in the alternately disposed region. |
| US09136450B2 |
Light emitting device
A light emitting device is provided with a base member, an interconnect pattern disposed on an upper surface of the base member, a light reflecting layer comprising a first layer disposed on a part of the interconnect pattern and formed from a metal material, and a second layer made of a dielectric multilayer reflecting film made with stacked layers of dielectric films having different refractive indices and covering an upper surface and side surfaces of the first layer, a light emitting element chip fixed so as to face at least a part of the light reflecting layer, and a light transmissive sealing member sealing the light reflecting layer and the light emitting element chip. |
| US09136449B2 |
Light emitting package
A light emitting device package may be provided that includes: a substrate; a first light emitting chip disposed on the substrate; a plurality of second light emitting chips disposed on the outer circumference of the first light emitting chip; and a lens formed on the first and the second light emitting chips. |
| US09136442B2 |
Multi-vertical LED packaging structure
The present disclosure involves a light-emitting diode (LED) packaging structure. The LED packaging structure includes a submount having a substrate and a plurality of bond pads on the substrate. The LED packaging structure includes a plurality of p-type LEDs bonded to the substrate through a first subset of the bond pads. The LED packaging structure includes a plurality of n-type LEDs bonded to the substrate through a second subset of the bond pads. Some of the bond pads belong to both the first subset and the second subset of the bond pads. The p-type LEDs and the n-type LEDs are arranged as alternating pairs. The LED packaging structure includes a plurality of transparent and conductive components each disposed over and electrically interconnecting one of the pairs of the p-type and n-type LEDs. The LED packaging structure includes one or more lenses disposed over the n-type LEDs and the p-type LEDs. |
| US09136436B2 |
Optoelectronic device and the manufacturing method thereof
An optoelectronic device comprises a semiconductor stack having a first surface, a contact layer having a first pattern on the first surface for ohmically contacting the semiconductor stack, a void in the semiconductor stack and surrounding the contact layer, and a mirror structure on the first surface and covering the contact layer, wherein the first surface has a first portion which is not covered by the contact layer and a second portion covered by the contact layer, and the first portion is rougher than the second portion. |
| US09136435B2 |
Semiconductor light-emitting element
A semiconductor light-emitting element includes a support substrate, a semiconductor film including a light-emitting layer provided on the support substrate, a surface electrode provided on a light-extraction-surface-side surface of the semiconductor film, and a light-reflecting layer provided between the support substrate and the semiconductor film, forming a light-reflecting surface. The surface electrode includes a first electrode piece and a second electrode piece. The light-reflecting layer includes a reflection electrode including a third electrode piece and a fourth electrode piece. The first electrode piece and the third electrode piece are arranged so as to not overlap when projected onto a projection surface parallel to a principal surface of the semiconductor film, and the shortest distance between the first electrode piece and the fourth electrode piece, is greater than the shortest distance between the first electrode piece and the third electrode piece. |
| US09136427B2 |
Light emitting diode and method of fabricating the same
Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer. |
| US09136421B2 |
Wide area array type photonic crystal photomixer for generating and detecting broadband terahertz wave
Provided is a broadband photomixer technology that is a core to generate continuous frequency variable and pulsed terahertz waves. It is possible to enhance light absorptance by applying the transmittance characteristic of a 2D light crystal structure and it is possible to increase the generation efficiency of terahertz waves accordingly. Moreover, it is possible to implement a wide area array type terahertz photomixer by applying an interdigit structure and spatially properly arranging a light crystal structure having various cycles. Accordingly, it is possible to solve difficulty in thermal characteristic and light alignment by mitigating the high light density of a light absorption unit and low photoelectric conversion efficiency is drastically improved. In addition, the radiation pattern of terahertz waves may be electrically controlled through the present invention. |
| US09136418B2 |
Optoelectronic devices including heterojunction and intermediate layer
Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer. |
| US09136412B2 |
Reconfigurable solar panel
A reconfigurable solar panel that provides for the repair, replacement, modification and upgrade of various solar panel components. |
| US09136408B2 |
Perovskite and other solar cell materials
Photovoltaic devices such as solar cells, hybrid solar cell-batteries, and other such devices may include an active layer having perovskite material and copper-oxide or other metal-oxide charge transport material. Such charge transport material may be disposed adjacent to the perovskite material such that the two are adjacent and/or in contact. Inclusion of both materials in an active layer of a photovoltaic device may improve device performance. Other materials may be included to further improve device performance, such as, for example: one or more interfacial layers, one or more mesoporous layers, and one or more dyes. |
| US09136407B2 |
Solid-state image sensor, method of manufacturing the same, and camera
A method of manufacturing a solid-state image sensor having a first charge accumulation region, a second charge accumulation region, includes implanting ions into a semiconductor substrate through first and second openings of a mask to form the first and second charge accumulation regions. The implanting ions includes a first implantation of implanting ions into a portion below a first transfer gate, and a second implantation of implanting ions into a portion below a second transfer gate in a direction different from a direction of the first implantation. |
| US09136406B2 |
Solar cell assembly with diffraction gratings
A solar cell structure using either a dye-sensitized or organic absorber is provided with a diffraction grating on at least one side to enhance the travel of first order diffraction components through the photo sensitive material. A two-sided cell uses diffraction gratings both top and bottom wherein the periodic diffraction elements of one grating are shifted by one-quarter of the grating period relative to the other. |
| US09136401B2 |
Compound semiconductor device and method of manufacturing the same
A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer. |
| US09136396B2 |
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other. |
| US09136395B2 |
Three-dimensional semiconductor memory devices
Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength. |
| US09136393B2 |
HK embodied flash memory and methods of forming the same
A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. |
| US09136392B2 |
Semiconductor memory device and method for manufacturing the same
According to one embodiment, the underlying film includes a memory region including a first trench and a peripheral region including a second trench. The stacked body includes conductive layers and insulating layers alternately stacked on the underlying film. The channel body is provided in a pair of first holes and the first trench. The first holes pierce the stacked body to be connected to the first trench. The memory film includes a charge storage film provided between a side wall of the first hole and the channel body, and between an inner wall of the first trench and the channel body. The conductor is provided in a pair of second holes and the second trench. The second holes pierce the stacked body to be connected to the second trench. |
| US09136390B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit. |
| US09136387B2 |
Semiconductor device and electronic apparatus
A semiconductor device includes: a transistor including an oxide semiconductor film; a first insulating film covering the oxide semiconductor film and including a first resin material; and a second insulating film including a second resin material that has polarity different from polarity of the first resin material, the second insulating film being laminated on the first insulating film. |
| US09136383B2 |
Contact structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer. |
| US09136380B2 |
Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09136378B2 |
Semiconductor device and manufacturing method for same
A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion. |
| US09136377B2 |
High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method
A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations. |
| US09136372B2 |
Silicon carbide semiconductor device
In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls. |
| US09136367B2 |
Semiconductor device
A semiconductor device includes: a p-type semiconductor layer mainly made of GaN; an n-type semiconductor layer mainly made of GaN and joined with the p-type semiconductor layer; a protective film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; a gate insulating film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; and a gate electrode joined with the gate insulating film. The protective film includes: a first layer made of Al2O3 and arranged adjacent to the p-type semiconductor layer and the n-type semiconductor layer to coat an edge of a p-n junction surface; a second layer made of an electrical insulation material different from Al2O3 and formed on the first layer; and an opening structure formed to pass through the first layer and the second layer. The gate insulating film is placed inside of the opening structure. |
| US09136360B1 |
Methods and structures for charge storage isolation in split-gate memory arrays
Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes. |
| US09136358B2 |
Nonvolatile semiconductor memory device and method for manufacturing same
According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second channel body layer penetrating the selection gate electrode and the interlayer insulating film and connected to the first channel body; a gate insulating film provided between the selection gate electrode and the second channel body layer; a second insulating layer provided on the gate insulating film and on the selection gate electrode; a contact layer provided on the second insulating layer; and a diffusion layer provided between the contact layer and the second insulating layer and connected to the second channel body layer and the contact layer. |
| US09136356B2 |
Non-planar field effect transistor having a semiconductor fin and method for manufacturing
A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity. |
| US09136347B2 |
Nitride semiconductor device
Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes. |
| US09136346B2 |
High electron mobility transistor (HEMT) capable of absorbing a stored hole more efficiently
A semiconductor device that can more efficiently absorb a stored hole includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, a second electrode, a control electrode, and a third electrode. The second semiconductor layer is provided on the first semiconductor layer and has a band gap narrower than that of the first semiconductor layer. The second semiconductor layer includes a first portion and a second portion which is provided together with the first portion and contains an activated acceptor. The third semiconductor layer is provided on the first portion and has a band gap wider than or equal to the band gap of the second semiconductor layer. The first and the second electrodes are provided on the third semiconductor layer. The control electrode is provided between the first electrode and the second electrode. The third electrode is provided on the second portion. |
| US09136345B1 |
Method to produce high electron mobility transistors with Boron implanted isolation
A method to produce high electron mobility transistors with Boron implanted isolation comprises the following steps: on a substrate forming in sequence a nucleation layer, a buffer layer, a barrier layer and a cap layer; coating a photoresist layer on the cap layer; photomasking and by exposure eliminating the photoresist layer of at least one isolation region; executing plural times an ion implantation process including: adjusting an incident angle of a Boron ion beam with respect to the substrate, and implanting the Boron ion beam into the cap layer, the barrier layer, the buffer layer, the nucleation layer and the substrate within the at least one isolation region so as to form an isolation structure while rotating the substrate by a rotation angle; eliminating the rest of the photoresist layer by exposure; and forming a source, a drain and a gate on the cap layer. |
| US09136340B2 |
Doped protection layer for contact formation
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion. |
| US09136337B2 |
Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, and group III nitride semiconductor device and method for manufacturing the same
A group III nitride composite substrate includes a support substrate and a group III nitride film. A ratio st/mt of a standard deviation st of the thickness of the group III nitride film, to a mean value mt of the thickness thereof is 0.001 or more and 0.2 or less, and a ratio so/mo of a standard deviation so of an absolute value of an off angle between a main surface of the group III nitride film and a plane of a predetermined plane orientation, to a mean value mo of the absolute value of the off angle thereof is 0.005 or more and 0.6 or less. Accordingly, there is provided a low-cost and large-diameter group III nitride composite substrate including a group III nitride film having a large thickness, a small thickness variation, and a high crystal quality. |
| US09136331B2 |
Semiconductor constructions
Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X. |
| US09136329B2 |
Semiconductor structure with dielectric-sealed doped region
Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. |
| US09136326B2 |
Semiconductor device with increased ESD resistance and manufacturing method thereof
A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes. |
| US09136321B1 |
Low energy ion implantation of a junction butting region
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer. |
| US09136316B2 |
Thin-film transistor array substrate with connection node and display device including the same
A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole. |
| US09136315B1 |
Organic light emitting display device and method of manufacturing the same
Provided are an organic light emitting display (OLED) device and a method of manufacturing the same. The OLED device includes: an array substrate, an intermediate layer over the array substrate, an insulating layer over the intermediate layer, and a plurality of driving signal lines over the insulating layer in a non-display area of the array substrate, the plurality of driving signal lines being completely separated from the intermediate layer by the insulating layer, each of the plurality of driving signal lines being configured to supply a driving signal from a driving circuit unit to a respective sub-pixel of a pixel among a plurality of pixels, wherein the intermediate layer under the plurality of driving signal lines is configured to reduce visibility of the driving signal lines such that incident light on the intermediate layer is uniformly reflected or absorbed with the plurality of driving signal lines. |
| US09136314B2 |
Method for manufacturing organic EL display and organic EL display
A method for manufacturing an organic electroluminescence display including multilayer structures that are each formed in a respective one of pixel areas in an effective area of a substrate and are each formed by a lower electrode, an organic layer, and an upper electrode, the organic electroluminescence display having a common electrode that electrically connects the pixel areas, the method including the steps of: forming a protective electrode and an outer-peripheral electrode that are electrically connected to the common electrode; forming the multilayer structures; and carrying out film deposition treatment involving electrification of the substrate. |
| US09136313B2 |
Organic light-emitting display apparatus and method for manufacturing the same
An organic light-emitting display apparatus and a method for forming the same, the apparatus including a transparent protection layer on a substrate; a via insulation layer on the transparent protection layer; a pixel electrode on the via insulation layer; an opposite electrode on the pixel electrode; and an intermediate layer between the pixel electrode and the opposite electrode, the intermediate layer including an organic emission layer. |
| US09136309B2 |
Organic electroluminescent display
An organic electroluminescent (EL) display includes a plurality of organic EL devices for red, green, and blue subpixels, each including a first electrode on a light output side, a second electrode opposite the first electrode, and an organic compound layer including a light-emitting layer therebetween. The organic EL devices have a resonator structure between a first reflective surface closer to the first electrode than the organic compound layer and a second reflective surface closer to the second electrode than the organic compound layer. A predetermined white color is displayed by mixing the three colors such that an optical distance of the organic EL devices of each color between an emission position in the light-emitting layer and the second reflective surface is set within ±10% from an optical distance corresponding to an nth-order minimum of a curve of required current density against at least the optical distance. |
| US09136302B2 |
Apparatus for vertically integrated backside illuminated image sensors
A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias. |
| US09136301B2 |
Multi-wave band light sensor combined with function of IR sensing and method of fabricating the same
Provided is a multi-wave band light sensor combined with a function of infrared ray (IR) sensing including a substrate, an IR sensing structure, a dielectric layer, and a multi-wave band light sensing structure. The substrate includes a first region and a second region. The IR sensing structure is in the substrate for sensing IR. The dielectric layer is on the IR sensing structure. The multi-wave band light sensing structure includes a first wave band light sensor, a second wave band light sensor, and a third wave band light sensor. The second wave band light sensor and the first wave band light sensor are overlapped and disposed on the IR sensing structure on the first region of the substrate from the bottom up. The third wave band light sensor is in the dielectric layer of the second region. |
| US09136300B2 |
Next generation imaging methods and systems
The advent of electronic-based imaging generally followed the four generalized ‘eras’ identified in FIG. 16 The trend is clearly toward higher and higher levels of integration for the act of “taking pictures.” FIG. 17 is a humble graphic attempt to summarize certain aspect of the present technology, and how a synthesis of these additional technical capabilities can represent a next era quite nicely. To the extent a great deal of past photography and filming has involved the mastery of technical limitations and turning limitations into art, a new challenge should develop where everyone has their own pocket Hasselblad/Steadicam, and exploration of new subject matter becomes the game. |
| US09136298B2 |
Mechanisms for forming image-sensor device with deep-trench isolation structure
Embodiments of mechanisms of for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region operable to detect incident radiation that enters the substrate through the back surface. The image-sensor device further includes a doped isolation region formed in the substrate and adjacent to the radiation-sensing region. In addition, the image-sensor device includes a deep-trench isolation structure formed in the doped isolation region. The deep-trench isolation structure includes a trench extending from the back surface and a negatively charged film covering the trench. |
| US09136297B2 |
Method for driving semiconductor device
A method for driving a semiconductor device which enables three-dimensional imaging is provided. The method for driving the semiconductor device also enables a reduction in the size of a pixel, two-dimensional imaging concurrently with the three-dimensional imaging, and/or accurate three-dimensional imaging of a fast-moving object. The distance from a light source to an object is measured by performing a first imaging and a second imaging with respect to the timings of the first irradiation and the second irradiation, respectively. A first photosensor absorbing visible light and a second photosensor absorbing infrared light are overlapped with each other and enable the two-dimensional imaging and the three-dimensional imaging, respectively, to be performed concurrently. Adjacent photosensors detect light reflected off substantially the same point of an object, preventing a reduction in the accuracy of the three-dimensional imaging of a fast-moving object. |
| US09136296B2 |
Photoelectric conversion apparatus and radiographic imaging apparatus
A photodiode includes a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type that is opposite to the first conductivity type of the first semiconductor layer, and a third semiconductor layer interposed between the first semiconductor layer and the second semiconductor layer. An edge of the first semiconductor layer is inset from an edge of the second semiconductor layer. |
| US09136290B2 |
Solid state imaging device, portable information terminal device and method for manufacturing solid state imaging device
According to one embodiment, a solid state imaging device includes a sensor substrate having a plurality of pixels formed on an upper face, a microlens array substrate having a plurality of microlenses formed and a connection post with one end bonded to a region between the microlenses on the microlens array substrate and with the other end bonded to the upper face. |
| US09136286B2 |
Display panel and electronic book
It is an object to provide a display panel and an electronic book which are manufactured with high yield and have high reliability. A display panel is provided which includes, a flexible display portion in which a scan line and a signal line intersect with each other over a substrate, a signal line driver circuit for outputting a first signal to the signal line adjacent to a first side of the flexible display portion over the substrate, and a scan line driver circuit for outputting a second signal to the scan line adjacent to a second side of the flexible display portion. In the display panel, the mechanical strength of a portion provided with the signal line driver circuit or the scan line driver circuit is improved as compared to the mechanical strength of other than the portion. |
| US09136282B2 |
Memories and methods of forming thin-film transistors using hydrogen plasma doping
Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled. |
| US09136281B2 |
Display device
According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size. |
| US09136280B2 |
Semiconductor device and driving method thereof
A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node. |
| US09136279B2 |
Display panel
A display panel includes a plurality of pads configured to provide a driver thereon, a plurality of first contacts respectively connected to the plurality of pads, a plurality of second contacts respectively provided so as to be opposed to the plurality of first contacts, a semiconductor layer configured to form a plurality of polysilicon films that are respectively extended to connect the plurality of first contacts and the plurality of second contacts to each other, and a gate metal layer different from the polysilicon layer. Each of a plurality of transistors is formed at a position where the gate metal layer traverses the polysilicon layer, and a plurality of transistor groups of the plurality of transistors are arranged in a zigzag pattern. Each of the plurality of transistor groups include three adjacent transistors of the plurality of transistors. |
| US09136277B2 |
Three dimensional stacked semiconductor structure and method for manufacturing the same
A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory. |
| US09136276B1 |
Memory cell structure and method for forming the same
A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other. |
| US09136275B2 |
Semiconductor device
A semiconductor device includes at least one channel layer, insulating layers stacked on top of one another while surrounding the at least one channel layer, first grooves and second grooves alternately interposed between the insulating layers, wherein the first groves have a greater width than the second grooves having a second width, and conductive layers formed in the first grooves. |
| US09136272B2 |
Semiconductor device
A semiconductor device may include a voltage supply unit suitable for supplying a voltage, a first conductive line coupled to the voltage supply unit, a second conductive line formed over the first conductive line, a voltage contact plug formed over the second conductive line, a voltage transmission line formed over the voltage contact plug, and a switching element suitable for switching the voltage transferred from the voltage transmission line. |
| US09136268B2 |
Semiconductor device and semiconductor memory device including capacitor
A semiconductor device includes: a second transistor having a second conductive type formed on a first well region having a first conductive type; a first transistor having a first conductive type formed on a second well region having a second conductive type; a first well guard ring having the first conductive type, the first well guard ring including at least a first portion formed between the first transistor and the second transistor; a second well guard ring having the first conductive type, the second well guard ring including at least a first portion formed between the first transistor and the second transistor; and a first capacitor formed on at least one of the first well region and the second well region, and located between the first portion of the first well guard ring and the first portion of the second well guard ring. |
| US09136261B2 |
Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection
An Electro-Static Discharge (ESD) protection using at least one I/O pad with at least one mesh structure of diodes provided on a semiconductor body is disclosed. The mesh structure has a plurality of cells. At least one cell can have a first type of implant surrounded by at least one cell with a second type of implant in at least one side of the cell, and at least cell can have a second type of implant surrounded by at least one cell with a first type of implant in at least one side of the cell. The two types of implant regions can be separated with a gap. A silicide block layer (SBL) can cover the gap and overlap into the both implant regions to construct P/N junctions on the polysilicon or active-region body on an insulated substrate. Alternatively, the two types of implant regions can be isolated by LOCOS, STI, dummy gate, or SBL on silicon substrate. The regions with the first and the second type of implants can be coupled to serve as the first and second terminal of a diode, respectively. The mesh structure can have a first terminal coupled to the I/O pad and a first terminal coupled to a first supply voltage. |
| US09136260B2 |
Method of manufacturing chip-stacked semiconductor package
A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other. |
| US09136259B2 |
Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking
A method is provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided. |
| US09136256B2 |
Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips
Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad (107) has a portion (107a) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip. |
| US09136255B2 |
Methods of fabricating package stack structure and method of mounting package stack structure on system board
A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate. |
| US09136253B2 |
Semiconductor light emitting device
According to one embodiment, a semiconductor light emitting device includes: a conductive layer; a first stacked body; a second stacked body; a first light-transmissive electrode; and a first interconnect electrode. The first stacked body includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is provided between the first semiconductor layer and the conductive layer. The first light emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The second stacked body includes a third semiconductor layer, a fourth semiconductor layer, and a second light emitting layer. The fourth semiconductor layer is provided between the third semiconductor layer and the conductive layer. The second light emitting layer is provided between the third semiconductor layer and the fourth semiconductor layer. The first interconnect electrode is provided between the second semiconductor layer and the third semiconductor layer. |
| US09136252B2 |
Semiconductor device
A semiconductor device includes a substrate having a first surface, a height adjuster mounted on the first surface of the substrate via a first adhesive layer, a semiconductor chip mounted on the height adjuster via a second adhesive layer, an electronic component mounted on the first surface of the substrate via a third adhesive layer, a bonding wire, and a sealing member. The length of the electronic component in a first direction corresponding to the thickness direction of the substrate is larger than the length of the semiconductor chip in the first direction, and the sum of the lengths of the height adjuster, the second adhesive layer, and the semiconductor chip in the first direction is larger than the length of the electronic component in the first direction. |
| US09136248B2 |
Multi-chip stacked package and method for forming the same
The present disclosure relates to a multi-chip stacked package and a method for forming the same. The package comprises a chip carrier and multiple levels of chips, with one or more chips being arranged in each level, wherein one or more levels of chips, except for the topmost chips, have conductive vias, a patterned conductor layer is arranged on a back surface of a lower one of two chips in two adjacent levels, conductive bumps are provided between two adjacent levels of chips, and the conductive vias of a lower chip are electrically coupled to an upper chip by means of the patterned conductor layer and the conductive bumps. In the present disclosure, electrical connections are redistributed by means of the patterned conductor layer, and are further used for coupling multiple levels of chips by means of the conductive bumps. The resultant chip has a reduced chip size and can be used for electrically coupling various levels of chips, which achieves flexible electrical connections. |
| US09136246B2 |
Integrated chip package structure using silicon substrate and method of manufacturing the same
An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry. |
| US09136236B2 |
Localized high density substrate routing
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough. |
| US09136232B2 |
Method for bonding wafers and structure of bonding part
A method for bonding wafers includes forming a first bonding part on a surface of a first wafer by stacking a diffusion preventing layer formed of a material having low wettability with AuSn above the first wafer and forming a bonding layer on a surface of the diffusion preventing layer such that the bonding layer stays back of an edge of the diffusion preventing layer, forming a second bonding part on a surface of a second wafer, and bonding the first bonding part and the second bonding part by eutectic bonding with an AuSn solder under a condition that the first wafer and the second wafer are opposed to each other. |
| US09136230B2 |
IC package with integrated waveguide launcher
Embodiments described herein include an integrated circuit (IC) device. For example, the IC device can include a substrate configured to be coupled to a printed circuit board (PCB), an IC die attached to the substrate, and a waveguide launcher formed on the substrate. The waveguide launcher is electrically coupled to the IC die through the substrate. |
| US09136228B2 |
ESD protection device
An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer provided on a surface of the semiconductor substrate. An ESD protection circuit is provided on or in an outer layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post electrodes. First ends of the interlayer wiring lines disposed in the thickness direction are connected to the input/output electrodes disposed on the surface of the semiconductor substrate, and second ends of the interlayer wiring lines are connected to first ends of the in-plane wiring lines routed in plan view. Prismatic post electrodes are provided between second ends of the in-plane wiring lines and terminal electrodes. |
| US09136227B2 |
Semiconductor device with buried bit line
A semiconductor device includes an isolation region, a semiconductor region, a groove, and an insulating film. The semiconductor region is defined by the isolation region. The groove is in the semiconductor region. The groove has first and second ends. At least one of the first and second ends reaches the isolation region. The insulating film is in the groove. |
| US09136226B2 |
Impurity doped UV protection layer
An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples. |
| US09136224B2 |
Alignment mark, photomask, and method for forming alignment mark
According to one embodiment, an alignment mark provided on an underlayer includes a plurality of first guide pattern features, and a first self-assembled film. The first guide pattern features extend in a first direction and are aligned in a second direction crossing the first direction. The first self-assembled film is provided between adjacent ones of the first guide pattern features and includes a plurality of first line pattern features and a second line pattern feature. The first line pattern features extends in the first direction, is aligned in the second direction, and has a pitch in the second direction narrower than a pitch in the second direction of the first guide pattern features. The second line pattern feature is provided between adjacent ones of the first line pattern features and extends in the first direction. |
| US09136223B2 |
Forming alignment mark and resulting mark
Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry. |
| US09136220B2 |
Semiconductor package and method for manufacturing the semiconductor package
A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed on the first surface of the first sealing insulating layer, at least one insulating layer formed on the at least one wiring layer, a second semiconductor chip mounted on the at least one insulating layer, and a second sealing insulating layer formed on the at least one insulating layer and configured to seal the second semiconductor chip. |
| US09136217B2 |
One-time programmable memory cell
A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics. |
| US09136215B2 |
Manufacturing method for semiconductor package
A manufacturing method includes the follow steps. Firstly, a carrier is provided. Then, a plurality of traces are formed on the carrier. Then, a trace molding compound layer is formed on the carrier by a first molding process. Then, the carrier is removed from the trace molding compound layer to expose an etched surface of the trace molding compound layer and trace upper surfaces of the traces. Then, at least a chip is disposed on the etched surface of the trace molding compound layer and the chip is connected to the trace upper surfaces. Then, a chip molding compound layer is formed on the etched surface by a second molding process substantially similar to the first molding process, wherein the chip molding compound layer and the trace molding compound layer are formed of substantially the same molding compound material. |
| US09136210B2 |
Interposer and semiconductor device
An interposer includes a substrate includes a plurality of penetrating electrodes, and a wiring portion formed on the substrate, in which the wiring portion includes a wiring layer electrically connected to the penetrating electrodes and an insulating layer covering the wiring layer. The interposer includes a plurality of first UBM structures provided at a side opposite the substrate of the wiring portion, in which the first UBM structures are electrically connected to the wiring layer. The interposer includes a plurality of bumps provided at the side opposite the wiring portion of the substrate, in which the plurality of bumps is electrically connected to each of the penetrating electrodes via a plurality of second UBM structures. |
| US09136206B2 |
Copper contact plugs with barrier layers
A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer. |
| US09136197B2 |
Impedence controlled packages with metal sheet or 2-layer RDL
A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces. |
| US09136194B2 |
Resin composition for encapsulation and electronic device using the same
The present invention provides a resin composition for encapsulating electronic components that contains a phenol resin curing agent and an epoxy resin, in which either the phenol resin curing agent or the epoxy resin has a biphenyl structure; a resin composition for encapsulating electronic components that contains a phenol resin curing agent and an epoxy resin, in which a glass transition temperature of a cured material is equal to or higher than 200° C., and a weight reduction rate of the cured material is equal to or lower than 0.3%; and an electronic device that includes an electronic component encapsulated with the resin composition. |
| US09136192B2 |
Warp correction device and warp correction method for semiconductor element substrate
A warp correction apparatus includes an injection mechanism including a nozzle that performs injection treatment, an adsorption table that holds the substrate by adsorption at a principal surface side or a film surface side, a moving mechanism that moves the adsorption table so that the substrate relatively moves with respect to an injection area of an injection particle by the nozzle, an injection treatment chamber that houses the substrate held on the adsorption table and in the interior of which injection treatment is performed, a measurement mechanism that measures a warp of the substrate, and a control device that, based on a difference between a target warp amount and a warp amount measured by the measurement mechanism, performs at least either one of a setting processing of an injection treatment condition of the injection mechanism and an accept/reject determination of the substrate for which injection treatment has been performed. |
| US09136190B2 |
Semiconductor manufacturing process system and method
According to one embodiment, a wafer processing device includes a processed number counting unit that counts a number of processed wafers, and a maintenance post-processing unit that executes a dummy lot process and a QC lot process after a maintenance process. A wafer preparation device prepares the dummy lot and the QC lot, when a first processed number is counted by the processed number counting unit. When a second processed number is counted by the processed number counting unit, a carrier device carries the dummy lot and the QC lot to the wafer processing device simultaneous with the maintenance process, before the maintenance process is completed. |
| US09136187B2 |
Method of adjusting a threshold voltage of a transistor in the forming of a semiconductor device including the transistor
A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error. |
| US09136184B2 |
In situ optical diagnostic for monitoring or control of sodium diffusion in photovoltaics manufacturing
A method of fabricating a photovoltaic device 100, includes the steps of providing a glass substrate 102, depositing a molybdenum layer 104 on a surface of the glass substrate, directing light through the glass substrate to the near-substrate region of the molybdenum layer 206, detecting an optical property of the near-substrate region of the molybdenum layer after interaction with the incident light 208 and determining a density of the near-substrate region of the molybdenum layer from the detected optical property 210. A molybdenum deposition parameter may be controlled based upon the determined density of the near-substrate region of the molybdenum layer 218. A non-contact method measures a density of the near-substrate region of a molybdenum layer and a deposition chamber 300. |
| US09136183B2 |
Transistor device and fabrication method
Fabrication methods for junctionless transistor and complementary junctionless transistor. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer. |
| US09136177B2 |
Methods of forming transistor devices with high-k insulation layers and the resulting devices
Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal). |
| US09136176B2 |
Semiconductor devices including an epitaxial layer with a slanted surface
A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. |
| US09136172B2 |
Method of manufacturing semiconductor device and method of manufacturing electronic assembly
A method of manufacturing a semiconductor device, includes: providing an adhesive layer on a support body; providing a semiconductor element on the adhesive layer; providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; and removing the substrate from the adhesive layer, wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed. |
| US09136171B2 |
Interconnect structure and fabrication method
An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed in the substrate. At least two porous films can be formed over the substrate and can include a first porous film having a first pore size, and a second porous film having a second pore size formed on the first porous film. The first porous size and the second porous size are different. The interconnect can be formed through the plurality of porous films to provide electrical connection to the semiconductor device in the substrate. |
| US09136165B2 |
Methods for stiction reduction in MEMS sensors
A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction. |
| US09136164B2 |
Semiconductor device and fabrication method
Semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region. An interlayer dielectric (ILD) layer formed over the substrate includes a top surface in the second region coplanar with a bottom of a trench in the ILD layer in the first region. Through-holes are formed in the ILD layer. A polymer layer fills the through-holes and the trench in ILD layer and covers top surface of ILD layer in both regions. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in ILD layer. A second metal layer is formed to fill each via on a corresponding first metal layer in both regions. The polymer layer between adjacent second metal layers is removed to form air gaps in the second region. |
| US09136161B2 |
Micro pick up array with compliant contact
Micro pick up arrays for transferring micro devices from a carrier substrate are disclosed. In an embodiment, a micro pick up array includes a compliant contact for delivering an operating voltage from a voltage source to an array of electrostatic transfer heads. In an embodiment, the compliant contact is moveable relative to a base substrate of the micro pick up array. |
| US09136160B2 |
Solid hole array and method for forming the same
A solid hole array and a method for forming the same are disclosed. The solid hold array may comprise: substrate with a via; a top hole array base formed on a top surface of the substrate and a bottom hole array base formed on a bottom surface of the substrate, wherein a front hole is located in the top hole array base at a place corresponding to the via; and top protection layer formed on a surface and sidewalls of the top hole array base and a bottom protection layer formed on a surface of the bottom hole array base, wherein a rear window is located in the bottom hole array base and the bottom protection layer at a place corresponding to the via. |
| US09136157B1 |
Deep N wells in triple well structures
A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate. |
| US09136154B2 |
Substrateless power device packages
A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer. |
| US09136153B2 |
3D semiconductor device and structure with back-bias
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors. |
| US09136149B2 |
Loading port, system for etching and cleaning wafers and method of use
A loading port includes a housing and a plurality of stations defined in the housing configured to receive a front opening universal pod (FOUP). The loading port further includes a connector configured to receive an inert gas. At least one of the plurality of stations is configured to deliver the inert gas to the FOUP to purge an interior of the FOUP of moisture. A system including the loading port and a method of using the system are also described. |
| US09136138B2 |
Equipment for manufacturing semiconductor device and seasoning process method of the same
Disclosed is an apparatus for processing a semiconductor and a method for generating a seasoning process of a reaction chamber. The method may include generating plasma in the reaction chamber using a production process recipe, obtaining at least one reference measurement value related to a byproduct of the generated plasma, performing a plurality of seasoning tests on the chamber to obtain a plurality of test results, generating an empirical model by forming at least one relational expression correlating variables manipulated during the performing of the plurality of seasoning tests to the plurality of test results, and estimating a seasoning process by using the at least one relational expression to estimate at least one estimated calculation value. |
| US09136137B2 |
Etchant composition and methods of fabricating metal wiring and thin film transistor substrate using the same
An etchant composition including 0.5 wt % to 20 wt % of a persulfate, 0.01 wt % to 1 wt % of a fluorine compound, 1 wt % to 10 wt % of an inorganic acid, 0.01 wt % to 2 wt % of an azole-based compound, 0.1 wt % to 5 wt % of a chlorine compound, 0.05 wt % to 3 wt % of a copper salt, 0.01 wt % to 5 wt % of an antioxidant or a salt thereof, based on a total weight of the etchant composition, and water in an amount sufficient for the total weight of the etchant composition to be equal to 100 wt % is disclosed. The etchant composition is suitable for use in forming a metal wiring by etching a metal layer including copper or in fabricating a thin film transistor substrate for a display apparatus. |
| US09136135B2 |
Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance. |
| US09136131B2 |
Common fill of gate and source and drain contacts
A semiconductor structure includes a source region, a drain region, a channel region and a gate region over a bulk silicon substrate. The gate region further includes a dielectric layer and one or more work function layers disposed over the dielectric layer. A first filler material, such as a flowable oxide is provided over the source region and the drain region. A second filler material, such as an organic material, is provided within the gate region. The first filler material and the second filler material are selectively removed to create, source, drain and gate openings. The gate, source and drain openings are filled simultaneously with a metal, such as tungsten, to create a metal gate structure, source contact and drain contact. |
| US09136129B2 |
Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology
A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure. |
| US09136127B2 |
Method of fabricating GOI silicon wafer, GOI silicon wafer and GOI detection method
The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer. With the technical solution here according to an embodiment of the invention, an error between the GOI silicon wafer and the VDMOS device can be lowered, good accuracy can be achieved, and a resource can be saved effectively, and furthermore the accuracy in a result of GOI detection can be well improved. |
| US09136117B2 |
Method for making semiconducting single wall carbon nanotubes
A method for making semiconducting single walled carbon nanotubes (SWCNTs) includes providing a substrate. A single walled carbon nanotube film including metallic SWCNTs and semiconducting SWCNTs is located on the substrate. At least one electrode is located on the single walled carbon nanotube film and electrically connected with the single walled carbon nanotube film. A macromolecule material layer is located on the single walled carbon nanotube film to cover the single walled carbon nanotube film. The macromolecule material layer covering the metallic SWCNTs is removed by an electron beam bombardment method, to expose the metallic SWCNTs. The metallic SWCNTs and the macromolecule material layer covering the semiconducting SWCNTs are removed. |
| US09136115B2 |
Method for manufacturing semiconductor device
An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith. |
| US09136114B2 |
Method of manufacturing semiconductor device, substrate processing method, computer-readable medium with program for executing a substrate processing method, and substrate processing apparatus
A method of manufacturing a semiconductor device is provided, including: forming an oxynitride film having a specific film thickness on a substrate by performing multiple numbers of times a cycle of: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element into a processing vessel in which the substrate is housed; changing the specific element-containing layer to a nitride layer by supplying a nitrogen-containing gas into the processing vessel; and changing the nitride layer to an oxynitride layer by supplying an oxygen-containing gas and an inert gas into the processing vessel, with this sequence as one cycle, wherein a composition ratio of the oxynitride film having the specific film thickness is controlled by controlling a partial pressure of the oxygen-containing gas in the processing vessel, in changing the nitride layer to the oxynitride layer. |
| US09136108B2 |
Method for restoring porous surface of dielectric layer by UV light-assisted ALD
A method for restoring a porous surface of a dielectric layer formed on a substrate, includes: (i) providing in a reaction space a substrate on which a dielectric layer having a porous surface with terminal hydroxyl groups is formed as an outer layer; (ii) supplying gas of a Si—N compound containing a Si—N bond to the reaction space to chemisorb the Si—N compound onto the surface with the terminal hydroxyl groups; (iii) irradiating the Si—N compound-chemisorbed surface with a pulse of UV light in an oxidizing atmosphere to oxidize the surface and provide terminal hydroxyl groups to the surface; and (iv) repeating steps (ii) through (iii) to form a film on the porous surface of the dielectric layer for restoration. |
| US09136107B2 |
Semiconductor device and method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening part, through which a part of the cap layer is exposed, and forming an oxidation film on an exposed surface of the cap layer by a wet process. |
| US09136106B2 |
Method for integrated circuit patterning
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. |
| US09136105B2 |
Bevel etcher
The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region. |
| US09136098B2 |
Ion guide coupled to MALDI ion source
A pulsed ion source is disclosed wherein the ion source is energized one or more times to generate a first group of ions and a second group of ions. The first and second groups of ions are simultaneously transmitted through an ion guide whilst keeping the first and second groups of ions isolated from each other. |
| US09136091B2 |
Electron beam apparatus for inspecting a pattern on a sample using multiple electron beams
An electron beam apparatus for inspecting a pattern on a sample using multiple electron beams includes a plurality of primary electro-optical systems and a plurality of secondary electro-optical systems associated with the respective primary electro-optical systems. The primary electro-optical systems are for irradiating multiple primary electron beams on a surface of the sample, and each includes an electron gun having an anode and an objective lens. The secondary electro-optical systems are for inducing secondary electrons emitted from a surface of the sample by irradiation of the primary electron beams. Detectors are each for detecting the secondary electrons and generating electric signals corresponding to the detected electrons. The anodes of the electron guns of the primary electro-optical systems comprise an anode substrate in common having multiple holes corresponding to the axes of the respective primary electro-optical systems. The anode substrate has metal coatings around the respective holes. |
| US09136088B2 |
Detection apparatus and operating method
The disclosed technology provides a detection apparatus and its operating method. The disclosed technology provides a detection apparatus, comprising: a test chamber, an exchange chamber, and a communicating mechanism, which is provided between the test chamber and the exchange chamber and capable of rendering the test chamber and the exchange chamber separated from or communicated with each other; wherein transmission devices are positioned within the test chamber and the exchange chamber, respectively, and the transmission devices are adapted to convey a probe frame from the test chamber to the exchange chamber or from the exchange chamber to the test chamber. |
| US09136085B2 |
Shock-resistant image intensifier
In one exemplary embodiment, a shock-resistant night vision assembly is configured to detect a high-acceleration event, for example, resulting from a round or burst of high-caliber rifle fire. Upon detecting the event, a voltage such as a photocathode voltage is forced to an inactive or protective level and held there for approximately 50 ms, giving time for mechanical excursions of the microchannel plate to settle out. Damage from physical impact and electrostatic discharge may thus be mitigated. |
| US09136084B2 |
Micro discharge devices, methods, and systems
Micro discharge devices, methods, and systems are described herein. One device includes a non-conductive material, a channel through at least a portion of the non-conductive material having a first open end and a second open end, a first electrode proximate to a first circumferential position of the channel between the first open end and the second open end, a second electrode proximate to a second circumferential position of the channel between the first open end and the second open end, a discharge region defined by a portion of the channel between the first electrode and the second electrode, an optical emission collector positioned to receive an optical emission from the discharge region, and a discharge shielding component between the discharge region and the optical emission collector. |
| US09136082B2 |
Ground-fault circuit interrupter
A ground-fault circuit interrupter (GFCI) device, including a relay for control a switch to be in an open position or a closed position, the relay including a first coil and a second coil, wherein when both the first coil and the second coil are non-conductive, the switch is caused to be in the open position. The GFCI also includes a relay start circuit connected to the first coil for causing the first coil to be conductive or non-conductive, wherein when the first coil is conductive, the first coil causes the switch to be in the closed position, but after the first coil is conductive, the coil start circuit becomes non-conductive. The GFCI further includes a relay sustain circuit connected to the second coil for causing the second coil to be conductive or non-conductive. In addition, the GFCI includes a ground fault detect circuit for causing both the relay start circuit and the relay sustain circuit to become non-conductive when a fault signal is detected, causing both the first coil and the second coil to be non-conductive, thereby causing the switch to be in the open position. |
| US09136081B2 |
D/C trip assembly
A D/C trip assembly for a circuit breaker is provided. The D/C trip assembly includes a magnet, a mounting assembly and an armature assembly. The mounting assembly includes a body, the mounting assembly body including a pivotal coupling. The armature assembly includes a magnetic body and a trip bar linkage, the trip bar linkage extending from the armature assembly body. The armature assembly body is structured to move between a first position, wherein the armature assembly body is close to the magnet, and a second position, wherein the armature assembly body is spaced from the magnet. The trip bar linkage is structured to move between a first position and a second position, the trip bar linkage positions corresponding to the armature assembly body positions. The trip bar linkage is structured to be coupled to a trip bar. |
| US09136080B2 |
Electromagnet device and electromagnetic relay using the same
The present invention provides an electromagnet device including: an electromagnet block having a spool around which a coil is wound and an iron core inserted in a central hole of the spool; a yoke connected to an end portion of the iron core via a permanent magnet; a movable iron piece pivotably supported on a pivoting shaft center located at an end face edge portion of the yoke, the movable iron piece is adapted to pivot on a basis of magnetization and demagnetization of the electromagnet block, and a protrusion having a linear edge portion which extends in parallel to the pivoting shaft center and the protrusion protrudes from at least either the movable iron piece or the iron core, the protrusion protrudes in a facing direction in which the movable iron piece and the iron core face each other. |
| US09136076B2 |
Mechanically operated cell switch of vacuum circuit breaker
There is provided a mechanically operated cell (MOC) switch of a vacuum circuit breaker, which is uniformly operated regardless of an insertion stroke of a push rod that operates a MOC switch of a vacuum circuit breaker. The MOC switch outputting an ON/OFF state of a vacuum circuit breaker when the vacuum circuit breaker operates includes: a main bracket; a rotational shaft installed in the main bracket; a connection lever rotatably coupled to the rotational shaft and having one end connected to an auxiliary switch; a roller coupled to the other end of the connection lever; and a horizontal moving unit installed in a portion of the to main bracket and making a horizontal movement to rotate the roller and allowing the other end of the connection lever to make an ascending and descending movement. |
| US09136075B2 |
Switch module built in steering wheel
Disclosed is a switch module located within a steering wheel of a vehicle that includes an input switch module, a feedback module, and a controller. The input switch module allows a driver to conduct a variety of switching operations by, for example, pressing the left, right, front, or back of the steering wheel, or by making a leftward or rightward torsional motion or a leftward or rightward diagonal motion with respect to the steering wheel. The switch module controller receives inputs from the input switch module that correlate to these switching operations, and outputs a signal to a vehicle device such as, for example, a head up display, and also to a feedback module, which provides a feedback response to the driver confirming the switching operation. The present invention allows the driver to control vehicle devices and systems while maintaining contact with the steering wheel, thereby improving vehicle safety. |
| US09136072B2 |
Indicator apparatus
In an indicator apparatus, a prism member includes: a prism member side surface; and a transmitting and reflecting surface that is inclined relative to the prism member side surface, and into which light from a light source is admitted. An adjacent member has an adjacent surface that is adjacent to the prism member side surface. The light from the light source is admitted into the transmitting and reflecting surface when the light source is lit, and passes through the prism member. If the prism member is viewed frontally when the light source is not lit, the adjacent surface is visible by optical reflection at the transmitting and reflecting surface. |
| US09136060B2 |
Precision high-frequency capacitor formed on semiconductor substrate
A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique. |
| US09136057B2 |
Ceramic electronic component, method of manufacturing the same, and collective component
A collective component has a first region that intersects with a conductive film for external terminal electrodes in a break line in which break leading holes are arranged and a second region that does not intersect with the conductive film for external terminal electrodes in the break line. The plurality of break leading holes includes at least one extending break leading hole located so as to extend over the first region and the second region. |
| US09136050B2 |
Magnetic device and method of manufacturing the same
A magnetic device comprises a lead frame, a first core body and a coil. The lead frame has a first portion and a second portion spaced apart from the first portion. A first core body is disposed on the lead frame, wherein the first core body comprises a first through opening and a second through opening. A coil is disposed on the first core body, wherein the coil has a first terminal and a second terminal, wherein the first portion is electrically connected with the first terminal via the first through opening, and the second portion is electrically connected with the second terminal via the second through opening, respectively. |
| US09136047B2 |
Method of forming low-resistance metal pattern, patterned metal structure, and display devices using the same
Disclosed herein is a method of forming low-resistance metal pattern, which can be used to obtain a metal pattern having stable and excellent characteristics by performing sensitization treatment using a copper compound before an activation treatment for forming uniform and dense metal cores, a patterned metal structure, and display devices using the same. |
| US09136046B2 |
Superconducting wire rod and method for manufacturing superconducting wire rod
Impurities are reduced in an oxide superconducting layer and in an interface between the oxide superconducting layer and an intermediate layer. A superconducting wire rod 1 has a structure including a substrate (10), an intermediate layer (20) formed on the substrate (10), a reaction suppressing layer (28) formed on the intermediate layer (20) and mainly containing polycrystalline SrLaFeO4+δ1 or CaLaFeO4+δ2, in which the δ1 and the δ2 each represent an amount of non-stoichiometric oxygen, and an oxide superconducting layer (30) formed on the reaction suppressing layer (28) and mainly containing an oxide superconductor. |
| US09136042B2 |
Differential signal transmission cable, multiwire differential signal transmission cable, and differential signal transmission cable producing method and apparatus
A differential signal transmission cable includes an insulated wire including a pair of differential signal transmission conductors coated with an insulation, a shield tape conductor made of a band-like member including an electrically conductive metal layer, and wrapped along an outer surface of the insulated wire so that its ends in a width direction are overlapped together, a first resin tape spirally wound along an outer surface of the shield tape conductor and around an outer side of the shield tape conductor, and a second resin tape spirally wound along an outer surface of the first resin tape and around an outer side of the first resin tape. The shield tape conductor, the first resin tape and the second resin tape are wound in a same circumferential direction around a center axis of the insulated wire. |
| US09136037B1 |
Adhesion promoter
Compositions useful for improving the adhesion of coating compositions, such as dielectric film-forming compositions, include a hydrolyzed amino-alkoxysilane having a protected amino moiety. These compositions are useful in methods of improving the adhesion of coating compositions to a substrate, such as an electronic device substrate. |
| US09136036B2 |
Injection moldable, thermoplastic composite materials
A thermoplastic composite material, which includes a thermoplastic, organic polymer; and a plurality of carbon nanotubes, is provided. The thermoplastic composite material exhibits a bulk volume resistivity of about 103 Ω-cm (ohm cm) to 1010 Ω-cm at 5,000 volts. Such thermoplastic composite materials may find utility in applications that require the thermoplastic to be capable of withstanding high voltage spikes, as would be encountered during a lightning strike. |
| US09136034B2 |
Polymer electrolyte membrane for a fuel cell, and method for preparing same
The present disclosure relates to a polymer electrolyte membrane having a construction wherein an ionomer is charged in pores of a nanoweb having a high melting point, being insoluble in an organic solvent and having excellent pore characteristics, under optimum conditions. Therefore, an overall thickness of the electrolyte membrane may be reduced, thereby attaining advantages such as decrease in ohmic loss, reduction of material costs, excellent heat resistance, low thickness expansion rate which in turn prevents proton conductivity from being deteriorated over a long term. The polymer electrolyte membrane of the present invention comprises a porous nanoweb having a melting point of 300□ or more and being insoluble in an organic solvent of NMP, DMF, DMA, or DMSO at room temperature; and an ionomer which is charged in pores of the porous nanoweb and contains a hydrocarbon material soluble in the organic solvent at room temperature. |
| US09136032B2 |
Cathode material
Provided is a cathode material capable of obtaining high energy density and superior instantaneous output characteristics in a lithium ion secondary battery. The cathode material is used in a lithium ion secondary battery (1), and includes FeF3 and LiV3O8 as a cathode active material. A mass ratio of FeF3 to LiV3O8 of the cathode material is in a range of 86:14 to 43:57. The cathode material further comprises a conductive auxiliary. |
| US09136031B2 |
Alumina sintered body, member including the same, and semiconductor manufacturing apparatus
An alumina sintered body contains alumina as a main component and titanium. The alumina sintered body further contains at least one element selected from the group consisting of lanthanum, neodymium, and cerium. Aluminum is contained in the alumina sintered body in an amount such that a ratio of aluminum oxide to total oxides in the alumina sintered body becomes 93.00 to 99.85% by weight where the total oxides are defined as a total amount of all oxides contained in the alumina sintered body. Titanium is contained in an amount such that a ratio of titanium oxide to the total oxides becomes 0.10 to 2.00% by weight. Lanthanum, neodymium, and cerium are contained in a combined amount such that a ratio of the combined amount to the total oxides becomes 0.05 to 5.00% by weight. Volume resistivity is 1×105 to 1×1012 Ω·cm at room temperature. |
| US09136029B2 |
Scintillator panel, and radiographic image sensor
A scintillator panel 1 and a radiation image sensor 10 in which characteristics can be changed easily at the time of manufacture are provided. The scintillator panel 1 comprises a scintillator 3 having an entrance surface 3a for a radiation; a FOP 2, arranged on an opposite side of the scintillator 3 from the entrance surface 3a, for transmitting the light generated by the scintillator 3; and a resin layer 5, formed from a resin containing a color material on the entrance surface 3a side of the scintillator 3, for performing at least one of absorption and reflection of the light generated by the scintillator 3. |
| US09136027B2 |
Method of drying high-level radioactive wastes and device thereof
A method of drying high-level radioactive wastes and device thereof contains a suspension mechanism for hanging a manual elevating mechanism, and a shielding cover. The manual elevating mechanism couples with a basket for accommodating wastes by using a hanging rope, and the shielding cover is fixed below the suspension mechanism and in a moving path of the basket. The basket is moved to a storage tank containing water in which radioactive wastes are stored, and the radioactive wastes are pumped into the basket by means of a pump. The basket is then lifted above a water surface of the storage tank and received in the shielding cover, and then the shielding cover is moved into a water holder so as to drain waters in the basket. The basket is further moved onto a heating seat to be heated and a vacuum equipment is started to dry the radioactive wastes. |
| US09136026B2 |
Reactor bottom repairing method
A heating laser beam is emitted to a cracked portion to remove moisture from the cracked portion, and subsequently, a welding laser beam is emitted to the cracked portion to heat and melt the cracked portion. The heating laser beam and the welding laser beam are emitted to an entire surface of the cylindrical body inside the reactor such as a stub tube penetrating through and fixed to a reactor bottom portion and a crack of the welded portion between the cylindrical body and the reactor bottom portion to thereby prevent a new crack from occurring and reactor water from leaking. |
| US09136025B2 |
Dual-cooled fuel rod's spacer grids with upper and lower cross-wavy-shape dimple
A dual-cooled fuel rod's spacer grid with upper and lower dimples, including a blocking area of a flow passage that coolant flows through is reduced and dual-cooled fuel rods are supported, and reduces a turbulent flow of the coolant as well as vibrations of the dual-cooled fuel rods, thereby lessening fretting damage done to the rods. The spacer grid includes a plurality of unit grid straps, each of which includes a body disposed in a vertical direction, an upper dimple protruding from an upper portion of the body, and a lower dimple spaced apart from the upper dimple in a downward direction and protruding from a lower portion of the body. The unit grid straps form a grid structure that have inner grid holes into which the dual-cooled fuel rods are held, and the held dual-cooled fuel rods are each supported in four directions by the upper and lower dimples. |
| US09136021B2 |
Self-repair logic for stacked memory architecture
Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs. |
| US09136020B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written. |
| US09136018B2 |
Internal voltage generation circuits
An internal voltage generation circuit includes a reference voltage generator and an internal voltage generator. The reference voltage generator is configured to adjust resistance values according to test signals and to generate an upper limit reference voltage and a lower limit reference voltage whose levels are determined according to the resistance values. The internal voltage generator is configured to generate an internal voltage which is driven according to the levels of the upper and lower limit reference voltages. |
| US09136014B2 |
Method for replacing the address of some bad bytes of the data area and the spare area to good address of bytes in non-volatile storage system
A method for replacing the address of some bad bytes (bad columns) of the data area and the spare area to the good address of bytes (good columns) in non-volatile storage system is disclosed. The steps of the method are: waiting for a command from a host; judging if there is still some data to be processed; if no, go back to the previous step; if yes, go to next step; judging if a bad column is used; if no, process data access and go back to the step of judging if there is still some data to be processed; and if yes, process data accessing as original operation and increase the address by one. |
| US09136012B1 |
Reliable readout of fuse data in an integrated circuit
An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses. |
| US09136011B2 |
Soft information module
A system and method for generating reliability information, such as “soft information,” from a flash memory device is disclosed. A plurality of memory cells are read by a data storage controller at a first read level to obtain a plurality of program values. On an error indicator being received in connection with reading the plurality of memory cells, the plurality of memory cells are read one or more times at one or more different read levels to categorize the plurality of memory cells into two or more cell program regions. A confidence value is then assigned to each memory cell based on a corresponding cell program region for the memory cell, the confidence value being representative of a likelihood that the memory cell is programmed to a corresponding program value read at the first read level. |
| US09136004B2 |
Semiconductor memory device and programming method for flash memory for improving reliabilty of insulating layer of memory cell
A programming method for suppressing deterioration of an insulating layer in a memory cell is provided. In the programming method for a flash memory of the invention, a cell unit including programming units that have been programmed is electrically isolated from a bit line; a cell unit not including programming units is electrically coupled with the bit line; a programming voltage is applied to selected word lines; and a pass voltage is applied to non-selected word lines. Moreover, during a period of applying the programming voltage, carriers are generated in a P-well, and hot carriers passing through a depletion region and accelerated by an electric field are injected into the memory cell. |
| US09136002B2 |
Semiconductor memory devices utilizing randomization and data programming methods thereof
A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data in at least one of the plurality of nonvolatile memories, wherein the plurality of nonvolatile memories has different types from one another. |
| US09135999B2 |
Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding
Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. |
| US09135993B2 |
Temperature based logic profile for variable resistance memory cells
A data storage device may generally be constructed and operated with at least one variable resistance memory cell having a first logic state threshold that is replaced with a second logic state threshold by a controller. The first and second logic states respectively corresponding to a predicted resistance shift that is based upon an operating temperature profile. |
| US09135992B2 |
Methods for forming memory devices with reduced operational energy in phase change material
Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material. |
| US09135987B2 |
FinFET-based boosting supply voltage circuit and method
A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first transistor is a planar transistor, a source of the first transistor being connected with the voltage supply, and a gate of the first transistor receiving a control signal. The second transistor includes a gate formed in at least two planes. A source of the second transistor is connected with the voltage supply, a gate of the second transistor receives the control signal, and a drain of the second transistor is connected with a drain of the first transistor and forms an output of the voltage boosting circuit for generating a boosted supply voltage as a function of the control signal. |
| US09135986B2 |
Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. |
| US09135985B2 |
Memory cell
This invention relates generally to a memory cell. The embodiments of the present invention provide a SRAM cell and a SRAM cell array comprising such SRAM cell. The SRAM cell according to the embodiments of the present invention includes a pull-up transistor and a pull-down transistor, such that it is unnecessary to pre-charge a pre-read bit line at the time of performing read operation. By adopting the method of the present invention, generation of leakage current can be suppressed and hence power consumption of SRAM chip can be reduced. |
| US09135982B2 |
Techniques for accessing a dynamic random access memory array
Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed. |
| US09135981B2 |
Memory system having memory ranks and related tuning method
A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters. |
| US09135980B2 |
Memory control circuit and method of controlling data reading process of memory module
This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal. |
| US09135975B2 |
Write pulse width scheme in a resistive memory
A resistive memory array includes a controller, a test reset driver coupled to the controller, a test write driver also coupled to the controller, and a test read sense amplifier also coupled to the controller. The resistive memory array also includes a set of test resistive memory elements representing a resistive memory macro. The test resistive memory elements are coupled to the test reset driver, the test write driver and the test read sense amplifier. A change in the state of one of the test resistive memory elements represents a change in the state of a set of corresponding elements in the resistive memory macro. |
| US09135971B2 |
Boosted read write word line
One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example. |
| US09135970B2 |
Tamper detection and response in a memory device
A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation. |
| US09135950B1 |
Optical disc drive high frequency modulation signal detection
A plurality of time periods corresponding to times at which a predicted transition in a signal is expected to occur are determined. The signal has bi-phase modulation, and the predicted transition corresponds to a transition in the signal from a first state to a second state as part of the bi-phase modulation. A next transition in the signal from the first state to the second state is detected, and it is determined whether the detected next transition occurred during one of the plurality of time periods. In response to determining that the detected next transition occurred during one of the plurality of time periods, a timing of the detected next transition is used to adjust a clock used for recovering channel bits in the signal. |
| US09135945B2 |
Disk rotating motor comprising bracket including cylindrical portion and folded portion
A disk rotating motor is provided with: a stator including a stator core and a bracket for fixing the stator core; a rotor that can be rotated with respect to the stator and includes a rotary shaft; and a bearing that rotatably supports the rotary shaft on the outer diameter side of the rotary shaft, the bearing being supported by the bracket. The bracket includes a cylindrical portion extending along the rotary shaft, and a folded portion formed by folding the upper end of the cylindrical portion onto the outer diameter side such that at least a coaxial part of the folded portion extends coaxially along an outer surface of the cylindrical portion. The cylindrical portion and the folded portion are sandwiched by the stator core and the bearing in a radial direction. |
| US09135943B2 |
Tape guide with flanges
A tape guide is provided for use with a tape drive that is configured to receive a length of tape having a tape width. The tape guide includes a body having an outer surface for receiving the tape thereon, and flanges on opposite ends of the body. The flanges may be spaced apart by a distance that is 125 to 500 microns greater than the tape width. |
| US09135942B2 |
Heat assisted magnetic recording head having wider heat sink and pole
In one embodiment, a system includes a magnetic head having a write portion having a main pole, a near field transducer comprising a conductive metal film having outer regions extending from an active region, and an optical waveguide for illumination of the near field transducer, wherein the conductive metal film extends in a cross track direction for a width at least 200% greater than a width of the active region of the conductive metal film, wherein a portion of the main pole extends along the conductive metal film in a cross track direction for a width at least 200% greater than the width of the active region of the conductive metal film. |
| US09135941B2 |
Dye for optical information recording medium and optical information recording medium
Provided is an optical information recording medium employing an In-Groove recording system, and having a preferable recording characteristic with a high modulation degree and low jitter characteristics. The medium is comprised of a circular-disk shaped substrate 2 having a through hole at a center portion thereof and a helical guide groove 3 on one surface thereof; a reflective layer 4 formed on the guide groove 3 of the substrate 2; a recording layer 5 formed on the reflective layer 4 and composed of an organic material including a dye; a protection layer 6 provided on the recording layer 5; and a light-transmissive layer 7 formed on the protection layer 6. The recording layer 5 includes an organic dye which is an azo metal complex compound having a structure represented by (Chemical formula 1) and a functional group represented by (Chemical formula 2). |
| US09135940B2 |
Radio frequency circuit
A radio frequency (RF) circuit includes a first microchip for transmitting RF signal, a second microchip, two resistors and at least two signal lines. Each signal line has opposite first and second ends, and each first end of each signal line is connected to the first microchip and each second end of each signal line is connected to the second microchip. Each signal line defines first and second gaps, the first gaps are adjacent to the first microchip and the second gaps are adjacent to the second microchip. The two resistors are selectively located at the gaps of any one signal line, whereby the first microchip and the second microchip are connected to each other through the signal line and the resistors to form a connection path. |
| US09135935B1 |
Customized head gimbal assembly bonding skew angle for adjusting two-dimensional magnetic recording reader alignment
System and methods are illustrated for customizing the HGA bonding skew angle of a TDMR slider including a plurality of readers to adjust reader alignment relative to a track location on disk media. Overlay error caused by manufacturing variations is compensated for by adjusting the skew angle of the slider when it is bonded to the suspension to form the HGA. Process operations for manufacturing a TMDR HDD include manufacturing a multiple reader, multiple layer TDMR slider, determining an overlay error in the slider, determining a slider bonding skew angle based on the determined overlay error and other parameters, and bonding the slider to a HDD suspension at the determined bonding skew angle. |
| US09135926B2 |
Apparatus and method of enhancing quality of speech codec
An apparatus and method of improving the quality of a speech codec are provided. In the method, a first energy of a signal decoded by a low-band codec is calculated, and a second energy of a signal decoded by a low-band enhancement mode is calculated. Then, when the first energy is less than a first threshold value or less than a product of the second energy and a second threshold value, a size of the decoded signal is scaled. Accordingly, generation of a quantization error with respect to a silence segment is reduced. |
| US09135925B2 |
Apparatus and method of enhancing quality of speech codec
An apparatus and method of improving the quality of a speech codec are provided. In the method, a first energy of a signal decoded by a core codec is calculated, and a second energy of a signal decoded by a low-band enhancement mode is calculated. Then, when the first energy is less than a first threshold value or less than a product of the second energy and a second threshold value, a size of the decoded signal is scaled. Accordingly, generation of a quantization error with respect to a silence segment is reduced. |
| US09135919B2 |
Quantization device and quantization method
A quantization device and quantization method are provided that reduce coding distortion with a small degree of calculation and achieve adequate coding performance thereby. A multistage vector quantization unit treats a number of candidates N that are designated prior to operation in the first-stage vector quantization unit, decrements the number of candidates by one beginning with the second-stage vector quantization unit and continuing with each stage thereafter. If the number of candidates is three or less, the multistage vector quantization unit assesses the quantization distortion at each stage, treating the number of candidates at the following stage as a predetermined value P if the quantization distortion is greater than a prescribed threshold, and treating the number of candidates at the following stage as a value Q that is less than the predetermined value P if the quantization distortion is less than or equal to the predetermined threshold. |
| US09135913B2 |
Voice input system, interactive-type robot, voice input method, and voice input program
A first voice input system according to the present invention includes: a voice input unit 21, which inputs a voice, and outputs a voice signal; a condition storing unit 22, which stores a malfunction condition set including a malfunction condition element to detect a voice input state; a condition selection unit 23 by which a selection signal for selecting a malfunction condition set from a condition storing unit 22 is input from an external application 30, and a malfunction condition set corresponding to the selection signal is stored; a voice input state detection unit 24 which analyzes the voice signal, collates the analysis result and a malfunction condition element included in the malfunction condition set held by the condition selection unit 23, and output the detection result; and a response unit 25 for operation processing according to the detection result. |
| US09135909B2 |
Speech synthesis information editing apparatus
A speech synthesis information editing apparatus is provided. The speech synthesis information editing apparatus includes a phoneme storage unit that stores phoneme information, which designates a duration of each phoneme of speech to be synthesized. The speech synthesis information editing apparatus also includes a feature storage unit that stores feature information, which designates a time variation in a feature of the speech. In addition, the speech synthesis information editing apparatus includes an edition processing unit that changes a duration of each phoneme designated by the phoneme information with an expansion/compression degree, based on a feature designated by the feature information in correspondence to the phoneme. |
| US09135907B2 |
Method and apparatus for reducing the effect of environmental noise on listeners
A method and apparatus for enhancing a desired audio signal for delivery through an electroacoustic channel include obtaining a noise estimate attributable to an external disturbance, applying the noise estimate to a dynamic noise compensation (DNC) process to thereby condition the desired audio signal as a function of the spectral characteristics of the noise estimate, applying the noise estimate to an adaptive equalization (AEQ) process to thereby condition the desired audio signal as a function of the electroacoustic response of the electroacoustic channel, and applying the noise estimate to an active noise cancellation (ANC) process configured to generate anti-noise for delivery into the electroacoustic channel. |
| US09135903B2 |
Electronic keyboard instrument
When a key depression speed and a key release speed of a key is to be detected based on a value of a counter (44) which accumulates a value every time the key passes through key switches (SW1, SW2), a number of digits of data indicating the key depression speed, a unit of the data being a bit and a number of digits of data indicating the key release speed, a unit of the data being a bit, are made the same. |
| US09135898B1 |
Finger pick for stringed instrument
A finger pick for being retained on a user's finger and for aiding in the playing of a stringed musical instrument includes a base portion, sizing wings, a spoon portion, and an opening defined by the base portion and the sizing wings. The sizing wings are bent upward from the base portion to define an interior space into which a user's finger is received to attach the finger pick to the finger. The opening extends transversely across the base portion and upward into the sizing wings when the sizing wings are bent upward. When the finger pick is inserted on the finger of a user, the soft tissue of the finger will protrude outwardly from the sizing wings and also through the opening, providing for three points of contact to the retain the finger pick on the finger. |
| US09135896B2 |
Pedal-operated stringed musical instrument actuator apparatus
A device for depressing the strings of a musical instrument, including a foot-operated pedal portion having a plurality of pedals operatively coupled to a control device, the pedals arranged chromatically and corresponding to major chords; a second foot-operated portion including toggles for modifying the major chords; and a hands-free string-engaging portion operatively coupled to the pedal portion. The string-engaging portion includes a plurality of actuators configured to overlie and depress the strings of the stringed musical instrument. The pedal portion also may include a control device operably coupled to and configured to receive input signals from the pedals and toggles, and the control device may be operably coupled to and configured to send output signals to the actuators, such that depressing one of the pedals causes the actuators corresponding to a predetermined chord to be depressed. |
| US09135894B2 |
Data access method and electronic apparatus for accessing data
A data access method applicable to a storage apparatus for reducing or eliminating an image tearing effect includes defining at least one write check point; comparing an actual write speed for writing data into the storage apparatus with a predetermined write speed at the write check point; and adjusting the actual write speed when a difference between the actual write speed and the predetermined write speed is larger than a predetermined value, for adaptively reducing the difference to be smaller than or equal to the predetermined value. |
| US09135893B2 |
Display device
A display device is provided. The display device comprises a display comprising a plurality of pixels arranged in a display plane. The display device is configured to determine a virtual plane at which a long-sighted user of the display device who is looking at the display sees sharp. Further, the display device is configured to determine a first contiguous group of pixels of the display which are located within a first optical path from a first virtual pixel of the virtual plane to an eye of the long-sighted user, and to determine a second contiguous group of pixels of the display which are located within a second optical path from a second virtual pixel of the virtual plane to the eye of the long-sighted user. |
| US09135890B2 |
Display device and driving method thereof
The present invention relates to a display device and a driving method thereof. A display device according to exemplary embodiments of the present invention includes: a signal controller to process an input image signal and an input control signal to control output of a digital image signal; a gray voltage generator to generate a gray reference voltage; and a data driver to generate gray voltages based on the gray reference voltage from the gray voltage generator, to receive the digital image signal, and to output a portion selected from the generated gray voltages as a data voltage, wherein the gray reference voltage includes a first gray reference voltage for the input image signal and a second gray reference voltage for an insertion gray, and the gray voltage generator generates one of the first gray reference voltage or the second gray reference voltage according to the selection signal included in the control signal to be provided to the data driver. |
| US09135887B2 |
Display device and driving method of the same
A display device includes: a display panel including scan lines, data lines, and color pixels located at crossing regions of the scan lines and the data lines, each of the color pixels including a driving transistor, the color pixels including first color pixels, second color pixels, and third color pixels; a scan driver configured to transfer a scan signal; a data driver configured to transfer an image data signal; an initialization voltage controller configured to set different initialization voltages for each pixel during each frame according to a threshold voltage deviation for the driving transistor of each pixel and calculate the initialization voltages including first, second, and third initialization voltages corresponding to the plurality of color pixels; an initialization voltage driver configured to apply the calculated first, second, and third initialization voltages; and a signal controller configured to generate and transfer a control signal and the image data signals. |
| US09135884B2 |
LCD plateau power conservation
Described herein are power conservation systems and methods that reduce power consumption for an electronics device including a liquid crystal display (LCD). The LCD includes a backlight that offers multiple luminance levels, where each level consumes a different amount of power. The systems and methods alter video information while the backlight remains at a backlight luminance level. The alteration reduces luminance for the video information to produce new video information that can be presented at a lower backlight luminance level. Change to the lower backlight luminance level may then occur without significantly affecting aggregate luminance of the new video information, as perceived by a user. The LCD and electronics device consume less power at the lower luminance level. |
| US09135879B2 |
Chamfer circuit of driving system for LCD panel, uniformity regulating system and method thereof
The present disclosure provides a chamfer circuit in a driving system of a liquid crystal display (LCD) panel and a uniformity regulating system and method. The chamfer circuit comprises a discharging resistor. The discharging resistor is an adjustable resistor, a resistance of the adjustable resistor is adjustable. In the present disclosure, a slope of a chamfered section is changed by regulating the resistance of the discharging resistor to change uniformity of the LCD panel. In this way, the discharging resistance is regulated without replacing the discharging resistor, and the uniformity of the LCD panel is regulated in accordance with each piece of the LCD panel. |
| US09135878B2 |
Shift register and liquid crystal display device using the same
A shift register is provided that outputs a gate driving pulse even if a start pulse provided to a first stage is not synchronized with a clock pulse. The shift register has multiple stages that sequentially output gate driving pulses. At least one stage includes a first switching device turned-on by a first clock signal and applying the start pulse to a first node. A second switching device is turned-on by the first clock signal and applies a first supply voltage to a second node. A third switching device is turned-on by the start pulse applied to the first node and outputs a second clock signal. A fourth switching device is turned-on by the first supply voltage and outputs a second supply voltage. A fifth switching device is turned-on by the start pulse and applies the start pulse to the first node. |
| US09135874B2 |
Display device and driving method thereof
The present invention provides a display device with reduced power consumption and that reduces changes in luminance, and perceptibility of flicker, and a driving method thereof. A display device according to an exemplary embodiment comprises: a display panel configured to display a still image and a motion picture; a signal controller configured to control signals for driving the display panel; and a graphics processing unit configured to transmit input image data to the signal controller, wherein the signal controller comprises a frame memory configured to store the input image data, and the display panel is driven at a first frequency when the motion picture is displayed and the display panel is driven at a second frequency that is lower than the first frequency when the still image is displayed. |
| US09135873B2 |
Liquid crystal display device
According to one embodiment, a liquid crystal display device includes an array substrate, a counter-substrate, a liquid crystal layer and a signal line driver. The array substrate includes a signal line, a pixel electrode, and a thin-film transistor. The counter-substrate includes a common electrode. The signal line driver is configured to deliver video signals of a positive polarity and a negative polarity to the signal line. The signal line driver is configured to deliver, prior to delivering the video signals to the signal line, a precharge signal to the signal line in every 1 horizontal scanning period. |
| US09135867B2 |
Display element pixel circuit with voltage equalization
This disclosure provides systems, methods and apparatus for improving the reliability of dual actuator light modulators by equalizing voltages provided to the two actuators of the light modulator. A pixel circuit for driving the dual actuator light modulator can include a data loading circuit coupled to an actuation circuit. The data loading circuit is utilized to store data received from a controller for a pixel associated with the light modulator. The actuation circuit is utilized to control a first actuator and a second actuator of the dual actuator light modulator based on the data stored by the data loading circuit. The actuation circuit includes a first stabilization capacitor and a second stabilization capacitor for stabilizing voltages provided to the first and second actuators. The actuation circuit also includes an equalization switch for equalizing voltages provided to the first and second actuators. |
| US09135864B2 |
Systems and methods for accurately representing high contrast imagery on high dynamic range display systems
A dual-panel display system is provided that comprises control modules and algorithms to select codeword pairs (CWs) to drive a first image-generating panel and a second contrast-improving panel. The first codewords is selected by considering some characteristics of the input image data (e.g., peak luminance) and to improve some image rendering metric (e.g., reduced parallax, reduced contouring, improved level precision). The first codeword may be selected to be the minimum first codeword within a set of codeword pairs that preserves the peak luminance required by the input image data. Also, the first codeword may be selected to minimize the number of Just Noticeable Difference (JND) steps in the final image to be rendered. The second codeword may be selected to similarly improve image quality according to a given quality metric. |
| US09135859B2 |
Organic light-emitting diode display for minimizing power consumption in standby mode, circuit and method for driving thereof
According to the present invention, there is discussed an organic light-emitting diode display device. More particularly, the present invention relates to an organic light-emitting diode display device for minimizing power consumption in a standby mode in which no images are displayed but not in a normal mode in which typical images are displayed, and a driving circuit and method thereof. An organic light-emitting diode according to an embodiment of the present invention may control a drain-source voltage (VDS) of the drive transistor provided in the pixel, thereby having an effect of capable of minimizing power consumption when in a standby mode. |
| US09135855B2 |
Display device, electronic device, driving circuit, and driving method thereof
A display device includes a pixel circuit that supplies current to a light emitting diode (LED) and a driver circuit. The pixel circuit includes a constant current circuit including a first transistor and a capacitor connected to a gate terminal of the first transistor, and a switch circuit including a second transistor. The driver circuit controls the pixel circuit such that the LED emits light by connecting the anode of the LED diode and the first power line under a non-light emission state of the LED, connecting the gate terminal of the first transistor and the anode after the anode is disconnected from the first power line, setting the gate terminal of the first transistor to a voltage corresponding to an amount of a supply current from the first power line, and after setting the gate terminal, switching a state of the LED into a light emission state. |
| US09135851B2 |
Methods and systems for measuring and correcting electronic visual displays
The present disclosure relates to methods and systems for measuring and correcting electronic visual displays. A method in accordance with one embodiment of the present technology includes generating a series of patterns for illuminating proper subsets of the light emitting elements of the display, such as regular grids of nonadjacent activated light emitting elements with the elements in between deactivated. For each generated pattern, an imaging device captures information about the activated light emitting elements. A computing device analyzes the captured information, comparing the output of the activated light emitting elements to target output values, and determines correction factors to calibrate the display to better achieve the target output values. In some embodiments, the correction factors may be uploaded to firmware controlling the display or used to process images to be shown on the display. |
| US09135850B2 |
Indicating operating system selection
Techniques related to abrasion scorings for illuminating operating system selections are described herein. A first abrasion scoring of a display material may reflect light from a first light source resulting in an image associated with a first operating system of the computing device being illuminated at the display material. A second abrasion scoring of the display material may reflect light from a second light source resulting in an image associated with a second operating system of the computing device being illuminated at the display material. |
| US09135849B2 |
Variable operating mode HMD application management based upon crowd determined distraction
Disclosed is a system and method for managing variable operating mode applications that vary a cognitive load of the output of the applications presented to users wearing head mounted display devices. A tolerance level is indicative of the cognitive load of each operating mode of an application is established. In a vehicle setting, the operating mode of the application is selected to enable the safe operation of the vehicle based in part upon the tolerance level associated with the operating mode. If errant operations of vehicles are detected, then an application server modifies the tolerance level and synchronizes the modified tolerance level with head mounted display devices including the application. |
| US09135844B2 |
Optical projection system capable of detecting projection image deformation and associated detection method
An optical projection system capable of detecting projection image deformation is provided. The optical projection system includes a laser source system, a scan unit, a detection unit and a signal control processing unit. The laser source system generates a visible laser having a visible wavelength and a detection laser. The scan unit projects the visible laser and the detection laser onto a projection plane, and drives the visible laser and the detection laser to scan along multiple scan lines to form a projection image. The detection unit detects the detection laser reflected by the projection plane, and outputs a voltage signal. The signal control processing unit determines whether the projection image is deformed according to the voltage signal, and accordingly determines whether to perform a correction operation. |
| US09135842B1 |
Mobile display and advertising assembly
A vehicle mounted display system generating advertising and/or other displayed messages which are clearly viewable from at least a rear exterior vicinity of the vehicle. An electronically powered display may comprise a digital display screen, such as an LCD, or a mechanically driven but electronically powered scrolling assembly. A mounting assembly selectively disposes the display assembly between operative and stored positions and a viewing assembly including at least one camera disposed to observe exterior areas which are obstructed by the operatively positioned display assembly. The viewing assembly also comprises a camera display disposed to be clearly viewable by the vehicle operator enables the operator to the view the obstructed areas. |
| US09135840B2 |
Multi-sectioned, billboard-mounted light-emitting device
The present invention relates to a multi-sectioned, billboard-mounted light-emitting device comprising: a mounting frame onto which one or a plurality of partition pieces are joined by being slotted in a detachable fashion, and on the front of which are formed a plurality of billboard housing space parts; a light-emitting-diode module in which a plurality of LEDs are provided at predetermined intervals; a light-guide plate which surface emits due to the LEDs; a back-surface plate devised such that the light generated from the light-guide plate is emitted towards the front surface; and a billboard plate which is provided on the front surface of the light-guide plate while being received in a detachable fashion at a size matched to each of the billboard housing space parts which are section bared by means of the partition pieces. |
| US09135835B2 |
Stain-resistant label adhered to product including one or more label-staining materials therein
In combination, a plastic label attached to an outer surface of a product by a pressure sensitive adhesive. The pressure sensitive adhesive is attached to an exposed surface of an inner surface layer of the label, and the product includes one or more materials capable of migrating through the label and providing visible stains therein. The inner surface layer of the label includes a hydroxyl functionalized polyether amine resin preventing the material exuded from the product from migrating through the label thickness to provide visible staining of said label. A single extruded film of the label or the core of a multilayer label including either high crystalline polypropylene homopolymer, with or without a hard resin, or a conventional polypropylene with a hard resin. |
| US09135833B2 |
Process for selecting compressed key bits for collision resolution in hash lookup table
A method and network element identify a set of bit indices for forming compressed keys, which are used to map a set of keys of corresponding input values to assigned lookup values in a hash table, where the keys of the input values have colliding hash values according to a hash function of the hash table. The method includes a set of steps including receiving the set of keys. The bits of the set of keys are traversed to find a best split bit index. The set of keys are split into two subsets according to the best split bit index. A check is made whether all of the set of keys have been split into separate subsets. A selected best split bit is added to a bit index. Alternate split bits are tallied and a bit is selected with a highest tally to add to bit index. |
| US09135830B2 |
Airport travel surface edge lighting and foreign object detection system and method
An object detection system for use in airports including an airport travel surface light assembly, a rotatable sensor assembly mounted on the airport travel surface light assembly for sensing objects and an omnidirectional illuminator mounted above the rotatable sensor assembly. |
| US09135829B2 |
Distance separation criteria indicator
Methods, systems, and computer-readable media described herein provide for the display of aircraft traffic and climb/descent information on an aircraft display. Flight data is received from a traffic aircraft in the vicinity of an ownship aircraft. Similar flight data is determined for the ownship aircraft. The flight data for the traffic aircraft and the ownship aircraft is used to determine a criteria indicator that is associated with at least the longitudinal separation and closure rate between the two aircraft. According to various embodiments, a number of altitude indication lines are displayed and an aircraft traffic indicator and ownship indicator corresponding with the traffic aircraft and ownship aircraft are displayed on the appropriate altitude indication lines. The criteria indicator is displayed so that the position of the criteria indicator with respect to the aircraft traffic indicator and ownship indicator informs a pilot as to whether an altitude change is possible. |
| US09135821B2 |
System and method for identifying parking spaces for a community of users
A mobile communications device includes a locator unit to receive and process information regarding a current location for the mobile communications device, a parking status determination unit to determine a parking status for the device based on at least changes in the current location, and a communication unit to forward the parking status to a parking community processor. A method includes determining a parking status of a vehicle associated with a person as a function of movement of a personal mobile communications device. |
| US09135817B2 |
Traffic management system
A real-time traffic management system comprising a main light controller module configured to monitor and control functionality of one or more traffic lights, a master control unit server software application, a network operations control module, and a network watcher application program. The main light controller nodule communicates with one or more coordinating light controller modules, onsite personnel, and a network operations center. The main light controller uses a camera that detects instances of vehicle demand and provides live images for situational awareness. The main light controller module comprises a global positioning satellite receiver and a light sensor for monitoring ambient lighting conditions. The network watcher application program continuously scans incoming data, monitors performance of all components in the system, and issues alerts and alarms to notify personnel of events or conditions outside of established tolerances. |
| US09135816B2 |
Intelligent laser tracking system and method for mobile and fixed position traffic monitoring and enforcement applications
An intelligent laser tracking system and method for mobile and fixed position traffic monitoring and enforcement applications. The system disclosed herein can autonomously track multiple target vehicles with a highly accurate laser based speed measurement system or, under manual control via a touch screen, select a particular target vehicle of interest. In a mobile application the police vehicle speed is determined through the OBD II CAN port and updated for accuracy though an onboard GPS subsystem. The system and method of the present invention simultaneously provides both narrow and wide images of a target vehicle for enhanced evidentiary purposes. A novel, low inertia pan/tilt mechanism provides extremely fast and accurate target vehicle tracking and can compensate for geometrical errors and the cosine effect. |
| US09135812B1 |
Miniature remote controller
A shortened adapter for a light bulb socket with highly overlapped male and female parts with an insulating hand-ring that extends only partially over the external surface of the adapter's female threading so it fits into the unthreaded collar of a light bulb socket, thereby significantly reducing the light bulb displacement. The shortened adapter can respond to an incoming signal and control the output of a light bulb. A reversible ring on the insulating hand-ring can change the adapter from being a dimmer to being an on-off control. A mechanism is disclosed to reversibly lock the adapter onto a light bulb. A miniature remote controller to work with the adapter is provided that has many advantages because of its very small size and compact shape. Further, one such controller can control several lights and several such controllers can control a single light in arbitrary combinations selected by the user. |
| US09135804B2 |
Systems and methods for assessing risks of pressure ulcers
A system, method and computer program product for assessing a risk of developing pressure ulcers, including a user input unit configured to receive facility setting information and objective and subjective information of a patient for a plurality of categories of patient data; a correlation unit configured to determine a corresponding risk value of developing a pressure ulcer for each category of patient data, based on the patient data received in each category; and a risk determination unit configured to determine a level of risk of a patient developing a pressure ulcer based on the correlated risk values. |
| US09135803B1 |
Advanced vehicle operator intelligence system
The method, system, and computer-readable medium causes the monitoring of a vehicle operator during the course of vehicle operation to determine whether the vehicle operator is impaired and causes a mitigating response when an impairment is determined to exist. The vehicle operator, the environment surrounding the vehicle, or forces acting on the vehicle may be monitored using a variety of sensors, including optical sensors, accelerometers, or biometric sensors (e.g., skin conductivity, heart rate, or voice modulation). When the vehicle operator is determined to be impaired, an alert or other mitigating response is implemented, based on the sensor data. In some embodiments, mitigating actions may be taken to avoid vehicle operator impairment. |
| US09135802B2 |
Hardware attitude detection implementation of mobile devices with MEMS motion sensors
Systems and methods for detecting an attitude of a device are disclosed. The system includes a processing system including at least a sensor processor and an application processor, which are distinct. The system further includes a memory system including one or more computer-readable media. The computer-readable media contains instructions that, if executed by the processing system, cause the system to perform operations. The operations include executing an application using the application processor, and receiving raw sensor readings from one or more sensors, using the sensor processor. The operations also include determining, using the sensor processor, a processed sensor metric comprising attitude data, and transmitting the processed sensor metric to the application. |
| US09135792B2 |
System and method generating motor driving signal and method controlling vibration
A system and method that generate a vibration motor driving signal includes; a first control unit that receives a first input signal and gain-adjusts the first input signal in response to a reference voltage to generate a first output signal, and a second control unit that receives the first output signal and gain-adjusts the first output signal in response to the reference voltage to generate a second output signal, wherein the second output signal is applied to a vibration motor as the vibration control signal. |
| US09135791B2 |
Haptic information presentation system and method
A system and method are disclosed in which in a conventional non-grounding man-machine interface having no reaction base on the human body and for giving the existence of a virtual object and the impact force of a collision to a person, a haptic sensation of a torque, a force and the like can be continuously presented in the same direction, which cannot be presented by only the physical characteristic of a haptic sensation presentation device. In a haptic presentation device, the rotation velocity of at least one rotator in the haptic presentation device is controlled by a control device, and a vibration, a force or a torque as the physical characteristic is controlled, so that the user is made to conceive various haptic information of the vibration, force, torque or the like. |
| US09135785B2 |
Gaming system and method providing indication of notable symbols
The gaming device and method disclosed herein produces an indication of an appearance of a notable or designated symbol in a symbol display region while at least one reel is spinning. The indication continues while the notable symbol appears in the symbol display region and while the at least one reel is spinning. Different indications are produced for the different notable symbols when appearing in the symbol display region while the at least one reel is spinning. |
| US09135782B2 |
Gaming machine and control method thereof
To provide a gaming machine and a control method therefor, having a new entertainment characteristics, a slot machine 10 of the present invention, when a “BONUS” symbol 250 associated with a pick-up bonus game is selected, receives selection of any one of twenty little pig's noses 210 displayed. Then, a benefit associated with the selected little pig's nose 210 is awarded. When the benefit to be awarded is a “stick house” 218 which means “step-up”, a step-up occurs to the stick house stage and the expectation value for a payout is raised. Thus, when one little pig's nose 210 is selected out of the twenty little pig's noses 210 displayed in the stick house stage, the payout amount of the benefit associated with the little pig's nose 210 is increased. |
| US09135781B2 |
Gaming machine and control method thereof
To provide a gaming machine and a control method therefor, having a new entertainment characteristics, a slot machine 10 of the present invention, when a “BONUS” symbol 250 associated with a pick-up bonus game is selected, receives selection of any one of twenty little pig's noses 210 displayed. Then, a benefit associated with the selected little pig's nose 210 is awarded. When the benefit to be awarded is a “stick house” 218 which means “step-up”, a step-up occurs to the stick house stage and the expectation value for a payout is raised. Thus, when one little pig's nose 210 is selected out of the twenty little pig's noses 210 displayed in the stick house stage, the payout amount of the benefit associated with the little pig's nose 210 is increased. |
| US09135780B2 |
Enhanced wagering game system with additional bonus challenges
A gaming system and method for conducting a wagering game includes a display having a display area showing a poker-themed wagering game. A wager input device receives a base wager to play the poker-themed wagering game. A controller is coupled to the display and the wager input device. The controller is operative to provide a plurality of symbol-bearing objects to form a user-playable hand and award a payoff based on a ranking of the user-playable hand meeting a predetermined criterion. The controller may receive a side wager separate from the base wager from the player to trigger a challenge based on meeting a condition in at least one of a predetermined number of future plays of the wagering game. Additional free challenges may be triggered for the predetermined number of future plays. |
| US09135777B2 |
Management of downloadable game components in a gaming system
Systems and methods provide interfaces to control the download of downloadable game components to one or more gaming machines or systems. The gaming configuration elements may include banner content, advertising content, denomination data, pay table, language data, video content, audio content, episodic game data, wagering game software, operating system software, device driver software and device firmware. |
| US09135776B2 |
Autonomous agent hybrid games
Systems and methods in accordance with embodiments of the invention operate an autonomous agent hybrid game including a gambling game providing a game of chance and an entertainment game providing a game of skill, where the autonomous agent hybrid game utilizes an agency module constructed to: configure an agent player profile based upon player instructions, where an agent player action during entertainment game gameplay is determined by the configuration of the agent player profile; communicate an agent gameplay gambling event occurrence based upon an agent player action to the gambling game, where the gameplay gambling event occurrence triggers an agent wager in the gambling game; and allocate a payout from the agent wager to a player profile associated with the player instructions based upon the agent player profile. |
| US09135775B2 |
Remote live automatic electro-mechanical and video table gaming
Electro-mechanical and video table games of chance send video feeds of game play and digital representations of results of game play by network communications to remote clients that receive wagers placed upon the result of the game play and derives a winning or a loss from both the wager and the digital representation of the result of the game play. The table game can include a roulette wheel, a roulette style ball, a device for rotating the roulette wheel at randomly changing rotational speeds, and a device for mechanically propelling the roulette style ball onto the rotating wheel at randomly changing velocities and spins. Also included can be a platform for supporting a die having a plurality of surfaces each bearing indicia unique to that on the other surfaces, and a device for randomly changing the movement and speed of the platform relative to the die. |
| US09135771B2 |
Memento dispensing device with simulated gaming features
A memento dispensing device for dispensing mementos in the form of tokens, medallions, souvenirs, and other articles or objects having commemorative value through the simulated operation of a gaming device commonly referred to and known in the art as a slot machine. Instructive steps set forth in a computer program, as executed and controlled by a main microcontroller, serve to direct and command the memento dispensing device to dispense at least one memento to the consumer or operator upon the consummation of a spin cycle for a set of mechanical reel wheels or simulated reel wheels on a video display. The main microcontroller, operating under the direction of the computer program, further directs the timed playback of video and audio stored on recognizable formats and activates lights at select moments during operation and after every instance the memento is dispensed from the memento dispensing device. |
| US09135768B2 |
Vertical medication storage system
Storage systems for inventory control are disclosed. The storage systems include a vertical storage structure having a plurality of vertically-stacked pockets. Each vertically-stacked pocket can be configured to be separately openable for providing user access to contents of the vertically-stacked pocket. The vertical storage structure can be a vertical sliding-type door, a hinged-type door, or a wall-mounted cabinet. |
| US09135766B2 |
Method of identifying a counterfeit bill using a portable terminal
A method and a portable terminal for identifying a counterfeit bill. The method includes receiving, by the portable terminal, an image of a bill photographed using visible rays and an image of the bill photographed using infrared rays; determining a denomination of the bill by comparing the image photographed using the visible rays with a denomination database; obtaining correction information using the image photographed using the visible rays and a corresponding bill image in the denomination database; forming a corrected image by correcting the image photographed using the infrared rays using the correction information; and determining whether the bill is counterfeit by comparing the corrected image with an image of the corresponding bill pre-stored in a genuine bill database. |
| US09135762B2 |
Determining operational state with tags
Systems and methods are provided relating to utilizing a plurality of RFID tags in conjunction with a circuit comprising at least one reed switch to facilitate determination of operational states and actions based thereon. A magnet can activate the reed switch causing a first RFID tag to be activated and transmit an associated RFID identifier from which a position/operation associated with the first RFID can be determined. The magnet can be removed to activate a second RFID tag whereupon a second RFID identifier is transmitted from which a second position/operation can be determined. The circuit comprising the reed switch and RFID tags can have an induction coil enabling the circuit to be activated when the induction coil is brought into proximity of a second induction coil and inductively coupled. |
| US09135760B2 |
Information sharing system, on-vehicle diagnosis terminal, and display terminal
An information sharing system (1) including a plurality of on-vehicle diagnosis terminals (10) and one or a plurality of display terminals (20) and sharing diagnostic information over wireless communication. The terminals (10, 20) include a first determination unit S7, S8 and a second determination unit S34, S35 configured to determine whether or not predetermined times T1, T2 have passed from stored clock times C1, C2 at which data sets DS are acquired from the any of the other terminals (10, 20). When the predetermined times have passed, new data sets DS are acquired and the storing into an other-vehicle data storing unit 15B and a data storing unit 25A is performed. When the predetermined times have not passed, new wireless communication is established with communication units (13, 23) of the terminals (10, 20) capable of establishing wireless communication. |
| US09135759B2 |
Driver measurement and incentive system for improving fuel-efficiency
A vehicle driver is provided with a display interface a smartphone, tablet, PC, or any telematics or in-vehicle device installed in the vehicle. The display interface presents a real-time target for the driver to follow to maximize fuel economy and safety, achieved by modulating the accelerator pedal appropriately. |
| US09135758B2 |
Vehicle status notification and operator identification
A computing system located on-board a vehicle issues an event notification responsive to detection of an event condition. The on-board computing system detects the presence of wireless-enabled devices located within the vehicle or within proximity to the vehicle over a wireless communications link. The on-board computing system seeks to determine the identity of one or more persons that enter, attempt to enter, or operate the vehicle based on identifiers obtained from one or more wireless-enabled devices carried by those persons. The on-board computing system distinguishes multiple users from each other by designating one user as the vehicle operator, and one or more other users as passengers of the vehicle. The on-board computing system may include a removable on-board interface device that interfaces with an on-board vehicle control system. |
| US09135753B2 |
Apparatus and method of augmented reality interaction
A method of augmented reality interaction for repositioning a virtual object on an image of a surface comprises capturing successive video images of the surface and first and second control objects and defining an interaction start area over the surface with respect to the virtual object. The method detects the control objects in successive video images, detects whether the control objects are brought together over the interaction start area, and if so, analyzes a region of successive video images using optical flow analysis to determine the overall direction of motion of the control objects and augmenting the video image to show the virtual object being held by the control objects. Augmenting the video image itself comprises superposing a graphical effect on the video image prior to superposition of the virtual object, such that the graphical effect visually disconnects the virtual object from the video image in the resulting augmented image. |
| US09135751B2 |
Displaying location preview
A mapping application that provides a graphical user interface (GUI) for displaying information about a location is described. The GUI includes a first display area for displaying different types of media for a selected location on a map. The GUI includes a second display area for displaying different types of information of the selected location. The GUI includes a set of selectable user interface (UI) items, each of which for causing the second display area to display a particular type of information when selected. |
| US09135748B2 |
Triangulation method of a surface of a physical object
An exemplary embodiment of the invention provides a method for producing a triangulation of a surface of a physical object the method comprising the steps of generating an intermediate mesh representation of the surface out of surface voxels (102) and detecting at least one T-junction in the intermediate mesh representation (103). The method further comprising the steps of decomposing of the at least one T-junction into at least one triangle and at least one two-point-polygon (104), and generating the triangulation of the surface out of the modelled intermediate mesh representation (107). |
| US09135740B2 |
Animated messaging
A method and apparatus that allows an animated interactive talking character to appear on a user's screen when conducting an Instant Messaging (IM) session. The character which is displayed on the user's screen is determined by a profile for the sender of the message. This allows a user to pre-select which character will be displayed on the screen of recipients of the instant messages. |
| US09135738B2 |
Efficient elasticity for character skinning
A novel algorithmic framework is presented for the simulation of hyperelastic soft tissues that drastically improves each aspect discussed above compared to existing techniques. The approach is robust to large deformation (even inverted configurations) and extremely stable by virtue of careful treatment of linearization. Additionally, a new multigrid approach is presented to efficiently support hundreds of thousands of degrees of freedom (rather than the few thousands typical of existing techniques) in a production environment. Furthermore, these performance and robustness improvements are guaranteed in the presence of both collision and quasistatic/implicit time stepping techniques. The result is a significant advance in the applicability of hyperelastic simulation to skeleton driven character skinning. |
| US09135736B2 |
Image processing device and image processing method which gather a plurality of images within an output image
A image processing device includes an image selection means and an image gathering means. The image selection means receives a plurality of rectangular selected images selected by user's operation. The image gathering means overlays specific sides of two selected images on each other among the plurality of selected images to gather the plurality of selected images within an output image corresponding to predetermined paper. |
| US09135735B2 |
Transitioning 3D space information to screen aligned information for video see through augmented reality
Methods, apparatuses, and systems are provided to transition 3D space information detected in an Augmented Reality (AR) view of a mobile device to screen aligned information on the mobile device. In at least one implementation, a method includes determining augmentation information associated with an object of interest, including a Modelview (M1) matrix and a Projection (P1) matrix, displaying the augmentation information on top of a video image of the object of interest using the M1 and P1 matrices, generating a second Modelview (M2) matrix and a second Projection (P2) matrix, such that the matrices M2 and P2 represent the screen aligned final position of the augmentation information, and displaying the augmentation information using the M2 and P2 matrices. |
| US09135724B2 |
Image processing apparatus and method
This technique relates to an image processing apparatus and a method for improving the coding efficiency for a quantization parameter.Provided are a predicted quantization parameter setting unit for setting a predicted quantization parameter for a current coding unit by using multiple quantization parameters which are set for multiple surrounding coding units located around the current coding unit which is target of coding processing, and a difference quantization parameter setting unit for setting a difference quantization parameter indicating a difference value between the quantization parameter which is set for the current coding unit and the predicted quantization parameter which is set by the predicted quantization parameter setting unit. The present disclosure can be applied to, for example, an image processing apparatus. |
| US09135719B1 |
Color name generation from images and color palettes
Systems and methods are provided for generating color names for colors corresponding to images and/or palettes. A color image is obtained, and one or more color palettes corresponding to the color image are identified. The color palette may be generated based on palette generation criteria, which may facilitate or control a palette generation process. Illustratively, the palette generation process may include image pre-processing, color distribution generation, representative color identification, palette candidate generation, and palette determination. A color name for each color identified in the color palette and/or the color image can be identified based at least in part on color name popularity information. Color name popularity information may be identified from color name-related voting results provided by a social network site. Aspects of the disclosure are further directed to processing the identified color name(s), such as updating color name metadata associated with the original color image and/or the color palette. |
| US09135715B1 |
Local feature cameras for structure from motion (SFM) problems with generalized cameras
Methods and systems for extraction of 3D geometry from a plurality of generalized camera images by a device that comprises an electronic circuit are provided. Methods include identifying an x and y coordinate, an orientation, and a scale for each of one or more feature locations in each of the generalized camera images, extracting a local image feature at each feature location, generating a feature camera centered on each feature location, identifying groups of feature cameras providing consistent triangulation opportunity, and triangulating each identified feature camera group by finding the 3D point that minimizes an error term. |
| US09135714B1 |
Method and system for integrating a graphical user interface capture for automated test and retest procedures
According to an embodiment of the present invention, a computer implemented system and system for capturing an image for automated test and retesting using an image capture function provided by a computer processor comprises: a capture tool, comprising at least one processor, configured to capture a screen image, a click position and user interaction; an image processing module, comprising at least one processor, configured to receive the screen image and generate a sub-image based at least in part on the click position; and a display module, comprising at least one processor, configured to display the sub-image and the user interaction to the user for generating at least one automated test step. |
| US09135712B2 |
Image recognition system in a cloud environment
An image recognition system in a cloud environment including uploading a plurality of images to the cloud environment, preprocessing the plurality of images, determining image classifiers for each of the plurality of images, extracting the features of each of the plurality of images, storing the images, features and classifiers, determining the image classifiers and key features of an image to be recognized from a multiplatform image device, selecting from the plurality of images, images which have the same classifiers as the image to be identified, matching a best one of the selected images with the image to be identified and displaying the match on a display of the .multi-platform image device. The system further functions by performing one or more of the above in the multiplatform imaging device and/or cloud environment. |
| US09135710B2 |
Depth map stereo correspondence techniques
Depth map stereo correspondence techniques are described. In one or more implementations, a depth map generated through use of a depth sensor is leveraged as part of processing of stereo images to assist in identifying which parts of stereo images correspond to each other. For example, the depth map may be utilized to describe depth of an image scene which may be used as part of a stereo correspondence calculation. The depth map may also be utilized as part of a determination of a search range to be employed as part of the stereo correspondence calculation. |
| US09135707B2 |
Real-time quality control of EM calibration
A probe (20) generates a plurality of image volumes (13i, 13j) of an anatomical object (10) within a coordinate system (11) and an imaging device (21) generates imaging data (22) representative of the image volumes (13i, 13j) of the anatomical object (10). A position sensor (30) is attached to the probe (20), and a tracking device (31) generates tracking data (22) representative of a tracking of the position sensor (30) within the coordinate system (11). A registration device (40) executes a validation testing of a calibration matrix (51) associated with a spatial relationship between the image volumes (13i, 13j) and the position sensor (30). The validation testing includes a testing of an absolute differential between an image based volume motion (VMIB) and a tracking based volume motion (VMTB) relative to a calibration threshold (CT). |
| US09135693B2 |
Image calibration and analysis
Systems, methods, apparatuses and computer program products for image calibration and analysis are described. One aspect provides quantitatively analyzing a representation of a dermatological condition of an image; and providing one or more outputs responsive to said quantitatively analyzing said representation of said dermatological condition of said image. Other embodiments are described. |
| US09135689B2 |
Apparatus and method for performing detail enhancement
An apparatus and method are provided for performing detail enhancement. The apparatus includes an edge detector that detects an edge pixel from contents based on a luminance component of the contents, a histogram analyzer that generates at least one histogram with respect to the edge pixel and determines a gain variable value of the edge pixel based on the at least one histogram, and a gain regulator that determines a gain corresponding to the gain variable value of the edge pixel. |
| US09135688B2 |
Method for brightness equalization of various images
The present invention provides a method for brightness equalization of a plurality of images to equalize brightness when composing, into a single image, a plurality of images acquired from a plurality of cameras. |
| US09135687B2 |
Threshold setting apparatus, threshold setting method and recording medium in which program for threshold setting method is stored
Disclosed is a threshold setting apparatus including a creating unit which creates a plurality of images of tones by performing a tone conversion process on an original image including a subject by using a plurality of temporary thresholds which are different from each other, a subject detection unit which detects the subject in each of the plurality of images of tones which are created by the creating unit, an evaluation value calculating unit which calculates evaluation values relating to likeness to the subject from the plurality of subjects detected by the subject detection unit and associates the evaluation values with the temporary thresholds, and a setting unit which sets a threshold suited for the tone conversion of the original image based on the plurality of evaluation values calculated by the evaluation value calculating unit. |
| US09135685B2 |
Image processing method and image processing device
A method includes: calculating a pixel statistical value and edge of pixels for each of areas of a multi-layer, the areas each containing a target pixel and having a successively decreased range; correcting the edge based on a pixel statistical value of an area that is wider than an area of a specific layer; correcting difference between a pixel statistical value of the specific layer and the pixel statistical value of a layer that is wider than the specific layer using the post-correction edge; correcting the pixel statistical value of the specific layer using post-correction difference and the pixel statistical value of the layer that is wider than the specific layer; and correcting the target pixel by repeating correction of the pixel statistical value successively in each layer until the area reduces its range from the maximum range to the minimum range. |
| US09135681B2 |
Image chroma noise reduction
An embodiment of a method for reducing chroma noise in digital image data and of a corresponding image processor. Chrominance components are subjected to low-pass filtering. The strength of the low-pass filtering is modulated in accordance with the dynamic range of the luminance signal and the dynamic range of each of the two chrominance signals in order to avoid color bleeding at image-object edges. Moreover, the low-pass filtering is selectively applied to pixels with similar luminance and chrominance values only. A combination of down-sampling and up-sampling units is employed so that comparatively small filter kernels may be used for removing chroma noise with low spatial frequency. |
| US09135677B2 |
Apparatus which layout one or more images and produce output, and the method thereof
An apparatus comprising: a determination unit configured to determine whether an object image satisfies a predetermined standard, if the object image is changed to a standard image size predetermined; a changing unit configured to change the standard image size predetermined, in case that the object image does not satisfy a predetermined standard by the determination unit; a generation unit configure to change the image to the image standard image size predetermined set or the standard image size changed by the standard image size changing unit and to generate the layout image. |
| US09135672B2 |
Display system and data transmission method thereof
A display system and a data transmission method thereof are provided. When a first frame stored in a frame buffer is identical to a second frame to be output from an audio and video (AV) source, the AV source is set an AV control signal corresponding to a self-refresh mode, and a timing controller reads the first frame to output a display data controlled by the AV control signal. When the first frame is differed from the second frame, the AV source is set the AV control signal corresponding to a data update mode and a AV data signal corresponding to the second frame, and the timing controller stores the second frame in the frame buffer controlled by the AV control signal and outputs the display data corresponding to the first frame or the second frame according the timing sequences of the AV data signal and the display data. |
| US09135670B2 |
Operational reliability systems and methods
An operational reliability system includes a flight grouping module, a block modification module, and a pairing optimizer. The system evaluates potential modifications to scheduled flight block time and quantifies associated changes in on-time performance B0. The system also evaluates the impact of block modifications to headcount, regulatory compliance, operating expenses, and so forth. Via use of the operational reliability system, compliance with external regulations, for example Federal Aviation Regulations (FAR), may be achieved with a higher degree of probability. |
| US09135669B2 |
Interrogation system employing prior knowledge about an object to discern an identity thereof
An interrogation system employable with an object having a radio frequency identification (RFID) tag and method of operating the same. In one embodiment, the interrogation system includes a database having prior knowledge about the object, and an interrogator that scans the RFID tag and discerns additional information therefrom about the object. The interrogator still further includes a control system that identifies the object based on the prior knowledge and the additional information. |
| US09135667B2 |
Systems and methods for building energy use benchmarking
Systems and methods for using an energy use model of a building for benchmarking is shown and described. An exemplary method includes receiving building data indicative of one or more characteristics of the building. The method further includes generating an energy use model for the building based on the building data and using the energy use model to generate statistics for the building. The method also includes identifying one or more other buildings having the same classification as the building. The method yet further includes comparing the generated statistics for the building to statistics for the identified one or more other buildings and providing an indication of the comparison. |
| US09135661B2 |
System and method for determining the liquidity of a credit
The present invention relates to a credit index, a system and method for structuring a credit index, a system and method for operating a credit index, and a system and method for determining the liquidity of a credit. |
| US09135652B2 |
Scannable recipe card to add items to shopping list
A system and method for automatically importing retail grocery products into an electronic shopping list by importing the ingredients listed on a recipe card, page in a recipe book, or the like. The recipe card may contain an identifier code that is uniquely associated with that recipe. The identifier code may be presented on the recipe card as a bar code. The system includes a database of recipes that returns a list of products when queried with a recipe identifier code. A user may scan or otherwise import the recipe identifier code through a mobile computing device, which then presents the ingredients as products in an electronic shopping list. The electronic shopping list may be implemented in a smartphone app. |
| US09135650B2 |
Person-to-person item recommendation with decline
A system that allows individuals to maintain lists of items of interest in an account, such as books, restaurants, hotels, clothes, etc. The system allows an individual to share an item in a list with another individual. When an individual wishes to share an item, the system may generate a share message to be sent by a selected method to a recipient. The share message may include a link for allowing the recipient to view the item on the system and provide a mechanism for allowing the recipient to accept or decline the share. The acceptance or, in particular, the rejection of the share establishes a positive or negative relationship between each individual and the item. The sharing of Items between individuals can be temporally and geographically mapped to identify patterns of interest, the value of an item to one or more people, or the strength of the bond between two or more people. |
| US09135647B2 |
Methods and systems for flexible and scalable databases
Methods and systems for utilizing a database are disclosed. The methods and systems determine a key representative of a storage location of first RDF data in a NoSQL database. In addition, the methods and systems read the first RDF data in the NoSQL database using the key. The methods and systems also write second RDF data derived from the first RDF data into a second database stored in memory. The methods and systems may also modify the second RDF data, and write third RDF data derived from the modified second RDF data into the NoSQL database. |
| US09135645B2 |
Systems and methods for commerce in media program related merchandise
The disclosed technology provides systems and methods for delivering a media program and purchase opportunities related to the media program to user equipment. A media program and its related merchandise information can be located at a distribution facility. The distribution facility can tailor the purchase opportunities it provides to the user equipment based on the user equipment's equipment category. When user equipment receives purchase opportunities, the user equipment can select the opportunities based on which types of merchandise are supported by the user equipment. The user equipment and/or a distribution facility may be able to determine the location of the user equipment. When the distribution facility provides merchandise information for physical merchandise to the user equipment, the merchandise information can be selected to include physical merchandise that are available for purchase at stores that are, for example, near the location of the user equipment. |
| US09135639B2 |
Systems and methods for selecting advertisements for display over a communications network
Systems and methods are provided for selecting advertisements for display over a communications network and, more particularly, to systems and methods for selecting video advertisements for display within internet web pages based on relevance, bid price, past performance, or a combination thereof. |
| US09135638B2 |
Software program and method for offering promotions on a phone
The present invention includes a method and software application for providing a promotion to a user on a phone. The software application resides on a user's phone and “listens” for phone numbers dialed by a user. In response to the user dialing a phone number, the software determines whether a promotion or an offer for a promotion should be provided to the user. In response to determining to play or offer to play a promotion to the user, the software application on the phone effectively “intercepts” the call and plays to the user either a promotion or an offer to hear about a promotion prior to placing an outbound voice call. The software application may retrieve the promotion from local memory or may connect with a remote server to download an applicable promotion. |
| US09135636B2 |
System and method for routing media
The system and method for streaming media to a viewer and managing the media comprises an enhanced service routing processor (ESRP), a real time switch management system (RTSMS), a name routing processor (NRP), and a managed media switch (MMS). The RTSMS has a reservation system. The ESRP receives media from an owner, manages the media according to media rules and order rules defined by the owner, and distributes the media to one or more switches, such as the MMS, according to the media rules and the order rules. The RTSMS is configured to receive the media rules and to receive a viewer's media request via the reservation server. The reservation system of the RTSMS processes the media request according to the media rules and builds a reservation for the requested media. The RTSMS generates the reservation to the viewer and to the NRP. The NRP receives the reservation data from the viewer and from the RTSMS. The NRP processes the reservation data and locates an MMS that can stream the media to the viewer. The NRP transmits the IP address of the MMS to the viewer and transmits the reservation data to the MMS. The viewer initiates a session or connection with the MMS using the reservation number. If the reservation data from the viewer matches the reservation data from the NRP, the MMS streams the media to the viewer. |
| US09135635B2 |
System and method for routing media
The system and method for streaming media to a viewer and managing the media comprises an enhanced service routing processor (ESRP), a real time switch management system (RTSMS), a name routing processor (NRP), and a managed media switch (MMS). The RTSMS has a reservation system. The ESRP receives media from an owner, manages the media according to media rules and order rules defined by the owner, and distributes the media to one or more switches, such as the MMS, according to the media rules and the order rules. The RTSMS is configured to receive the media rules and to receive a viewer's media request via the reservation server. The reservation system of the RTSMS processes the media request according to the media rules and builds a reservation for the requested media. The RTSMS generates the reservation to the viewer and to the NRP. The NRP receives the reservation data from the viewer and from the RTSMS. The NRP processes the reservation data and locates an MMS that can stream the media to the viewer. The NRP transmits the IP address of the MMS to the viewer and transmits the reservation data to the MMS. The viewer initiates a session or connection with the MMS using the reservation number. If the reservation data from the viewer matches the reservation data from the NRP, the MMS streams the media to the viewer. |
| US09135634B1 |
Static discharge station
Implementations of a static discharge station are provided. In some implementations, the static discharge station may be employed by a user to discharge a build-up of static electricity prior to pumping gas. In some implementations, the static discharge station may have advertising thereon. In this way, a user or a passerby may be exposed to the displayed advertisement(s). In some implementations, the static discharge station may be comprised of a body portion having a button thereon, a support pole, a base, a wire, and a grounding rod. In some implementations, the button may be configured to selectively make contact with the support pole of the static discharge station. In some implementation, a user may discharge a static electricity build-up by touching the button. In this way, the static build-up may travel through the button, support pole, base, and wire into the grounding rod. In some implementations, the base may serve to ground the static discharge station without the use of a wire and/or grounding rod. |
| US09135633B2 |
Needs-based mapping and processing engine
A mechanism is disclosed that dramatically minimizes the time it takes to gather needs, dramatically minimizes the expense it takes to gather those needs, and ensures those statements are formulated in manner that comply with a set of rules designed to ensure the right inputs are used in downstream strategy formulation, marketing, product development, and related company workflows. In addition, the mechanism may or may not minimize the time it takes for a company to acquire the capability to uncover these needs statements. |
| US09135627B2 |
Method and system for on-line survey recruitment
A system and method are disclosed for presenting on-line survey invitations to users over a network. The system selectively presents survey invitations to users in accordance with a survey recruitment definition associated with a tag embedded within a Web page (node) downloaded and executed on a user computer. A particular survey is selected from a set of presently active surveys applied by a survey logic server to received requests based upon a category (node ID) provided by a user computer in accordance with the execution of logic contained in the survey recruitment definition. |
| US09135626B2 |
Advertising middleware
A method and system for facilitating interaction with one or more advertisement functionalities is provided. An advertisement middleware provides advertisement functionalities for interfacing with one or more systems and components of an underlying device. The advertisement middleware includes a transport layer, an application programming interface and one or more functional modules. The functional modules may include a player module, a cache, a report module, a profile module, a loyalty module and a payment module. Each module may perform various advertising tasks for an advertisement application. In addition, use of a particular advertisement application may be tracked to provide incentives to developers to create advertisement applications. |
| US09135622B2 |
Secure payment made from a mobile device through a service provider
Methods and systems enable merchants to accept payments through a service provider from a consumer using an app on a mobile device, for example, without redirecting the consumer to the service provider and without collecting the customer's service provider password (a separate PIN may be used). An example of an app on a mobile device is given, but secure payments are also enabled for purchases and other transactions for a website, a merchant, or a service provider who needs to accept payments from customers. A two-key approach allows a merchant, using the two keys—a collection key for merchant apps and general servers and a private, more secure, charge key for merchant “back-end” systems—to collect a user's username and personal identification number (PIN) for acquiring payments through a service provider without compromising the user's service provider username and password (the PIN is distinct from the password). |
| US09135621B2 |
Methods and systems for performing authentication in consumer transactions
The method for authenticating a mail order or telephone order transaction according to the present invention includes receiving authentication information from a cardholder, providing authentication information to an issuer, and determining whether the authentication information is valid. If the authentication information is valid, the issuer informs the merchant that the transaction is valid. In an embodiment, the issuer may not supply a personal assurance message and/or other confidential cardholder information previously supplied by the cardholder in response to the authentication information. |
| US09135619B1 |
Merchant identification of payer via payment path
Novel features to be used in a proxy card payment system include a real-time request to override a declined transaction or to select a different financial account and the insertion of user identification information into the transaction approval message sent to the merchant. A payment request is forwarded to the payment system, which maintains the proxy card account and determines whether the transaction violates a user-defined rule. If the transaction is declined by the issuer that maintains the financial account, or the payment system for violation of a user-defined rule, the payment system sends a real-time message to the user. The user is prompted to override the rule causing the transaction to be declined or to select a new account to process the transaction. Once the payment system receives authorization for the transaction, it inserts the user identification information in an approval message before transmitting the approval to the merchant. |
| US09135616B2 |
Systems and methods to facilitate online transactions
Systems and methods are provided to facilitate online transactions via mobile communications. In one aspect, a system includes a communication interface to receive an input from a merchant; a plurality of converters to interface with a plurality of controllers for delivery of premium messages sent by the system to collect funds for purchases made by customers; and a common format processor coupled with the plurality of converters to send the premium messages. The common format processor determines a combination of one or more premium messages, in response to a first customer making a first purchase from the merchant at a first price. The total price of the one or more premium messages is based on the first price and a portion of service charges associated with the one or more premium messages, where the portion is specified by the input received via the interface. |
| US09135615B1 |
Systems and methods for processing payment transactions at fuel dispensing stations
The methods and systems described herein provide for processing electronic payments at a retail location. Secure payment information for use in processing future payment transactions initiated by a mobile device may be stored at a secure location remote from retail locations. A mobile device of a user may be detected and location determined based at least in part on the strength of a signal via a wireless antennas at the retail location. A determination is made that the mobile device is associated with a user who previously provided payment information for use in processing payment transactions. The mobile device may receive incentives based at least in part on the determined location. A user may complete a payment transaction at the retail location without providing the secure payment information at the retail location. |
| US09135614B2 |
System and method for managing issuance of financial accounts
A system for managing issuance of a corporate meeting account for use in making purchases related to a meeting. The system comprises a communication interface adapted to communicate with a client computer executing an event management software and with a computer from each issuer, a processor coupled to the communication interface, and a management module executable by the processor. The management module receives, through the communication channel, a request to issue a financial account related to the meeting from the event management software. The request includes an issuer identifier and meeting account parameters. The management module generates an account issuance message and transmits the message to a computer of the issuer identified by the issuer identifier. This way, the process of opening a financial account associated with a meeting event is automatically done without having to manually contact the issuer. |
| US09135613B2 |
System and method for controlling financial transactions over a wireless network
A system and method for controlling financial transactions is disclosed. A customer, using a wireless device, identifies a point of sale and the amount of a transaction at that point of sale is first communicated to a central service and then transmitted to the wireless device for display at the wireless device. The customer can either accept the transaction amount to complete the transaction or reject the amount to cancel the transaction. The customer may have to enter a password or personal identification number to verify the authorization to use the wireless financial system. The customer is billed for the transaction via credit, debit, ATM or other methods, such as the wireless carrier or an internet provider. |
| US09135611B1 |
Advanced systems and methods for geographical card
A system, method, and computer-usable medium are disclosed for managing financial transactions by controlling the purchase of allowed and disallowed purchase items. A transaction control card is used to purchase a purchase item. Account information related to the transaction control card and purchase item data related to the purchase item is then processed to determine whether the purchase item is disallowed for purchase by any single, or combination of, disallowed purchase item data parameters. |
| US09135609B2 |
System and method to purchase applications by a point of sale terminal
A system and method to allow users to purchase software applications for point of sale (POS) terminals from an application server via a network (e.g., the Internet) utilizing the POS terminal itself. One or more menus providing portals to available applications and their respective demonstration applications are provided to users on POS terminals. The demonstration applications may be directly downloaded from the application server onto the POS terminals. In addition, the user is able to purchase the application via the POS terminal either before or after the user has viewed/downloaded the demonstration application. After purchase, the application may be downloaded directly from the application server onto the POS terminal. Further, information associated with the demonstration applications downloaded to each POS terminal may be reported to a manufacturer of each demonstration application. |
| US09135606B2 |
Changing email addressee categorization
A request to change an addressee category of a received email is received by a computing device. An indication of a changed addressee category is also received by the computing device. The changed addressee category is propagated to one or more instances of the received email. |
| US09135603B2 |
Methods and systems for merging topics assigned to content items in an online application
A question-and-answer application having questions with which topics are associated is described. In some embodiments, user-generated topics are assigned to questions to indicate the subject matter covered by the questions. The application logic includes topic merge logic for quickly and efficiently merging two topics, while enabling the topic merge operation to be easily undone if necessary. |
| US09135599B2 |
Smart notebook
Techniques are disclosed herein for allowing sharing of notes and ideas between electronic devices. The presence of a number of electronic devices is determined. A determination is made that the electronic devices are to be part of a shared workspace. A shared workspace is generated for the electronic devices. The shared workspace is displayed on a display screen of at least one of the electronic devices. The shared workspace that is displayed may be based on the capabilities of the electronic device. The shared workspace that is displayed may reflect the location of the electronic devices. |
| US09135598B2 |
Anonymous reporting system
An anonymous reporting system (10) is provided for use in reporting and following up on incidents, accidents and the like. The system (10) is initiated by a system provider (12) on behalf of an institutional participant/client (14) for access by any number of individual users (16). The most common implementation is a web based interface (24) including a web site (27). The interface (24) includes an anonymizer (38) for safeguarding the identity of each individual user (16). The system (10) permits the user (16) to enter a report (28) and then assigns a random number identifier (74) associated with the report (28). The report (28) is forwarded to selected recipients (22) and to one or more administrators (32) associated with the participant/client (14). The administrators (32) may request follow up comments or send messages (64) associated with the report (28) by the access number (74) so that the user (16) may continue dialog, all while remaining totally anonymous. The system (10) is especially adapted for use in school or large company situations. |
| US09135595B2 |
High-load business process scalability
The present disclosure involves systems, software, and computer implemented methods for providing high-load business process scalability in cloud-based infrastructures. One process includes operations for receiving a message at a first computer node executing a first business process instance. A second business process instance associated with the message is identified. The message is sent to a messaging queue for retrieval by the second business process instance if the second business process instance is not located at the first computer node. |
| US09135594B2 |
Ambient project management
A computer-implemented method of ambient ad hoc project management can include defining a project and associating a project decay function with the project, wherein the project decay function regulates a rate at which project health declines. Responsive to detecting a project event, one or more parameters of the project decay function can be determined from the project event. Project health can be calculated according to the project decay function using the parameter(s). An indication of the project health can be output. |
| US09135593B2 |
Internal management of contact requests
Embodiments of the invention provide for systems, devices, apparatus, methods, and computer program products for allowing a first agent associated with an entity to initiate contact with a second agent associated with the entity via a contact entry point. The contact entry point is displayed on an interface page and enables a first agent to contact other agents associated with the entity in a faster, more efficient, and better informed manner. |
| US09135592B2 |
Device management system
A device management system is equipped with a storage section, a detecting component, and a calculating component and manages an installation device. The storage section stores operating rules of the installation device. The detecting component detects a violating action of the installation device running counter to the operating rules. The calculating component calculates a violating quantity that quantitatively expresses the violating action. |
| US09135589B2 |
Navigation bridge
Described herein is a system that can link multiple electronic media production and/or publication applications. The linking of the multiple applications may be facilitated through a browser. Also, a toolbar included in the browser may facilitate the links between applications and assist a user in controlling one or more workflows that use the linked applications. |
| US09135587B2 |
Methods and systems for creating business-oriented report entities
In an implementation, when creating a report, a user is provided with one or more suggestions for the report, such as a suggested grouping category, based on what has been done in one or more previous reports. |
| US09135585B2 |
Managing consistent interfaces for property library, property list template, quantity conversion virtual object, and supplier property specification business objects across heterogeneous systems
A business object model, which reflects data that is used during a given business transaction, is utilized to generate interfaces. This business object model facilitates commercial transactions by providing consistent interfaces that are suitable for use across industries, across businesses, and across different departments within a business during a business transaction. In some operations, software creates, updates, or otherwise processes information related to a property library, a property list template, a quantity conversion virtual object, and/or a supplier property specification business object. |
| US09135584B2 |
Method and apparatus to model content state and access control in backend-systems and business processes
A method to model and change the state of associated content objects from one or more workflow and task management systems is provided. The method includes overlaying a business process model associated with a graphical content state overlay. A state of the content objects changes accordingly when the business process instance proceeds. Access rights are forwarded from human tasks in a business process to an associated content object. Concurrent access rights that are forwarded from multiple systems are handled. The graphical content state overlay areas include an active state overlay to graphically indicate a business process instance is active, an assessed overlay to graphically indicate a business process instance is assessed, an approval/rejected overlay to graphically indicate a business process instance has received one of an approval decision and a rejection decision, and a state archived overlay to graphically indicate a business process instance has been archived. |
| US09135582B2 |
Power demand forecast device, method and system and power failure detection system
Disclosed herein is a power demand forecast device including: an absence detection section adapted to detect whether a consumer is absent at a given location; and a power demand forecast section adapted to forecast a power demand on a forecasted date and time in future based on an absence detection result obtained by the absence detection section. |
| US09135580B1 |
Systems and methods for parking vehicles
In one embodiment, a method includes associating a pre-existing dataset to one or more physical entities via association with an encoded token; monitoring interactions between the entity and the token; providing data from the dataset to the entity based on that monitoring; and updating the dataset with new or modified data from the entity by referencing the encoded token. In another embodiment, a method includes transmitting a vehicle retrieval request to a service provider including a delivery location; generating a listing event based on transmission of retrieval request; and transmitting a dataset back to retrieval requester. |
| US09135577B2 |
Statistical determination of power-circuit connectivity
A mechanism is provided for statistical determination of power circuit connectivity based on signal detection in a circuit. Signal data from the circuit gathered and a determination is made as to whether a signal of interest is present in the gathered signal data from the circuit using a statistical analysis of the gathered signal data. The statistical analysis comprises using a mean current value and statistical deviation of the current value of the signal data over a predetermined period of time to compute a confidence range. The confidence range is compared to a first threshold and a second threshold. A determination is made that the signal is present in response to the confidence range being above the first threshold. A determination is made that the signal is not present in response to the confidence range being below the second threshold. |
| US09135574B2 |
Contextual decision logic elicitation
Disclosed herein is a method of managing decision logic. The method includes receiving data, storing the data, and receiving a set of rules. A decision is generated based at least in part on the data and on the set of rules, and is a part of the decision logic. The decision logic is managed in a first mode or a second mode. When in the first mode or the second mode, the set of rules is managed in the context of the data by a first user. The managing includes reviewing and editing the set of rules for the decision logic in the context of the data. The editing is done by at least one of (i) modifying a rule in the set of rules, (ii) creating another rule and adding it to the set of rules and (iii) making an exception to a rule in the set of rules. |
| US09135571B2 |
Methods and apparatus for entity detection
Techniques for entity detection include matching a token from at least a portion of a text string with a matching concept in an ontology, wherein the at least a portion of the text string has been labeled as corresponding to a particular entity type. A first concept may be identified as being hierarchically related to the matching concept within the ontology, and a second concept may be identified as being hierarchically related to the first concept within the ontology. Based at least in part on the labeling of the at least a portion of the text string as corresponding to the particular entity type, a statistical model may be trained to associate the first concept with a first probability of corresponding to the particular entity type and the second concept with a second probability of corresponding to the particular entity type. |
| US09135570B2 |
Active acquisition of privileged information
A method for active learning using privileged information is disclosed. A processing device receives a set of labeled examples and a set of unlabeled examples. For each unlabeled example in the set of unlabeled examples, the processing device determines whether to query at least one of an oracle to obtain a label for the unlabeled example or a teacher to obtain privileged information about the unlabeled example. The processing device outputs a decision rule based on minimizing a number of queries to the oracle for a label and the teacher for privileged information. Minimizing the number of queries to the teacher and the oracle is based on a cost of querying the teacher or the oracle. |
| US09135566B2 |
Apparatus and method for processing sensor data in sensor network using a feature vector identifier of the sensor data
In a sensor network, a sensor data processing apparatus generates a feature vector identifier table by classifying feature vector identifiers of a plurality of situation information determination reference data to be a reference of situation determination according to a sensor type index and a feature vector identifier set index of the plurality of situation information reference data. When the sensor data processing apparatus receives sensor data, the sensor data processing apparatus generates a feature vector identifier of the sensor data and extracts a sensor type index and a feature vector identifier set index of a feature vector identifier most similar to the feature vector identifier of sensor data with reference to a feature vector identifier table, and generates situation recognition information using the extracted sensor type index and feature vector identifier set index. |
| US09135564B2 |
Using cyclic Markov decision process to determine optimum policy
A method for determining an optimum policy by using a Markov decision process in which T subspaces each have at least one state having a cyclic structure includes identifying, with a processor, subspaces that are part of a state space; selecting a t-th (t is a natural number, t≦T) subspace among the identified subspaces; computing a probability of, and an expected value of a cost of, reaching from one or more states in the selected t-th subspace to one or more states in the t-th subspace in a following cycle; and recursively computing a value and an expected value of a cost based on the computed probability and expected value of the cost, in a sequential manner starting from a (t−1)-th subspace. |
| US09135560B1 |
Automatic parser selection and usage
The automatic selection and usage of a parser is disclosed. Raw data is received from a first remote device. At least a portion of the raw data is evaluated using a plurality of rules. A confidence measure is determined for at least some of the rules. An indication that the raw data pertains to a source is provided as output when the confidence measure exceeds a threshold. |
| US09135559B1 |
Methods and systems for predictive engine evaluation, tuning, and replay of engine performance
Disclosed are methods and systems of creating, evaluating, and tuning a predictive engine for machine learning, including steps to deploy the predictive engine with an initial parameter set; receive queries to the deployed engine variant and in response, generate predicted results; receive corresponding actual results; associate the queries, the predicted results, and the actual results with a replay tag; evaluate the performance of the deployed engine variant; generate a new engine parameter set based on tuning of one or more parameters of the initial engine parameter set, according to the evaluation results; deploy the new engine variant to replace the initial engine variant; receive a replay request from an operator specifying the currently or a previously deployed engine variant; and in response to the replay request, replay at least one of the queries, the corresponding predicted results, the actual results, and the evaluation results. |
| US09135555B2 |
Enhanced predictive input utilizing a typeahead process
Particular embodiments may retrieve information associated with one or more nodes of a social graph from one or more data stores. A node may comprise a user node or a concept node. Each node may be connected by edges to other nodes of a social graph. A first user may be associated with a first user node of the social graph. Particular embodiments may detect that the first user is entering an input term. Predictive typeahead results may be provided as the first user enters the input term. The predictive typeahead results may be based on the input term. Each predictive typeahead result may include at least one image. Each predictive typeahead result may correspond to at least one node of the social graph. |
| US09135551B2 |
Inductive antenna coupling
This invention pertains to the connection between a radio frequency circuit and its antenna. Miniaturization of radio frequency integrated circuits has made attaching these circuits to their antennas increasingly difficult and costly. This invention uses magnetic coupling, as performed in transformers, between circuits and antennas as a practical solution to reduce cost and effort in attaching the two sides as well as to protect the circuit against electrostatic discharge. Furthermore a simple pre-assembly testing methodology is accounted for as an additional benefit of the method. |
| US09135545B1 |
Magnetic stripe emulator for persistently emulating magnetic stripe data
A proxy card for persistently emulating a set of magnetic stripe data associated with a payment card is disclosed. The proxy card provides a magnetic stripe emulator that includes a plurality of parallel traces of conductive material oriented in a direction perpendicular to a direction in which the proxy payment card is designed to be swiped. The parallel traces are coated with a layer of a magnetic medium of low coercivity. A microcontroller on the proxy card generates electrical signals to drive electrical current along each of the plurality of parallel traces in a selected direction. The electrical current causes alignment of particles in the magnetic medium of the magnetic stripe emulator which encodes the set of magnetic stripe data on the magnetic stripe emulator. The proxy card can then emulate the payment card when swiped through a magnetic card reader without consuming any power. |
| US09135541B2 |
Image forming apparatus and nonvolatile memory writing method
Provided is an image forming apparatus, including a nonvolatile memory writing unit configured to write into the nonvolatile memory, at every predetermined time period in which change data is written into the volatile memory within that predetermined time period, the change data written into the volatile memory, a temporary area writing unit configured to write new change data into a temporary area while a primary area writing unit is writing any change data into the primary area, and a primary area transfer unit configured to transfer any change data written into the temporary area by the temporary area writing unit to the primary area when the primary area writing unit completes writing the change data into the primary area. |
| US09135540B2 |
Image processing apparatus, image processing method, and program for processing black characters at high resolution
An image processing apparatus includes an acquiring unit configured to acquire first image data representing gradation of a black character image, and second image data having a resolution lower than that of the first image data and representing gradation of a color image; a first generating unit configured to generate first dot data in accordance with a gradation value of each pixel in the first image data acquired by the acquiring unit; and a second generating unit configured to assign a number of dots to each pixel in the second image data, the number being greater than the maximum number of dots to be assigned by the first generating unit to each pixel in the first image data, and generating dot data for forming an image having an image attribute, in accordance with a gradation value of each pixel in the second image data acquired by the acquiring unit. |
| US09135539B1 |
Barcode printing based on printing data content
A method and system is provided for printing a barcode computed based on content of a printed page data system on a document, the method comprising: using a methodology of regular expression; applying a regular expression subsystem to text contained in a print stream generating data; converting the data to a barcode applying barcode computation, to produce a bitmap barcode representing the barcode; inserting the bitmap barcode into an Enhanced Meta File (EMF) print stream defined by the printing system in the Port Monitor or Print Processor subsystem; inserting the bitmap barcode into an XML Paper Specification (or XPS) print stream defined by the printing system in the Port Monitor or Print Processor subsystem; and combining the barcode with the print stream to contain the barcode in a specific position in the print stream in the Port Monitor or Print Processor subsystem. |
| US09135537B2 |
Information processing apparatus, information processing method, and medium
An object of the present invention is to provide an information processing apparatus capable of skipping printing of an appropriate margin area based on information on a header or footer at the time of performing printing. In the present invention, header/footer information including at least one of header information and footer information for a document, which is set to an application that creates the document, is acquired, and based on the acquired header/footer information, a margin area of the document is calculated. Then, a setting is performed to a printer driver capable of giving a printing apparatus instructions to perform printing by skipping printing of a margin area so that the printing apparatus skips printing of the margin area calculated in the calculation step. |
| US09135536B2 |
Image processing apparatus and image processing method generating binary data specifying dot arrangement in a unit area of a print medium
Even in the case where input image data is binary data, dot arrangement appropriate for a printing apparatus is achieved to output a high quality image that suppresses an adverse influence such as density unevenness, stripes, or granular feeling. For this purpose, after the inputted binary data has been converted to multivalued data having lower resolution, a dot arrangement pattern that preliminarily specifies printing or non-printing for each of print pixels is set with being related to the multivalued data, and thereby new binary data is generated. At this time, the dot arrangement pattern is set to the dot arrangement appropriate for the printing apparatus, and therefore the high quality image that suppresses the adverse influence such as the density unevenness, stripes, or granular feeling can be outputted. |
| US09135530B2 |
Printer position determination and selection for a terminal apparatus and system
A terminal apparatus includes: a first position receiving unit configured to receive terminal position information indicating a position of the terminal apparatus; a receiving unit configured to receive a plurality of distance information corresponding to each of printers that are printer candidates to execute a printing, wherein each of the plurality of distance information is generated on the basis of coordinate information, which includes information of a latitude and a longitude indicating a position of the corresponding printer, and the terminal position information; a choosing unit configured to preferentially choose a printer having a short distance to the terminal apparatus from the printers based on the distance information; and a printing instruction unit configured to transmit a printing instruction for printing execution to a specific printer of the one or more chose printers. |
| US09135529B2 |
Terminal apparatus configured to perform wireless communication with a printing apparatus for executing printing processing based on a printing job
A non-transitory computer-readable medium has a computer program stored thereon and readable by a computer of a terminal apparatus configured to perform wireless communication with a printer. The computer program, when executed by the computer, causes the computer to perform operations including: a position registration process of registering information, which indicates a first position for acquiring related information, with a storage unit in the terminal apparatus; a terminal position acquisition process of acquiring terminal position information indicative of a position of the terminal apparatus; an information acquisition process of acquiring the related information corresponding to a current status of the printer in a case where the position of the terminal apparatus is within a specific range that is defined on the basis of the first position; and an output process of outputting the acquired related information. |
| US09135528B2 |
Information processing apparatus, job processing method in information processing apparatus, and storage medium
A user inputs information, such as a user identification (ID), on a printer by using an operation unit included in the printer. The printer inputs a print request for printing an intermediate print job corresponding to the user ID to the printer driver of an application server. When the request is received from the printer, a print request receiving function of the printer driver starts a series of print processing. The printer driver extracts an intermediate print job corresponding to a target user ID stored on a print job storage memory. A print setting final determination function finally determines print setting information to the extracted intermediate print job. |
| US09135527B2 |
Ejecting device for storage card
An ejecting device includes a housing for allowing insertion of a storage card, an engaging member, a processor, a ejecting member, an electromagnet, a switch button, and an spring member. The ejecting member is received and movable in the housing. The engaging member is configured to engage in the ejecting member or disengage from the ejecting member. The switch button is configured to generate an ejection signal. The processor is configured to execute a program to save data in the storage card in response to the ejection signal and control the electromagnet to pull the engaging member out of the ejecting member after the execution of the program is finished. The spring member is configured to push the ejecting member and the storage card out of the housing. |
| US09135526B2 |
Method for extracting information of interest from multi-dimensional, multi-parametric and/or multi-temporal datasets
Method of extraction of information of interest to multi-dimensional, multi-parametric and/or multi-temporal datasets related to a same object under observation through data fusion, in which a plurality of different data sets are provided concerning a single object, with the data related to various parameters and/or different time acquisition instants of said parameters. The data set are subjected to a first processing step by principal component analysis generated by an identical number of datasets with transformed data; and each of the datasets is combined in non-linearly with the corresponding transformed data set to obtain a certain predetermined number of combinations of parameters by weighing using parameters determined empirically using training datasets which determine the values of the non-linear weighting parameters that maximize the value of the new features associated with the data of interest, as compared to those of other data. |
| US09135520B2 |
Histogram methods and systems for object recognition
A multidimensional histogram is used to characterize an image (or object), and is used to identify candidate matches with one or more reference images (or objects). An exemplary implementation employs hue information for two of the dimensions, and a second derivative function based on luminance for a third dimension. The simplicity and speed of the detailed arrangements make them well suited for use with cell phones and other mobile devices, which can use the technology for image/object recognition, e.g., in visual search applications. |
| US09135517B1 |
Image based document identification based on obtained and stored document characteristics
A method and apparatus for identifying a document in a set of stored documents based on a pattern of characteristics in the document is presented. A digital image including at least a portion of the a document is acquired. A pattern of characteristics is then identified in the digital image. The pattern is matched to the set of stored documents to identify the document in the digital image from the set of stored documents. |
| US09135514B2 |
Real time tracking/detection of multiple targets
A mobile platform detects and tracks at least one target in real-time, by tracking at least one target, and creating an occlusion mask indicating an area in a current image to detect a new target. The mobile platform searches the area of the current image indicated by the occlusion mask to detect the new target. The use of a mask to instruct the detection system where to look for new targets increases the speed of the detection task. Additionally, to achieve real-time operation, the detection and tracking is performed in the limited time budget of the (inter) frame duration. Tracking targets is given higher priority than detecting new targets. After tracking is completed, detection is performed in the remaining time budget for the frame duration. Detection for one frame, thus, may be performed over multiple frames. |
| US09135511B2 |
Three-dimensional object detection device
A three-dimensional object detection device includes an image capturing unit, an image conversion unit, a three-dimensional object detection unit, a light source detection unit a degree-of-certainty assessment unit and a control unit. The degree-of-certainty assessment unit assesses a degree of certainty that a light source is headlights of another vehicle in two lanes over. The control unit sets a threshold value so that the three-dimensional object is more difficult to detect in a forward area of a line connecting the light source and the image capturing unit in the detection frame when the degree of certainty is at a predetermined value or higher, and sets a threshold value so that the three-dimensional object is more difficult to detect in progression from a center side toward front or rear ends of the detection frame when the degree of certainty is less than a predetermined value. |
| US09135507B2 |
Method for searching a roof facet and constructing a building roof structure line
A method for searching a building roof facet and reconstructing a roof structure line, in which the searching is performed automatically and without limitation of how slope of the roof facet, and the building structure line is constructed through aerial imagery. At first, lidar point clouds on the roof are extracted to compose a roof facet by using coplanarity analysis, and the roof is differentiated to a possible flat roof and a pitched roof. An optimal roof facet is obtained by analyzing lidar point clouds to overcome the low pitched facet issue. A relationship of a roof facet on a 2-dimensional space is analyzed to ascertain an area of a roof structure line. An initial boundary is generated. Line detection is performed on the images and a roof structure line segment is composed. All the structure line segments are used to reconstructing a 3-dimensional building pattern in object space. |
| US09135506B2 |
Method and apparatus for object detection
A method for detecting a plurality of object regions in an image, wherein the plurality of object regions having similar specific structural features, comprises: an estimation step for estimating a common initial value for the specific structural features of the plurality of object regions; and a determination step for determining, for each of the plurality of object regions, a final value for the specific structural feature of the object region and a final position thereof separately based on the estimated common initial value. |
| US09135502B2 |
Method for the real-time-capable, computer-assisted analysis of an image sequence containing a variable pose
The invention relates to a method for the real-time-capable, computer-assisted analysis of an image sequence of an object consisting of elements that can be moved relative to each other and are interconnected, said sequence containing a variable pose, wherein the individual images of the image sequence are recorded by way of a time-of-flight (TOF) camera such that said images can be processed by a computer, and contain brightness and distance data as functions of the pixel coordinates of the camera for each image of the sequence, comprising the following steps: a. Capturing the pixels of an individual image forming the object, b. calculating a three-dimensional (3D) point cloud in a virtual space, said point cloud representing the surface of the object that is visible to the camera, by a computational projection of object-depicting pixels in such a space, while taking captured distance data to the object into consideration, c. fitting a model of the object consisting of nodes and edges into the computer-generated 3D point cloud for the individual images, wherein the nodes represent a selection of elements of the object and the edges represent the connections of said elements amount each other, d. iteratively updating all node positions by applying a learning rule for training a self-organizing map having a previously defined number of randomly selected dots of the point cloud, e. repeating steps a. to d. for each subsequent individual image of the sequence, wherein for the fitting in step c. the result of step e. of the preceding image is used in each case, and f. determining the varying pose from the positions of predetermined nodes of the model which have been captured in at least representative images of the image sequence. |
| US09135500B2 |
Facial recognition
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing facial recognition. In one aspect, a method includes accessing a first digital photograph. A first face template is generated for each face detected in the first digital photograph. Second user identifiers that are associated with a first user identifier are determined. A digital photograph index of photographs, user identifiers, and areas in the digital photographs in which a face of a user identified by user identifier is located is accessed. Second user identifiers are selected, and second face templates are generated from the faces of the user the digital photographs. First face templates that match second face templates are identified, and for each first face template that matches a second face template, data is generated specifying the area in the first digital photograph in which the face of the second user is located. |
| US09135497B2 |
Identifying randomly distributed microparticles in images to sequence a polynucleotide
Performing sequencing of a polynucleotide. A first image of microparticles that are distributed in a random fashion on a substrate may be received. Each of the microparticles may include a plurality of similar oligonucleotides of the polynucleotide. A second image of the microparticles may be received. A plurality of first subportions of the first image may be determined. Each subportion may include a respective plurality of microparticles distributed in a random fashion. The second image may be analyzed to identify a plurality of second subportions in the second image. Each of the plurality of second subportions may correspond to a respective one of the plurality of first subportions. A plurality of the microparticles may be matched from the first and second images based on said analyzing. At least a portion of the sequence of nucleotides of the polynucleotide may be determined based on said matching. |
| US09135492B2 |
Image based dial gauge reading
A system and method include obtaining an image of an analog dial gauge. The image is processed to identify an endpoint of the gauge and a needle position in the image. A reading of the gauge is determined from the endpoint, the needle position, and information regarding the range of the gauge. |
| US09135491B2 |
Digital point-of-sale analyzer
A digital point-of-sale system for determining key performance indicators (KPIs) at a point-of-sale includes a product identification unit and a realogram creation unit. The product identification unit is configured to receive a captured image of a product display and to identify products in the captured image by comparing features determined from the captured image to features determined from products templates. The realogram creation unit is configured to create a realogram from the identified products and product templates. A product price KPI unit is configured to identify a product label proximally located to each identified product, and to recognize the product price on each product label. Each product price is compared to a predetermined range of prices to determine whether the product label proximally located to the identified product is a correct product label for the identified product. |
| US09135487B2 |
Sample information detection apparatus and sample information detection method
According to an embodiment, a sample information detection apparatus includes, a reflection unit includes a reflection mirror configured to reflect an image of a sample container configured to contain a sample, an image acquisition unit includes an imaging unit configured to image an imaging range covering images reflected by the reflection mirror, the image acquisition unit being configured to acquire the image of the sample container that is reflected by the reflection mirror, and a sample information detection unit configured to detect information displayed on a side portion of the sample container based on the acquired image. |
| US09135484B2 |
Data reader with light source arrangement for improved illumination
Light sources are contained in a data reader housing that also contains an imager. In one embodiment, one light source includes a number of LEDs placed in a number of hollow reflectors located toward the rear of a data scanner, where the hollow reflectors have substantially flat reflective surfaces to project light through a window and into a read volume. Other embodiments include additional light sources located proximate sidewalls of the data scanner and also include a number of LEDs placed in hollow reflectors to project light through the window and into the read volume. In other embodiments, additional LEDs are included outside the hollow reflectors to project light through the window and into a different portion of the read volume than the LEDs located in the hollow reflectors. |
| US09135483B2 |
Terminal having image data format conversion
There is set forth herein an indicia reading terminal having data format conversion capabilities. The indicia reading terminal includes an image sensor integrated circuit with an image sensor array comprising a plurality of pixels. The image sensor integrated circuit is configured to output image data in a first data format to a data formatting circuit for conversion to image data in a second data format. The data formatting circuit is configured to provide the image data in the second data format to the at least one data interface of a microprocessor integrated circuit, which is operative to transfer image data received by the at least one data interface into memory of the indicia reading terminal. A CPU of the microprocessor integrated circuit is operative for executing a decoding algorithm for processing image data in the memory for attempting to decode at least one symbol represented in the memory. |
| US09135482B2 |
Mobile dispensing system for medical articles
A mobile dispensing cart having a plurality of locked drawers has medical articles stored therein for particular patients. The storage drawers have sizes wherein the resonant frequency of the sizes does not match the frequency of operation of the RFID system of the cart. Faraday cages and enclosures are used in the storage areas that provide robust RFID fields for exciting and reading RFID tags. An HCP for a particular patient obtains access to the drawers and opens a drawer. An RFID scanning system takes an inventory of the cart after the drawer is closed to determine if any medical article was taken, and if so which one. The identified taken article is compared to the data base of medical articles stored in the cart for the patient and if the taken article does not match the patient data base, an alarm is provided. |
| US09135479B2 |
Antenna assembly for a tag reader
An antenna assembly includes a stand having a convex outer surface positioned to intercept and engage a vehicle tire as the vehicle tire passes over the convex stand surface. The height and contour of the convex stand surface slows the rotational rate of the vehicle tire, and thereby a transmitting device carried by the tire, to a preferred rotational read rate as the vehicle tire passes over the convex surface. One or more antenna members mount to the stand proximal to the convex surface, each antenna having a directionally aimed tilted antenna field positioned to continuously receive data transmission from the electronic transmitting device as the vehicle tire passes over the convex stand surface at the reduced rotational read rate. |
| US09135474B2 |
PCB mounted cover activated intrusion detection switch
An intrusion detection switch is attached directly to a printed circuit board and utilized within an enclosure. Wires are not used to extend the switch to the top of the enclosure. An extension mechanism is used to extend a triggering portion of the intrusion detection switch to an engaging surface at the top of the enclosure. When the enclosure lid is properly shut, the engaging service is directed downward, thereby pushing an activation switch of the intrusion detection switch down. Switches may be assembled to an internal main printed circuit board where the switch is completely protected. Therefore, routing and maintaining of wiring to a switch is eliminated. A linkage system or mechanism can be mounted to the main chassis of the enclosure and act as an interface to an enclosure top cover. This eliminates potential damage to switches and wires and provides for a more reliable switch. |
| US09135471B2 |
System and method for encryption and decryption of data
Systems and methods for reducing problems and disadvantages associated with traditional approaches to encryption and decryption of data are provided. A method for encryption and decryption of data, may include encrypting or decrypting data associated with an input/output operation based on at least one of an encryption key and a cryptographic function, wherein at least one of the encryption key and the cryptographic function are selected based on one or more characteristics associated with the data to be encrypted or decrypted. Another method may include encrypting an item of data based on at least one of a first-layer encryption key and a first-layer cryptographic function to produce first-layer encrypted data and encrypting the first-layer encrypted data based on at least one of a second-layer encryption key and a second-layer cryptographic function to produce second-layer encrypted data. |
| US09135463B2 |
Storage device, method for accessing storage device, and storage medium storing program for accessing storage device
A storage device that stores data accessed by a host device via an interface includes a deactivation executing part performing a plurality of deactivating processes deactivating access to the data at different levels via the interface; a setting information storing part storing setting information which includes deactivation identifying information identifying the deactivating process and a condition under which the deactivating process is performed; a judging part referring to the setting information stored on the setting information storing part, comparing the condition represented by the setting information with an operation state of the storage device, and judging whether the condition represented by the setting information is satisfied or not; and a deactivation control part ordering the deactivation executing part to execute one of the plurality of deactivating processes identified with the deactivation identifying information represented by the setting information when the judging part has judged that the condition is satisfied. |
| US09135462B2 |
Upload and download streaming encryption to/from a cloud-based platform
Embodiments of the present disclosure include systems and methods for upload and/or download streaming encryption to/from an online service, or cloud-based platform or environment. The encryption process includes the following parts: Upload encryption, download decryption, and a central piece of infrastructure called the Interval Key Server (IKS). During both upload and download, the encryption and decryption processes are performed while the files are being uploaded/downloaded, (e.g., the files are being encrypted/decrypted as they are being streamed). |
| US09135461B1 |
Heterogeneous virtual machines sharing a security model
Methods and systems for sharing a security model with heterogeneous virtual machines (VMs) are provided. A method for sharing a security model with heterogeneous VMs may include making a direct function call to an object model from each of two or more heterogeneous VMs using a direct binding generated for the respective VM based on the respective VM and a security policy. The direct bindings of the two or more heterogeneous VMs share the security policy. The method may also include ensuring only one of the two or more heterogeneous VMs interacts with the object model at a time. A system for sharing a security model with heterogeneous VMs may include a heterogeneous VM manager and a heterogeneous VM scheduler. The system may further include a principal tracker and a proxy component. |
| US09135460B2 |
Techniques to store secret information for global data centers
Techniques to store secret information for global data centers securely may provide a front end service for a back end data store. The front end service may be responsible for deployment, upgrade, and disaster recovery aspects, and so forth, of data center maintenance. Data centers may access data and data-related services from the back end data store through the front end service. Secrets that are needed to access secure data may be stored on behalf of the data centers without providing the secrets to the data centers. |
| US09135459B2 |
Security management unit, host controller interface including same, method operating host controller interface, and devices including host controller interface
A method of operating a host controller interface includes receiving a buffer descriptor including sector information from a main memory, fetching data by using a source address included in the buffer descriptor, selecting one of a plurality of entries included in a security policy table by using the sector information, and determining whether to encrypt the fetched data by using a security policy included in the selected entry. |
| US09135456B2 |
Secure data parser method and system
A secure data parser is provided that may be integrated into any suitable system for securely storing and communicating data. The secure data parser parses data and then splits the data into multiple portions that are stored or communicated distinctly. Encryption of the original data, the portions of data, or both may be employed for additional security. The secure data parser may be used to protect data in motion by splitting original data into portions of data, that may be communicated using multiple communications paths. |
| US09135454B2 |
Systems and methods for enabling searchable encryption
A system and method for enabling searchable encryption of encrypted documents stored by a client on one or more storage providers includes a broker server in communication with the client and the one or more storage providers. The broker server is adapted to transfer the encrypted documents between the client and the one or more storage providers and to maintain information indicating where the encrypted documents are transferred. The broker server further stores information for at least one encrypted index for the encrypted documents and a test function for a searchable encryption mechanism used to encrypt the at least one encrypted index. |
| US09135452B2 |
Method and system for anonymization in continuous location-based services
In some embodiments, a computer-implemented method includes receiving a first location-based service (LBS) request from a requesting device. One or more peer devices are selected from a plurality of actual peer devices. A set of false queries is generated, by a computer processor, based on the selected peer devices. Transmitted to a service provider are a real query, representing the first LBS request of the requesting device, and the set of false queries representing the selected peer devices. A set of query responses are received from the service provider. From the set of query responses, a real query response is extracted, corresponding to the real query. The real query response is transmitted to the requesting device in reply to the first LBS request. |
| US09135451B2 |
Data isolation in shared resource environments
A data connection of a shared resource is placed in isolation mode to remove its ability to communicate with other data connections of the shared resource. This ability to isolate the data connection is dynamic in that it can be turned on/off at any time. This provides increased data security for the entities using the data connection. |
| US09135445B2 |
Providing information about a web application or extension offered by website based on information about the application or extension gathered from a trusted site
A method for installing an offered web application or browser extension in a web browser includes receiving a user action on a website located at a first internet domain. Information about the offered web application or browser extension not currently installed in the web browser is displayed in response to the user action. The displayed information is provided by a digital marketplace located at a second internet domain distinct from the first internet domain. A correspondence of the displayed information to the offered web application or browser extension is ensured through functionality provided by the web browser. An indication to install the offered web application or browser extension is received from a user, and the web application or browser extension is installed in response to the received indication. |
| US09135441B2 |
Progressive static security analysis
A disclosed method includes determining modifications have been made to a program and deriving data flow seeds that are affected by the modifications. The method includes selecting one of the data flow seeds that are affected by the modifications or data flow seeds that are not affected by the modifications but that are part of flows that are affected by the modifications and performing a security analysis on the program. The security analysis includes tracking flows emanating from the selected data flow seeds to sinks terminating the flows. The method includes outputting results of the security analysis. The results comprise one or more indications of security status for one or more of the flows emanating from the selected data flow seeds. At least the deriving, selecting, and performing are performed using a static analysis of the program. Apparatus and program products are also disclosed. |
| US09135438B2 |
Systems and methods for correlating and distributing intrusion alert information among collaborating computer systems
Systems and methods for correlating and distributing intrusion alert information among collaborating computer systems are provided. These systems and methods provide an alert correlator and an alert distributor that enable early signs of an attack to be detected and rapidly disseminated to collaborating systems. The alert correlator utilizes data structures to correlate alert detections and provide a mechanism through which threat information can be revealed to other collaborating systems. The alert distributor uses an efficient technique to group collaborating systems and then pass data between certain members of those groups according to a schedule. In this way data can be routinely distributed without generating excess traffic loads. |
| US09135437B1 |
Hypervisor enforcement of cryptographic policy
Techniques for restricting the execution of algorithms contained in applications executing on virtual machines executing within a computer system are described herein. A first sampled set of computer executable instructions is gathered from a virtual machine by a controlling domain and compared against a reference set of computer executable instructions. If the first set is similar to the reference set, and if the execution of the algorithm corresponding to the reference set is restricted by one or more computer system polices, one or more operations limiting the execution of the restricted algorithm are performed, thus ensuring conformance with the computer system policies. |
| US09135436B2 |
Execution stack securing process
An approach to securing an execution stack (or cloud architecture) is provided. For example, an image is separated into a plurality of layers to form a trusted execution stack. Each of the plurality of layers is hardened to secure key cloud components of the trusted execution stack. |
| US09135435B2 |
Binary translator driven program state relocation
This disclosure is directed to binary translator driven program state relocation. In general, a device may protect vulnerable program functions by setting them as non-executable. If an attempt is made to execute a protected program function, the program may trap to a binary translator in the device that may be configured to relocate program state from what has already been established (e.g., on a stack register). Program state may include resources (e.g., memory locations) used by the program during the course of execution. The binary translator may then translate the program into an executable form based on the relocated program state, and may be executed accordingly. Intruding code that attempts to overcome normal program execution and implement hostile operations (e.g., based the program state that is reflected in the stack register) will not function as intended since the relocated program state will cause unexpected results. |
| US09135434B2 |
System and method for third party creation of applications for mobile appliances
The creation of an application for any mobile appliance, for example Apple's iPhone, requires several elements to be present at compile time. In the Apple example of an enterprise application where an entity wishes to develop applications internally for its staff, two of these elements are the source code and a digital certificate. These must be combined in the compiler so that the application may be properly authorized to run in the appliance. Where the owner of the source code and the owner of the digital certificate are not the same, serious concerns arise because each element must be secured. An intermediating system and method are described that allows each party to cooperate securely through a third party escrow service to produce the complied application while leaving no unwanted residue of the independent parts. |
| US09135431B2 |
Harmonic detector of critical path monitors
A system for monitoring a clock input signal including a reference clock to be monitored, a flip-flop, a plurality of delay logic blocks, a sampling unit, and a comparison unit. The reference clock may have an expected maximum frequency. The flip-flop may be configured to generate a corresponding clock signal at a reduced frequency compared to the reference clock. The plurality of delay logic blocks may be configured to receive the reduced frequency clock signal and delay the signal for various amounts of time, each less than an expected period of the reference clock. The sampling unit may be configured to sample the signals output from the plurality of delay logic blocks. The comparison unit may be configured to receive the outputs of the flip-flop and the sampling unit and use these outputs to determine if the reference clock is running at an acceptable frequency compared to the expected frequency. |
| US09135429B2 |
Mobile device for authenticating a device accessory
A mobile device for authenticating a device accessory is disclosed. The mobile device receives a unique identifier from a device accessory, sends the received unique identifier to a server via a communication network, and receives information from the server relating to the unique identifier. |
| US09135428B2 |
Cross system secure logon
A cross system secure logon in a target system by using a first authentication system and a second authentication system. A correct password may be valid on the first authentication system and the second authentication system. An aspect includes receiving an input password, generating a first hash key by using the first authentication system, and/or generating a second hash key by using the second authentication system, wherein each authentication system uses a system unique non-collision free hash algorithm. Further, in one aspect, comparing the first hash key with a first predefined hash key of the correct password stored in the first authentication system, and/or comparing the second hash key with a second predefined hash key of the correct password stored in the second authentication system. Furthermore, granting access to the target system based on at least one of the comparisons. |
| US09135427B2 |
Authentication using a subset of a user-known code sequence
Authentication in a system includes presenting information to a user containing a partial sequence of a passcode along with distractors. The user is challenged to identify the partial sequence from among the information in order to gain access to the system. |
| US09135420B2 |
Biometric data-driven application of vehicle operation settings
Biometric data-driven application of vehicle operations is implemented by a scanner, a computer processor communicatively coupled to the scanner over a vehicle network, and logic executable by the computer processor. The logic receives, from the scanner over the vehicle network, biometric data for an operator of a vehicle and compares the biometric data from the scanner to sets of biometric data stored in a memory device of the vehicle. Upon determining that the biometric data from the scanner matches one of the sets of biometric data stored in the memory device, the logic retrieves operational settings configured for the operator and implements at least one action to achieve a result defined by the operational settings. |
| US09135416B2 |
GUI-based authentication for a computing system
Machines, systems and methods for providing an authentication challenge are provided. The method comprises analyzing data stored in a computing system equipped with a graphical user interface (GUI), wherein the data stored is related to identity and relationships among items that have a profile; and based on the analysis, issuing a challenge to authenticate access to one or more content or services available by way of the computing system, in response to a user interaction with the computing system, wherein the response to the challenge is known to a user who has personal knowledge of the identity and relationships among the items with a profile, and wherein the user successfully authenticates against the challenge by interacting with visual presentations of the items by placing the items in an order that indicates a correct relationship between at least two or more of the items. |
| US09135412B1 |
Token-based security for remote resources
Systems and methods of token-based protection for remote resources are disclosed. For example, a method may include receiving, at a second computing device, a configuration message from a first computing device. The configuration message includes information to configure a resource at the second computing device. For example, the resource may be a cloud transcoder. The method also includes generating, at the second computing device, a short token that enables the first computing device to access the resource. For example, the short token may be used to receive a long token that can be used to send application programming interface (API) requests to the cloud transcoder. |
| US09135407B2 |
License management apparatus, license management method, and storage medium
A license management apparatus transfers license information from a transfer source device to a transfer destination device. The license information is required for enabling functions of a program package serving as an integrated product including a plurality of functions. The license management apparatus includes a management unit and a transfer unit. The management unit manages all or part of the plurality of functions as belonging to one group. After license information of functions included in the program package and managed by the management unit as belonging to the same group is acquired from the transfer source device, the transfer unit transfers license information of functions managed as belonging to the same group to the transfer destination device. |
| US09135402B2 |
Systems and methods for processing sensor data
Systems and methods for processing sensor data are provided. In some embodiments, systems and methods are provided for calibration of a continuous analyte sensor. In some embodiments, systems and methods are provided for classification of a level of noise on a sensor signal. In some embodiments, systems and methods are provided for determining a rate of change for analyte concentration based on a continuous sensor signal. In some embodiments, systems and methods for alerting or alarming a patient based on prediction of glucose concentration are provided. |