Digital master clock |
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| 申请号 | US3681914D | 申请日 | 1970-04-30 | 公开(公告)号 | US3681914A | 公开(公告)日 | 1972-08-08 |
| 申请人 | QUASAR MICROSYSTEMS INC; | 发明人 | LOEWENGART HARRY R; | ||||
| 摘要 | A master clock source develops clock signals for transmission to a plurality of receiving or ''''slave'''' terminals. The clock signals are periodically scanned and transferred to the slave terminals once each second, thereby to continuously up-date the clock indication at the receiving terminals. | ||||||
| 权利要求 | 1. A master-slave clock system in which a master terminal transmits clock signals to at least one remote slave terminal coupled to said master terminal, said remote terminal including means for indicating the time in terms of a first least significant time unit periodically varying at a first rate, said system comprising means in said master terminal for developing timing signals in terms of a second least significant time unit varying at a second rate greater than said first rate, and means for periodically transmitting to said remote terminal a time signal correct to said first least significant unit at said second rate. 2. The system of claim 1, in which said first least significant time unit is a minute, and said second least significant time unit is a second, said circuit comprising means for enabling said transmitting means a predetermined period during each minute. 3. The system of claim 1, further comprising means for enabling said transmitting means a predetermined period during each of said first least significant time units. 4. The system of claim 3, in which said timing signal developing means comprises means for producing a multi-bit signal defining said time signal each of said first least significant time units, aNd said transmitting means comprises means for sequentially sending one bit of said multi-bit signal to said remote terminal each of said second least significant time units during said predetermined period. 5. The system of claim 4, in which said first least significant time unit is a minute, and said second least significant time unit is a second. 6. The system of claim 3, further comprising switch means having an input receiving said timing signals and an output coupled to said transmitting means, and control means for enabling said switch means only during said predetermined period. 7. The system of claim 6, in which said control means comprises counter means, and further comprising a source of counting signals, means for enabling counting of said counting signals at said counter means at a predetermined portion of each signal transferring period, and means for thereafter disabling counting after said counter means has counted a predetermined number of said counting signals, the period between said counting enabling and disabling defining said predetermined period. 8. A circuit for supplying clock signals to at least one remote terminal, said circuit comprising means for producing timing signals, switching means having an output, an input coupled to said timing signal producing means, and a control terminal, output means coupled to the output of said switching means and to said remote terminal, and control means coupled to said timing signal producing a series of means and to the control terminal of said switching means for periodically transferring timing signals from said switching means to said output means at a rate greater than that at which the least significant time unit of said transferred clock signal varies. 9. The circuit source of claim 8, further comprising means for periodically enabling said control means during a predetermined period of each timing signal transferring period. 10. The circuit of claim 9, in which said timing signals at the input of said switching means is in the form of a parallel multi-bit word, said control means comprising means for sequentially transferring succeeding ones of said bits to said output means at said greater rate during said predetermined period. 11. The circuit of claim 8, in which said control means comprises counter means, and further comprising a source of counting signals, means for initiating counting of said counting signals at said counter means at a predetermined portion of each signal transferring period, and means for thereafter disabling counting after said counter means has counted a predetermined number of said counting signals, the period between said counting enabling and disabling defining said predetermined period. 12. The system of claim 1, for use in a data processing system having a central data processing unit and at least one remote unit connected to said central data processing unit, in which said master terminal is positioned in and forms part of said central data processing unit, and wherein said remote slave terminal is positioned in and forms part of said one remote unit, said master-slave system including means for synchronizing said central data processing unit and said remote unit to continuously indicate the same time. |
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