Compared count digitally controlled pacemaker
阅读：300发布：2023-05-19
专利汇可以提供Compared count digitally controlled pacemaker专利检索，专利查询，专利分析的服务。并且A cardiac pacer having adjustable rate and/or pulse width controls controlled by digital means including a first counter for receiving information and storing the data, a second counter connected to clock means, and logic means for comparing the outputs of the first and second counters to determine pulse rate and width. The preferred embodiments of the digitally controlled pacer include means connected to the first counter for receiving coded set signals and rejecting noise and other interference signals. The preferred embodiment of a transmitter for sending coded signals to the pacer is also shown, the transmitter being digitally operable to provide coded bursts of RF pulses to the pacer receiver.，下面是Compared count digitally controlled pacemaker专利的具体信息内容。
1. Electro-medical stimulation apparatus comprising: first and second binary data storage means; means for selectively changing data stored in the first storage means; means for continually changing data stored in the second storage means at a predetermined rate; means for comparing at least portions of data stored in the first and second storage means and for providing signals in the presence of a predetermined comparisons; and means connected to receive the signals from the means for comparing for providing stimulation signals.
2. The apparatus of claim 1 including: means connected to the first storage means for controlling the width of the stimulation signals according to at least a portion of the data stored in the first storage means.
3. The apparatus of claim 1 including: means connected to the first storage means for controlling the amplitude of the stimulation signals according to at least a portion of the data stored in the first storage means.
4. The apparatus of claim 1 in which the means for selectively changing the data stored in the first storage means includes: receiver and decoder means connected to the first storage means.
5. The apparatus of claim 4 including the combination: transmitter and encoder means for transmitting coded signals to the receiver and decoder means.
6. The apparatus of claim 1 including: further means for comparing at least other portions of data stored in the first and second storage means and for providing a signal in the presence of a predetermined comparison; means connecting the further means for comparing to the means for providing a stimulation signal; and the means for providing a stimulation signal having means responsive to a signal from the means for comparing for starting a stimulation signal, and having meaNs responsive to a signal from the further means for comparing for stopping the stimulation signal.
7. Apparatus for providing electro-medical stimulation pulses comprising: clock means having a pulsed output signal; first counter means connected to count the output of the clock means; further counter means for receiving and storing a predetermined count; comparison logic means for continually comparing the counts in the first and further counter means to provide a polarity of signals; and stimulation circuit means controlled by the plurality signals for providing stimulation signals.
8. The apparatus of claim 7 including: means for receiving pulse signals; and means connecting the means for receiving to the further counter means.
9. The apparatus of claim 8 including: means for transmitting pulse signals; and means connected to the means for transmitting for varying the number of pulses transmitted.
10. The apparatus of claim 9 including: means connected to the means for transmitting for encoding the transmitted pulse signals; and means connected to the means for receiving for decoding the transmitted pulse signals.
11. Digital apparatus for electro-medical stimulation comprising: first binary counter means having input terminal means, reset terminal means and output terminal means; second binary counter means having input terminal means and output terminal means; data input means connected to the first counter input terminal means and reset terminal means; binary clock means connected to the second counter input terminal means; logic circuit means having input terminal means and output terminal means; means connecting a portion of the first and second binary counter output terminal means to the logic circuit means input terminal means; output circuit means adapted to be connected to a portion of a body; and means connecting the logic circuit means output terminal means to the output circuit means.
12. The apparatus of claim 11 in which said second binary counter includes reset terminal means connected to said output circuit means.
13. The apparatus of claim 11 including: inhibit means included in the output circuit means further of the second binary counter output terminal means connected to the output circuit means inhibit means for inhibiting operation of the output circuit means until a minimum count is reached in the second binary counter means.
14. The apparatus of claim 11 including: output pulse width control means; and means connecting the output pulse width control means between the output circuit means and a further portion of the first binary counter output terminal means.
15. The apparatus of claim 14 in which the output pulse width control means comprises: monostable multivibrator means, means for adjusting the period of oscillation of the monostable multivibrator means; and means connecting the means for adjusting to the further portion of the first binary counter output terminal means for controlling the period of oscillation according to the binary states of the further portion of the first binary counter output terminal means.
16. The apparatus of claim 11 in which the logic circuit means includes: a plurality of logic gates having input terminal means and output terminal means; each of the logic gates having a portion of its input terminal means connected to a portion of the first binary counter output terminal means, and having a further portion of its input terminal means connected to a portion of the second binary counter output terminal means; and means connecting the logic gates output terminal means to the logic circuit means output terminal means.
17. The apparatus of claim 11 including: second logic circuit means having input terminal means and output terminal means; means connecting a further portion of the first and second binary counter output terminal means to the second logic circuit means input terminal means; and means connecting the second logic circuit means output terminal means to the output circuit means.
18. The apparatus of claim 17 in which the output circuit means includes: means responsive to the logic circuit means for starting an output signal; and means responsive to the second logic circuit means for stopping the output signal.
19. The apparatus of claim 11 in which the data input means includes: RF receiver and decoder means.
20. The apparatus of claim 19 including in combination: RF transmitter and encoder means.
21. The apparatus of claim 20 in which the RF transmitter and encoder means includes: enabling means; RF oscillator means having a transmission coil; code logic means connecting the enabling means to the oscillator means for providing a first timed period of oscillation when the enabling means is actuated; further binary counter means; further binary clock means; means connecting the further clock means between the enabling means and the further counter means and to the code logic means; means connecting the further counter means to the code logic means; means for commencing a plurality of further timed periods of oscillation in response to the output pulses of the further clock means; means connected to the further counter means for stopping the further timed periods of oscillation until the enabling means is again actuated; and selection means connected to the further counter means for selecting a desired number of the further timed periods of oscillation.
22. The apparatus of claim 21 in which the RF receiver and decoder means includes: means for detecting the first timed period of oscillation; further code logic means connected to the means for detecting and enabled thereby only where a pulse of the first timed period and frequency of oscillation is detected; the means for detecting and the further code logic means also for detecting the further timed periods of oscillation and for providing a binary count signal to the input terminal means of the first binary counter means for each such further timed period occurring within a predetermined time.
23. In implantable cardiac pacer apparatus, including electrode means adapted to be connected to a heart and circuit means for providing electrical impulses on the electrode means, the improvement comprising: electrical storage means for storing programs and having at least first and second storage portions; means for receiving remotely sent programs connected to the first storage portion; clock means; means connecting the clock means to the second storage portion; means for comparing programs stored in the first and second storage portions for providing signals; means for connecting the means for comparing between the first and second storage portions and the circuit means, for controlling the electrical impulses according to the stored program; and all said means encapulated in means substantially inert to body fluids and tissue.
24. The apparatus of claim 23 in which the means for receiving remotely sent programs comprises: means for receiving and decoding transmitted RF signals.
25. The apparatus of claim 24 including in combination: means for transmitting coded RF signals representative of a storable electrical program.
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