Data transmission with dual PSK modulation专利检索-正交相移键控电信专利检索查询-专利查询网

Data transmission with dual PSK modulation

阅读：382发布：2021-11-23

专利汇可以提供Data transmission with dual PSK modulation专利检索，专利查询，专利分析的服务。并且A binary data stream of cadence f to be transmitted by PSK (phase-shift keying) modulation is split into two pulse sequences, composed of alternate bits of that data stream, which are translated into 180* phase shifts of respective sinusoidal carrier waves in quadrature with each other, the frequency f of the two carrier waves being the reciprocal of the pulse width 2/f of the two pulse sequences in a specific instance. A pair of interleaved trains of trigger pulses, each coinciding with the zero crossings of a respective carrier wave, enable the operation of associated phase shifters - in response to amplitude changes of the respective pulse sequences - only at a peak of a carrier wave in trailing position or at a zero crossing of a carrier wave in leading position, thereby minimizing the amplitude excursions occurring upon a subsequent passage of the combined carrier waves through a band-pass filter or other network of limited bandwidth.，下面是Data transmission with dual PSK modulation专利的具体信息内容。

权利要求

1. A system for transmitting information contained in a bit stream having a cadence f, comprising: conversion means for deriving from said bit stream a pair of pulse sequences of pulse width 2/f composed of lengthened alternate bits of said bit stream; a source of two sine waves, of a frequency at least equal to half the reciprocal of said pulse width 2/f, in quadrature with each other; a pair of phase inverters for said sine waves respectively responsive to said square waves for translating amplitude changes of said pulse sequences into 180* phase shifts of said sine waves; pulse-generating means for producing two interleaved trains of trigger pulses respectively coinciding with the zero crossings of said sine waves; delay means connected to said conversion means for preventing the transmission of said amplitude changes to said phase inverters until the arrival of a trigger pulse; discriminating means responsive to the relative amplitudes of said pulse sequences for controlling the transmission of said trigger pulses to said delay means to reverse the phase of a sine wave in trailing position only at a peak thereof and of a sine wave in leading position only at a zero crossing thereof; and circuit means of limited bandwidth connected to said source downstream of said phase inverters for synthesizing a phasemodulated carrier from the combined sine waves.

2. A system as defined in claim 1 wherein said circuit means comprises a summing circuit followed by a linear bandpass filter.

3. A system as defined in claim 1 wherein said delay means comprises a pair of buffer registers and timing means synchronized with said conversion means for alternately loading said buffer registers with the pulses of said pulse sequences, respectively, said discriminating means including a selection network connected to the outputs of said buffer registers and switch means controlled by said selection network for applying trigger pulses from either train in parallel to respective reading inputs of said buffer registers.

4. A system as defined in claim 3 wherein said selection network is an Exclusive-OR gate.

5. A system as defined in claim 3 wherein said source comprises an oscillator working in parallel into said phase inverters and a 90* phase shifter inserted between said oscillator and one of said phase inverters, said pulse-generating means including a pair of zero-crossing detectors respectively connected to the output of said oscillator and to the output of said phase shifter.

6. A system as defined in claim 5 wherein said oscillator has a synchronizing input connected to said timing means for maintaining a predetermined time position between said trigger pulses and the pulses of said pulse sequences.

7. A system as defined in claim 5 wherein said conversion means comprises a stream splitter, a pair of intermediate registers inserted between said stream splitter and said buffer registers, and transfer means alternately operable by said timing means for discharging said intermediate registers into said buffer registers.

8. A system as defined in claim 7 wherein said loading means comprises a flip-flop switchable by said timing means.

9. A method of transmitting information contained in a bit stream having a cadence f, comprising the steps of: converting said bit stream into a pair of pulse sequences of pulse width 2/f composed of lengthened alternate bits of said bit stream; generating a pair of sine waves, of a frequency at least equal to half the reciprocal of said pulse width 2/f, in quadrature with each other; determining at each instant the relative phase of said sine waves; reversing the phase of each sine wave in response to amplitude changes of a respective pulse sequence, a phase reversal of a sine wave in trailing position taking place only at a peak thereof and a phase reversal of a sine wave in leading position taking place only at a zero crossing thereof; and combining the two sine waves into an outgoing carrier.

10. A method as defined in claim 9 wherein said sine waves are of frequency f/2.

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Data transmission with dual PSK modulation

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