专利汇可以提供A/d converter专利检索,专利查询,专利分析的服务。并且PURPOSE: To shorten the A/D conversion time, that is, to realize the same effect as the high speed A/D conversion by devising the A/D converter such that a delay time till a digital output signal is read after the end of the A/D conversion is shortened as small as possible.
CONSTITUTION: For example, a 10-bit shift register 11 is provided in a successive approximation register(SAR) 15 to count comparison stage from a most significant bit to a least significant bit. A carrying signal (i) is imparted from a 0-th order bit of the shift register 11, the signal (j) of a counted value '1' is imparted from a 1st bit and the signal (k) of a counted value '1' is imparted from a 2nd bit to a selector circuit 13. Moreover, the selector circuit 13 is controlled by a CPU 3 and one among the signals i, j, k is outputted to a register 14 as an end flag. The selector circuit 13 is provided with internal registers iR, jR and kR, and as soon as the counting signals i, j, k are detected from the shift register 11, the signals are recorded in each register. The SAR outputs an interrupt requesting signal 7 a little before the end of A/D conversion.
COPYRIGHT: (C)1992,JPO&Japio,下面是A/d converter专利的具体信息内容。
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