Universal active lattice network专利检索-终端电阻电阻器电气元件和设备专利检索查询-专利查询网

Universal active lattice network

阅读：657发布：2022-01-21

专利汇可以提供Universal active lattice network专利检索，专利查询，专利分析的服务。并且The invention provides an active lattice network which may be used in place of a passive lattice network of any order. There is provided a differential amplifier having a pair of input ports and a pair of output ports. Each of the input ports is connected to the same input terminal through a respective resistance element corresponding to the terminating resistance of the network and to a common terminal through a respective impedance element having predetermined characteristics. The output of the network may be obtained either from the pair of output ports or from one of the output ports and the common terminal.，下面是Universal active lattice network专利的具体信息内容。

权利要求

1. An active lattice network comprising, a common terminal and an input terminal for connection to a source of input signal, a pair of output terminals, a differential amplifier having a pair of input ports and a pair of output ports, each of said input ports being connected to said input terminal through a respective resistance element corresponding to the terminating resistance of the network and to said common terminal through a respective impedance element having predetermined characteristics, said pair of output ports being respectively connected to said pair of output terminals.

2. An active lattice network as defined in claim 1 wherein said output terminals are respectively connected to said common terminal and one of said output ports.

3. An active lattice network as defined in claim 1 wherein said differential amplifier comprises a pair of transistors each having a base, emitter and collector electrodes, the base electrode of each transistor being connected to a respective one of said input ports, the emitter electrodes of the transistors being connected together and to said common terminal through a current source, the collector electrode of each transistor being connected to a source of voltage through a respective resistor and to a respective one of said pair of output ports.

4. An active lattice network as defined in claim 3 wherein said pair of transistors are on the same semiconductor chip.

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Universal active lattice network

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