专利汇可以提供High frequency ring oscillator with feed-forward paths专利检索,专利查询,专利分析的服务。并且An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.,下面是High frequency ring oscillator with feed-forward paths专利的具体信息内容。
What is claimed is:
The present invention relates in general to complementary metal oxide semiconductor (CMOS) circuits for implementing a very high frequency voltage controlled oscillator (VCO).
Phase-locked loops (PLLs) have been widely used in high-speed communication systems because PLLs efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with nominal power supply voltages and high frequency clock operation or low performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL, this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency. The prior art has described ways of selecting operating points of voltage and frequency statically, for example, stopping execution while allowing the PLL to frequency lock to a new frequency. This slows system operations and complicates system design.
One of the key circuits in a PLL is a voltage-controlled oscillator (VCO). Circuits in the PLL generate an error voltage that is coupled to the VCO to control the frequency of the VCO output. By frequency dividing the output of the PLL and feeding it back and comparing it to a low frequency crystal-controlled reference clock, a stable high frequency clock may be generated. The VCO in a PLL typically has a range over which the frequency of the VCO may be voltage-controlled. In systems employing frequency scaling, it is desirable to have a voltage-controlled frequency range for normal voltage operation and another voltage-controlled frequency range for low voltage operation without resorting to two VCOs.
The VCO circuit is sometimes considered the most difficult circuit to implement in the PLL especially if ultra high frequencies and low jitter are required. Typically, the VCO is made using five or more inverting elements in a ring oscillator configuration. Standard ring oscillator topologies are relatively simple to design, have low-power, and have robust noise margins. The main drawback to the ring oscillator is that many stages are required to generate high quality signals and many stages lead to lower frequencies.
The requirements for high frequency VCOs are becoming more demanding and in some cases the shortest ring oscillator of three stages may not produce sufficiently high frequencies. A number of circuit topologies have been developed to improve the frequencies possible with the ring oscillator. One such circuit topology is the “classic interpolator” as seen in
When high frequency VCOs are configured using inverting stages in a ring topology, it is important to know what are the best and worst case ranges that are achievable give process variations. In many cases, the guaranteed usable range is too narrow for a wide range of applications. This limits the application of the VCO and may require a selection process at the chip level to determine if a particular chip VCO has a realizable desired frequency range.
Therefore, there is a need for a way of configuring a ring VCO with a wide band useable frequency range when considering worst and best case process variations.
A voltage controlled ring oscillator is configure using inverting stages with voltage controlled pass gates coupling a parallel stage to each output of the main ring and a voltage controlled pass gate coupling feed-forward stages to each output of main ring. When the voltage controlled coupling is turned OFF, the basic ring oscillator operates at its lowest frequency where each inverting stage in the main ring is loaded with the highest capacitance of inactive stages. As the voltage controlled coupling is turned progressively ON, the inverting stages in the main ring are paralleled with inverting stages that increase the drive at each output from the main ring and from a feed-forward signal thereby increasing the oscillating frequency. The capacitance decreases the low frequency range while leaving the high frequency range-unaffected thus allowing a wider guaranteed band of worst/best case operation.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits may be shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing, and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.
Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
No matter what output state is assumed, traversing through the forward delay path will yield a logic state that changes the assumed state. This is true for P and N channel devices which in each stage are coupled to different gate control signals. This circuit topology will give good results; however, it does not have a phase synchronous complementary output and it is limited to 5 stages because each stage feeds back from 3 stages ahead which requires 4 stages and the overall circuit must be inverting so it requires 5 stages.
Input IN 1 621 is coupled to Input 650 of inverter 601 configured with PFET 610 and NFET 611 and the output of inverter 601 is coupled to OUT 623 of MI-G 630. Inverter 601 is in the main path (e.g., making up the main ring). Inverter 603 is configured with PFET 616 and NFET 617 and is coupled in parallel with inverter 601 with pass gate 619 which is controlled by voltage VCT 620. Inverter 603 forms the secondary path from IN 1 621 to OUT 623. A signal at IN 2 622 is coupled to OUT 623 by inverter 602 and pass gate 618. Inverter 602 is configured with PFET 612 and NFET 613. The signals at IN 1 621 and IN 2 622 “interpolate” to generate the output signal at OUT 623 depending on their timing and the strength of the coupling determined by voltage VCT 624. The signal at IN 2 622 is also coupled to OUT 623 via inverter 604 and pass gate 619. Inverter 604 is configured with PFET 614 and NFET 615. The strength of signal at IN 2 622 is further modulated by pass gate 619. Normally all the inverters 601-604 are the same size, however, they may have variable sizes and still be within the scope of the present invention. Pass gate 619 is normally twice as big as pass gate 618 since it has to conduct the current of both inverters 603 and 604. When pass gates 618 and 619 are both turned OFF, only the signal from inverter 601 is used to drive OUT 623. In this case, all the capacitance of the other devices load OUT 623, thus the response through inverter 601 is the slowest. As VCT turns ON pass gates 618 and 619 the drive from inverters 602-604 assist in driving the capacitance at output 623 and the response to output 623 is the faster. The signal at OUT 623 is the interpolation of the signals at IN 1 621 and IN 2 622 coupled through inverters 602-604 via pass gates 618 and 619. The large capacitance load on inverter 601, when the pass gates 618-619 are OFF, sets the low frequency response of MI-G 630 substantially independent of the high frequency response. The drive and the interpolation of inverters 602-604 via pass gates 618-619 sets the high frequency response of MI-G 630. When MI-G 630 is used to form a ring oscillator, a wider frequency range is realized under best/worst case process variations.
Referring to
Although the method, system and computer program product are described in connection with several embodiments, it is not intended to be limited to the specific forms set forth herein, but on the contrary, it is intended to cover such alternatives, modifications and equivalents, as can be reasonably included within the spirit and scope of the invention as defined by the appended claims. It is noted that the headings are used only for organizational purposes and not meant to limit the scope of the description or claims.
标题 | 发布/更新时间 | 阅读量 |
---|---|---|
一种基于电荷泵的高压驱动电路 | 2020-05-08 | 619 |
一种低电源灵敏度的电感电容压控振荡器及其应用 | 2020-05-08 | 855 |
一种锁相环路频率合成器自动校准电路及方法 | 2020-05-08 | 614 |
锁相环及其压控振荡器的校准方法 | 2020-05-08 | 863 |
一种FPGA高速收发器及其动态控制方法 | 2020-05-08 | 856 |
射频信号放大装置和射频前端模组 | 2020-05-08 | 903 |
一种用于高速接口电路的自适应电荷泵锁相环 | 2020-05-08 | 853 |
用于晶体振荡器热漂移的后补偿 | 2020-05-11 | 162 |
一种发光组件、调光调色电路及调光调色装置 | 2020-05-08 | 632 |
一种电加热设备的温度控制器 | 2020-05-08 | 479 |
高效检索全球专利专利汇是专利免费检索,专利查询,专利分析-国家发明专利查询检索分析平台,是提供专利分析,专利查询,专利检索等数据服务功能的知识产权数据服务商。
我们的产品包含105个国家的1.26亿组数据,免费查、免费专利分析。
专利汇分析报告产品可以对行业情报数据进行梳理分析,涉及维度包括行业专利基本状况分析、地域分析、技术分析、发明人分析、申请人分析、专利权人分析、失效分析、核心专利分析、法律分析、研发重点分析、企业专利处境分析、技术处境分析、专利寿命分析、企业定位分析、引证分析等超过60个分析角度,系统通过AI智能系统对图表进行解读,只需1分钟,一键生成行业专利分析报告。