Logic gate
阅读：23发布：2023-02-28
专利汇可以提供Logic gate专利检索，专利查询，专利分析的服务。并且A logic circuit having a first multiemitter transistor each of whose emitters is connected to a different input terminal and whose collector is connected to a junction point. A second transistor, whose conduction is controlled by means of a plurality of diodes coupled between its base and a different one of the input terminals, has its emitter connected to the base of the first transistor. For one operating condition the emitter-tobase junctions of the first transistor as well as the diodes are reverse biased and the second transistor provides a high transient current followed by a lower steady state current, through the base-to-collector junction of the first transistor, into the junction point. For another operating condition at least one of the emitter-to-base junctions of the first transistor as well as at least one of the diodes are forward biased and a transient current is provided to the base of the first transistor which then draws its collector current out of the junction point.，下面是Logic gate专利的具体信息内容。
1. In a logic circuit, in combination: a first transistor having a collector, base and emitter; a current source; a second transistor having a collector, base and emitter, directly connected at its base to said current source and at its emitter to the base of said first transistor, the base-toemitter path of said second transistor being in the forward direction relative to the flow of current from said source; an asymmetrically conducting device connected between the emitter of said first transistor and the base of said second transistor, said device being poled in the forward direction relative to the flow of current from said source; a signal input terminal at said emitter of said first transistor; and means for applying a signal to said input terminal which, when of one value, is sufficient to forward bias said device for causing the current from said current source to flow into said device and into said input terminal, and when of second value is sufficient to reverse bias said device and the emitter-tobase path of said first transistor for causing the current from said current source to flow through the base to emitter path of said second transistor and the base-to-collector path of said first transistor.
2. In a logic circuit as set forth in claim 1, further including a third transistor having a base, emitter and collector, the emitter of said third transistor being connected to the collector of said second transistor, and the collector of said third transistor being connected to a source of operating potential poled in a direction to permit said third transistor to conduct current through its collector-to-emitter path to said second transistor; and means coupled to the base of said third transistor and responsive to said first transistor for controlling the state of said third transistor.
3. The combination as claimed in claim 2 wherein said last-named means comprises a fourth transistor having collector, base and emitter, connected at its base to the collector of said first transistor and responsive to base-to-collector current flow in said first transistor for conducting and applying a signal to the base of said third transistor for cutting the latter off.
4. The combination as claimed iN claim 2, wherein said last-named means comprises a fourth transistor having a collector, base and emitter, connected at its base to the collector of said first transistor and responsive to base-to-emitter current flow in said first transistor for being driven to cutoff and for applying a signal to the base of said third transistor for driving the latter into conduction.
5. In a logic circuit as set forth in claim 1, said asymmetrically conducting device comprising a diode.
6. The combination as claimed in claim 5 further including: first and second power terminals for a source of operating potential, and wherein said current source includes a resistor connected at one end to the base of said second transistor and at the other end to that one of said two power terminals which is poled to forward bias the base-to-emitter junction of said second transistor.
7. The combination as claimed in claim 6 further including a resistor connected at one end to said signal input terminal and at the other end to that one of the two power terminals whose potential is in a direction to reverse bias said asymmetrically conducting device.
8. The combination as claimed in claim 3 further including at least one alternating current coupling element coupled between the collector of said second transistor and the base of said first transistor responsive to an abrupt change in potential at the collector of said second transistor for alternating current coupling a corresponding change in voltage to the base of said first transistor.
9. The combination as claimed in claim 8 wherein said coupling element comprises a reverse biased semiconductor junction.
10. In a logic circuit, in combination: a plurality of input signal terminals adapted to receive multivalued signals; a transistor having a plurality of emitters each connected to a different one of said input terminals, a base, and a collector having a capacitance associated therewith; a source of current; current amplifying means, having a control electrode connected to said source of current, for amplifying the current from said current source and for supplying the amplified current to the base of said transistor, said amplified current flowing from the base-to-collector of said transistor for charging the capacitance associated therewith in response to signals applied at said input terminals having a value to reverse bias the base-to-emitter junctions of said transistor; asymmetrically conducting means, connected between the control electrode of said current-amplifying means and a different one of said input terminals in a direction to easily conduct current from said control electrode to said input terminals, said asymmetrically conducting means being responsive to signals having a first voltage level applied at said input terminals in a direction to forward bias one or more of the emitter-to-base junctions of said transistor for causing said current source current to flow through said asymmetrically conducting means and thereby preventing the further flow of current source current to said amplifying means.
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