专利汇可以提供Frequency calibration circuit for automatically calibrating frequency and method thereof专利检索,专利查询,专利分析的服务。并且Generate a series of digital data according to a pair of differential signals received from a low speed universal serial bus. Calibrate coarsely a frequency of an oscillator according to a width of an end-of-packet of the series of digital data. And calibrate finely the frequency of the oscillator according to a width of a SYNC pattern of the series of digital data.,下面是Frequency calibration circuit for automatically calibrating frequency and method thereof专利的具体信息内容。
What is claimed is:
This application claims the benefit of U.S. Provisional Application No. 61/359,829, filed on Jun. 30, 2010 and entitled “FREQUENCY CALIBRATION CIRCUIT FOR AUTOMATICALLY CALIBRATING FREQUENCY AND METHOD THEREOF,” the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention is related to a frequency calibration circuit for automatically calibrating frequency and method thereof, and particularly to a frequency calibration circuit for automatically calibrating frequency according to an end-of-packet and a SYNC pattern of a low-speed Universal Serial Bus and method thereof.
2. Description of the Prior Art
An oscillator is one component found in many electronic products. Periodic waves generated by oscillators may be employed as carriers in communication systems, as timers or counters in computers or control systems, and as signals with different clocks used to control other circuits in microprocessors.
Generally speaking, frequencies generated by crystal oscillators, such as quartz oscillators, are more accurate, but system vendors often use less accurate non-crystal oscillators, such as resistor-capacitor (RC) oscillators, due to lower cost. The prior art uses corrected parameters to program non-volatile memories, such as an erasable programmable read only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), and a flash memory, during production of the non-volatile memories, or uses laser-trimming to calibrate the frequency of the RC oscillator. However, regardless of whether the corrected parameters are written to the non-volatile memory or the laser-trimming is employed, additional cost is incurred.
An embodiment of the present invention provides a method for automatically calibrating frequency. The method includes generating a series of digital data according to a pair of differential signals received from a low-speed Universal Serial Bus (USB); outputting a first pulse and a first predetermined value when an end-of-packet (EOP) is detected from the series of digital data; counting a first number of clocks generated by an oscillator during the first pulse; comparing the first number of clocks with the first predetermined value to generate a first comparison result; calibrating coarsely a frequency of the oscillator according to the first comparison result; outputting a second pulse and a second predetermined value when a SYNC pattern is detected; counting and accumulating a second number of clocks generated by the oscillator during the second pulse; counting number of the second pulses; stopping counting and accumulating the second number of clocks when the number of the second pulses is equal to a predetermined value; comparing the accumulated second number of clocks with the second predetermined value to generate a second comparison result; calibrating finely the frequency of the oscillator according to the second comparison result; and clearing the number of the second pulses.
Another embodiment of the present invention provides a frequency calibration circuit for automatically calibrating frequency. The frequency calibration circuit includes a Universal Serial Bus, a physical layer, a pulse generator, an oscillator, a first counter, a comparator, and a controller. The Universal Serial Bus is used for transmitting a pair of differential signals from a host in a low-speed mode. The physical layer is coupled to the Universal Serial Bus for converting the pair of differential signals into a series of digital data, wherein the series of digital data comprises a plurality of binary data packets, idle data, and a plurality of keep-alive end-of-packets. The pulse generator is coupled to the physical layer for determining to output a first pulse corresponding to an end-of-packet or a second pulse corresponding to a SYNC pattern and determining to output a first predetermined value corresponding to the end-of-packet or a second predetermined value corresponding to the SYNC pattern according to an adjusting signal when detecting the end-of-packet or the SYNC pattern from the series of digital data. The oscillator is used for generating clocks. The first counter is coupled to the pulse generator and the oscillator for counting first number of clocks generated by the oscillator during the first pulse and counting second number of clocks generated by the oscillator during the second pulse. The comparator is coupled to the first counter and the pulse generator for comparing the first number of clocks with the first predetermined value to generate a first comparison result, and comparing the accumulating second number of clocks with the second predetermined value to generate a second comparison result. The controller is coupled to the comparator, the oscillator, and the pulse generator for generating the adjusting signal according to the second pulse, and calibrating the clocks generated by the oscillator according to the first comparison result and the second comparison result.
The present invention provides a frequency calibration circuit for automatically calibrating frequency and method thereof. The frequency calibration circuit for automatically calibrating frequency and method thereof utilize an end-of-packet of a low-speed Universal Serial Bus to calibrate coarsely a frequency of an oscillator, and a SYNC pattern of the low-speed Universal Serial Bus to calibrate finely the frequency of the oscillator. Thus, the present invention may be applied to electronic products without using the non-volatile memory and/or the laser trimming to greatly simplify process of manufacturing and testing chips.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
The pulse generator 106 includes a first pulse generator 1062, a second pulse generator 1064, a second counter 1066, a first multiplexer 1068, and a second multiplexer 1070. The first pulse generator 1062 is coupled to the physical layer 104 for generating the first pulse P1. The second pulse generator 1064 is coupled to the physical layer 104 for generating the second pulse P2, and a control signal COL for the controller 114. The second counter 1066 is coupled to the second pulse generator 1064 for counting a number of the second pulses. The second counter 1066 stops counting and clearing the number of the second pulses when the number of the second pulses is equal to the predetermined value K. The first multiplexer 1068 is coupled to the first pulse generator 1062, the second counter 1066 and the controller 114 for determining to output the first pulse P1 or the second pulse P2 to the first counter 110 according to the coarse tune mode CM or the fine tune mode FM.
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Step 500: Start.
Step 502: The physical layer 104 generates the series of digital data according to the pair of differential signals received from the low-speed Universal Serial Bus 102.
Step 504: The first pulse generator 1062 generates the first pulse P1 when the end-of-packet is detected from the series of digital data.
Step 506: The first multiplexer 1068 outputs the first pulse P1 to the first counter 110 according to the coarse tune mode CM of the adjusting signal.
Step 508: The second multiplexer 1070 outputs the first predetermined value V1 to the comparator 112 according to the coarse tune mode CM of the adjusting signal.
Step 510: The first counter 110 counts the first number of clocks C1 generated by the oscillator 108 during the first pulse P1.
Step 511: The comparator 112 compares the first number of clocks C1 and the first predetermined value V1; if the absolute value of the first difference between the first number of clocks C1 and the first predetermined value V1 is greater than the first threshold value T1, the comparator 112 generates the first comparison result E1 and proceeds to Step 512; if not, go to Step 514.
Step 512: The controller 114 calibrates coarsely the frequency of the oscillator 108 according to the first comparison result E1.
Step 514: Does the second pulse generator 1064 detect the SYNC pattern from the series of digital data? If yes, go to Step 516; if no, go to Step 510.
Step 516: When the second pulse generator 1064 detects the SYNC pattern from the series of digital data, the second pulse generator 1064 generates the second pulse P2 to the second counter 1066 and a control signal COL to the controller 114.
Step 518: The controller 114 adjusts the adjusting signal from the coarse tune mode CM to the fine tune mode FM according to the control signal COL.
Step 520: The first multiplexer 1068 outputs the second pulse P2 to the first counter 110 according to the fine tune mode FM of the adjusting signal.
Step 522: The second multiplexer 1070 outputs the second predetermined value V2 to the comparator 112 according to the fine tune mode FM of the adjusting signal.
Step 524: The first counter 110 counts and accumulates the second number of clocks C2 generated by the oscillator 108 during the second pulse P2.
Step 526: The second counter 1066 counts the number of the second pulses and determines whether the number of the second pulses is equal to the predetermined value K; if yes, go to Step 528; if no, go to Step 524.
Step 528: The first counter 110 stops counting and accumulating the second number of clocks.
Step 530: The comparator 112 compares the accumulated second number of clocks C2*K with the second predetermined value V2; if the absolute value of the second difference between the accumulated second number of clocks C2*K and the second predetermined value V2 is greater than a second threshold value T2, the comparator 112 generates the second comparison result E2 and proceeds to Step 532; if not, go to Step 524.
Step 532 The controller 114 calibrates finely the frequency of the oscillator 108 according to the second comparison result E2.
Step 534: The second counter 1066 clears the number of the second pulses; go to Step 524.
In Step 504, as shown in
In Step 516, when the second pulse generator 1064 detects the SYNC pattern from the series of digital data, the second pulse generator 1064 generates the second pulse P2 to the second counter 1066 and a control signal COL to the controller 114, where the second counter 1066 starts to count the number of the second pulses. In Step 518, the controller 114 adjusts the adjusting signal from the coarse tune mode CM to the fine tune mode FM according to the control signal COL. In Step 524, the first counter 110 counts and accumulates the second number of clocks C2 generated by the oscillator 108 during the second pulse P2. That is to say, when the number of the second pulses is not yet equal to the predetermined value K, the first counter 110 keeps on counting and accumulating the second number of clocks C2, and does not send the second number of clocks C2 to the comparator 112 temporarily, where the predetermined value K is set by the user. As shown in
To sum up, the frequency calibration circuit for automatically calibrating frequency and method thereof utilize the end-of-packet of the low-speed Universal Serial Bus to calibrate coarsely the frequency of the oscillator, and the SYNC pattern of the low-speed Universal Serial Bus to calibrate finely the frequency of the oscillator. Thus, the present invention may be applied to electronic products without using the non-volatile memory and/or the laser trimming to greatly simplify processes of manufacturing and testing chips.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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