Error detection system专利检索-算术逻辑单元中央处理器电脑零配件专利检索查询-专利查询网

Error detection system

阅读：364发布：2021-10-24

专利汇可以提供Error detection system专利检索，专利查询，专利分析的服务。并且The present invention includes circuitry for generating signals corresponding to the predicted residues of logic operations performed in the arithmetic logic unit of a digital processor. In addition, circuitry for generating signals corresponding to the actual residue of the result of a logic operation performed in the arithmetic logic unit and means for comparing the predicted and actual residue signals are provided thereby to check the accuracy of the logic calculations performed in the arithmetic logic unit.，下面是Error detection system专利的具体信息内容。

权利要求

1. In a data processing system including a first generator circuit for generating output signals in response to control circuitry which output signals represent a selected logic function of first and second input signals, a circuit for checking the operation of said first generator circuit comprising a. means for generating reference logic signals representing a reference logic function of said first and second input signals, b. residue generating means for generating first, second, third and fourth residue signals representing, respectively, the residues of said first and second input signals, the residue of said output signals and the residue of said reference logic signals, c. a residue manipulation circuit responsive to said residue generating means for generating a residue predictor signal, said manipulation circuit comprising 1. adder means for generating signals corresponding to the mod 3 addition function of said first and second residue signals, 2. second generator means responsive to said adder means and said reference logic residue signals for generating a plurality of constituent logic function signals, and 3. means responsive to said control circuitry for selecting one of said constituent logic function signals, and d. means for comparing said selected constituent logic function signal and said third residue signal and for generating a signal when said selected logic function signal and said third residue signal are not identical thereby to signal an error in said selected logic function signal.

2. second generator means responsive to said adder means and said reference logic residue signals for generating a plurality of constituent logic function signals, and

2. Apparatus according to claim 1 wherein said second generator circuit comprises a plurality of selectable logic circuits, each arranged to generate one of said constituent logic function signals, and wherein said means for selecting responsive to said control circuitry comprises a decoder responsive to said control signals for generating signals for selecting one or more of said selectable logic circuits.

3. means responsive to said control circuitry for selecting one of said constituent logic function signals, and d. means for comparing said selected constituent logic function signal and said third residue signal and for generating a signal when said selected logic function signal and said third residue signal are not identical thereby to signal an error in said selected logic function signal.

3. Apparatus according to claim 2 wherein said means for generating reference logic signals comprises an AND gate.

4. Apparatus according to claim 2 wherein said means for generating reference logic signals comprises a NAND gate.

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Error detection system

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