Binary arithmetic, logical and shifter unit
阅读：173发布：2021-10-25
专利汇可以提供Binary arithmetic, logical and shifter unit专利检索，专利查询，专利分析的服务。并且The arithmetic logic unit and position scaler receives information from a data bus, provides arithmetic functions such as add, logical AND and exclusive OR, and shift manipulations to the information received from the data bus, and then directs the resultant information to the same data bus. The information bit position scaler or shifter includes logic for shifting bit information in a right, left or circular mode. The position scaler provides layers of shifts with the last shift of one being performed in a multiplexer unit which is common to the arithmetic logic unit.，下面是Binary arithmetic, logical and shifter unit专利的具体信息内容。
1. In a data processing system having a data bus for receiving and transmitting sets of data information bit signals, and instruction means for generating arithmetic commands, shift commands and instruction signals, an arithmetic logic system comprising: arithmetic selection means for receiving the arithmetic commands and for generating arithmetic function signals in response thereto; input storage means connected to said data bus to receive a set of data information bit signals for storing the received data information bit signals as one of the arithmetic operands upon actuation of an allow input instruction signal from the instruction means; arithmetic gating means connected to said arithmetic selection means for receiving arithmetic function signals; a plurality of full adder units, one for each data information bit signals in a set, connected to said arithmetic gating means; output storage means connected to said plurality of full adder units for storing a second arithmetic operand comprising a set of data information bit signals and for storing the resultant of the arithmetic and logic operations; carry look ahead means connected to said arithmetic gating means for gating an overflow signal in the event the arithmetic operation results in an excess information bit over the number in a set of data information bit signals, said carry look ahead means generating said excess information bit signal when requested by an instruction signal requesting the carry information from the instruction means; said input and output storage means addressing said arithmetic gating means, wherein said arithmetic gating means operates in response to the arithmetic commands to perform arithmetic and logic functions on the data information bit signals in said input and output storage means in cooperation with said plurality of full adder units, the resultant froM said plurality of full adder units being directed to said output storage means for storage therein; and means connected to said output storage means and receiving an instruction signal from said instruction means for gating the resultant set of data information bit signals to said data bus.
2. An arithmetic logic system as defined in claim 1 further including a shift section for shifting position of a set of information bit signals, either right or left with blank information fill, said shift section comprising: a shift selection means for receiving the shift commands and for generating shift direction signals designating the right or the left shift of information bit signals and for generating shift selection signals, and responsive thereto to generate first shift signals comprising the concurrent activation of the shift direction signals with a true and inverted highest shift selection signal, and subsequent shift signals comprising the remaining shift selection signals and an inverted counterpart of each shift selection signal; a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the data information bit signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit; said highest shift selection unit connected to receive a set of data information signals from said data bus and said first shift signals from said shift selection means, for shifting the received data information signals the number of positions required by said highest shift selection unit; said lower shift selection units shifting in one direction only and connected to said shift selection unit to receive shift selection signals for activation of the shift selection unit to shift the data information bit signals the positions required according to the unit; and a third storage means connected to said lowest shift unit for receiving and storing the shifted data information bit signals and for transmitting said stored data information bit signals to said data bus.
3. A shift section as defined in claim 2 wherein both left and right shift direction signals are activated to form a circular shift thereby placing the lesser significant digits into more significant positions and vice versa without loss of data information bit signals.
4. A shift section as defined in claim 2 wherein the number of information bit signals shifted are equal to eight, said plurality of shift selection units are equal in number to three, the highest shift selection unit shifts the information bits four places and the lower shift selection unit shifts the information bit signals two and one places respectively.
5. An arithmetic logic system as defined in claim 1 wherein said means connected to said output storage means is a multiplexer unit performing a shift by one scaler function on a set of data information bit signals.
6. An arithmetic logic system as defined in claim 5 further including a shift section for shifting position of a set of information bit signals, either right or left with blank information fill, said shift section comprising: a shift selection means for receiving the shift commands and for generating shift direction signals designating the right or the left shift of information bit signals and shift selection signals, and responsive thereto to generate first shift signals comprising the concurrent activation of the shift direction signals with a true and inverted highest shift selection signal, and subsequent shift signals comprising the remaining shift selection signals and an inverted counterpart Of each shift selection signal; a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the data information bit signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, the lowest or shift by one selection unit being performed by said multiplexer unit; said highest shift selection unit connected to receive a set of data information signals from said data bus and said first shift signals from said shift selection means, for shifting the received data information signals the number of positions required by said highest shift selection unit; said lower shift selection units, including said multiplexer unit, shifting in one direction only and connected to said shift selection unit to receive shift selection signals for activation of the shift selection unit to shift the data information bit signals the positions required according to the unit; and a third storage means connected between the next lowest shift selection unit and the shift by one selection unit of the multiplexer for receiving and storing the shifted data information bit signals and for transmitting the shifted data information bit signals to said multiplexer for shifting therein, if required, said multiplexer transmitting the fully shifted data information bit signals to said data bus when activated.
7. An arithmetic logic system connected to a data bus for receiving and transmitting sets of data information bit signals from and to the data bus, and receiving arithmetic commands, shift commands and instruction signals from an instruction generating means, said arithmetic logic system comprising: arithmetic selection means for receiving the arithmetic commands and for generating arithmetic function signals in response thereto; input storage means connected to said data bus to receive a set of data information bit signals for storing the received data information bit signals as one of the arithmetic and logical operands upon activation of an allow input instruction signal from the instruction generating means; arithmetic gating means connected to said arithmetic selection means for receiving arithmetic function signals; a plurality of full adder units, one for each data information bit signal in a set, connected to said arithmetic gating means; output storage means connected to said plurality of full adder units for storing a second arithmetic operand comprising a set of data information bit signals and for storing the resultant of the arithmetic and logic operations; said input and output storage means addressing said arithmetic gating means, wherein said arithmetic gating means operates in response to the arithmetic commands to perform arithmetic and logic functions on the data information bit signals in said input and output storage means in cooperation with said plurality of full adder units, the resultant from said plurality of full adder units being directed to said output storage means for storage therein; and means connected to said output storage means and receiving an instruction signal from the instruction generating means for gating the resultant set of data information bit signals to said data bus.
8. An arithmetic logic system as defined in claim 7 further including carry look ahead means connected to said arithmetic gating means for gating an overflow signal in the event the arithmetic operation results in an excess information bit over the number in a set of data information bit signals, said carry look ahead means generating said excess information bit signal when rEquested by an instruction signal requesting the carry information from the instruction means.
9. An arithmetic logic system as defined in claim 7 further including a shift section for shifting position of a set of information bit signals, either right or left with blank information fill, or in a circular mode without loss of data information bit signals.
10. An arithmetic logic system as defined in claim 9 wherein said shift section comprises: a shift selection means for receiving the shift commands and for generating shift direction signals designating the right or the left shift of information bit signals and shift selection signals, and responsive thereto to generate first shift signals comprising the concurrent activation of the shift direction signals with a true and inverted highest shift selection signal, and subsequent shift signals comprising the remaining shift selection signals and an inverted counterpart of each shift selection signal; a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the data information bit signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit; said highest shift selection unit connected to receive a set of data information signals from said data bus and said first shift signals from said shift selection means, for shifting the received data information signals the number of positions required by said highest shift selection unit; said lower shift selection units shifting in one direction only and connected to said shift selection unit to receive shift selection signals for activation of the shift selection unit to shift the data information bit signals the positions required according to the unit; and a third storage means connected to said lowest shift unit for receiving and storing the shifted data information bit signals and for transmitting said stored data information bit signals to said data bus.
11. An arithmetic logic system as defined in claim 7 wherein said means connected to said output storage means is a mutiplexer unit performing a shift by one scaler function on a set of data information bit signals.
12. An arithmetic logic system as defined in claim 11 further including a shift section for shifting position of a set of information bit signals, either right or left with blank information fill, said shift selection comprising: a shift selection means for receiving the shift commands and for generating shift direction signals designating the right or the left shift of information bit signals and shift selection signals, and responsive thereto to generate first shift signals comprising the concurrent activation of the shift direction signals with a true and inverted highest shift selection signal, and subsequent shift signals comprising the remaining shift selection signals and an inverted counterpart of each shift selection signal; a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the data information bit signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, the lowest or shift by one selection unit being performed by said multipLexer unit; said highest shift selection unit connected to receive a set of data information signals from said data bus and said first shift signals from said shift selection means, for shifting the received data information signals the number of positions required by said highest shift selection unit; said lower shift selection units, including said multiplexer unit, shifting in one direction only and connected to said shift selection unit to receive shift selection signals for activation of the shift selection unit to shift the data information bit signals the positions required according to the unit; and a third storage means connected between the next lowest shift selection unit and the shift by one selection unit of the multiplexer for receiving and storing the shifted data information bit signals and for transmitting the shifted data information bit signals to said multiplexer for shifting therein, if required, said multiplexer transmitting the fully shifted data information bit signals to said data bus when activated.
13. An arithmetic logic system connected to a data bus for receiving and transmitting sets of data information bit signals from and to the data bus, and receiving arithmetic commands, shift commands and instruction signals from an instruction generating means, said arithmetic logic system comprising: arithmetic selection means for receiving the arithmetic commands and for generating arithmetic function signals in response thereto; input storage means connected to said data bus to receive a set of data information bit signals for storing the received data information bit signals as one of the arithmetic and logical operands upon activation of an allow input instruction signal from the instruction generating means; arithmetic gating means connected to said arithmetic selection means for receiving arithmetic function signals; a plurality of full adder units, one for each data information bit signal in a set, connected to said arithmetic gating means; output storage means connected to said plurality of full adder units for storing a second arithmetic operand comprising a set of data information bit signals and for storing the resultant of the arithmetic and logic operations; said input and output storage means addressing said arithmetic gating means, wherein said arithmetic gating means operates in response to the arithmetic commands to perform arithmetic and logic functions on the data information bit signals in said input and output storage means in cooperation with said plurality of full adder units, the resultant from said plurality of full adder units being directed to said output storage means for storage therein; a multiplexer unit connected to said output storage means and receiving an instruction signal from said instruction generating means for gating the resultant set of data information bit signals to said data bus; and a shift section controlled by the shift commands for shifting position of a set of information bit signals, either right or left with blank information fill, or in a circular mode without loss of data information bit signals, said multiplexer unit further receiving shifted data information bit signals from said shift section for performing a shift by one scaler function under control of the shift commands for said shift section.
14. An arithmetic logic system as defined in claim 13 further including carry look ahead means connected to said arithmetic gating means for gating an overflow signal in the event the arithmetic operation results in an excess information bit over the number in a set of data information bit signals, said carry look ahead means generating said excess information bit signal when requested by an instruction signal requesting the carry information from the instruction means.
15. A system for performing arithmetic, logical and shifting manipulations on a set of data information bit signals received from a data bus for transmission to tHe same data bus after performing the manipulations according to arithmetic commands, shift commands and instruction signals from an instruction generating means, said system including two identical arithmetic logic systems interconnected such that each transmits a different one-half of the set of data information bit signals to the data bus, each of said arithmetic logic systems comprising: arithmetic selection means for receiving the arithmetic commands and for generating arithmetic function signals in response thereto; input storage means connected to said data bus to receive one-half of a set of data information bit signals for storing the received data information bit signals as one of the arithmetic and logical operands upon activation of an allow input instruction signal from the instruction generating means; arithmetic gating means connected to said arithmetic selection means for receiving arithmetic function signals; a plurality of full adder units, one for each data information bit signal in one-half of a set, connected to said arithmetic gating means; output storage means connected to said plurality of full adder units for storing a second arithmetic operand comprising a one-half set of data information bit signals and for storing the resultant of the arithmetic and logical operations; carry look ahead means connected to said arithmetic gating means for gating an overflow signal in the event the arithmetic operation results in an excess information bit over the number in one-half of a set of data information bit signals, said overflow signal being the carry out signal from the system if the arithmetic logic system handles the most significant digits of the set and a carry in signal to the other arithmetic logic system if the arithmetic logic system handles the lesser significant digit of the set; a multiplexer unit connected to said output storage means and receiving an instruction signal from the instruction generating means for gating the resultant one-half set of data information bit signals to said data bus; and a shift section for shifting position of a one-half set of information bit signals, either right or left with blank information fill, or in a circular mode without loss of data information bit signals, said shift section comprising; a shift selection means for receiving the shift commands and for generating shift direction signals designating the right or the left shift of information bit signals and shift selection signals, and responsive thereto to generate first shift signals comprising the concurrent activation of the shift direction signals with a true and inverted highest shift selection signal, and subsequent shift signals comprising the remaining shift selection signals and an inverted counterpart of each shift selection signal, selectively combined with a signal designating the arithmetic logic system supplying the most significant one-half of the set of data information bit signals to the data bus to permit a left shift only for certain of the information bit signals for the most significant half section and a right shift only to the same information bits for the other half section; a plurality of shift selection units including a highest shift selection unit and one or more lower shift selection units, with the lowest to the highest shift selection units each progressively shifting an incrementally higher power of two from a zero power up to and including a power of two which, when combined, gives a number of shifts to place the most significant information bit signal into the least significant bit position and vice versa, the data information bit signals from the shift selection units being directed, in turn, from the highest shift selection unit to the lowest shift selection unit, the lowest or shift by one selection unit operations being performed by said multiplexer unit; said highest shift selection unit connected to receive a set of data information signals from said data bus and said firSt shift signals from said shift selection means, for shifting the received data information signals the number of positions required by said highest shift selection unit; said lower shift selection units, including said multiplexer unit, shifting in one direction only and connected to said shift selection unit to receive shift selection signals for activation of the shift section unit to shift the data information bit signals the positions required according to the unit; and a third storage means connected between said multiplexer unit and the next lowest shift selection unit for receiving and storing the shifted data information bit signals and for transmitting the shifted data information bit signals to said multiplexer for shifting therein, if required, said multiplexer transmitting the fully shifted one-half set of data information bit signals to said data bus when activated.
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