Digitally controlled weight adjustment system专利检索-超平面数学与统计专利检索查询-专利查询网

Digitally controlled weight adjustment system

阅读：452发布：2021-11-06

专利汇可以提供Digitally controlled weight adjustment system专利检索，专利查询，专利分析的服务。并且A hyperplane radar signature recognizer consists of a delay line through which a radar signature which is to be classified is propagated. The delay line includes a plurality of time spaced taps at which time spaced points on the radar signature are sampled. Each delay line tap is sampled through an associated electrically controlled weight with the weighted samples being summed to provide a measure of signal classification. The electrically controlled weights are controlled by propagating through the delay line prior to the receipt of the radar signature an amplitude standardized pulse. With all weights disabled so as to present an open circuit to the aforementioned summing network the weights are enabled one at a time in turn, and the output from the summing network compared against a desired weight value. The electrically controlled weight is then adjusted until its value is equal to the desired value. After all the electrically controlled weights have been set to their desired values the signature recognizer is ready to receive the radar signature. The timing logic circuit required to program the adjustment of the electrically controlled weights is also disclosed.，下面是Digitally controlled weight adjustment system专利的具体信息内容。

权利要求

1. In a radar signature recognizer which includes: a delay line having a plurality of output taps; a summing network having an output terminal; a plurality of controlled weights, one associated with each said output tap, each said controlled weight being connected between its associated output tap and said summing network; an improvement consisting of means for adjusting said controlled weights comprising: first means for storing in predetermined order the desired value of each of said controlled weight; second means for propagating a standardized amplitude signal through said delay line; third means for activating said controlled weights in a predetermined sequence, one at a time; fourth means comparing the resultant signals at said summing network output terminal with the desired value of the activated controlled weight for generating an error signal; and, fifth means responsive to said error signal for adjusting the activated controlled weight.

2. The improvement of claim 1 wherein said fourth means includes clock means for synchronizing the operation of said fourth means with said first, second, third and fifth means.

3. The improvement of claim 2 wherein said first means comprises shift register means for storing in digital form information related to the desired value of each said controlled weight, said shift register means being responsive to said clock means for strobing said desired values from said shift register means in said predetermined order synchronously with operation of said third means.

4. The improvement of claim 3 with additionally a plurality of means responsive to information strobed from said shift register means for inverting or non-inverting a signal passing therethrough, one of said latter means being connected between each said controlled weight and said summing network.

5. The improvement of claim 1 wherein said plurality of controlled weights comprise a plurality of adjustable electrical resistances.

6. The improvement of claim 1 wherein each of said plurality of controlled weights comprises: a field effect transistor having a source-drain circuit connected between the controlled weight associated delay line output tap and said summing network, and a gate electrode; a capacitor having a first plate connected to said gate electrode and a second plate; and switching means responsive to said third means for selectively applying first and second voltages on said second plate.

7. In a radar signature recognizer which includes: means for delaying a signal propagated therethrough including a plurality of time spaced output taps; means for summing electrical signals applied thereto and including an output terminal upon which first signals related to the sum of said electrical signals is generated; and a plurality of adjustable resistance means, one associated with each said output tap, connected between its associated output tap and said means for summing; an improvement consisting of means for adjusting said resistance means comprising: a source of clock pulses; first means for propagating an amplitude standardized signal through said means for delaying; second means responsive to said clock pulses for generating in predetermined order information related to the desired value of each said resistance means; third means responsive to said clock pulses for activating said resistance means in a predetermined sequence one at a time synchronously with the generation of information related to the desired value of the activated resistance means; and, fourth means comparing said first signals with said information for generating an error signal, the activated resistance means being responsive to said error signal.

8. The improvement of claim 7 wherein said second means comprises a shift register means for storing in binary format the desired value of each said resistance means, said shift register means being responsive to said clock pulses for generating said desired values in said predetermined order.

9. The improvement of claim 7 wherein each said resistance means includes: a field effect transistor having a source-drain circuit connected between its associated output tap and said means for summing, and a gate electrode; a capacitor having a first plate connected to said gate electrode and a second plate; switching means for selectively applying first and second voltages to said second plate; and, means responsive to said error signal for adjusting the voltage stored across said capacitor.

10. The improvement recited in claim 7 wherein said means for adjusting comprises: means responsive to said clock pulses for discharging the capacitors of all said resistance means; and, means responsive to said error signal for subsequently increasing the voltage stored across said capacitor.

11. The improvement of claim 7 wherein each said resistance means includes: an adjustable resistance having one end connected to its associated output tap and a second end; and an inverting and non-inverting amplifier responsive to said information, said amplifier being connected between said adjustable resistance second end and said means for summing.

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