High speed fluidic devices |
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| 申请号 | US7290270 | 申请日 | 1970-09-16 | 公开(公告)号 | US3825739A | 公开(公告)日 | 1974-07-23 |
| 申请人 | MARTIN MARIETTA CORP; | 发明人 | RICHARDS E; DEPPERMAN W; | ||||
| 摘要 | This invention relates to a binary accumulator stage consisting of pure fluid bistable and OR-NOR elements. The stage is joined with other similar stages to form a binary accumulator. Each stage sums an input value, a carry-in value supplied by a previous stage, and an addend value present in the addend register. An output signal and a carry-out signal are generated by each stage, the carry-out signal being fed to the succeeding stage as a carry-in signal. | ||||||
| 权利要求 | 1. A fluidic binary accumulator stage comprising: a. fluidic means for entering a carry-in signal from a previous stage; b. fluidic means for entering an input signal; c. fluidic carry logic means for summing said input signal and said carry-in signal into a first sum and for providing a partial carry-out signal; d. a fluidic addend register including a first fluidic memory means which contains an addend value; e. fluidic sum logic means for summing said first sum and said addend value into a second sum; f. a second fluidic memory means; g. a fluidic OR-NOR logic circuit means responsive to said second sum for setting said second memory means; h. means to receive an add signal for actuating said OR-NOR logic circuit means; i. a feed back circuit from said second memory means to said addend register for entering said second sum into said first memory means, said feedback circuit including fluidic gating means; j. means to receive a shift signal for actuating said gating means; and k. a fluidic carry-out logic circuit meanS responsive to said partial carry-out signal and an output of said addend register to provide a complete carry-out signal for a subsequent accumulator stage. 2. A fluidic binary accumulator stage comprising: a. fluidic means for entering a carry-in signal from a previous stage; b. fluidic means for entering an input signal; c. fluidic carry logic means for summing said input signal and said carry-in signal into a first sum and for providing a partial carry-out signal; d. a fluidic addend register including a first fluidic bistable flip-flop which contains an addend value; e. fluidic sum logic means for summing said first sum and said addend value into a second sum; f. a second fluidic bistable flip-flop; g. a fluidic OR-NOR logic circuit means responsive to said second sum for setting said second bistable flip-flop; h. means to receive an add signal for actuating said OR-NOR logic circuit means; i. a feedback circuit from said second flip-flop to said addend register for entering said second sum into said first bistable flip-flop, said feedback circuit including fluidic gating means; j. means to receive a shift signal for actuating said gating means; and k. a fluidic carry-out logic circuit means responsive to said partial carry-out signal and an output of said addend register to provide a complete carry-out signal for a subsequent accumulator stage. 3. A fluidic binary accumulator stage as defined in claim 2 in combination with at least one other accumulator stage of substantially identical construction thereby forming a multi-bit accumulator. 4. A fluidic binary accumulator stage as defined in claim 2, including a fluidic output stage coupled to said fluidic OR-NOR circuit means and responsive to its output. 5. A fluidic binary accumulator stage as defined in claim 4 in combination with at least one other accumulator stage of substantially identical construction thereby forming a multi-bit accumulator. 6. A fluidic binary accumulator stage as defined in claim 4, wherein said fluidic output stage is a third fluidic bistable flip-flop. 7. A fluidic binary accumulator stage as defined in claim 6 in combination with at least one other accumulator stage of substantially identical construction thereby forming a multi-bit accumulator. |
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