| Document | Document Title |
|---|---|
| US12088837B2 |
Weighted prediction in video coding
A video processing method includes generating, for a conversion between a current block of a video and a bitstream representation of the video, a motion vector for the current block; invoking a weighted prediction processing tool or a second processing tool in a mutually exclusive manner; and performing the conversion according to the invoking. The invoking of the second processing tool comprises refining the motion vector. |
| US12088836B2 |
Affine linear weighted intra prediction mode
A method for video decoding in a decoder is provided. Prediction information for a current block in a current picture is decoded. The prediction information indicates whether the current block is coded in MIP. Based on the prediction information indicating that the current block is coded in MIP, an MIP mode index is determined according to index information included in the prediction information. An intra prediction candidate mode for the current block is determined to be a Planar intra prediction mode based on the prediction information indicating that the current block is not coded in MIP. The current block is reconstructed according to (i) an MIP mode in a mode candidate list based on the prediction information indicating that the current block is coded in MIP and (ii) the Planar intra prediction mode based on the prediction information indicating that the current block is not coded in MIP. |
| US12088834B2 |
Selective use of virtual pipeline data units for intra block copy video coding
A method of visual media processing includes determining a size of a buffer to store reference samples for prediction in an intra block copy mode; and performing a conversion between a current video block of visual media data and a bitstream of the current video block, using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture. |
| US12088833B2 |
Signaling of number of merge candidates
Aspects of the disclosure provide a method and an apparatus including processing circuitry for video encoding. The processing circuitry determines a maximum number of geometric merge mode merge candidates, and generates maximum number of geometric merge mode candidates information based on a relation between the maximum number of geometric merge mode merge candidates and a maximum number of merge candidates. The processing circuitry generates a coded video bitstream including coding information. The coding information indicates that a geometric merge mode is enabled for a coding level higher than a picture level of a current picture and the maximum number of merge candidates satisfies a condition. The maximum number of geometric merge mode merge candidates is equal to the maximum number of merge candidates minus a value indicated by the maximum number of geometric merge mode candidates information. |
| US12088827B2 |
Image coding method, image decoding method, image coding apparatus, image decoding apparatus, and image coding and decoding apparatus
An image coding method of coding an image on a per coding unit basis, the method comprising: applying a frequency transform to luminance data and chrominance data of transform units in the coding unit including predetermined blocks each corresponding to one or more of the transform units; and coding the luminance data and the chrominance data to which the frequency transform has been applied to generate a bitstream in which the luminance data and the chrominance data are grouped on a per predetermined block basis. |
| US12088820B2 |
Decoder and corresponding methods to signal picture partitioning information for slices
A method of coding performed by a decoding device and a decoder are disclosed. The method comprises: obtaining a bitstream for a current picture; obtaining a quantity of tiles in a tile row of the current picture; obtaining a value of an address of a current slice, the current slice is comprised in the current picture; obtaining a value of a horizontal coordinate according to the value of the address of the current slice; parsing an indication value for a slice width from the bitsteam for the current picture, when a difference value between the quantity of tiles in the tile row of the current picture and the value of the horizontal coordinate is not equal to a first threshold. |
| US12088819B2 |
Method and apparatus for predicting motion information of picture block, encoder, and decoder
A method for predicting motion information of a picture block and a related product is provided. The method includes: determining a candidate motion information list of a current picture block, where the candidate motion information list includes at least one combined candidate motion information, one combined candidate motion information is obtained by weighting P candidate motion information by using corresponding weighting factors; determining target motion information in the candidate motion information list; and predicting motion information of the current picture block based on the target motion information. |
| US12088812B2 |
Image coding device and method
In relation to an in-loop filtering procedure described in the present document, a virtual boundary is defined so as to further increase the subjective/objective visual quality of a restored picture and the in-loop filtering procedure can be applied across the virtual boundary. The virtual boundary can include, for example, a discontinuous edge such as a 360-degree image, a VR image, or picture in picture (PIP). For example, the virtual boundary can be at a predetermined appointed position, and the existence and/or the position thereof can be signaled. Embodiments of the present document present a method for efficiently signaling virtual boundary-related information. |
| US12088811B2 |
Methods and systems for encoding pictures associated with video data
Several methods and systems for encoding pictures associated with video data are disclosed. In an embodiment, a method includes determining by a processing module, whether a picture is to be encoded based on at least one of a skip assessment associated with the picture and an encoding status of a pre-selected number of pictures preceding the picture in an encoding sequence. The method further includes encoding by the processing module, a plurality of rows of video data associated with the picture upon determining that the picture is to be encoded, wherein the plurality of rows are encoded based on a pre-selected maximum encoded picture size. |
| US12088810B2 |
Encoding method that encodes a first denominator for a luma weighting factor, transfer device, and decoding method
An encoding device includes a deriving unit and an encoding unit. The deriving unit is configured to derive a first reference value based on fixed point precision representing roughness of a weighting factor that is used for multiplying a reference image. The encoding unit is configured to encode a first difference value that is a difference value between the weighting factor and the first reference value and the fixed point precision. The weighting factor is included in a first range of predetermined bit precision having the first reference value at approximate center. The first difference value is in the predetermined range. |
| US12088809B2 |
Image encoding/decoding method and device, and recording medium in which bitstream is stored
Disclosed herein is an image decoding method. The method of decoding an image comprises obtaining prediction information and residual signal information for a current block from a bitstream and reconstructing, based on the obtained prediction information and the residual signal information, the current block, wherein the prediction information is obtained through entropy decoding, and wherein a context model used for the entropy decoding of the prediction information is determined based on a prediction mode of a neighboring block of the current block. |
| US12088807B2 |
United states method and apparatus for encoding video, and decoding method and apparatus
The present invention relates to a video encoding method and apparatus for setting and encoding quantization parameters, and to a video decoding method and apparatus for decoding and setting quantization parameters in a video encoding and decoding apparatus which uses blocks having various sizes and depths as encoding and decoding units. |
| US12088800B2 |
Method and apparatus for encoding/decoding video and method for transmitting bitstream
An image decoding method is disclosed. The image decoding method includes obtaining intra prediction mode information of a current block from a bitstream, determining an intra prediction mode of the current block based on the intra prediction mode information and an intra prediction mode of a neighboring block located around the current block, deriving a value of a first filter flag for use of filtering of an intra prediction reference sample of the current block based on coding parameters for the current block, selecting an interpolation filter to be used for intra prediction of the current block based on the first filter flag, and generating an intra prediction block of the current block using the selected interpolation filter. |
| US12088799B2 |
Encoder, a decoder and corresponding methods of intra prediction
A method of coding implemented by a decoding device, comprising: setting a value of candidate intra prediction mode of a current block to be a default value, wherein the current block is predicted using an intra prediction mode but not a Matrix-based Intra Prediction (MIP) mode and a neighboring block adjacent to the current block is used to derive the value of candidate intra prediction mode of the current block and is predicted using MIP mode; obtaining a value of the intra prediction mode of the current block according to the default value. |
| US12088795B2 |
Method and device for encoding/decoding image, and recording medium storing bit stream
An image encoding/decoding method and apparatus for predicting a second color component block using a first color component block are provided. An image decoding method of the present invention comprises deriving a prediction parameter using the first color component block, and predicting the second color component block using the derived prediction parameter. |
| US12088791B2 |
Encoder, decoder, encoding method, and decoding method
An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode. |
| US12088790B2 |
Subpicture signaling in video bitstreams
A method includes performing a conversion between a video comprising a video picture that includes one or more subpictures and a bitstream of the video according to a format rule. The format rule specifies that whether each of the one or more subpictures in the video picture includes a single slice is determined based on a constraint flag. |
| US12088787B2 |
Disallowing unused layers in multi-layer video bitstreams
A method of decoding is provided. The method includes receiving, by the video decoder, a video bitstream including a video parameter set (VPS) and a plurality of layers, where each layer is included in at least one output layer set (OLS) specified by the VPS; and decoding, by the video decoder, a picture from one of the plurality of layers. A method of encoding is also provided. The method of encoding includes generating, by the video encoder, a plurality of layers and a video parameter set (VPS) specifying one or more output layer sets (OLSs), wherein each layer from the plurality of layers is included in at least one of the OLSs specified by the VPS; encoding, by the video encoder, the plurality of layers and the VPS into a video bitstream; and storing, by the video encoder, the video bitstream for communication toward a video decoder. |
| US12088784B2 |
Thermal imaging camera and shutter operation state monitoring method thereof
A shutter operation state monitoring method performed in a thermal imaging camera includes, controlling a shutter of the thermal imaging camera to be closed, capturing a first thermal image, calculating a correction offset value for the first thermal image, controlling the shutter to be opened, capturing a second thermal image, applying the correction offset value to the second thermal image, measuring a sound with a microphone when controlling the shutter to be closed and/or when controlling the shutter to be opened, determining whether the measured sound matches an operation sound of the shutter, and outputting an alarm indicating malfunction of the shutter if the measured sound does not match the operation sound. |
| US12088783B2 |
Imaging apparatus and gain ratio acquisition method therefor
An object of the present invention is to reduce time required for calibration between gains in a level control circuit. The level control circuit performs, using any of first and second gains that differ from each other, level control of an analog signal output to a vertical signal line that corresponds to each column of a pixel array. An analog-digital converter converts the level-controlled analog signal into a digital signal. A test signal generating unit generates first and second test signals that differ from each other. A gain ratio acquiring unit simultaneously supplies one of the vertical signal lines with the first test signal and supplies another of the vertical signal lines with the second test signal to acquire a gain ratio between the first gain and the second gain of the level control circuit. |
| US12088778B2 |
Efficient multi-view coding using depth-map estimate and update
This disclosure is directed to coding a multi-view signal, which includes processing a list of plurality of motion vector candidates associated with a coding block of a current picture in a dependent view of the multi-view signal Such processing includes estimating a first motion vector based on a second motion vector associated with a reference block in a current picture of a reference view of the multi-view signal, the reference block corresponding to the coding block of the current picture in the dependent view. The first motion vector is added into the list, and an index is used that specifies at least one candidate from the list to be used for motion-compensated prediction. The coding block in the current picture is coded by performing the motion-compensated prediction based on the at least one candidate indicated by the index. |
| US12088775B2 |
Process for creating and for comparing color profiles
The present invention relates to a process for comparing a reference colour profile or the color space value of the reference color profile of an analogue reference pattern with a decorative-element-specific color profile or the color space value of the decorative-element-specific color profile of a digital or analogue decorative element. In the course of the process, a reference color profile is created by reading in and storing measurement data of at least one portion of an analogue reference pattern by means of a hyperspectral area measuring device. According to the invention, a decorative-element-specific color profile is created either from the digital data of a digital decorative element or using hyperspectral area measurement of at least one portion of an analogue decorative element. |
| US12088770B2 |
Display system, display method, and display program for displaying a content of electronic document
A display system including: a document content acquisition unit that acquires, on a basis of bibliographic information that includes storage location information indicating a storage location of each of a plurality of electronic documents to be displayed and is related to a bibliographic matter of each of the plurality of electronic documents, document content information indicating a content of at least one electronic document among the plurality of electronic documents stored in the storage location; and a display unit that displays, on a basis of correspondence information in which each of a plurality of items set in advance is associated with a description position in the at least one electronic document, and the document content information, content indicated by the document content information corresponding to the description position in the at least one electronic document, on a user terminal of a user for each item. |
| US12088766B2 |
Reading apparatus with a displaceable cover member that covers a feed port
A reading apparatus includes a reading part that reads information of a document, a housing that accommodates the reading part, a document feeding port feed the document therethrough, and a cover member that is disposed on the housing and is displaceable to an open position at which the document feeding port is opened and a closed position at which the document feeding port is closed, wherein the cover member includes an opening and closing end portion on an upstream side in a transport direction of the document, the housing includes a facing portion that is a portion facing a bottom surface of the opening and closing end portion when the cover member is at the closed position, and a gap through which the document passes is formed between a part or the whole of the bottom surface of the opening and closing end portion and the facing portion. |
| US12088764B2 |
Image processing apparatus and job output method
An image processing apparatus includes a controller, a display, and a job executor that executes a job at a predetermined setting based on setting information for job execution sent from a terminal device, wherein the controller starts up an application in response to a startup instruction, generates apparatus information including identification information on the image processing apparatus based on the started application, displays the generated apparatus information on the display for the terminal device, and controls the job executor to output the job at a predetermined setting based on setting information for job execution sent from the terminal device having read the displayed apparatus information, and terminates the application when a termination determination time has elapsed after startup of the application. |
| US12088763B2 |
Recording device including medium tray having a first and second region
A recording device includes a recording unit configured to perform recording on media, a main body provided with the recording unit, and a medium accommodation unit configured to be attached to and detached from the main body and configured to accommodate the media, wherein the medium accommodation unit includes a first region configured to accommodate a pre-recording medium before being subjected to recording by the recording unit, and a second region configured to accommodate a recorded medium after being subjected to the recording by the recording unit. |
| US12088761B2 |
Voice and speech recognition for call center feedback and quality assurance
A computer-implemented method for providing an objective evaluation to a customer service representative regarding his performance during an interaction with a customer may include receiving a digitized data stream corresponding to a spoken conversation between a customer and a representative; converting the data stream to a text stream; generating a representative transcript that includes the words from the text stream that are spoken by the representative; comparing the representative transcript with a plurality of positive words and a plurality of negative words; and generating a score that varies according to the occurrence of each word spoken by the representative that matches one of the positive words, and/or the occurrence of each word spoken by the representative that matches one of the negative words. Tone of voice, as well as response time, during the interaction may also be monitored and analyzed to adjust the score, or generate a separate score. |
| US12088758B2 |
Locally recording media based on a disconnection from a multi-participant communication
A disconnection of a client device is disconnected during a multi-participant communication, such as a call or a conference. An indication of the disconnection is transmitted to the client device to cause an agent at the client device to record media locally at the client device. The media recorded by the agent at the client device based on the indication of the disconnection is later received and included within a recording of the communication. For example, a gap of the recording in which the disconnection occurred may be identified, such as by performing a comparison of media within the recording to identify a start time of the gap and an end time of the gap. The media is then inserted within a portion of the recording of the multi-participant communication corresponding to the gap. |
| US12088756B1 |
Dynamic direction of incoming calls
Apparatus and methods concerning call routing are disclosed. In an example embodiment, a call alert message, indicative of the call answer options, is communicated from a data-communications server to the communication device, determined in response to receiving an incoming call for a communication device at the server. A selected option is received from the communication device. In response to the selected option indicating the first call answer option, the call is routed to the communication device as a call via a data network or in response to the selected option indicating the second call answer option, the call is routed to the communication device via a PSTN. |
| US12088754B2 |
Method for controlling mobile terminal, and mobile terminal
The present disclosure provides a method and an apparatus for controlling a mobile terminal, a mobile terminal and a storage medium. The method is applied to the mobile terminal with a touch screen and includes: detecting whether the mobile terminal is in a folding process of switching from an unfolded posture to a folded posture; and disabling, in response to detecting a touch event acting on the touch screen during the folding process, a response to the touch event. |
| US12088749B2 |
Display-module assembly and electronic device
A display-module assembly (100) and an electronic device (1000) are described. The display-module assembly (100) includes: a cover plate (10) including a window portion (101) and a non-window portion (102) surrounding the window portion (101); a display module (30) disposed at the inner side of the cover plate (10); a bonding layer (20) including a first bonding portion (201) and a second bonding portions (202). The first bonding portion (201) is adhered between the window portion (101) and the display module (30). An ink layer (40) is provided on the surface of the non-window portion (102) facing the display module (30). The second bonding portion (202) is adhered between the ink layer (40) and the display module (30). |
| US12088748B2 |
Handheld electronic device
A portable electronic device includes a housing, a sensor array including a first camera module having a first field of view, a second camera module having a second field of view different from the first field of view, and a light source, and a rear cover formed from a glass material and defining a raised sensor array region positioned over the sensor array. The raised sensor array region defines a first hole extending through the rear cover and positioned proximate a first corner region of the raised sensor array region, and a second hole extending through the rear cover and positioned proximate a second corner region diagonal from the first corner region. The first camera module includes a first camera housing defining a recess at a corner of the first camera housing, and the second camera module includes a second camera housing extending into the recess. |
| US12088746B2 |
Cell phone frame and method for manufacturing the same
A cell phone frame, and a method for manufacturing the same, includes a composite plate. The composite plate encloses an accommodation space for accommodating the cell phone. The composite plate includes a first plate and a second plate, a first side surface of the first plate having striations. The first side surface of the second plate and the first side surface of the first plate are rolled to connect, and the striations of which adjacent ones have a pitch of 0.005 mm to 0.03 mm account for more than 90% of all the striations. |
| US12088738B2 |
Custom rules for global certificate issuance
Techniques are described for enabling users of a certificate management service to create certificate issuance policies that can be applied to certificate issuance requests across both public and private certificate authorities (CAs) and other certificate-related services. According to embodiments described herein, a certificate issuance policy includes one or more certificate issuance rules to be applied to requests associated with one or more specified user accounts or roles for certificate-related resources (e.g., public certificates, private certificates, etc.). The application of a certificate issuance rule can be conditioned on a particular request context (e.g., based on a user account or role associated with a request, a type of certificate requested, a subject name identified in the request, etc.) and can specify a wide range of actions to be performed on requests matching a rule (e.g., allowing or denying a request, modifying one or more parameters of the request, etc.). |
| US12088735B1 |
Apparatus, systems, and methods relying on non-flashable circuitry for improving security on public or private networks
A hardware unit relies on non-flashable circuitry for improving security on a public or private network. The hardware unit can be added to a network without substantial modifications to the other devices already connected to the network. The hardware unit detects and blocks or drops data packets or frames that contain an instruction of a known file-sharing protocol other than a reading instruction that are not digitally signed by a recognized source. Thus, a cyber attack may be prevented instantaneously by what it attempts to do, typically the creation, insertion, deletion, update, renaming, or writing of files to compromise code or data. |
| US12088733B1 |
Systems and methods for privacy preserving distributed ledger consensus
A method includes receiving a consensus agreement rule (“CAR”) comprising identities of a first party and second party; receiving a first SignedData message comprising first content and a first digital signature; creating a second SignedData message comprising a second digital signature of the second party on a hash of the second content and an acceptance indication; verifying, based on the acceptance indication and based on the identities on the CAR matching the identities on the signatures, that the second party accepted the terms of the agreement; and transmitting the second SignedData message to a trusted party for posting to a distributed ledger, wherein the terms of the agreement are kept private while the second SignedData message is posted to the distributed ledger, and wherein the terms of the agreement are formatted as a smart contract whose execution causes a transfer of value in response to a fulfillment of a condition. |
| US12088732B2 |
Automated tamper detection of meter configuration parameters
A method includes storing, at a head-end system, an indication of initial configuration parameters of a configurable resource meter. The method also includes requesting, by the head-end system, a report indicating updated configuration parameters from the configurable resource meter and receiving, at the head-end system, the report indicating the updated configuration parameters of the configurable resource meter. Additionally, the method includes comparing an indication of the updated configuration parameters to the indication of the initial configuration parameters. Further, the method includes determining a potential compromise of the configurable resource meter when the indication of the updated configuration parameters is different from the indication of the initial configuration parameters. |
| US12088730B2 |
Tracking provenance of digital data
A data authentication system stores a token representing data distributed from a data source to a data recipient, allowing the data recipient to authenticate the data. The data authentication system receives, from a data source, a first token that represents a digital entity distributed by the data source to a data recipient. A representation of the first token is sent for storage on a blockchain. A request is received from a data recipient to authenticate the digital entity, where the request includes a second token that represents the digital entity as distributed to the data recipient. The data authentication system authenticates the second token against the stored first token to verify that the data recipient received authentic data. |
| US12088724B2 |
Method for proving original of data, and apparatus therefor
A method according to an embodiment of the present disclosure includes obtaining proof data including a photographed image and a challenge code for proving original of the image, generating hash data by using the proof data, generating signature data for the hash data, transmitting the proof data, the hash data, and the signature data to a server, and receiving an access path to an original verification result of the proof data from the server. |
| US12088721B2 |
Dongle for ciphering data
A dongle for ciphering, receiving and transmitting data to and from an external device is provided. The dongle includes a user interface configured to receive authentication data to confirm an identity of a user. The dongle is disabled for ciphering data unless an authorised user is identified. A data transfer channel is configured to couple the dongle to the external device to receive and transmit user data between the dongle and the external device. A hardware encryption engine is configured to perform a ciphering transformation on user data received from the external device. The dongle is configured to perform a return transmission to return the user data that has been transformed to the external device via the data transfer channel in real-time using a single data transfer channel without storage of the user data on the dongle. |
| US12088719B2 |
Method and system for incremental training of machine learning models on edge devices
A method and system for incremental training of machine learning (ML) models on edge devices, is disclosed. A base version of ML model is received by a first device of the peer to peer network of devices. The base version of the ML model is incremental trained in real-time by updating weights associated with the parameters of the ML model during a predetermined window of time. The ML model are devoid of an underlying event data used to generate the incremental version of the ML model. The updated weights associated with parameters of the incrementally trained ML model and/or the respective parameters are shared by each edge device with other edge devices. The edge devices update their respective ML models based on the received updated weights and/or parameters upon subsequent events at the edge devices and the updated version of the ML models are further incrementally trained. |
| US12088717B2 |
Systems and methods for AI/machine learning-based blockchain validation and remediation
A system described herein may utilize artificial intelligence/machine learning (“AI/ML”) or other suitable techniques to automatically identify blocks added to or proposed to be added to a blockchain, with conflicting and/or otherwise incompatible information, and to automatically remediate the blockchain based on the identified conflict and/or incompatibility. The model may associate different types of conflicts and/or incompatibilities with different types of remedial measures. The remedial measures may include the rejection of a proposed block, recording a new block that takes precedence or priority over a previously recorded block, or other suitable remedial measures. |
| US12088716B2 |
Monitoring a manufacturing process
The present disclosure relates to monitoring processes. A processor creates a numerical representation of a nominal operation of the process. The processor then encrypts the numerical representation using homomorphic encryption to determine an encrypted numerical representation that blocks access to the numerical representation but allows calculations on the numerical representations. The processor proceeds by creating smart contracts on a blockchain platform using the encrypted numerical representation as a first input to the calculations of the smart contract. Next, the processor attempts execution of the smart contract using the current operation of the process as a second input to the calculations of the smart contract. The execution of the smart contract generates an output result by performing the calculations on the encrypted numerical representations. Based on the output of the execution of the smart contract, the processor finally determines that the current operation is outside the nominal operation. |
| US12088714B2 |
Image acquisition apparatus, server, and encryption and decryption methods
The application provides an image acquisition apparatus, a server, and encryption and decryption methods, and relates to the field of data processing. The image acquisition apparatus includes: an image acquisition device including an encryption processor and a data interface provided in the image acquisition device, wherein the encryption processor is configured to encrypt, by using a stored first key, image data acquired by the image acquisition device to obtain image ciphertext data; the data interface is configured to obtain the image ciphertext data and output the image ciphertext data to a terminal device. With the technical solution of the application, security of the image data can be ensured. |
| US12088713B2 |
Dynamic selection and calibration of ciphers based on network and resource constraints
The disclosure provides an approach for cryptographic agility. Embodiments include receiving a request from an application for a cryptographic operation, wherein the request is associated with a computing device. Embodiments include determining one or more resource constraints related to the computing device. Embodiments include selecting, based on the one or more resource constraints, a cryptographic technique from a plurality of cryptographic techniques associated with indications of resource requirements. Embodiments include performing the cryptographic operation using the cryptographic technique. Embodiments include providing a response to the application based on performing the cryptographic operation. |
| US12088710B2 |
Key rotation for sensitive data tokenization
This document describes techniques for rotating keys used to tokenize data stored in a streaming data store where data is stored for a maximum time [W]. In some embodiments, a data layer of such a data store can encrypt arriving original data values twice. The original data value is first encrypted with a first key, producing a first token. The original data value is encrypted with a second key, producing a second token. Each encrypted token can be stored separately in the data store. A field may be associated with two database columns, one holding the value encrypted with the first key and the second holding the value encrypted with the second key. Keys are rotated after time [K], which is at least equal to and preferably longer than [W]. Rotation can involve discarding the older key and generating a new key so that two keys are still used. |
| US12088709B2 |
Information processing apparatus, information processing method, and storage system
An information processing apparatus or method that can share secret information by plural holders. The apparatus or method execute a control to: calculate or generate an encryption key and k key symbols from k random numbers; encrypt k information symbols using the encryption key to output k encrypted symbols; output any one of the k encrypted symbols and the k key symbols as k message symbols; output a flag indicating which one of the k encrypted symbols and the k key symbols are the k message symbols; encode the k message symbols with a maximum distance separable code to output n code symbols; and-output n code blocks from the n code symbols and the flag, wherein k is a positive integer of one or more, and n is a positive integer larger than k. |
| US12088705B2 |
Secure distribution of entropy
Techniques are disclosed for securely distributing entropy in a distributed environment. The entropy that is distributed may be quantum entropy that is generated by a quantum entropy generator or source. The true random entropy generated by a trusted entropy generator can be communicated securely among computer systems or hosts using secure communication channels that are set up using a portion of the entropy. The distribution techniques enable computer systems and hosts, which would otherwise not have access to such entropy generated by the trusted entropy source, to have access to the entropy. |
| US12088703B2 |
Method and apparatus for control action based on software defined networking associated with quantum key distribution network management in quantum key distribution network
The present disclosure relates to a method and apparatus for control action based on software-defined networking associated with quantum key distribution network (QKDN) management in a quantum key distribution network. A method for performing a control action associated with QKDN management in a QKDN according to an embodiment of the present disclosure may include: receiving, by a first control entity, control action information from a QKDN manager; determining, by the first control entity, a target of the control action based on the control action information; classifying, by the first control entity, the control action sequentially as one of a routing or rerouting-related control action, a provisioning-related control action, a protection or recovery-related control action, and a charge-related control action based on the target of the control action; and transmitting, by the first control entity, information for performing the control action for a target associated with the classified control action. |
| US12088690B2 |
Method for robust communication between nodes that are adjacent at layer 3
A method for communication between nodes, where the method includes: constructing, by a first Layer 3 node, a link local control frame; adding, by the first Layer 3 node, a destination group Media Access Control (MAC) address to the link local control frame, wherein the destination group MAC address is outside a block of destination group MAC addresses assigned for Ethernet bridging purposes; and transmitting, by the first Layer 3 node, the link local control frame to a second Layer 3 node. |
| US12088688B2 |
Packet processing method, network device, and related device
In a packet processing method, a network device receives a packet of an application running in a server connected to the network device. The network device separates data of the application from the packet, and writes the data of the application into a memory allocated in the server to the application. |
| US12088685B2 |
Platform for multi-stream sampling and visualization
A stream tool is disclosed that allows a user to seamlessly connect with the different data streams, regardless of the streams' transmission platforms or communication protocols, in order to visually see a representation of the type of data that the data streams are transmitting. A user may specify a particular data stream and provide corresponding connection details. A collection of abstracted software functions enable interaction with the different stream platforms and protocols. Using these abstracted functions, a stream-processing service accesses a requested data stream and samples its data events for either sample timeframe or up to a threshold number of data events. The sampled data events are parsed and visually presented to the user in an easy-to-understand format. The user may then inspect the data stream's data for use in developing robust applications that may integrate and use such data. |
| US12088682B2 |
Digital media distribution frequency management systems and methods for reducing digital media across digital networks and platforms with pixel based requests
Digital media distribution frequency management systems and methods are disclosed for reducing digital media across digital networks and platforms. A set of impression identifiers (IDs) is determined for a digital media asset as displayed on graphic user interfaces (GUIs) of open web digital channel(s). An identifier of a user is determined as well as an impression count of the user based on the set of impression IDs and an open web ID of the user. A pixel based request, comprising the identifier of the user and instructions to embed a pixel on a GUI of the online based digital media content distribution platform, is pushed to an application programming interface (API) of an online based digital media content distribution platform, which in turn is configured to suppress or allow the digital media asset to be displayed based on a pixel type determined from the impression count of the user. |
| US12088664B2 |
Data distribution method, recording medium, and data distribution system
In a data distribution method according to the disclosure, first authentication servers and a first data server belong to a first group, and second authentication servers and a second data server belong to a second group different from the first group. A first authentication server obtains first transaction data that includes a data obtaining request indicating a request for obtaining or referring to data pertaining to an apparatus, and records a block including the first transaction data into its distributed ledger belonging to the first group. A second authentication server obtains the first transaction data, and records the block including the first transaction data into a distributed ledger belonging to the second group. The first authentication server causes the first data server to transfer the data pertaining to the apparatus held therein to the second data server or to make such data available for reference by the second data server. |
| US12088663B2 |
Methods for determining second screen content based on data events at primary content output device
Aspects as described herein are directed to providing an enhanced user experience for consuming content on a computing device. Secondary computing devices, such as handheld smartphones and tablet-style computers, may be identified by a primary computing device, such as a set-top box. The secondary computing devices may be configured to receive actionable instructions from the primary computing device. An actionable event associated with content being outputted to a user via the primary computing device may be determined and an actionable instruction may be transmitted to the secondary computing device in response to the determined actionable event. |
| US12088659B2 |
Method and device for storing and distributing file content in mc network
A method, performed by a mission critical data (MCData) message store entity, of depositing MCData for file distribution (FD). the method includes receiving a MCData deposit an object request message or a MCData retrieve file to store locally request message, wherein the MCData deposit an object request message comprises information regarding the object and the MCData retrieve file to store locally request message comprises information regarding object identifier, based on the MCData deposit an object request message or the MCData retrieve file to store locally request message, retrieving uniform resource locator (URL) of file content in a MCData content server, based on a result of the retrieving, fetching the file content from the MCData content server, storing the file content into a MCData user's storage area in the MCData message store entity, and updating the object with the URL referencing the file content stored in the MCData user's storage area. |
| US12088658B2 |
Contextual remote control user interface
A mobile device is coupled to a computer system configured to access media content sources and play media content items provided thereby on a media device. The mobile device receives a first control specification that includes a plurality of first information items each associated with one of the media content sources and a first action definition. The first information items are concurrently displayed on a remote control user interface of the mobile device. In accordance with a selection of one of the first information items corresponding to a first content source, the mobile device transmits a command of a first action definition corresponding to the selected first information item to the computer system, and receives a second control specification that includes a plurality of second information items. Each second information item is associated with a respective content item provided by the first content source and a second action definition. |
| US12088652B2 |
Deadline signaling for streaming of media data
A client device includes a memory comprising a buffer for buffering data having real-time constraints and a hardware-based processor comprising digital logic circuitry. The processor is configured to execute a real-time application configured to determine times during which the data will be available for download, determine a time at which the data is needed to prevent a buffer underrun for the buffer, and when the data is available, send a request for the data and deadline information representative of the time at which the data is needed to avoid the buffer underrun. In this manner, a sending device can prioritize delivery of the requested data to prevent the buffer underrun for the client device. |
| US12088647B1 |
Content and device agnostic online experience sharing with in-page control passing
A system for providing a shared online experience session to a first user device and a second user device. The system includes a processor, a cloud browser, and an encoder. The processor is configured to (a) receive, from the first user device, data identifying an online interaction where the first user device is in navigational control of the content within the shared online experience session; (b) execute, using the cloud browser, the online interaction to generate frame and raw data; (c) encode, using the encoder, the frame and raw data to produce an encoded stream of frames; and (d) contemporaneously provide the encoded stream of frames to the first user device and the second user device. |
| US12088643B2 |
Videoconferencing with reduced quality interruptions upon participant join
In an embodiment, a computing system can include one or more processors and one or more non-transitory computer-readable media that store instructions that, when executed by the one or more processors, cause the computing system to perform operations. The operations can include: receiving an internal encoder state of an encoder running on a first computing device being used to participate in a video conference currently in progress; receiving data indicative of a second computing device being used to join the video conference; compressing, based at least in part on receipt of the data, the internal encoder state to generate a compressed internal encoder state of the encoder; and/or transmitting the compressed internal encoder state to the second computing device to synchronize the internal encoder state of the encoder running on the first computing device with an internal decoder state of a decoder running on the second computing device. |
| US12088642B2 |
Process and computer for establishing data transmission
A process and a computer establish a data transfer from a provider (1, 2) that provides data to a consumer (9) that uses the data. A consumer (9) transmits a request message (probe) for requested data to a communications agent (5). In response, the communications agent (5) adds an entry for the request message (probe) to a requests list (AL). Subsequently, a provider (1, 2) transmits a registration message (Hello) to the communications agent (5). The communications agent (5) searches the requests list (AL) for an entry for a request message (probe) that matches the received registration message (Hello). If a matching entry is found in the requests list (AL), the communications agent (5) initiates a data transfer from the provider (1, 2) to the consumer (9). |
| US12088629B2 |
Securing network devices against network vulnerabilities
A method including transmitting, by a network device to a security device, an initial security instruction set including a plurality of initial security instructions; transmitting, by the network device to the security device based on transmitting the initial security instruction set, an event signal associated with the security device carrying out a network-facing operation; transmitting, by the security device to the network device based on receiving the event signal, a security instruction associated with the security device carrying out the network-facing operation, the security instruction being from among the plurality of initial security instructions; translating, by the network device, the security instruction into a host instruction to be executed by the network device; and receiving, by the security device from the network device based on transmitting the security instruction, communication information to enable the security device to carry out the network-facing operation is disclosed. Various other aspects are contemplated. |
| US12088626B2 |
Visualizing firewall-permitted network paths for assessing security of network configuration
A computer-implemented method of generating in a display a dynamic accessibility diagram representing a firewall configuration of a firewall in a computer network. A computer generates in the display a pair of concentric rings representing the firewall, including outer and inner concentric rings each having segments respectively representing remote address ranges and local address ranges of the ACL rules. Selection of a segment causes generation of an accessibility curve between the selected segment and a pairing segment, thereby graphically representing accessibility between the corresponding remote and local address ranges. |
| US12088622B2 |
Method and apparatus for defending against cyber attacks, receiving device and computer storage medium
Embodiments of the present disclosure provide a method and system for defending against cyber-attacks, and a computer storage medium. An apparatus for defending against cyber-attacks randomly generates a new keyword. The apparatus for defending against cyber-attacks transmits the new keyword to a transmitting device and a receiving device, respectively. The receiving device updates a keyword set of the receiving device to include the new keyword, acquires a keyword carried in a communication message transmitted by the transmitting device, and determines whether the communication message is a cyber-attack message according to the keyword carried and the keyword set. The receiving device discards the communication message in response to the communication message being determined to be a cyber-attack message. |
| US12088618B2 |
Methods and systems for asset risk determination and utilization for threat mitigation
Disclosed are methods and systems for assessing system risks associated with one or more assets coupled to a network and mitigating against said system risks. According to one implementation, a method for assessing a system risk comprises receiving network data associated with a first asset communicatively coupled to a network, quantifying the network data, and generating a risk parameter using the quantified network data and vulnerability data associated with the network. The method further comprises determining, based on the risk parameter that a security risk of a first asset of the network is higher than the security risk of a second asset of the network. Upon this determining, the method initiates remediation operations that first secure the first asset on the network against a security breach to the network. |
| US12088617B1 |
Network monitor with a homodyne detector for early identification of network attacks
A system has a firewall ingress node carrying network traffic. An attack injector creates a network attack flow on the firewall ingress node and thereby forms with the network traffic a composite firewall input signal on the firewall ingress node. A firewall egress node carries a response signal corresponding to the composite firewall input signal. A network monitor is connected to the firewall ingress node and the firewall egress node. The network monitor includes a homodyne detector to multiply the response signal by an oscillating driver signal to form a product that is integrated over time to form a homodyne detector response signal that is larger when the homodyne detector response signal has some component with the same frequency as the oscillating driver signal. |
| US12088616B2 |
Deep cyber vulnerability mitigation system
A method, system, or apparatus for mitigating computer and network security deficiencies is provided in which, the method, system, or apparatus scans computer system components for finding a vulnerability, generates a Vulnerability Priority Scoring System (VPSS) score for the vulnerability based on the vulnerability, develops a vulnerability mitigation policy based on a system state comprising the VPSS score, wherein the vulnerability mitigation policy provides a best action for mitigating the vulnerability selected among one or more trained possible actions by a deep neural network, and performs the vulnerability mitigation policy based on the best action. Other aspects, embodiments, and features are also claimed and described. |
| US12088613B2 |
Machine learning powered authentication challenges
Systems and methods are disclosed for automatically predicting a risk score of a user login attempt by receiving a user login attempt and generating a login feature vector associated with the user login attempt. The systems and methods further train a machine learning technique to establish a relationship between the login feature vector and the risk score. The trained machine learning technique is applied to new user login attempts to predict a risk score associated with the login attempt and issue an authentication challenge to the user if the risk score exceeds a predetermined threshold value. |
| US12088608B2 |
Methods and apparatus to analyze telemetry data of a network device for malicious activity
Methods, apparatus, systems and articles of manufacture are disclosed to analyze telemetry data of a network device for malicious activity. An example apparatus includes an interface to obtain first telemetry data, a rules generator to, using the first telemetry data, generate a global block list using a machine learning model, the machine learning model generated based on a device specific block list and a device specific allow list, and a model manager to transmit the global block list to a gateway, the gateway to facilitate on-path classification of second telemetry data. |
| US12088607B2 |
Endpoint-assisted inspection of encrypted network traffic
In one embodiment, a traffic inspection service executed by an intermediary device obtains, from a monitoring agent executed by an endpoint device, keying information for an encrypted traffic session between the endpoint device and a remote entity. The traffic inspection service provides a notification to the monitoring agent that acknowledges receipt of the keying information. The traffic inspection service uses the keying information to decrypt encrypted traffic from the encrypted traffic session. The traffic inspection service applies a policy to the encrypted traffic session between the endpoint device and the remote entity, based on the decrypted traffic from the session. |
| US12088603B2 |
Multi-computer system for comprehensive threat detection and mitigation
Arrangements for comprehensive threat mitigation are provided. In some aspects, an indication of threat or potential threat may be received from an external entity. In some examples, the threat may include a cybersecurity threat. In response to receiving the indication of threat, identifying data associated with the external entity may be extracted from the indication and used to retrieve pre-stored customizations associated with the desired mitigating actions of the external entity. The one or more mitigating actions may be identified and instructions to execute the one or more mitigating actions may be generated and transmitted to one or more computing devices for execution. |
| US12088600B1 |
Machine learning system for detecting anomalies in hunt data
An anomaly detection system is disclosed capable of reporting anomalous processes or hosts in a computer network using machine learning models trained using unsupervised training techniques. In embodiments, the system assigns observed processes to a set of process categories based on the file system path of the program executed by the process. The system extracts a feature vector for each process or host from the observation records and applies the machine learning models to the feature vectors to determine an outlier metric each process or host. The processes or hosts with the highest outlier metrics are reported as detected anomalies to be further examined by security analysts. In embodiments, the machine learnings models may be periodically retrained based on new observation records using unsupervised machine learning techniques. Accordingly, the system allows the models to learn from newly observed data without requiring the new data to be manually labeled by humans. |
| US12088595B2 |
Entity authentication for pre-authenticated links
Techniques for increasing security for pre-authenticated links are disclosed herein. Computing systems that generate pre-authenticated links are configured to assign an entity identifier to pre-authenticated links to specify an entity permitted to access respective data through the pre-authenticated link. When activating a respective pre-authenticated link, an entity attaches an entity token to the request to prove an identity of the requesting entity. If the identity from the entity token matches the entity identifier, the computing system may grant access to the respective data. |
| US12088589B2 |
Method, system, and computer program product for controlling access in a network of servers
Provided is a method for controlling access in a network of servers, which may include generating a set of nodes including a node for each account of each server. For each respective node, at least one other node of the set of nodes having credential-free access to the respective node may be determined. For each respective node, an edge connecting the respective node to each of the other node(s) of the set of nodes having credential-free access may be generated. The set of nodes and edges may collectively define a graph. For at least a first node, second nodes of the set of nodes that have indirect access to the first node(s) via at least one of the other node(s) having credential-free access to the first node(s) may be determined based on the graph. A system and computer program product are also disclosed. |
| US12088586B2 |
Biometric validation process utilizing access device and location determination
A first biometric sample of a user is received by an access device from a user device. First biometric information is generated in an obscured format, based on the first biometric sample. A plurality of biometric information is received in an obscured format. The plurality of biometric information corresponds to a plurality of users, and was obtained from biometric samples of the plurality of users. The first biometric information in the obscured format is compared to the plurality of biometric information in the obscured format, and a match result is generated based on the comparing. The match result is provided to a server computer. Based on the match result, information indicating that one of the plurality of users that is associated with one of the plurality of biometric information is the user associated with the first biometric information is received. |
| US12088585B2 |
Voice skill session lifetime management
Disclosed are various aspects of voice skill session lifetime management. In some examples, a session extension request is received. The session extension request extends a voice skill session of a voice-activated device. A personal client device is identified based on the session extension request. A command to emit an ultrasonic pulse is transmitted to the personal client device. |
| US12088584B2 |
Authentication token management for multiple processes and representational state transfer clients
Embodiments for processing authentication tokens in a system with multiple Representational State Transfer (REST) servers and clients. An intelligence process for multiple processes or multiple REST clients in an OS effectively communicates with multiple REST servers and proactively manages each server's authentication token. A shared library is loaded into a process that uses shared memory to manage the generation and expiry of a token and to communicate with a supported REST server through a single function call. The REST Authentication token will be generated for each REST server and stored in the shared memory which will be reused across multiple processes that use the library. The REST token will be validated for each function call. |
| US12088582B2 |
Secure access via remote browser isolation
Techniques to provide secure access to a service via an unmanaged device are disclosed. In various embodiments, a request from an unmanaged device to access a service is received via a communication interface. A user associated with the request is authenticated at least in part by prompting the user to use a managed device associated with the user to interact with data displayed at the unmanaged device. Access to the service is provided via the unmanaged device at least in part via a virtual browser instance running on a secure node and configured to access the service on behalf of the user and stream data associated with the service to the unmanaged device. |
| US12088581B2 |
Track activities of components in endpoints having secure memory devices via identity validation
A security server to validate identity data of computing devices having secure memory devices and track activities of components in the computing devices. The server system is configured to store data representative of a unique device secret sealed in the memory device. The server system can generate a first cryptographic key independently from the memory device generating a second cryptographic key. The memory device uses the second cryptographic key to generate identity data including a message and a verification code generated via cryptographic operations combining the message and the second cryptographic key. The server system can use the first cryptographic key to determine whether the verification code is valid for the message. If so, the security server can generate an activity record associating the activity of the computing device with identifications of respective components of the computing device confirmed via validation of the identity data. |
| US12088579B2 |
Secure account login and authentication
Systems, methods, and devices are described for secure account login and authentication. A set of key options including a correct key option and information indicative of a hash value are received from an authentication server. A user is prompted to select one of the set of key options. The key option selected by the user is received. A subset of PIN elements of a user-registered PIN to be input by the user is identified based on the hash value. The user is prompted to enter the subset of PIN elements. The subset of PIN elements entered by the user are received. An encoded PIN is generated based on the key option selected by the user and the subset of PIN elements entered by the user. The encoded PIN is transmitted to the authentication client that is configured to make an authentication decision based on the encoded PIN. |
| US12088576B2 |
System, method, and computer program product for managing computational cluster access to multiple domains
A computer implemented method for managing computational cluster access to multiple domains includes generating, using a ticket-based computer network authentication protocol, a primary set of keys based on remote system access credentials for a primary domain and a secondary set of keys based on remote system access credentials for a secondary domain. The method includes merging the primary set of keys with the secondary set of keys to form a merged set of keys. The method further includes activating a system daemon to provide access to the primary domain and the secondary domain by a computational cluster based on the merged set of keys. The method further includes connecting, using the ticket-based computer network authentication protocol via the system daemon, a remote computing device of the primary domain and a remote computing device of the secondary domain to the computational cluster. |
| US12088573B2 |
System and method for securely changing network configuration settings to multiplexers in an industrial control system
A secure control system includes a network of multiplexers that control end/field devices of an infrastructure system, such as an electric power grid. The multiplexers have a default secure lockdown state that prevents remote access to data on the multiplexers and prevents modification of software or firmware of the multiplexer. One or more of the multiplexers include a physical authentication device that confirms the physical proximity of a trusted individual when remote access is requested. A user accesses the network and one of the multiplexers remotely by way of login credentials. The trusted individual confirms the identity of the remote user and operates the physical authentication device connected with and in proximity to that multiplexer, thereby confirming that the remote user can be trusted to access data and reconfigure the multiplexers. The multiplexer connected with the physical authentication device generates a token that is passed to each of the multiplexers that the remote user needs access to. The token may specify a time period, after which, the multiplexers will reenter secure lockdown mode. |
| US12088571B2 |
System and methods of determining and managing probes in a multi-hop network
The present application describes a method including one or more steps. One step of the method includes receiving, at a gateway including an encrypted pathway, traffic from a third party originating outside a multi-hop network intended for a client inside the network. Another step of the method includes determining, using a trained machine learning model, a probe of the received traffic attempting to obtain confidential information about the multi-hop network. Yet another step of the method includes flagging the third party based on determined probe. |
| US12088569B1 |
Protocol free encrypting device
The present invention provides an encrypting device including an encryption unit and a communications unit. Paired encrypting devices allow for communication of trusted data between trusted devices over an untrusted network. Data received by the encryption unit is encrypted and provided with a connectionless header for delivery to the communications unit. Data received by the communications units is provided with a complex header for delivery to the paired encrypting device. The encrypting devices may be implemented in hardware or may be virtualized on a server or a plurality of severs. Arrangement of the encrypting devices in a hub-and-spoke topology allows for communication amongst a plurality of trusted devices. The encrypting devices can be used to covert commercially available equipment suitable for high assurance environments. |
| US12088568B2 |
Systems and methods for secure key service
Systems and methods for providing a secure custodial service for managing a digital asset. The method comprises receiving a first value for use in decrypting at least one attribute value, receiving the at least one attribute value in encrypted form, and storing, on at least one storage device, the first value and the at least one attributed value in encrypted form, wherein at least one attribute value has been encrypted using a second value and a public key associated with secure hardware, and the second value corresponds to the first value. |
| US12088566B2 |
User inviting method and apparatus, computer device, and computer-readable storage medium
A user inviting method includes: obtaining a user identifier of a current login user, in response to a trigger operation for a target invitation link corresponding to a target two-dimensional code, the target two-dimensional code being encrypted by using a public key and used for indicating jump to a target invitation page; accessing the target invitation link based on the user identifier, and obtaining a private key corresponding to the public key in response to that the user identifier is consistent with a target user identifier corresponding to the target invitation link; decrypting the target two-dimensional code by using the private key, and displaying the target invitation page in response to that the target two-dimensional code is decrypted successfully; and submitting user information written to the target invitation page in response to a submitting operation for the target invitation page. |
| US12088559B1 |
Implementing a proxy server to selectively obfuscate traffic
Systems and techniques provide activity monitoring and selective obfuscation of various fields or categories of information included in traffic between servers providing services and end-user devices accessing such services. The selective obfuscation may account for a user's role and one or more levels of authorization or permission assigned to such a role. More generally, the disclosed techniques provide the ability to selectively restrict end-user access to data included in server responses, such that desired portions of the data are not accessible while other portions of the data are still accessible. A traffic routing tool at a proxy server may intercept traffic to a given service and may determine whether or not the traffic should be routed to an obfuscation engine configured to selectively obfuscate traffic. |
| US12088556B2 |
Automated firewall feedback from network traffic analysis
Security rule feedback systems and methods include capturing network traffic data, the network traffic data including a plurality of traffic records. The traffic records are grouped into first and second traffic records having corresponding first and second source address identifiers, first and second source port identifiers, first and second destination address identifiers, and first and second destination port identifiers. Network interfaces associated with the first and second records are identified based on source address identifiers. Security rule populations are associated to the network interfaces. A determination is made as to a direction of network traffic, based on the security rule populations. Thereby, dispensable security rules may be identified. |
| US12088551B2 |
Network control method and network interface card
A network control method is configured to balance the loading of a plurality of processes. The method includes obtaining an IP address of a packet; deleting a portion of bits of the IP address to generate a series according to an IP address entropy distribution; performing a hash function to the series to generate a hash value; performing a modulo operation to the hash value to obtain a remainder; and assigning the packet to a processor of the plurality of processes corresponding to the remainder. |
| US12088548B2 |
Systems and methods for edge device discovery
A system may receive registration information regarding a user equipment (UE). The system may determine a UE usage type for the UE from a plurality of UE usage types. The plurality of UE usage types includes a first UE usage type associated with accessing first services using a cloud domain name system (DNS) and a second UE usage type associated with accessing second services using an edge DNS. The system may receive a notification indicating that the UE is requesting access to a service and identify an edge device for providing access to the service. The system may obtain information identifying the UE usage type of the UE based on UE identification information of the UE. The system may provide, to the UE, DNS information regarding using the cloud DNS or the edge DNS to obtain a network address of the edge device. |
| US12088539B2 |
Determining reply content for a reply to an electronic communication
Methods and apparatus related to determining reply content for a reply to an electronic communication. Some implementations are directed generally toward analyzing a corpus of electronic communications to determine relationships between one or more original message features of “original” messages of electronic communications and reply content that is included in “reply” messages of those electronic communications. Some implementations are directed generally toward providing reply text to include in a reply to a communication based on determined relationships between one or more message features of the communication and the reply text. |
| US12088532B2 |
Method for ACK/NACK transmission and reception in wireless communication system and apparatus therefor
The present invention relates to a method and apparatus for transmitting and receiving an acknowledgement/negative-acknowledgement (ACK/NACK) by a terminal for vehicle-to-everything (V2X) communication in a wireless communication system. Particularly, the method comprises the steps of: receiving a configuration for a resource pool for V2X communication; for a particular wireless resource in a resource pool, when a reception time point of a first ACK/NACK and a transmission time of a second ACK/NACK have been simultaneously configured, determining a use of the particular wireless resource; and transmitting and receiving one ACK/NACK selected from the first ACK/NACK and the second ACK/NACK, on the basis of the use of the particular wireless resource. The UE is capable of communicating with at least one of another UE, a UE related to an autonomous driving vehicle, a base station or a network. |
| US12088528B2 |
Communications devices, infrastructure equipment and methods
A communications device comprises transceiver circuitry configured to transmit signals to and receive signals from a wireless communications network via a wireless access interface of the wireless communications network, and controller circuitry configured in combination with the transceiver circuitry to determine uplink communications resources of the wireless access interface to be used for the transmission of data by the communications device, to receive a plurality of uplink cancellation indicators that each indicate that at least a portion of the uplink communications resources is allocated for the transmission of signals by another communications device and is located within communications resources of one of a plurality of reference regions, and to determine, in accordance with dimensions of a first reference region and dimensions of a second reference region, that at least a portion of the uplink communications resources is allocated for the transmission of signals by another communications device. |
| US12088525B2 |
Information transmission method and apparatus and communication device
The embodiments of the present disclosure provide information transmission methods and apparatuses, and a communication device. The method includes: sending reporting information including at least one first information that is associated with at least one reference signal resource to a network device by a terminal device. |
| US12088522B2 |
Extended discovery burst transmission window
A base station may schedule a plurality of synchronization signal blocks (SSBs) in an extended discovery burst (DRS) transmission window including a plurality of candidate SSBs including at least two candidate SSBs with a same SSB beam index, and transmit the plurality of SSBs based on the scheduling of the plurality of SSBs in the extended DRS transmission window. A UE may monitor for a plurality of SSBs in the extended DRS transmission window including the plurality of candidate SSBs including at least two candidate SSBs with the same SSB beam index, and perform measurements based on SSBs of the plurality of SSBs received from the base station. The base station may transmit a signal indicating one or more scheduling parameters of the plurality of SSBs, and the UE may determine SSB index of each candidate SSB of the plurality of candidate SSBs. |
| US12088518B2 |
Method, device, and system for transmitting and receiving reference signal and data channel in wireless communication system
Provided is a wireless communication user equipment that wirelessly communicates. The wireless communication user equipment includes a communication module; and a processor configured to control the communication module. The processor is configured to receive a demodulation reference signal (DM-RS) of data channel and receive the data channel based on the DM-RS of the data channel, wherein a time-frequency resource mapped to the DM-RS is predetermined. When the time-frequency resource mapped to the transmission of the DM-RS of the data channel overlaps with the time-frequency resource mapped to a different purpose from the transmission of the DM-RS, the processor is configured not to receive the DM-RS in a resource element (RE) overlapping with the time-frequency resource mapped to the different purpose in the time-frequency resource mapped to the transmission of the DM-RS. The DM-RS is a reference signal specific to the wireless communication device. |
| US12088516B2 |
Resource allocation for multi-TRP URLLC
An approach is described for an access node configured for ultra-reliable and low latency (URLLC) transmission using multi-transmission reception point (TRP) to a UE. The access node includes processor circuitry and radio front end circuitry. The processor circuitry is configured to allocate resource blocks into a first portion and a second portion based on a resource indication value (RIV), a length of contiguously allocated resource blocks (LRBS) and a fraction. The radio front end circuitry is configured to transmit the first portion to the UE via a first transmission reception point (TRP1), and transmit the second portion to the UE via a second transmission reception point (TRP2). |
| US12088514B2 |
Sub-band position modulation techniques for wireless communication
Aspects of the disclosure relate to efficiently exchanging data in power-limited wideband communications. A base station and a UE transmit data using sub-band position modulation (SBPM), in which a select subset of frequency sub-bands carry the data transmission. At a given interval of the streamed data portion, a new subset of the sub-bands may be selected as the active sub-bands, thus modulating the active sub-band positions during the data transmission. A receiver monitors for the data transmission signal and detects the sub-bands on/off state in order to receive the data within the active sub-bands. The entities exchange no control information indicating which sub-bands a given transmission uses. Further, SBPM includes pattern recognition by both devices in order to convey additional information each interval by selecting the positions of the active sub-bands to match the pattern associated with the information to be conveyed. |
| US12088509B2 |
Default gateway management method, gateway manager, server, and storage medium
Provided is a default gateway management method. The method includes that: a target attribute label of a target application container is detected in response to a default gateway application request; and in a case where the target attribute label exists and a target default gateway pool configured with the target attribute label exists in a gateway resource pool, a default gateway is allocated for the target application container from the target default gateway pool. Further provided are a gateway manager, a server, and a storage medium. |
| US12088508B2 |
Methods for data transmission on ethernet multidrop networks implementing dynamic physical layer collision avoidance
A method for transmitting data on a communication network, the communication network including a plurality of network nodes connected to one same medium for sending and receiving data signals. The data are transmitted by nodes on the medium during transmission cycles, and each transmission cycle includes a plurality of transmission opportunities each of which is allocated to a respective node based on a node identifier associated with that node. The method provides that at least one node listens to the medium for signals transmitted during a transmission cycle and detects the node identifiers associated with the nodes that used a respective transmission opportunity to transmit at least a signal. Accordingly, the node creates a list of the node identifiers detected, wherein the node identifiers are listed according to the order of the transmission opportunities in the transmission cycle. |
| US12088502B2 |
Adaptive network control of traffic flows in a secure network
A method is provided for rate limiting in a network. The method comprises receiving a traffic flow from the network. In a supervised learning phase, and determining if the traffic flow matches a pretrained network flow model. If so, the method comprises designating the traffic flow as a classified traffic flow according to the pretrained network flow model. The method further comprises advancing to a grouping phase, conditioned upon the traffic flow not matching pretrained network flow models. In the unsupervised learning phase, the method comprises designating the traffic flow as a classified traffic flow. In the grouping phase that follows the supervised learning phase and the unsupervised learning phase, the method comprises using side information about the traffic flows to assign related traffic flows into traffic flow groups, identifying a particular traffic flow group from the traffic flow groups as being an offending traffic flow group. |
| US12088501B2 |
Systems and methods for supporting traffic steering through a service function chain
Methods and system for supporting traffic steering through a service function chain, the service function chain comprising at least one data processing function. An aspect of the disclosure provides for a method for steering traffic of a packet data unit (PDU) performed by a session management function. The method includes receiving PCC rules from a policy control function, the PCC rules including information comprising at least one of service function chain information; final delivery indication; and selective traffic steering information and associated parameters. The method further includes configuring at least one user plane function (UPF) according to the information. In some embodiments the configuring the at least one UPF includes instructing a first UPF to detect traffic according to the packet detection rules and route the received packet according to the forwarding action rules. |
| US12088499B2 |
System and method for reducing data packet processing false alarms
Aspects of the disclosure relate to a multipoint environment that enables a station (STA) to communicate with multiple access points (APs) and an AP to communicate with multiple STAs in a single wireless protocol stack. For example, a STA can authenticate simultaneously with multiple APs and decode any data packet that includes in a header a destination address that matches an address of the STA, irrespective of the source address included in the header of the data packet. Similarly, an AP can decode any data packet that includes in a header a destination address that matches an address of the AP or that matches a wildcard address associated with the AP, irrespective of the source address included in the header of the data packet. |
| US12088495B2 |
Intelligent route selection for low latency services
A solution for route selection includes receiving, by a network repository, from a first network function (NF), a query related to a target NF; querying, by the network repository, a route selection node for a shortest path to the target NF; receiving, by the network repository, from the route selection node, an indication of the shortest path to the target NF; and based on at least receiving the indication of the shortest path to the target NF, transmitting, by the network repository, to the first NF, a route to the target NF. In some examples, the shortest path has at least one of: a minimum number of hops, a minimum latency, a minimum jitter, and a minimum weighted transport score. In some examples, the route selection node is co-located with the network repository, which may be a network repository function (NRF). |
| US12088493B2 |
Multi-VRF and multi-service insertion on edge gateway virtual machines
In an embodiment, a method for a VRF and multi-service insertion on edge gateways is described. In an embodiment, the method comprises obtaining a rule configuration. Based on, at least in part, the rule configuration, a rule table is created. The rule table comprises rule data records, wherein a rule data record comprises packet attributes and a redirection identifier. A policy configuration comprising policy records is obtained. Each policy record comprises a redirection identifier, a next_hop, and an address pair for interfaces. A mapping between VRF identifiers and address pairs is generated. Based on, at least in part, the mapping and the policy configuration, a policy table is generated. The policy table comprises table records, wherein a table record comprises a redirection identifier, a next_hop, and an address pair. The rule and policy tables are used to redirect a packet from an edge gateway to a service virtual machine. |
| US12088488B2 |
Radio network node, user equipment and methods performed therein
Embodiments herein may relate to a method performed by a UE for handling communication in a wireless communication network. The UE transmits an indication to a radio network node, indicating a type of data traffic for communication of the UE, wherein the type is related to a level of performance. |
| US12088484B2 |
Micro segment identifier instructions for path tracing optimization
Techniques for optimizing technologies related to network path tracing and network delay measurements are described herein. Some of the techniques may include using an IPv6 header option and/or segment identifier field of a segment list or a TLV of a segment routing header as a telemetry data carrier. The techniques may also include using an SRv6 micro-segment (uSID) instruction to indicate to a node of a network that the node is to perform one or more path tracing actions and encapsulating the packet and forward. Additionally, the techniques may include using short interface identifiers corresponding to node interfaces to trace a packet path through a network. Further, the techniques may include using short timestamps to determine delay measurements associated with sending a packet through a network. In various examples, the techniques described above and herein may be used with each other to optimize network path tracing and delay measurement techniques. |
| US12088483B2 |
Telemetry data optimization for path tracing and delay measurement
Techniques for optimizing technologies related to network path tracing and network delay measurements are described herein. Some of the techniques may include using an IPv6 header option and/or segment identifier field of a segment list or a TLV of a segment routing header as a telemetry data carrier. The techniques may also include using an SRv6 micro-segment (uSID) instruction to indicate to a node of a network that the node is to perform one or more path tracing actions and encapsulating the packet and forward. Additionally, the techniques may include using short interface identifiers corresponding to node interfaces to trace a packet path through a network. Further, the techniques may include using short timestamps to determine delay measurements associated with sending a packet through a network. In various examples, the techniques described above and herein may be used with each other to optimize network path tracing and delay measurement techniques. |
| US12088482B2 |
Optimized data streaming detection and prioritization
An example method may include receiving first data packets intended for a client device at a virtual private network (VPN) server, receiving, concurrently with the first data packets, second data packets at the VPN server, identifying, via the VPN server, whether the first or second packets correspond to a real-time streaming session based on one or more of header information and packet size of the first and second packets and a transmission rate associated with the first and second packets, prioritizing the first data packets, identified as real-time streaming session data packets, to be delivered to the client device prior to the second data packets, identified as non-real-time streaming session data packets, and performing connection bonding or connection mirroring using two or more connections when one or more of a data packet loss rate is above a threshold packet loss rate and the transmission rate is below a threshold transmission rate. |
| US12088480B2 |
Network analytics transfer method and apparatus, and network function entity
A network analytics transfer method and apparatus, and a network function entity are provided. The method includes receiving an analytics transfer request, wherein the analytics transfer request is configured to request to transfer first network analytics from a source network function entity to the target network function entity; obtaining analytics aggregation information of the first network analytics according to the analytics transfer request, wherein the analytics aggregation information includes aggregation indication information of one or more first network function sub-entities, and the first network function sub-entities are configured to provide first analytics results to the source network function entity; performing network analytics aggregation according to the analytics aggregation information to obtain an aggregated analytics result of the first network analytics. |
| US12088476B2 |
Intelligent lifecycle management of analytic functions for an IOT intelligent edge with a hypergraph-based approach
The disclosure relates to a framework for dynamic management of analytic functions such as data processors and machine learned (“ML”) models for an Internet of Things intelligent edge that addresses management of the lifecycle of the analytic functions from creation to execution, in production. The end user will be seamlessly able to check in an analytic function, version it, deploy it, evaluate model performance and deploy refined versions into the data flows at the edge or core dynamically for existing and new end points. The framework comprises a hypergraph-based model as a foundation, and may use a microservices architecture with the ML infrastructure and models deployed as containerized microservices. |
| US12088474B2 |
Predictive scoring based on key performance indicators in telecommunications system
A method includes: receiving protocol event data from a plurality of probes within the telecommunication system; determining a most probable cause of a call event from the protocol event data; applying the most probable cause to a trained machine learning algorithm that includes the most probable cause as its input and a telecommunication system score as its output; and in response to an output score from the trained machine learning algorithm, performing a corrective action for a plurality of network users that are expected to be affected by the most probable cause. |
| US12088458B1 |
Controller device management of peripheral devices
Controller devices may be communicatively coupled to distributed devices in a workspace. The controller devices may be positioned in various geographic locations relative to locations of the distributed devices within the workspace. Each of the controller devices may be utilized to maintain an account of, and locally control, one or more of the distributed devices. Portal devices may utilize the controller devices to manage the distributed devices by configuring, controlling, and updating the controller devices. The control devices may be utilized to establish communication channels between the portal devices and the distributed devices to provide access for a user to the distributed devices. The communication channels may be accessible to user devices based on security credentials that are modified in real-time or near real-time. |
| US12088454B2 |
Restoring system functionality when primary maintenance interface is unavailable
An approach for restoring system functionality when a primary maintenance interface is unavailable is provided. In an embodiment, a computer maintenance application that is configured to use a Virtual Telecommunications Access Method (VTAM) interface to connect to a mainframe system is retrieved. A mainframe system is accessed with the computer maintenance application using the VTAM interface. During the access, a maintenance activity is performed on the mainframe system using the computer maintenance application. |
| US12088451B2 |
Cross-platform programmable network communication
Various aspects of the subject technology relate to systems, methods, and machine-readable media for cross-platform programmable network communication. The method includes receiving, at a network toolchain, instructions for network hardware of a radio access network (RAN), the instructions comprising a domain specific language for the RAN. The method also includes determining through the network toolchain an architectural model for the network hardware, the architectural model comprising network patterns of the network hardware. The method also includes generating, by the network toolchain, translated instructions based on the instructions, the translated instructions comprising a configuration and control layer (CCL) code. The method also includes sending the CCL code to the network hardware. The method also includes executing the CCL code by the network hardware. The method also includes causing the network hardware to perform a network function based on execution of the CCL code. |
| US12088450B2 |
Communication method and apparatus
This application relates to the field of communication technologies and discloses a communication method and a communication apparatus. One example method includes: A network device sends temporary SSB burst configuration information to a terminal device served by a secondary serving cell, where the temporary SSB burst configuration information includes a periodicity and/or an offset for sending a temporary SSB burst by the network device in the secondary serving cell configured for the terminal device. The network device sends a temporary SSB burst in the secondary serving cell based on the temporary SSB burst configuration information, where a temporary SSB included in the temporary SSB burst does not include a PBCH. |
| US12088448B2 |
Method and apparatus for applying optimized phase rotation by considering preamble puncturing in 802.11ax and various RF capabilities
A method and an apparatus for transmitting an EHT PPDU to a wireless LAN system are presented. Particularly, a transmission device generates an EHT PPDU, and transmits the EHT PPDU to a reception device through a 320 MHz band of which a partial band is punctured on the basis of an RF. A legacy preamble includes an L-STF and an L-LTF. The legacy preamble is generated by applying a first phase rotation value. The first phase rotation value is determined on the basis of a first method and a second method. The first method is for acquiring an optimum PAPR in the L-LTF. The second method is for acquiring an optimum PAPR on the basis of a maximum transmission bandwidth supported by the RF. The first phase rotation value is acquired on the basis of a second phase rotation value and a third rotation value. The second phase rotation value is a phase rotation value which repeats a phase rotation value that is defined with respect to an 80 MHz band in an 802.11ax system. The third phase rotation value is a phase rotation value that is defined by 80 MHz band units in the 320 MHz band. |
| US12088446B2 |
Bandwidth parts for positioning signals
A method of operating a UE includes receiving a configuration of multiple bandwidth parts. Each bandwidth part of the multiple bandwidth parts is associated with a respective access node of multiple access nodes. The method also includes receiving positioning signals on each bandwidth part of the multiple bandwidth part from the respectively associate access node of the multiple access nodes. Said receiving is in accordance with the configuration. The method also includes participating in positioning of the UW based on said receiving of the positioning signals. |
| US12088445B2 |
Methods and apparatuses for frequency-offset determination and resource block transmission
A method of frequency-offset determination includes: receiving a resource block containing one or more auxiliary frequency-offset estimation signals and pilot signals from a second device; and calculating the one or more auxiliary frequency-offset estimation signals and the pilot signals to determine a frequency offset for demodulating the resource block. At least one of the first device or the second device is a vehicle. |
| US12088439B1 |
Phased burst mode receiver equalization training
A phased approach to training of an upstream burst mode receiver equalizer is disclosed that proceeds incrementally through modulation schemes requiring increasing levels of equalization in a manner where the equalizer maintains the capability to accurately recover data transmitted during each training phase. The phased approach includes an initial training phase (one or more upstream bursts) using a simple modulation format, one or more intermediate phases of different modulation schemes, and a final training phase using the PON-defined (high) line rate upstream modulation format. Equalizer settings generated during the initial phase are used as a starting point for the equalization process in the next training phase, and so on, until the equalizer training reaches the final phase where the ONU uses the PON-defined upstream data rate and the burst mode equalizer is updated accordingly. |
| US12088436B2 |
Apparatus and method for adjusting both a cyclic prefix length and a symbol interval of a complex symbol sequence
[Object] To adaptively adjust a symbol interval in accordance with a communication environment.[Solution] An apparatus including: a communication unit configured to perform radio communication; and a control unit configured to perform control such that control information for adjusting a symbol interval in a complex symbol sequence into which a bit sequence is converted is transmitted from the communication unit to a terminal, the control information being set on a basis of a predetermined condition. |
| US12088430B2 |
Systems and methods for preserving system contextual information in an encapsulated packet
In some embodiments, a computing system includes a communication interface; and a processor that is coupled to the communication interface. In some embodiments, least one of the communication interface or the processor receives a network packet from the network via a network adapter port; encapsulates the received network packet with a tunnel header, wherein the tunnel header comprises network identifier information identifying the network adapter port; addresses, based on the network identifier information, an outer Internet protocol (IP) header of the encapsulated network packet with an outer IP address corresponding to a network function in a first computing device; and sends the encapsulated network packet toward the network function identified by the outer IP address. |
| US12088426B2 |
Automating a software-defined wide area network policy for internet of things end points
The present disclosure is directed to managing industrial internet of things end points and includes one or more processors and one or more computer-readable non-transitory storage media coupled to the one or more processors and comprising instructions that, when executed by the one or more processors, cause one or more switches to perform operations comprising: identifying a first end point using a protocol associated with the first end point, determining a classification for the identified first end point based on one or more attributes of the first end point, identifying one or more related end points having the classification in common with the first end point, segmenting the first end point with the identified one or more related end points, and applying one or more policies to the segmented first end point and the one or more related end points. |
| US12088420B2 |
Configuration and application of sidelink identification in wireless communication system
According to an aspect of the present disclosure, there is provided a method of transmitting feedback information from a user equipment (UE) in a new radio (NR) vehicle-to-everything (V2X) system. Here, the method of transmitting feedback information may include performing, by a first UE and a second UE, a session establishment process based on at least one of unicast and groupcast; exchanging, by the first UE and the second UE, ID information in the session establishment process; and completing, by the first UE and the second UE, the session establishment. Here, when the first UE and the second UE complete the session establishment, a physical layer ID representing a session may be determined. |
| US12088418B2 |
Hybrid automatic repeat request feedback for outer loop adaptation for 5G or other next generation network
Intelligent hybrid automatic repeat request (HARQ) feedback can better support link adaption. Thus, in addition to the traditional HARQ feedback, which is to relay acknowledgement (ACK) and negative acknowledgement (NAK) data based on a decoding result, a new state for the HARQ feedback can be represented as “ACK+”. Consequently, ACK+ can be used to indicate to the network that a modulation and coding scheme (MCS) of a current data packet is too conservative, and the user equipment (UE) is capable of supporting a more aggressive MCS. |
| US12088414B2 |
Methods and procedures for transmitting a transport block over multiple time units in an uplink shared channel
Systems, methods, and instrumentalities are disclosed for narrowband (NB) LTE operation. A WTRU may receive a first downlink data transmission, for example, via a physical downlink shared channel (PDSCH). The WTRU may determine to send a hybrid automatic repeat request (HARQ) acknowledgment (ACK) in response to receipt of the first downlink data transmission. The WTRU may transmit a first uplink reference signal. The WTRU may indicate the HARQ-ACK using a first cyclic shift index that is applied to the first uplink reference signal. The WTRU may determine to send a HARQ negative ACK (HARQ-NACK), for example, on a condition that a second downlink data transmission is not correctly received. The WTRU may send a second uplink reference signal. The WTRU may indicate the HARQ-NACK using a second cyclic shift that is applied to the second uplink reference signal. |
| US12088411B2 |
Cyclic redundancy check (CRC) generation
A system such as an imaging system may include Cyclic Redundancy Check (CRC) value generation circuitry. The CRC value generation circuitry may include a data splitter that splits an input data bit stream instead multiple split data bit streams each inserted with a number of bits having a value of 0. A plurality of CRC value generators may each have a corresponding input path to receive a respective one of the split data bit streams and generate corresponding partial CRC values. A data combiner coupled to the plurality of Cyclic Redundancy Check value generators may combine the partial CRC values to generate a final CRC value. A normalizer may be coupled between each of the plurality of CRC generators and the data combiner. Two CRC value data storage structures may help the plurality of Cyclic Redundancy Check value generators and the data combiner perform the desired CRC computations. |
| US12088402B2 |
Service connecting antennas to remote regions
A Data Delivery Service (DDS) is described, which is a service in a multi-tenant environment that transmits satellite data between a satellite antenna and a user instance. The DDS transports the antenna data to a different region, which allows a user to reuse their infrastructure for multiple antenna sites, thereby, reducing their infrastructure footprint and costs. Gateway instances can be launched at scheduled times in different regions and a secure communication channel can be established between the gateway instances to establish inter-region communication. |
| US12088399B2 |
Communication method and communication apparatus
The present disclosure provides a communication method, including: receiving a Doppler parameter; and determining a time compensation amount for a signal based on the Doppler parameter. When the method is performed by a terminal device, the terminal device can receive the Doppler parameter from a satellite or a satellite measurement and control center. When the method is performed by a satellite, the satellite can receive the Doppler parameter from a satellite measurement and control center. Therefore, the apparatus performing the method does not need to calculate the Doppler parameter locally, thereby reducing the burden on the apparatus. |
| US12088398B1 |
Configurable orthogonal frequency division multiplexing (OFDM) signal and transmitter and receiver for same
A modem is configurable on a satellite, user terminal or gateway generates a radio frequency (RF) signal using an orthogonal frequency division multiplexing (OFDM) protocol including a radio frame including one or more bursts. A burst of the one or more bursts includes a first portion including burst detection data, a second portion including channel characteristic estimation data, a third portion including payload data, and fourth and fifth portions including pilot data. The first portion in a time domain is included in the burst prior to the second, third, fourth, and fifth portions. The first portion can include a pseudo-random noise sequence inserted in the time domain. The same physical modem can be configured to transmit signals on an uplink or downlink between a user terminal and a satellite or on the uplink or downlink between the satellite and the gateway. |
| US12088396B2 |
Measurement reporting with delta values
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a first transmit-receive point (TRP), a first channel state information reference signal (CSI-RS) associated with the first TRP and a first beam. The UE may receive, from the first TRP or a second TRP, a second CSI-RS associated with the first TRP or the second TRP, wherein the second CSI-RS is associated with a second beam. The UE may transmit, to the first TRP or the second TRP, an indication of a delta value between a measurement of the first CSI-RS and a measurement of the second CSI-RS. Numerous other aspects are described. |
| US12088395B2 |
Beam failure recovery for single DCI-based M-TRP URLLC transmissions
Apparatuses and systems for providing multiple structures to enable flexibility of a multiple transmission and reception point ultra-reliable low-latency communication (M-TRP URLLC) operation and reduce measurement effort and power consumption from a transceiving apparatus such as a UE are provided. The techniques disclosed here feature a transceiving apparatus including a transceiver and circuitry. The transceiver, in operation, receives signals from multiple transmission and reception points (M-TRPs) in a network on at least physical downlink shared channels (PDSCHs). The circuitry, in operation, performs beam failure recovery (BFR) by evaluating beam failure detection (BFD) and candidate new beam detection (CBD) for the signals from at least a first one of the M-TRPs. The signals from the first one of the M-TRPs comprise signals received on a physical downlink control channel (PDCCH), and the circuitry determines to skip evaluation of one or both of the BFD and the CBD for one or more additional ones of the M-TRPs in response to one or more conditions. |
| US12088390B2 |
Method for supporting beam correspondence and apparatus thereof
There is provided for supporting beam correspondence. The method may be performed by a user equipment (UE) and comprise: transmitting UE capability information to a base station. The UE capability information may include first information related a capability of supporting beam correspondence. The beam correspondence may be determined based on at least a beam correspondence tolerance requirement. The beam correspondence tolerance requirement may include a delta effective isotropic radiated power (EIRP) of 3 dB. |
| US12088388B2 |
Type II CSI port selection codebook enhancement with partial reciprocity
A base station and wireless communication (UE) may perform type II CSI-RS port selection based at least on partial reciprocity between an uplink path and a downlink path between the base station and the UE. The base station may identify dominant signal paths between the base station and the UE, based on measurements performed during uplink transmissions, and may transmit, to the UE, corresponding information indicative of CSI measurement and reporting configuration that may include a single measurement resource or multiple measurement resources. Each measurement resource may include multiple-port CSI-RS ports. The UE may indicate, to the base station, selection of a measurement resource when multiple measurement resources are configured, and may also report layer independent or layer common selection of a subset of CSI-RS ports included in the indicated single measurement resource or multiple measurement resources. Further enhancements include frequency domain compression enhancement and dynamic codebook parameter reconfiguration. |
| US12088386B1 |
Systems and methods for dynamic MIMO-mode switching based on user device mobility
Aspects herein provide systems, methods, and media for dynamically switching between multiple input multiple output algorithms to improve spectral efficiency and capacity. In aspects, based on data encoding traffic, user device mobility, and coverage, a base station automatically and intelligently selects and implements a particular downlink operating schema. Using various periodicity, the base station dynamically switches between various downlink operating schemas to reflect changing conditions in the date that encodes traffic, user device mobility, and coverage. |
| US12088383B2 |
Uplink SRS with precoding
Certain aspects of the present disclosure provide techniques for uplink sounding reference signal (SRS) transmission with precoding. A method for wireless communication by a user equipment (UE) includes receiving a SRS configuration that configures one or more SRS resource sets, each resource set including one or more SRS resources, each SRS resource comprising one or more SRS ports. The UE receives a set of precoders via an indicator, the set of precoders including a precoder associated with each SRS resource and determines one or more precoders to apply for one or more SRS transmissions via one or more of the SRS resources. |
| US12088381B2 |
Mechanisms for reduced density CSI-RS
According to some embodiments, a method for use in a network node of transmitting channel state information reference signals (CSI-RS) comprises: transmitting, to the wireless device, an indication of the subset of PRBs that the wireless device should use to measure CSI-RS; and transmitting CSI-RS on the indicated subset of PRBs. According to some embodiments, a method for use in a wireless device of receiving CSI-RS comprises: receiving an indication of a subset of PRBs that the wireless device should use to measure CSI-RS associated with an antenna port; and receiving CSI-RS on the indicated subset of PRBs. In some embodiments, the indication of the subset of PRBs that the wireless device should use to measure CSI-RS comprises a density value and a comb offset. |
| US12088380B2 |
Artificial intelligence based channel state information framework
This disclosure relates to techniques for providing an artificial intelligence based framework for performing channel state information reporting in a wireless communication system. A cellular base station may provide system information for a cell to a wireless device. The system information may indicate that the cell supports artificial intelligence based channel state information reporting. The wireless device may provide wireless device capability information to the cellular base station. The capability information may indicate that the wireless device supports artificial intelligence based channel state information reporting. The wireless device may determine an artificial intelligence model to use to perform channel state information reporting with the cell, and may perform channel state information reporting using the selected artificial intelligence model. |
| US12088379B2 |
CSI acquisition for partial reciprocity
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit a sounding reference signal (SRS) that indicates that the UE is configured with a quantity of receive elements that is greater relative to a quantity of transmit elements with which the UE is configured. The UE may receive, based at least in part on transmitting the SRS, a first channel state information (CSI) reference signal (CSI-RS) set and a second CSI-RS set. The UE may transmit a CSI report that is based at least in part on the first CSI-RS set and the second CSI-RS set. Numerous other aspects are provided. |
| US12088377B2 |
Coefficient indication for channel state information
Methods, systems, and devices for wireless communications are described. A user equipment (UE) may perform channel state information measurements on reference signal transmissions from a base station. The UE may identify a set of cross layer coefficients associated with a set of spatial layers based on the channel state information measurements. The UE may additionally identify a set of precoding coefficients associated with a spatial layer from the set of spatial layers. In some implementations, the set of precoding coefficients may be based on the set of cross layer coefficients. In some examples, the UE may transmit the set of cross layer coefficients and the set of precoding coefficients to the base station. |
| US12088373B2 |
Methods and systems for beam tracking process management and indices
In a multi-BPL scenario, some form of beam-related indication is desirable to provide assistance to the UE in setting its Rx spatial filtering configuration to receive PDSCH. The assistance to the UE is in the form of a certain indicator indicating a spatial QCL assumption between PDSCH DMRS antenna port(s) and DL RS (e.g., CSI-RS) antenna port(s), such as a preferred CSI-RS resource that was measured and reported previously. |
| US12088369B2 |
Method and apparatus for learning-based channel matrix prediction
Methods and apparatus are provided in which channel matrices at time slots are estimated using reference signals received from a base station (BS) at the time slots. A sequence of channel matrices at future time slots are estimated using the estimated channel matrices as input to a neural network (NN) trained based on known sets of past and future channel matrices. A parameter is determined using at least one channel matrix from the sequence of channel matrices. |
| US12088368B2 |
Systems and methods for satellite selection using beamscanning techniques
Systems and methods are described for connecting with LEO satellites while reducing emissions toward GEO satellite communications. A system to implement the instant techniques may include a system comprised of a user communications equipment and a LEO constellation. The user equipment (“UE”) may comprise a communications modem and an active antenna unit with a transmit and receive beamformer. In further implementations, the UE may include additional receive only beamformers. The LEO constellation can have a regenerative payload or bent pipe, and can include orbits at different altitudes. Methods as described herein may include a procedure by which the user equipment and LEO satellite work together to identify candidate serving satellites, and select the one that allows to meet the power density requirements to avoid interfering with the GEO satellites. |
| US12088366B2 |
Closed loop spatial interference control in full duplex
Methods, systems, and devices for wireless communications are described. A base station may manage a shape of a beam to selectively reduce interference at one or more wireless nodes. The base station may receive a capability message from a first wireless node indicating a capability of the first wireless node to support one or more beam tapering configurations. In some cases, the base station may receive an interference report from a second wireless node, indicating that the first wireless node caused interference at the second wireless node. The base station may transmit a beam tapering configuration of the one or more beam tapering configurations to the first wireless node, and the first wireless node may transmit a beamformed message to the base station according to the beam tapering configuration. In some cases, the beam tapering configuration may be associated with less interference when transmitting the beamformed message. |
| US12088360B2 |
Dispersive waveguide crosstalk mitigation
Embodiments may relate to a baseband module with communication pathways for a first data signal and a second data signal. The baseband module may also include a finite impulse response (FIR) filter in a communication path between the first signal input and the second signal output. Other embodiments may be described or claimed. |
| US12088358B2 |
Predictive quality of service via channel aggregation
A wireless system includes a controller that is configured to measure a first Reference Signal Received Power (RSRP1) from a first carrier at a first time, measure a second Reference Signal Received Power (RSRP2) from a second carrier at a second time, annotate the RSRP1 to the first carrier and the RSRP2 to the second carrier, in response to the first time and the second time being within a contemporaneous period, associate the RSRP1 and RSRP2 to the contemporaneous period, create an N-Dimension vector of RSRP1 and RSRP2 at the contemporaneous period, process the N-Dimension vector via a trainable function to obtain a predicted data rate, and in response to the predicted data rate falling below a normal operating range threshold, operate the system in a low bandwidth mode. |
| US12088356B2 |
Electronic device for adjusting output power of signal by using millimeter wave, and control method therefor
An electronic device using a millimeter wave, according to various embodiments, includes a communication circuit and at least one processor. The at least one processor can be configured to: control the communication circuit so that a first millimeter wave signal is output at a first strength; use the communication circuit so that the first millimeter wave signal receives a first reflection signal reflected by an object; confirm whether the object is positioned within a first distance from the electronic device; determine the strength of a second millimeter wave signal to be a second strength corresponding to a second distance between the electronic device and the object, the second distance being shorter than the first distance; and control the communication circuit so that the second millimeter wave signal is output at the determined second strength. |
| US12088355B2 |
Reduction of emulated channel count for phased-array systems through angle-of-arrival processing
Systems and methods for emulating a channel for wireless communications between a transmit (TX) system-under-test (SUT) and a receive (RX) SUT. The TX and RX SUTs include integrated antenna arrays for transmitting and receiving wireless signals. For a plurality of paths of the emulated channel, and for each antenna element of the TX SUT, a respective phase shift and gain modification is applied to a wireless signals transmitted by the respective antenna element. The phase shifts and gain modifications emulate path length differences between different antenna elements. The signals for each antenna element are summed, and a path-specific modification is applied to each aggregate signal for each path. For each RX antenna element, phase shift and gain modifications are applied to emulate path-length differences for the RX antenna elements, the resultant signals are summed for each path, and the emulated wireless signals are output to the RX antenna elements. |
| US12088354B2 |
High speed acoustic communications and telemetry via solid pieces
A method and a system are disclosed for high speed acoustic transmission of data in networks and sequences of solid pieces using various propagation modes. The data is converted to several sets, and then the sets are transmitted via propagation modes such as extensional or flexural or torsional or their combinations, using multiple transmitters. This allows to increase transmission rate or reduce transmission error or both for data communication. |
| US12088349B2 |
Signal pre-compensation method and apparatus
A signal pre-compensation method is provided. In the method, at least one target frequency subband is determined from a plurality of frequency subbands of a first optical signal and an optical signal of the at least one target frequency subband in the first optical signal is demodulated based on the at least one target frequency subband. A first electrical signal is obtained after demodulation, and a pre-compensation parameter is updated based on the at least one target frequency subband, the first electrical signal, and a second electrical signal. Herein the pre-compensation parameter is used to perform signal pre-compensation on the second electrical signal, and the first optical signal is generated after the pre-compensation is performed on the second electrical signal. |
| US12088343B2 |
Photonic integrated circuit-based polarization-independent optical devices
An apparatus includes a photonic integrated circuit having an optical phased array, where the optical phased array includes multiple unit cells. Each unit cell includes an antenna element configured to transmit or receive optical signals having a linear polarization of light. Each unit cell also includes a modulator configured to phase-shift the optical signals transmitted or received by the antenna element. Each unit cell further includes a quarter waveplate configured to convert between the linear polarization of light and a circular polarization of light. |
| US12088329B2 |
Wireless chip to chip communication with selective frequency multiplexing with different modulation schemes
A transmitter for chip to chip communication may include a modulator and a transmit frequency converter. The modulator may modulate a first received signal according to a first modulation scheme. The modulator may also modulate a second received signal according to a second modulation scheme. The transmit frequency converter may center the first received signal on a first frequency that does not comprise a phase within a radio frequency (RF) domain to generate a first centered signal. The transmit frequency converter may also center the second received signal on a second frequency that comprises a phase within the frequency band to generate a second centered signal. The second centered signal may be orthogonal to the first centered signal. A frequency gap may be positioned between the first centered signal and the second centered signal within the frequency band. |
| US12088325B2 |
Filter system and operation method thereof
A filter system includes: a first mixer, converting an input signal into a first signal according to a reference frequency signal, wherein the reference frequency signal corresponding to a target frequency band; an analog-to-digital converter, coupled to the first mixer, converting the first signal into a first digital signal; a digital filter, coupled to the analog-to-digital converter, filtering the first digital signal according to a first frequency band and generating a second digital signal, wherein the first frequency band corresponding to the first signal; a digital-to-analog converter coupled to the digital filter, converting the second digital signal into a second signal; and a second mixer, coupled to the digital-to-analog converter, converting the second signal into an output signal according to the reference frequency signal, wherein the output signal corresponds to the input signal filtered by the target frequency band. |
| US12088321B2 |
Device and method for decoding polar code in communication system
The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a post-4th generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure is for decoding a polar code in a communication system. An operation method of a reception device comprises the steps of: receiving data encoded by means of a polar code and comprising a plurality of bits; confirming one or more bits which do not require a decoding operation among the plurality of bits; and decoding at least some of the bits remaining after excluding the one or more bits. |
| US12088318B2 |
Communication apparatus
In a communication apparatus, an analog circuit includes a circuit element to be connected to a first conductor, and processes a differential signal. A communication circuit receives, via a connection circuit, a differential signal processed by the analog circuit, and generates a signal for which the potential of a second conductor is used as a reference potential based on the received differential signal. An inductor is connected between the first conductor and the second conductor. The connection circuit includes a circuit element different from a capacitor. The analog circuit (21), the connection circuit, the communication circuit, the inductor, the first conductor, and the second conductor are housed in a conductive housing box. |
| US12088313B2 |
Pipelined hybrid noise-shaping analog-to-digital converter
Systems and methods are provided for implementing an analog-to-digital converter. In some embodiments, the analog-to-digital converter comprises a first-stage quantizer, a second-stage quantizer, and a noise cancellation filter. The first-stage quantizer is configured to receive an analog input signal and generate a first-stage digital output signal based on the analog input signal and a residual signal based on the first-stage digital output signal and the analog input signal. The second-stage quantizer is configured to receive the residual signal, to determine a first-stage quantization error based on the residual signal, to digitize the first-stage quantization error, and to generate a second-stage digital output signal based on the first-stage quantization error. The noise cancellation filter is configured to receive the first-stage digital output signal and the second-stage digital output signal and to generate a noise-cancellation output signal comprising a quantization error component less that the first-stage quantization error. |
| US12088309B2 |
Control arrangement and method
A control arrangement is disclosed for providing a plurality of phase-coherent oscillating signals. It comprises a reference clock signal arrangement for providing a high-frequency reference clock signal and a plurality of modules each comprising a plurality of channels for providing the plurality of phase-coherent oscillating signals. |
| US12088307B2 |
Circuit and method to enhance efficiency of semiconductor device
A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width. |
| US12088306B2 |
Clock domain crossing
An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge. |
| US12088305B2 |
Circuit arrangement and method for monitoring a signal formed by alternating voltage
A circuit arrangement for monitoring an alternating voltage signal includes a comparator configured to receive the alternating voltage signal or a signal obtained from the alternating voltage signal at a first comparator input and output a comparator signal at a comparator output. The circuit arrangement further includes a zero crossing detector configured to receive a reference signal or a signal obtained from the reference signal at a monitoring input and generate a detector signal at an output of the zero crossing detector. The circuit arrangement further includes a logic circuit including a first timing element connected downstream of the zero crossing detector for generating a first clock signal and a second timing element connected downstream of the zero crossing detector for generating a second clock signal. |
| US12088304B2 |
Spread spectrum clock generation device
A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval. |
| US12088303B1 |
Self-calibrated phase tuning system
A clock generation apparatus has a delay circuit, a phase selection circuit, and a phase measurement circuit. The delay circuit outputs a first signal that is a delayed version of an input signal. The phase selection circuit receives the input signal and one or more phase-shifted versions of the input signal and outputs a second signal that is a phase-shifted version of the input signal. The phase measurement circuit compares the phases of the first signal and the second signal and provides a first output that controls phase of the second signal relative to the input signal. The phase measurement circuit also provides a second output that controls a delay applied by the delay circuit to the input signal to generate the first signal. |
| US12088301B2 |
Resetting integrated circuits
A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC. |
| US12088300B2 |
Duty-cycle correction and related devices, apparatuses, and methods
Electronic devices for correcting a duty-cycle of a clock signal are disclosed. An electronic device may include circuitry configured to receive an input clock signal and generate, based on the input clock signal, a number of corrected clock signals. The circuitry may further be configured to generate, via an amplifier of the circuitry, a number of error signals based on the number of corrected clock signals and adjust a duty cycle of the number of corrected clock signals based on the number of error signals. Further, the circuitry may be configured to disable the amplifier in response to determining that the input clock signal is disabled. Associated apparatuses and methods are also disclosed. |
| US12088299B2 |
Clock distribution with transimpedance amplifier and biquad filter
An integrated circuit (IC) includes a voltage-to-current converter circuit having a first voltage terminal, a second voltage terminal, a first current terminal, and a second current terminal. A transimpedance amplifier (TIA) and biquad filter circuit has a first TIA and biquad filter input coupled to the first current terminal and has a second TIA and biquad filter input coupled to the second current terminal. The transimpedance amplifier includes cross-coupled transistors configured to use positive feedback. |
| US12088298B2 |
Computing apparatus triggered by an edge of a supply-line signal with a pulse width counter
A computing apparatus triggered by an edge of a supply-line signal with a pulse width counter includes: a clock circuit to supply clock signals to a pulse width counter from an output port of said clock circuit; said pulse width counter triggered by said clock signals to count the pulse width of a supply-line signal from a power supply line, to set a circuit status of said computing apparatus in accordance with said pulse width, and to output said circuit status to an edge-triggered computing unit; and the edge-triggered computing unit to do computing triggered by an edge of a supply-line signal, and to output computing result as the output of said computing apparatus in accordance with said circuit status. The circuit status of the computing apparatus is set in accordance with pulse width counter of supply-line signals. |
| US12088296B2 |
Clock gating using a cascaded clock gating control signal
A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal. |
| US12088293B2 |
Data bus signal conditioner and level shifter
A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate. |
| US12088290B2 |
Hand-held machine tool and related method
A method is provided for actuating a hand-held machine tool including a drive device, with a control device for actuating the drive device and at least two capacitive sensor elements operatively connected to the control device being provided. The method includes the following method steps of determining an electrical charge of the first and second sensor element comparing the determined first electrical charge with a defined first threshold value and the determined second electrical charge with a defined second threshold value; enabling the actuation of the drive device and/or defined activation of the drive device via the control device when a predefined condition exists between the determined first electrical charge of the first sensor element and the determined detected second electrical charge of the second sensor element. A machine tool for carrying out a method of this kind is also described. |
| US12088289B2 |
Soft handover in a coupled dual-oscillator system
A system includes a sensor integrated circuit (IC), including a driver adapted to be coupled to an oscillator, the driver including first and second transistors. The sensor IC includes an amplitude control amplifier coupled to the first transistor. The sensor IC also includes a common mode control amplifier coupled to the second transistor. The sensor IC includes a handover control circuit coupled to the amplitude control amplifier and configured to hand off an operation from the sensor IC to a different sensor IC, the handover control circuit including a resistor network coupled to a switch network. |
| US12088286B2 |
Temperature sensors
In examples, a circuit comprises a first current source coupled to a voltage source node. The circuit comprises a resistor having a first resistor terminal and a second resistor terminal, where the first resistor terminal is coupled to the first current source. The circuit comprises a bipolar transistor having a base, a collector, and an emitter, with the base coupled to the first resistor terminal, the emitter coupled to the second resistor terminal, and the collector coupled to the voltage source node. The circuit comprises a second current source coupled to the emitter and the second resistor terminal, with the second current source coupled to a ground node. The circuit comprises a Schmitt trigger having an input coupled to the emitter, the second resistor terminal, and the second current source. |
| US12088281B2 |
Transversely-excited film bulk acoustic resonator with multi-mark interdigital transducer
Acoustic resonator devices and acoustic filter devices. An acoustic resonator includes a piezoelectric plate having front and back surfaces. A portion of the back surface is attached to a substrate. The piezoelectric plate comprises a diaphragm spanning a cavity. A conductor pattern is formed on the front surface. The conductor pattern includes a multi-mark interdigital transducer (IDT), with fingers of the IDT on the diaphragm. |
| US12088278B2 |
Bulk acoustic wave resonator with patterned mass loading layer and recessed frame
Aspects of this disclosure relate bulk acoustic wave resonators with a patterned mass loading layer at least contributing to a difference in mass loading between a main acoustically active region of the bulk acoustic wave resonator and a recessed frame region of the bulk acoustic wave resonator. Related methods of manufacturing can involve forming the patterned mass loading layer in the main acoustically active region and the recessed frame region in a common processing step such that the patterned mass loading layer has a higher density in the main acoustically active region than in the recessed frame region. |
| US12088274B2 |
Acoustic wave device
An acoustic wave device includes a piezoelectric substrate, an interdigital transducer electrode on the piezoelectric substrate, and reflectors. The interdigital transducer electrode includes first and second busbars including first and second cavities in a first direction, and first and second edge regions and first and second gap regions. The first and second edge regions include low acoustic velocity regions. Regions in which the first and second cavities are provided include high acoustic velocity regions. The reflector includes first and second reflector busbars and first reflection electrode fingers each including a second end portion that faces the second reflector busbar. The first reflection electrode fingers overlap the entire or substantially the entire second gap region when viewed in the first direction. |
| US12088272B2 |
Solidly-mounted transversely-excited film bulk acoustic resonator
Resonator devices are disclosed. An acoustic resonator device includes a piezoelectric plate having front and back surfaces, an acoustic Bragg reflector on the back surface, and an interdigital transducer (IDT) on the front surface. The acoustic Bragg reflector reflects a primary shear acoustic mode excited by the IDT in the piezoelectric plate over a frequency range including a resonance frequency and an anti-resonance frequency of the acoustic resonator device. |
| US12088263B2 |
Equalizer circuit and related power management circuit
An equalizer circuit and related power management circuit are provided. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit(s) via a signal path for amplifying a radio frequency signal(s). An equalizer circuit is provided in the power management circuit to equalize the differential target voltage prior to generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function including a second-order complex-zero term and a real-zero term for offsetting a transfer function of an inherent trace inductance of the signal path and an inherent impedance of the voltage amplifier circuit. By employing the second-order transfer function with the real-zero term, it is possible to reduce distortion in the ET voltage, especially when the RF signal(s) is modulated in a wide modulation bandwidth. |
| US12088259B2 |
Balanced amplifiers with wideband linearization
An RF amplifier utilizes first and second main amplifiers in a balanced amplifier configuration with first and second auxiliary amplifiers connected in parallel across the first and second main amplifiers, respectively. The main and the auxiliary amplifiers are biased such that the third-order nonlinearity components in the combined output current are reduced. A common or independent bias control circuit(s) control(s) the DC operating bias of the auxiliary amplifiers and establishes DC operating points on curves representing third-order nonlinear components within the drain current having a positive slope (opposite to the corresponding slope of the main amplifiers). This results in reduction of overall third-order nonlinear components in combined currents at the output. In another embodiment, a phase shift of an input to one auxiliary amplifier is used to provide a peak in minimization at a frequency associated with the phase shift. |
| US12088257B2 |
High-frequency amplifier
A high-frequency amplifier includes: a carrier amplifier which amplifies a first signal; a peak amplifier which amplifies a second signal; a first matching circuit which is connected to the output terminal of the carrier amplifier; a second matching circuit which is connected to the output terminal of the peak amplifier; a first transmission line which is connected between the first matching circuit and the second matching circuit, and has an electric length that is less than ¼ of the wavelength of the center frequency of a predetermined frequency band. The phase rotation by a series inductor which is included in each of the first matching circuit and the second matching circuit and has one end that has been grounded is opposite to the phase rotation by the first transmission line. |
| US12088256B2 |
Doherty power amplifier
An input signal is input to a main power amplifier and an auxiliary power amplifier. A combiner is connected to an output of the main power amplifier and an output of the auxiliary power amplifier. The combiner includes an impedance converter, first and second lumped elements. The impedance converter is connected to a combining point. The first lumped element is connected between the output of the main power amplifier and the combining point. The second lumped element is connected between the output of the auxiliary power amplifier and the combining point. A line length between the output of the main power amplifier and the combining point is the same as that between a line length between the output of the auxiliary power amplifier and the combining point. |
| US12088247B2 |
Modular photovoltaic power production system
Apparatuses and systems are presented for photovoltaic power production. A plurality of adaptive solar panels comprise photovoltaic faces and connective edge faces. Connective edge faces each comprise a panel connection interface so that the plurality of adaptive solar panels are releasably affixed one to another in configurations adaptive to surfaces and environmental geometric space constraints. Connective edge faces each further comprise a panel electrical connector such that the plurality of adaptive solar panels are releasably electrically connectable. One or more adaptive connection units comprise unit connection interfaces so that the one or more adaptive connection units are releasably affixed to the plurality of adaptive solar panels. One or more adaptive connection units further comprise one or more connection electrical connectors so that the one or more adaptive connection units are releasably electrically connectable to the plurality of adaptive solar panels. |
| US12088246B2 |
Apparatus, method and article for maximizing solar charge current through the use of split wire(s) in a solar array with solar panels connected in the combination of series and parallel
In a maximum power point tracking (MPPT) solar charging system, the solar array is re-configured to have the majority panels connected in parallel, while some panels remain in series for MPPT charge controller. The split wire(s) from the string of panels connected in series can be connected to all the other panels connected in parallel. The split wire is connected to the apparatus_Solar Charge Maximizing controller, to directly power a direct current_DC load, and to charge a battery or battery bank with the same nominal voltage. The solar charge maximizing controller(s) works in conjunction with MPPT charge controller(s) to maximize the total charge current in the ever-changing solar radiation conditions and in the constant changing DC load (inverters in general) conditions. |
| US12088241B2 |
Spring clip for photovoltaic module mounting
A module mounting system may include a photovoltaic (PV) module frame including a mounting rail. The module mounting system may include a spring clip with a PV module frame interfacing element and a clip interfacing element. The spring clip may apply spring force via deformation to lock the PV module frame and a clip together. A second embodiment of the spring clip may include an upper component having one or more arms and a lower component having a central loop configured to rotate relative to each other and interface with the PV module frame or the mounting rail. A second embodiment of the module mounting system may include screwless clips including outer walls and inner walls coupled together as a continuous sheet of material. The screwless clips may couple to a respective mounting flange and a respective frame flange to lock the mounting purlin and the PV module frame together. |
| US12088237B2 |
Trestle
A trestle includes a base, a slide bracket, a fixing unit, a first fastener, and a second fastener. The fixing unit is installed on the slide bracket and fixes a solar panel that is mounted on a surface of a roof surface. A mounting surface on which the solar panel is mounted is formed on a receiving member of the fixing unit. A fixing unit main body of the fixing unit is formed capable of holding down and fixing the solar panel to the mounting surface by the second fastener, and is fixed to the receiving member. The first fastener is attached such that the fixing between the slide bracket and the fixing unit can be released while maintaining the fixing between the receiving member and the fixing unit main body by the second fastener. |
| US12088236B2 |
Control of an induction generator of a wind turbine
A method of controlling an induction generator is provided connected to a utility grid, the method including: receiving an actual grid frequency; and controlling rotor windings of the generator by a rotor control signal having a rotor winding reference frequency being set in dependence of the actual grid frequency. |
| US12088223B2 |
DQ0 and inverse DQ0 transformation for three-phase inverter, motor and drive design
A test and measurement device includes an interface configured to acquire analog three-phase signals from a device under test, and a processor programmed to execute instructions that cause the processor to perform a direct-quadrature-zero, DQ0, transformation and produce DQ0 signals based on the analog three-phase signals, and measure performance of the device under test based on the DQ0 signals. A method includes acquiring three-phase signals from a device under test, performing a direct-quadrature-zero, DQ0, transformation on the three-phase signals to produce DQ0 signals, and using the DQ0 signals to measure performance of the device under test. |
| US12088221B2 |
Piezoelectric energy harvester with a controlled deflection beam, in particular for powering a leadless autonomous cardiac capsule
The module comprises, in an envelope tube, a pendular unit comprising a piezoelectric transducer, PZT, beam, an inertial mass coupled to the free end of the beam, and a beam mount secured to the tube and fastened to a clamping part of the beam. The module further includes a symmetrization insert for calibrating and symmetrizing the pendular unit oscillations in transverse and lateral directions. The symmetrization insert is distinct from the beam mount and comprises a peripheral portion secured to the tube independently of the beam mount, and a central portion with an axial through-cavity inside which the beam extends in said region of free travel. The axial cavity extends between opposite travel limitation surfaces, which are symmetrical and capable of coming into contact with the beam in a bending configuration of the beam. |
| US12088220B2 |
Vibrating actuator, multi-axis stage, articulated robot, and continuum robot
A vibrating actuator includes a vibrator and a contact body. The vibrator includes an elastic body and an electrical-mechanical energy transducer. The contact body is long in a predetermined direction and contacts the vibrator. The vibrator and the contact body are relatively moved in the predetermined direction by vibration of the vibrator. An end portion of the long contact body is covered with a viscoelastic body circumferentially with respect to the predetermined direction. |
| US12088219B2 |
Multi-directional energy harvester
An embodiment multi-directional vibration energy harvester includes a fixing part in which fixed discs of a conductive material are stacked spaced apart from each other and electrically connected to each other and a vibration unit in which vibration discs are arranged to be spaced apart from each other with the vibration discs being alternately stacked with the fixed discs, wherein the fixed discs and the vibration discs are arranged so that as an arrangement distance between a vibration disc of the vibration discs and a fixed disc of the fixed discs is changed by an external force, an electron moves between the vibration disc and the fixed disc. |
| US12088218B2 |
Energy harvester
An energy harvester includes an electrode part including a plurality of partition walls spaced apart from one another in a horizontal direction, and spaces defined between the plurality of partition walls, and a cantilever part including a cantilever member having at least a partial region provided in the space defined in the electrode part, the cantilever member includes a plurality of cantilever members, each of the plurality of cantilever members having a first end and a second end, wherein the first end is positioned in the space defined in the electrode part, and wherein the second end is fixedly coupled to a housing, and in which a natural frequency of at least one of the plurality of cantilever members is different from a natural frequency of each of the remaining cantilever members. |
| US12088212B2 |
Power supply circuit, related actuator and method of supplying a load
A power supply circuit for supplying a load, which may be a SMA component or a piezoelectric component, may use short high-voltage pulses to achieve fast heating of the load and, in order to comply with functional requirements, the SMA or piezoelectric component should not be supplied by connecting it directly to an electric line at a relatively high voltage. It is also disclosed an actuator comprising a power supply circuit of this disclosure and at least one load, comprising at least one smart materials chosen between a piezoelectric device and a a shape memory alloy (SMA) component, and a method of supplying a load comprising the steps of: connecting the AC to DC voltage converter of the power supply circuit to the AC mains by closing the input switch for charging a tank capacitor of the converter and, at the same time, opening the output switch for disconnecting the load from the tank capacitor: disconnecting the AC to DC voltage converter of the power supply circuit from the AC mains by opening the input switch and, at the same time, closing the output switch to supply the load by discharging the tank capacitor. |
| US12088210B2 |
Gallium nitride bi-directional high electron mobility transistor in switched mode power converter applications
A switched mode power converter is provided herein and comprises a cycloconverter comprising a plurality of switches, wherein each switch of the plurality of switches is a native four quadrant bi-directional switch with a common drift region configured to allow current flow in a first direction from a first source terminal to second source terminal and in a second direction from the second source terminal to the first direction. |
| US12088209B2 |
Asymmetrical half-bridge flyback converter and power supply system
Embodiments of this application disclose an asymmetrical half-bridge flyback converter and a power supply system, to reduce a loss of the asymmetrical half-bridge flyback converter, and improve efficiency of the asymmetrical half-bridge flyback converter. The asymmetrical half-bridge flyback converter, including: a first power transistor, a second power transistor, a primary-side resonant capacitor, a transformer, a third power transistor, and a secondary-side resonant capacitor, where the first power transistor and the second power transistor are coupled to two terminals of a direct current power supply after being connected in series; and a primary side of the transformer is connected in parallel to two terminals of the first power transistor through the primary-side resonant capacitor, and a secondary side of the transformer is coupled to the third power transistor and the secondary-side resonant capacitor. |
| US12088207B2 |
Power supply circuit
A power supply circuit including a transformer, a transistor controlling an inductor current flowing through a primary coil of the transformer, an integrated circuit configured to switch the transistor, and a feedback circuit configured to, when a load current is smaller and larger than a predetermined value, generate a feedback voltage to cause the output voltage to reach the target level, and to lower the output voltage, respectively. The integrated circuit includes a determination circuit determining whether the transistor operates in a first or second mode, a first overload protection circuit detecting whether the load is in an overload state, based on a power supply voltage and a determination result of the determination indicating the first mode, and a switching control circuit controlling the switching of the transistor, based on the feedback voltage, a determination result of the determination circuit, and a detection result of the first overload protection circuit. |
| US12088202B2 |
Single inductor buck-boost converter with auxiliary capacitor
A buck-boost converter includes a voltage input terminal, a voltage output terminal, a first switch, a second switch, an inductor, a third switch, and an auxiliary capacitor. The first switch includes a first terminal coupled to the voltage input terminal, and a second terminal. The second switch includes a first terminal coupled to the voltage output terminal, and a second terminal. The inductor is coupled between the second terminal of the first switch and the second terminal of the second switch. The third switch includes a first terminal coupled to the second terminal of the second switch, and a second terminal. The auxiliary capacitor is coupled to the second terminal of the third switch. |
| US12088200B2 |
Boost power conversion circuit, method, inverter, apparatus, and system
This application discloses a boost power conversion circuit, a method, an inverter, an apparatus, and a system. In the conversion circuit, a voltage control circuit is added on a three-level boost. The voltage control circuit can be connected in series in a third closed loop, and the third closed loop is a loop including an inductor, a first switching transistor, a flying capacitor, a second diode, and an input end. The voltage control circuit clamps a voltage of a common point of the first diode and the second diode when a voltage on an input end of the boost power conversion circuit is less than a startup voltage of the boost power conversion circuit. The voltage borne by the second diode is reduced, so that a diode with relatively small voltage stress can be selected. |
| US12088198B2 |
Power converter and converting method with light loading state control
A power stage circuit generates an output signal according to an input signal and a control signal. A ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. A calculation circuit generates a calculation signal according to the output signal and a reference signal. The calculation circuit operates in a first mode when the power converter operates in a light loading state, and the calculation circuit operates in a second mode when the power converter operates in a normal state. A control circuit generates the control signal according to the calculation signal and the ramp signal. The control circuit includes a comparator circuit and a control signal generator. The comparator circuit generates a comparison signal according to the calculation signal and the ramp signal. The control signal generator generates the control signal according to the comparison signal. |
| US12088195B2 |
Resonant converter with multiple resonant tank circuits
A resonant converter has a primary resonant tank circuit and a secondary resonant tank circuit. An inverter circuit converts an input DC voltage received by the resonant converter at an input voltage node to a pulsating signal that is fed to the primary resonant tank circuit to generate a resonant tank current that flows through a primary winding of a transformer. The resonant tank current induces current in a secondary winding of the transformer. The induced current is rectified by a rectifier and the rectified signal is filtered to generate an output DC voltage at an output voltage node. The secondary resonant tank circuit is disposed between the secondary winding of the transformer and the output voltage node, and a tank node of the secondary resonant tank is connected to the primary resonant tank circuit through the inverter circuit. |
| US12088193B2 |
Turn-on procedure for a load control device
A load control device may be configured to turn on lighting loads to obtain a fast turn-on time that may be substantially consistent across lighting loads that have different load voltages. The load control device may comprise a power converter circuit configured to produce a voltage across a capacitor, and a control circuit configured to control the power converter circuit to generate the voltage across the capacitor. The control circuit may determine a learned voltage from the magnitude of the voltage across the capacitor. For example, the control circuit may measure the magnitude of the voltage and store the measured voltage as the learned voltage. The control circuit may determine an operating parameter for the power converter circuit as a function of the learned voltage, and control the power converter circuit according to the operating parameter to charge the capacitor until the magnitude of the voltage exceeds a threshold. |
| US12088191B1 |
High side gate driver architecture
A system for driving a plurality of high side NMOS power switches includes a charge pump to generate a boot voltage across a charge pump capacitor and a plurality of high side drivers. Each high side driver includes a PMOS switch to turn on the high side NMOS power switch and an NMOS switch to turn off the high side NMOS power switch. A first inverter chain coupled between the boot voltage and the input voltage generates a first control signal to control the PMOS switch and a second inverter chain coupled between an internal boot voltage and the floating switch node generates a second control signal to control the NMOS switch. The boot voltage can be equal to the input voltage plus a regulator voltage and is substantially independent of a voltage at the floating switch node and the internal boot voltage can be equal to a voltage at the floating switch node plus a regulator voltage. |
| US12088190B2 |
Zero-voltage-switching control circuit, control method and switching power supply
A zero-voltage-switching control circuit for a switching power supply having a main power switch and a synchronous rectifier switch, is configured to: control the synchronous rectifier switch to be turned on for a first time period before the main power switch is turned on and after a current flowing through the synchronous rectifier switch is decreased to zero according to a switching operation of the main power switch in a previous switching period of the main power switch; and where a drain-source voltage of the main power switch is decreased when the main power switch is turned on, in order to reduce conduction loss. |
| US12088187B2 |
Power supply device and method for controlling same
A power supply device is provided. The power supply device includes a rectifier circuit for rectifying an inputted alternating current power supply, a capacitor circuit comprising a first and second capacitor which are connected in series, and smoothing the alternating current power supply rectified in the rectifier circuit, an inverter for converting the output power of the capacitor circuit to a preset power and outputting same, a switch for selectively connecting a middle node of the first capacitor and the second capacitor and an end of the alternating current power, a sensor for detecting a size of the alternating current power, and a controller which confirms a power mode of the alternating current power on the basis of an output value of the sensor, and which controls the switch so that the capacitor circuit multiplies and amplifies the selectively rectified alternating current power based on the confirmed power mode. |
| US12088184B2 |
Current regulator system
An example of a power supply system includes a switching voltage regulator comprising at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The system also includes a current regulator configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch. The system also includes a switch controller configured to provide the switching signal to control the at least one switch based on an amplitude of the output voltage relative to a reference voltage and based on the switching time. |
| US12088183B2 |
Electrical system
An electrical system may include an electronic control unit (ECU), a load driver connected to the ECU and configured to selectively provide a first electrical connection between a power source and a load, and/or a secondary power circuit connected to the ECU and configured to selectively provide a second electrical connection between said power source and said load. The secondary power circuit may include a wake-up circuit including a wake-up circuit switch, a trigger circuit including a trigger circuit switch, a sensing circuit including a sensing circuit switch; a switching circuit including a switching circuit switch; and/or a disable circuit connected to the ECU. The ECU may be configured to control the disable circuit to selectively open the switching circuit switch. The disable circuit may include a first disable circuit switch connected to ground and a second disable circuit switch connected to the switching circuit switch. |
| US12088174B2 |
Motor
Disclosed is a motor comprising: a housing; a stator arranged in the housing; a rotor arranged in the stator; and a first bus bar arranged under the stator, wherein the first bus bar includes a plurality of neutral terminals which are connected to a coil of the stator, are separated by circuitry, and are arranged to be rotationally symmetrical with respect to one another based on the center of the stator. Accordingly, terminals of identical shapes are combined to implement terminals that are respectively connected to four circuits separated from one another, and thus, advantageous effects of ensuring accurate positions of the terminals and simplifying assembling processes are provided during the processes of molding the bus bar. |
| US12088173B2 |
Electric compressor
An electric compressor includes an inverter, a housing with an opening, an inverter connector, a power connector, and a cable that electrically connects both connectors. The housing accommodates the inverter. The inverter connector includes a cover, an outer sealing member, and an inner sealing member. The cover includes an insertion hole through which the cable is inserted, and is disposed in the opening so as to position the cable in the opening. The outer sealing member is interposed between the opening and the cover. The inner sealing member is interposed between the insertion hole and the cable. The insertion hole includes a restriction portion that restricts a movement of the cable, and a fitting portion that is located closer to the inverter than the restriction portion and in which the inner sealing member is fitted. The insertion hole is narrower at the restriction portion than at the fitting portion. |
| US12088169B2 |
Electric drive unit for a motor vehicle
The invention relates to an electric drive unit for a motor vehicle, having two electric drives (5A, 5B), which are arranged in a housing casing (4) of a common drive housing (3) and each comprise a stator and a rotor (8) rotating together with a rotor shaft (8A, 8B). Adjacent shaft ends (10A, 10B) of the rotor shafts (8A, 8B) are rotatingly mounted in a bearing housing (25), which is the central region of a bearing plate (20) arranged in the drive housing (3). In order to create an electrical drive unit having electric drives arranged one behind the other in a common drive housing, which is compact in the longitudinal direction, without disadvantages with respect to the strength of the drive housing being associated therewith, components of the bearing plate (20) are struts (21, 22, 23) which extend from the bearing housing (25) to the outside and connect the bearing housing (25) to the housing casing (4) of the drive housing (3). |
| US12088163B2 |
Stator for an electric machine
A stator for an electric machine, including a shaped rod winding, wherein the shaped rod winding is formed by a plurality of shaped rods which have connecting points in the region of a winding head, wherein the connection points are surrounded by a casting layer, and wherein a thickness of the casting layer is predetermined by an enveloping element which is arranged on the winding head close to the contour. |
| US12088160B2 |
Brushless DC motor with circuit board for winding interconnections
A brushless direct-current (BLDC) motor for a power tool includes a rotor assembly; a stator assembly including a stator having stator teeth forming slots therebetween and stator windings wound around the stator teeth; stator terminals extending substantially parallel to the longitudinal axis from the stator assembly and being substantially aligned with centerlines of the slots of the stator assembly; and a circuit board mounted on the stator terminals adjacent the stator assembly. The circuit board includes conductive traces facilitating a one of a delta or a series connection between the stator windings. An end insulator is provided at an axial end of the stator to electrically insulate the stator from the stator windings, the end insulator including support members to support the stator terminals relative to the stator assembly. The circuit board is mounted and fastened to the support members. |
| US12088159B2 |
Generator with lap windings and segmented permanent magnets
A generator arranged to be driven by an aircraft engine, the generator comprising a stator and a rotor. The stator comprises a stator core and a plurality of slots longitudinally extending in a direction of a longitudinal axis of the stator, for receiving conductors to form windings of the stator, and a plurality of power channels. Each power channel comprises a set of windings having at least a first phase winding including a first set of coils comprising a plurality of conductors wound in a lap winding configuration, the first set of coils having a split phase belt such that the first set of coils comprises at least a first coil and a second coil, the first coil being mechanically shifted with respect to the second coil by a predetermined number of slots of the stator. The rotor comprises a permanent magnet adapted to reduce eddy-current losses. |
| US12088156B2 |
Rotor position-based ramp rate to reduce vehicle harshness during active discharge
A controller, responsive to a signal indicating deactivation of a vehicle and disconnection of a traction battery from an inverter, generates a d-axis current command for the inverter having a ramp portion that defines a rate of change in current magnitude that depends on an electric angle between a rotor and stator of an electric machine. |
| US12088153B2 |
Electric motor system, fan module for a vehicle and electrical connector
The invention relates to an electric motor system (1) for a vehicle, which comprises an electric motor (M) having two power terminals configured to be connected to a power supply line (KL30) and a reference potential line (KL31), and a signal terminal. The electric motor system (1) further comprises a switch element (D) with a first end configured to connect the power supply line (KL30), and a second end connected to a corresponding power terminal of the electric motor (M), and a driving circuit (HS) configured to monitor whether the electric motor (M) has a malfunction and control the switch element (D) correspondingly, a logic portion of a motor driving circuit is configured to be connected and powered by a key line (KL15) carrying a voltage indicative of the ignition status of the vehicle. The invention further provides a fan module for a vehicle. |
| US12088148B2 |
Housing for an electric motor
A motor according to the present application includes a rotor including a magnet, a yoke including an inner side surface around the magnet and having an annular shape, and a holder configured to hold the yoke. The yoke includes an end portion at the holder side in a rotating shaft (X) direction of the rotor. An outer side surface of the holder fits in an inner side surface of the yoke. The end portion of the yoke at the holder side and an outer side surface of the holder engage with each other. |
| US12088147B2 |
Rotating electric machine
A rotating electric machine includes a field element and an armature. The field element includes a magnet portion that includes a plurality of magnets arranged in an array in a circumferential direction. In the magnet, an easy axis of magnetization is oriented in a circular arc shape such that, on a d-axis side closer to a d-axis that is a magnetic pole center, the orientation of the easy axis of magnetization is parallel to the d-axis compared to a q-axis side closer to a q-axis that is a magnetic pole boundary, and a circular-arc-shaped magnet magnetic path is formed along the easy axis of magnetization. The magnet is formed into a circular arc shape when viewed from an axial direction of the rotor, and is provided with a first reference surface that is a planar surface and a second reference surface that is parallel to the first reference surface. |
| US12088144B2 |
Stator for an electric motor
A stator for an electric motor is described. An example stator includes a stator core having teeth that are radially arranged about a common central axis of the stator and located in a spaced apart manner from one another. Each tooth has an inward portion and an outward portion. The example stator further includes an electrically transmissive coil of wire that is wound contiguously upon the inward portions of at least a subset of teeth from the plurality of teeth. The stator also includes wedge members that are radially arranged about the common central axis and located intermittently with the plurality of teeth such that each wedge member abuts with the outward portions of adjacently located teeth. |
| US12088139B2 |
Modularized ESS and power distribution system
A system employing a modular containerized energy-storage systems (ESS) and power cabinet control system allows for long duration uninterruptible power supply (UPS) capabilities for battery and electrochemical storage devices. modular containerized ESS and power cabinet control system. Long duration uninterruptible power supply (UPS) capabilities for battery and electrochemical storage devices may be realized. Embodiments of a modularized energy storage system can comprise a first power cabinet configured to function as a primary power and load balancing appliance. The first power cabinet can comprises power electronics including a DC-AC inverter, transformer, and frequency regulator; a set of one or more energy storage systems, which may be battery-based. |
| US12088137B2 |
Medical device with power-up routine
The present disclosure relates to a method for powering up a medical device powered by a battery. The method includes executing an initial battery test. In the initial battery test, a difference voltage between a battery voltage measured without and with a test load is determined. The test load is favorably dimensioned not to significantly stress the battery. The difference voltage is compared with a difference voltage threshold, the difference voltage threshold being predefined in dependence of the no-test-load voltage. The method further includes providing an alarm if the difference voltage is above the difference voltage threshold. The present disclosure further concerns a medical device that implements the method and a method for determining the relation between the difference voltage and the difference voltage threshold. The disclosure can be used to ensure that an alarm is provided if a newly inserted battery is too weak to power the medical device. |
| US12088135B2 |
Electronic device and control method
An electronic device includes a first control unit, a voltage conversion unit, a power supply unit, and a second control unit. The voltage conversion unit converts the voltage supplied from a power supply device into an output voltage, depending on a voltage of a battery. The power supply unit uses power supplied from the power supply device to charge the battery and supply power to the first control unit. The second control unit controls the power supply unit, to supply power to the first control unit via the voltage conversion unit, in a case where a duty of PWM control exceeds a predetermined threshold, and to supply power to the first control unit without passing through the voltage conversion unit, in a case where the duty of PWM control is less than the predetermined threshold. |
| US12088130B2 |
Electronic devices with multiple energy storage device charging circuits and corresponding methods
An electronic device included a first energy storage device coupled to a second energy storage device by a conductor. A charging node is coupled to the first energy storage device. Another conductor couples the charging node to the second energy storage device. A switch is electrically coupled between the conductor and the second energy storage device. A control circuit opens the switch, thereby allowing a first charging current to flow from the charging node to the first energy storage device through the conductor and a second charging current to flow from the charging node to the second energy storage device through the other conductor and closes the switch when a difference between a voltage of the first energy storage device and a voltage of the second energy storage device is within a predefined voltage difference threshold. |
| US12088125B2 |
Devices and methods for fine-tuning alignment of charging device with implanted medical device
Devices, systems and methods for improved alignment of a charging device for an implanted medical device are disclosed herein. The system can include a charging device that outputs one or more charge parameters during charging to an external user device that outputs an alignment indicator to facilitate fine-tuned alignment of the external charging device. The indicator can be a dynamically updated while adjusting alignment of the charging device. The indicator can includes any of a visual, audio, or haptic output. The user device can be a clinician programmer, patient remote, or a patient's personal computing device. The functionality of the indicator can be incorporated into the charging device itself or distributed across multiple devices to allow fine-tuning of alignment remotely. The alignment feature can be included in a device of a clinical specialist or field technician for troubleshooting alignment problems experienced by some patients. |
| US12088124B2 |
Operating frequency based power level altering in extended range wireless power transmitters
A power transmitter for wireless power transfer includes a control and communications unit configured to provide power control signals to control a power level of a power signal configured for transmission to a power receiver and including a pulse width modulation (PWM) signal generator for determining and selecting the operating frequency from the operating frequency range. The power transmitter further includes an inverter circuit configured to receive a direct current (DC) power and convert the input power to a power signal, coil configured to transmit the power signal to a power receiver, the coil formed of wound Litz wire and including at least one layer, the coil defining, at least, a top face, and a shielding comprising a ferrite core and defining a cavity, the cavity configured such that the ferrite core substantially surrounds all but the top face of the coil. |
| US12088121B2 |
Wireless charging device, method, and system
A wireless power receiving device according to an embodiment of the present specification is a wireless power receiving device that receives wireless power from a wireless power transmission device. The wireless power receiving device: receives wireless power from the wireless power transmission device at an operating frequency through magnetic coupling with the wireless power transmission device; communicates with the wireless power transmission device using at least one of in-band communication using the operating frequency and out-band communication using a frequency other than the operating frequency; transmits a swap inquiry message to the wireless power transmission device through one of the in-band communication and the out-band communication; and receives a response message to the swap inquiry message from the wireless power transmission device through the other of the in-band communication and the out-band communication, and determines whether to swap the wireless power transmission device. |
| US12088118B2 |
Energy-autonomous optical wireless communication system
An optical wireless communication receiver includes one or more harvesting solar cells configured to transform light into electrical power; one or more communication solar cells configured to transform light into an electrical signal embedding information; a rechargeable battery configured to store the electrical power generated by the one or more harvesting solar cells; a communication module configured to decode the electrical signal generated by the one or more communication solar cells and extract the information; a first switch configured to connect the one or more harvesting solar cells to the rechargeable battery for a harvesting-first state, and to the communication module for a communication-second state; a second switch configured to connect the one or more communication solar cells to the communication module for a communication-first state, and to the rechargeable battery for a harvesting-second state; and a microprocessor configured to control the first and second switches. |
| US12088113B2 |
Isolated power supply circuit and control method thereof
The present invention provides an isolated power supply circuit, which includes: a transmitting unit and a receiving unit. The transmitting unit is connected with a voltage source and includes a resonant circuit and a gate voltage division circuit. The gate voltage division circuit includes: a first voltage division branch, wherein one terminal of the first voltage division branch is connected between a first inductor and an input terminal of a first MOS transistor; and a second voltage division branch, wherein one terminal of the second voltage division branch is connected between a second inductor and an input terminal of a second MOS transistor. Therefore, voltages at gates of the first MOS transistor and the second MOS transistor can be changed by regulating voltage division conditions of the first voltage division branch and the second voltage division branch. |
| US12088112B1 |
Wireless charger and a charging method of the wireless charger
A novel wireless charger comprises a charger bracket provided with a first charging module; a mobile phone charging panel provided with a second charging module; a watch charging panel provided with a third charging module; a base provided with a power jack; wherein, the base is provided with an electric slip ring, a gear is sleeved on the electric slip ring, and a clamping pin abutting against the gear is also arranged in the base; the charging method is as follows: a wirelessly-charged mobile phone is placed on the mobile phone charging panel, a wirelessly-charged watch is placed on the watch charging panel, and a wirelessly-charged earphone is placed on the charger bracket. |
| US12088109B2 |
System for the extraction of energy from the electric field of power cables
Systems for extracting electrical energy in power cables, from the electric field, without making electrical contact with the main conductors of the cable, which comprises a power cable and an extraction device of energy from the electric field, which captures the electric field inside the power cable, with alternating or direct voltage. Devices for extracting energy from the electric field. Manufacturing methods of the energy extraction system in power cables from the electric field. Manufacturing methods of the energy extraction device. |
| US12088104B2 |
Energy management system and method of operation thereof
An energy management system and a method of operation thereof are provided. The energy management system includes a receiver that receives power amount information indicating an amount of power generated by a first new and renewable energy power plant, an amount of power stored in a first energy storage device for the first new and renewable energy power plant, an amount of power generated by a second new and renewable energy power plant, and an amount of power stored in a second energy storage device for the second new and renewable energy power plant and a controller that determines an operation mode for each of the first energy storage device and the second energy storage device based on the received power amount information. |
| US12088100B2 |
Method for controlling integrated renewable electric generation resource and charge storage system providing desired capacity factor
Methods for controlling an integrated renewable energy source (RES) and energy storage system (ESS) of a RES-ESS facility having a point of grid interconnect (POGI) limit are provided. A forecast for energy production of the RES as well as a state of charge (SOC) schedule are used to calculate a SOC target-based POGI cap that is less than the POGI limit, with the SOC target-based POGI cap representing as low a peak power output value as possible while still ensuring satisfaction of the SOC schedule. The forecasted RES production, SOC schedule, and SOC target-based POGI cap are used to generate a time-varying charge/discharge control signal for the ESS that ensures the SOC schedule is satisfied. |
| US12088094B2 |
DC-power supply device, DC-powered device, and operating methods
The invention relates to a DC-power supply device (400) for supplying operational DC-power to one or more DC-powered devices that have respective DC-power requirements, that comprises a power interface (402) for providing, via a single twisted-pair wired bus (401), DC output power, a DC-power-supply network communication unit (404) configured to receive DC-power requirement information indicative of a DC-voltage requirement and a DC-current requirement for operation of the respective connected DC-powered devices, and a DC-power-supply control unit (406) configured to drive, in an initialization supply mode, delivery of initialization DC-output power amount, that is suitable for transmission by the DC-powered devices of respective DC-power requirement information, to determine, using the DC-power requirement information and a power-determination rule, and provide an operational DC output power for powering operation of at least one the DC-powered devices in its regular operation mode, thus enabling a powering of multiple DC-powered devices having different DC-power requirements. |
| US12088090B1 |
Electrostatic discharge protection apparatus and method for data transceiver
A physical layer transceiver assembly includes physical layer transceiver circuitry having an input/output terminal configured for coupling to data channel medium, and an electrostatic discharge protection circuit coupled between the terminal and a ground of the assembly. The electrostatic discharge protection circuit includes a reactive filter network coupled to the terminal and configured to selectively limit current flow through the electrostatic discharge protection circuit, and an electrostatic discharge protection device coupled between the reactive filter network and the ground of the assembly. Where the electrostatic discharge protection device is a snapback device, the reactive filter network is configured to limit current at frequencies that adversely affect the snapback device. One implementation of the reactive filter network is a band-stop filter that limits current in a frequency band including the frequencies that adversely affect the snapback device, and passes current at frequencies above and below the frequency band. |
| US12088088B2 |
Electronic delay with stabilized output voltage and over current/short circuit protection
A system includes a circuit breaker and a delay circuit. The circuit breaker has a coil to enable control of a contact to selectively couple a load to a power source responsive to a coil voltage signal applied to the coil. The delay circuit has a depletion mode MOSFET and an energy storage circuit. The depletion mode MOSFET is controlled as an active current sink to provide the coil voltage signal based on a DC voltage signal. The energy storage circuit has an input coupled to a drain of the depletion mode MOSFET, a capacitor, and an output coupled to the drain of the depletion mode MOSFET, the energy storage circuit charges the capacitor from the DC voltage signal and delivers current to the depletion mode MOSFET to delay discontinuation of the coil voltage signal responsive to a drop or discontinuation of the DC voltage signal. |
| US12088083B2 |
Protective circuit equipped with a reflux circuit and a switching circuit and energy storage apparatus containing the protective circuit
A protection circuit 100 of an energy storage apparatus 20 equipped with external terminals 58A, 58B, the protection circuit 100 being equipped with a reflux circuit 110 connected in parallel to a load 12 connected between the external terminals, and also equipped with a switching circuit 120, wherein: the reflux circuit 110 is equipped with a reflux element 111 which causes an induced current produced when the current to the load 12 is blocked to return to the load 12, and a semiconductor switch 115 which is connected in series to the reflux element 111; and the switching circuit 120 switches the semiconductor switch 115 from conducting to blocking after a delay of a prescribed interval from when a reverse voltage is applied to the external terminals 58A, 58B. |
| US12088082B2 |
Integrated circuit-based nano-relay
An integrated circuit-based nano-relay, comprising: an integrated circuit system of the nano-relay constructed according to an integrated circuit module built from a combinational logic circuit. An integrated power data processing algorithm is called by means of the integrated circuit module to perform signal processing on an input power signal, and power service data is output, that is, an integrated circuit is mainly constructed by means of the combinational logic circuit, the protection logic of the nano-relay is achieved by means of a hardware circuit module, and a response speed of the relay is improved. |
| US12088076B2 |
Pivotable and adjustable support for electrical device
A mud ring supports an electrical device with respect to a junction box. The mud ring includes a base member configured to be coupled to the junction box; a cover coupled to the base member for movement between a first position and a second position, the cover including an opening; and an insert positioned in the opening and supported for movement relative to the cover, the insert configured to be coupled to the electrical device. |
| US12088070B2 |
Method and system with two curves for guiding a cable tie
A guide system to enable installation of a cable tie on a supporting element by passing the cable tie through a first passage to traverse the supporting element, then through a second passage to come back to the same side of the supporting element, enabling the cable tie to surround one or more cables. The guide device includes a gutter with a guide surface with two curves, a first longitudinal curve enabling the surface to extend from a passage to the other passage and a second transverse curve forming a partial envelope for receiving the cable tie and guiding and holding the cable tie in the gutter. The device also has at least one protrusion with a wedging surface projecting from the surface of the gutter to come into contact with and wedge against the supporting element to lock the gutter in position in relation to the supporting element. |
| US12088067B2 |
Spark plug
A spark plug includes an insulator having an axial hole, a center electrode disposed in the axial hole and having a forward end portion projecting to a forward end of the axial hole, a tubular metallic shell which holds the insulator on its inner circumference and has a screw portion formed on its outer circumferential surface, and a ground electrode whose first end portion is fixed to a through hole provided in the metallic shell and whose second end portion forms a discharge gap between the second end portion and the forward end portion. The screw portion has a first screw portion located on a rear end of the through hole and a second screw portion located on a forward end of the through hole, and the first screw portion has a pitch diameter larger than that of the second screw portion. |
| US12088063B2 |
Photonic crystal surface-emitting laser
A photonic crystal surface-emitting laser includes a substrate, an n-type cladding layer, an active layer, an index matching layer and a photonic crystal structure. The n-type cladding layer is disposed over the substrate. The active layer is disposed over the n-type cladding layer. The index matching layer is disposed over the n-type cladding layer and is arranged around the active layer. The index matching layer is electrically insulating, and an effective refractive index of the index matching layer is substantially identical to an effective refractive index of the active layer. The photonic crystal structure is disposed over the active layer and the index matching layer. |
| US12088061B2 |
Light source device, drive method, and sensing module
A light source device including a light emitting unit in which multiple light emitting elements including vertical cavity surface emitting lasers are arranged is intended to curb temperature rise. A light source device according to the present technology includes a light emitting unit in which multiple light emitting elements including vertical cavity surface emitting lasers are arranged, and a driving unit that, regarding the light emitting element in the light emitting unit, causes multiple light emitting elements to be caused to emit light in a light emission target period to emit light in a time-divided manner in the light emission target period. By adopting time-division light emission, the number of light emitting elements that are caused to emit light simultaneously is reduced. |
| US12088060B2 |
Multi-wavelength laser generator using ring filter
Embodiments of the present disclosure are directed to multi-wavelength laser generator may produce light with a frequency comb having equally spaced frequency lines. In various embodiments, the laser generator includes first, a semiconductor gain element is used to provide gain to the laser being generated. Second, a ring resonator filter, or ring filter, is used to select the wavelength comb spacing. Third, a narrow-band DBR or narrow-band mirror is used to select the number of wavelengths that lase. Fourth, a wide-band or narrow-band mirror is used to provide optical feedback and to form the optical cavity. Fifth, a phase tuner section is used to align the cavity modes with the ring resonances (i.e. the ring filter modes) in order to reduce or minimize the modal loss. Other embodiments may be described and/or claimed. |
| US12088059B2 |
Light emitting element
A light emitting element comprising a layered structure configured by layering a first light reflecting layer 41 configured by layering a plurality of thin films, a light emitting structure 20, and a second light reflecting layer 42 configured by layering a plurality of thin films, wherein the light emitting structure 20 is configured by layering, from the first light reflecting layer side, a first compound semiconductor layer 21, an active layer 23, and a second compound semiconductor layer 22, a second electrode 32 and an intermediate layer 70 are formed between the second compound semiconductor layer 22 and the second light reflecting layer 42 from the second compound semiconductor layer side, and the value of a surface roughness of a second surface 72 of the intermediate layer 70 in contact with the second light reflecting layer 42 is less than the value of a surface roughness of a first surface 71 of the intermediate layer 70 facing the second electrode 32. |
| US12088058B2 |
Cooling of a laser set
Various embodiments that pertain to cooling of a laser set are described. In one example, the lasers can be a set of laser diodes. A laser diode cooling system can create a vacuum environment that causes a coolant to be below atmospheric pressure. The coolant can be water supplied by an exchangeable tank. When the tank is empty, the tank can be replaced with a new tank. |
| US12088057B2 |
Driving and stabilization system for pump laser
A driving and stabilization system for a pump laser, and a pump laser system. The driving and stabilization system includes a constant current stabilization device, a constant temperature stabilization device, a power detection device, an environment detection device, and a control device. The constant current stabilization device includes a voltage comparison circuit, a constant current driving circuit, and a switch protection circuit. The constant temperature stabilization device includes an internal constant temperature stabilization circuit and an external constant temperature stabilization circuit. |
| US12088056B2 |
Laser light source and laser projector with laser light source
A laser light source includes a nonlinear optical medium and a pump laser source configured to generate a pump laser beam to form a signal beam and an idler beam in the nonlinear optical medium by parametric down conversion. The laser light source further includes a seed light source configured to generate a seed signal beam and/or a seed idler beam having a coherence length lesser than a coherence length of the pump laser beam, and a superpositioning device configured to superposition the seed signal beam and/or the seed idler beam with the pump laser beam for joint coupling into the nonlinear optical medium. |
| US12088055B2 |
Fluid edge cladding for spectroscopic absorption of laser emissions and amplified spontaneous emission
In one embodiment a laser amplifier includes a light pump source that can generate light at a first wavelength or range of wavelengths. The laser amplifier further includes an optically pumped laser amplifier having a gain medium that amplifies light at a second wavelength or range of wavelengths in response to receiving generated light from the light pump source. A housing is used to at least partially surround the gain medium and hold a coolant fluid able to absorb the second wavelength or range of wavelengths. |
| US12088054B2 |
Tailored laser pulse trains for burst-mode illumination
A laser system may include one or more seed lasers to generate a pulsed seed beam. The system may further include a pulse pattern generator to generate an intermediate patterned burst-mode beam from at least one laser pulse from the pulsed seed beam, where the intermediate patterned burst-mode beam includes one or more pulse bursts, and where each of the one or more pulse bursts includes a series of laser pulses with a selected pattern of inter-pulse spacings. The system may further include two or more power amplifiers to amplify the intermediate patterned burst-mode beam to form an amplified patterned burst-mode beam, where at least two of the power amplifiers amplify different portions of the intermediate patterned burst-mode beam, and where the amplified patterned burst-mode beam includes a series of amplified pulse bursts including amplified laser pulses with the selected pattern of inter-pulse spacings. |
| US12088053B2 |
Cable adaptor coaxially connected to an outer conductor and signal line of a cable
Disclosed is a cable adaptor comprising a first member which is conductive and comes into contact with a signal pin of the cable, a second member disposed outside the first member and coupled to the first member, a third member which is conductive and disposed outside the second member, and a contact pin fixed to the first member. Here, the first member includes a first body coupled to the second member and a first contact portion which extends from the first body and comes into contact with the signal pin. The third member includes a second body coupled to the second member and a second contact portion which extends from the second body and comes into contact with the outer conductor. A plurality of first contact points of the signal pin and the first contact portion are arranged at same intervals along a circumferential direction of the signal pin. |
| US12088051B2 |
Electrical male terminal
An electrical male terminal of this invention includes a clamp or crimp area, a main body, and a blade. Protruding members and support members of the main body act as overstress protection. A panel shield member protects a protruding guide member. In another embodiment of this invention, a protruding member extends from a first support member of the main body, and a cut-out portion at the lower portion of the main body accommodates therein the protruding member. Furthermore, in this another embodiment of the electrical male terminal of this invention, a protrusion extends from the unattached end portion of the lever member to protect the electrical male terminal from inadvertently falling out during use. The configuration or shape of the cross-section across the upper portion at the front portion of the main body and the support member at the front portion of the main body of the electrical male terminal is substantially U-shaped. The configuration or shape of the cross-section across the attached portion of the lever member of the electrical male terminal is substantially U-shaped. The electrical male terminal is formed, substantially in its entirety, as a contiguous and continuous single construction having included therein at least the main body, the clamp or crimp area, and the neck area that joins the main body and the clamp or crimp area, and/or the lever member (or tang member) and/or the blade. |
| US12088046B2 |
Backplane connector for providing angled connections and system thereof
A backplane connector includes a shielded design that has wafers with signal terminals supported as edge-coupled terminal pairs for differential signaling. A ground shield is mounted on each wafer and provides a U-channel that partially shields each terminal pair. An insert can be provided to help connect the ground shield to a U-shield to provide U-shaped shielding structure substantially the entire way from a tail to a contact. |
| US12088043B2 |
Easy lock connector with unlock structure
The invention provides an easy lock connector with unlock structure applied to a flat wire and a circuit board. The flat wire has a notch and a ground wire on the two sides of a head end respectively. The easy-lock connector includes an upper housing, a lower housing, a rubber core and a terminal. After the notch of the flat wire is buckled by a stopper of the lower housing, by pressing a pressing member of the upper housing, the pressing member applies an external force to an elastic member of the lower housing to deform the elastic member. An extension arm of the lower housing is linked by the elastic member to cause the stopper to act in one direction so as to release the state of the stopper from locking the gap. In another embodiment, the easy-lock connector can also achieve an electromagnetic shielding effect by adding a shielding iron shell. |
| US12088042B2 |
Connector with supporting member pressing resilient pieces against the wire
The present disclosure provides a connector with which it is possible to suppress an increase in the number of components. A retainer comprises a main body part having a plurality of through-holes through which a plurality of electric wires respectively pass, and a plurality of retaining parts protruding from the main body part and respectively retaining the plurality of electric wires. Each of the plurality of retaining parts has an elastic piece elastically deformable in a second direction crossing a first direction in which the retaining parts protrude. A plurality of supporting members are respectively attached to the outer peripheral surfaces of the plurality of retaining parts. The supporting members each press the elastic piece against the outer peripheral surface of the electric wire. |
| US12088039B2 |
Seal arrangement of a plug-in connection for establishing electrical connections and a device for driving a compressor with the seal arrangement
A seal arrangement for a plug-in connector for establishing electrical connections via a housing, in particular a device for driving a compressor. The seal arrangement exhibits a mounting element to accommodate plug-in connectors for transmitting electrical energy and data, and a sealing element located between the housing and the mounting element. The mounting element is designed with a flange with a sealing surface facing in the direction of the housing. The sealing surface of the flange thus exhibits a first contour and the housing exhibits a second contour in the area of the location of the sealing surface surrounding a pass-through opening. |
| US12088036B2 |
Wiring apparatus and system
An electric metallic tube (EMT) conduit apparatus includes an electric metallic tube (EMT) conduit, a first insulated connector housing attached to a first end of the electric metallic tube (EMT) conduit and a second insulated connector housing attached to a first end of the electric metallic tube (EMT) conduit. The first insulated connector housing includes a plurality of electrically conductive male pins and the second insulated connector housing includes a plurality of electrically conductive female pins. A plurality of conductors within the electric metallic tube (EMT) conduit include a first end attached to one of the male pins of the first insulated connector housing, and a second end attached to one of the female pins of the second insulated connector housing. |
| US12088033B2 |
Electrical plug, electrical device, electrical plug connection, and method for producing an electrical device
An electrical plug forms an electrical plug connection to a coupling that is complementary to the plug. The electrical plug includes a plurality of metal contact elements for electrically contacting an electrical apparatus arranged in a housing, a contact carrier element and a receiving element for receiving the coupling in a receiving space surrounded by the receiving element. The receiving element can be introduced into the housing in a first direction through an opening in the housing. The receiving element, to form the plug, can be brought into engagement in the first direction with the contact carrier element, the contact elements being guided through the contact carrier element and having contact regions which, when the receiving element has been brought into engagement with the contact carrier element, extend into the receiving space, away from the contact carrier element, counter to the first direction. |
| US12088030B2 |
Power connector and power connector assembly
A power connector has a casing, a first power terminal, and a second power terminal. The casing has at least one cable-in opening. The first power terminal has a first inner connecting portion and a first outer connecting portion. The first inner connecting portion is secured in the casing and has a first through hole matrix. The first through hole matrix faces the at least one cable-in opening and has multiple first through holes. The first outer connecting portion is located outside of the casing. The second power terminal is basically the same as the first power terminal. The first power terminal is located between the second power terminal and the at least one cable-in opening. The first power terminal shields part of the second power terminal and allows the second through hole matrix of the second power terminal to be exposed to the at least one cable-in opening. |
| US12088024B2 |
Antenna having high isolation and low cross-polarization level, base station, and terminal
An antenna having high isolation and a low cross-polarization level, a base station, and a terminal are provided. The antenna includes a radiation layer, a feed layer, and an aperture coupling layer disposed between the radiation layer and the feed layer. The aperture coupling layer includes a metal sheet. A first feeding slot, a second feeding slot, and a middle slot are configured in the metal sheet. The middle slot is located between the first feeding slot and the second feeding slot, and is located in a weak electric field region of the metal sheet. The middle slot is configured between the first feeding slot and the second feeding slot of the metal sheet. |
| US12088023B2 |
Radio-related telecommunications systems and methods
This invention discloses two novel antenna assemblies that protect a radio antenna from the elements and permit effective stealthy use with very high performance, and corresponding manufacturing methods. It also discloses a novel assembly for reducing or eliminating radio-frequency interference among electronic equipment such as may be attached to an antenna system, and corresponding manufacturing methods, and systems and methods for model-based radiotelecommunications comprising computing control and command data from one or more multivariate models to operatively control the transmission or reception performance of radioelectronics and antenna systems by computing over the model data to achieve the best performance according to one or more transmission characteristics or user goals. |
| US12088020B2 |
Antenna structure and electronic device using same
An antenna structure is applicable in an electronic device having a metal frame. At least one slot is defined in the metal frame. The antenna structure includes a first radiating portion, a second radiating portion, and an antenna module. The first radiating portion and the second radiating portion are portions of the metal frame. The second radiating portion is separated from the first radiating portion with the at least one slot. The antenna module is spaced from an inner side of the metal frame. A projection of the antenna module is partially overlapping a projection of the first radiating portion or a projection of the second radiating portion in a predetermined direction, the antenna structure excites a plurality of radiation modes. The application also provides an electronic device with the antenna structure. |
| US12088015B2 |
Antenna assembly having antenna elements in helical pattern
An antenna assembly (10) includes a substrate (24) and an array of antenna elements (26). Each antenna element is supported by the substrate at respective locations so that the antenna elements are arranged in space in a helix pattern (28). The helix pattern has a pitch along an axis about which the helix pattern turns. An arc length spacing of the antenna elements along the helix pattern and the pitch are arranged so that, in a transmit mode, a radio frequency (RF) signal fed to each of the antenna elements results in emission of a radiated signal with a rotational wave front from the antenna assembly at a first frequency and a first mode. |
| US12088012B2 |
Apparatus radiating and receiving microwaves with physically preset radiation pattern, and radar apparatus comprising such an apparatus
Apparatus for radiating and/or receiving microwaves and comprising one radiator group with u building blocks with u being an even number, wherein said radiator group has a sandwich-layout comprising a structured layer with q integrated cavities on one side face, with q being an even number, and a structured metal layer covering at least part of said one side face, said u building blocks are structurally identical, said metal layer is structured so that each of said u building blocks comprises a suspended patch-shaped element, which is cavity-backed by one of said q integrated cavities, the shape and size of said patch-shaped elements is defined by boundary slots of said metal layer, said at least one radiator group has a common, central feed point as interface for a hollow waveguide, and wherein said apparatus comprises a hollow waveguide or a waveguide flange being connected to said central feed point. |
| US12088009B2 |
Low-cost higher order floquet structure integrated meander line polarizer and radome
A higher order Floquet-mode structure (HOFS) integrated meander line polarizer and radome including: a substrate including layers having a dielectric constant (dk) of 2.9; a HOFS including metal layers disposed in a first subset of the layers; and meander lines, to provide a phase shift and match, disposed in a second subset of the layers, wherein the substrate includes a low-cost material and the metal layers include a feature trace and gap widths of about 10 mils or greater. |
| US12088008B2 |
Laser cut carbon-based reflector and antenna system
An electromagnetic reflector composed of a non-knitted, non-metallic carbon-based material mesh, antenna system incorporating the reflector and method for fabrication are disclosed. |
| US12088006B1 |
Leaky coaxial cable and indoor distribution system
A leaky coaxial cable according to the present disclosure includes: an inner conductor, a first insulating dielectric layer, an intermediate conductor, a second insulating dielectric layer and an outer conductor arranged from the inside to the outside in proper order, where the inner conductor, the intermediate conductor and the outer conductor are coaxially arranged, periodically slotted holes are opened on several length segments of the outer conductor, the intermediate conductor and the outer conductor construct a leaky transmission channel, and the inner conductor and the intermediate conductor construct a feeder transmission channel. The leaky coaxial cable according to the present disclosure integrates feeder transmission and leaky transmission to have a dual-mode transmission characteristic, and may be used to solve a problem that system capacity cannot be increased when signal coverage is carried out indoors. The present disclosure further provides an indoor distribution system using the above leaky coaxial cable. |
| US12088004B2 |
Image-capturing doorbell device
This document describes an image-capturing doorbell device. In aspects, the image-capturing doorbell device provides a compact, space-efficient, battery-powered, doorbell camera. The architecture of the image-capturing doorbell device is optimized by concentrating sensors at one end of the device and user input mechanism(s) at the opposing end of the device and including a thin and narrow middle portion between the two opposing ends. The sensors include an image sensor and a PIR sensor mounted to the same PCB for space conservation. A camera lens protrudes from an outer surface of an IR window aligned with IR LEDs to mitigate IR flare. The PIR sensor is aligned with a lens that enhances radial motion detection by implementing two stacked rows of lenslets. The user input mechanism includes a light ring formed via a two-shot molding technique with a button to bond the light ring to the button for enhanced waterproofing. |
| US12087999B2 |
Package antenna and radar assembly package
The present disclosure provides a package antenna and a radar assembly package. The package antenna includes a first antenna and a second antenna adjacent to the first antenna. Directivity of electromagnetic wave from the package antenna is achieved through the cancelation of radiation fields from the first and second antennas. |
| US12087998B2 |
Wireless intelligent electronic device
An intelligent electronic device (IED) is provided. The IED includes a metering sub-assembly and an input base module sub-assembly. The metering sub-assembly is hinged to the input base module sub-assembly, where when in an open position, various cables, connectors, and input/output cards/modules are accessible. Various input/output cards/modules are interchangeable to add/change functionality and/or communication capabilities to the IED In one embodiment, a communication card is provided with at least one antenna disposed internal or external to a housing of the IED. |
| US12087997B2 |
Antenna systems for controlled coverage in buildings
Antenna systems for controlled coverage in buildings are disclosed where a data communications network in a building includes one or more external antennas. At least one of the external antennas is disposed on a roof or exterior of the building disposed in or associated with a window, a sky sensor or a digital architectural element. The one or more external antennas are coupled to a network infrastructure of the building via one or more data carrying lines and/or wireless links and are configured for communication with an external wireless network. The network infrastructure includes one or more data carrying lines, one or more network switches, and at least one control panel. In some embodiments, at least one of the external antennas is configured for communication with an external wireless network. |
| US12087993B2 |
Broadband and low cost printed circuit board based 180° hybrid couplers on a single layer board
A hybrid coupler includes a 90° hybrid coupler and a first quarter wavelength conductive stub. The 90° hybrid coupler includes a coupling section, a first input transmission line that is coupled to the coupling section, a second input transmission line that is coupled to the coupling section, a first output transmission line that is coupled to the coupling section and a second output transmission line that is coupled to the coupling section. The first quarter wavelength conductive stub is coupled to the second output transmission line. |
| US12087991B2 |
Substrate integrated waveguide device including a resonance region therein coupled by conductor posts to first and second lines and a transistor coupled between the first and second lines
An aspect of the present invention reduces loss that may occur in cases where electromagnetic waves are guided from one main surface side of a substrate to the other main surface side of the substrate. A waveguide device (10, 10A, 20) includes: a substrate (11); a first conductor layer (12A) and a second conductor layer (12B) which are provided on both main surfaces of the substrate, respectively; a main conductor post (MP) which penetrates between the both main surfaces; and one or more sub-conductor posts (SP) which penetrate between the both main surfaces and which, together with the main conductor post, guide a TEM mode or a quasi-TEM mode. |
| US12087988B2 |
Wiring board
A wiring board including a dielectric line containing a resin (A), and a dielectric exterior covering the dielectric line and containing a resin (B). The dielectric exterior has a relative permittivity lower than a relative permittivity of the dielectric line at 6 GHz and 25° C. |
| US12087987B2 |
Printed circuit boards and methods for manufacturing thereof for RF connectivity between electro-optic phase modulator and digital signal processor
A Printed Circuit Board (PCB) and methods for manufacturing the PCB board are provided. The PCB includes a plurality of layers; a signal pad, at a first layer of the plurality of layers, connected to a signal transmission trace strip line, at a second layer of the plurality of layers, wherein the signal pad is configured to connect to a surface mount Radio Frequency (RF) connector that is configured to interface an RF signal with the signal pad; a PCB ground cage structure through the plurality of layers, surrounding the signal pad; and extended ground reference planes located at the first layer and a third layer of the plurality of layers, wherein the extended ground reference planes extend into a volume of the PCB ground cage structure. |
| US12087986B2 |
Galvanic isolator
An isolator, circuit, and isolation method are disclosed. An illustrative capacitive isolator is disclosed to include an input side that receives an electrical input signal, an output side that outputs an electrical output signal, and an isolation barrier that electrically isolates the input side from the output side. The input side is further disclosed to include an array of input capacitors, where each capacitor in the array of input capacitors receives an input pulse based on the electrical input signal, where each capacitor in the array of input capacitors receives the input pulse offset from input pulses received at others of the capacitors in the array of input capacitors thereby extending a pulse duration of the electrical input signal. |
| US12087980B2 |
System and method for controlling cold start of fuel cell
Disclosed are a system and method for controlling a cold start of a fuel cell. The system includes a fuel cell configured to be supplied with fuel gas and oxidizing gas so as to generate electric power, a main bus terminal configured to electrically connect an output terminal of the fuel cell to a high-voltage battery, accessories, or a driving device so as to output the electric power generated by the fuel cell, a main relay provided at the main bus terminal between the output terminal of the fuel cell and the high-voltage battery, the accessories, or the driving device and configured to electrically connect or cut off the main bus terminal, a COD resistor connected to the main bus terminal at an output terminal side of the fuel cell with reference to the main relay, and a controller configured to supply the electric power generated by the fuel cell to the COD resistor in the state in which the main relay is cut off, and to control the COD resistor to consume the electric power generated by the fuel cell and supplied thereto. |
| US12087978B2 |
Multiple perforation plate for fuel cell separators
A multiple perforation plate for fuel cell separators includes virtual flow path hole central lines spaced apart from each other at a constant interval in a length direction corresponding to a flow direction of reaction gas and formed in a width direction perpendicular to the flow direction of the reaction gas, a plurality of flow path holes formed at a constant interval on the flow path hole central lines in the width direction, and expansion parts formed at both sides of a middle point of each of the flow path holes in the width direction so as to have a greater width in the length direction than that of other points of each of the flow path holes. |
| US12087973B2 |
Energy storage device
An energy storage device may include an electrode assembly including electrodes and separators, wherein the electrodes and separators are alternately stacked in a vertical direction of the energy storage device; an external member accommodating the electrode assembly therein; and electrode leads joined to the electrodes provided in the electrode assembly, the electrode leads are provided in the external member, the electrodes include a positive electrode and a negative electrode, the electrode leads include: a positive electrode lead having one side joined to the positive electrode; and a negative electrode lead having one side joined to the negative electrode, first and second through holes are provided in upper and lower surfaces of the external member, respectively, in the vertical direction, and a portion of the positive electrode lead is provided to face the first through hole in the external member, and a portion of the negative electrode lead is provided to face the second through hole in the external member. |
| US12087971B2 |
Power supply assembly and method for manufacturing the same
The present disclosure relates to a power supply assembly and a method for manufacturing the same. The power supply assembly includes a negative electrode sheet, a separator, and a positive electrode sheet. The negative electrode sheet includes a negative tab, and the positive electrode sheet includes a positive tab, a positive electrode material covering a first foil, a first recess and a second recess. The first recess is formed by removing a positive electrode material covering a first region of the first foil and configured for receiving the positive tab, and a size of the first recess is larger than a size of the positive tab. The second recess is formed by removing a positive electrode material covering a second region of the first foil and configured for receiving the negative tab, and a size of the second recess is larger than a size of the negative tab. |
| US12087969B2 |
Lead acid battery separators having improved rib-profiles, batteries, systems, and related methods
Disclosed herein are exemplary embodiments of improved separators for lead acid batteries, improved lead acid batteries incorporating the improved separators, and vehicles, devices, or systems incorporating the same. A lead acid battery separator is provided with a porous membrane with a plurality of ribs extending from a surface thereon. The plurality of ribs preferably includes both positive ribs and negative ribs having similar heights. The ribs are provided with a plurality of discontinuous peaks arranged such as to provide resilient support for the porous membrane in order to resist forces exerted by active material swelling and thus mitigate the effects of acid starvation associated with such swelling, and increasing the acid availability at the electrodes. A lead acid battery is further provided that incorporates the provided separator. Such a lead acid battery may be a flooded lead acid battery, an enhanced flooded lead acid battery, a gel battery, an AGM battery, and may be provided as operating in a partial state of charge. Systems incorporating such a lead acid battery are also provided, such as a vehicle or any other energy storage system, such as solar or wind energy collection. Other exemplary embodiments are provided such as to have any one or more of the following: increased or improved acid availability, reduced or mitigated acid starvation, and other improvements. |
| US12087968B2 |
Zinc secondary battery and separator for zinc secondary battery
A separator for a zinc secondary battery according to the present disclosure includes a zirconium sulfate-containing porous layer and a porous base material layer that are stacked on each other. The porous base material layer, the zirconium sulfate-containing porous layer, and the porous base material layer may be stacked in this order. The porous base material layer may be a resin porous layer. A zinc secondary battery according to the present disclosure includes the separator for a zinc secondary battery according to the present disclosure. |
| US12087967B2 |
Functional separator, manufacturing method therefor, and lithium secondary battery comprising same
A functional separator capable of improving the capacity and lifetime of a battery by coating a material capable of reducing lithium polysulfide on a separator surface in order to resolve the problems caused by leaching of lithium polysulfide, a preparation method thereof and a lithium secondary battery including the same. The functional separator includes a base separator; a conductive carbon layer on the surface of the base separator; and a metal oxide formed on at least one of an interior and the surface of the conductive carbon layer. |
| US12087966B2 |
Separator for rechargeable battery and lithium rechargeable battery comprising same
This application relates to a separator for a rechargeable battery. The separator includes a porous substrate and a coating layer on at least one surface of the porous substrate. The coating layer includes a binder including a fluorine-based binder and a (meth)acryl-based binder, and a filler. The fluorine-based binder includes a first structural unit derived from vinylidene fluoride and a second structural unit derived from at least one monomer of hexafluoropropylene, chlorotrifluoroethylene, trifluoroethylene, ethylene tetrafluoride, and ethylene monomers, and the second structural unit is included in an amount of 10 wt % or less with respect to the fluorine-based binder. The fluorine-based binder includes a first fluorine-based binder having a weight average molecular weight of 800,000 to 1,500,000 and a second fluorine-based binder having a weight average molecular weight of less than or equal to 600,000. The (meth)acryl-based binder has pencil hardness of 5H or higher. |
| US12087965B2 |
Battery, electric apparatus, and method and device for preparing battery
This application provides a battery, an electric apparatus, and a method and a device for preparing battery, relating to the field of battery technologies. The battery includes a battery cell having an electrode terminal; a fire prevention pipeline, configured to accommodate a fire prevention medium; and a fastener, configured to fasten the fire prevention pipeline. The fastener is connected to the electrode terminal. |
| US12087964B2 |
Battery module
The battery module includes: battery stack including a plurality of batteries that are stacked, each of the plurality of batteries having valve portion; duct plate configured to cover a surface of battery stack on which the plurality of valve portions are disposed, duct plate having gas discharge duct that is connected to valve portions of respective batteries, and temporarily stores a blown-off gas; cover plate placed on duct plate; and flow path portion defined by duct plate and cover plate, flow path portion extending from gas discharge duct and allowing leaking of a gas in gas discharge duct to an outside of battery module. Cover plate is disposed in a state where a predetermined gap is formed between cover plate and first wall portion of gas discharge duct that faces valve portions, and opening that allows an inside of gas discharge duct and the gap to communicate with each other is formed in first wall portion of gas discharge duct. |
| US12087962B2 |
Battery pack and power supply system
Battery pack (10) having a substantially sealed structure includes a plurality of cells (11-16) each having an opened portion provided in order to discharge an internal gas when an internal pressure rises. Non-resettable pressure switch (30, 31) that is connected to controller (50) by a signal line. The pressure switch changes irreversibly from a significant state to a non-significant state when a pressure in battery pack (10) is greater than a predetermined pressure threshold value. |
| US12087961B2 |
Battery-centric virtual grid (VG) system
A battery-centric virtual grid system may include battery modules, each including: one or more battery cells, one or more processors that obtain performance information from the one or more battery cells, the one or more processors configured to identify a respective device being powered by the respective modules from the plurality based on the respective performance information and to determine characteristics of the respective device being powered by the respective module from the plurality based on the performance information or configured to receive data from the respective device powered by the module from the plurality, the one or more transceivers configured to remotely receive and transmit data, thus the respective device becoming part of an IOT network via the respective module, and an enclosure at least partially enclosing the one or more battery cells, the one or more module processors, and the one or more transceivers. |
| US12087957B2 |
Battery, apparatus using battery, and preparation method and preparation device of battery
A battery includes a plurality of battery cells and a support member configured to support the plurality of battery cells. The support member includes a recess. One battery cell of the battery cells extends into and is supported in the recess. |
| US12087955B2 |
Bracket, battery assembly, and power consumption device
A bracket, a battery assembly, and a power consumption device are provided. The bracket is configured for being connected to batteries and a power consumption device body; each of the batteries includes a sealed box body and a battery cell accommodated in the box body; the bracket includes a pair of first beams which are oppositely arranged and at least one support beam, and each support beam is connected to the pair of first beams, the at least one support beam separates a space between the pair of first beams into a plurality of subspaces, the plurality of subspaces are arranged along a length direction of the first beam, each subspace is used for accommodating at least one of the batteries, and each support beam separates two adjacent subspaces and is used for installing the box bodies of the batteries accommodated in the two adjacent subspaces. |
| US12087953B2 |
Secondary battery
Various embodiments of the present invention relate to a secondary battery and aim to simplify the structure of a terminal part to minimize the space taken up by parts inside a case. To this end, provided in the present invention is a secondary battery comprising: an electrode assembly for a prismatic secondary battery; a case for a prismatic secondary battery for accommodating the electrode assembly; a cap plate coupled to the case; and a terminal part which is coupled to a side portion of the electrode assembly and is extendedly bent from the side portion to an upper portion of the electrode assembly, wherein the terminal part includes a bent part which is bent upward from an end part connected to the upper portion of the electrode assembly to protrude out of the cap plate. |
| US12087951B2 |
Electrochemical cell integrates electrolysis and fuel cell functions
An electrochemical cell is provided having an anode, a cathode, and an alkaline electrolyte. The cell is sealed and generates energy via a water-splitting reaction. In accordance with aspects and embodiments, the cathode comprises a surface layer having a first work function and base metal having a second work function. The work function of the surface layer metal is greater than the work function of the base metal. The differences in work functions cause transient charge to travel from the base metal to the surface layer. A double layer of charge forms at the interface of the surface layer and electrolyte that stores energy and drives a water-splitting reaction. Hydrogen gas produced from the water-splitting reaction at the cathode is spontaneously oxidized at the anode, releasing energy, and powering an external load. In some embodiments, the disclosed sealed electrochemical cells may be capable of delivering electrode current densities of 25 mA/cm2 at 0.55V to an external load. |
| US12087945B2 |
Cathode active material for lithium secondary battery and lithium secondary battery including the same
A cathode active material for a lithium secondary battery including a lithium-transition metal composite oxide particle is provided. A crystal grain size of the lithium-transition metal composite oxide particle measured by an XRD analysis is 250 nm or more, and an XRD peak intensity ratio of the lithium-transition metal composite oxide particle is 9.8% or less. A lithium secondary battery including the lithium-transition metal composite oxide particle and having improved life-span and rate capability is provided. |
| US12087943B2 |
Precursor of positive electrode active material for nonaqueous electrolyte secondary batteries and production method thereof and positive electrode active material for nonaqueous electrolyte secondary batteries and production method thereof
Provided is a precursor of a positive electrode active material containing, in a reduced amount, impurities which do not contribute to a charge/discharge reaction but rather corrode a firing furnace and peripheral equipment and thus having excellent battery characteristics and safety, and production method thereof.A method for producing a precursor of a positive electrode active material for nonaqueous electrolyte secondary batteries having a hollow structure or porous structure includes obtaining the precursor by washing nickel-manganese composite hydroxide particles having a particular composition ratio and a pore structure in which pores are present within the particles with an aqueous carbonate solution having a carbonate concentration of 0.1 mol/L or more. |
| US12087938B2 |
Negative electrode for power storage device, power storage device, and electric device
A power storage device having high capacitance is provided. A power storage device with excellent cycle characteristics is provided. A power storage device with high charge and discharge efficiency is provided. A power storage device including a negative electrode with low resistance is provided. A negative electrode for a power storage device includes a number of composites in particulate forms. The composites include a negative electrode active material, a first functional material, and a compound. The compound includes a constituent element of the negative electrode active material and a constituent element of the first functional material. The negative electrode active material includes a region in contact with at least one of the first functional material or the compound. |
| US12087937B2 |
Non-aqueous electrolyte secondary battery
A non-aqueous electrolyte secondary battery according to one aspect of the present invention includes: a positive electrode plate in which a positive electrode mixture layer containing a positive electrode active material is formed on a positive electrode current collector; a negative electrode plate in which a negative electrode mixture layer containing a negative electrode active material is formed on a negative electrode current collector; a separator; a non-aqueous electrolyte; a sealing member; and an outer casing. The negative electrode active material contains graphite and a silicon material. The silicon material contains silicon oxide represented by SiOx (0.5≤x<1.6) and a silicon-lithium silicate composite in which a silicon phase is dispersed in a lithium silicate phase represented by Li2zSiO(2+z) (0 |
| US12087933B2 |
Anodes, cathodes, and separators for batteries and methods to make and use same
Anodes, cathodes, and separators for batteries (electrochemical energy storage devices). The anodes are Li metal anodes having lithiated carbon films (Li-MWCNT) (as dendrite suppressors and protective coatings for the Li metal anodes). The cathodes are sulfurized carbon cathodes. The separators are GNR-coated (or modified) separators. The invention includes each of these separately (as well as in combination both with each other and with other anodes, cathodes, and separators) and the methods of making each of these separately (and in combination). The invention further includes a battery that uses at least one of (a) the anode having a lithiated carbon film, (b) the sulfurized carbon cathode, and (c) the GNR-modified separator in the anode/cathode/separator arrangement. For instance, a full battery can include the sulfurized carbon cathode in combination with the Li-MWCNT anode or a full battery can include the sulfurized carbon cathode in combination with other anodes (such as a GCNT-Li anode). |
| US12087928B2 |
Battery module and battery pack including the same
A battery module according to an embodiment of the present disclosure comprises: a battery cell stack in which a plurality of battery cells are stacked; a U-shaped frame accommodating the battery cell stack and having an open upper portion; and an upper plate covering the battery cell stack at the open upper portion of the U-shaped frame. A surface of the battery cell stack extending parallel to a stacking direction of the plurality of battery cells is mounted on a bottom portion of the U-shaped frame. A stepped portion is formed on one side of the bottom portion of the U-shaped frame, and at least one of the battery cells includes a protruding portion protruding toward the stepped portion. The stepped portion may be formed by a bent portion of the bottom portion of the U-shaped frame. |
| US12087924B2 |
Gas adsorption sheet for secondary batteries
Provided is a gas adsorption sheet for a secondary battery, which contains gas adsorbent particles excellent in gas adsorption property, and allows the gas adsorption performance of the gas adsorbent particles to be sufficiently exhibited. According to one embodiment of the present invention, there is provided a gas adsorption sheet for a secondary battery, including: a heat-resistant base material; and a gas adsorption layer arranged on at least one surface of the heat-resistant base material, wherein the gas adsorption layer contains: a binder resin; and gas adsorbent particles each of which is formed of an inorganic porous material having pores, and is capable of adsorbing a gas. |
| US12087922B2 |
Energy storage device, motor vehicle or monitoring system comprising such an energy storage device, and use of such an energy storage device
Energy storage device, in particular for the starter of an internal combustion engine, includes at least one energy storage element, a data generating unit for acquiring operating parameters of the energy storage device and generating corresponding data, at least one separating device for reversibly separating an electrically conductive connection between the energy storage element and a power source and/or an electrically conductive connection between the energy storage element and a power receiver, and a data transmitting unit for transmitting data between the data generating unit and a data input/output device and between the data input/output device and the separating device, where the separating device is actuated depending on data which is transmitted from the data generating unit and/or the data transmitting unit to the separating device. |
| US12087921B2 |
Vehicular battery charger, charging system, and method providing wireless charging screen
A vehicle battery charger and a vehicle battery charging system are described and illustrated, and can include a controller enabling a user to enter a time of day at which the vehicle battery charger or system begins and/or ends charging of the vehicle battery. The vehicle battery charger can be separate from the vehicle, can be at least partially integrated into the vehicle, can include a transmitter and/or a receiver capable of communication with a controller that is remote from the vehicle and vehicle charger, and can be controlled by a user or another party (e.g., a power utility) to control battery charging based upon a time of day, cost of power, or other factors. |
| US12087919B2 |
Battery balancing apparatus and battery pack including the same
A battery balancing apparatus according to an embodiment of the present disclosure includes a first selection unit to selectively connect each of a plurality of batteries included in a first battery group between a first node and a second node, a resistance adjustment unit to connect a first resistor, a second resistor, a series circuit of the first and second resistors or a parallel circuit of the first and second resistors between the first node and the second node, and a control unit. The control unit determines at least one of the batteries as a first balancing target based on a first voltage signal indicating voltage of each battery. The first selection unit connects the first balancing target between the first node and the second node. The control unit controls the resistance adjustment unit based on a voltage difference between voltage of the first balancing target and a reference voltage. |
| US12087915B2 |
Rechargeable battery features and components
Energy storage devices, battery cells, and batteries of the present technology may include a housing characterized by a first end and a second end opposite the first end. The batteries may include a set of electrodes located within the housing. The set of electrodes may be positioned within the interior region of the housing. The set of electrodes may include a first electrode and a second electrode. The first electrode may include a tab coupled with a surface of the housing at a distal end and coupled with the first electrode at a proximal end. The tab may be coupled with a first surface of the first electrode. A first insulating material may be applied along a second surface of the first electrode across a section corresponding to a location where the tab is coupled with the first electrode. The batteries may also include a cap at least partially contained within the interior region of the housing. The cap may be characterized by a first surface facing the set of electrodes. |
| US12087912B2 |
Secondary battery
To secure ionic conductivity by improving the adhesion between an electrode material mixture and a solid electrolyte and suppressing electrodeposition of lithium. A lithium ion secondary battery (100) includes a positive electrode including an electrode material mixture that fills pores of a metal porous body constituting an electrode current collector, a first solid electrolyte layer including a solid electrolyte that fills pores of a resin porous body, and a negative electrode including an electrode material mixture that fills pores of a metal porous body constituting an electrode current collector. The positive electrode and the negative electrode are alternately stacked with the first solid electrolyte layer provided therebetween. |
| US12087910B2 |
Electrolytes for lithium-ion batteries operating at extreme conditions
Electrolytes for lithium ion batteries with carbon-based, silicon-based, or carbon- and silicon-based anodes include a lithium salt; a nonaqueous solvent comprising at least one of the following components: (i) an ester, (ii) a sulfur-containing solvent, (iii) a phosphorus-containing solvent, (iv) an ether, (v) a nitrile, or any combination thereof, wherein the lithium salt is soluble in the solvent; a diluent comprising a fluoroalkyl ether, a fluorinated orthoformate, a fluorinated carbonate, a fluorinated borate, a fluorinated phosphate, a fluorinated phosphite, or any combination thereof, wherein the lithium salt has a solubility in the diluent at least 10 times less than a solubility of the lithium salt in the solvent; and an additive having a different composition than the lithium salt, a different composition than the solvent, and a different composition than the diluent. In some electrolytes, the nonaqueous solvent comprises an ester. |
| US12087909B2 |
High energy batteries and methods of making the same
Batteries that include an electrolyte, having an electrolytic solvent, and a cathode, the cathode including a first cathode active material in contact with a second cathode active material, and where a ratio of the solubility of the first cathode active material in the electrolytic solvent to the solubility of the second cathode active material in the electrolytic solvent is less than 0.5. The batteries can be economically packed and can provide high energy density. |
| US12087903B2 |
Separator for electricity storage devices, and electricity storage device
A separator for electricity storage devices, which comprises a porous layer that contains a polyolefin resin and an ionic compound, and which is configured such that: the content of the ionic compound in the porous layer is from 5% by mass to 99% by mass (inclusive); and the degree of whiteness of this separator is more than 98.0. |
| US12087896B2 |
Semiconductor light-emitting device
Semiconductor light-emitting device, includes: substrate having base and conductive part; first to third semiconductor light-emitting elements; first to third wires connected to the first to third semiconductor light-emitting elements respectively; and light-transmitting resin part covering the first to the third semiconductor light-emitting elements, wherein the base has main and rear surfaces facing opposite sides in thickness direction of the base, wherein the conductive part includes main surface part on the main surface, wherein the main surface part includes main surface first part where the first and second semiconductor light-emitting elements are mounted, wherein the main surface first part reaches both ends of the main surface in first direction perpendicular to the thickness direction, and wherein the main surface first part is separated from both the main surface part where the third semiconductor light-emitting element is mounted and the main surface part where the first, second, and third wires are connected. |
| US12087888B2 |
Optoelectronic component with a luminescence conversion layer
An optoelectronic component may include at least one light-emitting semiconductor layer sequence and at least one luminescence conversion layer having a transparent conductive oxide and at least one dopant for forming luminescence centers. |
| US12087883B2 |
Display device
According to one embodiment, a display device includes a substrate, an anode electrode, a light emitting element and a reflector plate. The anode electrode is arranged on the substrate. The light emitting element is mounted on the anode electrode. The reflector plate is arranged under the anode electrode, and is arranged to overlap a region where the light emitting element is mounted, in planar view. An anode terminal is arranged on a bottom part and electrically connected to the anode electrode. A cathode terminal is arranged across an entire upper surface on a side opposite to the anode terminal. The anode electrode being smaller than the cathode terminal in a position overlapping the region where the light emitting element is mounted in planar view. |
| US12087876B2 |
Micro-electronic element transfer method
A micro-electronic element transfer apparatus including a first conveyer portion, a second conveyer portion, and a light source device is provided. The first conveyer portion is configured to output a plurality of micro-electronic elements. The second conveyer portion includes a first rolling component and a substrate. The substrate is disposed on the first rolling component and is moved through rolling of the first rolling component. A plurality of bumps are disposed on the substrate. The light source device is configured to irradiate the bumps for heating, and the bumps generate a phase transition. When the micro-electronic elements are outputted from the first conveyer portion, a connection force between the micro-electronic elements and the first conveyer portion is less than a connection force between the micro-electronic elements and the bumps. The micro-electronic elements are respectively bonded to the bumps. A micro-electronic element transfer method is also provided. |
| US12087875B2 |
Method for manufacturing photovoltaic (PV) module
A method for manufacturing a photovoltaic (PV) module includes: using a stringer to simultaneously solder at least two cell strings, and soldering an interconnecting bar at a predetermined position; performing electroluminescence (EL) inspection and appearance inspection/photoluminescence (PL) inspection on cells in the at least two cell strings to obtain cell images and cell inspection results; automatically soldering bus bars at heads and tails of the cell strings; placing the cell modules on front plate glass in sequence, and marking a suspicious cell; when a cell that needs to be repaired exists in the cell modules, sending a repair instruction, and delivering the front plate glass of carrying the cell modules to a repair workstation; at a stacking workstation, soldering together bus bars at tails of two adjacent cell modules; and performing EL inspection and appearance inspection/PL inspection. |
| US12087871B2 |
Microstructure enhanced absorption photosensitive devices
Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more. |
| US12087869B2 |
Assembly for a semiconductor photonic component
The invention relates to an assembly (10) for a semiconductor photonic component (31, 32), wherein the semiconductor photonic component (31, 32) is accommodated in an assembly housing (11) being shielded from the environment. Furthermore, the invention relates to an assembly housing (11) for use with such assembly for a semiconductor photonic component (31, 32). Accordingly, the assembly (10) at least comprising a substrate (30); at least one semiconductor photonic component (31, 32) mounted to the substrate (30), said at least one semiconductor photonic component (31, 32) including a photonic active surface element (31A, 32A); an assembly housing (11) for shielding the substrate (30) and the at least one semiconductor photonic component (31, 32) from the environment; the assembly housing (11) comprises a housing wall part (20, 20) provided with at least one photonic window element (21) facing the photonic active surface element (31A, 32A) of the at least one semiconductor photonic component (31), said at least one photonic window element (21) forming a monolithic part with the housing wall part (20, 20′) and having a transmissivity being larger than the transmissivity of the housing wall part (20, 20′). |
| US12087868B2 |
Epitaxial wafer, method of manufacturing the epitaxial wafer, diode, and current rectifier
An epitaxial wafer, a method of manufacturing the epitaxial wafer, a diode, and a current rectifier are provided. The epitaxial wafer comprises a Si substrate layer; an insulating layer formed on the Si substrate layer; and a nitride semiconductor layer formed on a surface of the insulating layer facing away from the Si substrate layer; wherein the insulating layer has a thickness configured such that under a forward bias voltage, the insulating layer may allow electrons and holes to pass from one side to the other side of the insulating layer via quantum tunneling so as to allow a forward current flow. |
| US12087867B2 |
On-chip diplexed multi-band submillimeter-wave/terahertz sources
A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler. |
| US12087861B2 |
FinFETs and methods of forming FinFETs
An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact. |
| US12087858B2 |
Semiconductor device including stress application layer
A semiconductor device includes a field effect transistor including: a semiconductor substrate including a channel forming region; a gate insulating film formed at the channel forming region on the semiconductor substrate; a gate electrode formed over the gate insulating film; a first stress application layer formed over the gate electrode and applying stress to the channel forming region; a source/drain region formed on a surface layer portion of the semiconductor substrate at both sides of the gate electrode and the first stress application layer; and a second stress application layer formed over the source/drain region in a region other than at least a region of the first stress application layer and applying stress different from the first stress application layer to the channel forming region. |
| US12087857B2 |
Semiconductor device and method for manufacturing the same
The application provides a method for manufacturing a semiconductor device. The method includes the following operations. A semiconductor substrate is provided, a plurality of separate trenches being formed in the semiconductor substrate. Plasma injection is performed to form a barrier layer between adjacent trenches A respective gate structure is formed in each of the plurality of trenches. A plurality of channel regions are formed in the semiconductor substrate, each of the plurality of trenches corresponding to a respective one of the plurality of channel regions. A source/drain region is formed between each of the plurality of trenches and the barrier layer, the source/drain region being electrically connected to the respective one of the plurality of channel regions, and a conductive type of the barrier layer is opposite to a conductive type of the source/drain region. |
| US12087856B2 |
Field effect transistor
A field-effect transistor includes an n-type semiconductor layer that includes a Ga2O3-based single crystal and a plurality of trenches opening on one surface, a gate electrode buried in each of the plurality of trenches, a source electrode connected to a mesa-shaped region between adjacent trenches in the n-type semiconductor layer, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on an opposite side to the source electrode. |
| US12087854B2 |
Vertical semiconductor device with improved ruggedness
A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers. |
| US12087853B2 |
Semiconductor device, method of fabricating the same, and display device including the same
A semiconductor device includes a substrate including a first region and a second region adjacent to the first region, the first and the second regions being disposed in a first direction parallel to an upper surface of the substrate; an etch-stop layer disposed on the first region and the second region; a separation layer disposed on an upper portion of the etch-stop layer, the separation layer being disposed on the first region; a high-electron-mobility transistor (HEMT) element disposed on an upper portion of the separation layer in a second direction perpendicular to an upper surface of the substrate; a light-emitting element disposed on the second region between the substrate and the etch-stop layer; and a plurality of first insulating patterns covering side surfaces of the HEMT element, the plurality of first insulating patterns extending to the etch-stop layer. |
| US12087848B2 |
Power semiconductor device with reduced loss and manufacturing method the same
Power semiconductor device with reduced loss and manufacturing method the same disclosed. Power semiconductor device include a first drift region of a first conductivity type, a second drift region of the first conductivity type formed by epitaxially growing on the first drift region and a plurality of buried ion regions of a second conductivity type formed to be buried in the second drift region. |
| US12087842B2 |
Inner spacer features for multi-gate transistors
A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure. |
| US12087831B2 |
High voltage edge termination structure for power semiconductor devices and manufacturing method thereof
A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region. |
| US12087826B2 |
Method for forming a semiconductor structure
The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A sacrificial layer is formed conforming to the high-k dielectric layer. |
| US12087825B2 |
Metal oxide film and semiconductor device
A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%. |
| US12087822B2 |
Trench SiC MOSFET integrated with high-speed flyback diode and preparation method thereof
A trench SiC MOSFET integrated with a high-speed flyback diode and a preparation method thereof are provided. The MOSFET is a trench structure, a trench-type gate-controlled diode is added in the vicinity of the MOSFET to solve the problem of electric field concentration at the bottom and corners of a trench, and P-type buried layers are added to the bottom of the trench to decrease the electric field intensity. Moreover, the gate-controlled diode and a body diode of the device are connected in parallel, so the on-voltage drop of the body diode is greatly decreased, thus reducing the loss in the reverse recovery mode. In addition, the gate-controlled diode is a unipolar device without the charge-storage effect, so the reverse recovery current of the body diode can be completely eliminated, thus reducing the dynamic loss. |
| US12087820B2 |
Semiconductor device having a plurality of III-V semiconductor layers
A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted. |
| US12087819B2 |
Dual channel structure
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material. |
| US12087817B2 |
High performance 3D vertical transistor device enhancement design
A microfabricated transistor device includes a vertical stack of two or more channels of field effect transistors on a semiconductor substrate. Each of the channels has a vertical conductive path relative to a surface of the semiconductor substrate. At least one of the channels includes a shell formed around a core material, the shell including epitaxial material. The vertical stack can include a channel for a PMOS field effect transistor, and a channel for an NMOS field effect transistor. |
| US12087815B2 |
Crossing multi-stack nanosheet structure and method of manufacturing the same
A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region. |
| US12087810B2 |
Capacitor and electronic device including the same
A capacitor including a lower electrode; an upper electrode apart from the lower electrode; and a between the lower electrode and the upper electrode, the dielectric including a dielectric layer including TiO2, and a leakage current reducing layer including GeO2 in the dielectric layer. Due to the leakage current reducing layer, a leakage current is effectively reduced while a decrease in the dielectric constant of the dielectric thin-film is small. |
| US12087806B2 |
Display device and tiled display device including the same
A display device includes a first substrate including a display area comprising pixels, and a non-display area surrounding the display area, a thin film transistor layer disposed on the first substrate and comprising a thin film transistor, a second substrate disposed on the thin film transistor layer and facing the first substrate, a sealing part disposed between the first substrate and the second substrate in the non-display area, and bonding the first and second substrates, a metal line disposed in the non-display area on the thin film transistor layer and overlapping the sealing part, and an antistatic member comprising a support supported by the metal line, a first receiver protruding from a top portion of the support to an exterior of the sealing part, and a second receiver protruding from a bottom portion of the support toward the exterior of the sealing part and facing the first receiver. |
| US12087800B2 |
Photodector including germanium layer and doped region
A problem to be solved is to make plural Ge PDs uniform in sensitivity by heating based on the Ge PDs with heaters photocurrent measurements taken by a current monitor, and thereby curb deterioration in a common-mode rejection ratio. A photodetector according to the present invention is a germanium photodetector (Ge PD) that uses germanium or a germanium compound in a light absorption layer, the photodetector including two or more Ge PDs placed to receive an input differential signal; a current monitor adapted to measure photocurrents of the two or more Ge PDs; resistors adapted to heat the respective Ge PDs; voltage sources connected to the respective resistors and capable of controlling voltage values independently of each other, wherein the voltage sources are connected with the current monitor, and the voltage sources manipulate voltages applied to the heaters such that current values output by the two or more Ge PDs will match each other. |
| US12087797B2 |
Image sensor structure
An example image sensor structure includes an image layer. The image layer includes an array of light detectors disposed therein. A device stack is disposed over the image layer. An array of light guides is disposed in the device stack. Each light guide is associated with at least one light detector of the array of light detectors. A passivation stack is disposed over the device stack. The passivation stack includes a bottom surface in direct contact with a top surface of the light guides. An array of nanowells is disposed in a top layer of the passivation stack. Each nanowell is associated with a light guide of the array of light guides. A crosstalk blocking metal structure is disposed in the passivation stack. The crosstalk blocking metal structure reduces crosstalk within the passivation stack. |
| US12087796B2 |
Imaging device
An imaging device including: pixel area and a peripheral area that lies outside the pixel area; light receiving element provided in the pixel area; circuit board provided in the pixel area and the peripheral area, the circuit board including a semiconductor substrate and a multilayer wiring layer, the multilayer wiring layer being provided between the semiconductor substrate and the light receiving element; first wiring line provided in the multilayer wiring layer, the first wiring line being electrically coupled to the light receiving element; a protective member that is opposed to the circuit board, the protective member and the circuit board sandwiching the light receiving element; and an extended wiring section provided between the semiconductor substrate and the protective member in the peripheral area, one end of the extended wiring section being open and another end of the extended wiring section being electrically coupled to the first wiring line. |
| US12087795B2 |
Solid-state imaging device and electronic apparatus
A solid-state imaging device is provided that includes a first substrate including at least a first electrode, a first modification layer, a first low-permittivity layer formed on the first modification layer, and a first joint surface where the first electrode and the first modification layer are exposed; and a second substrate including at least a second electrode, a second modification layer, a second low-permittivity layer formed on the second modification layer, and a second joint surface where the second electrode and the second modification layer are exposed. The first modification layer has higher hydrophilicity than the first low-permittivity layer. The second modification layer has higher hydrophilicity than the second low-permittivity layer. The first substrate and the second substrate form a laminate structure and are electrically connected by bonding the first joint surface and the second joint surface. |
| US12087794B2 |
Solid-state imaging device, solid-state imaging device manufacturing method, and electronic device
Provided is a solid-state imaging device capable of further improving reliability of a solid-state imaging device and further reducing manufacturing cost. Provided is a solid-state imaging device including a second semiconductor substrate provided with a photoelectric conversion unit and a second element, a second insulating layer, a first semiconductor substrate provided with a first element, and a first insulating layer arranged in this order from a light incident side, and including a groove formed on the first semiconductor substrate, in which the groove has a first side wall and a second side wall, and a part of at least one side wall of the first side wall or the second side wall extends in an oblique direction with respect to a surface of the first semiconductor substrate on the light incident side. |
| US12087793B2 |
Image sensor including an anti-reflection element and electronic apparatus including the same
An image sensor includes: a sensor substrate including a plurality of first pixels configured to sense light of a first wavelength and a plurality of second pixels configured to sense light of a second wavelength; and an anti-reflection element provided on the sensor substrate, wherein the anti-reflection element includes a plurality of low-refractive index patterns and a high-refractive index layer provided between the plurality of low-refractive index patterns and the sensor substrate. |
| US12087792B2 |
Suppressed cross-talk pixel-array substrate and fabrication method
A reduced cross-talk pixel-array substrate includes a semiconductor substrate, a buffer layer, a metal annulus, and an attenuation layer. The semiconductor substrate includes a first photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first photodiode region. The buffer layer is on the back surface and has a feature located above the first photodiode region with the feature being one of a recess and an aperture. The metal annulus is on the buffer layer and covers the trench. The attenuation layer is above the first photodiode region. |
| US12087791B2 |
Image sensor
An image sensor includes a pixel array including first pixels and second pixels, each of the first and second pixels including photodiodes, a sampling circuit detecting a reset voltage and a pixel voltage from the first and second pixels and generating an analog signal, an analog-to-digital converter image data from the analog signal, and a signal processing circuit generating an image using the image data. Each of the first pixels includes a first conductivity-type well separating the photodiodes and having impurities of a first conductivity-type. The photodiodes have impurities of a second conductivity-type different from the first conductivity-type. Each of the second pixels includes a second conductivity-type well separating the photodiodes and having impurities of the second conductivity-type different from the first conductivity-type. A potential level of the second conductivity-type well is higher than a potential level of the first conductivity-type well. |
| US12087786B2 |
Image sensor and method of fabricating the same
Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate. |
| US12087777B2 |
Systems and methods for a semiconductor structure having multiple semiconductor-device layers
A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate. |
| US12087776B2 |
Semiconductor device and manufacturing method thereof
The method for forming a semiconductor device includes forming gate spacers on a substrate; forming a gate structure on the substrate and laterally between the gate spacers; forming a protective cap over the gate structure and laterally between the gate spacers; forming source/drain structures over the substrate and on opposite sides of the gate structure; depositing a dielectric layer over the protective cap, the gate spacers, and the source/drain structures; performing an etching process on the dielectric layer to form an opening exposing one of the source/drain structures, the etching process further etching a first one of the gate spacers to expose the protective cap; selectively depositing a capping material on the exposed protective cap; forming a source/drain contact in the opening. |
| US12087775B2 |
Gate structures in transistor devices and methods of forming same
A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam. |
| US12087772B2 |
Nanosheet device architecture for cell-height scaling
A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures. |
| US12087766B2 |
Integrated circuit device
An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body. |
| US12087763B2 |
Nitride-based semiconductor bidirectional switching device and method for manufacturing the same
The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions. |
| US12087762B2 |
Nitride semiconductor device
Nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity above the substrate; a second nitride semiconductor layer of a second conductivity different from the first conductivity, above the first nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer; an electron transport layer and an electron supply layer disposed along inner surfaces of the first opening, in stated sequence from the substrate-side; a gate electrode above the electron supply layer, covering the first opening; a source electrode connected to the electron supply layer and the electron transport layer, at a position separated from the gate electrode; and a drain electrode on a surface of the substrate opposite to a surface on which the first nitride semiconductor layer is disposed. At least part of the second nitride semiconductor layer is fixed to a potential different from a potential of the source electrode. |
| US12087760B2 |
Semiconductor devices and methods of manufacturing semiconductor devices
In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region. |
| US12087759B2 |
Low capacitance two channel and multi-channel TVS with effective inter-connection
A transient voltage suppressing device includes a plurality of fingers arranged laterally along a major surface of an epitaxial layer. The plurality of fingers includes fingers of a first type and fingers of a second type. The first type and second type of fingers each include a silicon controlled rectifier (SCR) region and a junction diode region. The plurality of fingers of the second type are conductively coupled together by a second metal layer disposed over top a first metal layer and electrically insulated from the first metal layer. The first metal layer conductively couples the SCR region and junction diode region of the first type of finger. |
| US12087750B2 |
Stacked-substrate FPGA semiconductor devices
A stacked-substrate FPGA device is described in which a second substrate is stacked over a first substrate. Logic transistors (e.g., semiconductor devices and at least some conductive interconnections between them) are generally fabricated on (or over) a first substrate and memory transistors (e.g., SRAM cells and SRAM arrays) are generally fabricated on a second substrate over the first substrate. This has the effect of physically disposing elements of a CLB and a programmable switch on two different substrates. That is a first portion of a CLB and a programmable switch corresponding to logic transistors are on a first substrate and a second portion of these components of an FPGA corresponding to SRAM transistors is on a second substrate. |
| US12087745B2 |
Package structure and manufacturing method thereof
A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction. |
| US12087743B2 |
Light-emitting window element and motor vehicle comprising a light-emitting window element
A light-emitting window element includes a transparent first carrier layer, a transparent second carrier layer, a substrate with a plurality of light-emitting semiconductor chips arranged thereon, and an optical layer having an adjustable transparency. The substrate with the plurality of light-emitting semiconductor chips and the optical layer are arranged between the first and second carrier layers, and the first and second carrier layers, the substrate with the plurality of light-emitting semiconductor chips and the optical layer form a laminate composite. |
| US12087740B2 |
Method of forming a semiconductor module
A method of forming a semiconductor module comprises forming a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Bots transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer. |
| US12087738B2 |
Packaged integrated circuit devices with through-body conductive vias, and methods of making same
A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. |
| US12087729B2 |
Multi-chip package having stress relief structure
A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group. |
| US12087727B2 |
Joint structure in semiconductor package and manufacturing method thereof
A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump. |
| US12087726B2 |
Device and method for joining substrates
A method and device for bonding a first substrate to a second substrate at contact surfaces of the substrates.The method includes the following steps: mounting the first substrate on a first mounting surface of a first substrate holder and mounting the second substrate on a second mounting surface of a second substrate holder, wherein the substrate holders are arranged in a chamber; contacting the contact surfaces at a bond initiation surface; and bonding the first substrate to the second substrate from the bond initiation surface to the centre of the substrates. |
| US12087723B2 |
Diffusion soldering with contaminant protection
A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body. |
| US12087722B2 |
Anisotropic electrically conductive film
An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles. |
| US12087719B2 |
Bond pad with micro-protrusions for direct metallic bonding
A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads. |
| US12087718B2 |
Bump structure having a side recess and semiconductor structure including the same
The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder. |
| US12087715B2 |
Integrated circuit features with obtuse angles and method of forming same
A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch. |
| US12087712B2 |
Method for fabricating an integrated circuit device
A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack. |
| US12087706B2 |
Semiconductor device including groove in termination region
An oxide film (4) is provided on an upper surface of the semiconductor substrate (1). A guard ring (3) is provided on the upper surface of the semiconductor substrate (1). An organic insulating film (6) directly contacts the oxide film (4) in a termination region (7) between the guard ring (3) and an outer edge portion of the semiconductor substrate (1). A groove (8) is provided on the upper surface of the semiconductor substrate (1) in the termination region (7). The groove (8) is embedded with the organic insulating film (6). |
| US12087705B2 |
Package structure with warpage-control element
A package structure is provided. The package structure includes a substrate and a chip-containing structure bonded to the substrate. The package structure also includes a warpage-control element attached to the substrate. The warpage-control element has a protruding portion extending into the substrate. |
| US12087703B2 |
Semiconductor device and in-vehicle electronic control device using the same
In a semiconductor device equipped with a current mirror circuit, a highly reliable semiconductor device capable of suppressing a change in a mirror ratio of the current mirror circuit over time is provided. A current mirror circuit that includes a first MOS transistor and a plurality of MOS transistors paired with the first MOS transistor, and a plurality of wiring layers formed on an upper layer of the MOS transistor are provided. The plurality of wiring layers are arranged such that wiring patterns have the same shape within a predetermined range from an end of a channel region of each of the first MOS transistor and the plurality of MOS transistors. |
| US12087701B2 |
Package module comprising shield film on semiconductor device and method of manufacturing the same
A module is provided that includes a substrate having a first main surface, a first component mounted on the first main surface, a first sealing resin disposed so as to cover the first main surface and the first component, and a shield film covering at least an upper surface of the first sealing resin. The shield film includes a conductive layer, a first protective layer covering the conductive layer, and a second protective layer. The first protective layer is locally formed with a marking section. The second protective layer includes a first region covering the first protective layer and a second region covering the marking section. |
| US12087700B2 |
Embedded die microelectronic device with molded component
Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding. |
| US12087699B2 |
Semiconductor module
A power module (1) providing a half bridge, the power module including: at least one substrate (2) including an inner load track (3), two intermediate load tracks (4) and two outer load tracks (5), each of which load tracks is elongated and extends substantially across the at least one substrate (2) in a first direction (6); wherein the two intermediate load tracks (4) are arranged adjacent to the inner load track (3), and each outer load track (5) is arranged on the opposite side of one of the two intermediate load tracks (4) with respect to a second direction (7) substantially orthogonal to the first direction (6). |
| US12087693B2 |
Non-conductive etch stop structures for memory applications with large contact height differential
Etch stops are disclosed for integrated circuit applications that have a set contacts of varying height, wherein there is a large height differential between the shortest and tallest contacts. In one example, an etch stop is provisioned over a 3D NAND memory staircase structure. The structure is then planarized with an insulator material that can be selectively etched with respect to the etch stop. Contact holes that land on corresponding wordlines of the staircase are etched. Due to the nature of the staircase, the holes vary in depth depending on which step of the staircase they land. The etch stop under the shallowest hole remains intact while the deepest hole is etched to completion. Once all holes have landed on the etch stop, a further etch selective to the insulator material is carried out to punch through the etch stop and expose underlying wordlines. Contacts are deposited into the holes. |
| US12087691B2 |
Semiconductor structures with backside gate contacts
A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions. |
| US12087688B2 |
Semiconductor storage device
A semiconductor storage device includes a first signal line extending in a first direction, and second signal line extending in the first direction and adjacent to the first signal line in a second direction orthogonal to the first direction. The first signal line includes a trunk wiring extending in the first direction, and one or more branch wirings branched from the trunk wiring and extending on one side toward the second signal line in the second direction. |
| US12087683B2 |
Low-dispersion component in an electronic chip
A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping. |
| US12087682B2 |
Power delivery structures
An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate. |
| US12087677B2 |
Molded packaging for wide band gap semiconductor devices
A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe. |
| US12087673B2 |
QFN device having a mechanism that enables an inspectable solder joint when attached to a PWB and method of making same
An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB). |
| US12087671B2 |
Overmolded microelectronic packages containing knurled flanges and methods for the production thereof
Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange. |
| US12087670B1 |
Metal substrates with structures formed therein and methods of making same
In-Substrate Structures (ISS) and isolation regions, including, but not limited to Through Metal Vias (TMV), Dielectric Isolation Vias (DIV), and Dielectric Isolation Pockets (DIP) formed in a metal substrate to provide enhanced operations for semiconductor packages incorporating a metal substrate, and methods of making the same. |
| US12087662B1 |
Semiconductor package structure having thermal management structure
The present disclosure provides a package structure and a method for forming a package structure. The package structure includes a first die having a front surface and a back surface opposite to the front surface; and a thermal management structure over the back surface. The thermal management structure includes a first copper-phosphorous alloy layer thermally coupled to the back surface of the first die. |
| US12087652B2 |
Semiconductor package device and method of manufacturing the same
A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad. |
| US12087651B2 |
Semiconductor device and method of manufacturing the same
An object is to provide a technique capable of suppressing an occurrence of a non-filled portion. A semiconductor device includes a base plate, a case, and a semiconductor element. The semiconductor element is disposed in a space of the base plate and the case. The semiconductor device includes a lead electrode. The lead electrode is connected to an upper surface of the semiconductor element in the space. The semiconductor device includes a raised portion. The raised portion is disposed on an upper surface of the lead electrode in the space. The semiconductor device includes a sealing resin. The sealing resin seals the semiconductor element and the lead electrode in the space. |
| US12087650B2 |
Interposer and semiconductor package including the same
A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad. |
| US12087647B2 |
Compound closed-type metal lid for semiconductor chip package
A compound closed-type metal lid for a semiconductor chip package is provided. The compound closed-type metal lid includes a cover plate, and a frame bottom board. The cover plate has a frame body, and a plurality of riveting holes. The riveting holes penetrate through the frame body and are distributed symmetrically on the frame body. The frame bottom board has a frame body, a plurality of riveting protrusions, and an opening. The riveting protrusions are distributed on an upper surface of the frame body. The cover plate is disposed on an upper surface of the frame bottom board. The riveting protrusions are correspondingly riveted in the riveting holes. |
| US12087644B2 |
Methods of determining process recipes and forming a semiconductor device
In an embodiment, a method includes performing a first atomic layer deposition (ALD) process to form a first material layer over a first blank wafer, the first ALD process comprising: performing a first precursor sub-cycle using a first precursor; performing a first purge sub-cycle using a inert gas; and performing a second precursor sub-cycle using a second precursor and the inert gas; and performing a second purge sub-cycle for a first duration over a second blank wafer different from the first blank wafer using the inert gas to deposit first defects onto the second blank wafer. |
| US12087642B2 |
Selective dual silicide formation
Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions. |
| US12087641B2 |
Method for forming semiconductor structure with fins using a multilayer mask structure for etching to form nanostructures
A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures. |
| US12087632B2 |
Integrated circuitry, memory arrays comprising strings of memory cells, methods used in forming integrated circuitry, and methods used in forming a memory array comprising strings of memory cells
A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed. |
| US12087631B2 |
Method for producing a composite structure comprising a thin monocristalline layer on a carrier substrate
A method for producing a composite structure comprises providing a donor substrate including a single-crystal material, and a support substrate having a first alignment pattern on a face or edge of the support substrate. A heat treatment is applied at least to the donor substrate to bring about a surface reorganization on at least one face of the donor substrate. The surface reorganization results in formation of first steps of nanometric amplitude, which are parallel to a first main axis. The donor substrate and the support substrate are optically aligned, to better than ±0.1° between a locating mark indicating the first main axis on the donor substrate and at least one alignment pattern of the support substrate. The donor substrate and the support substrate are then assembled together, and a thin layer is transferred from the donor substrate onto the support substrate. |
| US12087630B2 |
Chip manufacturing method
A chip manufacturing method includes a modified layer forming step of forming a modified layer and a crack by applying, along planned dividing lines, a first laser beam having a wavelength transmitted through a substrate of a wafer including the substrate and a laminate in a state in which the back surface side of the substrate is exposed and a condensing point of the first laser beam is positioned within the substrate from the back surface side of the substrate, a grinding step of thinning the wafer to a predetermined thickness by grinding the back surface side of the substrate exposed in the modified layer forming step, and a laser-processed groove forming step of forming a laser-processed groove in the laminate by applying, along the planned dividing lines, a second laser beam having a wavelength absorbed by the substrate, from the front surface side of the wafer. |
| US12087626B2 |
High aspect ratio via fill process employing selective metal deposition and structures formed by the same
A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from a physically exposed conductive surface located at a bottom of the via portion of the integrated line-and-via cavity without filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that includes copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity. |
| US12087618B2 |
Method for forming semiconductor die having edge with multiple gradients
A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths. |
| US12087614B2 |
Gap fill dielectrics for electrical isolation of transistor structures in the manufacture of integrated circuits
Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps. |
| US12087612B2 |
Micro device structure and display apparatus
A micro device structure including a device and a fixed structure is provided. The device has an upper surface, a lower surface, and a first side surface. The lower surface is opposite to the upper surface. The first side surface connects the upper surface and the lower surface. The fixing structure includes a connecting portion and a first turning portion. The connecting portion extends at least from the upper surface of the device to the first side surface. The first turning portion is in contact to be connected with a first end of the connecting portion and extends outward from the first side surface to be away from the first side surface. The first end of the connecting portion is located on the first side surface between the upper surface and the lower surface. A display apparatus is also provided. |
| US12087608B2 |
Transfer apparatus and processing system
The present disclosure provides a transfer apparatus and a processing system. The transfer apparatus includes a first transfer assembly configured to transfer a first workpiece to a chamber. The transfer apparatus includes a second transfer assembly configured to transfer a second workpiece from the chamber. The transfer apparatus includes an isolation assembly disposed between the first transfer assembly and the second transfer assembly and configured to isolate energy transfer between the first workpiece and the second workpiece. The transfer apparatus further includes a support assembly configured to restrict the isolation assembly between the first transfer assembly and the second transfer assembly. |
| US12087601B2 |
Reducing line edge roughness and mitigating defects by wafer freezing
A photoresist is developed on a semiconductor wafer. The wafer is introduced into a controlled cold temperature environment and is maintained there until inelastic thermal contraction of the developed photoresist material results in reducing the critical dimension (CD) of the photoresist by not less than 10% from its value before exposure to the controlled cold temperature environment. Then the semiconductor wafer is removed from the controlled cold temperature environment. |
| US12087600B2 |
Thermocouple guide and ceramic heater
A thermocouple guide includes a straight tube portion and a curved tube portion formed in continuation with the straight tube portion to turn an extension direction from the straight tube portion. A cross-section of a tip-side part of the curved tube portion, the tip-side part occupying a predetermined range including a tip end of the curved tube portion, has an external shape that is obtained by linearly cutting both sides of a circle. |
| US12087599B2 |
Substrate processing apparatus and apparatus cleaning method
A substrate processing apparatus includes a processing tub, a storage, a liquid recovery unit, a storage drain line and a liquid recovery unit drain line. The processing tub is allowed to accommodate therein multiple substrates, and configured to store therein a processing liquid. The storage is connected to the processing tub, and configured to store therein the processing liquid drained from the processing tub. The liquid recovery unit is configured to receive the processing liquid overflown from the processing tub. The storage drain line is configured to drain a liquid stored in the storage. The liquid recovery unit drain line is configured to drain a liquid received from the liquid recovery unit to an external drain line provided at an outside. |
| US12087597B2 |
Semiconductor structure comprising various via structures
A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias. |
| US12087596B2 |
Controlling of height of high-density interconnection structure on substrate
An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part. |
| US12087592B2 |
Ambient controlled two-step thermal treatment for spin-on coating layer planarization
To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer. |
| US12087590B2 |
Self-healing polishing pad
Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads. |
| US12087588B2 |
Substrate processing apparatus and substrate processing method
A substrate processing apparatus includes a holder configured to hold a combined substrate in which a first substrate and a second substrate are bonded to each other; a first detector configured to detect an outer end portion of the first substrate; a second detector configured to detect a boundary between a bonding region where the first substrate and the second substrate are bonded and a non-bonding region located at an outside of the bonding region; a periphery removing device configured to remove a peripheral portion of the first substrate as a removing target from the combined substrate held by the holder. |
| US12087586B2 |
Method of forming chromium nitride layer and structure including the chromium nitride layer
Methods and systems for depositing chromium nitride layers onto a surface of the substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a deposition process, depositing a chromium nitride layer onto a surface of the substrate. The deposition process can include providing a chromium precursor to the reaction chamber and separately providing a nitrogen reactant to the reaction chamber. The deposition process may be a thermal cyclical deposition process. |
| US12087584B2 |
Method for forming semiconductor structure
A method for forming a semiconductor structure includes: providing a substrate, a gate dielectric layer and an undoped polycrystalline silicon layer sequentially stacked; performing a thermal doping process, and doping first doping ions in the polycrystalline silicon layer; and performing an ion implantation process, and doping second doping ions in a preset region of the polycrystalline silicon layer. The preset region is spaced at a preset distance from a surface of the polycrystalline silicon layer away from the gate dielectric layer in a direction perpendicular to a surface of the substrate. |
| US12087583B2 |
Semiconductor structure and fabrication method thereof
Embodiments of the present application provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a substrate; a first mask layer positioned on the substrate, wherein the first mask layer has a plurality of discrete first mask patterns; and a second mask layer positioned on the first mask layer, wherein the second mask layer has a second mask pattern, and at least a part of sidewalls of the second mask pattern is positioned on tops of the first mask patterns. |
| US12087581B2 |
Active region, active region array and formation method thereof
Disclosed are an active region, an active region array and a formation method thereof. The active region is formed in a substrate. The active region is provided with a wordline structure. The wordline structure penetrates the active region in a first direction and divides the active region into a source region and a drain region. The source region and the drain region are arranged in a second direction, and a size of the drain region in a third direction is greater than that of the source region in the third direction. An angle between the first direction and the second direction is an acute angle, and the third direction is perpendicular to the second direction. |
| US12087577B2 |
Method for dividing a bar of one or more devices
A method for dividing a bar of one or more devices. The bar is comprised of island-like III-nitride-based semiconductor layers grown on a substrate using a growth restrict mask; the island-like III-nitride-based semiconductor layers are removed from the substrate using an Epitaxial Lateral Overgrowth (ELO) method; and then the bar is divided into the one or more devices using a cleaving method. |
| US12087574B2 |
Oxidative conversion in atomic layer deposition processes
A method for processing a substrate is described. A first reactant in vapor phase is introduced into a reaction chamber having the substrate therein. The first reactant is allowed to be adsorb onto the substrate surface. The non-reactive portion of the first reactant is purged from the reaction chamber after a flow of the first reactant has ceased. The second reactant is introduced in vapor phase into the reaction chamber while the first reactant is adsorbed onto the substrate surface. The second reactant comprises a 1:1:1 ratio of dihydrogen (H2), a nitro-gen-containing reactant, and an oxygen-containing reactant. A plasma is ignited based on the second reactant. The substrate surface is exposed to the plasma. The plasma is extinguished. Gas from the reaction chamber is purged. |
| US12087572B2 |
Etch stop layer
Disclosed are methods for the formation of silicon nitride (SiN) on only the horizontal surfaces of structures such as 3D NAND staircase. This allows for thicker landing pads for subsequently formed vias. In some embodiments, the methods involve deposition of a SiN layer over a staircase followed by a treatment to selectively densify the SiN layer on the horizontal surfaces with respect to the sidewall surfaces. A wet etch is then performed to remove SiN from the sidewall surfaces. The selective treatment results in significantly different wet etch rates (WERs) between the horizontal surfaces and the sidewalls. |
| US12087570B2 |
Method and system for filtering ions defined by a targeted charge to mass ratio
A method of filtering an ion beam to isolate ions having a targeted charge to mass ratio includes providing a quadrupole mass filter device (2), and emitting an ion beam (1′) from a source (1) towards a quadrupole mass filter device (2). An electrical field is applied between the rods (3, 3′) of each pair of opposite rods (3, 3′) of the device (2), each field being defined by combined direct and alternative potentials, calibrating each of the electrical fields in order to create at least one exact focusing point (8) at the exit (5) The method includes generating, by means of rods (3, 3′) which are segmented longitudinally, an electrical field extending between and along each pair of segmented rods (3, 3′), and calibrating the local field segments by adjusting the settings of their respective individual DC and AC potentials in order to create at least one intermediate node. An unstable motion region or region of variable stability (10) is created and maintained in the vicinity of and at said at least one intermediate node location. |
| US12087569B2 |
Time-of-flight mass spectrometry device and analysis method
A time-of-flight mass spectrometry device includes an electrode to which a DC high voltage is applied in order to form an ion flight space and a high voltage power supply device that applies the high voltage to the electrode. The high voltage power supply device includes a high voltage generating circuit that generates the high voltage, and a voltage control circuit that is selectively set to a convergence responsiveness priority mode in which the high voltage generating circuit is controlled such that the high voltage has first convergence responsiveness and first stability or a stability priority mode in which the high voltage generating circuit is controlled such that the high voltage has second convergence responsiveness that is lower than the first convergence responsiveness and second stability that is higher than the first stability. |
| US12087567B2 |
Ion guide with reduced noding effect
An ion optical arrangement (1) for use in a mass spectrometer comprises electrodes (11, 12, 14) comprising a multipole arrangement defining an ion optical axis, and a voltage source for providing voltages to the electrodes to produce electric fields. The ion optical arrangement is configured for producing a radio frequency electric focusing field for focusing ions on the ion optical axis. The radio frequency electric focusing field has a varying frequency so as to reduce any mass dependence of ion trajectories through the ion optical arrangement. The ion optical arrangement may further be configured for producing a static electric field in response to a DC bias voltage applied to the multipole arrangement. A superimposed varying electric field may be produced by superimposing an AC voltage upon the DC bias voltage. |
| US12087565B2 |
Mass spectrometer
An object of the invention is to provide a mass spectrometer capable of preventing a sample from remaining inside an ion source container for a long time. In the mass spectrometer according to the invention, in addition to a first gas used for ionizing an ion source, a second gas flowing toward an exhaust unit along an inner wall of the ion source container is supplied inside the ion source container (see FIG. 1). |
| US12087564B2 |
Tuned synthetic dendrimer calibrants for mass spectrometry
Provided are synthetic dendrimer calibrants for mass spectrometry. The calibrants are distinguished by their relative case and rapidity of synthesis, comparatively low cost, long shelf life, high purity, and amenability to batch synthesis as mixtures. The latter characteristic enables parallel preparation of higher molecular weight compounds displaying useful distributions of discrete molecular weights, thereby providing multi-point mass spectrometry calibration standards. Methods of making, tuning and using said calibrants are provided. |
| US12087563B2 |
Semiconductor processing tool and methods of operation
The physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. During a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. The physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. Additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. |
| US12087557B2 |
Substrate processing system including coil with RF powered faraday shield
A substrate processing system includes a processing chamber including a dielectric window and a substrate support arranged therein to support a substrate. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A Faraday shield is arranged between the coil and the dielectric window. An RF generator is configured to supply RF power to the coil. The coil is coupled by stray capacitance and/or directly coupled to the Faraday shield. A capacitor is connected to one of the coil and the Faraday shield to adjust a position of a voltage standing wave along the coil. |
| US12087556B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus of an embodiment includes a chamber, an introducing part, a substrate electrode, a high-frequency power source, a low-frequency power source, and a switching mechanism. The introducing part introduces a process gas into the chamber. The substrate electrode is disposed in the chamber, a substrate is directly or indirectly mounted on the substrate electrode, and the substrate electrode includes a first and a second electrode elements alternately arranged. The high-frequency power source outputs a high-frequency voltage of 40 MHz or more for ionizing the process gas to generate plasma. The low-frequency power source outputs a low-frequency voltage of 20 MHz or less for introducing ions from the plasma. The switching mechanism applies the low-frequency voltage alternately to the first and the second electrode elements. |
| US12087554B2 |
Substrate treating apparatus and substrate treating system having the same
A substrate treating apparatus, including a process chamber having a bottom portion configured to secure a substrate while a substrate treating process is performed on the substrate; and a dielectric window arranged at an upper portion of the process chamber to define a process space, and including: an insulative body, an antenna disposed on an upper surface of the insulative body, a protection layer disposed on a lower surface of the insulative body, and an etch resistor protruding from at least a portion of the protection layer toward the process space, wherein, based on power being applied to the antenna, a plasma is generated in the process space, and wherein the insulative body is protected from the plasma by the protection layer and the etch resistor. |
| US12087552B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus according to an exemplary embodiment includes a processing container, a stage, an upper electrode, a shower plate, and a waveguide, wherein the stage is provided inside the processing container, the shower plate is provided above the stage with a space in the processing container interposed between the shower plate and the stage, the upper electrode is provided above the shower plate, the waveguide includes an end portion and guides radio-frequency waves in a VHF band or a UHF band therethrough, the end portion is disposed to face the space, and emits the radio-frequency waves to the space, the shower plate includes a plurality of pillars and is made of a dielectric material, gaps are provided inside the shower plate, and the plurality of pillars are disposed in the gaps, respectively. |
| US12087537B2 |
On-load tap changer
An on-load tap changer uninterruptedly switches between winding taps of a tap-changing transformer. The on-load tap changer includes: at least one selector configured to preselect, in a powerless manner, a selected winding tap of the winding taps; at least one diverter switch configured to actually switch loads from a previous winding tap to a preselected winding tap of the winding taps; at least one toothed gearing comprising a first gearwheel and a second gearwheel, the first gearwheel being assigned to the selector, and the second gearwheel being assigned to the diverter switch; and a drive shaft, which is configured to be actuated by a motor drive. The first gearwheel and the second gearwheel are directly interconnected mechanically in such a way that the first gearwheel and the second gearwheel are simultaneously actuatable. The drive shaft is configured to drive either the first gearwheel or the second gearwheel. |
| US12087528B2 |
Enhanced switchgear monitoring and diagnostics in a protection relay
Systems, methods, and computer-readable media are used for monitoring and diagnosing power system assets. An example of a power system asset may include an individual circuit breaker, a switchgear that may include multiple circuit breakers, or any other asset that may be included in a power system. A system for monitoring and diagnosing these power system assets may include one or more intelligent protection relay and switchgear monitor device(s) that may be communicatively coupled in a master-slave or peer-peer configuration in a time-synchronized manner of operation. |
| US12087527B2 |
Switching device on an electric line comprising a vacuum interrupter
A current switch including a main contact including an electrically conductive knife, and an electrically insulating element, fitted in a mobile manner on a first portion of electric line in order to alternatively follow an opening movement and a closing movement; a shunt branch including a first part electrically connected to a second portion of the line, including a vacuum interrupter configured to be actuated alternatively between an open state and a closed state, a second part fitted in a mobile manner on the first part and configured to actuate the vacuum interrupter. During the opening movement, the electrically conductive knife acts upon the second part in order to actuate the vacuum interrupter, and during the closing movement, the electrically insulating element acts upon the second part without actuating the vacuum interrupter. |
| US12087526B2 |
Medium voltage circuit breaker switching pole
A medium voltage circuit breaker switching pole includes: a fixed contact of a vacuum interrupter; a movable contact of the interrupter; and a threaded drive element. The movable contact moves along a longitudinal axis of the interrupter. A center axis of the drive element is parallel to the longitudinal axis of the interrupter. When in an open configuration the fixed contact and movable contact are separated from one another. When in a closed configuration the fixed contact and movable contact are in contact with one another. Rotation of the drive element about its center axis in a first direction is transitions the switching pole from the open configuration to the closed configuration. Rotation of the drive element about its center axis in a second direction counter to the first direction transitions the switching pole from the closed configuration to the open configuration. |
| US12087525B2 |
Low voltage switch pole
Described herein is a switch pole for a low voltage switching device including an insulating casing defining an internal space with a contact area and an arc-extinguishing area of the switch pole, a fixed contact assembly and a movable contact assembly positioned in the contact area and including, respectively, one or more fixed contacts and one or more movable contacts, which can be mutually coupled or uncoupled, and an arc chamber positioned in the arc-extinguishing area that includes a plurality of parallel arc-breaking plates. The insulating casing includes an insulating wall partially separating the contact area from the arc-extinguishing area and a channel connects the contact area to the arc-extinguishing area. The switch pole further includes an additional arc-breaking element anchored to the insulating wall, passing through the channel of the insulating wall and arranged in electrical connection with a terminal arc-breaking plate of the arc chamber. |
| US12087524B2 |
Voltage sensor for electrical switchgear and electrical switchgear comprising same
A circuit breaker includes a capacitive voltage sensor located within its insulating casing. The voltage sensor includes a capacitor located between the terminals of the circuit breaker adjacent a low potential surface provided by a coil of a current sensor. The capacitor is dome shaped. The voltage sensor does not appreciably increase the size or weight of the circuit breaker and is reliable and accurate. |
| US12087520B2 |
Wire distributor-combined tumbler switch device
The present disclosure provides a wire distributor-combined tumbler switch device including a bracket assembly which is fixed to a switch housing bracket installed on a wall surface of a building, a switching-wire distributor module which is coupled to the bracket assembly, is electrically connected to an electric wire of an electric device, regulates power on/off, and is configured to distribute electric wires of a distributing board, and a detachable coupling means configured to detachably couple the switching-wire distributor module to the bracket assembly. |
| US12087518B2 |
Keyboard
A keyboard includes a plurality of keyswitches, a plastic baseplate, and a membrane circuit board. Each keyswitch has a keycap, a lifting mechanism and an elastic member. The lifting mechanism is movably connected to the keycap. The elastic member abuts against the keycap. The plastic baseplate has a first hole formed corresponding to each elastic member and has a connecting structure corresponding to each lifting mechanism. The connecting structure is movably connected to the lifting mechanism to make the keycap movable relative to the plastic baseplate. The membrane circuit board is disposed under the plastic baseplate. Each elastic member passes through the first hole on the plastic baseplate to be disposed on the membrane circuit board. When the keycap is pressed, the elastic member deforms downward to trigger the membrane circuit board. When the keycap is released, the elastic member returns the keycap to its original position. |
| US12087515B2 |
Electrolytic capacitor and method for manufacturing electrolytic capacitor
An electrolytic capacitor that includes a resin molding that includes a capacitor element including an anode, a dielectric layer, and a cathode, a sealing resin sealing the capacitor element; a first external electrode on a first end surface of the resin molding; and a second external electrode on a second end surface and connected to the cathode exposed at the second end surface of the resin molding, wherein when viewed in a thickness direction perpendicular to the length direction, the anode includes a first anode region having a first outer edge exposed at the first end surface and connected to the first external electrode, and a second anode region having a second outer edge positioned closest to the second external electrode in the length direction, and a length of the first outer edge is greater than a length of the second outer edge in a width direction. |
| US12087514B2 |
Electrolytic capacitor and paste for forming conductive layer of electrolytic capacitor
An electrolytic capacitor including a capacitor element. The capacitor element includes an anode body, a dielectric layer covering at least a part of the anode body, a solid electrolyte layer covering at least a part of the dielectric layer, and a cathode lead-out layer covering at least a part of the solid electrolyte layer. The cathode lead-out layer includes a conductive layer. An oxygen permeability of the conductive layer at a thickness of 10 μm is less than or equal to 7 cc/m2·day·atm. |
| US12087513B2 |
Multilayer capacitor
In a multilayer capacitor, when a distance between a surface of a first external electrode at an apex position of the first external electrode and a curved surface is defined as Ht, and a distance between the apex position and an apex position of the main surface in a facing direction of the pair of main surfaces is defined as Y, 0 |
| US12087507B2 |
Current separation method, doping method, and doping apparatus of nonaqueous lithium power storage element
An object of the present disclosure is to provide a doping method in which the status of the progress of a main reaction can be estimated in the lithium carbonate decomposition-type doping step of a nonaqueous lithium power storage element. The separation method, the doping method, and the doping apparatus according to the present disclosure include calculating a capacitor current density iC and an electrode reaction current density iR based on voltage and current of a cell that are measured during doping of the cell. |
| US12087506B2 |
Separators comprising elongated nanostructures and associated devices and methods, including devices and methods for energy storage and/or use
The use of elongated nanostructures in separators and associated devices and methods, including devices and methods for energy storage and/or use, are generally described. According to certain embodiments, the elongated nanostructures can extend from a first solid substrate to a second solid substrate. In some embodiments, the nanostructures penetrate a surface of the first solid substrate (e.g., a first electrode) and/or a surface of the second solid substrate (e.g., a second electrode). The elongated nanostructures can, according to certain embodiments, provide structural reinforcement between two substrates (e.g., between two electrodes) while maintaining electronic insulation between the two substrates. |
| US12087505B2 |
Low-cost linear actuator having a moving printed coil assembly defined on a printed circuit board
A linear actuator includes a magnet housing having first and second planar sides, a front plate and a rear plate, and a base plate covering a channel defined by the magnet housing. A first plurality of magnets is secured to the first planar side and a second plurality of magnets is secured to the second planar side. A linear guide slidably secured to an inner surface of the base plate. A piston assembly has a piston element attached to the linear guide. The piston assembly includes a shaft and a printed circuit board attached to the piston element. The printed circuit board defines a controller and a printed coil assembly. A flex cable is electrically connected to the printed circuit board. The piston assembly is disposed to move linearly during operation of the linear actuator. |
| US12087503B2 |
System and method of flux bias for superconducting quantum circuits
Quantum computing systems require methods to control energies of qubits and couplers for quantum operations. Flux biasing of qubits and quantum couplers is provided for a superconducting quantum computer using single-flux-quantum (SFQ) technology. This method is applicable to a wide range of superconducting qubit structures and couplers, including transmons, fluxoniums, flux qubits, phase qubits and other superconducting qubits. This method enables arbitrary-amplitude time-varying flux biasing of qubits and couplers, due to a sequence of high-speed SFQ pulses. Several preferred embodiments are disclosed which provide high-fidelity control of fast single-qubit and multi-qubit operations. |
| US12087502B2 |
Inductor component
An inductor component comprising a spiral wiring wound on a plane; a first magnetic layer and a second magnetic layer located at positions sandwiching the spiral wiring from both sides in a normal direction relative to the plane on which the spiral wiring is wound; a vertical wiring extending from the spiral wiring in the normal direction to pass through the first magnetic layer; and an external terminal disposed on a surface of the first magnetic layer to connect an end surface of the vertical wiring. The first magnetic layer has magnetic permeability lower than that of the second magnetic layer. |
| US12087499B1 |
Systems and methods for amplifying power
Systems and methods for amplifying power, voltage, and current are provided. A system can include one or more inductors, each inductor including a magnetic core, a primary winding, and a secondary winding. The secondary winding can include two secondary winding wires, and the secondary winding wires can be connected to each other by a connection wire. |
| US12087498B2 |
Module with reversely coupled inductors and magnetic molded compound (MMC)
A device includes a first inductor and a second inductor reversely coupled with the first inductor. The first and second inductors have overlapping windings. The device also includes a housing for the first and second inductor. The housing is filled with a magnetic molding compound. |
| US12087490B2 |
Inductor
An inductor includes a coil including a winding section and extended sections, a body containing the coil and having a bottom surface and end surfaces adjacent to the bottom surface and opposed to each other, and outer electrodes on at least the bottom surface and connected to the extended sections. The winding-axis direction of the coil intersects with the bottom surface. The conductor has a cross section with a rectangular shape defined by thickness and width and has first surfaces defined by its extending direction and the thickness direction and second surfaces defined by the extending direction and the width direction. The winding section is spirally wound such that the second surfaces are on an outer side and on an inner side, respectively, and is wound in two tiers connected in their innermost locations, and both ends are in outermost locations in the tiers, respectively. |
| US12087489B2 |
Transformer designs for very high isolation with high coupling
Various examples are provided related to transformer designs that offer very high isolation while maintaining high coupling between the windings. In one example, an isolation transformer includes a first excitation coil wound around a first core and a second excitation coil wound about a second core. The second core is electrically separated from the first core by a high resistivity magnetic material or a non-conductive material. The first and second cores can include corresponding core segments arranged in a trident geometry or a quindent geometry. The core segments can align when the first excitation coil is inserted into a void of the second excitation coil. The isolation transformer designs are mechanically separable which can result in safe, energized, plug operations. |
| US12087488B2 |
Coil component and electronic component
A coil component includes a magnetic core that includes a pair of wind portions, a pair of coil conductors where respective conductive wires are wound around the wind portions, and a securing member that has spring properties, includes an upper surface portion, first and second side surface portions, and first and second bottom surface portions, and secures the core while surrounding the core. With the securing member removed from the core, angles formed by the upper surface portion and first side surface portion, the upper surface portion and second side surface portion, the first side surface portion and first bottom surface portion, and the second side surface portion and second bottom surface portion are acute angles. The first and second side surface portions are formed by curved surfaces. The first and second bottom surface portions serve as mounted portions when the coil component is mounted over a mounting board. |
| US12087485B2 |
Adjustable inductor and method of using the same
An adjustable inductor including a toroidal core defining a plurality of gaps, a compressible gap material positioned in the gaps, at least one winding wound on the core, a force-applying structure, and a film substantially covering the adjustable inductor. The force-applying structure is operable to apply a force to the core to adjust the gaps and thereby an inductance of the adjustable inductor. The film is configured to prevent movement of force-applying structure when above a predetermined temperature threshold, and allow movement of the force-applying structure when below the predetermined threshold. |
| US12087479B2 |
Metal oxide varistor with reinforced electrodes
A metal oxide varistor (MOV) device including a MOV chip, electrically conductive first and second electrodes disposed on opposite sides of the MOV chip, and electrically conductive first and second leads connected to the first and second electrodes, respectively, wherein the first and second electrodes are formed of a material having a melting point greater than 1100 degrees Celsius. |
| US12087477B2 |
Chip resistor
An object is to provide a chip resistor capable of coping with high power. A chip resistor of the present disclosure includes insulating substrate, a pair of electrodes, and resistance member. A pair of electrodes are provided at both ends of the upper face of insulating substrate. Resistance member is provided on insulating substrate and connected to the pair of electrodes. Insulating substrate has first region in the center thereof and second regions at both ends of first region. Recess is provided in first region of insulating substrate. Resistance member formed in first region has a meandering shape in a top view. At least a part of resistance member is embedded in recess. Trimming groove is provided in resistance member formed in second region. |
| US12087474B2 |
Cable and antenna device with coaxial cable
A cable includes a first shield portion that includes at least one or more lines for transmitting a signal or electric power and that is provided on the outer side of the lines, a first layer that is provided in such a manner as to cover an outer circumference of the first shield portion and that includes a member that absorbs radio waves, a second shield portion that is provided on an outer side of the first layer, a second layer that is provided in such a manner as to cover an outer circumference of the second shield portion and that includes a member that absorbs radio waves, and insulating resin that covers an outer side of the second layer. |
| US12087461B2 |
Power conversion system
A power conversion system for converting thermal energy from a heat source to electricity is provided. The system includes a chamber including an inner shroud having an inlet and an outlet and defining an internal passageway between the inlet and the outlet through which a working fluid passes. The chamber also includes an outer shroud substantially surrounding the inner shroud. The chamber includes a source heat exchanger disposed in the internal passageway, the source heat exchanger being configured to receive a heat transmitting element associated with the heat source external to the chamber, and to transfer heat energy from the heat transmitting element to the working fluid. The system also includes a compressor disposed adjacent the inlet of the inner shroud and configured to transfer energy from the compressor to the working fluid, and an expander disposed adjacent the outlet of the inner shroud. |
| US12087460B2 |
Underground nuclear power reactor with a blast mitigation chamber
An underground nuclear power reactor system has a hollow blast tunnel which extends from one end of a containment member. The system includes a nuclear reactor vessel and other components that may be positioned on a movable support member or on a bottom wall of the containment member. A blast tunnel, which defines a blast chamber, has a plurality of spaced-apart debris deflectors positioned therein. The blast chamber has an upper wall with a roof opening formed therein which is selectively closed by a roof portion. If the reactor needs to be repaired or replaced, the roof portion is opened so that the reactor vessel can pass through the roof opening. If the reactor vessel explodes, a blast therefrom drives debris therefrom through a blast door and into the blast chamber where the deflectors reduce blast force as the debris passes through the blast chamber. |
| US12087459B2 |
Closed-vessel molten salt fission reactor
A closed-vessel molten salt reactor (cvMSR) is described herein. A cvMSR may comprise a suspended container, such as a metallic container, within a trench surrounded by a concrete enclosure and a concrete cover having a number of channels. The container is rotatable between different orientations. The container may be hollow and a solution of fissile materials and salt materials may be provided within the container. The solution may be capable of undergoing a chain reaction nuclear fission process once a threshold temperature is reached. Heat generated by the solution may heat a fluid surrounding the container. The heated fluid may be transported, through the number of channels of the concrete cover, to an external location where the heated fluid may be used in distributing heat and/or electricity generation. |
| US12087456B2 |
Integral vessel isolation valve
A nuclear reactor comprises a nuclear reactor core disposed in a pressure vessel. An isolation valve protects a penetration through the pressure vessel. The isolation valve comprises: a mounting flange connecting with a mating flange of the pressure vessel; a valve seat formed into the mounting flange; and a valve member movable between an open position and a closed position sealing against the valve seat. The valve member is disposed inside the mounting flange or inside the mating flange of the pressure vessel. A biasing member operatively connects to the valve member to bias the valve member towards the open position. The bias keeps the valve member in the open position except when a differential fluid pressure across the isolation valve and directed outward from the pressure vessel exceeds a threshold pressure. |
| US12087455B2 |
Fusion energy device with geodesic deviation gravitational effects
A fusion reactor with a spherical shaped confinement apparatus comprising a plurality of conductive coils that form a rotating negative potential well about a confined center at the center of the system, confining electrons expelled from a surrounding electron discharging grid to obtain a curved spherical rotation pattern to the electrons confined with in the confinement apparatus. The confinement apparatus is also rotated by a multipolar rotating electric machine to promote improved confinement by reducing the amount of time for electrons to escape confinement and shaping the particles in a more curved and spherical shape to allow converging and diverging geodesic effects to enhance tighter and denser particle confinement. This fusion concept reduces the amount of energy needed to operate while minimizing magnetic reconnection disturbances, allowing the NESAR to be the world's first reactor to meet the break-even point of fusion with possible gravitational effects. |
| US12087454B2 |
Systems and methods for the detection and classification of biological structures
A classification model for identifying or classifying biological structures depicted in a base image can be generated by training a label generation model and then using the label generation model to train the classification model. The label generation model can be configured to accept co-registered base and informer images, while the classification model can be configured to accept base images. The classification model can output an indication when a biological structure is identified or classified in a base image. |
| US12087451B2 |
Contact tracing pre-screening method for infectious disease susceptible people based on WiFi matching
Disclosed in the present invention is a contact tracing pre-screening method for infectious disease susceptible people based on WiFi matching. In the method, based on WiFi connection records of a user and a list of anonymous identification codes of confirmed users collected by a mobile device, a judgment on whether a user has an infection risk is given through the steps of record matching, information compression, dangerous WiFi database construction, coincidence rate calculation between the user and a dangerous WiFi, etc. Data required by this method is easy to be obtained for general smart mobile devices, and no special application program is required. Compared with traditional contact tracing methods based on GPS and Bluetooth, this method provides another dimension of information without using an additional device and sensitive data, has higher operating efficiency, and can help to carry out contact tracing more comprehensively and efficiently. |
| US12087449B2 |
Personal pandemic proximity index system and method
The personal pandemic proximity index system and method include a data ingestion pipeline configured to receive location data associated with disease-positive cases, a data processing module configured to clean and process the received data, a personal pandemic proximity module configured to determine a numerical personal pandemic proximity index value associated with an individual having an interaction at an address relative to the location data, and a graphical user interface configured to present, to a patient care team, the numerical personal pandemic proximity index value, which may include a modified workflow to limit the spread of disease. |
| US12087442B2 |
Methods and systems for confirming an advisory interaction with an artificial intelligence platform
A system for confirming an advisory interaction with an artificial intelligence platform. The system includes a constitutional generator module configured to receive a first advisory input, retrieve an expert input, select a machine-learning process as a function of the expert input, and generate a therapeutic corrector. The system includes a constitutional advisory module configured to display a therapeutic corrector on a graphical user interface and receive a second advisory input. The system includes a best practices module the best practices module designed and configured to retrieve from an expert database a best practices training set, calculate an optimal vector output, generate an optimal vector output containing an expected therapeutic corrector implementation response, authenticate a second advisory input, and update the best practices module. |
| US12087440B1 |
Methods and apparatus for utilizing an autonomous vehicle to support contactless medical interactions
According to one aspect, a vehicle includes a chassis and a system configured to cause the vehicle to operate autonomously and carried on the chassis. The vehicle also includes a first compartment carried on the chassis, the first compartment having a first mechanism contained therein and configured to facilitate performing a first procedure. A second mechanism carried on the chassis is also included in the vehicle. The second mechanism is configured to support a telepresence session. In one embodiment, the first procedure is a first medical procedure, and first mechanism is configured to be remotely controlled to perform the first medical procedure. |
| US12087439B2 |
Biological information measuring apparatus
Provided is a living organism information measurement device which users can easily and reliably operate. A living organism information measurement device for acquiring living organism information and generating measurement data relating to the information is provided with a device body, and a panel detachably attached to the device body. The device body comprises a control unit which executes a plurality of functions of the device body, a living organism information measurement unit which is connected to the control unit and generates the measurement data, and a first communication unit connected to the control unit. The panel comprises a second communication unit including a memory storing predetermined information. When the panel is attached to the device body, the first communication unit receives the predetermined information from the second communication unit. The control unit selects and executes a function corresponding to the received predetermined information among the plurality of functions. |
| US12087438B2 |
Liquid dispensing system creating and maintaining a personalized bubble with a defined radius and concentration
A method and device for creating and maintaining a personalised bubble of scent, the method including: providing a wearable device including a perfume reservoir, a perfume dispenser coupled to the perfume reservoir, and a controller to dispense a volume of perfume from the device at intervals; controlling said wearable device to dispense a pulse volume of scent from said perfume reservoir at a pulse interval; and determining said pulse volume and said pulse interval to maintain a mass per unit volume concentration of said perfume above a threshold level within a defined radius from said wearable device. |
| US12087437B1 |
Systems and methods for generating automated real-time graphical user interfaces
Computer-implemented systems and methods are provided for generating automated and real-time graphical user interfaces. A computerized system may include at least one processor configure to perform operations including receiving real-time status information with a identifier, loading a milestone plan including a set of milestone tasks and an initial estimated discharge time period associated with the set of milestone tasks, determining whether the real-time status information indicates completion of the milestone task, updating the milestone plan based on the real-time status information to indicate completion of the milestone task and include one or more remaining milestone tasks, automatically generating information reflecting a graphical representation of the completed milestone task and the one or more remaining milestone tasks, automatically calculating a revised estimated discharge time, and providing the generated interface update information and the revised estimated discharge time for output on the station display. |
| US12087434B2 |
Location-procedure embedding based method for patient in-hospital location and procedure prediction
A method and system for predicting the next location for a patient in a healthcare facility, including: defining a location-procedure co-occurrence matrix for the healthcare facility, wherein the location-procedure co-occurrence matrix define the probability that a procedure will be performed in a specific location; defining a procedure transition matrix, wherein the procedure transition matrix defines the probability of moving from a first procedure to a second procedure; defining a patient input vector based upon the patient condition and procedures performed on the patient; calculating an output vector based upon the patient input vector and the procedure transition matrix; producing a procedure vector by setting all values in the output vector to zero except for the N highest values in the output vector, where N is an integer; calculating a location prediction vector based upon the procedure vector and the location-procedure co-occurrence matrix; and transmitting information regarding the M most likely next locations for the patient to a display device. |
| US12087429B2 |
Surgical planning systems that automatically assess different potential trajectory paths and identify candidate trajectories for surgical systems
Surgical planning systems that automatically identify one or a plurality of different candidate trajectories to a defined intrabody treatment region. The systems can rank the identified candidate trajectories in an order of hierarchy based on defined parameters such as distance from a critical no-go location and whether a single or multiple different candidate trajectories are needed to provide coverage of the defined intrabody treatment region. The surgical planning systems are also configured to provide a User Interface that defines a workflow for an image-guided surgical procedure and allows a user to select one or more of the identified candidate trajectories steps in the workflow. |
| US12087428B2 |
Systems and methods for generating a body degradation reduction program
System for generating a body degradation reduction program including a computing device configured to receive at least a degradation marker, retrieve a body degradation profile as a function of the at least a degradation marker, assign the body degradation profile to a degradation category, identify, using the degradation category and the body degradation profile, a plurality of lifestyle elements, wherein identifying the plurality of lifestyle elements includes calculating a plurality of lifestyle element amounts as a function of a respective effect of each of a plurality of lifestyle elements on the body degradation profile as a function of the degradation category, identifying the plurality of lifestyle elements as a function of the plurality of lifestyle element amounts, and generate a body degradation reduction program, using the plurality of lifestyle elements, wherein the body degradation reduction program includes a frequency and a magnitude of engagement of the plurality of lifestyle elements. |
| US12087419B1 |
Methods and systems to improve patient medication adherence
Methods and systems for improving patient medication adherence by determining when and/or how to intervene with a patient regarding medication adherence are disclosed. An example computer-implemented method for estimating an adherence risk score for a medication taken by a patient includes: receiving, via a network interface from a server configured for determining follow up with patients regarding medication adherence, a request for an adherence risk score for a patient and medication combination, the adherence risk score representing a risk that the patient will not be adherent with taking the medication as prescribed during a time period; obtaining, with one or more processors, pharmacy records for the patient and medication combination; processing the pharmacy records with a machine learning model to determine the adherence risk score; and providing, via the network interface, the adherence risk score to the server. |
| US12087415B2 |
System and method for populating electronic medical records with wireless earpieces
A system, method and wireless earpieces for populating an electronic medical record utilizing wireless earpieces. The sensor measurements are analyzed. The sensor measurements are associated with the electronic medical record of the user. The electronic medical record of the user is populated with the sensor measurements. Communications including the electronic medical record are communicated. |
| US12087413B2 |
Method, apparatus and computer program product for graph-based encoding of natural language data objects
Methods, apparatuses, systems, computing devices, and/or the like are provided. An example method may include retrieving a plurality of natural language data objects from a database; determining, based at least in part on the plurality of natural language data objects and by utilizing an entity extraction machine learning model, a plurality of entity identifiers for the plurality of natural language data objects; determining, based at least in part on the plurality of entity identifiers and by utilizing the entity extraction machine learning model, one or more entity relationship identifiers for the plurality of natural language data objects; generating, based at least in part on the plurality of entity identifiers and the one or more entity relationship identifiers, a graph-based data object for the plurality of natural language data objects; and performing one or more prediction based actions based at least in part on the graph-based data object. |
| US12087409B2 |
Method and system for predicting properties of chemical structures
A method for predicting a property of a sample molecule involves, for each of a multitude of reference molecules, obtaining a multitude of fingerprints and at least one property, and obtaining the multitude of fingerprints of the sample molecule. The method further involves for each of the multitude of reference molecules, using each of the multitude of fingerprints, calculating distances to the sample molecule, and for each of the multitude of reference molecules, determining a relative predictive dominance, based on the distances to the sample molecule. The method also involves, for each of the multitude of reference molecules, determining a fitness value based on the relative predictive dominance, and predicting the at least one property of the sample molecule based on the at least one property of the multitude of reference molecules and the fitness values obtained for the reference molecules. |
| US12087408B2 |
Crystal analysis method, crystal analysis device, and storage medium
A crystal analysis method for a computer to execute a process includes creating a graph that indicates data of repeating unit cell in an ionic crystal and data of an adjacent repeating unit cell that is adjacent to the repeating unit cell; analyzing the ionic crystal based on the graph; and when a number of first intra-cell node that indicates data of an anionic atom bonded to a cationic atom in the repeating unit cell is n, setting a number of second intra-cell node that indicates data of the anionic atom in the repeating unit cell n−1 or less, wherein the data of repeating unit cell includes a plurality of intra-cell nodes that indicate data of atoms in the repeating unit cell, and the plurality of intra-cell nodes include the first intra-cell node and the second intra-cell node. |
| US12087406B2 |
Methods using chromatin-related nucleic acid signals for performing clinical actions
Processes to reveal biological attributes from nucleic acids are provided. In some instances, nucleic acids are used to develop frequency sequence signal maps, construct V-plots, and/or to train computational models. In some instances, trained computational models are used to predict features that reveal biological attributes. |
| US12087405B2 |
Methods of processing a biofluid sample
Disclosed herein are methods and compositions for processing biofluid samples. Some such methods may include obtaining a biofluid sample from a subject having a disease state such as lung cancer. The biofluid sample may be contacted with a nanoparticles to adsorb proteins. The proteins may then be ionized or contacted with a detection reagent. Also disclosed herein are compositions comprising proteins coupled to a nanoparticle upon contact of the nanoparticle with a biofluid sample from a subject having a disease. |
| US12087403B2 |
DNA alignment using a hierarchical inverted index table
System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match. |
| US12087396B2 |
Memory system
A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads. |
| US12087390B2 |
Storage device based on daisy chain topology
Embodiments of the present disclosure relate to a storage device based on a daisy chain topology. According to embodiments of the present disclosure, a storage device may include a plurality of memory package chips each including a plurality of memory dies capable of storing data; and a controller communicating with the plurality of memory package chips and connected to the plurality of memory package chips through one or more daisy chain circuits. |
| US12087388B2 |
Method of performing internal processing operations with pre-defined protocol interface of memory device
A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode. |
| US12087387B2 |
Methods and systems for managing read operation of memory device with single ended read path
A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal. |
| US12087384B2 |
Bias voltage generation circuit for memory devices
The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers. |
| US12087381B2 |
Systems and methods for detecting and configuring lanes in a circuit system
An electronic circuit system includes a main device that generates first and second strobe signals and a clock signal, a first peripheral device that uses the first strobe signal to generate a first output signal in a first lane in response to the clock signal, and a second peripheral device that uses the second strobe signal to generate a second output signal in a second lane in response to the clock signal. The main device determines if the first peripheral device is coupled to the main device through the first lane based on the first output signal. The main device determines if the second peripheral device is coupled to the main device through the second lane based on the second output signal. The main device also has the ability to detect if a peripheral device is faulty and to select a valid configuration of peripheral devices. |
| US12087378B2 |
Bit selection for power reduction in stacking structure during memory programming
Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address. |
| US12087373B2 |
Non-volatile memory with optimized erase verify sequence
An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit. |
| US12087369B2 |
Power state aware scan frequency
A system can include a memory device and a processing device to perform operations that include detecting a transition associated with the memory device from a first power state to a second power state. Responsive to detecting the transition from the first power state to the second power state, the operations include determining a value of a scan frequency in view of the second power state, wherein one or more scan iterations are initiated in accordance with the value of the scan frequency. The operations further include performing one or more block family calibration operations in accordance with the value of the scan frequency. |
| US12087365B2 |
Modulation of source voltage in NAND-flash array read
Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle. |
| US12087364B2 |
Semiconductor device with a memory capable of batch erasing a plurality of sectors and method of manufacturing the same
A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasing is succeeded or not, and a control block configured to control the flash memory. The control block includes a batch erasing range control circuit indicating a collectively erased range in the flash memory. When the verification result signal VR indicates failure of erasing of sectors in a first range specified by the batch erasing range control circuit after the erasing is executed, a second range for which erasing is to be executed again is calculated on the basis of a failure sector address that specifies a sector for which the erasing is failed and an end sector address that specifies an end of the first range, the specified second range is set to the batch erasing range control circuit, and erasing sectors in the second range is executed. |
| US12087363B2 |
Control gate signal for data retention in nonvolatile memory
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential. |
| US12087358B2 |
Access line grain modulation in a memory device
Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device. |
| US12087350B2 |
Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration
Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction. |
| US12087348B2 |
Dynamic random access memory (DRAM) structure with body bias voltage that can be adapted to the access pattern of cells
Disclosed is an adaptive application of bias voltages to the access transistors in the cells in dynamic random access memory (DRAM) structures, according to the access pattern of the rows, in other words, whether the rows are accessed and/or how often rows are accessed. |
| US12087347B2 |
Methods for adjusting row hammer refresh rates and related memory devices and systems
Methods of operating a memory device are disclosed. A method may include determining an amount of activity associated with at least one memory bank of a memory device. The method may further include adjusting a row hammer refresh rate for the at least one memory bank based on the amount of activity associated with the at least one memory bank. Memory devices and systems are also described. |
| US12087346B2 |
Memory device
A memory device includes a memory cell array, a row select circuit, a refresh controller and a memory control logic. The memory cell array includes memory cells arranged in rows and columns. The row select circuit is connected to the rows. The refresh controller controls the row select circuit to apply a refresh operating voltage to one or more rows. The memory control logic decodes a command received from a memory controller and outputs a refresh command and external refresh address information. The refresh controller controls the row select circuit to perform one of an external refresh operation and an internal refresh operation, based on the refresh command that is output from the memory controller and based on whether a first row-hammering row address of the internal refresh operation is identical with a second row-hammering row address of the external refresh operation. |
| US12087345B2 |
Balanced negative bitline voltage for a write assist circuit
A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline. |
| US12087342B2 |
Aluminum alloy disc blank for magnetic disc and magnetic disc
An aluminum alloy disc blank for a magnetic disc made of an aluminum alloy containing Fe: 0.005 to 1.800 mass % with the balance being Al and inevitable impurities, wherein a flatness change of the aluminum alloy disc blank for a magnetic disc when the aluminum alloy disc blank for a magnetic disc is held in the atmosphere at 50° C. or lower for 336 hours is 2.0 μm or less. |
| US12087341B2 |
Magnetic recording medium and magnetic read/write apparatus
A magnetic recording medium includes a substrate, an underlayer formed on the substrate, and a magnetic layer formed on the underlayer. The magnetic layer includes an alloy having a L10 structure. The underlayer includes a first underlayer and a second underlayer. The first underlayer includes Mo and Ru, the content of Ru in the first underlayer is in a range of 5 atom % to 30 atom %, and the second underlayer includes a material having a body-centered cubic (BCC) structure. The second underlayer is formed between the first underlayer and the substrate. |
| US12087332B2 |
Timecode generation and assignment
A timecoding technique for determining and assigning timecodes for variable frame rate video. Content identified for timecode assignment is decoded, and for sequential frames of the content, portions of timestamps are compared to determine if the frames are from a same time period (e.g., from the same second in time). For a subsequent frame from the same time period, an index is atomically incremented, a timecode generated from a combination of the time period and the index, and the timecode assigned to the frame. For a subsequent frame from a different time period, the index is initialized, a timecode generated from a combination of the different time period and the initialized index, and the timecode assigned to the frame. Accumulated durations of frames may be used in place of timestamps, in some instances. |
| US12087331B2 |
Retaining high resolution tape directory in overwritten end of data set
An End of Data Set (EOD) including a High Resolution Tape Directory (HRTD) is written at a position next to a last written user data set on a tape. When appending a new user data set, the new user data set is written starting from a position next to an end longitudinal position (LPOS) of the EOD to generate an overwritten EOD. |
| US12087325B2 |
Image capture device, recording device, and display control device
An image capture device for recording HDR (high dynamic range) image data obtained through image capture performs control so as to, when encoding HDR image data obtained by capturing an image with an image sensor, divide part of the HDR image data corresponding to a coding area to be encoded into a plurality of divided HDR image data, encode each of the plurality of divided HDR image data by using encoding means, and record the plurality of divided HDR image data that are encoded on a recording medium in a predetermined recording format. |
| US12087322B2 |
Method and system for sentiment analysis of natural language inputs
A method for providing sentiment analysis of a natural language service request to automatically identify and map a user state of mind by utilizing artificial intelligence is disclosed. The method includes receiving, via a graphical user interface, a raw input, the raw input including a computer file corresponding to a natural language request; parsing the raw input into component parts; annotating, by using a model, each of the component parts with a predetermined indicator, the predetermined indicator corresponding to the user state of mind; mapping, by using the model, the component parts based on the predetermined indicator; compiling the mapped component parts into a structured input, and determining, by using the model, a quality that corresponds to the structured input. |
| US12087318B1 |
Voice controlled system
A distributed voice controlled system has a primary assistant and at least one secondary assistant. The primary assistant has a housing to hold one or more microphones, one or more speakers, and various computing components. The secondary assistant is similar in structure, but is void of speakers. The voice controlled assistants perform transactions and other functions primarily based on verbal interactions with a user. The assistants within the system are coordinated and synchronized to perform acoustic echo cancellation, selection of a best audio input from among the assistants, and distributed processing. |
| US12087316B2 |
Vehicle quality problem management system and method for processing data thereof
The present disclosure relates to a vehicle quality problem management system and a data processing method thereof. The system includes a management server including a server communication device that performs wireless communication with a mobile device, and a server processing device connected to the server communication device, and the server processing device receives a voice signal containing a current quality problem from the mobile device, converts the current quality problem in the voice signal to text using speech to text (STT), and registers the current quality problem converted into the text in a database (DB). |
| US12087310B2 |
Apparatus and method for providing enhanced guided downmix capabilities for 3D audio
An apparatus for downmixing three or more audio input channels to obtain two or more audio output channels is provided. The apparatus includes a receiving interface for receiving the three or more audio input channels and for receiving side information. Moreover, the apparatus includes a downmixer for downmixing the three or more audio input channels depending on the side information to obtain the two or more audio output channels. The number of the audio output channels is smaller than the number of the audio input channels. The side information indicates a characteristic of at least one of the three or more audio input channels, or a characteristic of one or more sound waves recorded within the one or more audio input channels, or a characteristic of one or more sound sources which emitted one or more sound waves recorded within the one or more audio input channels. |
| US12087309B2 |
Method and system for lossless value-location encoding
A method of encoding samples in a digital signal is provided that includes receiving a frame of N samples of the digital signal, determining L possible distinct data values in the N samples, determining a reference data value in the L possible distinct data values and a coding order of L−1 remaining possible distinct data values, wherein each of the L−1 remaining possible distinct data values is mapped to a position in the coding order, decomposing the N samples into L−1 coding vectors based on the coding order, wherein each coding vector identifies the locations of one of the L−1 remaining possible distinct data values in the N samples, and encoding the L−1 coding vectors. |
| US12087305B2 |
Speech processing
Techniques for performing spoken language understanding (SLU) processing are described. An SLU component may include an audio encoder configured to perform an audio-to-text processing task and an audio-to-NLU processing task. The SLU component may also include a joint decoder configured to perform the audio-to-text processing task, the audio-to-NLU processing task and a text-to-NLU processing task. Input audio data, representing a spoken input, is processed by the audio encoder and the joint decoder to determine NLU data corresponding to the spoken input. |
| US12087304B2 |
Electronic device for providing text and control method therefor
An electronic device for providing content including an image and a voice is disclosed. The electronic device comprises: a display configured to display an image; a memory in which a voice recognition module including various executable instructions is stored; and a processor configured to acquire expected words that will possibly be included in a voice, based on information about content, using the expected words to perform voice recognition for the voice through the voice recognition module, and displaying, on the display, text converted from the voice based on the voice recognition. |
| US12087302B2 |
Tone and echo cancellation using two acoustic sound cancellers
Example techniques involve systems with multiple acoustic echo cancellers. An example implementation captures first audio within an acoustic environment and detecting, within the captured first audio content, a wake-word. In response to the wake-word and before playing an acknowledgement tone, the implementation activates (a) a first sound canceller when one or more speakers are playing back audio content or (b) a second sound canceller when the one or more speakers are idle. In response to the wake-word and after activating either (a) the first sound canceller or (b) the second sound canceller, the implementation outputs the acknowledgement tone via the one or more speakers. The implementation captures second audio within the acoustic environment and cancelling the acoustic echo of the acknowledgement tone from the captured second audio using the activated sound canceller. |
| US12087299B2 |
Multiple virtual assistants
A speech-processing system may provide access to multiple virtual assistants via one or more voice-controlled devices. Each assistant may leverage language processing and language generation features of the speech-processing system, while handling different commands and/or providing access to different back applications. Different assistants may be available for use with a particular voice-controlled device based on time, location, the particular user, etc. The voice-controlled device may include components for facilitating user interaction with multiple assistants. For example, a multi-assistant component may facilitate enabling/disabling assistants, assigning gestures and/or wakewords, etc. The multi-assistant component may handle routing commands to a command processing subsystem corresponding to an assistant invoked by the command. The voice controlled device may further include observer components, each configured to monitor the voice-controlled device for invocations of a particular assistant. |
| US12087298B2 |
Electronic device and method of controlling thereof
Disclosed is an electronic device. The electronic device may execute an application for transmitting and receiving at least one of text data or voice data with another electronic device using the communication module, in response to occurrence of at least one event, based on receiving at least one of text data or voice data from the another electronic device, identify that a confirmation is necessary using the digital assistant based on at least one of text data or voice data being generated based on a characteristic of ab utterance using a digital assistant, generate a notification to request confirmation using the digital assistant based on confirmation being necessary, and output the notification using the application.A method for identifying that a confirmation is necessary may include identifying using voice data or text data that is received from another electronic device using a rule-based or AI algorithm.When a confirmation is necessary is identified using the AI algorithm, the method may use machine learning, neural network, or a deep learning algorithm. |
| US12087297B2 |
Voice filtering other speakers from calls and audio messages
A method includes receiving a first instance of raw audio data corresponding to a voice-based command and receiving a second instance of the raw audio data corresponding to an utterance of audible contents for an audio-based communication spoken by a user. When a voice filtering recognition routine determines to activate voice filtering for at least the voice of the user, the method also includes obtaining a respective speaker embedding of the user and processing, using the respective speaker embedding, the second instance of the raw audio data to generate enhanced audio data for the audio-based communication that isolates the utterance of the audible contents spoken by the user and excludes at least a portion of the one or more additional sounds that are not spoken by the user The method also includes executing. |
| US12087293B2 |
Smart voice wake-up control method and control device thereof
The invention discloses a smart voice wake-up control method and a control device thereof. The smart voice wake-up control device includes a casing, a main control board, a control switch, a voice pickup, a relay, an output terminal, an input terminal and a work indicator capable of emitting multiple colors of light, the main control board is respectively connected with the control switch, the voice pickup, the relay and the work indicator, and the relay is respectively connected with the output terminal and the input terminal. When multiple smart voice wake-up control devices are used simultaneously, the user can change the light color of the work indicator by controlling the control switch to distinguish different colors of voice wake-up commands, i.e., use the light color of the work indicator to show the color wake-up voice, so that the user can get the wake-up commands intuitively and quickly for controlling. |