| Document | Document Title |
|---|---|
| US11323415B2 |
Method and apparatus for providing over the top streaming
Various implementations described herein are directed to technologies for providing over the top streaming for one or more clients of a network. A network is formed among the network among customer premises equipment. The customer premises equipment may include at least a gateway and the one or more clients. A user selection for over the top (OTT) content is received. The OTT content is received and includes one or more cue points. The gateway is marked as a proxy server in response to receiving the one or more cue points. Proxy data is received from the gateway corresponding to the one or more cue points. |
| US11323412B2 |
DNS rendezvous localization
A method of generating a routing table containing information as to the weighted distance between client's that use a resolver and each rack gateway, taking into account how traffic to each client can egress from the CDN AS. The routing table is generated from matrix multiplication of two matrices. One matrix contains information as to the proportion of each client's use of each resolver in a first autonomous system. The second matrix contains information as to the distance between each client and each rack, with respect to an egress gateway, in a second autonomous system. The resulting routing table is used to identify a gateway from which to serve content to a client. |
| US11323411B2 |
Method and system for scheduling edge CDN node
The present disclosure is related to the content delivery technology and discloses a method and system for scheduling an edge CDN node. The method is applicable to a CDN scheduling center under a 5G network architecture and includes: receiving a terminal request for a target domain name sent by a central layer UPF network element; assigning a target edge CDN node to a terminal according to location information of the terminal carried in the terminal request if the terminal request is an HTTPDNS request; and assigning the target edge CDN node to the terminal according to a source IP address of the terminal request if the terminal request is a conventional DNS request. By adopting the present disclosure, the CDN scheduling center may determine the location information of the terminal under the 5G network architecture, thereby accurately assigning the edge CDN node to the terminal. |
| US11323409B2 |
Efficient ARP bindings distribution in VPN networks
In response to receiving an ASR message, a VTEP generates a specially modified control plane message advertising the IP-to-MAC binding of the ASR message. The control plane message may be modified to indicate that it is not to be used for MAC learning. The control plane message is advertised over the network. When an intended recipient receives the message, it uses that message just for the IP-to-MAC binding. When an unintended recipient receives the message, it may drop it as invalid. |
| US11323406B2 |
System and method for identifying and retrieving signature contact information from an email or email thread
An email message body is processed to identify groups of characters that match patterns from a set of predefined signature data patterns. For each identified group of characters, a respective block of the email message body is reviewed to identify other groups of characters within the respective block that also match patterns from the set of predefined signature data patterns. A block score is generated for the respective block based on the groups of characters identified as matching patterns from the set of predefined signature data patterns. One of the blocks is selected based on the block scores generated for the respective blocks, and signature contact information is retrieved from the selected block. |
| US11323405B2 |
Host state-sensing for message interruption
Embodiments of the present invention address deficiencies of the art in respect to managing interrupting requests to engage in a collaborative session and provide a novel and non-obvious method, system and computer program product for host state sensing for message interruptions. In one embodiment of the invention, a data processing system configured for host sensing for message interruption can include a messenger disposed is a host computing platform, prioritization logic including program code enabled to assign priorities to incoming messages, and host state sensing logic coupled to the host computing platform. The host state sensing logic can include program code enabled to adjust a threshold value for permitting message interruptions for messages having assigned priorities beyond the threshold value. |
| US11323404B2 |
System and method for displaying message or user lists
A system and method displays lists of users or messages in segments, with some segments showing messages or users believed to be more relevant to the user than others on the list. |
| US11323400B1 |
Protecting sensitive data using conversational history
Methods and systems for protecting sensitive data using conversational history are described herein. An enterprise data validation server may receive conversation snippets and create a topic model. The enterprise data validation server may detect a message is being sent from a first user to a second user, determine a topic distribution between the first user and the second user, and a topic distribution of the message. The enterprise data validation server may determine a bias value associated with the message by comparing the topic distribution of the message and the topic distribution between the first user and the second user. Accordingly, based on a determination that the bias value exceeds a threshold, the enterprise data validation server send an alert containing a warning message. |
| US11323399B2 |
Client-agnostic and network-agnostic device management
In accordance with an example implementation of this disclosure, an email handler comprises email processing circuitry, a web server, and a database. The email processing circuitry is operable to generate a uniform resource locator for a notification object to be embedded in an email message. The email processing circuitry is operable to embed the notification object in the email message. The email processing circuity is operable to send the email message into a network. The web server is operable to receive a request sent to the uniform resource locator by a client device, The web server is operable to determine characteristics of the client device based on content of the request. The web server is operable to store the characteristics in the database. The web server is operable to control access to content by the client device based on characteristics of the client device stored in the database. |
| US11323395B2 |
Computing device and method for message construction and processing based upon historical data
A computing device, method and computer program product are provided to process messages received from a source and to construct messages transmitted to a recipient that include the information required to elicit the desired response. In relation to a method, an electronic message is received and analyzed relative to requirements of the related message to determine whether the electronic message includes information required by the related message. If the analysis determines that the electronic message fails to satisfy the requirements of the related message, the method searches historical data related to prior messages to identify additional information sufficient in combination with the information provided by the electronic message to satisfy the requirements of the related message, constructing the related message based upon the additional information identified from the historical data and the information provided by the electronic message, and causing the related message to be transmitted to a request processor. |
| US11323394B2 |
Buffer control method, network element, and controller
A buffer control method, a network element, and a system. The method includes: receiving, by a network element, a flow table message from a controller, where the flow table message includes buffer information of a data packet matching a flow table; processing, by the network element, a buffer of the data packet based on the buffer information, and sending a flow table response message to the controller. In the method, the network element can save, based on a corresponding saving manner, at least one data packet matching the flow table to the buffer corresponding to the flow table. Thus a data flow granularity-based buffer processing manner can be supported in an OpenFlow protocol, and a data buffering requirement of a mobile network can be met. |
| US11323393B2 |
System and method for improving network storage accessibility
A system and method for improving network storage accessibility, the method including: sending at least a first request for a data block to be sent from a storage device to a client device over a network connection; determining if the network is congested; initiating a client-specific buffer when it is determined that the network is congested, wherein the requested data block is stored in the client-specific buffer; and sending at least a second request for the data block stored within the client-specific buffer to be sent to the client device. |
| US11323390B2 |
Request arbitration by age and traffic classes
Example implementations relate to hybrid arbitration of requests for access to a shared pool of resources. An example implementation includes receiving a set of requests for access to the shared pool of resources. The requests may each be from any number of traffic classes. A traffic class may be selected according to turn-based arbitration logic. Additionally, a request from each traffic class of a subset of received requests may be selected. A request selected by the age-based arbitration logic and of the selected traffic class may be granted access to the shared pool of resources. |
| US11323387B2 |
Prioritized communication session establishment in computer networks
Techniques are described for prioritized establishment of communication sessions. In one example, a network device parses a configuration file that defines a plurality of communication sessions of a routing protocol and includes priority values assigned to the communication sessions. The network device creates two or more lists of communication sessions for two or more of the priority values based on the configuration file, wherein each list of the two or more lists is created for a particular priority value of the priority values and defines one or more communication sessions of the plurality of communication sessions that are assigned the particular priority value. The network device then establishes the one or more communication sessions included in each list of the two or more lists according to an ordering based on the priority values associated with the two or more lists. |
| US11323384B2 |
Packet processing technique for a communication network
A system comprising one or more network elements and configured to process at least first and second packet flows. The system comprises a first packet gate selectively switchable between an open state for packet transmission and a closed state and an associated first packet queue. The first packet gate and the first packet queue are configured to handle first packet flow packets. The system further comprises a second packet queue configured to handle second packet flow packets. Moreover, the system comprises at least one processor configured to control switching of the first packet gate between the open state and the closed state based on the occurrence of a first event associated with the second packet queue to trigger transmission of the first packet flow packets in a relative transmission order among the first packet flow packets and the second packet flow packets. |
| US11323380B2 |
Method of synchronization of data packet transmission
The present disclosure concerns a method of synchronization of data packet transmission (P1, P2, P3) in a network (N), including and/or initiating the acts of: Receiving (S1), e.g. from a terminal device (T1, T2, T3) of the network (N), one or more data packets (P1, P2, P3) after a threshold time interval (tt) of a periodic transmission window (RT, BE), wherein the threshold time interval (tt) is arranged at the beginning of said periodic transmission window (RT, BE), and Forwarding (S2) the data packet (P1, P2, P3) in a subsequent transmission window (RT, BE), preferably directly after the transmission window in which the data packet (P1, P2, P3) was received, within the threshold time interval (tt) of the transmission window (RT, BE). |
| US11323379B2 |
Adaptive monitoring of computing systems
An adaptive monitoring method, system, and computer program product including an intelligent monitoring system which obtains at least one preference from a user, where the at least one preference includes at least one maximum monitoring overhead. |
| US11323376B2 |
Bandwidth control in a network address translation (NAT) environment
Embodiments disclosed herein provide systems and methods for controlling bandwidth across a network address translation (NAT) system. In a particular embodiment a method provides, identifying a first endpoint and a second endpoint to a communication session. The first endpoint is located within a domain of the NAT system and the second endpoint is located outside to the domain. The method further provides determining a bandwidth limitation for the communication session and exchanging communications between the first and second endpoints in accordance with the bandwidth limitation. |
| US11323372B2 |
Flexible steering
In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry. |
| US11323369B2 |
Transforming a multi-level hybrid hierarchical forwarding information base format
A network device may receive forwarding data associated with a multi-level hybrid hierarchy forwarding information base of the network device. The network device may process the forwarding data to generate a first set of transformed forwarding next hop entries. The network device may process the first set of transformed forwarding next hop entries, associated with default forwarding classes, to generate a second set of transformed forwarding next hop entries. The network device may process the first set of transformed forwarding next hop entries, associated with all classes of traffic, to generate a third set of transformed forwarding next hop entries. The network device may group the sets of transformed forwarding next hop entries, based on transformed group next hop entries, to generate a final set of transformed forwarding next hop entries. The network device may transform the final set of transformed forwarding next hop entries into a particular format. |
| US11323364B2 |
Ingress replication procedures to facilitate migration to segment routing technology in a computer network
In some examples, a network device may determine whether a first egress network device is segment routing (SR) aware. Based on the first egress network device being SR aware, the network device may initiate establishment of an SR tunnel toward the first egress network device. The network device may forward multicast traffic on the SR tunnel. The network device may also determine whether a second egress network device is SR aware. Based on the second egress network device not being segment routing aware, the network device may initiate establishment of a non-SR tunnel toward the second egress network device. The network device may forward multicast traffic on the non-SR tunnel. |
| US11323360B2 |
Sequence number checksum for link state protocols
In general, various aspects of the techniques described in this disclosure provide a sequence number checksum for link state protocols. In one example, the disclosure describes an apparatus, such as a network device, having a control unit operative to obtain link state information describing links between pairs of the network devices in a network topology, the link state information being fragmented into a plurality of link state protocol (LSP) fragments; compute a sequence number checksum from sequence numbers of the link state protocol (LSP) fragments; receive an LSP data unit from another network device in the network; determine whether a sequence number checksum in the LSP data unit matches a sequence number checksum computed from the link state information; and configure a delay for processing the LSP data unit in response to determining a mismatch between the sequence number checksum of the LSP data unit and the sequence number checksum computed from the link state information. |
| US11323359B2 |
Multi-channel communication
Multi-channel communication over wired and/or wireless communication mediums is contemplated. The multi-channel communication may be of the type sufficient to facilitate data delivery utilizing two or more channels/paths associated with an access point configured to facilitate communications with a plurality of devices. The multi-channel communications may be controlled to maximize performance through limitations placed on communications permitted over one or more of the channels/paths. |
| US11323358B1 |
Load-aware ECMP
A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can optimize at least one feature of the overlay network and a corresponding group of paths within the underlay network. |
| US11323355B1 |
Partition abstraction in distributed computing systems
Techniques of partition abstraction in a wide area network are disclosed herein. In one example, a method includes receiving, at a partition of the wide area network, a request to perform a computing task with a computing resource in the wide area network, the computing resource having a resource identifier. In response to receiving the request, the method also includes determining whether the resource identifier of the computing resource includes a partition embedded globally unique identifier (PEGUID) and in response to determining that the resource identifier includes a PEGUID, extracting the PEGUID from the resource identifier and decoding the PEGUID to identify a partition corresponding to the computing resource. |
| US11323351B2 |
Communication device and communication method for processing authentication information
A communication device includes a processor. The processor monitors a first message that is periodically transmitted from a representative device in a first network. The processor transmits a second message to the communication devices in the first network when the first message is not detected. When plural data components obtained by dividing authentication information have been distributed from the representative device plural communication devices in the first network, the processor receives data components transmitted from the communication devices in the first network in response to the second message. When a specified number of data components are received, the processor regenerates the authentication information from the specified number of data components. The processor generates new authentication information by rewriting at least a portion of the regenerated authentication information. The processor connects to a second network based on the new authentication information. |
| US11323340B2 |
Packet flow monitoring in software-defined networking (SDN) environments
Example methods are provided a first host to perform packet flow monitoring in a software-defined networking (SDN) environment. One example may comprise the first host receiving a request to monitor a packet flow and triggering a telemetry process based on a predetermined event associated with the packet flow. The method may also comprise: in response to the triggered telemetry process and detecting an egress packet associated with the packet flow, generating an encapsulated packet by encapsulating the egress packet with an outer header; configuring a telemetry instruction in the outer header; and sending the encapsulated packet with the telemetry instruction to the second host via one or more intermediate network devices. The telemetry instruction may be configured to cause the one or more intermediate network devices to add, to the encapsulated packet, metadata associated with a network state experienced by the encapsulated packet. |
| US11323337B2 |
Resource measurement and management
Aspects of the disclosure relate to measuring and managing data traffic in one or more networks. In some embodiments, a monitor may measure the traffic at one or more locations within the network(s) or devices associated therewith to determine whether the traffic exceeds a threshold. When the traffic exceeds the threshold, one or more actions may be taken, such as issuing or transmitting a command or directive. The command or directive may advise a device or an application to throttle or reduce an input or stimulus responsible for generating the traffic. In some embodiments, a throttling may be effectuated to reduce the data traffic. |
| US11323335B2 |
SLA handling in network slices
Embodiments herein relate to a method performed by a RAN node (12), for managing communication on a first network slice in a communications network (1). The communications network (1) comprises partitioned sets of functionalities. A first set of functionalities belongs to the first network slice. The first set of functionalities is at least 5 partly separated from another set of functionalities out of a total set of functionalities in the communications network (1). The RAN node (12) receives, from a CN node (16), information regarding requested resources for a first network slice identified by a network slice identifier. The RAN node (12) determines that the received information does not correspond to a Service Level Agreement (SLA) for the first network slice. |
| US11323330B1 |
Validating network topologies
In general, the disclosure describes techniques for a hybrid diagramming application to provide a flexible network diagramming environment while also ensuring that the rules of the network are not violated. A service provider defines rules for various network objects, where the rules define where the various network objects can reside in the network topology, as well as how the various devices can be connected. A computing device executing the application receives an indication of user input assigning a first network device to a first area network in a network topology. The computing device validates, based on one or more characteristics of the first network device, that the first network device does not violate one or more rules for the first area network. The computing device, responsive to validating the first network device, generates a graphical user interface of the network topology and outputs, for display, the graphical user interface. |
| US11323323B2 |
Communication system, communication apparatus, and communication method
A rule for transferring data over a communication network is changed for each communication apparatus without spending time and cost. In a communication system in which a plurality of communication apparatuses are connected to a network, at least one of the plurality of communication apparatuses includes rule storage means for storing a plurality of transfer rules for transferring data over the network, transfer means for transferring data incoming over the network in accordance with one of the plurality of transfer rules, and rule switching means for switching one transfer rule to another transfer rule when the communication apparatus receives a notification from the outside. |
| US11323320B2 |
Concurrent transactions on NETCONF devices across network services
Techniques are disclosed for managing a network. In one example, a device configuration manager is configured to generate, in accordance with a device management protocol, a configuration change request representing a transaction having a first sub-transaction specifying a first configuration change for a network device of the network and a second sub-transaction specifying a second configuration change for the same network device. The device configuration manager is further configured to output the configuration change request to the network device and receive a reply message from the network device. The reply message includes a first response element specifying whether the first configuration change is successfully committed at the network device and a second response element specifying whether the second configuration change is successfully committed at the network device. |
| US11323318B2 |
Network slicing in IMS
Systems and methods are disclosed for enabling Internet Protocol (IP) Multimedia Subsystem (IMS) network slicing. In some embodiments a method performed by a wireless device relating to registering with an IMS network slice or initiating a session using an IMS network slice comprises sending a message to an IMS node via a radio access network, the message comprising an identifier of a desired IMS network slice. In this manner, IMS network slicing is enabled. |
| US11323317B1 |
Software capabilities management from a service provider environment
A technology is described for managing network communication device software capabilities. An example method may include sending a connection request from a network communication device electronically to a service provider environment. Software capabilities for the network communication device may be verified from the service provider environment. A software capabilities modification instruction for the network communication device may be received from the service provider environment. The software capabilities of the network communication device may be modified based on the software capabilities modification instruction. |
| US11323312B1 |
Software-defined network monitoring and fault localization
The disclosure describes techniques for network monitoring and fault localization. For example, a controller comprises one or more processors operably coupled to a memory configured to: receive a first one or more Quality of Experience (QoE) metrics measured by a first probe traversing a first path comprising one or more links; receive a second one or more QoE metrics measured by a second probe traversing a second path comprising one or more links; determine, from the first one or more QoE metrics, that the first path has an anomaly; determine, from the second one or more QoE metrics, that the second path has an anomaly; and determine, in response to determining the first path and the second path has an anomaly, based on the type of metrics and the type of links, that an intersection between the first path and the second path is a root cause of the anomaly. |
| US11323308B2 |
Core isolation for logical tunnels stitching multi-homed EVPN and L2 circuit
Techniques are described to provide layer 2 (L2) circuit failover in the event connectivity to an Ethernet Virtual Private Network (EVPN) instance is lost. For example, if one of multi-homed provider edge (PE) devices loses connectivity to the EVPN instance, the PE device may mark its customer-facing interface as down and propagate the interface status to the access node such that the access node may update its routing information to switch L2 circuits to another one of the multi-homed PE devices having reachability to the EVPN instance. In some examples, the plurality of PE devices may further implement Connectivity Fault Management (CFM) techniques to propagate the interface status to the access node such that the access node may update its forwarding information to send traffic on a different L2 circuit to another one of the multi-homed PE devices having reachability to the EVPN instance. |
| US11323307B2 |
Method and system of a dynamic high-availability mode based on current wide area network connectivity
In one aspect, a computer-networking method useful for implementing dynamic high-availability (HA) mode based on current wide area network (WAN) connectivity, comprising the steps of: providing a first edge device of a local area network (LAN) with the WAN; providing a second edge device of the LAN with the WAN; and synchronizing a state of plurality of links with the WAN that are connected to the first edge device and the second edge device. |
| US11323305B1 |
Early detection of telemetry data streaming interruptions
A computing device may receive, from a collector device, a request to subscribe, in a target-defined mode, to network telemetry data regarding a network element associated with the computing device. The computing device may, in response to receiving the request, provision a network telemetry sensor to operate in a working mode to collect the network telemetry data regarding the network element. The collector device may send, to the collector device, the network telemetry data collected by the network telemetry sensor, wherein the network telemetry data indicates the working mode of the network telemetry sensor. |
| US11323301B2 |
Method and device for transmitting or receiving superposition coding signal by using device-to-device communication in wireless communication system
The present application discloses a method for transmitting an uplink relay signal by a relay terminal in a wireless communication system. Specifically, the method comprises the steps of: superposition encoding relay data and side link data according to a predetermined power ratio so as to generate the uplink relay signal; and transmitting the uplink relay signal and a superposition encoding-specific reference signal sequence corresponding to the power ratio to a base station and a target terminal. |
| US11323297B2 |
Receiver/transmitter co-calibration of voltage levels in pulse amplitude modulation links
A driver circuit of a PAM-N transmitting device transmits a PAM-N signal via a communication channel, wherein N is greater than 2, and the PAM-N signal has N signal levels corresponding to N symbols. A PAM-N receiving device receives the PAM-N signal. The PAM-N receiving device generates distortion information indicative of a level of distortion corresponding to inequalities, in voltage differences between the N signal levels. The PAM-N receiving device transmits to the PAM-N transmitting device the distortion information indicative of the level of the distortion. The PAM-N transmitting device receives the distortion information. The PAM-N transmitting device adjusts one or more drive strength parameters of the driver circuit of the PAM-N transmitting device based on the distortion information. |
| US11323293B2 |
Wireless communication method and wireless communication device
A wireless communication method and a wireless communication device. An electronic device for a user equipment in a wireless communication system, including a processing circuit configured to receive, from a base station, channel state information reference signal with a set of reception filters, perform channel estimation on a downlink channel from the base station to the user equipment, select, from the set of reception filters, one or more particular reception filters corresponding to respective channel estimation results that satisfy a first predetermined condition, and signal, from the user equipment to the base station, sounding reference signal with one or more particular transmission filters, wherein the one or more particular transmission filters and one or more particular reception filters are reciprocal respectively. |
| US11323292B2 |
Connecting to multiple cloud instances in a telecommunications network
Aspects of the disclosure involve systems and methods for utilizing Virtual Local Area Network separation in a connection, which may be a single connection, between a customer to a telecommunications network and a cloud environment to allow the customer to access multiple instances within the cloud through the connection. A customer may purchase multiple cloud resource instances from a public cloud environment and, utilizing the telecommunications network, connect to the multiple instances through a communication port or connection to the cloud environment. To utilize the single connection or port, communication packets intended for the cloud environment may be tagged with a VLAN tag that indicates to which cloud instance the packet is intended. The telecommunications network may route the packet to the intended cloud environment and configure one or more aspects of the cloud environment to analyze the attached VLAN tag to transmit the packet to the intended instance. |
| US11323291B2 |
Port activation system
A server-facing port activation system includes a core network system, a server device, and a networking device that includes at least one uplink port coupled to the core network system, and a first downlink port coupled to the server device. The networking device begin initialization operations and, in response, identifies that the first downlink port is coupled to the server device and prevents the first downlink port from being made available. While preventing the first downlink port from being made available, the networking device configures the at least one uplink port coupled to the core network system with server device information associated with the server device. The networking device then determines that the at least one uplink port coupled to the core network system is available and, in response, causes the first downlink port that is coupled to the server device to be made available. |
| US11323290B2 |
Establishing a network micro-tunnel within a network tunnel
A first network device may communicate, in association with a tunnel establishment network protocol, with a second network device to cause a network tunnel between the first network device and the second network device to be established. The first network device may determine, based on communicating with the second network device to cause the network tunnel to be established, that the network tunnel is to support network micro-tunnel functionality within the network tunnel. The first network device may communicate, based on determining that the network tunnel is to support network micro-tunnel functionality, with the second network device to identify a traffic class, of one or more traffic classes, to which network micro-tunnel functionality within the network tunnel is to be applied. The first network device may cause a network micro-tunnel to be established within the network tunnel for traffic associated with the traffic class. |
| US11323288B2 |
Systems and methods for server cluster network communication across the public internet
Server cluster communication across the public internet using a single secure User Datagram Protocol (UDP) is facilitated by an intermediary registry server. The intermediary registry server enables servers within a cluster to identify and securely communicate with peer servers in the cluster across disparate locations and through firewalls Using an external address registry shared to each member of a server cluster peer group, individual servers can establish a direct secure channel using a single UDP tunnel. |
| US11323283B2 |
Domestic appliance commissioning
Methods for commissioning a domestic appliance, as provided herein, may include the transmission and receiving of signals between the domestic appliance, a previously-commissioned appliance, a remote user-interface device, and a remote server such that a network credential for a local wireless network is transmitted from the previously-commissioned appliance to the domestic appliance. |
| US11323281B2 |
System and method for providing network support services and premises gateway support infrastructure
A service management system communicates via wide area network with gateway devices located at respective user premises. The service management system remotely manages delivery of application services, which can be voice controlled, by a gateway, e.g. by selectively activating/deactivating service logic modules in the gateway. The service management system also may selectively provide secure communications and exchange of information among gateway devices and among associated endpoint devices. An exemplary service management system includes a router connected to the network and one or more computer platforms, for implementing management functions. Examples of the functions include a connection manager for controlling system communications with the gateway devices, an authentication manager for authenticating each gateway device and controlling the connection manager and a subscription manager for managing applications services and/or features offered by the gateway devices. A service manager, controlled by the subscription manager, distributes service specific configuration data to authenticated gateway devices. |
| US11323280B2 |
Network node for network based multicast replication
A network node adapted to forward incoming data packets, the network node including a tag identifying unit, adapted to identify a tag of an incoming data packet as a replicate tag; a tag look-up module, adapted to retrieve from a tag table a number of replications and destinations for the replicate tag; a replicating engine, configured to replicate the incoming data packet according to the number of replications, thereby generating replicated data packets; and a forwarding unit, adapted to forward the replicated data packets to the destinations. |
| US11323277B2 |
Mission critical video identifier for mission critical video policies
A policy control function device receives, from a mission critical video (MCVideo) application function, a DIAMETER AA-Request (AAR) command. The DIAMETER AAR command comprise: an attribute value pair (AVP) comprising an MCVideo-identifier identifying an MCVideo service; and a quality of service (QoS) parameter indicating a QoS of the MCVideo service. A Diameter command comprising one or more QoS policies based on the MCVideo-identifier and the QoS parameter is sent to a network function. |
| US11323271B2 |
Retrieving public data for blockchain networks using highly available trusted execution environments
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enhancing blockchain network security. Implementations include receiving a request for data from the data source, transmitting the request to a relay system that is external to the blockchain network and that includes a multi-node cluster including a plurality of relay system nodes, receiving a result provided from a relay system node, the result being digitally signed using a private key of the relay system node, verifying that the relay system node is registered, verifying an integrity of the result based on a public key of the relay system node and a digital signature of the result in response to verifying that the relay system node is registered, and transmitting the result to a client in response to verifying the integrity of the result. |
| US11323269B2 |
Preserving privacy of linked cross-network transactions
An example operation may include one or more of storing a first hashed timelock request in a first storage structure, where the first hashed timelock request is hashed based on a first secret, generating a second secret based on the first secret and a public key of a client, hashing the second secret to generate a hashed second secret, and transmitting a request for a second hashed timelock request to the client, where the request comprises the generated hashed second secret. |
| US11323267B1 |
Systems and methods for maintaining confidentiality, integrity, and authenticity of the last secret
Systems and methods for securely sharing and authenticating a last secret. A system includes a dealer computing system and a combining computing system. The dealer computing system includes a public/private key pair, an encryption key established with the combining computing system, and a circuit structured to generate a last secret and a first key controlling access to a secure computing system. The last secret is the last cryptographic element controlling access to the first key. The circuit is structured to split the last secret into first and second splits. The circuit is structured to generate a first and second SigncryptedData messages by signcrypting each of the first split and the second split with the public/private key pair and the encryption key established with the combining computing system. The circuit is structured to transmit the first SigncryptedData message to a first share-holder and the second SigncryptedData message to a second share-holder. |
| US11323264B2 |
Validating tracked portions of received sensor data using computer cryptographic processing
A computer identifies capture device output that represents an aspect of a recorded event. The computer cryptographically processes the tracked portions of capture device output to produce a validatable master file which includes master file media data tracked portion from the capture device output, master tracked portion metadata of said master file media data tracked portion, and master file blockchain data. The master file blockchain data includes a master file block history portion, a master file signature key portion, and a signed hash of said master file media data tracked portion. The computer also modifies the master file media data tracked portion to produce a reference file media data tracked portion. reference files and distributable files. The computer verifies the authenticity of each of these files. |
| US11323262B2 |
Method and system for verifying a voter through the use of blockchain validation
The present invention is a method for authenticating a voter and casting their vote comprising: receiving, a voter's identification information, wherein the identification information is associated with a voter's account, processing, the voter's identification information in relation to governing bodies requirements for a voter's eligibility, encrypting, a portion of the voter's identification information and storing the encrypted portion of the voter's identification information and the remaining portion of non-encrypted voter's identification information in a block of a blockchain, receiving, a request from the voter account to cast a vote, accessing, the voter's account, receiving, a vote from the voter's account, wherein the vote is accompanied by a signature of the voter account, and indexing, a first portion of the vote data in a block in an encrypted format, and a second portion of the vote data in a block in a non-encrypted format in the block chain. |
| US11323260B2 |
Method and device for identity verification
One embodiment provides a method and system for identity verification. During operation, a digital identity client executing on a computer receives an identity-verification request comprising an identifier of a user, sends a query for available identity-verification services to identity-verification-service-publishing blockchain, determines an identity-verification server based on a result of the query, interacts with the determined identity-verification server to complete identity verification of the user, generates a public-private key pair comprising a public key and a private key corresponding to the identifier of the user, and stores, in identity-verification blockchain, identity-verification information associated with the user. The identity-verification information comprises at least a hash value of the public key, thereby facilitating subsequent identity verification of the user based on the identity-verification information stored in the identity-verification blockchain. |
| US11323256B2 |
Method for generating on-board a cryptographic key using a physically unclonable function
A method, cryptographic device, and computer readable memory with instructions, for generating a cryptographic key from at least one prime number, by performing during runtime of the cryptographic device by obtaining from memory a challenge and at least one associated increment number, generating a seed by applying a Physically Unclonable function to said obtained challenge, generating at least one prime number from said generated seed by performing said cryptographic prime numbers generation algorithm and by performing therein as many incrementation steps as said obtained at least one increment number, and generating the cryptographic key from the generated prime number. |
| US11323252B2 |
Relay network for encryption system
A method comprises registering, by a first device having a public key, with a gateway server by providing a proof of work based on the first device public key and encrypting and decrypting data using cryptographic information transmitted via the gateway server between other devices similarly registered. |
| US11323250B2 |
Method and system for key agreement utilizing semigroups
A method for key agreement between a first party and a second party over a public communications channel, the method including selecting, by the first party, from a semigroup, a first value “a”; multiplying the first value “a” by a second value “b” to create a third value “d”, the second value “b” being selected from the semigroup; sending the third value “d” to the second party; receiving, from the second party, a fourth value “e”, the fourth value comprising the second value “b” multiplied by a fifth value “c” selected by the second party from the semigroup; and creating a shared secret by multiplying the first value “a” with the fourth value “e”, wherein the shared secret matches the third value “d” multiplied by the fifth value “c”. |
| US11323249B2 |
Cryptographic methods and systems for authentication in connected vehicle systems and for other uses
Cryptographic authentication is described to improve security in connected vehicle systems and other applications. Identity Based Cryptography and threshold cryptography are among techniques used in some embodiments. |
| US11323247B2 |
Methods and systems for secure data communication
A computer-implemented method, which comprises: receiving an input message comprising N-bit input segments, N being an integer greater than one; converting the N-bit input segments into corresponding N-bit output segments using a 2N-by-2N one-to-one mapping stored in a non-transitory storage medium; and generating an output message comprising the N-bit output segments. Also, a computer-implemented method for a recipient to validate a message received from a sender, the message including a first part and a second part. This method comprises receiving a token from a witnessing entity; obtaining a first data element by joint processing of the first part of the message and the token; obtaining a second data element by joint processing of the second part of the message using a key associated with the sender; and validating the message by comparing the first and second data elements. |
| US11323245B2 |
Method for linking block-chain using hyper-chain, and apparatus therefor
Disclosed herein is a method for linking a blockchain using a hyper-chain and an apparatus therefor. According to the present invention, a correlation of a common block on at least two blockchains is identified by a predetermined method, and a hyper-block including an information of the correlated common block on the at least two blockchains is stored on a hyper-chain. |
| US11323241B2 |
Encryption processing system, encryption processing device and recording medium
An encryption processing system includes: an encryption data generation device, an encryption processing device, and a processing result utilization device. A first processor of the encryption data generation device is configured to perform preprocessing by generating encrypted data of homomorphic encryption corresponding to data obtained by multiplying plaintext data as a target by a power of a predetermined number of two or more. A second processor of the encryption processing device is configured to perform acquiring the encrypted data, and executing a processing on the encrypted data in an encrypted state to obtain a processing result in the encrypted state. A third processor of the processing result utilization device is configured to perform acquiring the processing result, and postprocessing by decrypting data of the processing result in the encrypted state and by dividing the decrypted data by the power of the predetermined number of two or more. |
| US11323238B2 |
Frame synchronization apparatus, optical communication apparatus, and frame synchronization method
A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination. According to this invention, it is possible to provide a frame synchronization apparatus that correctly determines a synchronization state even if an error rate of received symbols is high. |
| US11323236B2 |
Narrowband PDCCH DMRS bundling with enhanced coverage
Narrowband (NB) Physical Downlink Control Channel (PDCCH) demodulation reference signals (DMRS) bundling coverage enhancements are disclosed. In some aspects, NB PDCCH DMRS bundling resources and timing are allocated in a virtual domain by a transmitting device, such as a base station. In some aspects the allocated resources are control channel elements (CCEs); the CCEs are allocated according to a pattern in the virtual domain. The base station may transmit NB PDCCH transmissions and corresponding DMRS transmissions in physical domain resources that correspond to the virtual domain resources, the CCE allocation pattern. In some aspects, the NB PDCCH DMRS can be used with PDCCH repetitions. To illustrate, a base station may repeat a PDCCH transmission (e.g., payload data thereof) in multiple particular PDCCH candidates of a plurality of PDCCH candidates. The particular PDCCH candidates may be identified based on PDCCH candidate number or a reference slot or search space set occasion. |
| US11323229B2 |
Method and device for determining uplink data and control signal transmission timing in wireless communication system
Methods and apparatuses are provided in which a radio resource control (RRC) message is transmitted to a terminal. A set of values for a timing between a physical downlink shared channel (PDSCH) and acknowledgement information is included in the RRC message, and the set of values is respectively associated with a set of numbers of a transmission time interval (TTI). First downlink control information (DCI) for a first PDSCH is transmitted to the terminal. A number of bits associated with one value in the set of values is included in the DCI. The first PDSCH is transmitted to the terminal. Acknowledgement information for the first PDSCH is received from the terminal, based on a transmission timing determined by using the RRC message and the number of bits in the DCI. |
| US11323228B2 |
Feedback for sidelink communications
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a sidelink communication on a sidelink between the UE and another UE. The UE may transmit, on the sidelink, one or more feedback communications associated with the sidelink communication in a reporting period having a configurable periodicity and/or being configured to occupy an entire bandwidth of a resource pool configured for the sidelink. Numerous other aspects are provided. |
| US11323227B2 |
Multiplexing of physical uplink shared channel (PUSCH) and physical uplink control channel (PUCCH) in uplink short burst transmission
Aspects of the disclosure relate to an apparatus and method for wireless communication. The apparatus receives downlink control information (DCI) or a radio resource control (RRC) message indicating a configuration of an uplink burst region of a downlink-centric slot, the configuration allocating resources within the uplink burst region between a physical uplink shared channel (PUSCH) and a physical uplink control channel (PUCCH) or uplink control information (UCI). The PUSCH is multiplexed with at least one of the PUCCH or the UCI in the uplink burst region. The apparatus further generates a feedback signal (e.g., Transmission Control Protocol (TCP) acknowledgement (ACK)) corresponding to a downlink (e.g., TCP) data packet received from a scheduling entity and transmits the feedback signal to the scheduling entity via the PUSCH configured in the uplink burst region of the downlink-centric slot. Other aspects, embodiments, and features are also claimed and described. |
| US11323223B2 |
Systems and methods for robust transmission for semi-persistent scheduling and configured grant
Aspects of the present application use diversity of more than one TCI state, QCL assumption, precoder and/or SRI on the network side to enable multiple transmission beams in a transmission period having multiple transmission opportunities to provide robust beam transmission from the network side. An example of transmission opportunities in a transmission period may be OFDM symbols in a slot. Aspects of the present application use diversity of more than one TCI state, QCL assumption, precoder and/or SRI at the UE to enable the UE to transmit multiple transmission beams in a configured transmission period having multiple transmission opportunities to provide robust transmission from the UEs. When using multiple transmission beams, in the event that data transmitted on one beam cannot be decoded (e.g. due to beam blockage, poor radio conditions, etc.), data transmitted on other beams can still be decoded successfully. |
| US11323222B2 |
Communication method, and apparatus
This application provides a communication method and an apparatus. The communication method includes: receiving, by user equipment, first indication information from a network device, where the first indication information indicates a first resource; determining, by the user equipment, a second resource, where the second resource and the first resource belong to a same resource set configured by the network device, and the first resource and the second resource are used to transmit a first downlink reference signal; and receiving, by the user equipment on a third resource, a second signal and/or channel transmitted by using a third antenna port, where the third antenna port has a quasi co-location QCL relationship with a second antenna port used when the first downlink reference signal is transmitted on the second resource. |
| US11323221B2 |
Method for receiving reference signal and method for sending reference signal
Various embodiments provide a method for receiving reference signal and a method for sending a reference signal. In those embodiments, a terminal device can determine a location of a resource element to which a reference signal is mapped. The terminal device can determine a reference signal sequence corresponding to the resource element. The index of each element in the reference signal sequence is determined based on a resource block index of a resource block corresponding to the resource element, a quantity of resource elements that carry the reference signal in the resource block, a resource block offset, or an inter-symbol offset. The terminal device can receive the reference signal by using the resource element, and performing channel estimation or channel sounding based on the received reference signal and the reference signal sequence. Therefore, the terminal device can complete channel estimation without learning of a system bandwidth. |
| US11323217B2 |
Multi-band width tone plan for OFDMA in a wireless network
Presented herein is a tone plan that can accommodate multiple bandwidth options. This tone plan may be designed around a fundamental tile, such as 20 MHz tile, that is replicated to 40 and 80 MHz (and 160 MHz and beyond). For wider bandwidths, the otherwise-unused guard tones between the 20 MHz tiles are filled by a new resource unit and DC tones. There are DC tones placed to support any client, for all defined and plausible future values of its current operating bandwidth and center frequency (i.e. any 20 MHz, any 40 MHz, any 80 MHz, 160 MHz and 80+80 MHz, 320, 160+80 etc.), as well as plausible future preamble puncturing cases. |
| US11323215B2 |
Radio communication apparatus, method, program, non-transitory computer readable recording medium, and system
In order to enable control related to radio communication to be performed more appropriately when radio transmission schemes coexist, a radio communication apparatus according to an example aspect of the present invention includes a radio communication processing unit configured to perform communication using a first radio transmission scheme within a frequency band, wherein the radio communication processing unit is configured to perform communication using a second radio transmission scheme within a bandwidth part of the frequency band, radio resources within the bandwidth part being allocable for communication using the second radio transmission scheme. |
| US11323210B2 |
Method and device for transmitting hybrid automatic repeat request information
The present disclosure provides a method and device for transmitting hybrid automatic repeat request (HARQ) information. The method can include monitoring a channel bearing the HARQ information on a target time domain unit, demodulating, on the basis of a HARQ network temporary identity notified by a base station, downlink control information borne by the channel in response to determining that a channel is monitored, and acquiring the HARQ information from a specified information field of the downlink control information. |
| US11323207B2 |
Method for HARQ ACK/NACK reporting in wireless communication system and apparatus therefor
A method by which a terminal reports hybrid automatic repeat request (HARQ) acknowledgment/negative acknowledgment (ACK/NACK) feedback in a wireless communication system, according to one embodiment of the present disclosure, comprises the steps of: detecting downlink data; and transmitting HARQ ACK/NACK information for the downlink data, wherein the HARQ ACK/NACK information can include a bit selected from a HARQ ACK/NACK bit information group in which the number of states of a bit indicating ACK and the number of states of a bit indicating NACK are different. |
| US11323204B2 |
PBCH timing and aspects of polar code design involving first scrambling of payload data and second scrambling of encoded data
PBCH design may affect timing indication in a wireless network and polar code interleaver design, among other things. Mechanisms may indicate half frame timing though de-modulation reference signal sequence initialization, de-modulation reference signal mapping order, or de-modulation reference signal resource element location. The payload of the PBCH comprises a master information block (MIB), which payload is scrambled and encoded using a polar code. After rate matching and interleaving of the polar codeword, second scrambling is applied and the data is modulated. |
| US11323199B2 |
Optical transmission system and optical power control method
This application provides a sending device, a receiving device, an optical transmission system, and an optical power control method. The sending device includes a multiplexing unit and an optical power adjustment unit. The multiplexing unit is configured to send at least two communication optical waves to a fiber channel, and is further configured to send or receive at least two detection optical waves through the fiber channel. The optical power adjustment unit is configured to: obtain a power control instruction, where the power control instruction is generated according to power change information between the at least two detection optical waves. The optical power adjustment unit is further configured to perform optical power amplification and/or attenuation on at least one communication optical wave in the at least two communication optical waves according to the power control instruction. |
| US11323196B1 |
Systems and methods for real-time transmission of digital data using a plurality of channels
Disclosed embodiments include systems, methods, and media for receiving and transmitting digital data over a plurality of channels. Disclosed embodiments may include receiving data from a plurality of sources through one or more networks. Disclosed embodiments may also include assigning a geographic area to the data from the plurality of sources, the geographic area corresponding to one or more locations associated with the data. Additionally, disclosed embodiments may include determining health effects for a predetermined location based on the data and its associated geographic locations. Further, disclosed embodiments may include generating, by querying a predetermined response database, instructions that address the determined health affects for the predetermined location, the instructions including an action and an associated device. And, disclosed embodiments may include transmitting, to the associated device, the action associated with the instructions. |
| US11323188B2 |
Monitoring systems and methods for radios implemented with digital predistortion
Disclosed are implementations, including a method for monitoring a performance of a transmitter in a radio with an adjustable digital predistortion system. The method includes determining a plurality of system characteristics, including determining one or more of, for example, data characterizing an input/output characteristic of a digital predistorter of the system, data characterizing a performance of a crest factor reduction process of the system, data characterizing a quality of a plurality of parameters associated with the digital predistorter, data characterizing an average time delay associated with the system, data characterizing an average gain associated with the system, and/or data characterizing a phase associated with the system. The method further includes comparing one or more of the plurality of system characteristics to respective one or more reference values, and controlling the adjustable digital predistortion system based on a result of the comparing. |
| US11323187B2 |
Smart nodes for monitoring a passive distributed antenna system
A system for monitoring passive components of a passive distributed antenna system is disclosed. The system includes a bi-directional amplifier, a public safety monitor coupled to and in communication with the bi-directional amplifier, and at least one smart node coupled to and in communication with the public safety monitor. The at least one smart node is positioned within the passive distributed antenna system and includes a processor, connected to or coupled to a spectrum analysis module configured to monitor signal characteristic information of at least one radio frequency signal passing through the passive distributed antenna system. The processor is configured to transmit the signal characteristic information to the public safety monitor and the public safety monitor generates system performance information based on a signal at the bi-directional amplifier and the transmitted signal characteristic information. |
| US11323185B2 |
Method and system for waveguide delay based equalization with summing at single-ended to differential converters in optical communication
Methods and systems for waveguide delay based equalization summing at single-ended to differential converters in optical communication are disclosed and may include: in an photonic circuit including a directional coupler, photodetectors, and a gain stage, receiving an input optical signal; splitting the input optical signal into first and second optical signals using the directional coupler; generating a first current from the first optical signal using a first photodetector; communicating the first voltage to a first input of the gain stage; generating a second current from the second optical signal using a second photodetector; communicating the second voltage to a second input of the gain stage; and generating a differential output voltage based on the first and second currents using the gain stage. |
| US11323183B1 |
Analog front-end
Examples described herein relate to an analog front-end (AFE). The AFE includes a trans-impedance amplifier to receive an input current and generate a pair of the differential voltage signals based on the input current and a reference current. Further, the AFE includes a dynamic voltage slicer to receive the differential voltage signals at input terminals and supply digital voltages at output terminals. The dynamic voltage slicer includes a preamplifier to generate a pair of intermediate voltages based on the differential voltage signals sampled at a predetermined frequency. The dynamic voltage slicer also includes a voltage latch circuit coupled to the preamplifier, wherein the voltage latch circuit is to regenerate a pair of digital voltages based on the pair of the intermediate voltages. Moreover, the AFE includes a logic latch coupled to the dynamic voltage slicer to provide digital output states based on the pair of the digital voltages. |
| US11323177B2 |
Method and system for free space optical communication performance prediction
Various embodiments provide a method for free space optical communication performance prediction method. The method includes: in a training stage, collecting a large number of data representing FSOC performance from external data sources and through simulation in five feature categories; dividing the collected data into training datasets and testing datasets to train a prediction model based on a deep neural network (DNN); evaluating a prediction error by a loss function and adjusting weights and biases of hidden layers of the DNN to minimize the prediction error; repeating training the prediction model until the prediction error is smaller than or equal to a pre-set threshold; in an application stage, receiving parameters entered by a user for an application scenario; retrieving and preparing real-time data from the external data sources for the application scenario; and generating near real-time FSOC performance prediction results based on the trained prediction model. |
| US11323175B1 |
Fast system optimization (FSO) with optimally placed recovery tones
Described herein is an apparatus including a continuous wave idler and an optical coupler that provide an optical signal having a power greater than optical channels carrying data, and positioned at a cross-over point between two spectral bands, with each band encompassing multiple optical channels. |
| US11323173B2 |
Ground-based antenna for concurrent communications with multiple spacecraft
A system includes an antenna of a ground station. The antenna is configured to generate signal beams. The signal beams define a plurality of cells in the sky. The antenna is fixed in position relative to the ground and mechanically fixed to a particular orientation. The antenna is a phased array antenna. The system also includes a processor coupled to the antenna. The processor is configured to support concurrent communication sessions with a plurality of spacecraft via the signal beams. The plurality of spacecraft is located within the plurality of cells. |
| US11323167B2 |
Communication time allocation method using reinforcement learning for wireless powered communication network and base station
The disclosure provides a communication time allocation method using reinforcement learning for a wireless powered communication network and a base station. The method includes: determining a communication time allocation corresponding to the t-th time block according to an objective function associated with the total estimated throughput of the communication nodes; requesting each communication node to perform specific communication behaviors according to the corresponding communication time interval in the t-th time block; obtaining the actual throughput of each communication node in the t-th time block; generating the weight vector of each communication node in the (t+1)-th time block according to the actual throughput, the weight vector, and the estimated throughput of each communication node in the t-th time block. |
| US11323163B2 |
Base station apparatus, terminal apparatus, wireless communication system and integrated circuit
A base station apparatus is capable of adjusting antenna gains in a horizontal direction and a vertical direction of the plurality of antennas included in the base station apparatus, by adjusting a phase and an amplitude of a signal addressed and transmitted to a terminal apparatus, stores a codebook which is shared with the terminal apparatus and describes a plurality of linear filters associated with antenna gains in the horizontal direction and antenna gains in the vertical direction, acquires control information indicating at least one out of a plurality of linear filters described in the codebook, of which notification is sent from the terminal apparatus, performs precoding on the signal addressed to the terminal apparatus, based on the control information and the first codebook, and transmits the signal subjected to the precoding. |
| US11323162B2 |
Data detection in MIMO systems with demodulation and tracking reference signals
What is disclosed is a method for wireless communication comprising receiving a wireless communication via a receiver of the mobile communication device, deriving a demodulation reference signal from a first plurality of symbols of the wireless communication; creating a channel estimation matrix using the demodulation reference signal; inverting the channel estimation matrix to obtain a channel pseudo-inverse matrix; deriving a tracking reference signal from a second plurality of symbols of the wireless communication; calculating a phase shift for one or more additional symbols based on the tracking reference signal; determining a corrected channel pseudo-inverse matrix for the one or more additional symbols by adjusting the channel pseudo-inverse matrix according to the calculated phase shift; and controlling the receiver to accomplish data detection using the corrected channel pseudo-inverse matrix on one or more orthogonal frequency division multiplexing subcarriers. |
| US11323158B2 |
Beamforming communication systems with power amplifier output impedance tuning control
Apparatus and methods for beamforming communication systems with power control based on antenna pattern configuration are provided. In certain embodiments, a beamforming communication system includes an antenna array including a plurality of antenna elements. The beamforming communication system further includes a plurality of signal conditioning circuits operatively associated with the antenna elements, and an antenna array management circuit that generates a plurality of control signals that individually control the signal conditioning circuits. The antenna array management circuit achieves a desired level of power control based on generating the control signals to select an antenna pattern configuration associated with a desired power control level. |
| US11323157B2 |
Downlink channel estimation method and apparatus based on sounding reference signal and communications system
A downlink channel estimation method and apparatus based on a sounding reference signal (SRS), and a communications system. The method includes: a base station receives a SRS sent by UE, the SRS being used for downlink channel estimation and supporting high-dimensional MU-MIMO; performing uplink channel estimation according to the SRS; and acquiring downlink channel information according to uplink channel information obtained in the uplink channel estimation. By means of embodiments of the present disclosure, downlink reference signal overheads and feedback overheads can be remarkably reduced, gain brought by large-scale antennas is obtained, and the system capacity can be further improved. |
| US11323156B2 |
Base station apparatus, terminal apparatus, and communication method
A terminal apparatus and a communication method are provided. The terminal apparatus communicates with a base station apparatus. The terminal apparatus includes a receiver and a measurement unit. The receiver is configured to receive downlink signals and configuration information in a first component carrier and a second component carrier. The measurement unit is configured to calculate Channel State Information (CSI) of the first component carrier and the second component carrier. In a case that spatial Quasi-coloration (QCL) for reception parameters is configured between the first component carrier and the second component carrier in the configuration information, the CSI of the first component carrier and the CSI of the second component carrier are calculated with a same reception parameter. |
| US11323149B2 |
Receiver feedback of repetition configuration
A method, a computer-readable medium, and an apparatus are provided for wireless communication comprising repetitions that provide a solution to the problem of identifying and refining a repetition configuration at a transmitter. A transmitter receives repetition configuration information from a receiver and transmits repetitions of a signal to the receiver based on the received repetition configuration information. The repetition configuration information comprises an indication of at least one of a repetition frequency hopping indicator, at least one beam index, a repetition type or whether repetition is enabled. |
| US11323147B1 |
Reducing insertion loss in a switch for a communication device
A switch is provided for a communication device operating in the RF or microwave frequency range. The switch can include one or more PIN diodes and a biasing circuit that includes one or more inductors. When operating at RF and/or microwave frequencies, the switch can be configured as a low pass filter using the parasitic inductances and capacitances of the PIN diodes and inductors to minimize the insertion loss of the switch. The parasitic capacitances for the low pass filter can be provided by operating the inductors of the switch above their self-resonant frequency such that the inductors operate like capacitors. The parasitic inductances for the low pass filter can be provided by the PIN diodes. |
| US11323144B2 |
Method and device for indicating inter-modulation distortion, base station, and user equipment
A method for indicating inter-modulation distortion (IMD) includes: sending a query request to user equipment (UE) when a second base station is to be configured for the UE, the query request being used for querying whether IMD will be generated for downlink reception when the UE simultaneously performs uplink transmission on a uplink frequency band combination to be configured by a first base station and the second base station; receiving a determining result fed back by the UE according to the query request; and configuring uplink transmission and downlink reception for the UE on a corresponding frequency band according to the received determining result. As such, signaling overhead of a system can be greatly reduce, and the occurrence of IMD can be avoided. |
| US11323143B1 |
Device and method for wireless transmission
In certain aspects, a device for wireless transmission includes a transmission path, a feedback path, and a DPD control module. The transmission path includes a digital pre-distortion (DPD) conversion module configured to perform pre-distortion processing on an amplitude and a phase of a transmission signal based on a pre-distortion processing strategy. The transmission path further includes a power amplifier coupled to a downstream of the DPD conversion module and configured to amplify a power of the transmission signal. The feedback path is coupled to the transmission path at the downstream of the power amplifier and configured to generate a feedback signal. The DPD control module is coupled to the feedback path and the DPD conversion module and configured to adjust the pre-distortion processing strategy based on an amplitude difference and a phase difference between the transmission signal and the feedback signal. |
| US11323142B2 |
Radio frequency module and communication device
A radio frequency module includes: a module board including a first principal surface and a second principal surface on opposite sides of the module board; an antenna connection terminal; a diplexer connected to the antenna connection terminal and including at least a first inductor which is a chip inductor; a transmission power amplifier; and a first circuit component disposed on a transmission path connecting the diplexer and the transmission power amplifier. The first inductor is disposed on the first principal surface, and one of the transmission power amplifier and the first circuit component is disposed on the second principal surface. |
| US11323141B2 |
Control method of multi-antenna module
A control method of a multi-antenna module includes the following. Antennas generating signals in at least a first frequency band and a second frequency band are provided. The antennas are divided into a first group and a second group by detecting performance of the antennas in the first frequency band and the second frequency band. Antennas of the first group have better performance in the first frequency band than in the second frequency band, and antennas of the second group are antennas other than the antennas of the first group. The number of the antennas of each of the first group and the second group is at least greater than or equal to 2. The first group is instructed to generate the signals in the first frequency band, and the second group is instructed to generate the signals in the second frequency band. |
| US11323138B1 |
Reed-Solomon code soft-decision decoding method and device
Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even. |
| US11323137B2 |
Method for performing beliefs propagation, computer program product, non-transitory information storage medium, and polar code decoder
A decoder performs: computing (S501) a value (i,j) of a performance-improvement metric for each kernel Ki,j; and sorting (S502) the kernels in a list in decreasing order of the values (i,j). The decoder then performs a beliefs propagation iterative process as follows: updating (S503) output beliefs for the W top kernels of the list , and propagating said output beliefs as input beliefs of the neighbour kernels of said W top kernels; updating (S504) output beliefs for each neighbour kernel of said W top kernels following update of their input beliefs, and re-computing (S505) the performance-improvement metric value (i,j) for each said neighbour kernel; setting (S505) the performance-improvement metric for said W top kernels to a null value; and re-ordering (S506) the kernels in the list . Then, the decoder repeats the beliefs propagation iterative process until a stop condition is met. |
| US11323134B2 |
Encoding method and device and decoding method and device for structured LDPC
Provided is an encoding method and device and a decoding method and device for structured LDPC. The encoding method includes: determining a base matrix used for encoding and performing an LDPC encoding operation on a source information bit sequence according to the base matrix and an expansion factor Z corresponding to the base matrix to obtain a codeword sequence, where Z is a positive integer. The base matrix includes multiple submatrices and the submatrices include an upper-left submatrix Hb1 and an upper-left submatrix Hb2, and the upper-left submatrix Hb1 is an upper-left submatrix of the upper-left submatrix Hb2. |
| US11323133B2 |
Flash memory apparatus and storage management method for flash memory
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks. |
| US11323132B2 |
Encoding method and encoding apparatus
An encoding apparatus includes a memory and a processor configured to acquire text data, specify a first dynamic dictionary among a plurality of dynamic dictionaries based on attribute information of a first word included in the text data, register the first word in association with a first dynamic code in the first dynamic dictionary, and encode the first word into the first dynamic code. |
| US11323121B2 |
Programmable device structure based on mixed function storage unit
A programmable device structure based on a mixed function storage unit includes a storage unit SRAM and a mixed function unit, wherein the storage unit comprises n register units and at least one selection control bit, wherein n=2{circumflex over ( )}x, and x is natural number; the register units are selected according to the selection control bit; and when the selection control bit selects the mixed function unit to serve as a lookup table, a logic function is achieved; or when the selection control bit selects the mixed function unit to serve as a multiplexer, a routing function is achieved. By multiplexing the register units, the programmable device structure achieves a routing function of a traditional FPGA and also provides a logic function, and the waste of resources is greatly reduced. |
| US11323119B2 |
Semiconductor device
A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch. |
| US11323114B2 |
Electrical system
An electrical system may include a mounting surface, a component configured for connection with the mounting surface and configured to move relative to the mounting surface, and/or an orientation sensor configured to determining an orientation of the component relative to the mounting surface. The orientation sensor may include a first sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected, at least indirectly, to the mounting surface, and a second sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected to move with the component. The orientation sensor may include an electronic controller. The electronic controller may be configured to compare first information from the first sensor to second information from the second sensor to determine the orientation of the component relative to the mounting surface. |
| US11323113B2 |
Current flow control device
A current flow control device includes a plurality of semiconductor switches disposed between a power source and a load and that are connected in parallel with each other, and the current flow control device being configured to control the flow of current between the power source and the load by turning on and off the semiconductor switches. The plurality of semiconductor switches include a first and a second semiconductor switch. The current flow control device includes a driving circuit configured to apply, to the first semiconductor switch, a voltage that is higher than a voltage output from the power source, to turn on the first semiconductor switch, a switch control unit configured to turn on the second semiconductor switch, and a resistor that is connected in series with a terminal on the power source side of the second semiconductor switch, the resistor lowering a voltage applied to the terminal. |
| US11323112B2 |
IGBT drive circuit for motor controller, and motor controller
The present disclosure discloses an IGBT driving circuit for an electric-motor controller and an electric-motor controller. The IGBT driving circuit includes: a function safety circuit provided on a driver board of the electric-motor controller, and a detection feedback circuit and a pulse-width-modulation (PWM) buffer circuit that are connected to the function safety circuit. The detection feedback circuit is configured to detect an IGBT module of the electric-motor controller, and when a specified malfunction of the IGBT module is detected, send a specified-malfunction signal to the function safety circuit. The function safety circuit is configured to judge according to a preset malfunction treating rule and the received specified-malfunction signal, and then output a corresponding controlling signal to the PWM buffer circuit. The PWM buffer circuit is configured to generate according to the corresponding controlling signal a PWM signal that drives the IGBT module, to control ON/OFF of the IGBT module to protect the IGBT module. The technical solutions of the present application have multiple functions of protection, which improves the stability and the safety of the IGBT, and has quick action and timely protection. |
| US11323107B2 |
Semiconductor apparatus including clock paths and semiconductor system including the semiconductor apparatus
A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths. |
| US11323105B2 |
Method and system for arbitrary optical pulse generation
A system, method, and apparatus for continuous seed laser pulses supplied to a CW pumped pre-amplifier and/or power-amplifier chain comprises an optical modulator configured to impress pulse signals on an optical signal, a waveform generator configured to establish a structure of the optical signal, and a keep-alive circuit that generates a continuous electrical pulse pattern provided to the optical modulator, wherein the system provides a continuous seed laser pulse structure. |
| US11323099B2 |
Electronic circuit with a transistor device and a biasing circuit
Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage. |
| US11323091B2 |
Transversely-excited film bulk acoustic resonator with diaphragm support pedestals
Acoustic resonator devices and methods are disclosed. An acoustic resonator device includes a substrate having a surface and a piezoelectric plate having front and back surfaces. The back surface of the piezoelectric plate is attached to the surface of the substrate except for a portion of the piezoelectric plate forming a diaphragm that spans a cavity in the substrate. An interdigital transducer (IDT) is formed on the front surface of the piezoelectric plate such that interleaved fingers of the IDT are disposed on the diaphragm. One or more diaphragm support pedestals extend between the substrate and the diaphragm within the cavity. |
| US11323089B2 |
Filter using piezoelectric film bonded to high resistivity silicon substrate with trap-rich layer
Acoustic resonator devices and filters are disclosed. An acoustic resonator includes a substrate having a trap-rich region adjacent to a surface and a single-crystal piezoelectric plate having parallel front and back surfaces, the back surface attached to the surface of the substrate except for a portion of the piezoelectric plate forming a diaphragm that spans a cavity in the substrate. An interdigital transducer (IDT) is formed on the front surface of the single-crystal piezoelectric plate such that interleaved fingers of the IDT are disposed on the diaphragm. The single-crystal piezoelectric plate and the IDT are configured such that a radio frequency signal applied to the IDT excites a shear primary acoustic mode within the diaphragm. |
| US11323088B2 |
Acoustic wave resonator
An acoustic wave resonator includes a resonating part disposed on and spaced apart from a substrate by a cavity, the resonating part including a membrane layer, a first electrode, a piezoelectric layer, and a second electrode that are sequentially stacked. 0 Å≤ΔMg≤170 Å may be satisfied, ΔMg being a difference between a maximum thickness and a minimum thickness of the membrane layer disposed in the cavity. |
| US11323086B2 |
Content audio adjustment
Methods, systems, and apparatuses are described for optimizing user content consuming experience by recognizing and classifying different sounds while a user views a program. The system may have or may access information related to the program audio being presented, enabling it to distinguish between conversations occurring in the program audio and conversations between users in the viewing environment. The system may turn the program volume down on one or more sound producing devices if it detects a conversation. The system may turn the program volume up if it detects an interrupting noise. The system may also adjust the program content based on locations of various objects within the listening or viewing environment, and types of users in the environment. |
| US11323084B2 |
Linear amplifier
A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage. |
| US11323082B2 |
Class-D amplifier which can suppress differential mode power noise
A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit. |
| US11323081B2 |
Power amplifier circuit
A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors. |
| US11323080B2 |
Amplification circuit, radio-frequency front end circuit, and communication device
An amplification circuit includes: an amplifier including a transistor that is connected between an input terminal and an output terminal; an input matching network that is connected between the input terminal and an input side of the amplifier and converts an impedance from a low impedance to a high impedance; a limiter circuit that is connected between a node between the input matching network and the input side of the amplifier, and ground and includes two diodes connected in opposite directions to each other; and a capacitor that is connected in series with the limiter circuit between the node and ground. |
| US11323078B2 |
Scalable periphery tunable matching power amplifier
A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. |
| US11323073B2 |
Front-end for processing 2G signal using 3G/4G paths
Front-end for processing 2G signal using 3G/4G paths. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal. |
| US11323070B1 |
Oscillator with fin field-effect transistor (FinFET) resonator
An integrated circuit may include oscillator circuitry having a resonator formed from fin field-effect transistor (FinFET) devices. The resonator may include drive cells of alternating polarities and sense cells interposed between the drive cells. The resonator may be connected in a feedback loop within the oscillator circuitry. The oscillator circuitry may include an amplifier having an input coupled to the sense cells and an output coupled to the drive cells. The oscillator circuitry may also include a separate inductor and capacitor based oscillator, where the resonator serves as a separate output filter stage for the inductor and capacitor based oscillator. |
| US11323069B2 |
Resonator circuit
A resonator circuit includes a transformer comprising a primary winding and a secondary winding. The primary winding is inductively coupled with the secondary winding. A primary capacitor is connected to the primary winding. The primary capacitor and the primary winding form a primary circuit. A secondary capacitor is connected to the secondary winding. The secondary capacitor and the secondary winding form a secondary circuit. The resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode. The resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode. The common mode resonance frequency is different from the differential mode resonance frequency. |
| US11323061B2 |
AC rotating electric machine control device
A control device for an AC rotating electric machine includes: a temperature detection unit configured to detect a temperature of a protection part; a maximum current adjustment unit configured to adjust a maximum current of an AC rotating electric machine so as to prevent the temperature of the protection part from exceeding a set temperature; an allowable torque calculation unit configured to calculate an allowable torque based on the maximum current adjusted; a torque command adjustment unit configured to adjust a torque command value directed to the AC rotating electric machine based on the allowable torque; an upper limit number-of-rotation calculation unit configured to calculate an upper-limit number of rotations of the AC rotating electric machine based on the maximum current adjusted; and a number-of-rotation adjustment unit configured to adjust the number of rotations of the AC rotating electric machine based on the upper-limit number of rotations. |
| US11323059B2 |
Power conversion device, X-ray image capturing apparatus, and motor drive device
A power conversion device comprising: a three-phase conversion circuit in which each of upper arm elements which are switching elements in an upper arm and each of lower arm elements which are switching elements in a lower arm are provided for each of three phases; and a switching control unit which alternately switches between an upper arm period of holding one of the upper arm elements ON and a lower arm period of holding one of the lower arm elements ON, wherein the switching control unit switches between the upper arm period and the lower arm period, based on an integrated value of power which is calculated by integrating a power pattern which is set beforehand. |
| US11323053B2 |
Bipolar stepper motor driving device
A bipolar stepper motor driving device drives a stepper motor including stator coils having plural phases. The bipolar stepper motor driving device includes H-bridge circuits, a current detector, a control circuit, and a re-turning-on instruction unit. The H-bridge circuits are provided correspondingly to the phases of the respective stator coils. The current detector detects current flowing in the stator coils. The control circuit executes drive control of the H-bridge circuits. The re-turning-on instruction unit commands the control circuit to switch into a short-circuited state a stator coil which has shifted from an energized state to an off-state among the stator coils, on a condition that an absolute value of a reverse current detected by the current detector has changed from a value larger than a threshold current value to a value smaller than the threshold current value. |
| US11323050B2 |
Power supply apparatus
According to one embodiment, the controller configured to, when an operation of the boosting circuit is in the boosting mode, and if an instantaneous value Ia of a current flowing through the reactor lowers to a value smaller than or equal to a set value Ias, switch the operation of the boosting circuit from the boosting mode to the non-boosting mode. |
| US11323048B2 |
Device for driving a plurality of motors and electric apparatus including the same
A device for driving a plurality of motors and an electric apparatus includes a first and a second capacitor, an inverter connected to a DC terminal, a multi-phase motor connected to the inverter, a single-phase motor serially connected with the multi-phase motor, and a controller configured to control the inverter. For starting the single phase motor during operation of the multi-phase motor, the controller is configured to perform, during an alignment period, an alignment of a rotor of the single-phase motor and perform, during a voltage compensation period, a voltage compensation for compensating a voltage change of a DC terminal neutral point between the first capacitor and the second capacitor based on the alignment of the rotor of the single-phase motor. |
| US11323047B2 |
Contact body easy to verify resin impregnation, manufacturing method thereof, and vibration actuator including contact body
A contact body that makes it possible to easily verify whether or not the resin has been properly impregnated in the pores. A metallic sintered body having a plurality of pores, as a main body, is in contact with a vibration element in a vibration actuator. The contact body includes a sliding portion that has a sliding surface in contact with the vibration element, and a non-sliding portion adjacent to the sliding portion and not in contact with the vibration element. The non-sliding portion is provided with a resin lump containing hard particles and resin, and the resin lump is formed to be lower in height in a vertical direction than the sliding surface. In the sliding portion, part of hard particles and resin is exposed on the sliding surface. |
| US11323044B2 |
Three-level inverter and a three-level brake chopper
A circuit comprising a first power node for connection to a positive voltage of a DC link, a second power node for connection to a negative voltage of the DC link and a mid-point power node for connection to a mid-point voltage of the DC-link, the circuit further comprising a three-level neutral point clamped converter module and a brake resistor connection. |
| US11323041B2 |
Semiconductor device
A higher-current device is implemented by increasing cross-sectional areas of terminals while securing solderability during mounting. The device makes securing of a creepage distance between terminals compatible with a reduction in package size. A semiconductor device 1 is provided with a package 2, a semiconductor circuit 3, a control circuit 6, a plurality of main terminals 7 and control terminals 8. Each main terminal 7 is configured of a plurality of subterminals S1, S2 and S3 arranged at mutually neighboring positions and projecting from the package 2. Distal end portions of the subterminals S1, S2 and S3 making up the same main terminal 7 are bent toward a mounting surface on which the semiconductor device 1 is mounted and the bending positions of the subterminals S1, S2 and S3 are configured to differ between the mutually neighboring subterminals S1 and S2, and subterminals S2 and S3. |
| US11323040B2 |
Device and method for protecting power circuit of base station in wireless communication system
The purpose of the present disclosure is to protect a power circuit of a base station in a wireless communication system, the base station comprising: at least one module for processing a signal; and the power circuit for supplying power to the at least one module. The power circuit comprises a transformer, a rectifier circuit and a smoothing circuit, and the power circuit reduces the ratio of an on-section of the rectifier circuit if a reverse current from the at least one module is detected. |
| US11323039B2 |
Method for improving conversion efficiency of CCM mode of flyback resonant switch power supply
A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a critical value Tset, calculating a time interval Ttap between adjacent zero points in the current connection time, outputting a shutdown signal at the zero points, and comparing the time interval Ttap with the preset critical value Tset; when Ttap>Tset, controlling the current shutdown time to be less than the shutdown time of the preceding cycle and outputting a start signal; when Ttap=0, controlling the current shutdown time to be greater than the shutdown time of the preceding cycle and outputting a start signal; and when 0 |
| US11323038B2 |
Single phase single stage bi-directional level 1 electric vehicle battery charger
A single phase single stage level-1 electric vehicle (EV) battery charger can control the power flow in both directions. The converter efficiency is high as the devices undergo ZCS which reduces switching loss in the devices. This converter does not require any intermediate DC link capacitor stage and the power density of the converter is high. |
| US11323037B2 |
Forward converter with secondary LCD connected in series to realize excitation energy transfer
The present disclosure provides a forward converter with secondary LCD connected in series to realize excitation energy transfer, comprising a forward converter main circuit and an energy transfer and transmission circuit. The forward converter main circuit includes a high-frequency transformer T, a switching tube S, a diode D1, a diode D2, an inductance L1, and a capacitor C1. The energy transfer and transmission circuit includes a diode D3, a capacitor C2, and an inductance L2. The circuit structure of the present disclosure has simple circuit structure and high reliability. And the reverse recovery problem of the diode could be eliminated by the soft switch-off or soft switch-on of the switching tube, which further reducing the loss of switching tube and diodes and improving the overall efficiency. In addition, the excitation energy could be transferred to the load side to improve the energy transmission efficiency. |
| US11323032B2 |
Plural power modules conversion device with switch element control
A power conversion device according to the present invention is provided with two or more sets of power modules each of which includes a switching element and a switching element control circuit having a third electrode voltage control part and a temperature detection part. The power modules PM1, PM2 are connected in parallel to each other. The switching element control circuit includes a temperature comparison part which calculates an average operation temperature of the switching element, and compares an operation temperature of the corresponding switching element and the average operation temperature. The third electrode voltage control part controls a third electrode voltage based on information including an average operation temperature, an operation temperature of the switching element, and a threshold voltage during operation. |
| US11323031B2 |
Half-bridge driver circuit with a switched capacitor supply voltage for high side drive signal generation
First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches. |
| US11323029B2 |
System and method of automatic calibration to maximize load current support of DC-DC converter operating in pulse-pairing mode
A DC-DC converter including converter circuitry, a voltage detector providing a low voltage signal, and pulse-pairing circuitry. The converter circuitry may be configured according to a buck or a boost configuration switching between a zero and peak current levels. The pulse-pairing circuitry includes a paired pulse generator, a load detector, and a maximum on timing controller. In response to the low voltage signal, the paired pulse generator activates an on signal for a pair of equal duration on pulses separated by a predetermined pulse separation interval. The on time periods are based on an adjustable time value and a peak current indication. The load detector provides a load adjust signal for adjusting the time value based on sampling the low voltage signal and an off time signal at the start of the second pulse. The maximum on timing controller adjusts the adjustable time value based on the load adjust signal. |
| US11323025B2 |
Power converter
A DC capacitor and a leg are connected in parallel to a high-voltage-side power line and a low-voltage-side power line. The leg includes a plurality of semiconductor switching elements connected in series between the power lines with an output end, connected to a load, between the plurality of semiconductor switching elements. An attenuator for attenuating a resonance is connected to a main circuit loop formed of the DC capacitor, the high-voltage-side power line, the low-voltage-side power line, a semiconductor switching element in ON state, and a drain-source parasitic capacitance of a semiconductor switching element in OFF state. |
| US11323022B2 |
System for controlling inductor current of boost converter
A system for controlling an inductor current of a boost converter includes a start-up controller that is configured to generate a control signal that has a fixed on-time duration and a dynamic off-time duration that decreases with each cycle of the control signal, and a pulse width modulation (PWM) circuit that is configured to generate a PWM signal. During a start-up of the boost converter, the PWM signal transitions from a deactivated state to an activated state when the control signal is activated, and from an activated state to a deactivated state when the inductor current is equal to a reference current. The reference current corresponds to a peak value of the inductor current during the start-up. Thus, during the start-up, the duty cycle of the PWM signal increases with each cycle of the PWM signal. The PWM signal is provided to the boost converter for controlling the inductor current. |
| US11323019B2 |
System and method for current pulse matching technique in a switched mode power converter
A switched mode power supply converter comprises a circuit pulse matching circuit configured to negate output voltage disturbance or noise during switching operation of a power conversion. The current pulse matching circuit input is driven by, or from, a power converter switch node of the switched mode power supply converter. The current pulse matching circuit comprises a rate-of-voltage change detection circuit driven by the power converter switch node. |
| US11323015B2 |
Actuator
An actuator is provided. In order to reduce the planar area of an actuator, a first magnetic drive circuit and a third magnetic drive circuit that vibrate a movable body in an X direction with respect to a support are provided respectively on both sides, in a Z direction, of a second magnetic drive circuit that vibrates the movable body in a Y direction with respect to the support. The movable ranges, in the X direction and the Y direction, of the movable body with respect to the support are regulated by a stopper mechanism constituted between a first magnet and a first coil holder holding a first coil, a stopper mechanism constituted between a second magnet and a second coil holder holding a second coil, and a stopper mechanism constituted between a third magnet and a third coil holder holding a third coil. |
| US11323014B2 |
Driving motor with asymmetric magnetic pole type of permanent magnet and claw pole electric excitation for electric automobile
The disclosure discloses a driving motor with an asymmetrical magnetic pole type of permanent magnet and claw pole electric excitation for an electric automobile which includes a front end cover, a rear end cover, a housing, an asymmetric magnetic pole type of permanent magnet rotor, a claw pole electric excitation rotor, and a stator. Wherein the asymmetric magnetic pole type of permanent magnet rotor is provided with first magnetic pole groups and second magnetic pole groups, the first magnetic pole groups and the second magnetic pole groups are of an asymmetric structure, polarities of outer sides of the first magnetic pole groups and the second magnetic pole groups are distributed in a manner of N poles and S poles arranged at intervals. A utilization of inner space of the motor rotor can be improved, the performance of the motor is improved, and the costs of the motor are reduced. |
| US11323010B2 |
Electric Machine
An electric machine, including a stator and a rotor shaft having a cooling device, which shaft carries at least one slip ring, which has a lateral surface, which electrically contacts a contact element fixed on the stator, and which is at least partially accommodated in a recess of the rotor shaft, wherein an extension section of the slip ring, which is at least partially accommodated in the recess, extends beyond the lateral surface in one or both axial directions of the rotor shaft. |
| US11323007B2 |
Magnetic levitation bearing, magnetic levitation rotor support assembly, and compressor
A magnetic levitation bearing, a magnetic levitation rotor support assembly, and a compressor. The magnetic levitation bearing is used for supporting a rotor by interacting with a thrust disc on the rotor, and comprises: a radial stator core having an annular structure, which is disposed on a radial outer side of the thrust disc and corresponds to the thrust disc in an axial direction of the rotor, the radial stator core and the thrust disc being separated by a first radial gap X1; and a radial control coil, which is disposed on the radial stator core and can generate a radial electromagnetic force to the thrust disc in a radial direction of the rotor. |
| US11323006B1 |
Multiple-discharge rain manifold for electric motor cooling and related system and method
An apparatus includes a housing configured to receive at least a portion of an electric motor. The apparatus also includes a manifold disposed on an upper surface of the housing. The manifold includes a number of vertical jets configured to target one or more portions of the electric motor, the vertical jets includes multiple vias extending between (i) a cavity within the manifold and (ii) an interior portion of the housing. The cavity within the manifold is defined by (i) at least a portion of the upper surface of the housing, (ii) one or more side walls extending from the upper surface of the housing, and (iii) a cover lid coupled to the one or more side walls and configured to cover the cavity and the vias. |
| US11323004B2 |
Rotating electric machine
A rotating electric machine includes a non-rotating member, a stator fixed to the non-rotating member, a field coil fixed to the non-rotating member, disposed on an inner diameter side of the stator, and having an iron core and a winding wound around the iron core, and a rotor rotatably disposed between the stator and the iron core. A flow path through which a heat exchange medium is supplied and discharged is formed in the iron core along an axial direction thereof. |
| US11323003B2 |
Compact, modular, pump or turbine with integral modular motor or generator and coaxial fluid flow
A coaxial pump or turbine module includes an integral, modular motor or generator comprising a magnet structure containing radial or axial permanent magnets and/or induction coils detachably fixed to a rotor, and a stator housing detachably fixed to the module housing. Working fluid is directed axially through a flow path symmetrically distributed within an annulus formed between the module housing and the stator housing. The stator housing can be cooled by the working fluid, or by a cooling fluid flowing between passages of the flow path. The flow path can extend over substantially a full length and rear surface of the stator housing. A plurality of the modules can be combined into a multi-stage apparatus, with rotor speeds independently controlled by corresponding variable frequency drives. Embodiments include guide vanes and/or diffusers. The rotor can be fixed to a rotating shaft, or rotate about a fixed shaft. |
| US11323000B2 |
Motor, stator module and coil winding method thereof
A winding method for a stator module applicable to a motor having z slots, 2p poles, and m phases. The stator module includes a stator core and a winding coil. The winding coil is made of a flat wire. The winding method includes: forwardly winding some stator slots by means of the arrangement and connection of multiple U-shaped conductor sections, and then reversely winding the stator slots; afterwards, forwardly winding the remaining stator slots, and then reversely winding the stator slots; and cycling in this way. |
| US11322997B2 |
Rotor for a synchronous drive motor
The invention relates to a rotor for a synchronous drive motor of an electrically driven motor vehicle having several rotor poles, wherein each rotor pole has at least three magnetic layers arranged radially one after the other with cavities, wherein an outermost magnetic layer includes at least one cavity filled with permanent magnetic material and each further magnetic layer includes at least two cavities filled with permanent magnetic material, furthermore each magnetic layer has an extension of a section of an ellipse, furthermore the central points of all ellipses lie within the smallest ellipse of the outer magnetic layer, wherein each cavity belonging to one of the at least three magnetic layers defines an interface in a radial plane, and each of these interfaces of a magnetic layer of the corresponding ellipse is divided into two partial interfaces, wherein bars made of the rotor material are formed in the second and every other magnetic layer between the cavities, and these bars, at the narrowest point, are at least twice as wide as the respective outer bars of the same magnetic layer. |
| US11322993B2 |
Device and method for providing user interface according to wireless power-sharing
An electronic device including a battery, a wireless interface operatively or electrically connected with the battery, a display, a memory, and a processor, wherein the processor is configured to: detect an event while the electronic device is in contact with or is connected to another electronic device via the wireless interface and wirelessly charging-shares power of the battery with the another electronic device via the wireless interface; turn off a wireless charging-sharing function when the event corresponds to a predetermined condition; provide a user notification about the turning-off of the wireless charging-sharing function via the display; and turn on the wireless charging-sharing function when a state of the electronic device corresponds to a wireless charging-sharing condition. The various embodiments also a method of operating the electronic device. Various embodiments are also possible. |
| US11322991B2 |
Flexible management system for optical wireless power supply
A safety supervision system for wireless power transmission, comprising a transmitter having an optical beam generator with safe states for transmitting power to receivers that convert the beam into electrical power. The system control unit stores previously known signatures categorized by predetermined parameters associated with one or more unwanted situations, stores data from sensors, compares this stored data to the signatures, and executes one or more responses based on this comparison. The system may comprise transmitter and/or receiver malfunction detection systems adapted to monitor the transmitter and receiver control units and to cause the optical beam generator to switch to a safe state upon detection of a transmitter or receiver control unit malfunction, and may further comprise a hazard detection system preventing human exposure to beam intensity above a predefined safe level. |
| US11322990B2 |
Situation aware wireless power transmission
A method of RF power delivery includes, in part, transmitting a first group of RF signals having a first group of phases to a first mobile device during a first time period. The first mobile device has a first position and a first orientation during the first time period. The method further includes, in part, transmitting a second group of RF signals having a second group of phases to the first mobile device during a second time period. The second group of phases are determined in accordance with a second position and a second orientation of the first mobile device during the second time period. The second position and second orientation are determined using sensors disposed in the first mobile device and transmitted via a wireless communications channel to an RF power generating unit transmitting the first and second group of RF signals. |
| US11322988B1 |
Low power transmitter for sensor arrays
A low power transmitter includes a low frequency feedback loop, a high frequency switching element embedded within the low frequency feedback loop, and a mixer electrically communicating with the low frequency feedback loop and the high frequency switching element. The low frequency feedback loop employs either a voltage mode interface or a current mode interface. The high frequency switching element includes a first transistor, a second transistor, and a pair of inductive elements. Alternatively, the high frequency switching element includes a single transistor and a single inductive element. |
| US11322987B2 |
Electric power transmission apparatus, wireless electric power supply system, and electric power transmission method
An electric power transmission apparatus comprises a first antenna, a storage medium, and at least one first processor. The at least one first processor is configured to cause the first antenna to output a second radio wave for electric power supply in response to a request signal, when a first radio wave including the request signal is received from an electric power reception apparatus via the first antenna. The at least one first processor is configured to store information about an electric power transmission condition of the second radio wave transmitted in response to the request signal in the storage medium as history information. The at least one first processor is configured to cause the first antenna to output the second radio wave with the electric power transmission condition based on the history information, irrespective of whether or not the first radio wave has been received. |
| US11322985B2 |
Wireless power transfer system, power transmission apparatus, and power reception apparatus
A wireless power transfer system can be achieved at a low cost, can be used as both a power transmission apparatus and a power reception apparatus, and can cope with a change in coupling coefficient of a resonant coil of the power transmission apparatus and a resonant coil of the power reception apparatus. The wireless power transfer system is a power transmission apparatus that is able to perform bidirectional wireless power transmission, and includes the following: a power supply; a switching circuit that includes a plurality of switching devices; a resonator that includes a coil and a capacitor; a drive control circuit that controls an ON/OFF operation of each switching device of the switching circuit; and a detector that detects a resonance current flowing through the switching circuit. The drive control circuit controls the ON/OFF of each switching device of the switching circuit to perform a power transmission operation or a power reception operation based on a resonant current waveform detected by the detector. |
| US11322978B2 |
Reconfigurable heterogeneous energy harvester for SWIPT receiver and method of energy harvester reconfiguration
A method of energy harvester reconfiguration for a simultaneous wireless information and power transfer (SWIPT) receiver including receiving an input power from an RF signal, determining whether a Nblock-th energy block is activated based on a condition for operating the Nblock-th energy block having a maximum valid input power, among Nblock energy blocks each having a predetermined valid input power, in response to the Nblock-th energy block being determined activated, determining a number of energy harvesting circuits that are activated, among a plurality of energy harvesting circuits included in the Nblock-th energy block, based on power conversion efficiency, and reconfiguring power input in the Nblock-th energy block and the plurality of energy harvesting circuits included in the Nblock-th energy block, based on the determination and result of determination. |
| US11322975B1 |
Power source switching
A power source switching circuit is disclosed. The power source switching circuit includes a voltage regulator, a first transistor and a second transistor. The first transistor is coupled with a first voltage source and the second transistor is coupled with a second voltage source. The voltage regulator includes a resistor, one or more diodes coupled together in series and a capacitor. Terminals of the capacitor are coupled between a gate and a source of the first transistor through a first switch and a second switch respectively. The capacitor is configured to hold charge to switch the first transistor on. A value of the capacitor is smaller than a gate to source capacitance of the first transistor. |
| US11322974B2 |
Ferroresonant transformer systems and methods
A ferroresonant transformer assembly comprising, a core, a main shunt, first, second, and third windings, first and second tap connectors, and a selection connector. The first windings configured to be operatively connected to a primary power source. The first tap connector operatively connected to a first intermediate point defined by the third windings. The second tap connector operatively connected to a second intermediate point defined by the third windings. The selection connector operatively connected to the at least one load. Based on voltage requirements of the at least one load, the selection connector is operatively selectively connected to a selected tap connector selected from the first and second tap connectors. |
| US11322971B2 |
Energy harvesting wireless sensing systems
The disclosure generally relates to wireless sensing nodes, energy harvesting, and energy charging. The disclosure also generally relates to reporting data gathered by the wireless sensing nodes to one or more network services. |
| US11322965B2 |
Charging control device and method
A charging control device includes: a battery state detector configured to detect a cell voltage of at least one cell of a battery and a charging current between the battery and a charging device; and a controller configured to perform a cell over voltage protection (COVP) function on the battery based on a cell over voltage protection voltage, and to vary the cell over voltage protection voltage in response to the charging current. |
| US11322964B2 |
Automatic control method and device for solar supercapacitor power supply
An automatic control method and device for a solar supercapacitor power supply, including: obtaining a current state of a power supply device and a capacitor voltage of an energy storage element; if the capacitor voltage exceeds an initial discharge voltage in a pure charging state, the power supply device switches to a power supply state and begins to discharge; if the power supply device has been switched to the power supply state and the capacitor voltage is lower than the termination discharge voltage, the power supply device is switched to the pure charging state wherein, the initial discharge voltage is higher than the termination discharge voltage, and a charge and discharge with hysteresis effect is achieved. The method and device provided by the disclosure can achieve the charge and discharge with hysteresis effect of the power supply device. |
| US11322963B2 |
Control method for power supply
A control method for a power supply, in which a link capacitor is connected between an external load and a power relay assembly (PRA) that includes a precharge resistor to control a power flow between a battery and the external load, the control method including: initiating precharge; after the initiating of the precharge, measuring voltages of the link capacitor by measuring a first voltage V1 of the link capacitor at a first time T1, measuring a second voltage V2 of the link capacitor at a second time T2, and measuring a third voltage V3 of the link capacitor at a third time T3, the first time T1, the second time T2, and the third time T3 each being different times; calculating a capacitance C of the link capacitor using the first voltage V1, the second voltage V2, and the third voltage V3; and terminating the precharge. |
| US11322960B2 |
Battery system, vehicle, and method for controlling charge and discharge of a secondary battery
A battery system includes a battery pack including a plurality of cells, and an ECU. The ECU calculates a current distribution in each cell using a ladder circuit network model, the ladder circuit network model being obtained by geometrically modeling an interior of the cell using a plurality of resistance elements and a plurality of power storage elements. The ECU calculates the current distribution in the cell by applying, to the ladder circuit network model, a resistance distribution in the cell calculated based on a salt concentration distribution in the cell. |
| US11322946B2 |
Battery pack, method for controlling charging of battery pack, and vehicle comprising battery pack
Disclosed is a battery pack, including: at least one battery module which includes a plurality of battery cells and is connected between a first terminal and a second terminal; a relay connected between the first terminal and a third terminal; and a battery management system (BMS) which is connected to the first to third terminals, and generates a charge control signal controlling a charge operation of a charger connected to the third terminal based on battery detection information obtained by detecting the plurality of battery cells and the at least one battery module. |
| US11322941B2 |
Method for controlling ESS output
A method of controlling output of an ESS depending on droop control according to frequency variation range of a power grid in the present invention may comprise steps of: monitoring the frequency variation range of the power grid; predicting frequency correction range resulting from regulation of an engine generator during a predetermined unit regulation time if the frequency variation range is determined to exceed a first reference value; controlling the output of the ESS with an output value determined by a frequency of the power grid according to a droop control algorithm set as a default if the predicted frequency correction range does not exceed a second reference value; and fixing the output of the ESS during the unit regulation time if the predicted frequency correction range exceeds the second reference value. |
| US11322934B2 |
Protection of a surge arrester with a better protection against failure from thermal overload in case of a temporary overvoltage in an electrical grid line
This present application concerns a method for preventing an electrical grid from a failure in case of a temporary overvoltage. A method comprising: a) providing an electrical grid line, a surge arrester and a disconnector device with a disconnector unit; b) connecting the surge arrester at one terminal to the electrical grid line; c) connecting the surge arrester at its other terminal to a second terminal of the disconnector device; d) connecting a first terminal of the disconnector device to ground potential; e) interrupting the electrical connection in between the electrical grid line and the ground potential in case of a temporary overvoltage; f) protecting the surge arrester from failure due to a thermal overload caused by the temporary overvoltages by operating the disconnector device before the surge arrester fails due to a thermal overload of the surge arrester. |
| US11322925B2 |
Overcurrent detection device, energy storage apparatus, and current detection method
An overcurrent detection device including: a current detection resistor that is connected in series to a main circuit and is configured to cause a potential difference at both ends according to a current flowing through the main circuit; a current detection circuit that includes a pair of connection portions and is configured to detect a potential difference between the pair of connection portions; a pair of voltage detection lines connecting the both ends of the current detection resistor to the pair of connection portions in the current detection circuit; and an erroneous detection prevention unit configured to prevent an increase in the potential difference between the pair of connection portions when at least any one of the pair of voltage detection lines has a connection failure. |
| US11322920B2 |
Ribbed extruded electrical conduit
An extruded aluminum conduit comprising a substantially cylindrical body including defining a conduit interior. The body may include an exterior surface defined by an outer diameter and an interior surface defined by an inner diameter. The conduit may include one or more protrusions protruding from the interior surface of the body toward the conduit interior and away from the exterior surface. The one or more protrusions may run substantially continuously from a first end of the body to a second end of the body. |
| US11322917B2 |
Arrangement comprising a compartment and a slide-in module
An arrangement includes: a module insertable into a housing or removable from a housing; and a slide-in compartment for receiving the module. The module is reversibly removable from the slide-in compartment. At least one side wall and/or a compartment rear wall and/or a compartment base of the slide-in compartment in an inserted state of the module forms or form a side wall and/or rear wall and/or a base wall and/or a roof of at least one module. |
| US11322914B2 |
Spark plug
A spark plug is provided with a center electrode and a ground electrode. The ground electrode includes an electrode tip, an electrode base material, an intermediate member and a first melt portion. The intermediate member is disposed between the electrode tip and the electrode base material. The first melt portion contains components of the electrode base material and the intermediate member, and is disposed at least at a part of the boundary between the electrode base material and the intermediate member. In a cross section including the axis of the ground electrode, the boundary line between the intermediate member and the first melt portion has at least two first projection portions projecting toward the electrode tip side, and the boundary line between the electrode base material and the first melt portion has at least two second projection portions projecting toward the opposite side of the first projection portions. |
| US11322912B2 |
Semiconductor laser array, semiconductor laser element, semiconductor laser module, and wavelength-variable laser assembly
A semiconductor laser array includes: a plurality of semiconductor lasers configured to oscillate in a single mode at oscillation wavelengths different from one another, each semiconductor laser including an active layer including a multi-quantum well structure including a plurality of will layers and a plurality of barrier layers laminated alternately, and an n-side separate confinement heterostructure layer and p-side separate confinement heterostructure layer configured to sandwich the active layer therebetween in a thickness direction, band gap energies of the n-side separate confinement heterostructure layer and the p-side separate confinement heterostructure layer being greater than band gap energies of the barrier layers of the active layer. The active layer is doped with an n-type impurity. |
| US11322909B2 |
Semiconductor laser device
A semiconductor laser device includes: a first semiconductor layer of a first conductivity type; a light emitting layer formed above the first semiconductor layer; a second semiconductor layer of a second conductivity type formed above the light emitting layer; and an electrode formed above a ridge portion formed in the second semiconductor layer. The electrode is divided at positions at which an integrated value of light intensities of higher-order mode oscillation has a local maximum. |
| US11322908B2 |
Nitride light emitter
A nitride light emitter includes: a nitride semiconductor light-emitting element including an AlxGa1-xN substrate (0≤x≤1) and a multilayer structure above the AlxGa1-xN substrate; and a submount substrate on which the nitride semiconductor light-emitting element is mounted. The multilayer structure includes a first clad layer of a first conductivity type, a first light guide layer, a quantum-well active layer, a second light guide layer, and a second clad layer of a second conductivity type which are stacked sequentially from the AlxGa1-xN substrate. The multilayer structure and submount substrate are opposed to each other. The submount substrate comprises diamond. The nitride semiconductor light-emitting element has a concave warp on a surface closer to the AlxGa1-xN substrate. |
| US11322907B2 |
Light emitting element housing package, light emitting device, and light emitting module
A light emitting element housing package of the present disclosure includes a base part including a first surface including a first recessed part for mounting a light emitting element. Surface roughness Sa of at least such a region of a bottom surface of the first recessed part that is opposite to a light emitting element mounted on the first recessed part is smaller than surface roughness Sa of a region other than the first recessed part of the first surface. Further, a light emitting device of the present disclosure includes the light emitting element housing package and a light emitting element housed in the light emitting element housing package. Further, a light emitting module of the present disclosure includes the light emitting device and a module substrate on which the light emitting device is mounted. |
| US11322902B2 |
Arrangement for monitoring an optical element, laser source and euv radiation generation apparatus
An arrangement monitors an optical element. The arrangement includes: a light source configured to emit radiation onto a surface of the optical element; a detector configured to detect the radiation that has been at least partially reflected at the surface of the optical element; and a holder for the optical element, in which the light source and the detector are integrated. The holder has a cooling region through which a cooling liquid is configured to flow, the cooling region being in contact with the optical element. The holder has a reservoir, through which a beam path between the light source and the detector extends. The reservoir is configured to receive the cooling liquid leaking out at the optical element in case of a leakage. |
| US11322900B2 |
Polymer holder, electrode system and manufacturing and handling methods of polymer holder
A polymer holder for a biosignal processing device, wherein a wall of the polymer holder forms a pocket, and the wall follows an outer contour of the biosignal processing device. The polymer holder has a first aperture for inserting the biosignal processing device into the pocket and removing the biosignal processing device from the pocket. The polymer holder includes an electrically conductive contact structure, which is in a wired electric contact with electrodes that receive the at least one biosignal, at a rear section opposite to the first aperture, and the electrically conductive contact structure is at least partly attached inside the wall. The electrically conductive contact structure is electrically connected with a counterpart of the biosignal processing device in response to an insert of the biosignal processing device in the pocket. |
| US11322898B2 |
Methods and systems for a modular plug-in bus wiring system
A modular plug-in bus wiring system for electrical connections. The system includes an adapter module, the adapter module including at least a housing wherein the housing includes a front side containing at least an electrical connector, a back side, an upper end, a lower end, and at least a receptacle. The system includes at least a plug configured to insert in the at least a receptacle wherein the at least a plug is connected to at least a cable that includes at least an electrically conductive wire. The at least a plug includes a ventral surface, a dorsal surface, a first side and a second side. |
| US11322893B2 |
Electrical connector
An electrical connector includes an insulating body having a mating surface. An insertion slot is concavely provided on the mating surface. Two side walls are located at two sides of the insertion slot. A slot bottom surface is formed on a concave direction of the insertion slot. One of the side walls is provided with aground accommodating slot and a signal accommodating slot. A signal terminal and a ground terminal are provided on the one of the side walls. The signal terminal is accommodated in the signal accommodating slot. The ground terminal is accommodated in the ground accommodating slot. A side of the insulating plug member has a first portion corresponding to the signal accommodating slot and a second portion corresponding to the ground accommodating slot. The first portion is accommodated in the signal accommodating slot and is provided closer to the mating surface than the slot bottom surface. |
| US11322882B2 |
Submersible connector seal
A connector seal for use in a submersible connection apparatus may include a shell comprising an internal channel and a groove disposed on an external surface of shell. The connector seal may also include an annular seal member disposed in the groove of the shell. The annular seal member may be configured to hermetically piston seal the connector seal within the submersible connection apparatus. The connector seal may also include a first interconnect disposed within the internal channel at a first end of the shell, a second interconnect disposed within the internal channel at a second end of the shell, a conductive pin configured to make an electrical connection through the connector seal. The conductive pin may extend between and disposed within the first interconnect and the second interconnect. |
| US11322880B2 |
Packing mounting structure
A packing mounting structure includes a casing having a passage part on a wall part facing a power detection terminal; packing including a seal part and an portion to be held; and a cover installed on the casing in a state in which the portion to be held is held by a hole part, and closing the passage part by the packing. The portion to be held includes a shaft part and a first flange part. The hole part includes a narrow part; an insertion hole part through which the first flange part is capable of passing; and a holding hole part configured to hold the shaft part in a state in which a gap is formed between the holding hole part and the shaft part. |
| US11322878B2 |
Connector
A connector is provided with a housing made of resin and including a first opening open upward, and a terminal made of conductive metal and partially embedded in the housing. The terminal includes a base end portion projecting forward from an inner wall on a rear surface side in the first opening of the housing, a connecting portion provided to extend forward and to be connected to a mating device, and a coupling portion coupling a front end part of the base end portion and a rear end part of the connecting portion. The base end portion and the connecting portion are disposed on different axes when viewed in a third direction orthogonal to an upward direction and a forward direction. A length L1 of the base end portion is equal to or longer than a length L2 between the base end portion and the connecting portion. |
| US11322875B2 |
Electrical connector with floating contacts each with multiple impedances
A connector (10) according to the present disclosure includes an insulator to be fitted to a connection object (60), and contacts (50) attached to the insulator. Each of the contacts (50) includes a contact portion (59), a first elastic portion (54A), a first adjustment portion (54B1), and a second adjustment portion (54B2). The contact portion (59) electrically contacts the connection object (60) when the insulator and the connection object (60) are fitted together. The first elastic portion (54A) is elastically deformable and extends from a first base (51) supported by the insulator. The first adjustment portion (54B1) is formed continuously with the first elastic portion (54A) and has an electric conductivity higher than that of the first elastic portion (54A). The second adjustment portion (54B2) is formed continuously with the first adjustment portion (54B1) and has an electric conductivity lower than that of the first adjustment portion (54B1). |
| US11322874B2 |
Connector
A lock member has: a contact part that contacts one surface of an object to be connected; a locking part that has a shape allowing engagement with a part to be locked formed on the object to be connected; a connection part; and a pressure-receiving part that is pressed by a pressing member. The lock member includes at least one contact provided with a fixing function and used to enable electrification. The locking part projects in a direction that moves away from a board-mounting surface at a side near the board-mounting surface, at a position corresponding to the part to be locked of the object to be connected. The contact part is positioned on the side far from the board-mounting surface at the side facing the locking part, and at a position closer to an insertion side of the object to be connected than the locking part. |
| US11322871B2 |
Electrical connector assembly having floating heat sink in resilient manner
An electrical connector assembly includes a seat unit and a cover unit. The seat unit defines a receiving cavity for receiving the CPU. The cover unit is pivotably mounted upon one end of the seat unit. The cover unit includes a first cover and a second cover surrounding the first cover. The first cover includes a first frame equipped with therein a floating heat sink which is located above and aligned with the receiving cavity. The heat sink forms a pair of side extensions sandwiched between a pair of pressing blocks and the first frame in a vertical direction and essentially downwardly pressed by the pair of pressing blocks of the first cover in a resilient manner. Resilient mechanism is provided between the pressing block and the heat sink to result in a downward force constantly urge the heat sink downwardly against the first frame. |
| US11322869B2 |
Electrical connector having a ground bus
A contact assembly includes a contact array having contacts including signal contacts and ground contacts. The signal contacts include signal intermediate portions extending between signal mating beams and signal contact tails. The ground contacts include ground intermediate portions extending between ground mating beams and ground contact tails. The contact assembly includes front and rear contact holders. The contact assembly includes a ground bus bridge extending between each of the ground contacts to electrically common each of the ground contacts. The ground bus bridge is integral with the ground contacts and extends across the signal intermediate portions in close proximity to the signal intermediate portions for resonance control of signals transmitted along the signal contacts. |
| US11322863B2 |
Tool-less terminal block
A tool-less terminal block includes an insulated base, a turning part, a conductive terminal and a spring clamp. The insulated base has a cavity and a slot communicating to the cavity; the turning part is pivotally coupled to the insulated base; the conductive terminal is fixed to the bottom of the slot; the spring clamp is accommodated in the cavity and disposed at the top of the conductive terminal, and the spring clamp has a movable elastic arm pressing the conductive terminal to seal the slot, and the movable elastic arm has a link rod fixed to the turning part and operable together with the turning part. When the turning part is turned to a released position, the link rod is pulled by the turning part to drive the movable elastic arm away from the conductive terminal to open the slot, so as to provide a convenient use. |
| US11322862B2 |
Conductor connection terminal
A conductor connection terminal having at least one first spring-loaded clamping connection with a first operating lever for opening and closing a first clamping point formed between a first clamping leg and a first busbar section and at least one second spring-loaded clamping connection with a second operating lever for opening and closing a second first clamping point formed between a second clamping leg and a second busbar section and wherein the at least first spring-loaded clamping connection and the at least second spring-loaded clamping connection are arranged directly side by side in a direction of arrangement in a housing in the direction transverse to a conductor insertion direction. At least two operating levers arranged directly side by side in the direction of arrangement are designed differently. |
| US11322861B2 |
Conductor connection terminal, clamping spring of a conductor connection terminal and terminal block
A conductor connection terminal, having an insulating material housing, a busbar, a clamping spring and an operating lever which is pivotably received in the insulating material housing over a pivoting range and can be pivoted between an open position and a closed position, wherein the clamping spring has an operating arm which is deflected via a spring driver of the operating lever at least in the open position, characterized in that the operating lever is supported in the open position at a first and a second support point spaced from the first, and that the operating lever is pulled against the first and the second support point by a tensile force of the clamping spring acting on the spring driver from the operating arm. |
| US11322859B2 |
Electronic device and insulation-displacement terminal
An electronic device includes a connection unit having an electric wire and an insulation-displacement terminal. The electric wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation-displacement terminal includes two beams facing each other in a first direction to define a slot, and receives the electric wire in the slot to have an electrical connection. The insulation-displacement terminal includes an introduction part defining an opening of the slot, a scrape part for scraping the insulation coating from the electric wire, and a fix part fixing the electric wire in order along a second direction from the opening to an innermost of the slot. The thickness of the scrape part gradually increases toward the second direction so that as the electric wire advances through the scrape part along the second direction the width of the conductor to be scraped gradually increases. |
| US11322854B2 |
Antenna module comprising reflector, and electronic device comprising same
The present invention relates to: a communication technique for merging, with IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system; and a system therefor. The present invention provides an antenna module comprising: an antenna array for radiating beams through a top surface thereof; a dielectric disposed to be spaced apart from the top surface of the antenna array by a first preset length; a first reflector comprising a metallic material, and disposed to be spaced apart from the bottom surface of the dielectric by a second preset length; and a second reflector comprising a metallic material and disposed in the partial region of the bottom surface, of the dielectric, which faces the top surface of the antenna array. |
| US11322851B2 |
Shape memory deployable rigid antenna system
Described are several embodiments of parabolic reflective antenna systems where rigid parabolic dishes based on shape memory materials are deployed to full size and shape from compact pre-folded preforms by application of heat. Several shape memory feeds working with the dishes are presented. Feed preforms include corrugated, telescopic and flattened ribbon types which extend or unfurl into final shapes upon application of heat. Several dish and feed embodiments also contain supports for secondary reflectors and patch antennas. |
| US11322850B1 |
Deflective electromagnetic shielding
Systems according to the present disclosure provide one or more surfaces that function as power transferring surfaces for which at least a portion of the surface includes or is composed of “fractal cells” placed sufficiently closed close together to one another so that a surface (plasmonic) wave causes near replication of current present in one fractal cell in an adjacent fractal cell. A fractal of such a fractal cell can be of any suitable fractal shape and may have two or more iterations. The fractal cells may lie on a flat or curved sheet or layer and be composed in layers for wide bandwidth or multibandwidth transmission. |
| US11322845B2 |
Communication device and communication method
An antenna device according to the present disclosure includes a first antenna that is oriented in a first direction and transmits and receives a signal with a first polarization, a second antenna that is oriented in a second direction opposite to the first direction and transmits and receives a signal with the first polarization, a third antenna that is oriented in a third direction and transmits and receives a signal with a second polarization, a fourth antenna that is oriented in a fourth direction opposite to the third direction and transmits and receives a signal with the second polarization. The second antenna is provided with a feeding point placed in phase with a feeding point of the first antenna. The fourth antenna is provided with a feeding point placed in opposite phase to a feeding point of the third antenna. |
| US11322844B2 |
Impedance compensation system with microstrip and slotline coupling and controllable capacitance
Embodiments of a circuit, system, and method are disclosed. In an embodiment, a circuit includes a first microstrip transmission line, a second microstrip transmission line, and a slotline formation, wherein the slotline formation extends between the first microstrip transmission line and the second microstrip transmission line so that the slotline formation is configured to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line during operation of the circuit. In addition, the circuit includes at least one controllable capacitance circuit electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line, wherein a magnitude of capacitance of the at least one controllable capacitance circuit is controllable (e.g., in response to a capacitance control signal received at a control interface). |
| US11322842B2 |
Composite right/left-handed transmission line antenna
A composite right/left-handed transmission line antenna includes a first radiator, a second radiator, and a capacitive matching circuit, where the first radiator is connected to the second radiator, the connected first radiator and second radiator are of a ring shape, and the matching circuit is connected to a feed-in point of the first radiator or the second radiator. |
| US11322840B2 |
Wireless devices having antennas for covering multiple frequency bands
An electronic device may be provided with wireless circuitry and a housing with upper and lower ends. The lower end may include first and second open slot antennas that are directly fed by respective feeds and that radiate in a cellular ultra-high band. The lower end may also include first and second inverted-F antennas. The upper end may include third and fourth inverted-F antennas. The first inverted-F antenna may have a first feed that conveys currents below 2700 MHz and a second feed that conveys antenna currents in the cellular ultra-high band, a wireless local area network band, and/or ultra-wideband frequency bands. If desired, the upper end may include a third open slot antenna that is directly fed by a corresponding antenna feed and that radiates in the cellular ultra-high band and/or in the ultra-wideband frequency bands. |
| US11322839B2 |
Method and apparatus for implementing reflection type phase shifters (RTPS) in a communication system
A controllable reflection type phase shifter that includes an adjustable hybrid coupler and controllable adjustable reflection load circuit is described and used in some embodiments to implemented a communication system. In some embodiments the communication system supports beam forming through the use of a plurality of TX/RX signal processing chains (SPCs), each SPC including at least one reflection type phase shifter, e.g., a controllable reflection type phase shifter. The controllable reflection type phase shifters in different SPCs of the array are configured, e.g., differently, based on the particular beam pattern being used to transmit or receive signals at a given time. Control information, e.g., control values, are stored in memory with the control values corresponding to an antenna pattern to be used at a given time being retrieved from memory and to control the circuits, e.g., controllable reflection type phase shifters, in the system. |
| US11322837B2 |
Calibration of active phased array system using beamforming RFIC built-in-test equipment
A calibration method for a phased array system comprises sequentially injecting a tone into a first plurality of antenna elements of an antenna array, receiving the tone by a second plurality of antenna elements of the antenna array through parasitic coupling between the first plurality of antenna elements and the second plurality of antenna elements, measuring a plurality of phase errors between the first plurality of antenna elements and the second plurality of antenna elements, populating a lookup table with the plurality of phase errors, and calibrating a plurality of phase shifters associated with a plurality of channels in the phased array system using the plurality of phase errors in the lookup table. |
| US11322833B2 |
Antenna apparatus having fastener system
In one embodiment of the present disclosure, a housing assembly for an antenna apparatus includes a radome portion, a lower enclosure portion, and a fastener system configured for coupling the radome portion and the lower enclosure portion couplable to form an inner compartment for antenna components of an antenna assembly. |
| US11322832B2 |
Antenna structure and electronic device comprising antenna structure
An electronic device includes a housing that includes a first plate, a second plate facing a direction opposite the first plate, and a side member surrounding a space between the first plate and the second plate, an antenna structure that includes a plurality of dielectric layers perpendicular to the side member and parallel to the first plate, a first array of conductive plates aligned in a first direction perpendicular to the first plate at a first dielectric layer of the dielectric layers, a second array of conductive plates spaced from the first array and aligned in the first direction at the first dielectric layer, wherein the second array is farther from the first plate than the first array, at least one ground plane positioned on at least one of the dielectric layers and interposed between the first array and the second array, when viewed from above the side member, and a wireless communication circuit electrically connected to the first array and the second array and configured to transmit and/or receive a signal having a frequency in a range of 20 GHz to 100 GHz. |
| US11322826B2 |
Antenna structure
An antenna structure includes a ground element, a metal mechanism element, a feeding element, a first connection element, a second connection element, and a shorting element. The metal mechanism element has a slot. The slot has a first edge and a second edge which are opposite to each other. The feeding element extends across the slot. A signal source is coupled through the feeding element to a feeding point on the first edge. The first connection element is coupled between a first connection point on the first edge and a second connection point on the second edge. The second connection element is coupled between a third connection point on the first edge and a fourth connection point on the second edge. A first grounding point on the second edge is coupled through the shorting element to the ground element. |
| US11322825B2 |
Antenna-deco film stack structure and display device including the same
An antenna-deco film stack structure includes a deco film including a light-shielding portion and a transmissive portion, a dielectric layer facing the deco film, an antenna pattern disposed on an upper surface of the dielectric layer and disposed under the deco film, the antenna pattern being at least partially covered by the light-shielding portion, and a ground pattern on a lower surface of the dielectric layer to at least partially cover the antenna pattern. The deco film and the antenna pattern are combined to improve radiation reliability and optical property of the antenna pattern. A display device including the antenna-deco film stack structure is also provided. |
| US11322824B2 |
Antenna assembly and wireless terminal
Disclosed are an antenna assembly and a wireless terminal. The antenna assembly includes: a metal frame, wherein a first partition gap and a second partition gap are spacedly arranged on the metal frame, and the metal frame positioned between the first partition gap and the second partition gap forms a first radiator; and a radio frequency module, wherein the radio frequency module is coupled to the first radiator by a radio frequency signal feeder, wherein the metal frame between the first partition gap and the second partition gap is provided with a first ground point. |
| US11322822B2 |
Antenna hardware disposed on a substrate to provide enhanced wireless connectivity
An antenna overlay system includes antenna hardware, a communication link, and electronic circuitry disposed on a substrate. The communication link couples the electronic circuitry to the antenna hardware. During operation, the electronic circuitry in communication with the antenna hardware is operable to control transmission and reception of wireless signals in a wireless region. An adhesive layer disposed on a surface of the substrate couples the substrate to an object such as a window. In one arrangement, the window is a low-E glass windowpane that substantially attenuates wireless signals from being received by communication equipment in a building in which the windowpane is installed. The antenna overlay system provides enhanced RF signal reception and transmission. |
| US11322819B2 |
Antenna module
An antenna module according to an embodiment of the present disclosure includes a dielectric substrate, a first antenna element, a first radio-frequency element, and a first heat-dissipating component. The first antenna element is provided on the dielectric substrate. The first radio-frequency element supplies electric power to the first antenna element. The first heat-dissipating component directs heat from the first radio-frequency element to the outside. The dielectric substrate, the first radio-frequency element, and the first heat-dissipating component are stacked in this order in the Z-axis direction, which is the direction normal to the dielectric substrate. The first heat-dissipating component includes metal. The first heat-dissipating component has a first width at its first position that differs from a second width at its second position located away from the first position in the Z-axis direction. |
| US11322818B2 |
Antenna assembly comprising lens and film layer
The present invention relates to a communication technique which fuses a 5G communication system with IoT technology to support higher data transmission rates after a 4G system, and system thereof. In addition, the present invention provides an antenna assembly which comprises: an antenna array which includes at least one antenna; a film layer which is made of at least one insulating material, spaced apart from the antenna array by a predetermined first distance and joined to one side of a window; and an installation aid which has a surface fixed and attached to the window and the other surface on which an antenna array seating portion is formed. |
| US11322815B2 |
Prematched power resistance in lange couplers and other circuits
Disclosed are various embodiments for a pre-matched power resistance system including a pre-matching network for use with a passive electrical device, such as a Lange coupler or a Wilkinson power splitter, where the system provides a predetermined input impedance across a predetermined target bandwidth. The pre-matched power resistance system network further includes an on-chip thin film resistor disposed on a substrate comprising a plurality of coplanar sub-resistors electrically isolated from one another and a manifold portion comprising a plurality of manifold traces in a tiered arrangement terminating in an electrical connection to a respective one of the coplanar sub-resistors. |
| US11322811B2 |
Method for improving lifespan of lithium secondary battery
A method for enhancing a lifetime of a lithium secondary battery including manufacturing a battery by injecting an electrolyte liquid to an electrode assembly-embedded battery; and charging and discharging the manufactured battery; and additionally injecting an electrolyte liquid earlier than half a cycle point with respect to the number of charge and discharge cycles reaching discharge capacity of 80% compared to initial capacity is provided. |
| US11322808B2 |
Secondary battery module and method of producing the same
A secondary battery module showing excellent packing efficiency which makes it possible to connect a secondary battery and a charge/discharge device with a stably low resistance without any unnecessary deformation of the secondary battery or an electrode terminal is disclosed. The secondary battery module includes a plurality of stack units, each of the stack units including: at least one non-conductive plate member; at least one conductive member fixed to the plate member; a secondary battery stacked on the plate member; and at least one electrode terminal sticking out of a side face of the secondary battery, and held by the conductive member. |
| US11322807B2 |
Electrode plate and battery cell of wound lithium-ion battery and method for manufacturing same
Provided are an electrode plate and a battery cell of a wound lithium-ion battery and a method for manufacturing same. The electrode plate comprises an electrode plate body and at least two groups of tabs arranged on the electrode plate body, with each group of tabs including multiple tabs, wherein the multiple tabs have equal intervals therebetween, and the widths of the multiple tabs are successively increased by 2πΔt, with Δt being the sum of the thicknesses of a positive electrode plate, a negative electrode plate and two layers of a separation film of the battery cell of the lithium-ion battery. The present invention can avoid the problem in the prior art of burrs on an electrode plate due to secondary die-cutting, and can reduce the possibility of self-discharge of the battery. Since the body of each tab is completely coated with an electrode material, the energy density is high, thereby improving the safety of the battery. By means of slightly adjusting the widths of the tabs, continuous production is realized. |
| US11322804B2 |
Isolatable electrodes and associated articles and methods
Articles containing electrodes and current collectors arranged such that at least one electrode can be electronically isolated from other components of the article and/or an electrochemical device, and associated systems and methods, are provided. In some cases, the articles contain substrates for which a change in volume of the substrate causes at least one electrode to become electronically isolated from other components of the article and/or an electrochemical device. In certain cases, heating the substrate causes the change in volume of the substrate. |
| US11322803B2 |
Electrical busbar with alignment features
A busbar system is configured to carry current, such as, for example, in a battery system. The busbar system includes two or more busbars, that interface at respective surfaces and are aligned by one or more alignment features. The one or more alignment features may include a boss feature such as a pin or other protrusion, a recess such as a hole, slot, or other recess feature, or both a boss feature and a recess feature. Each busbar may include an alignment feature that engages with the alignment feature of the other busbar to cause, maintain, or otherwise effect alignment. Alignment of the busbars ensures relative position, prevents relative motion, or both. The busbars are engaged with each other by positioning the busbars such that their mating surfaces can engage, and then engaging alignment features of the busbars to provide alignment of the busbars relative to each other. |
| US11322799B2 |
Electrode including single-sided electrode with inorganic coating layer attached to slurry on collector and electrode assembly including the same
The present invention provides an electrode assembly in which a plurality of unit cells are disposed, wherein one of the unit cells comprises: a first double-sided electrode in which a slurry is on opposite surfaces of a first collector; a separator adjacent to the first double-sided electrode; a second double-sided electrode adjacent to the separator and in which a slurry is on opposite surfaces of a second collector; and a single-sided electrode adjacent to the second double-sided electrode and in which the slurry is only on one surface of a third collector, the one surface facing the second double-sided electrode, the single-sided electrode having a coating layer on the slurry thereof, the coating layer preventing contact between the slurry of the single-sided electrode and the slurry on one of the surfaces of the second collector that faces the single-sided electrode, the coating layer allowing ions to pass therethrough. |
| US11322796B2 |
Resin composition for manufacturing separator, preparation method therefor, and battery comprising same
A resin composition for fabricating a separator which is easy to control viscosity, a method of preparing the same, and a battery including the same, are disclosed. |
| US11322791B2 |
Multi-battery assembly and container comprising such an assembly
The invention concerns a multi-battery assembly, and a container comprising such an assembly, for use in particular in the field of high energy-density assemblies comprising a plurality of Ni—Cd, Ni-MH, lead-acid or Li-ion stationary batteries stored in a container or a library-like room. The multi-battery assembly comprises at least three rows (1 to 4) of batteries (12 to 23) connected in series and/or parallel, including two end rows (1, 4) and at least two intermediate rows (2, 3), each row being connected in series and/or parallel to at least one adjacent row, extending in a first direction (d1), and comprising at least one level (36 to 38) of a plurality of batteries connected in series and/or parallel, each of the levels extending in the first direction (d1). At least each intermediate row is a row that is movable relative to an adjacent row in a second direction (d2) substantially perpendicular to the first direction (d1), and is connected in series and/or parallel to said adjacent row by one of the batteries of one of the levels of same and by one of the batteries of one of the levels of said adjacent row by means of a connection element (60 to 63) that is configured to maintain the connection between the movable row and the adjacent row while allowing the movable row to move relative to the adjacent row in the second direction (d2), so as to allow at least one temporary corridor (50) to be created between the movable row and the adjacent row without disconnection. |
| US11322790B2 |
Prismatic secondary battery
A prismatic secondary battery including a battery container containing an electric storage element and having first and second wide surfaces and an opening; a lid having first and second through holes and a centerline extending along a length of the lid; a first and second flat plate-like current collector plate inserted into the first and second through holes made of metal materials. A first insertion position of the first current collector plate is spaced at a first distance from the centerline of the lid, the first distance extending in a direction parallel to a top surface of the lid from the centerline toward the first wide surface. A second insertion position of the second current collector plate is spaced at a second distance from the centerline, the second distance extending in a direction parallel to the top surface of the lid. |
| US11322787B2 |
Encapsulating in-situ energy storage device with cathode contact
An energy storage device has all components, e.g. anode, electrolyte, and cathode contained and sealed with a trench in a substrate. Various methods and structures are disclosed for sealing the components. In some embodiments, a sealer or sealing layer seals the components. One embodiment uses a tension clamp to contain the components with additional pressure. Another embodiment uses a cathode structure cup which is held in place in the substrate via sidewall trench features. Different external connections to the device are disclosed. The invention enables full three-dimensional components to be created and contained entirely within the substrate during assembly, curing, galvanic cycling and other manufacturing processes and provides improved sealing of the components during device operation. |
| US11322784B2 |
Cooling member and power storage module
A cooling member includes refrigerant, an absorbing member absorbing the refrigerant, an enclosing member including flexible sheet members, that are connected to each other and enclosing the refrigerant and the absorbing member in a sealed state, and a heat releasing section configured to receive heat from the enclosing member and release the heat to an outside. |
| US11322783B2 |
Systems and methods for providing safe battery removal from a flash memory based electronic device
A system for managing a battery removal from an electronic device is provided. The electronic device includes a battery interface including multiple battery coupling contacts that engage with battery contacts of the battery in an installed position of the battery. A battery removal detector is configured to detect, based on signals received via the battery interface, an ongoing battery removal process during which first battery contact(s) are disconnected from corresponding first interface contact(s) while second battery contact(s) remain connected with second battery coupling contact(s), and in response, to output a battery removal signal. The system also includes a controller that receives the battery removal signal and, still during the battery removal process, controls a memory device of the electronic device to prevent or complete a defined operation (e.g., writing of persistent storage keys) prior to completion of the battery removal process, to thereby prevent a corruption of the memory device. |
| US11322779B1 |
Electrolyte for Li secondary batteries
An electrolyte composition suitable for lithium ion secondary batteries comprises lithium bis(trifluoromethansolfonyl)imide (LiTFSI), 1,1,2,2-tetrafluoro-ethyl-2,2,3,3-tetrafluoropropyl ether (TTE), sulfolane (SL) and fluoroethylene carbonate (FEC) in an amount (x) of 0 |
| US11322776B2 |
Co-fired all-solid-state battery
A co-fired all-solid-state battery that includes a negative electrode, a solid electrolyte layer, and a positive electrode. The negative electrode contains a negative electrode active material and a garnet-type solid electrolyte. The negative electrode active material contains Li, V, and O. The negative electrode active material has a mole ratio (Li/V) of a Li content to a V content of 2.0 or more. The garnet-type solid electrolyte contains Li, La, Zr, and O. |
| US11322773B2 |
Lithium secondary battery
Provided is a lithium ion secondary battery that has excellent cycle characteristics and employs a silicon material for a negative electrode. This lithium ion secondary battery is characterized by having a negative electrode comprising a plate-like artificial graphite and a material comprising silicon as a constituent element, wherein at least some of particles of the plate-like artificial graphite are bent and have a crease on a plate face. |
| US11322771B2 |
Fuel cell tie rod isolator
A fuel cell includes a fuel cell stack. A pressure plate is arranged on one side of the fuel cell stack. The pressure plate includes a hole, and a tie rod assembly has a tie rod received in the hole. A nut with a conical surface is secured to the tie rod. An isolator is arranged in the hole between the tie rod assembly and the pressure plate. The isolator has a conical portion, and the conical surface engages the conical portion to provide a conical interface. The tie rod assembly applies a clamp load on the fuel cell stack via the conical interface. |
| US11322769B2 |
Flow battery
In a flow battery according to one aspect of the present disclosure, a first liquid does not include an undesired compound. The flow battery satisfies requirement (i), (ii), (iii) or (iv). (i) An anode active material 14 includes graphite, and the first liquid has an equilibrium potential of not more than 0.15 V vs. Li/Li+. (ii) An anode active material includes aluminum, and the first liquid has an equilibrium potential of not more than 0.18 V vs. Li/Li+. (iii) An anode active material includes tin, and the first liquid has an equilibrium potential of not more than 0.25 V vs. Li/Li+. (iv) An anode active material includes silicon, and the first liquid has an equilibrium potential of not more than 0.25 V vs. Li/Li+. |
| US11322760B2 |
Fuel cell system and method for controlling fuel cell system
A fuel cell system comprises: a gas-liquid separator separating exhaust gas of a fuel cell stack into a liquid component and a gas component and storing liquid water of the liquid component; a circulation pipe; a drain pipe discharging the liquid water; and a drain valve opening and closing the drain pipe. In an end scavenging process that is executed when operation of the fuel cell system is finished, the control unit opens the drain valve when a valve opening condition for the drain valve is satisfied. The valve opening condition is set such that an amount of the liquid water stored in the gas-liquid separator at the time the drain valve is opened in the end scavenging process is larger than an amount of the liquid water stored in the gas-liquid separator at the time the drain valve is opened during normal operation of the fuel cell system. |
| US11322758B2 |
Reduction of cell degradation in fuel cell systems
A method for reducing cell degradation in a fuel cell system includes adding oxygen-containing gas to a fuel in the anode chamber to prevent an increase in a cell voltage above a predetermined maximum value. |
| US11322751B2 |
Method for producing catalyst for air secondary battery, method for producing air secondary battery, catalyst for air secondary battery, and air secondary battery
A battery includes an electrode group including an air electrode and a negative electrode stacked with a separator therebetween, and an accommodating bag accommodating the electrode group along with an alkali electrolyte solution. The air electrode includes a catalyst for an air secondary battery. This catalyst for an air secondary battery is produced by a method for producing a catalyst for an air secondary battery, the method including a precursor preparation step of preparing a bismuth-ruthenium oxide precursor, a calcination step of calcining the bismuth-ruthenium oxide precursor obtained in this precursor preparation step to form a bismuth-ruthenium oxide, and a nitric acid treatment step of immersing the bismuth-ruthenium oxide obtained by this calcination step in a nitric acid aqueous solution. |
| US11322750B2 |
Surface modified platinum or platinum alloy catalyst for oxygen reduction reaction
An oxygen reduction reaction (ORR) catalyst, a membrane-electrode assembly and a polymer electrolyte membrane fuel cell containing the catalyst are provided. The ORR catalyst is a solid catalyst on a carbon support and the solid catalyst contains platinum metal or a platinum alloy metal having a surface complexed with a monodentate thiol ligand comprising an aromatic or heteroaromatic ring containing at least one of a bromide and an iodide substituent. |
| US11322748B2 |
High-energy cathode material particles with oxy-fluoride surfaces for aqueous processing
A method of forming a metal oxy-fluoride surface on lithium metal oxide cathode material particles is disclosed. Such a metal oxy-fluoride surface may help to prevent lithium metal oxide cathode active materials from reacting with water, thus enabling aqueous processing of cathodes made from such materials in the manufacture of lithium batteries. Such a method may also reduce lithium battery manufacturing costs and time by substituting water for currently-used organic solvents that are expensive and require special handling and disposal. Such a method may also reduce the cost of lithium metal oxide cathode active materials as the requirements for moisture-free manufacture, storage, and processing will be reduced or eliminated. |
| US11322747B2 |
Solid-state lithium batteries incorporating glass fibers
A solid-state battery cell includes a cathode comprising a cathode glass fiber scaffold impregnated with cathode active material, an anode comprising an anode glass fiber scaffold impregnated with lithium metal or a lithium metal alloy, and a first electrolyte layer comprising an electrolyte glass fiber scaffold impregnated with a first solid-state electrolyte, the electrolyte layer positioned between the cathode and the anode and the electrolyte glass fiber scaffold extending throughout the first electrolyte layer. |
| US11322745B2 |
Electrode, power storage device, electronic device, and manufacturing method of electrode
Provided is an electrode including a current collector and an active material layer. The active material layer includes an active material, a film including silicone, a conductive additive, and a binder. The active material is in the form of a particle. The film including silicone covers at least part of the active material. |
| US11322734B2 |
Negative electrode active material, negative electrode comprising the negative electrode active material, and secondary battery comprising the negative electrode
A negative electrode active material which includes a secondary particle including first primary particles, wherein the first primary particle includes a core including SiOx, wherein 0≤x<2, an intermediate layer which covers at least a portion of a surface of the core and includes silicon nitride, silicon oxynitride, or a mixture thereof, and a carbon coating layer which covers at least a portion of the intermediate layer and includes nitrogen-doped carbon, and a negative electrode and a lithium secondary battery which include the same. |
| US11322732B2 |
Electrode for lithium-ion cell, lithium-ion cell, and method for manufacturing electrode for lithium-ion cell
The present invention aims to provide an electrode for lithium ion batteries which exhibits excellent electrical conductivity even if its thickness is large. The electrode for lithium ion batteries of the present invention includes a first main surface to be located adjacent to a separator of a lithium ion battery and a second main surface to be located adjacent to a current collector of the lithium ion battery. The electrode has a thickness of 150 to 5000 μm. The electrode contains, between the first main surface and the second main surface, a conductive member (A) made of an electronically conductive material and a large number of active material particles (B). At least part of the conductive member (A) forms a conductive path that electrically connects the first main surface to the second main surface. The conductive path is in contact with the active material particles (B) around the conductive path. |
| US11322731B2 |
Lithium secondary battery
A lithium secondary battery which is made of an anode-free battery and includes lithium metal formed on a negative electrode current collector by charging. The lithium secondary battery includes the lithium metal formed on the negative electrode current collector in a state of being shielded from the atmosphere, so that the generation of a surface oxide layer (native layer) formed on the negative electrode according to the prior art does not occur fundamentally, thereby preventing the deterioration of the efficiency and life characteristics of the battery. |
| US11322729B1 |
Electrode manufacturing
A method for manufacturing zinc negative electrodes includes mixing a powder including zinc with polytetrafluoroethylene to form a homogenous blend, injecting a lubricant into the homogenous blend to form a dough, kneading the dough to form a fibrillated dough, and extruding the fibrillated dough through a die to form a ribbon. The method also includes calendering the ribbon to a target thickness to form a plaque, drying the plaque to form an active material sheet, laminating portions of the active material sheet to a current collector substrate to form an electrode blank, and sectioning the electrode blank into zinc negative electrodes. |
| US11322727B2 |
Optical device
An object of the present invention is to provide an optical device that can accomplish both the effect of preventing external light reflection and the improvement of utilization efficiency of light emitted from an organic electroluminescent element. The object is achieved by an optical device having an organic electroluminescent substrate, a circularly polarized light-separating layer that has a liquid crystal alignment pattern, in which the direction of an optical axis derived from a liquid crystal compound changes while continuously rotating in one direction in a plane, and separates light into right-handed circularly polarized light and left-handed circularly polarized light, a patterned retardation layer that converts circularly polarized light into linearly polarized light and has a plurality of regions among which the direction of a slow axis varies in the same plane, and a polarizer. |
| US11322726B2 |
Display panel, display screen, and display terminal with multiple light paths and compensation layer in groove
Provided is a display panel, comprising a substrate, and a plurality of film layers sequentially disposed on the substrate. The display panel has m paths orthogonal to a surface of the substrate, and including a first path and a second path comprising different film layers. When a thickness of the film layer is set to a preset thickness and/or when a refractive index is set to a preset refractive index, the display panel allows an externally incident light to enter therein in a direction orthogonal to the surface of the substrate, and pass through the first path and the second path. A difference value between optical lengths of the first path and the second path is an integer multiple of a wavelength of the externally incident light. |
| US11322723B2 |
Packaging structure including water-absorbing layer, display component and display device
A packaging structure, a display component and a display device are provided by the present disclosure. The packaging structure includes: a substrate; a light-emitting unit arranged on the substrate; a packaging layer, by which the light-emitting unit is packaged on the substrate; and a water-absorbing layer which is arranged in the packaging layer and completely wrapped by the packaging layer. |
| US11322722B2 |
Semiconductor device
The aim is to improve the bending resistance a display device. The display device in one embodiment includes a substrate including a first surface and a second surface and a curved part between the first surface and the second surface, a display element arranged on the first surface, a conducting layer connected with the display element and extending to the second surface from the first surface via the curved part, a plurality of protective layers having a lower ductility than the substrate and arranged in the substrate side and/or opposite side to the substrate side with respect to the conducting layer and along the curved part, wherein each of the plurality of protective layers spreading over the curved part, to a certain region of the first surface side from the curved part, and to a certain region of the second side from the curved part. |
| US11322721B2 |
Encapsulation structure of organic light emitting diode display panel and manufacturing method thereof
An encapsulation structure of an organic light emitting diode (OLED) display panel and a manufacturing method thereof are provided. By changing an edge design of a panel encapsulation structure and adding an encapsulation reduction layer to the encapsulation structure, the encapsulation reduction layer can be restored by subsequent processing after the encapsulation reduction layer is eroded by water and oxygen. This prevents an OLED display device from being oxidized, thereby extending a life of a device. |
| US11322719B2 |
Organic light emitting diode comprising inverted triangular groove structure at boundary line between display region and non-display region and method of fabricating thereof
An organic light emitting diode (OLED) device and the method of fabricating thereof. The OLED device includes a substrate, a display region, a non-display region, and an encapsulation structure covering the display region and the non-display region. The non-display region is composed of a flexible substrate that is bendable, the flexible substrate is curved toward a second surface of the substrate. The non-display region is provided with at least one groove structure at an edge adjacent to the display region, the groove structure extends along a first direction which is parallel to a boundary line between the display region and the non-display region. |
| US11322718B2 |
Flexible display panel and preparation method
A flexible display panel includes: a first organic layer; a blocking layer disposed on the first organic layer; and a first adhesion enhancing layer disposed between the first organic layer and the blocking layer. |
| US11322717B2 |
Optoelectronic component and protective layer
Various embodiments provide a process for producing an optoelectronic component. The process includes forming a first electrode and at least one contact section atop a carrier, forming an optically functional layer structure atop the first electrode, forming a second electrode atop the optically functional layer structure, the first electrode or the second electrode being electrically connected to the contact section, applying a protective layer to at least a subregion of the contact section, the protective layer being formed by a material which is repellent to a substance for production of an encapsulation layer, and forming the encapsulation layer atop the second electrode and atop the contact section, the subregion remaining free of the encapsulation layer because of the protective layer. |
| US11322716B2 |
Flexible light-emitting panel, method of manufacturing flexible light-emitting panel, and display device
The flexible light-emitting panel, the manufacturing method thereof and the display device, the flexible light-emitting panel comprises: a backplate; the adhesive layer comprises a first sub-adhesive layer disposed on the backplate and a plurality of protrusions from the first sub-adhesive layer away from the backplate a second sub-adhesive layer; the flexible layer is disposed on the first sub-adhesive layer, and the flexible layer comprises a plurality of spaced sub-flexible layers, the second sub-adhesive layer is located at spacings; and an array is sequentially stacked on each sub-flexible layer The substrate, the light-emitting component and the encapsulation layer; the cover plate is disposed on the encapsulation layer and the second sub-adhesive layer. |
| US11322714B2 |
Display device including OLED surrounded by nanotube extending through carrier, and manufacturing method thereof
Disclosed is a display device, a manufacturing method thereof and a display apparatus. The display device includes a carrier having a first surface and a second surface opposite to each other, and at least one nanotube in the carrier. Each nanotube includes a tube wall and a receiving cavity surrounded by the tube wall. The receiving cavity includes a first open end at the first surface and a second open end at the second surface. The display device further includes a first electrode at the first open end, a second electrode at the second open end and a light-emitting layer between the first electrode and the second electrode. |
| US11322712B2 |
OLED device structure with reduced voltage drop and manufacturing method thereof
An organic light-emitting diode (OLED) structure and a manufacturing method thereof are provided. The OLED structure includes a substrate, a metal layer, a passivation layer, an anode, and an OLED functional layer. By setting the OLED functional layer to form a PN junction with low impedance. The PN junction and a conductive layer with high impedance constitute a resistive divider, and the PN junction is turned on by adjusting a high-voltage direct current (DC) input source and a low-voltage DC input source. Because the resistance of the PN junction is very small, the potential of the cathode can be approximated to the potential of the low-voltage DC input source according to resistive voltage divider rule, and the low-voltage DC input source uses low-resistance metal, which can effectively avoid the problem of IR drop. |
| US11322708B2 |
Organic light-emitting diode having long lifespan property
The present disclosure relates to an organic light-emitting diode: comprising a first electrode; a second electrode facing the first electrode; and a hole transport layer and a light-emitting layer disposed in that order between the first and the second electrode, wherein the light-emitting layer includes a host and a hole assistant material represented by the following Chemical Formula A, the hole assistant material having a highest occupied molecular orbital (HOMO) energy level lower in absolute value than that of the host. |
| US11322707B2 |
Cadmium-free quantum dot LED with improved emission color
A light-emitting device is configured to emit light in improved accordance with the Rec. 2020 specification. The light emitting device includes a substrate; a first electrode disposed on the substrate between an outer surface of the light emitting device and the substrate; a second electrode disposed between the first electrode and the outer surface; a first emissive layer in electrical contact with the first electrode and the second electrode, wherein the first emissive layer includes quantum dots that emit light when electrically excited, and wherein the first emissive layer is associated with a first peak wavelength, λ1; and a second emissive layer disposed between the first emissive layer and a viewing side of the light emitting device, wherein the second emissive layer is a photoluminescent layer that includes quantum dots that emit light when optically excited, and the second emissive layer is associated with a second peak wavelength, λ2, different from the first peak wavelength. The second emissive layer operates to convert a portion of light emitted by the first emissive layer from the first peak wavelength to the second peak wavelength, such that the resultant overall emission is in accordance with the Rec. 2020 specification. |
| US11322703B2 |
Photoelectric conversion element and solid-state imaging apparatus
A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; and an organic photoelectric conversion layer provided between the first electrode and the second electrode and formed using a plurality of materials having average particle diameters different from each other, the plurality of materials including at least fullerene or a derivative thereof. |
| US11322702B1 |
Electrical devices having radiofrequency field effect transistors and the manufacture thereof
Electrical device including a substrate having a surface and a radiofrequency field effect transistor (RF-FET) on the substrate surface. RF-FET includes a CNT layer on the substrate surface, the CNT layer including electrically conductive aligned carbon nanotubes, and pin-down anchor layers on the CNT layer. A first portion of the CNT layer, located in-between the pin-down anchor layers, is not covered by the pin-down anchor layers and is a channel region of the radiofrequency field effect transistor and second portions of the CNT layer are covered by the pin-down anchor layers. For cross-sections in a direction perpendicular to a common alignment direction of the aligned CNTs in the first portion of the CNT layer: the aligned CNTs have an average linear density in a range from 20 to 120 nanotubes per micron along the cross-section, and at least 40 percent of the aligned CNTs are discrete from any CNTs of the CNT layer. |
| US11322701B2 |
High dielectric constant composite material and application thereof
A high dielectric constant composite material and method for preparing organic thin film transistor using the material as dielectric. The method includes: using sol-gel method, hydrolyzing terminal group-containing silane coupling agent to form functional terminal group-containing silica sol, cross-linked with organic polymer to form composite sol as material of dielectric of organic thin film transistor; forming film by solution method such as spin coating, dip coating, inkjet printing, 3D printing, etc., forming dielectric after curing; preparing semiconductor and electrode respectively to prepare organic thin film transistor device, which, based on composite dielectric material, has mobility of 5 cm2/V·s, exceeding that of using SiO2, having low threshold voltage and no hysteresis effect. Compared with traditional processes like SiO2 thermal oxidation, above method has advantages of simple process, low cost, suitable for large-area preparation, with great market application value. |
| US11322698B2 |
Transparent organic light emitting display apparatus and method of manufacturing the same
A transparent organic light emitting display apparatus and a method of manufacturing the same are discussed. The transparent organic light emitting display apparatus can comprise an emission area, a transmission area disposed adjacent to the emission area and configured to pass external light therethrough, and an undercut area formed in the transmission area, wherein the undercut area is filled by an encapsulation layer. |
| US11322695B2 |
Ink composition for organic light-emitting device, organic light-emitting device including film formed by using the ink composition, and method of manufacturing the organic light-emitting device
An ink composition for an organic light-emitting device, the ink composition including a luminescent host material and a solvent, wherein the luminescent host material includes at least one compound represented by Formula (1) and Formula (3), and wherein the solvent includes at least one selected from an aromatic ether, an aromatic ester, and an aromatic ketone: wherein, in Formulas (1) and (3), groups and variables are the same as described in the specification. |
| US11322693B2 |
Organic light-emitting element, and light-emitting material and fluorescent body used in same
Disclosed is an organic light-emitting device using a compound capable of emitting delayed fluorescence and capable of undergoing intramolecular hydron transfer. The compound includes, for example, a compound represented by the general formula. X1 to X3 each represent O or S; R1 to R6 each represent nH or a substituent; n, n1 to n3 each represent an integer of 1 to 3. |
| US11322685B2 |
Controlling positive feedback in filamentary RRAM structures
A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers. |
| US11322673B2 |
Thermoelectric module and temperature modulating apparatus including the same
A thermoelectric module includes a flexible film with an insulation characteristic, the film having a shape that is longer in a lengthwise direction than in a width direction, a plurality of n-type thermoelectric elements and a plurality of p-type thermoelectric elements alternately arranged on one surface of the film in the lengthwise direction of the film, and first electrodes and second electrodes that alternately connect the plurality of n-type thermoelectric elements and the plurality of p-type thermoelectric elements at one side and an opposite side with respect to the width direction of the film to electrically connect the plurality of n-type thermoelectric elements and the plurality of p-type thermoelectric elements in series. One lateral end and an opposite lateral end of the film are bent with the plurality of n-type thermoelectric elements, the plurality of p-type thermoelectric elements, the first electrodes, and the second electrodes attached to the film. |
| US11322668B2 |
Semiconductor device
A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer. |
| US11322667B2 |
Light-emitting device package
A semiconductor device package includes a light emitting device disposed on a body, and at least one resin disposed between the body and the light emitting device. The body may include first and second opening parts passing through the body from the upper surface of the body, and at least one recess concavely provided from the upper surface of the body towards the lower surface of the body. The light emitting device may include a first bonding part disposed on the first opening part, and a second bonding part disposed on the second opening part. The at least one recess may be disposed between the first and second opening parts, and along the circumferences of the first and second opening parts. The at least one resin may be provided to the at least one recess. The at least one resin may include a reflective material. |
| US11322666B2 |
Optoelectronic device
An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill. |
| US11322664B2 |
Method of manufacturing light emitting device
A method of manufacturing a light emitting device includes: providing a light emitting element including a light extraction surface, an electrode-formed surface on a side opposite to the light extraction surface, lateral surfaces positioned between the light extraction surface and the electrode-formed surface, and a pair of electrodes on the electrode-formed surface; providing a covering member including a lens portion and a first recess on a side different from the lens portion; disposing the light emitting element on a bottom surface of the first recess, with the light extraction surface and the bottom surface of the first recess facing each other; and forming a reflective member in the first recess to cover the lateral surfaces of the light emitting element while at least a part of the pair of electrodes is exposed from the reflective member. |
| US11322661B2 |
Spin-sensitive ultraviolet light-based device and method
A spin-sensitive ultraviolet light-based device includes a p-type GaN layer; an n-type Gd doped ZnO nanostructure grown on the GaN layer; a first electrode formed on the GaN layer; and a second electrode formed on the Gd doped ZnO nanostructure. Electrons supplied through the first and second electrodes are spin-polarized by the Gd doped ZnO nanostructure. Polarized ultraviolet light emitted or received by the Gd doped ZnO nanostructure is correlated with the spin-polarized electrons. |
| US11322659B2 |
Method for manufacturing wavelength conversion member, wavelength conversion member, and light-emitting device
Provided are a method for manufacturing wavelength conversion members that enables manufacturing of wavelength conversion members having a high light extraction efficiency and suppression of material loss, a wavelength conversion member obtained by the method, and a light-emitting device. A method for manufacturing a plurality of wavelength conversion members by breaking into parts a base material 10 for the wavelength conversion members includes the steps of: preparing the base material 10 having a first principal surface 11 and a second principal surface 12 opposed to each other; forming a breaking groove 13 in the first principal surface 11; bonding a support 20 to the second principal surface 12 of the base material 10 having the breaking groove 13 formed in the first principal surface 11; pressing through the support 20 a region of the base material 10 where the breaking groove 13 is formed, thus breaking the base material 10 into the plurality of wavelength conversion members along the breaking groove 13; expanding the support 20 to form a gap between the plurality of wavelength conversion members lying on the support 20; and removing the plurality of wavelength conversion members from the support 20 after forming the gap. |
| US11322658B2 |
Light-emitting device and method of manufacturing the same
A light-emitting device includes a base member including a first lead, a second lead, and a securing member securing the first lead and the second lead, a light-emitting element mounted on an upper surface of the base member, a frame disposed on the upper surface of the base member to surround the light-emitting element, a first member covering at least a portion of an upper surface of the securing member exposed at an outer peripheral side of the frame in a top view, the first member being in contact with an outer lateral surface of the frame and containing a reflective material, and a second member covering the light-emitting element, the frame, and the first member. The first member has an inclined region in a cross-sectional view. A maximum height of the inclined region is less than a height of an upper end of the frame. |
| US11322657B2 |
Flip-chip light emitting device and production method thereof
A flip-chip light emitting device includes a transparent substrate, an epitaxial light-emitting structure, a transparent bonding layer interposed between the transparent substrate and the light-emitting structure, and a protective insulating layer disposed over the light-emitting structure and the bonding layer. The transparent bonding layer has a smaller-thickness section that has a first contact surface for the protective insulating layer to be disposed thereover, and a larger-thickness section that has a second contact surface meshing with and bonded to a roughened bottom surface of the light-emitting structure. The first contact surface is smaller in roughness than the second contact surface. A method for producing the device is also disclosed. |
| US11322653B2 |
Light-emitting device with optical power readout
A light emitting device with on-chip optical power readout includes a light emitting mesa and a light detecting mesa formed adjacent to each other on the same substrate of a chip, and a portion of the light emitted from the light emitting mesa is transmitted to the light detecting mesa at least through the substrate. The light emitting mesa and the light detecting mesa have exactly the same epitaxial structure and can be electrically isolated from each other by an insulation layer, or an airgap formed therebetween, or by ion implantation. The light emitting mesa and the light detecting mesa can also share an n-type structure and a common n-electrode while having their own p-electrode, respectively. |
| US11322652B2 |
Methods for producing composite GaN nanocolumns and light emitting structures made from the methods
A method for growing on a substrate strongly aligned uniform cross-section semiconductor composite nanocolumns is disclosed. The method includes: (a) forming faceted pyramidal pits on the substrate surface; (b) initiating nucleation on the facets of the pits; and; (c) promoting the growth of nuclei toward the center of the pits where they coalesce with twinning and grow afterwards together as composite nanocolumns. Multi-quantum-well, core-shell nanocolumn heterostructures can be grown on the sidewalls of the nanocolumns. Furthermore, a continuous semiconductor epitaxial layer can be formed through the overgrowth of the nanocolumns to facilitate fabrication of high-quality planar device structures or for light emitting structures. |
| US11322651B2 |
Light-emitting element and method for manufacturing same
A light-emitting element includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a first electrode, and a second electrode. The first semiconductor layer includes gallium and nitrogen and is of an n-type. The second semiconductor layer includes gallium and nitrogen and is of a p-type. The light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer. The first semiconductor layer includes a first partial region and a first side surface region. The first partial region includes a first surface contacting the first electrode. The first side surface region includes a first side surface crossing a plane perpendicular to a first direction. The first direction is from the second semiconductor layer toward the first semiconductor layer. |
| US11322650B2 |
Strained AlGaInP layers for efficient electron and hole blocking in light emitting devices
A light-emitting device is disclosed. The light emitting device includes an electron blocking layer, a hole blocking layer, wherein at least a portion of the hole blocking layer is arranged to have a compressive strain, and an active layer disposed between the hole blocking layer and the electron blocking layer. |
| US11322648B2 |
Photon source and a method of fabricating a photon source
A method for using a photon source, which includes a semiconductor structure having a first light emitting diode region, a second region including a quantum dot, a first voltage source, and a second voltage source, is provided. The method includes steps of applying an electric field across said first light emitting diode region to cause light emission by spontaneous emission, wherein the light emitted from said first light emitting diode region is absorbed in said second region and produces carriers to populate said quantum dot; and applying a tuneable electric field across said second region to control the emission energy of said quantum dot, wherein the light emitted from the second region exits said photon source. |
| US11322644B2 |
Method for transferring light emitting elements, and method for making display panel
A method for transferring light emitting elements during manufacture of a display panel includes providing light emitting elements; providing a first electromagnetic plate defining adsorption positions; providing a receiving substrate defining receiving areas; energizing the first electromagnetic plate to magnetically adsorb one of the light emitting elements at each adsorption position; facing the first electromagnetic plate to the receiving substrate; and transferring the light emitting elements to one corresponding receiving area of the receiving substrate. |
| US11322643B2 |
Optoelectronic device
An optoelectronic device comprising a semiconductor structure includes a p-type active region, an n-type active region, and an i-type active region. The semiconductor structure is comprised solely of one or more superlattices, where each superlattice is comprised of a plurality of unit cells. Each unit cell can comprise a layer of GaN and a layer of AlN. In some cases, a combined thickness of the layers comprising the unit cells in the i-type active region is thicker than a combined thickness of the unit cells in the n-type active region, and is thicker than a combined thickness of the unit cells in the p-type active region. The layers in the unit cells in each of the three regions can all have thicknesses that are less than or equal to a critical layer thickness required to maintain elastic strain. |
| US11322638B2 |
Waveguide-integrated avalanche photodiode
Various embodiments of a monolithic avalanche photodiode (APD) are described, which may be fabricated on a silicon-on-insulator substrate. The monolithic APD includes an optical waveguide that guides an incident light to an active region of the APD. An optical coupler is integrally formed with the optical waveguide to capture the incident light. The monolithic APD also includes an optical reflector to reflect a portion of the incident light that is not readily captured by the optical coupler back to the optical coupler for further capturing. The active region includes an absorption layer for converting the incident light into a photocurrent, an epitaxial structure for amplifying the photocurrent by avalanche multiplication, as well as a pair of electrical conductors for conducting the amplified photocurrent. |
| US11322637B2 |
Sam photodiode with multiplication of a single type of carrier in a periodic multilayer region
An avalanche photodiode including an absorption region, a collection region and a multiplication region between the absorption region and the collection region that performs a carrier multiplication by impact ionisation of a single type of carrier. The multiplication region includes a plurality of multilayer structures where each multilayer structure includes, from the absorption region to the collection region, an acceleration layer having a first energy band gap then a multiplication layer having a second energy band gap. The first energy band gap is greater than the second energy band gap. |
| US11322635B2 |
Light detection device
A photodetecting device includes a semiconductor substrate including a one-dimensionally distributed plurality of pixels. The photodetecting device includes, for each pixel, a plurality of avalanche photodiodes arranged to operate in Geiger mode, a plurality of quenching resistors electrically connected in series with the respective avalanche photodiodes, and a signal processing unit arranged to process output signals from the plurality of avalanche photodiodes. Light receiving regions of the plurality of avalanche photodiodes are two-dimensionally distributed for each pixel. Each signal processing unit includes a gate grounded circuit and a current mirror circuit electrically connected to the gate grounded circuit. The gate grounded circuit is electrically connected to the plurality of avalanche photodiodes of the corresponding pixel via the plurality of quenching resistors. The current minor circuit is arranged to output a signal corresponding to output signals from the plurality of avalanche photodiodes. |
| US11322634B2 |
Copper-based chalcogenide photovoltaic device and a method of forming the same
A method for forming a photovoltaic device comprising the steps of: providing a first conductive material on a substrate; depositing a continuous layer of a dielectric material less than 10 nm thick on the first conductive material; annealing the first conductive material and the layer of dielectric material; forming a chalcogenide light-absorbing material on the layer of dielectric material; and depositing a second material on the light-absorbing material such that the second material is electrically coupled to the light-absorbing material; wherein the first conductive material and the dielectric material are selected such that, during the step of annealing, a portion of the first conductive material undergoes a chemical reaction to form: a layer of a metal chalcogenide material at the interface between first conductive material and the dielectric material; and a plurality of openings in the layer of dielectric material; the openings being such to allow electrical coupling between the light-absorbing material and the layer of a metal chalcogenide material. Additionally contemplated is a photovoltaic device formed by this method. |
| US11322633B2 |
Optomechanical system for absorbing light or emitting light and corresponding method
An optomechanical system for absorbing light or emitting light, comprising as static frame element, an optical arrangement, a light absorbing/emitting substrate and a shifting mechanism. The shifting mechanism moves at least one layer of the optical arrangement relative to the light absorbing/emitting substrate or vice versa, wherein the movement is through one or more translation element relative to the static frame element in such a way that the transmitted light can be optimally absorbed by the light absorbing/emitting substrate, or that the incident light emitted by the light absorbing/emitting substrate can be optimally transmitted by the optical arrangement. Furthermore, the present invention also relates to a corresponding method for absorbing light or emitting light with the aforementioned optomechanical system. |
| US11322631B2 |
Solar cell panel
A solar cell panel can include a solar cell; a sealing member for sealing the solar cell; a first cover member disposed on the sealing member at one side of the solar cell; and a second cover member disposed on the sealing member at another side of the solar cell, in which the first cover member includes a base member and a colored portion having a light transmittance lower than a light transmittance of the base member, the first cover member constituting a colored area, and the colored portion includes at least two layers each formed of an oxide ceramic composition and having different colors or different light transmittances. |
| US11322630B2 |
Monolithic infrared transceiver
An optoelectronic device includes a semiconductor substrate and a first stack of epitaxial layers, which are disposed over the semiconductor substrate and are configured to function as a photodetector, which emits a photocurrent in response to infrared radiation in a range of wavelengths greater than 940 nm. A second stack of epitaxial layers is disposed over the first stack and configured to function as an optical transmitter with an emission wavelength in the range of wavelengths greater than 940 nm. |
| US11322628B2 |
Optical member driving mechanism
An optical member driving mechanism is provided, including a movable portion, a fixed portion, and a driving assembly. The movable portion is connected to an optical member. The movable portion is movable relative to the fixed portion. The driving assembly is configured to drive the movable portion to move relative to the fixed portion. |
| US11322627B2 |
Solar cell, multi-junction solar cell, solar cell module, and solar power generation system
According to one embodiment, a solar cell includes a first electrode, a second electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode. When a transmittance of the solar cell is measured in a wavelength range of 700 to 1000 nm, an average of the transmittance of the solar cell is 60% or more. |
| US11322624B2 |
Detection apparatus, fabrication method thereof, array substrate, and display apparatus
The present disclosure is related to a detection apparatus. The detection apparatus may include a gate insulating layer. The gate insulating layer may include at least a first layer and a second layer opposite the first layer. A plurality of protruding structures may be provided on a surface of the first layer facing the second layer and/or a surface of the second layer facing the first layer. The first layer and the second layer of the gate insulating layer may be connected through the protruding structures. |
| US11322620B2 |
Metal-assisted single crystal transistors
Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed. |
| US11322619B2 |
Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer. |
| US11322616B2 |
Semiconductor device
A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer. |
| US11322615B2 |
SOI wafers and devices with buried stressor
A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer. |
| US11322614B2 |
Semiconductor device
A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction. |
| US11322612B2 |
Semiconductor device with region of varying thickness
According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region. |
| US11322611B2 |
Methods for LDMOS and other MOS transistors with hybrid contact
A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region. |
| US11322607B2 |
Semiconductor device
A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region. |
| US11322606B2 |
Heterojunction semiconductor device having high blocking capability
A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer. |
| US11322601B2 |
Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. |
| US11322600B2 |
High electron mobility transistor
A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve. |
| US11322598B2 |
Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region. |
| US11322597B2 |
Gate material-based capacitor and resistor structures and methods of forming the same
At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers. |
| US11322592B2 |
Field effect transistor with channel layer with atomic layer, and semiconductor device including the same
A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material. |
| US11322590B2 |
Semiconductor device having asymmetrical source/drain
A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins. |
| US11322584B2 |
Semiconductor device and manufacturing method for same
A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface. |
| US11322583B2 |
Semiconductor device including barrier layer between active region and semiconductor layer and method of forming the same
A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region. |
| US11322581B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes first, second, and third electrodes, first and fourth semiconductor regions of a first conductivity type, and second and third semiconductor regions of a second conductivity type. The third semiconductor region is provided around the second semiconductor region along a first plane crossing a first direction from the first electrode toward the first semiconductor region and is separated from the second semiconductor region. The fourth semiconductor region is provided around the third semiconductor region along the first plane, and has a greater impurity concentration of the first conductivity type than the first semiconductor region. The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region. The third electrode is provided on the third and fourth semiconductor regions, is electrically connected to the third and fourth semiconductor regions, and is separated from the second electrode. |
| US11322579B2 |
Metal-insulator-metal (MIM) capacitor and semiconductor device
A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction. |
| US11322569B2 |
Array substrate with first gate, second gate, binding region with hole, and manufacturing method of same
The present application provides an array substrate and a manufacturing method of the same, the array substrate includes a display region, the display region includes a thin film transistor structure layer including a gate electrode layer and a source drain electrode layer, wherein the gate electrode layer and the source drain electrode layer are made of an alloy material including one or a group selected from Al, Ge, Nd, Ta, Zr, Ni, or La. |
| US11322568B2 |
Display panel and display device having a micro-cavity structure with transflective layers
Provided are a display panel and a display device having a micro-cavity structure with transflective layers. The display panel includes a first display region, a second display region, a base substrate, a thin film transistor array layer and a pixel definition layer. A pixel density of the first display region is greater than a pixel density of the second display region. The thin film transistor array layer is disposed on a side of the base substrate. The pixel definition layer is disposed on a side of the thin film transistor array layer facing away from the base substrate and includes multiple openings. The second display region includes multiple light emitting regions and multiple light transparent regions. A part of the openings of the pixel definition layer form the light emitting regions. At least one micro-cavity structure is arranged in each of the multiple light transparent regions. |
| US11322567B2 |
Display panel, manufacture method thereof and display apparatus
A display panel, a manufacture method thereof and a display apparatus are provided. The display panel includes a display area, which includes a plurality of pixel units, wherein the pixel units include electroluminescent display devices and pixel drive circuits for driving the electroluminescent display devices to emit light; the electroluminescent display devices include light-emitting devices and virtual light-emitting devices; the light-emitting devices are electrically connected with the pixel drive circuits, while the virtual light-emitting devices are not connected with the corresponding pixel drive circuits; the display area includes a first display area and a second display area; and in the first display area and the second display area, the distribution density of the electroluminescent display devices is the same, and the density of the pixel drive circuits in the second display area is less than that of the pixel drive circuits in the first display area. |
| US11322566B2 |
Display substrate and display device
The present disclosure provides a display substrate, including: a display area having a contour, at least a portion of the contour having a curved shape, the display area being divided into a plurality of sub-display areas, at least one of the sub-display areas close to an edge of the display area having a contour conformal to the contour of the display area. The at least one sub-display area includes a plurality of sub-pixels arranged therein along an extending direction of the contour of the sub-display area. |
| US11322564B2 |
Display device
A display device capable of reducing a non-display area includes a substrate including at least one hole area disposed within an emission area, and at least one blocking hole passing through inorganic insulating films disposed beneath a light emitting element while including upper and lower insulating films made of different materials. Side surfaces of the upper inorganic insulating film exposed through the blocking hole protrude beyond side surfaces of the lower inorganic insulating film exposed through the blocking hole, respectively. Accordingly, it is possible to minimize a bezel area, which is a non-display area, and to disconnect a light emitting stack by the blocking hole. |
| US11322563B2 |
Electroluminescent device with improved luminous efficiency and viewing angle and method of manufacturing the same
Described is an electroluminescent device including an array substrate having a thin-film transistor formed thereon, an organic insulating layer formed on the array substrate having the thin-film transistor formed thereon, barriers disposed on the organic insulating layer, an anode formed on the organic insulating layer between the barriers to thus be electrically connected to the thin-film transistor and configured to cover at least a portion of the barriers, a light-emitting layer formed on the anode, and a cathode formed on the light-emitting layer, thus exhibiting superior emission efficiency and a wide viewing angle. A method of making or manufacturing the electroluminescent device is also described. |
| US11322556B2 |
Method of integrating functional tuning materials with micro devices and structures thereof
The disclosure is related to creating different functional micro devices by integrating functional tuning materials and creating an encapsulation capsule to protect these materials. Various embodiments of the present disclosure also related to improve light extraction efficiencies of micro devices by mounting micro devices at a proximity of a corner of a pixel active area and arranging QD films with optical layers in a micro device structure. |
| US11322554B2 |
Display apparatus
A display apparatus includes a lower substrate, first to third light-emitting devices arranged on the lower substrate, where the first to third light-emitting devices each includes a color emission layer, an upper substrate arranged above the lower substrate with the first to third light-emitting devices therebetween, a first insulating layer arranged on a lower surface of the upper substrate in a direction to the lower substrate, the first insulating layer defining a (1-1)st opening corresponding to the first light-emitting device, a (1-2)nd opening corresponding to the second light-emitting device, and a (1-1)st groove connecting the (1-1)st opening to the (1-2)nd opening, a first color quantum dot layer arranged in the (1-1)st opening, and a second color quantum dot layer arranged in the (1-2)nd opening. |
| US11322553B2 |
Display apparatus including color-conversion layer and filter layer stacked in different insulating layers
A display apparatus includes a first pixel, a second pixel, and a third pixel which emit light of different colors from one another, a first insulating layer on a first display element of the first pixel, and a second insulating layer on the first insulating layer. The first insulating layer defines a first opening portion corresponding to the first display element, the second insulating layer defines a first opening corresponding to the first opening portion, and the first opening portion has a first extension portion which extends in a first direction and at least partially exposes the second insulating layer. |
| US11322551B2 |
Display panel and display device
The present disclosure discloses a display panel and a display device. The display device includes a first display area and a second display area, where the first display area includes a plurality of first sub-pixel units, and each of the first sub-pixel units includes a first light emitting device and a driving circuit for driving the first light emitting device to emit light; where the second display area includes a plurality of second sub-pixel units and a plurality of first voltage signal lines, each of the second sub-pixel units includes a second light emitting device, and the first voltage signal lines are directly and electrically connected to anodes of the second light emitting devices. |
| US11322549B2 |
Display device
A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines. |
| US11322546B2 |
Current delivery and spike mitigation in a memory cell array
A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another. |
| US11322543B2 |
Method for MRAM top electrode connection
Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer. |
| US11322542B2 |
Light-emitting diode (LED) assembly and method of manufacturing an LED cell of the same
A light-emitting diode (LED) assembly comprises a plurality of LED cells and a driving circuit. Each of the LED cells includes an LED and a transistor. The LED includes first and second LED layers and an LED electrode. The first LED layer includes a III-V compound semiconductor. The second LED layer is over the first LED layer. The LED electrode is over the second LED layer. The first LED layer is free of an LED electrode. The transistor includes a drain region connected to the first LED layer. The driving circuit is configured to drive the LED cells. |
| US11322541B2 |
Light-emitting device
A light-emitting device includes: a circuit board; and a light-emitting element mounted on the circuit board, the light-emitting element including: a substrate provided on the circuit board, the substrate having a first side along a first direction and a second side along the first direction, wherein a second direction from the first side toward the second side being is orthogonal to the first direction; n semiconductor stacked bodies (n being a natural number of 2 or more) provided on the substrate, the n semiconductor stacked bodies comprising a first semiconductor stacked body and a second semiconductor stacked body that are electrically insulated from each other; and n+1 interconnect layers. |
| US11322539B2 |
Semiconductor device and manufacturing method, and electronic appliance
There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps. |
| US11322537B2 |
Imaging detection chip with an optical antenna comprising a plurality of antenna cells each comprising one or more nanocones coupled to photosensitive array
An imaging detection chip, including an optical antenna and a photosensitive array in parallel to the optical antenna. The optical antenna is an array structure including a plurality of antenna cells spaced apart and electrically connected to each other. The photosensitive array is an array structure including a plurality of photosensitive cells spaced apart from each other. The plurality of antenna cells and the plurality of photosensitive cells are equal in number. The plurality of antenna cells of the optical antenna is aligned, perpendicularly to a parallel direction of the photosensitive array and the optical antenna, with the plurality of photosensitive cells at corresponding positions of the photosensitive array, respectively. The plurality of antenna cells each includes one or more nanocones each including a top surface; top surfaces of the plurality of antenna cells are electrically connected to each other. |
| US11322532B2 |
Backside illuminated image sensor
The backside illuminated image sensor comprises a substrate of semiconductor material, detector elements arranged at a main surface, a dielectric layer on or above the main surface, a first capacitor layer and a second capacitor layer above the main surface, the capacitor layers forming a capacitor (C1, C2). A peripheral circuit is integrated in the substrate apart from the detector elements, the peripheral circuit being configured for one or more operations of the group consisting of voltage regulation, charge pump operation and stabilization of clock generation, and the capacitor layers are electrically connected with contact regions of the peripheral circuit. |
| US11322529B2 |
Display panel, electronic device, and method of operating same
The present invention relates to a display panel, an electronic device, and an operation method of the electronic device. The display panel is divided into a display region and a plurality of image capturing regions. Each of the image capturing regions includes: a camera module; a pixel module disposed on the camera module; and the pixel module includes a plurality of sub-pixel units, each of the sub-pixel units spaced apart on the camera module. By adding a plurality of cameras hidden under the display panel, the invention can not only improve accuracy of eye-tracking technology, but also prevent the problem of reduced appearance aesthetics caused by the plurality of cameras. |
| US11322527B2 |
Pixel unit, manufacturing method thereof, and display device
The present invention teaches a pixel unit including thin film transistors (TFTs) and pixel electrodes corresponding to the TFTs. The pixel electrodes are connected to the source electrodes of the TFTs. Each pixel electrode includes multiple arc-shaped electrode units arranged at intervals along an axial direction around a periphery of a corresponding TFT. The electrode units are electrically connected together. The present invention adopts arc-shaped pixels (similar to concentric circles) so that liquid crystal molecules are closer to being isotropic. Then, by having different vertical alignment (VA) TFT designs in the primary pixel region and secondary pixel region and utilizing the differences in W/L and capacitance, different voltage levels for primary pixel electrode and secondary pixel electrode are achieved. The color shift problem is improved and the viewing angle is enhanced. |
| US11322525B2 |
Array substrate and display panel having organic insulating elastic layer disposed on bending pathway
An array substrate and a display panel are provided. The array substrate includes a flexible substrate, a peripheral trace, and a bending pathway. The array substrate is folded along the bending pathway so that the peripheral trace is located on the back side of a display zone to increase an area of the display zone of a displaying screen. |
| US11322524B2 |
Display panel
A display panel is disclosed, which includes: a substrate including a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer and a first conducting electrode on the substrate, wherein the first conducting electrode electrically connects to the active layer, and the first conducting electrode extends along a first direction; and a conductive layer disposed on the border region and including an opening, wherein the conductive layer partially overlaps the first conducting electrode in a top view of the border region, wherein a minimum distance from an edge of the opening to the active layer along the first direction is different from a minimum distance from another edge of the opening to the active layer along a second direction, and the first direction is different from the second direction. |
| US11322519B2 |
Semiconductor device and method of fabricating the same
A semiconductor includes a ferroelectric layer, a first semiconductor layer, a first gate, a second semiconductor layer, a second gate and contact structures. The ferroelectric layer has a first surface and a second surface opposite to the first surface. The first semiconductor layer is disposed on the first surface of the ferroelectric layer. The first gate is disposed on the first semiconductor layer over the first surface. The second semiconductor layer is disposed on the second surface of the ferroelectric layer. The second gate is disposed on the second semiconductor layer over the second surface. The contacts structures are connected to the first semiconductor layer and the second semiconductor layer. |
| US11322513B2 |
Method for manufacturing semiconductor memory device and semiconductor memory device
According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film. |
| US11322512B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device including a stacked body that includes insulating layers and conductive layers that are alternately stacked, a first film provided inside a recess portion that penetrates through the stacked body, a second film provided on a surface of the first film, a third film provided on a surface of the second film, and a fourth film provided on a surface of the third film. An average concentration of a halogen element per unit area in the third film and the fourth film is lower than an average concentration of the halogen element per unit area at an interface between the third film and the fourth film. |
| US11322511B2 |
Semiconductor memory device
A semiconductor memory device includes a memory cell array disposed on a source plate; a discharge plate disposed on a bottom surface of the source plate; a source line discharge circuit disposed on a substrate below the discharge plate, and electrically coupling the discharge plate to a ground node in response to a source line discharge control signal; and a discharge path provided between the discharge plate and the source line discharge circuit. |
| US11322504B2 |
Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded SRAM in state-of-the-art CMOS technology
Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces. |
| US11322503B2 |
Integrated circuit including at least one memory cell with an antifuse device
An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state. |
| US11322500B2 |
Stacked capacitor with horizontal and vertical fin structures and method for making the same
A stacked capacitor includes a substrate having a first ILD layer thereon and a source conductive plate in the first ILD layer; a second ILD layer disposed on the first ILD layer; and a stacked capacitor area in the second ILD layer. The stacked capacitor area partially exposes the source conductive plate. A fin-shaped structure is disposed on the source conductive plate within the stacked capacitor area. The fin-shaped structure includes horizontal fins and vertical fins. A widened central hole penetrates through the fin-shaped structure and partially exposes the source conductive plate. A first conductive layer is disposed on the fin-shaped structure and the source conductive plate in the widened central hole. A capacitor dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the capacitor dielectric layer. |
| US11322495B2 |
Complementary metal-oxide-semiconductor device and method of manufacturing the same
A complementary metal-oxide-semiconductor device includes a p-type field effect transistor and an n-type filed effect transistor. The p-type filed effect transistor has a first transistor architecture. The n-type field effect transistor is coupled with the p-type field effect transistor and has a second transistor architecture. The second transistor architecture is different from the first transistor architecture. The p-type field effect transistor and the n-type field effect transistor share a same gate structure. |
| US11322492B2 |
Semiconductor device with controllable channel length and manufacturing method thereof
A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region. |
| US11322488B2 |
Display device using semiconductor light emitting element
The present invention relates to a display device and, more particularly, to a display device using a semiconductor light emitting element. The display device according to the present invention comprises a light emitting element module, wherein the light emitting element module comprises: a red semiconductor light emitting element that emits red light; a green semiconductor light emitting element that is disposed on the top surface of the red semiconductor light emitting element; a blue semiconductor light emitting element that is disposed on the top surface of the green semiconductor light emitting element; an individual electrode portion for supplying an individual signal to each of the red semiconductor light emitting element, the green semiconductor light emitting element, and the blue semiconductor light emitting element; and a common electrode portion for supplying a common signal to the red semiconductor light emitting element, the green semiconductor light emitting element, and the blue semiconductor light emitting element. |
| US11322479B2 |
Semiconductor packages and manufacturing methods thereof
A semiconductor package includes a first chip, a plurality of through vias and an encapsulant. The first chip has a first via and a protection layer thereon. The first via is disposed in the protection layer. The through vias are disposed aside the first chip. The encapsulant encapsulates the first chip and the plurality of through vias. A surface of the encapsulant is substantially coplanar with surfaces of the protection layer and the plurality of through vias. |
| US11322477B2 |
Package structure and method of fabricating the same
A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die. |
| US11322476B2 |
Manufacturing method of producing shielded individual semiconductor packages
A manufacturing method of a semiconductor package includes a groove forming step of cutting a semiconductor package substrate from an upper surface side along division lines in a cut-in-depth range of at least such a depth as to cause a ground line included in a wiring substrate to be exposed in a processing groove to such a depth that the semiconductor package substrate is not fully cut with a first cutting blade, thereby forming the processing groove having a first width at least on an upper surface of a sealing material, a shielding layer forming step of forming a shielding layer on a side surface of the processing groove, a bottom surface of the processing groove, and the upper surface of the sealing material with a conductive material from an upper side of the sealing material, and a dividing step of, cutting the semiconductor package substrate into individual semiconductor packages. |
| US11322475B2 |
Stack semiconductor packages having wire-bonding connection structure
A semiconductor package includes a package substrate having a hole pattern including a first through hole extending in a first direction and a second through hole extending in a second direction substantially perpendicular to the first direction, at least one first semiconductor chip disposed on the package substrate to overlap with the first through hole, at least one second semiconductor chip disposed on the package substrate to overlap with the second through hole, first bonding wires passing through the first through hole to electrically connect the at least one first semiconductor chip to the package substrate, and second bonding wires passing through the second through hole to electrically connect the at least one second semiconductor chip to the package substrate. |
| US11322470B2 |
Optical semiconductor package and method for manufacturing the same
A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure. |
| US11322469B2 |
Dual solder methodologies for ultrahigh density first level interconnections
An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy. |
| US11322468B2 |
Semiconductor device including metal holder and method of manufacturing the same
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad. |
| US11322466B2 |
Semiconductor die containing dummy metallic pads and methods of forming the same
A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric layers embedding first metal interconnect structures and located over the first semiconductor devices, a first pad-level dielectric layer embedding first bonding pads and located over the first interconnect-level dielectric layers, and first edge seal structures laterally surrounding the first semiconductor devices. Each of the first edge seal structures vertically extends from the first substrate to a distal surface of the first pad-level dielectric layer, and includes a respective first pad-level ring structure that continuously extends around the first semiconductor devices. At least one row of first dummy metal pads is embedded in the first pad-level dielectric layer between a respective pair of first edge seal structures. Second pad-level ring structures embedded in a second semiconductor die can be bonded to the rows of first dummy metal pads. |
| US11322464B2 |
Film structure for bond pad
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die. |
| US11322461B2 |
Package with integrated multi-tap impedance structure
A package is disclosed. In one example the package comprises a carrier having a plurality of leads and an electronic component mounted on the carrier and comprising at least one pad. An impedance structure electrically couples the at least one pad with the carrier so that, at different ones of the leads, different impedance values of the impedance structure can be tapped. |
| US11322460B2 |
Secure integrated-circuit systems
A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility. |
| US11322457B2 |
Control of warpage using ABF GC cavity for embedded die package
Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material. |
| US11322453B2 |
Semiconductor package having channels formed between through-insulator-vias
A semiconductor package includes a die, through insulator vias, an encapsulant, and a pair of metallization layers. The through insulator vias are disposed beside the die. The encapsulant wraps the die and the through insulator vias. The pair of metallization layers is disposed on opposite sides of the encapsulant. One end of each through insulator via contacts one of the metallization layers and the other end of each through insulator via contacts the other metallization layer. The through insulator vias form at least one photonic crystal structure. A pair of the through insulator vias is separated along a first direction by a channel filled by the encapsulant. A width of the channel along the first direction is larger than a pitch of the photonic crystal structure along the first direction. |
| US11322451B2 |
Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module
A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. |
| US11322450B2 |
Chip package and method of forming the same
A chip package including a semiconductor die, an insulating encapsulant, and a first redistribution layer is provided. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is provided over the semiconductor die and the encapsulant and includes a first redistribution portion and a second redistribution portion in contact with the first redistribution portion. The first redistribution portion is between the second redistribution portion and the semiconductor die. The first redistribution portion includes a first dielectric portion and a plurality of first conductive features embedded in the first dielectric portion. The plurality of first conductive features electrically connects the semiconductor die to the second redistribution portion. The second redistribution portion includes a second dielectric portion and a plurality of second conductive features embedded in the second dielectric portion and connected to the first conductive features. A top surface of the second dielectric portion is substantially level with top surfaces of the plurality of second conductive features. A method of forming the chip package is also provided. |
| US11322448B2 |
Electronic module
An electronic module has a first substrate 11; a second substrate 21 provided in one side of the first substrate 11; and a chip module 100 provided between the first substrate 11 and the second substrate 21. The chip module 100 has an electronic element 13, 23 and a connecting body 60, 70, 80 electrically connected to the electronic element 13, 23. The electronic element 13, 23 extends along a first direction that is a thickness direction of the electronic module. |
| US11322446B2 |
System-in-packages including a bridge die
A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die. |
| US11322440B2 |
Three-dimensional memory device with dielectric wall support structures and method of forming the same
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located between line trenches, a first memory array region and a second memory array region, and a pair of dielectric wall structures located between the first line trench and the second line trench and between the memory array regions. Each layer within the alternating stack continuously extends between the first memory array region and the second memory array region in a connection region. The electrically conductive layers of the alternating stack have lateral extents that decrease with a distance from the substrate in a staircase region. Dielectric material plates interlaced with insulating plates or insulating layers are provided between the dielectric wall structures. |
| US11322439B2 |
FEOL interconnect used as capacitance over fins instead of gates
Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins. |
| US11322437B2 |
Flip chip interconnection and circuit board thereof
A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads. |
| US11322435B2 |
Package substrate having power trace pattern and ground trace pattern, and semiconductor package including the same
A package substrate according to an aspect of the disclosure includes a substrate body, and a first power trace pattern and a first ground trace pattern disposed on a first surface of the substrate body. The first power trace pattern has a parent power line portion and at least one child power line portion branched from the parent power line portion, and the first ground trace pattern has a parent ground line portion and at least one child ground line portion branched from the parent ground line portion. At least a portion of the first power trace pattern is disposed to surround at least a portion of the first ground trace pattern, and at least a portion of the first ground trace pattern is disposed to surround at least a portion of the first power trace pattern. |
| US11322434B2 |
Top-to-bottom interconnects with molded lead-frame module for integrated-circuit packages
Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate. |
| US11322425B2 |
Semiconductor device
Provided is a semiconductor device having excellent heat radiation performance and electromagnetic wave suppression effect. A semiconductor device 1 comprises: a semiconductor element 30 formed on a substrate 50; a conductive shield can 20 having an opening hole 21; a conductive cooling member 40 located above the conductive shield can 20; a heat conductive sheet 10 formed between the semiconductor element 30 and the conductive cooling member 40 at least through the opening hole 21; and a conductive member 11 electrically connecting the conductive shield can 20 and the conductive cooling member 40. |
| US11322421B2 |
Package structure and method of forming the same
Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes. |
| US11322408B2 |
Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack. |
| US11322403B2 |
Wafer processing method
A wafer processing method includes: cutting a device layer stacked on a semiconductor substrate along division lines to form cut grooves; positioning a focal point of a laser beam having a transmission wavelength to the semiconductor substrate inside an area of the semiconductor substrate corresponding to a predetermined one of the division lines and applying the laser beam to the wafer from a back surface of the wafer, thereby forming a plurality of modified layers inside the wafer along all of the division lines; and grinding the back surface of the wafer to be thinned, causing a crack to grow from each of the modified layers formed inside the area of the semiconductor substrate corresponding to the predetermined one of the division lines to the front surface side of the wafer, thereby dividing the wafer into individual device chips. |
| US11322399B2 |
Semiconductor structure and formation method thereof
Semiconductor structure and method for forming the semiconductor structure are provided. An exemplary method includes: providing a substrate, including a first region and a second region; forming a gate structure over the substrate; forming a first interlayer dielectric layer over the substrate; forming a plurality of metal plugs in the first interlayer dielectric layer; forming a second interlayer dielectric layer over the first interlayer dielectric layer; forming a first via in the first region exposing a metal plug, and a second via in the second region exposing the first interlayer dielectric layer by etching the second interlayer dielectric layer; fully filling the first via with a first tungsten layer; forming an adhesion layer over the first tungsten layer, the second interlayer dielectric layer, and a sidewall and bottom of the second via; and fully filling the second via with a second tungsten layer. |
| US11322397B2 |
Method of manufacturing semiconductor devices including formation of adhesion enhancement layer
In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer. |
| US11322395B2 |
Dielectric capping structure overlying a conductive structure to increase stability
Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure. |
| US11322394B2 |
Contact formation method and related structure
A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer. |
| US11322393B2 |
Method of forming a semiconductor device
A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer. |
| US11322388B2 |
Semiconductor structure formation
An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches. |
| US11322384B2 |
Substrate processing apparatus and substrate processing method
According to one embodiment, a substrate processing apparatus and a substrate processing method that can improve the quality of substrates are provided. The substrate processing apparatus according to one embodiment includes: a table 20 configured to support a processing target W including a substrate W1, a ring W2 surrounding a surrounding of the substrate W1, and a dicing tape W3 adhered to a lower surface of the substrate W1 and a lower surface of the ring W2, and a liquid supplier 50 configured to eject a liquid which does not mix with a processing liquid for processing the substrate W1 and which has a specific gravity heavier than the processing liquid to one of an upper surface of the ring W2 of the processing target W supported by the table 20 rotating by the rotation mechanism 30, an outer circumference end portion of the substrate W1 of the processing target W supported by the table 20 rotating by the rotation mechanism 30, and between the substrate W1 and the ring W2 of the processing target W supported by the table 20 rotating by the rotation mechanism in accordance with a rotation number of the table 20 to supply the liquid between the substrate W1 and the ring W2 of the processing target W. |
| US11322381B2 |
Method for substrate registration and anchoring in inkjet printing
A method for printing on a substrate includes printing a support structure by printing a liquid precursor material and curing the liquid precursor material, positioning a substrate within the support structure, printing one or more anchors on the substrate and the support structure by printing and curing the liquid precursor material to secure the substrate to the support structure, and printing one or more device structures on the substrate while anchored by printing and curing the liquid precursor material. |
| US11322379B2 |
Wafer storage box, wafer transfer device and wafer storage and transfer assembly having the same
A wafer storage box, wafer transfer device and wafer storage box and transfer assembly. The wafer storage and transfer assembly includes a chassis which is capable of translating or rotating, a sliding shaft, connecting levers, arms and at least two positioning sidewall. The chassis includes a groove. The sliding shaft can translate along the groove. The connecting levers are connected to the sliding shaft. Each arm extends from a connecting lever. The two positioning sidewall are respectively arranged on opposite sides of the chassis. Each positioning sidewall includes tracks accommodating the pins of connecting levers. The width of each of the tracks reduces from the front end of the positioning sidewall to the back end of the positioning sidewall. The wafer storage and transfer assembly can vacuum adsorb several wafers to achieve high efficiency of wafer storing and transferring. |
| US11322375B2 |
Light irradiation type heat treatment method and heat treatment apparatus
A silicon semiconductor wafer is transported into a chamber, and preheating of the semiconductor wafer is started in a nitrogen atmosphere by irradiation with light from halogen lamps. When the temperature of the semiconductor wafer reaches a predetermined switching temperature in the course of the preheating, oxygen gas is supplied into the chamber to change the atmosphere within the chamber from the nitrogen atmosphere to an oxygen atmosphere. Thereafter, a front surface of the semiconductor wafer is heated for an extremely short time period by flash irradiation. Oxidation is suppressed when the temperature of the semiconductor wafer is relatively low below the switching temperature, and is caused after the temperature of the semiconductor wafer becomes relatively high. As a result, a dense, thin oxide film having good properties with fewer defects at an interface with a silicon base layer is formed on the front surface of the semiconductor wafer. |
| US11322374B2 |
Optical station for exchanging optical elements
An optical station for a laser processing device including a plurality of holders for holding respective optical elements; a rotatable magazine having a plurality of accommodation spaces for accommodating the plurality of holders; a positioning device having a holder clamp for clamping and positioning a selected one of the optical elements. a magazine actuator for rotating the magazine; linear shifting means for shifting the magazine in a direction parallel to the optical axis, wherein the magazine is shifted towards the positioning device such that the positioning device lifts the holder from its accommodation space. |
| US11322369B2 |
Powder protecting three-way valve
Disclosed is a powder protecting three-way valve for a semiconductor or flat panel display manufacturing apparatus, including: a valve casing including an inlet and a plurality of outlets; a rotating ball rotatably installed in the valve casing to control a flow direction of reaction by-product gas; a nitrogen gas supply member which receives nitrogen gas from an outside, guides a flow of the nitrogen gas using a guide path, and supplies the nitrogen gas into the valve casing to prevent a powder contained in the reaction by-product gas from accumulating in the valve casing; and a heating unit installed in the nitrogen gas supply member to heat the nitrogen gas passing through an interior of the nitrogen gas supply member. The nitrogen gas supply member is formed as a thin flat body pressed against one side surface of the valve casing and is integrally coupled to the valve casing. |
| US11322366B1 |
Ultrafast laser annealing of thin films
A method for locally annealing and crystallizing a thin film by directing ultrashort optical pulses from an ultrafast laser into the film. The ultrashort pulses can selectively produce an annealed pattern and/or activate dopants on the surface or within the film. |
| US11322362B2 |
Landing metal etch process for improved overlay control
A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned. |
| US11322360B2 |
Method of manufacturing semiconductor structure
A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing the die on a substrate; disposing a molding surrounding the die; removing a portion of the molding to expose a sidewall of the sacrificial layer, wherein a top surface of the molding is at a level substantially same as the top surface of the die; and removing the sacrificial layer from the die. |
| US11322359B2 |
Single process for liner and metal fill
After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process. |
| US11322357B2 |
Buried damage layers for electrical isolation
Structures including electrical isolation and methods of forming a structure including electrical isolation. A first polycrystalline layer is located in a substrate, and a second polycrystalline layer is positioned between the first polycrystalline layer and a top surface of the substrate. The substrate includes a first portion of the single-crystal semiconductor material that is positioned between the second polycrystalline layer and the top surface of the substrate. The substrate includes a second portion of the single-crystal semiconductor material that is positioned between the first polycrystalline layer and the second polycrystalline layer. The first polycrystalline layer has a thickness. The second polycrystalline layer has a portion with a thickness that is greater than the thickness of the first polycrystalline layer. |
| US11322356B2 |
System and method for precision formation of a lattice on a substrate
A system and method for manufacturing a lattice structure of ionized particles on a substrate, wherein the process may be improved by controlling the number of ionized particles that are ejected from an ionizer and directed to a substrate, and wherein the ionized particles are disposed on the substrate, thereby enabling the creation of a lattice structure that may be as thin as a single layer of ionized particles. |
| US11322351B2 |
Tin oxide films in semiconductor device manufacturing
Tin oxide film on a semiconductor substrate is etched selectively in a presence of silicon (Si), carbon (C), or a carbon-containing material (e.g., photoresist) by exposing the substrate to a process gas comprising hydrogen (H2) and a hydrocarbon. The hydrocarbon significantly improves the etch selectivity. In some embodiments an apparatus for processing a semiconductor substrate includes a process chamber configured for housing the semiconductor substrate and a controller having program instructions on a non-transitory medium for causing selective etching of a tin oxide layer on a substrate in a presence of silicon, carbon, or a carbon-containing material by exposing the substrate to a plasma formed in a process gas that includes H2 and a hydrocarbon. |
| US11322348B2 |
Multi-function equipment implementing fabrication of high-k dielectric layer
A multi-function equipment implements a method of fabricating a thin film. The multi-function equipment according to the invention includes a reaction chamber, a plasma source, a plasma source power generating unit, a bias electrode, an AC (Alternating Current) voltage generating unit, a DC (Direct current) bias generating unit, a metal chuck, a first precursor supply source, a second precursor supply source, a carrier gas supply source, an oxygen supply source, a nitrogen supply source, an inert gas supply source, an automatic pressure controller, and a vacuum pump. |
| US11322347B2 |
Conformal oxidation processes for 3D NAND
Embodiments described herein generally relate to conformal oxidation processes for flash memory devices. In conventional oxidation processes for gate structures, growth rates have become too fast, ultimately creating non-conformal films. To create a preferred growth rate for SiO2 on SiNx films, embodiments in this disclosure use a thermal combustion of a ternary mixture of H2+O2+N2O to gain SiO2 out of Si containing compounds. Using this mixture provides a lower growth in comparison with using only H2 and O2, resulting in a lower sticking coefficient. The lower sticking coefficient allows an optimal amount of atoms to reach the bottom of the gate, improving the conformality in 3D NAND SiO2 oxidation layers, specifically for ONO replacement tunneling gate formation. |
| US11322346B2 |
Cleaning substrate method and method of processing substrate using the same
A method of processing a substrate may include preparing the substrate, polishing the substrate, and cleaning the substrate using a double nozzle, which is configured to provide a spray and a chemical solution onto the substrate. The spray may include a deionized water, and the chemical solution may be diluted with the deionized water. The chemical solution and the spray may be spaced apart from each other by a distance of 7 cm to 12 cm. |
| US11322342B2 |
Mass separator using retractable magnetic yoke on a beam bending path
Provided is a mass separator (100) for performing mass separation for an ion beam (IB). The mass separator (100) includes a transfer structure (30) that is a component of a yoke (13) and move at least one of an upper yoke (13a) positioned over the beam path (L), a lower yoke (13b) positioned under the beam path (L), and a side yoke (13c, 13d) positioned at a side of the beam path (L) between a normal position (P) in the traveling of the ion beam (IB) and a retracted position (Q) that does not overlap with at least a part of the normal position (P); the yoke (13) is surrounding the beam path (L) and is made of a magnetic body. |
| US11322340B2 |
Coupling of ion mobility spectrometer with mass spectrometer
Disclosed is an ion carousel having a first surface and a second surface adjacent to the first surface. The second surface includes a first inner array of electrodes arranged along a first loop path and configured to receive a first ion packet and a second ion packet temporally separated from the first ion packet by a separation time. The first inner array of electrodes generates a traveling waveform which includes a plurality of potential wells that travel along the first loop path and receive ions from the first and second ion packets. The plurality of potential wells include at least a first potential well and a second potential well. An output switch is configured to selectively eject ions from the first potential well out of the carousel at time T1 and eject ions from the second potential well out of the carousel at time T2. |
| US11322338B2 |
Sputter target magnet
A method for modifying magnetic field distribution in a deposition chamber is disclosed. The method includes the steps of providing a target magnetic field distribution, removing a first plurality of fixed magnets in the deposition chamber, replacing each of the first plurality of fixed magnets with respective ones of a second plurality of magnets, performing at least one of adjusting a position of at least one of the second plurality of the magnets, and adjusting a size of at least one of the second plurality of magnets, adjusting a magnetic flux of at least one of the second plurality of magnets, measuring the magnetic field distribution in the deposition chamber, and comparing the measured magnetic field distribution in the deposition chamber with the target magnetic field distribution. |
| US11322335B2 |
Charged particle multi-beam device
A charged particle multi-beam device includes a charged particle source, a collimator lens, a multi-light-source forming unit, and a reduction projection optical system. The multi-light-source forming unit has first to third porous electrodes disposed side by side in an optical axis direction. A plurality of holes for causing the multi-beams to pass is formed in each of the first to third porous electrodes. The first porous electrode and the third porous electrode have the same potential and the second porous electrode has potential different from the potential of the first porous electrode and the third porous electrode. A diameter of the holes on the second porous electrode is formed larger further away from an optical axis such that a surface on which the multi-light sources are located is formed in a shape convex to the charged particle source side. |
| US11322328B2 |
Circuit breakers with shaped neutral busbars and/or load terminals and related methods
Arc Fault Circuit Interrupter (AFCI), Ground Fault Circuit Interrupter (GFCI) or AF/GF circuit breakers which may optionally have relatively small or compact bodies that have shaped neutral busbars and/or load terminals with an arm that extends through a window of a current transformer in a circuit breaker housing. The neutral busbar and/or load terminal can have a rigid or semi-rigid shaped body with a first segment that extends through the window of the current transformer and a second segment that extends behind the first segment about a printed circuit board. A plug-on, pigtail or bolt-on neutral can engage an electrical pad of the neutral busbar. |
| US11322326B1 |
Elastic contact plate structure of electromagnetic relay
An elastic contact plate structure of an electromagnetic relay includes at least one elastic plate assembly and at least one contact structure. The elastic plate assembly includes first, second, third and fourth plates sequentially stacked on one another, and first plate has a first convex arc bent portion with first mounting hole formed at an end; second plate has second convex arc bent portion with second mounting hole formed at an end. Third plate has third mounting hole formed at an end; fourth plate has fixed section, which has fourth mounting hole, and elastic section. Contact structure is passed and fixed into first, second, third, and fourth mounting hole. Therefore, the force receiving strength of elastic contact plate structure shows a positive linear change with the deformation, and the stability of connecting or disconnecting elastic contact plate structure is improved significantly, so as to achieve a better electrical performance. |
| US11322323B1 |
Magnetic switch assembly
A magnetic switch assembly comprising a toggle bar and a switch actuator each rotatable between a first position and a second position, at least one set of magnets including a first magnet mounted on the proximal end portion of the toggle bar and a second magnet mounted on the proximal end portion of the switch actuator and a corresponding pair of electrical contacts including a first electrical contact coupled to a first electrical conductor and a second electrical contact coupled to a second electrical conductor wherein the toggle bar is normally bias in the first position when the switch actuator is in the first position with the first magnet disposed in spaced relationship relative to the second magnet when each is in the first position and having a gap therebetween such that the first electrical contact and the second electrical contact engage each other to complete an electrical circuit between the first electrical conductor and the second electrical conductor and when the switch actuator is moved from the first position to the second position decreasing the gap between the first magnet and the second magnet as the magnetic attraction therebetween overcomes the toggle bar bias disengaging the second electrical contact from the first electrical contact to create an open electrical circuit. |
| US11322322B2 |
Insulating molded body and gas circuit breaker
An insulating molded body to be used for an arc extinguishing device of a gas circuit breaker is provided. The insulating molded body includes a fluororesin mixture which contains a fluororesin and an oxygen generator configured to generate oxygen through thermal decomposition at 450° C. or more and 1,150° C. or less with an arc generated when a conduction current is interrupted. The oxygen generator is dispersed in the fluororesin. Also provided is a gas circuit breaker including an insulating nozzle formed of the insulating molded body. |
| US11322319B2 |
Disconnecting device for interrupting a direct current of a current path, and on-board electrical system of a motor vehicle
A separating device for interrupting a direct current of a current path, in particular for an on-board electrical system of a motor vehicle. The separating device has a hybrid switch with a current-conducting mechanical contact system and a first semiconductor switch connected to the hybrid switch in parallel and having a switchable resistance cascade with at least one ohmic resistor which is connected to the contact system of the hybrid switch in parallel. |
| US11322316B2 |
Home monitoring and control system
This application is directed to a home monitoring and control system including a doorbell installed at a door of a home. The doorbell has a button configured to, upon being touched, depressed or activated, wirelessly initiate a first communication to indicate presence of a person at the door. The doorbell also has a camera configured to capture video data within a field of view, and a processor configured to cause a communication component to enable the first communication and wirelessly stream via a remote server the video data captured by the camera to a monitoring device associated with an occupant of the home. A rechargeable battery is coupled to a housing wire and configured to be charged via the housing wire, and the doorbell is configured to charge and discharge the rechargeable battery based on power usage of the doorbell. |
| US11322313B2 |
Power accumulation system and vehicle including the same
A power accumulation system includes a power accumulation device, a relay device provided in a pair of power lines disposed between the power accumulation device and a power conversion device that exchanges power with the power accumulation device, a capacitor provided between the pair of power lines between the relay device and the power conversion device and an electronic control device that controls the relay device. The electronic control device is configured to execute a predetermined foreign matter removal process when it is not possible to bring one of a first relay and a second relay from a power blocking state to a conductive state. |
| US11322311B2 |
Methods, systems and apparatus for powering a vehicle
This application is directed to an apparatus for providing electrical charge to a vehicle. The apparatus comprises a driven mass, a generator, a charger, a hardware controller, and a communication circuit. The driven mass rotates in response to a kinetic energy of the vehicle and is coupled to a shaft such that rotation of the driven mass causes the shaft to rotate. The driven mass exists in one of (1) an extended position and (2) a retracted position. The generator generates an electrical output based on a mechanical input coupled to the shaft such that rotation of the shaft causes the mechanical input to rotate. The charger is electrically coupled to the generator and: receives the electrical output, generates a charge output based on the electrical output, and conveys the charge output to the vehicle. The controller controls whether the driven mass is in the extended position or the retracted position in response to a signal received from the communication circuit. |
| US11322310B2 |
Method for producing photochemical electrode
A photochemical electrode includes: an electrically conductive layer; and a photoexcitation material layer provided over the electrically conductive layer and including a photoexcitation material, wherein the photoexcitation material layer is one of a first photoexcitation material layer in which a potential of the conduction band minimum decreases from a second surface opposite to a first surface on the side of the electrically conductive layer toward the first surface and a second photoexcitation material layer in which a potential of the valence band maximum decreases from the second surface toward the first surface. |
| US11322309B2 |
Tantalum capacitor
A tantalum capacitor includes: a tantalum body including tantalum, and having a tantalum wire in which a distance from a lower surface of the tantalum body is closer than a distance from an upper surface of the tantalum body; an insulating member on which the tantalum body is disposed; an encapsulation portion; an anode terminal including an upper anode and connected to the tantalum wire, a lower anode pattern, and an anode connection portion connecting the upper anode pattern and the lower anode pattern; and a cathode terminal including an upper cathode pattern and connected to the tantalum body, a lower cathode pattern disposed on a lower surface of the insulating member to be spaced apart from the lower anode pattern, and a cathode connection portion connecting the upper cathode pattern and the lower cathode pattern. |
| US11322307B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a third segregation by each of metal elements of a first segregation and a second segregation is provided at each of a first corner region in which an end in a length direction in which the first segregation is provided overlaps an end in a width direction in which the second segregation is provided in a first internal electrode layer, and a second corner region in which an end in the length direction in which the second segregation is provided overlaps an end in the width direction in which the second segregation is provided in a second internal electrode layer. |
| US11322305B2 |
Multilayer capacitor
A multilayer capacitor includes a capacitor body having first through six surfaces, and having alternately stacked first internal electrodes and second internal electrodes having dielectric layers therebetween and each having one end thereof exposed through a respective one of third and fourth surfaces. First and second conductive layers respectively include first and second connection portions respectively disposed on the third and fourth surfaces of the capacitor body and respectively connected to the first and second internal electrodes, and first and second band portions respectively extending from the first and second connection portions to respective portions of the first, second, fifth, and sixth surfaces of the capacitor body. First and second reinforcing layers each include a carbon material and an impact-absorbing binder and are respectively disposed on the first and second band portions. |
| US11322304B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween in a stacking direction, and including a first surface and a second surface opposing each other in the stacking direction, a first through electrode penetrating the body and connected to the first internal electrode; a second through electrode penetrating the body and connected to the second internal electrode, first and second external electrodes disposed on the first surface and the second surface, respectively, and connected to the first through electrode, third and fourth external electrodes spaced apart from the first and second external electrodes and connected to the second through electrode, and an identifier disposed on the first surface or the second surface of the body, and the first and second through electrodes protrude from the first surface of the body. |
| US11322301B2 |
Method for manufacturing inductor built-in substrate
A method for manufacturing an inductor built-in substrate includes forming openings in a core substrate including a resin substrate and a metal foil laminated on the resin substrate, filling a magnetic resin in the openings formed in the substrate, forming a shield layer including a first plating film on the substrate and on a surface of the magnetic resin such that the shielding layer is formed on the metal foil and on the surface of the magnetic resin, forming first through holes in the substrate, applying a desmear treatment in the first through holes, forming second through holes in the magnetic resin after the desmear treatment, and forming a second plating film on the substrate, on the magnetic resin, and in the first and second through holes such that the second plating film is formed on the shield layer, in the first through holes, and in the second through holes. |
| US11322299B2 |
Folded MRI safe coil assembly
Implants or sensors often include and rely on inductive and ferromagnetic electrical components to measure and communicate data outside of the body to an external device, creating a safety concern when a patient with these implants or sensors must undergo an MRI scan. Further, various external devices that include inductive and ferromagnetic electrical components are exposed to potentially damaging MRI scans. An electrical coil assembly can include an electrical coil that includes a substrate and an electrical conductor supported by a first face of the substrate. In an example, the electrical coil assembly further includes a fuse element that is configured to move from a disengaged position in which the electrical fuse conductor is out of contact with the electrical conductor to an engaged position in which the electrical fuse conductor contacts the electrical conductor so as to define a short circuit. |
| US11322296B2 |
Pulse transformer and circuit module having the same
Disclosed herein is a pulse transformer that includes first to fourth terminal electrodes provided on the first flange part, fifth to eighth terminal electrodes provided on the second flange part, first and second wires wound around the winding core part having one end connected to the first and second terminal electrodes and other end connected to the seventh and eighth terminal electrodes, and third and fourth wire wound around the winding core part having one end connected to third and fourth terminal electrodes and other end connected to the fifth and sixth terminal electrodes. A winding direction of the first and third wires is opposite to a winding direction of the second and fourth wires. |
| US11322295B2 |
Coil component
A coil component includes a magnetic body portion that includes metallic particles and a resin material, a coil conductor that is embedded in the magnetic body portion, and a first outer electrode and a second outer electrode each of which is electrically connected to the coil conductor. At least a portion of an outer layer of the magnetic body portion forms an electrically conductive layer that includes a second metallic material having a specific resistance lower than a specific resistance of a first metallic material forming the metallic particles. The electrically conductive layer includes a first electrically conductive layer that is electrically connected to the first outer electrode and a second electrically conductive layer that is electrically connected to the second outer electrode. The first electrically conductive layer and the second electrically conductive layer are electrically isolated from each other. |
| US11322292B2 |
Coil component
A coil component includes a body, a coil conductor embedded in the body, and outer electrodes disposed on the outside of the body. The body includes a first magnetic layer containing a substantially spherical metallic magnetic material and second and third layers containing a substantially flat metallic magnetic material. At least the wound section of the coil conductor is between the second and third magnetic layers in the direction along the axis of the coil conductor. In the direction perpendicular to the axis, the second and third magnetic layers have a width equal to or larger than the outer diameter of the wound section of the coil component. The substantially flat metallic magnetic material is oriented so that the flat plane thereof is perpendicular to the axis of the coil conductor. The first magnetic layer extends between the second and third magnetic layers and the outer electrodes. |
| US11322282B2 |
Electromagnetic actuator
An electromagnetic actuator includes an essentially cylindrical pole tube, an armature situated radially within the pole tube, and an electromagnetic coil situated radially outside of the pole tube, the pole tube including a first axial end area, a second axial end area, and an outer recess, which extends in the circumferential direction, in proximity to the first axial end area on an outer side of the pole tube. On an inner side, the pole tube includes an inner recess that extends in the circumferential direction and whose axial extension is smaller than an axial extension of the outer recess and that is situated approximately at the height of an edge area of the outer recess pointing away from the second axial end area viewed in the axial direction. |
| US11322281B2 |
Multilayer block core, multilayer block, and method for producing multilayer block
A multilayer block core includes a multilayer block in which nanocrystalline alloy ribbon pieces are layered, the nanocrystalline alloy ribbon pieces having a composition represented by the following Composition Formula (A). Fe100-a-b-c-dBaSibCucMd Composition Formula (A) In Composition Formula (A), each of a, b, c, and d is an atomic percent; the expressions 13.0≤a≤17.0, 3.5≤b≤5.0, 0.6≤c≤1.1, and 0≤d≤0.5 are satisfied; and M represents at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, and W. |
| US11322280B2 |
Chip resistor
A chip resistor includes a substrate, a resistor layer, a first conductive layer, an insulating layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer is electrically connected to the resistor layer. The insulating layer covers the resistor layer and the first conductive layer. The second conductive layer covers the first conductive layer and the insulating layer. The third conductive layer covers the second conductive layer and the insulating layer. The fourth conductive layer covers the second conductive layer and the third conductive layer. Bonding strength between the third and fourth conductive layer is stronger than that between the second and fourth conductive layer. |
| US11322278B2 |
Automated wire processing system
A system is provided for wire processing. The wire processing system may include a wire transport, a processing station that may provide wire to the wire transport, a processing station that may move an electrical component threaded onto the wire, and a processing station that may move the electrical component to a position on the wire for further processing. |
| US11322276B2 |
Wire harness
A wire harness including: a wire; a cover that covers the wire; and a braid made of resin that covers the wire, wherein: the wire protrudes from a first end of the cover to an outside of the cover, and a space is formed between the wire and the first end, and the braid is provided at a position that overlaps the first end of the cover in a longitudinal direction of the wire and is exposed to the outside of the cover. |
| US11322275B2 |
Flame resistant data cables and related methods
A data cable is provided herewith, along with related methods. The disclosed data cables may meet the requirements for a UL 2196 flame test, including subsequent hose stream test. The disclosed data cables include two or more pairs of conductors wrapped with a flame-retardant tape and surrounded by low smoke zero halogen (LSZH) thermoset insulation. A shield may surround the conductor pairs and a non-halogen flame retardant polyolefin may surround the shield. In certain embodiments, the pairs of conductors present in the cable may have different lay lengths. |
| US11322274B2 |
Low dielectric constant structures for cables
A ribbon cable is described, including a plurality of conductors extending along a length of the cable, and a structured insulative tape comprising a plurality of spaced apart supports forming alternating first and second groups of supports disposed on a major surface of the structured insulative tape. Each first group of supports includes at least one taller first support, and each second group of supports includes at least one shorter second support. The insulative tape is helically wrapped around the plurality of conductors along the length of the cable such that each first group of supports is disposed between and maintains a minimum separation between two adjacent conductors, and each second group of supports is disposed around one or more conductors to maintain spacing between the conductors and an outer surface of the ribbon cable. |
| US11322268B2 |
Method and device for disposing nuclear waste using deep geological repository
A disposal device comprises a raw material conveyor, a raw material mixer, a liquid waste conveying pipeline, an additive tank, a powder waste conveyor, an output pump, a liquid supply pump, a liquid supply manifold, an output manifold, a mixed liquid conveying pipeline, a high-pressure injection pump, a high-pressure pipeline, and a wellhead sealing device. A method of employing the device includes: drilling a well; forming a fracture in the granite stratum; preparing a raw material; and injecting, by using the disposal device, a sand-carrying feed liquid from a high-pressure injection pump into the fracture of the underground granite stratum, so as to perform solidification. |
| US11322266B2 |
Modular fluid flow distribution system in which differently shaped plates can be rearranged to different positions
Modular flow control systems include several differently-shaped structures to achieve desired flow characteristics in fluid flow. Systems include one or many plates held in desired positions by a retainer within the flow. The plates are uniquely shaped based on their position, or vice versa, to shape flow in a desired manner. The plates may fill an entire flow area or may extend partially throughout the area. Plates can take on any shape and are useable in systems installed in any type of flow conduit. When used in a PCCS upper manifold in a nuclear reactor, a chevron plate directly below the inlet divides flow along the entire upper manifold. Perforated plates allow flow to pass at ends of the PCCS upper manifold. The plates can be installed along a grooved edge during an access period and held in static position by filling the length of the PCCS upper manifold. |
| US11322264B2 |
Systems and methods for human-augmented communications
The present disclosure is generally directed to the field of human-augmentation using computing devices and techniques. In particular, a computer-implemented method may include: (1) identifying, via a message identification component, at least one message associated with a message exchange platform, the message including a query; (2) transmitting, via a communication component, the message to one or more users at respective user devices; (3) receiving, via a recommendation component, responses to the query from the respective user devices; (4) determining, via a scoring component, respective scores of the responses; and (5) selecting, via the scoring component, at least one response having a score exceeding a predetermined threshold. Various other methods, systems, devices, and computer-readable media are also disclosed. |
| US11322263B2 |
Systems and methods for collaborative notifications
Systems and methods are provided for presenting aggregate data in response to a natural language user input. In one example, a system includes a display and a computing device coupled to the display and storing instructions executable to output, to the display, a patient-specific communication thread including communication among one or more care providers monitoring a patient and a virtual healthcare assistant, generate, with the virtual healthcare assistant, a notification indicating a change in a state of the patient, and output, to the display, the notification, where the notification is displayable as part of the communication thread. |
| US11322262B2 |
System and method for consulting on culture plate readings
Systems and methods are provided for selecting colony locations. Selecting colony locations can include determine a location of a selection tool on a culture plate image, determining a location of a potential source of error on the culture plate image, comparing the location of the selection tool to the location of the potential source of error; and determining an error when the location of the selection tool overlays the location of the potential source of error. |
| US11322256B2 |
Automated labeling of images to train machine learning
A method, computer system, and a computer program product for automatic labeling to train a machine learning algorithm is provided. The present invention may include labeling a medical image with at least one finding from a corresponding medical report. The present invention may include determining a localization information from the labeled medical image. The present invention may include training the machine learning algorithm with the determined localization information. The present invention may include detecting at least one candidate in a test medical image. The present invention may include generating a discrepancy list between the at least one detected candidate in the test medical image and at least one human-reported finding in a corresponding test medical report. The present invention may include, in response to determining that the generated discrepancy list is above a threshold, retraining the trained machine learning algorithm until the generated discrepancy list is below the threshold. |
| US11322253B2 |
Wireless sensor connectivity
A wireless-connectivity system includes a sensor dongle configured to be electrically connected to a sensor device, a monitor dongle configured to be electrically connected to a medical monitor system, and a dongle-connectivity management hub configured to cause a wireless coupling to be established between the sensor dongle and the monitor dongle. The sensor dongle is configured to receive sensor data from the sensor and wirelessly transmit data to the monitor dongle via the wireless coupling, the data being based at least in part on the sensor data. |
| US11322250B1 |
Intelligent medical care path systems and methods
Further system and methods associated there with can use a combination of big data, machine learning, and/or regression equations to make living care paths based on sensitivities, probability, and/or statistics, which increases the chances of a living care path being successful. System, in some embodiments, can also provide a visual representation of the treatment options and statistics to the patient and HCP. As configured, system can empower patients, making them more informed about their condition, expectations of recovery, and more confident in their HCP's recommended treatment measure. |
| US11322246B2 |
Systems and methods for processing electronic images for generalized disease detection
Systems and methods are disclosed for generating a specialized machine learning model by receiving a generalized machine learning model generated by processing a plurality of first training images to predict at least one cancer characteristic, receiving a plurality of second training images, the first training images and the second training images include images of tissue specimens and/or images algorithmically generated to replicate tissue specimens, receiving a plurality of target specialized attributes related to a respective second training image of the plurality of second training images, generating a specialized machine learning model by modifying the generalized machine learning model based on the plurality of second training images and the target specialized attributes, receiving a target image corresponding to a target specimen, applying the specialized machine learning model to the target image to determine at least one characteristic of the target image, and outputting the characteristic of the target image. |
| US11322245B2 |
Medical image processing apparatus and medical observation system
A medical image processing apparatus includes: a superimposed image generation unit configured to generate a superimposed image by superimposing a subject image and a fluorescent image in areas corresponding to each other; a determination unit configured to determine whether or not at least one of a subject and an observation device moves from timing before timing at which one of the subject image and the fluorescent image is captured to the timing; and a superimposition controller configured to cause the superimposition image generation unit to prohibit a superimposition in an area of at least a part of the subject image and the fluorescent image when the determination unit determines that at least one of the subject and the observation device moves. |
| US11322243B2 |
Method and system for identifying and displaying medical images
An improved method and system for identifying and displaying related images obtained during an examination is disclosed. Each image includes both pixel data, corresponding to the image to be displayed, and location information, defining a relationship between the pixel data and a reference point. During a review of the images, a physician may identify an abnormality or particular region of interest in one image. The location information corresponding to the position identified by the physician within the image is obtained from the image file. Having identified location information for a particular location on the first image, the system analyzes the location information corresponding to the pixel data for each of the other stored images to identify any other image that intersects the identified location. All images that intersect the identified location may then be displayed adjacent to the first image for inspection by the physician. |
| US11322236B1 |
Data abstraction system architecture not requiring interoperability between data providers
Described are data abstraction systems, methods, and media for aggregating and abstracting data records from data providers, which are not substantially interoperable with each other. Features include data provider connector modules dynamically loaded, based on definitions stored on disk, that facilitate data mapping and individual matching. |
| US11322232B2 |
Lesion tracking system
A lesion tracking system is operable to receive a first medical scan and second medical scan associated with a patient ID. A lesion area calculation is performed on a first subset of image slices determined to include a lesion detected in the first medical to generate a first set of lesion area measurements. The lesion area calculation is performed on a second subset of image slices determined to include the lesion in the second medical scan to generate a second set of lesion area measurements. A lesion volume calculation is performed on the first set of lesion area measurements and the second set of lesion area measurements to generate a first lesion volume measurement and a second lesion volume measurement, respectively, and the first and second lesion volume measurements are utilized to calculate a lesion volume change for transmission to a client device for display via a display device. |
| US11322226B2 |
Systems and methods for generating, visualizing and classifying molecular functional profiles
Various methods, systems, computer readable media, and graphical user interfaces (GUIs) are presented and described that enable a subject, doctor, or user to characterize or classify various types of cancer precisely. Additionally, described herein are methods, systems, computer readable media, and GUIs that enable more effective specification of treatment and improved outcomes for patients with identified types of cancer. Some embodiments of the methods, systems, computer readable media, and GUIs described herein comprise obtaining RNA expression data and/or whole exome sequencing (WES) data for a biological sample; determining a molecular-functional (MF) profile using the data; determining sets of visual characteristics for GUI elements using the data; generating a personalized GUI using the determined visual characteristics; and presenting the generated personalized GUI to a user. |
| US11322219B2 |
Memory system, integrated circuit system, and operation method of memory system
A memory system may include a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation, a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected, a second ECC generation circuit suitable for generating a second write ECC using the write data received from the memory controller, and generating the second write ECC using the write data whose error has been corrected by the first error correction circuit, when the detection of the error is noticed from the first error correction circuit, and one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC. |
| US11322216B1 |
Fuse array structure
A fuse array structure includes first and second active areas, first and second line contacts, first and second gate contacts and a common gate layer formed across the first and second active areas. The first line contact and the first gate contact are formed on the first active area. The second line contact and the second gate contact are formed on the second active area. The common gate layer is between the first active area and the first gate contact and is between the second active area and the second gate contact. The first active area, the first line contact, the first gate contact and the common gate layer form a first fuse. The second active area, the second line contact, the second gate contact and the common gate layer form a second fuse. |
| US11322207B1 |
Program method including multiple precharge steps for memory device
A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program operation. The program method including performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell. |
| US11322206B2 |
Storage device and operating method thereof
A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a memory controller. The non-volatile memory includes memory blocks each including a word lines. The memory controller determines a word line strength of each of the word lines, adjusts a state count of each of the word lines based on the word line strengths, and adjust a program parameter of each of the word lines to decrease a program time variation between the word lines. |
| US11322205B2 |
Non-volatile memory device and method for programming the same
A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level. |
| US11322201B2 |
Bit-line voltage generation circuit for a non-volatile memory device and corresponding method
An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element. |
| US11322200B1 |
Single-rail memory circuit with row-specific voltage supply lines and boost circuits
A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail. |
| US11322197B1 |
Power-gating techniques with buried metal
Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers. |
| US11322192B2 |
Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address. |
| US11322191B2 |
Charge extraction from ferroelectric memory cell
A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell. |
| US11322187B2 |
Protection circuit for memory in display panel and display panel
The present application discloses a protection circuit for a memory in a display panel and a display panel. The circuit comprises a timing controller, a memory, a power circuit, and a switching circuit. Instead of having a computer provide a write protection signal to the memory to limit data in the memory from being overwritten, the power circuit provides a stable and reliable write protection signal to the memory, and then the timing controller controls the switching circuit to be turned on for grounding the write protection signal of the memory only when an instruction to write data to the memory is received. |
| US11322185B2 |
Active random access memory
Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands. |
| US11322179B2 |
Hard disk fault handling method, array controller, and hard disk
A storage array includes a plurality of hard disks, each of the hard disks is divided into a plurality of chunks, and a plurality of chunks of different hard disks form a chunk group by using a redundancy algorithm. The storage array obtains fault information of a faulty area in a first hard disk, and determines a faulty chunk storing the lost data according to the fault information. The storage array recovers the data in the faulty chunk by using another chunk in a chunk group to which the faulty chunk belongs and stores the recovered data in a recovered chunk. The recovered chunk is located in a second hard disk which is not a hard disk for forming the chunk group. |
| US11322167B2 |
Auditory communication devices and related methods
Auditory communication devices and related methods are described herein. An example auditory communication device can include a microphone configured to collect acoustic energy and convert the collected acoustic energy into an audio signal, a processor operably coupled to the microphone, and a memory operably coupled to the processor. The processor can be configured to receive the audio signal from the microphone, create a time-frequency (T-F) representation of the audio signal, classify each of a plurality of T-F units into one of N discrete categories, and attenuate the T-F representation of the audio signal. A respective level of attenuation for each of the T-F units is determined by its respective classification. The processor can be further configured to create a synthesized signal from the attenuated T-F representation of the audio signal. |
| US11322166B2 |
Systems and methods for detecting and removing traceable identifying audio content from media content
Systems and methods are disclosed for detecting and removing traceable identifying audio content from electronic media content. One method includes: receiving, over a network, media content to be broadcast or distributed, the media content including audio data; determining whether the audio data of the media content includes traceable identifying audio content defined by an audio identifier; generating new audio data based on the audio data of the media content when an audio identifier is determined to be include in the audio data; removing audio data from the media content when the audio identifier is determined to be include in the audio data; adding the new audio data to the media content when the audio data is removed from the media content; and broadcasting or distributing the media content having the new audio data to one or more user devices. |
| US11322163B2 |
Audio encoding device, method and program, and audio decoding device, method and program
An audio packet error concealment system includes an encoding unit for encoding an audio signal consisting of a plurality of frames, and an auxiliary information encoding unit for estimating and encoding auxiliary information about a temporal change of power of the audio signal. The auxiliary information is used in packet loss concealment in decoding of the audio signal. The auxiliary information about the temporal change of power may contain a parameter that functionally approximates a plurality of powers of subframes shorter than one frame, or may contain information about a vector obtained by vector quantization of a plurality of powers of subframes shorter than one frame. |
| US11322162B2 |
Method and apparatus for resampling audio signal
A method, a computer-readable medium, and an apparatus for resampling audio signal are provided. The apparatus resamples the audio signal in order to preserve the audio playback quality when dealing with audio playback overrun and underrun problem. The apparatus may receive a data block of the audio signal including a first number of samples. For each sample of the first number of samples, the apparatus may slice a portion of the audio signal corresponding to the sample into a particular number of sub-samples. The apparatus may resample the data block of the audio signal into a second number of samples based on the first number of samples and the particular number of sub-samples associated with each sample of the first number of samples. The apparatus may play back the resampled data block of the audio signal via an electroacoustic device. |
| US11322157B2 |
Voice user interface
A method of speaker authentication comprises: receiving a speech signal; dividing the speech signal into segments; and, following each segment, obtaining an authentication score based on said segment and previously received segments, wherein the authentication score represents a probability that the speech signal comes from a specific registered speaker. In response to an authentication request, an authentication result is output based on the authentication score. |
| US11322156B2 |
Features search and selection techniques for speaker and speech recognition
With recent real-world applications of speaker and speech recognition systems, robust features for degraded speech have become a necessity. In general, degraded speech results in poor performance of any speech-based system. This poor performance can be attributed to feature extraction functionality of speech-based system which takes input speech file and converts it into a representation called as a feature. Embodiments of the present disclosure provide systems and methods that compute distance between each degraded speech feature extracted from an input speech signal with each clean speech feature comprised in a memory of the system to obtain set of matched clean speech features wherein at least a subset of cleaned speech features are dynamically selected based on a pre-defined threshold and the computed distance, thereby computing statistics for the dynamically selected clean speech features set for utilizing in at least one of a speech recognition system and a speaker recognition system. |
| US11322155B2 |
Method and apparatus for establishing voiceprint model, computer device, and storage medium
A method and apparatus for establishing a voiceprint model, a computer device, and a storage medium are described herein. The method includes: collecting speech acoustic features in a speech signal to form a plurality of cluster structures; calculating an average value and a standard deviation of the plurality of cluster structures and then performing coordinate transformation and activation function calculation to obtain a feature vector; and obtaining a voiceprint model based on the feature vector. |
| US11322149B2 |
Artificial intelligence apparatus for generating recipe information and method thereof
Disclosed herein are an artificial intelligence apparatus for generating recipe information including a learning processor configured to generate recipe text including at least one of cooking ingredient information or description text of cooking from cooking content, by providing the cooking content to a recipe text generation model, and a processor configured to generate recipe information of the cooking based on the recipe text, and a method of operating the same. |
| US11322148B2 |
Speaker attributed transcript generation
A computer implemented method processes audio streams recorded during a meeting by a plurality of distributed devices. Operations include performing speech recognition on each audio stream by a corresponding speech recognition system to generate utterance-level posterior probabilities as hypotheses for each audio stream, aligning the hypotheses and formatting them as word confusion networks with associated word-level posteriors probabilities, performing speaker recognition on each audio stream by a speaker identification algorithm that generates a stream of speaker-attributed word hypotheses, formatting speaker hypotheses with associated speaker label posterior probabilities and speaker-attributed hypotheses for each audio stream as a speaker confusion network, aligning the word and speaker confusion networks from all audio streams to each other to merge the posterior probabilities and align word and speaker labels, and creating a best speaker-attributed word transcript by selecting the sequence of word and speaker labels with the highest posterior probabilities. |
| US11322145B2 |
Voice processing device, meeting system, and voice processing method for preventing unintentional execution of command
A voice processing device includes a voice receiver that receives a voice, an imager, an image acquirer that acquires a captured image captured by the imager, an utterer identifier that identifies an utterer based on the voice received by the voice receiver and the captured image acquired by the image acquirer, a voice determiner that determines whether the voice is a specific word based on the voice received by the voice receiver and an image of the utterer identified by the utterer identifier, the image being included in the captured image, and a voice transmitter that switches a transmission destination of the voice received by the voice receiver based on a determination result by the voice determiner. |
| US11322143B2 |
Forming chatbot output based on user state
Techniques are described herein for chatbots to achieve greater social grace by tracking users' states and providing corresponding dialog. In various implementations, input may be received from a user at a client device operating a chatbot, e.g., during a first session between the user and the chatbot. The input may be semantically processed to determine a state expressed by the user to the chatbot. An indication of the state expressed by the user may be stored in memory for future use by the chatbot. It may then be determined, e.g., by the chatbot based on various signals, that a second session between the user and the chatbot is underway. In various implementations, as part of the second session, the chatbot may output a statement formed from a plurality of candidate words, phrases, and/or statements based on the stored indication of the state expressed by the user. |
| US11322142B2 |
Acoustic sensing-based text input method
Embodiments of the present application provide an acoustic sensing-based text input method, comprising: obtaining audio information corresponding to text to be input; dividing the audio information to obtain an audio segment for each letter to be recognized in the text to be input; sending to the server, a type of the text to be input, the audio segments for letters to be recognized, and arrangement of the audio segment for the letter to be recognized in the audio information; receiving input result returned by the server, and displaying, based on the input result, text information corresponding to the text to be input on the display screen of the mobile terminal. The method allows effective text input without relying on a display screen. |
| US11322141B2 |
Information processing device and information processing method
An information processing device includes a communication controller that performs communication control for receiving transmission data transmitted from a client, transmitting the transmission data to a first service providing server that performs a first service process, receiving a first service process result from the first service providing server, transmitting data according to the first service process result to a second service providing server that performs a second service process that is different from a first service, receiving a second service process result from the second service providing server, and transmitting the second service process result to the client. The first service process result is obtained by performing the first service process on the transmission data. The second service process result is obtained by performing the second service process on the data according to the first service process result. |
| US11322139B2 |
Presentation of indications with respect to questions of a communication session
According to one or more embodiments of the present disclosure, operations regarding providing indications with respect to questions of a communication session may include obtaining transcript data. The transcript data may include a transcription of audio of the communication session. The operations may further include obtaining multiple questions determined to be asked during the communication session. The operations may further include determining, based on an analysis of the transcript data during the communication session, which of the questions have been asked during the communication session. In addition, the operations may include causing, during the communication session, the device involved in the communication session to indicate which of the questions have been asked. |
| US11322133B2 |
Expressive text-to-speech utilizing contextual word-level style tokens
The present disclosure relates to systems, methods, and non-transitory computer-readable media that generate expressive audio for input texts based on a word-level analysis of the input text. For example, the disclosed systems can utilize a multi-channel neural network to generate a character-level feature vector and a word-level feature vector based on a plurality of characters of an input text and a plurality of words of the input text, respectively. In some embodiments, the disclosed systems utilize the neural network to generate the word-level feature vector based on contextual word-level style tokens that correspond to style features associated with the input text. Based on the character-level and word-level feature vectors, the disclosed systems can generate a context-based speech map. The disclosed systems can utilize the context-based speech map to generate expressive audio for the input text. |
| US11322132B2 |
Engine sound enhancement
Methods, systems, devices and apparatuses for a sound enhancement system. The sound enhancement system includes an airflow sensor. The airflow sensor is configured to measure an airflow into an engine of the vehicle. The sound enhancement system includes an electronic control unit. The electronic control unit is coupled to the airflow sensor. The electronic control unit is configured to determine a time of when to output an audio signal that mimics or enhances engine sound based on the airflow into the engine of the vehicle. The electronic control unit is configured to generate the audio signal based on the airflow into the engine of the vehicle. The sound enhancement system includes an audio device. The audio device is configured to output the audio signal based on the timing of when to output the audio signal. |
| US11322128B2 |
Virtual ambient zone creation in co-working spaces
An embodiment for creating a virtual ambient workstation is provided. The embodiment may include receiving a request to reserve an ambient space for a determined time period. The embodiment may also include identifying one or more workstations that are occupied by one or more other individuals. The embodiment may further include identifying combined vocal-fold sound patterns provided to a cognitive system based on the identified one or more workstations occupied by the one or more other individuals. The embodiment may also include evaluating data obtained from the one or more workstations and the combined vocal-fold sound patterns. The embodiment may further include generating an ambient noise remediation sound using an acoustic beam system. The embodiment may also include training the cognitive system. The embodiment may further include determining whether a level of ambient sound is sufficient and providing feedback to the cognitive system through machine learning. |
| US11322126B2 |
Broadband sparse acoustic absorber
A broadband sparse acoustic absorber includes a periodic array of spaced apart unit cells, generally having a lateral fill factor less than 0.5. Each unit cell includes a pair of joined, and inverted, Helmholtz resonators, having longitudinal and lateral neck portions that are perpendicular to one another. The longitudinal neck portions are typically covered and/or filled with acoustic absorbing material. Sound suppression systems include sound emitting devices that are at least partially surround by one or more such arrays. |
| US11322119B2 |
Semiconductor device
A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation. |
| US11322116B2 |
Display device and method for controlling brightness thereof
A display device is disclosed. The display device comprises: a storage configured to store output brightness information for each gradation according to brightness information of an image; and a processor configured to acquire target brightness corresponding to brightness information of an input image on the basis of the information stored in the storage, acquire a target light amount on the basis of a light amount of the input image, acquire a plurality of correction effects corresponding to a plurality of correction images by applying a plurality of gradation adjustment curves to the input image, acquire a gradation adjustment curve corresponding to the maximum correction effect among the plurality of correction effects, and adjust and output a gradation for each pixel of the input image on the basis of the acquired gradation adjustment curve. |
| US11322115B2 |
Display system, display control method, and program
A display system, a display control method for the display system and a non-transitory computer readable recording medium storing a program executable by a computer coupled to the display device are provided. The display system includes an HMD and a smartphone. The HMD includes an image display unit that transmits outside light and displays an image, and a DP illuminance sensor that detects an illuminance of the outside light. The smartphone includes an SP display control unit that adjusts, based on first illuminance information indicating a detection result of the DP illuminance sensor, a brightness of the image displayed by the image display unit, and an SP illuminance sensor that detects the illuminance. The SP display control unit can adjust the brightness of the image, based on second illuminance information indicating a detection result of the SP illuminance sensor. |
| US11322109B2 |
Narrow bezel panel display
Disclosed are embodiments of a narrow bezel display. The narrow bezel display has a structure in which output terminals of gate circuits are connected to jumping units through wires having a multistage path, thereby reducing the bezel size of a display. A dielectric layer may be disposed under the multistage path without placing another wire layer thereunder to prevent non-uniform capacitance between the wires and an underlying wire layer. Thus, a dimming phenomenon may be prevented during operation of the display or a short circuit may be prevented during an electrostatic test. |
| US11322107B2 |
Gate driver on array circuit driving system and display device
The present disclosure provides a gate driver on array (GOA) circuit driving system and a display panel. The GOA circuit driving system includes a power chip including a plurality of output pins, a plurality of filter units respectively corresponding to the plurality of output pins, and a GOA circuit including a plurality of signal input terminals respectively corresponding to the plurality of output pins, wherein each of the plurality of output pins is electrically connected to the corresponding signal input terminal through the corresponding filter unit, and each of the plurality of filter units is configured to filter an electrostatic voltage transmitted from the corresponding signal input terminal to the corresponding output pin, therefore solving a problem that the power chip cannot work normally due to a release of static electricity from the GOA circuit to the power chip during an ESD test. |
| US11322105B2 |
Active matrix substrate, liquid crystal display device, and organic EL display device
According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure. |
| US11322102B2 |
Display device and display method reproducing kinematic parallax for expressing high sense of realism
A display device and a display method which can reproduce kinematic parallax and express a high sense of realism without using image display means are provided. The display device includes an image display unit having a stripe structure having subpixels of a plurality of colors disposed so that subpixels of the same color are arranged in a first direction and enabling an observer to observe, through an aperture, an image formed by pixels, each pixel being constituted by the subpixels of a plurality of colors. The aperture has a shape in which areas of the subpixels of the plurality of colors which can be seen through the aperture are uniform, and in which a numerical aperture decreases along a second direction orthogonal to the first direction. A plurality of the apertures are provided so as not to overlap with each other. |
| US11322098B2 |
Display device
A display device including a first scan line, a first dot and a second dot each including first to fourth pixels sequentially connected to the first scan line, a data driver to supply data voltages to first to fourth output lines, and a switch unit to selectively connect the first to fourth output lines to the first to fourth pixels of the first dot or the second dot, in response to first and second control signals, and including first to fourth switches to selectively connect the first to fourth output lines to the first to fourth pixels of the first dot, respectively, in response to the first control signal, and fifth to eighth switches to selectively connect the first to fourth output lines to the third, the second, the first, and the fourth pixels of the second dot, respectively, in response to the second control signal. |
| US11322093B2 |
Pixel circuit and display apparatus having the same
A pixel circuit includes a first switching element including a control electrode connected to a first node, an input electrode which receives a first power voltage and an output electrode connected to a third node, a second switching element including a control electrode which receives a compensation gate signal, an input electrode connected to a second node and an output electrode connected to the third node, a third switching element including a control electrode which receives a write gate signal, an input electrode connected to the first node and an output electrode connected to the second node, a storage capacitor including a first electrode which receives an initialization voltage and a second electrode connected to the first node, a program capacitor which receives a data voltage and connected to the second node, and an organic light emitting element connected to the third node and which receives a second power voltage. |
| US11322086B2 |
Light emitting apparatus and display device
A light emitting apparatus and a display device are provided. The light emitting apparatus includes a light emitting unit and a pixel circuit. The pixel circuit is electrically connected to the light emitting unit. The pixel circuit includes a first driving transistor and a second driving transistor. The first driving transistor and the second driving transistor are configured to provide a first driving current and a second driving current to the light emitting unit at the same time, respectively. The first driving transistor includes a first gate terminal. The second driving transistor includes a second gate terminal. The first gate terminal and the second gate terminal are electrically connected to different nodes. The display device includes the light emitting apparatus. |
| US11322085B1 |
Pixel circuit and display panel
A pixel circuit is provided, which includes a switching unit, a driving unit, a first light-emitting control unit, a second light-emitting control unit, a light-emitting unit, a storage unit, a voltage dividing unit, a reset unit, and a compensation unit. In the pixel circuit provided by the embodiment of the disclosure, the compensation unit, which is not limited to a duty cycle of a switching unit, can independently compensate a threshold voltage of the driving unit during a duty cycle of the compensation signal, and is suitable for high frequency pixel driving. |
| US11322080B1 |
Image display system
An image display system includes a motion detection device that detects motion of an object in an input image; and a black data insertion device that inserts black data in one frame of the input image, thereby generating an output image. A duty cycle of the inserted black data in the frame is changed according to a result of the motion detection device. |
| US11322079B2 |
Display control method and apparatus, driving module and electronic device
A display control method includes: obtaining a delay instruction from a processor, in which the delay instruction includes a delay duration required to display a current image frame; determining a plurality of control pulses required to display the current image frame according to the delay duration, in which duty cycles of the plurality of the control pulses are identical; and when a synchronization signal is received, generating each of the plurality of the control pulses sequentially, in which the control pulse is configured to control an active-matrix organic light-emitting diode (AMOLED) display for dimming and displaying. |
| US11322077B1 |
Display device
Disclosed herein is a display device for preventing a luminance floatation phenomenon in a low grayscale region. The display device includes a display panel, an external input interface configured to receive an image signal from an external device, and a controller configured to adjust a gamma value when an input frequency of the image signal is less than an output frequency of the display panel and a variable refresh rate (VRR) function for changing the output frequency according to the input frequency is activated and to output the image signal to the display panel based on the adjusted gamma value. |
| US11322076B2 |
Pixel driving chip and driving method therefor, and display apparatus
A pixel driving chip and a driving method therefor, and a display apparatus. The pixel driving chip includes a data input circuit, a time selection circuit, and a current control circuit; the data input circuit is configured to receive display data, and partition the display data to obtain a data partition to which the display data belongs in M data partitions that are obtained on the basis of a display data range; the time selection circuit is configured to determine, according to the data partition to which the display data belongs, an output time length corresponding to the display data, and within the output time length, output the display data to the current control circuit; the current control circuit is configured to determine, according to the display data, a driving current flowing through a light emitting element corresponding to the display data. |
| US11322074B2 |
Data transmission method and device, display device
A data transmission method comprises: receiving and storing image data, wherein the image data comprises first data and second data, the first data is encrypted verification data, and the second data is original data; comparing the first data with the second data in stored image data; replacing the second data with the first data, if the second data and the first data are inconsistent. |
| US11322073B2 |
Method and apparatus for dynamically optimizing gamma correction for a high dynamic ratio image
An information handling system operating a learning dynamic gamma-correction optimization system may execute a method including identifying a combination of red, green, and blue subpixel component values for a plurality of pixels, and determining optimal red, green, and blue subpixel component values for the plurality of pixels by running a gamma correction algorithm using a gamma correction factor associated with a maximum gradient energy between the plurality of pixels. A training session for a neural network may include associating each of the red, green, and blue subpixel component values with one of a plurality of input signal node values and forward propagating the input signal node values through the neural network to output preliminary output signal node values using initial weighting values, comparing the optimal red, green, and blue subpixel component values with the preliminary output signal node values to determine error signals for each output value, determining an error signal associated with each node of the neural network by back propagating the determined error signals through the neural network, and determining a plurality of corrected weighting variables that would result in output of the optimal red, green, and blue subpixel component values. |
| US11322072B1 |
Display device
A display device is provided. The display device includes a panel, a memory, and a controller. The panel includes multiple pixels. The memory includes a first section and a second section. The memory stores an aging record table. Multiple brightness attenuation values recorded in the aging table are respectively divided into multiple first portion attenuation values and multiple second portion attenuation values. The first section stores the first portion attenuation values. The second section stores the second portion attenuation values. The controller includes an update circuit and a compensation circuit. The controller is coupled to the panel and the memory. The update circuit receives gray values displayed by the pixels to update the aging table. The compensation circuit reads the first portion attenuation values from the first section so as to perform an aging compensation on the pixels. |
| US11322066B2 |
Panel control circuit and display device including the same
A panel control circuit configured to control a display panel includes a plurality of pixels. The panel control circuit includes a controller configured to output an image data and a source driver, including an output circuit and an output control circuit, configured to generate data signals based on the image data. The controller is configured to output an output change signal for changing an output of the source driver. The output circuit is configured to output the data signals to the display panel, and the output control circuit is configured to output an adjusting current to the output circuit in a signal transition section of the output change signal. |
| US11322065B2 |
Display device preventing a common voltage drop and minimizing a bezel
A display device includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels and a common voltage line disposed in the display area; and a driving voltage line connected to each of the plurality of pixels, wherein a subset of the plurality of pixels overlaps the common voltage line in the display area in a plan view, and the external common voltage line and the common voltage line are connected to each other. |
| US11322060B2 |
Display device
A display device is proposed, the display device including a display panel including a display panel including a plurality of unit pixels including at least two sub-pixels that share a data line and are connected to different gate lines, a driving circuit supplying a scan signal and a data voltage to first and second sub-pixels included in the unit pixel and connected to different data lines, a sensing unit connected to the first and second sub-pixels throughs a sensing line to sense operating characteristics of the first and second sub-pixels, and a timing controller controlling the driving circuit and the sensing unit to obtain sensing data corresponding to the operating characteristics and compensate the data voltage based on the sensing data. |
| US11322054B2 |
Flexible cover window
A cover window is proposed. Particularly, a flexible cover window having improved visibility for a flexible display is proposed, the flexible cover window including: a first window made of glass and provided on an upper part of a first surface of the flexible display; a second window made of glass and provided on an upper part of a second surface of the flexible display; and a folding part provided between the first window and the second window by corresponding to a folding area of the display and filled with a transparent resin material, wherein a transparent resin layer is provided on a total surface of each of the first window and the second window by continuing to the folding part filled with the transparent resin material. |
| US11322052B2 |
Water air land tracks baggage identification locator computer product and methods
Disclosed is a method for locating, tracking and securing luggage. The method comprises steps of providing luggage tags configured with a luggage identifier code. The luggage identifier code is associated with a travel profile. The luggage tags further comprising one or more tamper-proof fasteners associated with one or more luggage tags. The luggage identifier code help to locate and track the luggage, while the tamper-proof fasteners help to secure the luggage. |
| US11322045B2 |
Urinating guiding accessory
A urinating guiding accessory (10), including: a projector (24), being disposed on a rear (64) top (66) of a toilet bowl (12), and directed towards a front internal wall (60) of the bowl (12), for projecting a guiding picture (14) onto the front internal wall (60) of the bowl (12); and a sensor (20), being disposed on the rear top of the toilet bowl (12) and directed outwards back (70) the toilet bowl (12) towards the user (50), for sensing the user's position, for controlling the guiding picture (14) accordingly. |
| US11322041B2 |
Augmented and mediated reality welding helmet systems
A welding helmet system is provided. The welding helmet system includes a protective shell and a welding display system. The welding display system is configured to be removably coupled to the protective shell. The welding display system is configured to receive data from a sensor, and to display a welding metric derived from the sensor via the image generation system. |
| US11322039B2 |
Apparatus to simulate driving a motorcycle and corresponding method
An apparatus to simulate driving a motorcycle includes a support base, a support body provided with a driving position on which a driver can take his place, and with command members configured to supply driving commands, a first movement unit connected to the support body and to the support base and configured to move the support body in space as a function of the driving signals. |
| US11322038B2 |
Simulator and method for simulating a use of a missile
A simulator for simulating a use of a missile of an attacking system is proposed. The simulator comprises: a storage device for storing of a terrain model of a battle terrain and target object models of target objects; a sensing unit for sensing and tracking a defined target object of the target objects in the battle terrain; a transmitting unit for transmitting a coded laser signal to the defined target object; a receiving unit for receiving a response signal transmitted by the defined target object; a providing unit for providing a target object model for the defined target object in dependence on at least type information of the received response signal; and a visual means associated with the missile for outputting a current visual representation of the battle terrain by means of the terrain model, the provided target object model and the location information. |
| US11322035B2 |
Information processing method, storage medium, information processing device, and information processing system
An information processing method includes: acquiring, by an information processing device, user's input information including a question sentence about a vehicle; and outputting, by the information processing device, an answer sentence according to a detail level, the detail level being an index indicating a detail degree of a sentence, and the detail level being determined based on a characteristic value of the question sentence. |
| US11322034B2 |
Method and system for generating operational data relating to aircraft movements in an airport infrastructure
The system for generating operational data includes an acquisition module of sets of aircraft movements tracking, an identification module which identifies a path for each aircraft from sets of movement tracking data, at least one runway and at least one parking zone, an identification module which identifies, for each path, phases associated with phase data, a generation module which generates sets of operational data comprising flight data, position data and phase data of each aircraft, and a transmission module which transmits these sets of operational data to a user system. |
| US11322033B2 |
Remote surface condition assessment
Method, apparatus, and computer program product are provided for assessing road surface condition. In some embodiments, candidate locations each forecast to have a dangerous road surface condition are determined, an optimized flight path is determined comprising a sequence of sites corresponding to the candidate locations, dispatch is made to a first site within the sequence, and a road surface condition at the first site is assessed using an onboard sensor (e.g., spectroradiometer). In some embodiments, a check for new information is performed before dispatch is made to a second site. In some embodiments, the candidate locations are determined using both a model forecast and data-mined locations considered hazardous. In some embodiments, the optimized flight path is determined using TSP optimization constrained by available flight time and prioritized by frequency of historical incident and severity of forecast road surface condition. |
| US11322030B2 |
Electric vehicle that distributes information between vehicles in a fleet
An electric vehicle is coupled to an communicates with the cloud. The cloud is coupled to and communicates with the electric vehicle. The cloud includes a server. The electric vehicle is configured to distribute information between electric vehicles in a fleet. The electric vehicle has cloud connectivity and a second local wireless communication to communication information to the fleet of electric vehicles. |
| US11322023B2 |
Driving support apparatus
A driving support apparatus is provided with: a recognizer configured to recognize a light of a traffic light that exists ahead of a host vehicle; and a controller configured to perform a deceleration support control if the host vehicle needs to be decelerated on the basis of the recognized light. The controller is configured to suppress a degree of the deceleration support control if the host vehicle needs to be decelerated on the basis of the recognized light and if the recognized light includes a light indicating permission to travel in a particular direction, in comparison with when the recognized light does not include the light indicating the permission to travel in the particular direction. |
| US11322022B2 |
Method for interacting traffic information, device and computer storage medium
The embodiments of the present disclosure provide a method and an apparatus for interacting traffic information, a device and a computer-readable storage medium. The method includes: in response to a first vehicle being about to overtake a second vehicle, sending overtake-preceding indicating information to the second vehicle; detecting whether the driver of the second vehicle makes a first response to the overtake-preceding indicating information; and in response to not detecting the first response made by the driver, sending additional indication information to the second vehicle. |
| US11322020B2 |
Synchronization signaling system
A synchronization signaling system, comprising a set of alert devices comprising at least one of a visual or audio output for producing an alert pattern, a master clock, a timing device capable of receiving updates from the master clock, a controller operably connected with the set of alert devices to control the set of alert devices. |
| US11322019B2 |
Emergency vehicle detection
Techniques for determining a direction of arrival of an emergency are discussed. A plurality of audio sensors of a vehicle can receive audio data associated with the vehicle. An audio sensor pair can be selected from the plurality of audio sensors to generate audio data representing sound in an environment of the vehicle. An angular spectrum associated with the audio sensor pair can be determined based on the audio data. A feature associated with the audio data can be determined based on the angular spectrum and/or the audio data itself. A direction of arrival (DoA) value associated with the sound may be determined based on the feature using a machine learned model. An emergency sound (e.g., a siren) can be detected in the audio data and a direction associated with the emergency relative to the vehicle can be determined based on the feature and the DoA value. |
| US11322014B2 |
Notification device, notification method, and program
A notification device is provided with: an abnormality estimation unit for estimating a state relating to an abnormality of a plant and a factor relating to the abnormality of the plant; an item specifying unit for specifying inspection items on the basis of the abnormality of the plant and the state relating to the factor relating to the abnormality of the plant estimated by the abnormality estimation unit; a notification unit for notifying of the inspection items specified by the item specifying unit; a stop-time item specifying unit for specifying the inspection items which should be checked at a time of a stop out of the inspection items specified by the item specifying unit; a check result acquisition unit for receiving a check result for the inspection items notified of by the notification unit; and a stop-time item output unit for outputting the inspection items which should be checked at the time of stop. |
| US11322013B2 |
Monitoring method of MES, monitoring device, and readable storage medium
A monitoring method of a manufacturing execution system (MES), a monitoring device, and a readable storage medium are provided. The monitoring method of the MES includes: reading log files of applications of an MES distributed on multiple servers and monitoring business operation information of the MES according to the log files. Based on this, this can make up for a gap in MES service monitoring and timely respond to abnormal production conditions. In addition, operators do not need to perform log query on each server. |
| US11322012B2 |
Remote cooking systems and methods
A remote temperature monitoring system includes a first unit operatively connected to one or more temperature sensors for sensing the temperature of one or more materials or food items being cooked or heated. The first unit transmits the sensed temperature to a second unit that is located remotely from the first unit during heating. The second unit is programmable with the desired temperature and/or heating parameters of the item. By monitoring the temperature status of the item over time, the system determines when the food has reached the desired temperature or degree of cooking, and notifies the user. |
| US11322010B1 |
Swimming pool monitoring
A monitor control unit that is configured to receive, from the electronic pool device, the sensor data, compare the sensor data to a threshold, based on comparing the sensor data to a threshold, determine that the sensor data exceeds the threshold, based on determining that the sensor data exceeds the threshold, provide an instruction to initiate the capture of image data by the camera of the electronic pool device, receive, from the camera of the electronic pool device, the image data, analyze the image data, based on analyzing the image data, identify a monitoring system action to perform, and perform the monitoring system action. |
| US11322008B2 |
Impact detection
An apparatus and methods for impact detection are disclosed. Example apparatus comprises a plurality of sensors. The apparatus is configured to determine whether a user is wearing an item in which the apparatus is comprised, and in response to a positive determination, operate the apparatus in an active operating mode. The active operating mode comprises operating one or more sensors in the plurality to generate data associated with motion of the user at a first sampling rate. |
| US11322007B2 |
Danger detector with a non-contact heat radiation sensor for detecting an open fire as well as to determine an ambient temperature
A danger detector, for example a flame detector, includes an alarm housing with an alarm cover. The housing part of the alarm cover is permeable to heat radiation in the central infrared range. A non-contact, optical heat radiation sensor which is sensitive to the incoming heat radiation and optically oriented to the housing part is arranged in the alarm housing. A processing unit for further processing a sensor signal emitted by the heat radiation sensor is mounted downstream of the heat radiation sensor. The processing unit is designed to monitor the signal emitted by the sensor with respect to significant fluctuations or flicker frequencies for open flames and to determine, based on a direct component of the signal emitted by the sensor, a temperature value for the ambient temperature in the surroundings of the danger detector. The heat radiation sensor may be a thermopile or a bolometer. |
| US11322006B2 |
Smoke detector
A smoke detector includes: a housing; a sensing chamber in the housing, wherein in the sensing chamber, a first light emitter and a first light receiver that are disposed at the periphery of the sensing chamber and facing a middle portion of the sensing chamber are included, a first baffle is included in the sensing chamber, the first baffle is disposed adjacent to the first light emitter and includes a baffle body and a branch portion, the baffle body extends from the periphery of the sensing chamber toward the middle portion, and the branch portion comprises a plurality of sub-baffles branching off the baffle body; and a circuit board electrically connected to the first light emitter and the first light receiver respectively. |
| US11322005B2 |
Portions of a security device system; methods of making and using them
A security device system including portions configured to have a combined state and a separated state. In the combined state, circuitry is configured to have an armed state and a not-armed state, and to trigger an alarm during a breach of the armed state. Depending on the embodiment, at least one of the portions, and in some embodiments more than one of the portions, participate in the armed and not-armed states. In some embodiments, the security device system includes an alarm device portion, a cradle portion, and a stratum portion. |
| US11322004B2 |
Method and a system for determining safe evacuation path/s
A system and a method for determining one or more safe evacuation paths in an event of fire. A method includes receiving measurements of parameter/s from one or more detectors. The one or more detectors detect parameter/s in an event of fire in a premises and are positioned at each of a plurality of evacuation paths inside the premises. The method further includes determining one or more safe evacuation paths from the plurality of evacuation paths inside the premises based on the measurements of the parameter/s. The method also includes displaying an indication of each of the one or more safe evacuation paths on an interface of a user device based on the determination. |
| US11322003B2 |
Information output device
This application relates to an information output device using a unit block module. Due to the use of the unit block module, apparatus of various sizes may be simply constructed and/or designed, durability and user convenience may be improved, waterproof properties are provided, power consumption is minimized, and an operation error of a driving module may be minimized. And, when a pin is driven down, the pin may be driven down more easily by the attraction of a magnetic material and a magnetic member. |
| US11322002B2 |
System for an alternative version of poker with redraw
A system and method of gaming includes, after collecting a wager, randomly selecting a first set of cards from a deck and displaying the first set of cards to the player along with a redraw offer (an amount that the player can pay to redraw the first set of cards). If the player accepts the offer, that amount is collected from the player and the player receives a new first set of cards from the deck. The play continues with randomly selecting a second set of cards from the deck and evaluating the best hand from the first set of cards combined with the second set of cards and determining a payout value by looking up that best hand in a payout table and awarding the payout value to the player. In some embodiments, the redraw offer is a fixed amount that is less than the wager amount. |
| US11321999B2 |
Crediting and debiting an electronic gaming machine in a casino environment
Devices, systems and methods are provided to enable casino operators to provide printed tangible items for patron uses, such as lottery tickets. Such embodiments accept tangible indicators of financial consideration from patrons, such as currency or tickets associated with certain verifiable values, such as valid and winning lottery tickets and other forms of consideration which a patron can provide to a casino in exchange for one or more points. |