| Document | Document Title |
|---|---|
| US10972249B1 |
System and method for data sampler drift compensation
A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine. |
| US10972246B2 |
Sounding reference signal (SRS) transmission protocol for an uplink pilot time slot
Certain aspects of the present disclosure provide apparatus and method for wireless communication. For example, the method generally includes receiving signaling indicating a first subframe configuration, the first subframe configuration corresponding to a subframe with a first number of symbols in an uplink pilot time slot (UpPTS), receiving signaling indicating a second configuration, the second configuration indicating a second number of symbols in the UpPTS, generating a frame comprising the UpPTS having the first number of symbols corresponding to the first subframe configuration, the UpPTS including one or more SRSs corresponding to the second configuration, and transmitting the frame comprising the UpPTS. |
| US10972244B2 |
Method and apparatus for low-overhead and low latency multi-beam operation
Systems, devices, and methods for low-overhead and low latency multi-beam operation in an advanced wireless communication system. A method of a user equipment (UE) for a multi-beam operation in a wireless communication system includes: receiving, from a base station (BS), a sounding reference signal (SRS) resource configuration; receiving, from the BS, a triggering message instructing the UE to transmit an SRS; receiving, from the BS, a configuration for a transmission configuration indicator (TCI) state that includes an identification (ID) indicating the SRS resource configuration; identifying a set of resources to transmit the SRS; and transmitting, to the BS over an uplink channel, the SRS based on the SRS resource configuration with a spatial domain transmission filter. The UE receives a downlink transmission from the BS with a spatial domain receive filter that is determined according to the ID included in the TCI state that is indicated for the downlink transmission. |
| US10972243B2 |
Mobile station and reception method
Provided is a radio communication device which can separate propagation paths of antenna ports and improve a channel estimation accuracy even when using virtual antennas. The device includes: a mapping unit which maps a data signal after modulation to a virtual antenna and a virtual antenna; a phase inversion unit which inverts the phase of S0 transmitted from an antenna port in synchronization with a phase inversion unit between the odd-number slot and the even-number slot; the phase inversion unit which inverts the phase of R0 transmitted from the antenna port; a phase inversion unit which inverts the phase of S1 transmitted from an antenna port in synchronization with a phase inversion unit; and the phase inversion unit which inverts the phase of R1 transmitted from an antenna port. |
| US10972242B2 |
Method for transmitting uplink and wireless device using same
A method and user equipment for performing an uplink transmission in a wireless communication system, are discussed. The method includes allocating transmission power to a first uplink transmission and a second uplink transmission when a total power in a transmission period including at least one or more OFDM symbols exceeds maximum power, wherein each of the first and second uplink transmissions is one of physical uplink shared channel (PUSCH) transmission, physical uplink control channel (PUCCH) transmission, physical random access channel (PRACH) transmission and sounding reference signal (SRS) transmission; and performing the first and second uplink transmissions according to the allocated transmission power, wherein the allocation of the transmission power is performed according to priority information. |
| US10972238B2 |
System and method for phase tracking reference signal (PT-RS) multiplexing
Technology for a next generation node B (gNB), operable to use phase tracking reference signals (PT-RS) is disclosed. The gNB can identify a modulation and coding 5 scheme (MCS) for the UE for a bandwidth part (BWP) with a subcarrier spacing (SCS). The gNB can select a time density of the PT-RS based on the MCS. The gNB can select a frequency density of the PT-RS based on an allocated bandwidth in the BWP. The gNB can encode the time density and the frequency density, for the PT-RS for transmission to the UE in higher layer signaling. |
| US10972236B2 |
Signal transmission method, signal reception method, apparatus, and system in wireless communication
This application relates to the field of wireless communications technologies, and in particular, to a data processing method, apparatus, and system. This application provides a data processing method. A transmit device uses a sequence to carry data and a reference signal. The transmit device carries the two channels of data on an odd element and an even element of the sequence, respectively. The transmit device successively maps the sequence that carries the two channels of data to allocated subcarriers, and then sends the data in an orthogonal frequency division multiplexing (OFDM) manner. This application is intended to decrease cubic metric (CM)/peak-to-average ratio of a transmitted signal of an orthogonal frequency division multiplexing OFDM system through sequence design and mapping of the two channels of data to subcarriers, thereby improving link quality of an entire transmission system. |
| US10972234B2 |
Devices, methods and computer programs for wireless communication with multiple-access
A network node device includes a radio transceiver configured to receive a data sequence from a plurality of user equipments (UEs) over first and second sets of resource elements, wherein the first set of resource elements is mapped non-orthogonally and the second set is mapped orthogonally. The network node device further comprises a processor configured to determine channel vectors based at least in part on the data sequence received over the first set of resource elements or over the second set of resource elements, and to utilize the data sequence as received over the second set of resource elements to associate the determined channel vectors with each of the plurality of UEs. |
| US10972233B2 |
Method and apparatus for sequence hopping in single carrier frequency division multiple access (SC-FDMA) communication systems
Methods and apparatuses are provided for transmitting and receiving a signal using a sequence in a wireless communication system. The method includes receiving, from a base station, information indicating whether sequence hopping is applied or not; transmitting, to the base station, the signal using a first sequence if a number of resource blocks allocated to the user equipment is less than a predetermined value; and transmitting, to the base station, the signal using a second sequence to which the sequence hopping is applied based on the received information if the number of the resource blocks allocated to the user equipment is greater than or equal to the predetermined value. The sequence hopping is performed using a pseudo-random function, and the sequence hopping is performed in a unit of a slot. |
| US10972231B2 |
Wireless communication terminal, base station device, resource allocation method
A radio communication terminal that increases the ACK/NACK resource utilization efficiency while preventing ACK/NACK collision, and that causes no unnecessary reduction of the PUSCH band in a system that transmits E-PDCCH control information. The radio communication terminal adopts a configuration including a receiving section that receives a control signal including an ACK/NACK index via an enhanced physical downlink control channel (E-PDCCH) transmitted using one configuration from among one or a plurality of configuration candidates, a control section that selects a resource to be used for an ACK/NACK signal of downlink data from among specified resources specified beforehand based on E-PDCCH configuration information used for transmission or reception of the E-PDCCH and the ACK/NACK index, and a transmitting section that transmits the ACK/NACK signal using the selected specified resource. |
| US10972230B2 |
Method and apparatus for sending feedback using two-stage uplink scheduling
A method comprises receiving in a first subframe of a burst from a base station a downlink transport block for which an acknowledgement is required. A first uplink channel in which an acknowledgement of said transport block to be provided is prepared. The first uplink channel is independent of transmission information. The first prepared uplink channel is transmitted with the acknowledgement in a later burst. |
| US10972228B2 |
Base station device, user equipment, wireless communication system, and communication method
A base station device including: a transmitter configured to transmit a transport block that includes a plurality of code block groups; and a receiver configured to receive a confirmation signal which indicates that one or more code block groups of the plurality of code block groups has not been successfully received, wherein the transmitter transmits a control signal when the receiver receives the confirmation signal, and the control signal comprises first information that indicates the one or more code block groups to be retransmitted and second information that indicates data is combined with the one or more code block groups being retransmitted and earlier received one or more code block groups stored in a buffer. |
| US10972224B2 |
Base station apparatus, terminal apparatus, and communication method thereof
To provide a base station apparatus, a terminal apparatus, and a communication method capable of efficiently performing retransmission control for small size data in grant-free multiple access where the base station apparatus accommodates a large number of terminal apparatuses. The base station apparatus for communicating with multiple terminal apparatuses, the base station apparatus including a receiver configured to receive an identification signal identifying a terminal apparatus having transmitted uplink data and the uplink data, and a transmitter configured to transmit a delivery confirmation signal for the uplink data, wherein the delivery confirmation signal includes a bundled delivery confirmation signal for the uplink data received on an identical time resource and an identical frequency resource, and a delivery confirmation signal for each terminal apparatus, the bundled delivery confirmation signal is associated with a parameter shared by the terminal apparatuses having transmitted the uplink data received on the identical time resource and the identical frequency resource, and the delivery confirmation signal for each terminal apparatus is associated with a parameter specific to the terminal apparatus. |
| US10972219B2 |
LDPC interleaver design for improved error floor performance
Certain aspects of the present disclosure provide techniques and apparatus for low density parity check (LDPC) interleaving with improved error floor performance. A method for wireless communications that may be provided by a transmitting device is provided. The method generally includes encoding one or more information bits using a LDPC code to produce a coded bit sequence comprising systematic bits and parity bits. The transmitting device stores the coded bit sequence in a circular buffer. The transmitting device performs rate matching on the coded bit sequence. The rate matching includes interleaving the parity bits with a partial interleaver and interleaving the systematic bits and interleaved parity bits with a systematic bit priority mapping (SBPM) interleaver. The transmitting device maps the SBPM interleaved bit sequence to constellation points according to a modulation scheme and transmits the modulated bit sequence. |
| US10972218B2 |
Apparatus and method for controlling receiving data
An electronic device and a method of operating the electronic device in a wireless communication system are provided. The method includes determining whether to perform a partial decoding or a normal decoding based on a channel quality; if partial decoding is performed, decoding partial data received by a transceiver from a second electronic device during a part one TTI; when the decoding of the partial data succeeds, performing at least one complementary decoding until a decoding success count reaches a decoding threshold; and when the decoding success count reaches the decoding threshold, outputting a decoding result for the at least one complementary decoding; and if normal decoding is performed, decoding all data of the one TTI and outputting a result. One of the at least one complementary decoding comprises decoding previous data, and additional data received by the transceiver during an additional part of the one TTI, after the previous data. |
| US10972217B2 |
Scheduling for low-density parity-check codes
Methods, systems, and devices for wireless communications are described. Efficient low-density parity-check (LDPC) scheduling of layered decoding may include receiving a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes, applying a first number of decoding iterations to decoding the message, applying a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, and decoding the message through completion of both the first number of decoding iterations and the second number of decoding iterations. In some cases, only a portion of the number of check nodes is decoded during each of the first number of decoding iterations and all of the number of check nodes are decoded during each of the second number of decoding iterations. |
| US10972213B2 |
Simultaneous transmission of periodic CQI and ACK/NACK
Methods and systems for simultaneous transmission of periodic Channel Quality Indicator (CQI) and Hybrid Automatic Repeat Request (HARQ) Acknowledgement (ACK)/Negative Acknowledgement (NACK) are presented. According to one aspect, a method of operation of a node comprises configuring the node to have two differently sized sets of resources. The method includes determining that the node needs to report feedback, the feedback comprising at least a periodic CQI feedback. The method includes, upon determining that the node needs to report the feedback, selecting one of the differently sized sets of resources to be used for reporting the feedback, wherein the larger set is selected when the node needs to also report a HARQ feedback, and wherein the smaller set is selected when the node does not need to also report a HARQ feedback. The method includes reporting the feedback on the selected set of resources. |
| US10972212B2 |
Quality parameter transmission method, terminal, and network side device
A quality parameter transmission method includes: sending, by the network side device, a first request message to the terminal, where the first request message is used to request a quality parameter related to user experience of a preset service; and after receiving the first request message from the network side device, sending, by the terminal, the quality parameter to the network side device. The network side device obtains, from the terminal, the quality parameter related to user experience of the preset service, and therefore can evaluate network operation quality by using the quality parameter, to facilitate network optimization, provide better network quality for the terminal, and improve user experience. |
| US10972211B2 |
Support for multiple coding schemes
A method of wireless communication of a user equipment (UE) includes communicating with a base station using a baseline channel code. The UE indicates to the base station, using the baseline channel code, support for an additional channel code that is different than the baseline channel code. The UE receives, from the base station, an indication to operate using the additional channel code. Then, the UE receives a first transmission on first set of resources and a second transmission on a second set of resources from the base station, the first transmission being encoded with the baseline channel code and the second transmission being encoded with the additional channel code. |
| US10972210B2 |
Enhanced channel interleaving for optimized data throughput
In a transmission scheme wherein multi-slot packet transmissions to a remote station can be terminated by an acknowledgment signal from the remote station, code symbols can be efficiently packed over the multi-slot packet so that the remote station can easily decode the data payload of the multi-slot packet by decoding only a portion of the multi-slot packet. Hence, the remote station can signal for the early termination of the multi-slot packet transmission, which thereby increases the data throughput of the system. |
| US10972198B2 |
Device and method for receiving and measuring wireless signal
The disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The disclosure is to receive and measure a wireless signal, and provides a device for measuring a wireless signal. The device includes a first antenna set including a plurality of antennas having adjustable oriented directions, a second antenna set including a plurality of antennas having fixed oriented directions, and at least one processor configured to receive and analyze wireless signals by using the first antenna set and the second antenna set, wherein the at least one processor may adjust the oriented directions of the plurality of antennas included in the first antenna set, receive the wireless signals by using the first antenna set and the second antenna set, and control to analyze the wireless signals. |
| US10972194B2 |
Proximate communication with a target device
Systems and methods may use proximate communication to retrieve information pertaining to a target device. In one example, the method may include detecting the target device within a vicinity of a user device, receiving an information request response communication including information pertaining to the target device, and receiving an operation request response communication including information pertaining to a performed operation. |
| US10972190B2 |
Systems and methods for modeling quantum structure and behavior
Systems and methods of modeling the structure and behavior of the quantum continuum based on geometrical principles are provided. In some embodiments, systems and methods of modeling quantum structure and behavior may include modeling a region of space as a three-dimensional projection of a field of N-dimensional hard-spheres, modeling a stable particle within the region of space as a locally stably packed set of hard-spheres, defining an energy subspace comprising one or more additional dimensions, and modeling an energy of the stable particle as an amount of hard-sphere geometry shifted out of the three spatial dimensions into the energy subspace sufficient for the set of hard-spheres to pack stably. Systems and methods for modeling virtual particles and performing quantum communication are also described. |
| US10972189B2 |
Long-haul high rate quantum key distribution
Multiple bit values can be encoded on a single photon in a quantum key distribution (QKD) system using a plurality of sidebands of an optical carrier frequency. Computational and conjugate bases can be defined, and photons decoded based on a selected state from either basis. If n sidebands are available, as many as log2n bits can be encoded on a single photon. Errors in detected bit values due to selection of an incorrect basis state or other errors can be at least partially corrected by bit distillation to identity bit strings for which a transmitter and a receiver record the same values, without insecure transmission of these values. |
| US10972175B2 |
Performance-based link management communications
Disclosed herein are system, method, and computer program product embodiments for utilizing parallel links to improve sub-network availability and latency performance for ATC traffic. An embodiment operates by receiving a generated message. The type of the generated message is determined, where the type is an air traffic control message or a non-air traffic control message. Based on the type of message, communication links are selected, where the communication links include parallel transmission links or a serial link. The method continues by copying the generated message and transmitting the copied message using the selected communication links. The method waits to receive an acknowledgement indicating receipt of the transmitted message. Upon identifying an acknowledgement, any of the copied messages not yet retransmitted are deleted. |
| US10972172B2 |
Method for fast beam sweeping and device discovery in 5G millimeter wave and upper centimeter-wave systems
A method of performing a beam alignment procedure in a mmW or upper centimeter wave system, usable for performing initial access (IA) for user equipment (UE) to establish a connection with a base station (BS) is disclosed. A UE receives a signal from a base station, divides a search space into a plurality of angular zones, locates a direction of peak received strength within each zone, and forms a beam along the direction of peak overall signal strength. The number of angular zones is chosen such that the probability that each zone contains one peak of signal strength exceeds some threshold. The method is applicable in mmW and upper cmW bands in both BS to UE and device-to-device (D2D) communications. |
| US10972164B2 |
Method and device for transmitting and receiving feedback signal in wireless communication system
A method, provided by the present disclosure, of transmitting a reference signal by means of a base station in a wireless communication system using a plurality of antenna ports comprises the steps of: mapping wireless resources, for transmitting a reference signal, to a plurality of antenna ports for transmitting the reference signal; and using the wireless resources and transmitting the reference signal to a terminal through the mapped antenna ports. The step of mapping to the antenna ports is characterized by being executed on the basis of a combination of a first mapping pattern between the wireless resources and the antenna ports and a second mapping pattern between the wireless resources and the antenna ports. |
| US10972161B2 |
Method and apparatus for explicit CSI reporting in advanced wireless communication systems
A method for a channel state information (CSI) feedback comprises receiving CSI feedback configuration information for the CSI feedback including a spatial channel information indicator based on a linear combination (LC) codebook, wherein the spatial channel information comprises at least one of a downlink channel matrix, a covariance matrix of the downlink channel matrix, or at least one eigenvector of the covariance matrix of the downlink channel matrix; deriving the spatial channel information indicator using the LC codebook that indicates a weighted linear combination of a plurality of basis vectors or a plurality of basis matrices as a representation of at least one of a downlink channel matrix, a covariance matrix of the downlink channel matrix, or at least one eigenvector of the covariance matrix of the downlink channel matrix; and transmitting over an uplink channel, the CSI feedback including the spatial channel information indicator. |
| US10972158B2 |
Distributed FD-MIMO: cellular evolution for 5G and beyond
A method for a user equipment (UE) is provided. The method comprises receiving, from a base station (BS), information via a dynamic signaling comprising at least one of a medium access control channel element (MAC CE) or downlink control information (DCI) that includes information for a set of channel state information-reference signal (CSI-RS); identifying CSI-RS resources each of which comprises a set of antenna ports based on the information; and measuring CSI using an aggregation of the CSI-RS resources, wherein an energy per resource element (EPRE) ratio between a CSI-RS and a physical downlink shared channel (PDSCH) is configured in the information to each of the CSI-RS resources comprising the aggregated CSI-RS resources. |
| US10972156B2 |
Measurement reporting in radio access networks for MU-MIMO operation
There is disclosed a method of operating an informing radio node in a radio access network. The method comprises transmitting beam reception information, the beam reception information being based on measurements performed on beams of a set of beams. The beam reception information indicates one or more beams of the set of beams to belong to a first subset of the set of beams, the first subset comprising weakly received beams.The disclosure also pertains to related devices and methods. |
| US10972149B2 |
Surface wave interference reduction
The present disclosure relates to a surface wave communication system comprising a surface wave conduit and being adapted for transmitting electromagnetic surface wave signals via the surface wave conduit. The surface wave communication system further comprises at least one interference cancelling system, where each interference cancelling system comprises an antenna arrangement and a cancelling device. The cancelling device is adapted to: input antenna signal components from the corresponding antenna arrangement in at least one corresponding antenna branch, input conduit signal components from the surface wave conduit in a conduit branch, to remove adapted antenna signal components from the conduit signal components such that recovered conduit signal components are obtained, and to output the recovered conduit signal components. |
| US10972141B2 |
Method for estimating arrival time based on noise cancellation
A method for estimating arrival time based on noise cancellation includes transmitting, with a transmit terminal, an ultra-wideband pulse sequence; performing power sampling on a received ultra-wideband signal; averaging a power sampling sequence; carrying out a calculation to obtain a noise mean vector; using a sum-of-rank method to obtain a rank of a power mean column vector; setting a decision threshold; and performing time-of-arrival (TOA) estimation. |
| US10972139B1 |
Wireless devices and systems including examples of compensating power amplifier noise with neural networks or recurrent neural networks
Examples described herein include methods, devices, and systems which may compensate input data for nonlinear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a recurrent neural network (RNN). The RNN may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate filter coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to the RNN. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage. |
| US10972136B2 |
Polar code rate matching method and apparatus
The embodiments of the application provides a polar code rate matching method and apparatus. The method includes: obtaining, by a communications device, to-be-encoded information; determining, by the communications device, a to-be-used rate matching manner based on the code rate, a code rate threshold, a target code length, and a target code length threshold, where the rate matching manner is a puncturing manner or a shortening manner; and rate matching, by the communications device based on the determined rate matching manner, a polar code of the to-be-encoded information. |
| US10972134B2 |
Low-density parity-check (LPDC) coded modulation (LCM) with alignment of LDPC codewords and discrete multi-tone (DMT) symbol boundaries
A system for a digital subscriber line (DSL) network with a DSL interface can operate with processing circuitry that can generate symbols in multicarrier communications with codewords for modulation of a parity check. The codewords can be aligned with symbol boundaries of the symbols in a continuous transmission of the multi-carrier communications. The processing circuitry reduces a number of parity bits by puncturing and a number of data bits for shortening of the codewords so that a codeword boundary is aligned with a symbol boundary for one or more symbols, or a transmission frame of symbols. |
| US10972129B2 |
Low density parity check code decoder and method for decoding LDPC code
A check node update processor of the low density parity check (LDPC) code decoder includes: an approximate first minimum (AFM) condition check unit which checks whether a predetermined specific condition is satisfied, and a check node determining unit which sets an approximate minimum value as a size of an entire check node output when it is determined that the specific condition is satisfied as a checking result in the AFM condition check unit and calculates a first minimum value as a true minimum value and sets a second minimum value as an approximate minimum value when it is determined that the specific condition is not satisfied to determine a size of the check node output. |
| US10972126B2 |
Data compression and storage
A data compression method comprises encoding groups of data items by generating, for each group, header data comprising h-bits and a plurality of body portions each comprising b-bits and each body portion corresponding to a data item in the group. The value of h may be fixed for all groups and the value of b is fixed within a group, wherein the header data for a group comprises an indication of b for the body portions of that group. In various examples, b=0 and so there are no body portions. In examples where b is not equal to zero, a body data field is generated for each group by interleaving bits from the body portions corresponding to data items in the group. The resultant encoded data block, comprising the header data and, where present, the body data field can be written to memory. |
| US10972124B2 |
Remote downhole signal decoder and method for signal re-transmission
A decoding device is used to securely send corresponding data gathered from multiple underground sources to multiple users. The device comprises a signal receiving port connected to multiple bandwidth filters and further connected to internet access points that are assigned to end users for secure data access. The invention facilitates allowing the signal and data being transmitted through the formation of the earth to reach end users located nearby and significant distances away from the source of the transmission. A system and method utilizing the decoding device is provided. |
| US10972116B2 |
Time to digital converter and A/D conversion circuit
There is provided a time to digital converter to which a reference signal and a trigger signal are input, the time to digital converter outputting a time digital value corresponding to a time event of the trigger signal with respect to the reference signal, the time to digital converter including a state transition section configured to output state information indicating an internal state and start, based on the trigger signal, state transition in which the internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with the reference signal, the state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information acquired by the transition-state acquiring section, the time digital value corresponding to a number of times of transition of the internal state. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state reverts to the first internal state is longer than a cycle in which the state information held by the transition-state acquiring section is updated. |
| US10972109B2 |
Sub sampling phase locked loop (SSPLL) with wide frequency acquisition
A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage. |
| US10972107B2 |
Serial data receiver with sampling clock skew compensation
An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples. |
| US10972103B2 |
Multiplier-accumulator circuitry, and processing pipeline including same
An integrated circuit comprising a plurality of multiply-accumulator circuitry, configurable in a concatenation architecture, to perform a plurality of multiply and accumulate operations, wherein the plurality of multiply-accumulator circuitry is organized into a plurality of groups, including a first group of multiply-accumulator circuitry and a second group of multiply-accumulator circuitry, wherein each group includes: a plurality of MAC circuits, each including a multiplier to multiply data by a multiplier weight data and generate a product data, and an accumulator to add input data and the product data to generate sum data, and wherein the plurality of MAC circuits of each group is organized in at least one row and connected in series to perform a plurality of concatenated multiply and accumulate operations. The integrated circuit also includes configurable interface circuitry to connect and/or disconnect the plurality of MAC circuits of the first and second groups of multiply-accumulator circuitry. |
| US10972094B1 |
Operating circuit and control method
An operating circuit including a system circuit and a power control circuit is provided. The system circuit operates according to the voltage of the node. The power control circuit includes a first connection port, a second connection port, a first always-on switch, a second always-on switch, a first current limiter, and a second current limiter. The first connection port is configured to receive first power provided by a first external device. The second connection port is configured to receive second power provided by a second external device. The first always-on switch is coupled to the first connection port to transmit the first power. The second always-on switch is coupled to the second connection port to transmit the second power. The first current limiter is coupled between the first always-on switch and the node. The second current limiter is coupled between the second always-on switch and the node. |
| US10972090B1 |
Output stage circuit for transmitting data via bus
An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON. |
| US10972089B2 |
Semiconductor device
A semiconductor device includes a power semiconductor switching element including a characteristic test terminal, and a control circuit configured to control an operation of the power semiconductor switching element. The power semiconductor switching element and the control circuit are formed in a same chip. The control circuit includes a gate voltage generation circuit configured to generate a current limit gate voltage for restricting an overcurrent flowing in the power semiconductor switching element in a desired range when an abnormality occurs, based on a characteristic of the power semiconductor switching element which is measured in advance by applying a voltage to the characteristic test terminal. |
| US10972088B1 |
Temperature detection of a power switch based on paired measurements of current and voltage
This disclosure is directed to circuits and techniques for detecting or responding to temperature of a power switch based on paired measurements of current and voltage. A driver circuit for a power switch may be configured to perform a current measurement and a voltage measurement associated with a temperature-dependent circuit element and control the power switch based at least in part on the current measurement and the voltage measurement. In some examples, the current and voltage measurements may be used to determine the temperature of the power switch. |
| US10972087B2 |
System and method for limting currents in a power distribution system
An apparatus and method for controlling voltage sharing between a set of switching components can include applying power from a current source with a positive lead and a negative lead, closing the set of switching components to connect power from the current source to an electrical load, detecting a set of voltage values for the set of switching components, and controlling a current limiting function of at least one of the set of switching components. |
| US10972086B2 |
Comparator low power response
In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal. |
| US10972084B1 |
Circuit and methods for transferring a phase value between circuits clocked by non-synchronous clock signals
A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output. |
| US10972082B2 |
Method and apparatus for cross correlation
A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions. |
| US10972077B2 |
System and method of duplicate circuit block swapping for noise reduction
An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits. |
| US10972069B2 |
Radio-frequency module
A substrate includes a conductor unit at constant potential. A first communication unit transmits a first signal in a first frequency band. A second communication unit performs at least one of transmission of a second signal in a second frequency band higher than the first frequency band and at least partially overlapping a harmonic of the first signal, or reception of a third signal in the second frequency band. First and second ends of a conductive wire are connected to the conductor unit. The second communication unit includes at least one of a transmitting filter that passes the second signal, a receiving filter that passes the third signal, or a low-noise amplifier that amplifies the third signal. The conductive wire is located between a first power amplifier of the first communication unit, and at least one of the transmitting filter, receiving filter, or low-noise amplifier of the second communication unit. |
| US10972067B2 |
Filter and multiplexer
A filter includes: a substrate; input and output terminals located on the substrate; a resonant circuit located in a series pathway between the input and output terminals; a first component including a first inductor, which is electrically connected between a first node in the series pathway and a ground, and mounted in a first region on the substrate; a second component including a second inductor, which is electrically connected between a second node different from the first node in the series pathway and a ground, and mounted in a second region different from the first region on the substrate; and a third component including an acoustic wave resonator, which is electrically connected between a third node between the first and second nodes in the series pathway and a ground, and mounted in a third region between the first and second regions on the substrate. |
| US10972065B2 |
Systems and methods for identifying and remediating sound masking
Some embodiments of the invention are directed to enabling a user to easily identify the frequency range(s) at which sound masking occurs, and addressing the masking, if desired. In this respect, the extent to which a first stem is masked by one or more second stems in a frequency range may depend not only on the absolute value of the energy of the second stem(s) in the frequency range, but also on the relative energy of the first stem with respect to the second stem(s) in the frequency range. Accordingly, some embodiments are directed to modeling sound masking as a function of the energy of the stem being masked and of the relative energy of the masked stem with respect to the masking stem(s) in the frequency range, such as by modeling sound masking as loudness loss, a value indicative of the reduction in loudness of a stem of interest caused by the presence of one or more other stems in a frequency range. |
| US10972062B2 |
Class-D amplifier and method
A class-D amplifier includes an analog-to-digital converter (ADC) configured to generate a first digital signal based on an analog input signal and a feedback signal received at an input node. A loop filter is configured to modify the first digital signal by moving an error of the ADC out of a predetermined frequency band, and a compensation filter is configured to further modify the first digital signal by introducing one or more poles or zeros, thereby generating a second digital signal. An output circuit is configured to generate an output signal at an output node based on the second digital signal, and the feedback signal is generated from the output signal. |
| US10972060B2 |
Radio frequency power amplifier and power amplifier module
In a radio frequency power amplifier, a semiconductor chip includes at least one first transistor amplifying a radio frequency signal, a first external-connection conductive member connected to the first transistor, a bias circuit including a second transistor that applies a bias voltage to the first transistor, and a second external-connection conductive member connected to the second transistor. The second external-connection conductive member at least partially overlaps with the second transistor when viewed in plan. |
| US10972058B2 |
Photodetector circuit
In accordance with aspects of the present invention, embodiments of a photodiode circuit. A photodiode circuit according to some embodiments includes a transimpedance amplifier; a resistor coupled across the transimpedance amplifier; and an amplifier stage coupled to receive an output from the transimpedance amplifier, wherein the photodiode circuit provides dynamic range across a current range of the photodiode circuit. In some embodiments, the transimpedance amplifier includes a receive signal strength indicator that provides a DC current signal to a tail of a first amplifier stage, the tail providing a current that is adaptively related to the DC current. In some embodiments, the resistor is a shielded resistor. In some embodiments, the adaptive current sink includes a plurality of switchable parallel current sinks. |
| US10972055B2 |
Integrated doherty power amplifier
Integrated Doherty power amplifiers are provided herein. In certain implementations, a Doherty power amplifier includes a carrier amplification stage that generates a carrier signal, a peaking amplification stage that generates a peaking signal, and an antenna structure that combines the carrier signal and the peaking signal. The antenna structure radiates a transmit wave in which the carrier signal and the peaking signal are combined with a phase shift. |
| US10972053B2 |
Doherty power amplifier with integrated second harmonic injection
Examples disclosed herein relate to a Doherty Power Amplifier (“DPA”) with integrated second harmonic injection. The DPA includes an amplifier circuit having a carrier amplifier and a peaking amplifier, and a combiner network coupled to the amplifier circuit, the combiner network having a plurality of transmission lines and a LC resonant circuit to inject a second harmonic from the carrier amplifier into the peaking amplifier. |
| US10972048B2 |
Photovoltaic module
The present invention is notably directed to a photovoltaic module, or PV module, comprising an array of photovoltaic cells, or PV cells, and electrical interconnects. The array of PV cells comprises N portions, N≥2, where the portions comprise, each, disjoint sets of PV cells of the array. The electrical interconnects connect the PV cells and the N portions of the array so as for PV cells within each of said portions to be electrically connected in parallel and the N portions to be connected in series. The PV cells and the portions are connected, via said interconnects, so to output an electrical current, in operation. The electrical interconnects are otherwise configured to provide electrical signals from each of the N portions. The invention is further directed to related systems and methods of fabrication and operation. |
| US10972046B2 |
Circuits and methods for controlling current in a parallel-connected array
A solar device system includes one or more solar devices shingled into an array of solar devices. Each solar device includes one or more current generation cells configured to generate electric current, a plurality of current buses, and a control circuit configured to distribute the generated electric current to the plurality of current buses, and route the generated electric current to an adjacent solar device. Additionally, the solar device system includes an array collector electrically connected to the one or more solar devices, the array collector being configured to collect the generated electrical current from the one or more solar devices and direct the generated electrical current to an inverter or a power grid. |
| US10972045B2 |
Pivoting members for a solar array
Pivoting members for pivoting a solar array mounted to a torque rail and tracking systems that include such pivoting members are disclosed. The pivoting member may include a liner between a rotating inner member and the outer housing of the pivoting member to reduce friction during pivoting of the solar array. |
| US10972044B2 |
Solar tracker
The present invention concerns a solar tracker (1000) comprising at least: a mobile device (1100) comprising at least: a table (1110) comprising at least one solar energy collector device (1112); a support structure (1120); first support arch (1130) and a second support arch (1150) configured to support the support structure (1120); a first ground support (1140) and a second ground support (1160) configured to support the first support arch (1130) and the second support arch (1150), respectively; a kinematic drive device (1141); the solar tracker (1000) being characterized in that: the support structure (1120) is a beam formed of a lattice structure comprising: at least one first, one second and one third longitudinal members; a plurality of crossmembers; a plurality of tie rods (1225). |
| US10972041B2 |
Battery pack and battery charger system
A battery pack and charger system includes a first battery pack having a first set of battery cells and configured to provide only a first operating voltage and a second battery pack having a second set of battery cells and configured to provide the first operating voltage and a second operating voltage that is different from the first operating voltage and a battery pack charger configured to be able to charge the first battery pack and the second battery pack. |
| US10972033B2 |
Motor control device, electrically driven actuator product, and electrically driven power steering device
A motor control device including: a power supply voltage detection unit configured to detect a power supply voltage; a rotational angular velocity detection unit configured to detect a rotational angular velocity of the motor; a command value calculation unit configured to calculate a q-axis and d-axis current command values; a gain computation unit configured to compute, based on an upper limit value of power supply current supplied from a power supply to the motor, the power supply voltage, the rotational angular velocity, the q-axis current command value, and the d-axis current command value, a limit gain reducing the power supply current to the upper limit value or lower by limiting the q-axis current command value and the d-axis current command value; and a driving circuit configured to drive the motor, based on the q-axis current command value and the d-axis current command value limited by the limit gain. |
| US10972032B2 |
Method and apparatus for detecting failure of current sensor of motor
A method and apparatus for detecting a failure of a current sensor measuring the magnitude of a current, by which a motor is driven. A required current calculator calculates a phase and a magnitude of a current required for a motor, in accordance with a torque required for the motor. An estimated current calculator calculates an estimated current, in accordance with the phase and the magnitude of the required current. A failure detector detects a failure of a current sensor by comparing the estimated current with a current measured by the current sensor. |
| US10972031B2 |
Active stabilization of DC link in motor drive systems
The present disclosure provides a system and method that provides active damping at the input of a motor drive system without the need for the hardware used in conventional and RC damping circuits. According to the disclosure a virtual damping network is realised at the input of the motor drive system based on modification of field-oriented control, FOC. More specifically, a control algorithm creates a virtual damping impedance at the motor drive input by applying a damping algorithm to both q and d components of the motor current. |
| US10972030B2 |
Multi-stage synchronous generator
The disclosed embodiments aim to improve upon existing multi stage generators for providing power to a load. In particular, embodiments of the invention include a regulator situated between the output of a pilot exciter and the main exciter of a multi stage generator system, the regulator arranged to limit the voltage available to a field current control element which sets the field current supplied to the main exciter. |
| US10972028B2 |
Dynamic generator voltage control for high power drilling and logging-while-drilling
A power generation system for a drilling tool includes a turbine, an alternator, a converter and a first active rectifier control (ARC). The turbine is adapted to be driven by a fluid flow in a well. The alternator is coupled to the turbine and generates an alternative current (AC). The converter converts the AC to direct current (DC) and carries out active rectification. The first active rectifier control (ARC) controls the active rectification of the converter. |
| US10972027B2 |
DC electric motor with asymmetrical stator inductors
A DC motor including a continuous rotation rotor; a first inductor characterized by first parameters; a second inductor characterized by second parameters; a voltage supply unit; a measurement unit for detecting time instants when a first induced voltage in the first inductor equals a second induced voltage in the second inductor; and a control unit for controlling the application of drive voltage pulses to the inductors. The rotor faces first the second inductor before facing the first inductor when being rotated. At least one of the second parameters is selected different from a corresponding parameter of the first parameters such that a maximum induced voltage in the first inductor is greater than a maximum induced voltage in the second inductor. The control unit is arranged to trigger each of the drive voltage pulses after a detection of an equal induced voltage in the first and second inductors. |
| US10972026B2 |
Motor controlling device
A motor controlling device includes a high-side first switching element corresponding to each phase of a three-phase brushless motor, a low-side second switching element corresponding to each phase, a shunt resistor disposed between and connected to the second switching element and a grounding line, and a power controlling section for controlling the first switching element and the second switching element. The device further includes a decision section configured to effect abnormality decision based on a sum of values of currents flowing in the shunt resistors of all the phases acquired by using the power controlling section to switch OFF the first switching element of any one phase whose duty ratio is found equal to or greater than a threshold value for a predetermined period and also to switch ON the second switching element of the same one phase for the predetermined period. |
| US10972021B2 |
Method and system for processing fault information of decoding chip in rotary transformer
Disclosed are a method and a system for processing fault information of a decoding chip in a rotary transformer. The method includes: reading data information transmitted by the decoding chip according to a preset period; determining whether the data information includes alarm information; when the data information includes the alarm information, estimating a rotor-position value after an alarm occurs in real time according to a rotational speed in the data information obtained before the alarm occurs; determining whether a difference between a current rotor-position value and the estimated rotor-position value is greater than a fault threshold; and when the difference between the current rotor-position value and the estimated rotor-position value is greater than the fault threshold, controlling a motor using the estimated rotor-position value. |
| US10972020B2 |
Control method and control device for electric vehicle
The control method for an electric vehicle sets a motor torque command value based on vehicle information and controls torque of a first motor connected to a first drive wheel which is one of a front drive wheel and a rear drive wheel. The control method for an electric vehicle calculates a first torque command value by a feedforward computation based on the motor torque command value, detects a rotation angular velocity of the first motor, and estimates a rotation angular velocity of the first motor based on the first torque command value by using a vehicle model Gp(s) that simulates a transfer characteristic from a torque input to the first drive wheel to a rotation angular velocity of the first motor. |
| US10972016B2 |
Multilevel converter circuit and method
A power conversion system including a first converter configured to convert an input voltage into a plurality of discrete voltages. A second converter configured to convert the plurality of discrete voltages into a plurality of modulated voltages. Each modulated voltage of the plurality of modulated voltages comprises two voltage levels equal, respectively, to two of the discrete voltages of the plurality of discrete voltages. A selection unit configured to alternatively output each modulated voltage of the plurality of modulated voltages across a pair of output terminals. |
| US10972012B2 |
Control circuit and control method of flyback converter
Embodiments of the present application provide a control circuit and a control method of a flyback converter, the control circuit comprises: a first sampling module, a second sampling module, and a control module; the first sampling module is coupled to the control module and the flyback converter, and outputs a first voltage signal to the control module; the second sampling module is coupled to the control module and the flyback converter, and outputs a second voltage signal to the control module; where the first voltage signal reflects an input voltage of the flyback converter, the second voltage signal reflects an output voltage of the flyback converter; the control module outputs a control signal according to the first voltage signal and the second voltage signal, and the control signal reflects a turn-on time of the switch in the flyback converter. |
| US10972011B2 |
LLC resonant converter having multiple transformers and a parallel inductor
The invention provides a series resonant LLC power converter unit to provide a plurality of power outputs. The power converter unit comprises a plurality of transformers arranged such that at least one primary winding of each transformer is connected in parallel and configured to provide a power output. An inductive element is positioned in parallel with a single primary winding selected from said plurality of transformers, wherein the inductive element and single primary winding restricts variation in inductance for said plurality of transformers and power outputs in operation. |
| US10972010B2 |
Controller and control method used in switched tank converter
A control method used in a switched tank converter with a first conversion unit, a second conversion unit and a rectification unit, includes: based on current flowing through the resonant tanks in the first and second conversion units, determining when to turn on the high side switches of the first and second conversion units, and when to turn on the low side switches of the first and second conversion units; detecting whether current flowing through the first, second, third and fourth rectification switches crosses zero; and based on the detection result, respectively determining when to turn off the high side switch of the first conversion unit, when to turn off the high side switch of the second conversion unit, when to turn off the low side switch of the second conversion unit, and when to turn off the low side switch of the first conversion unit. |
| US10972007B2 |
Sense circuit for buck converter circuit
A voltage regulator circuit included in a computer system may include multiple devices and a switch node coupled to a regulated power supply node via an inductor. The voltage regulator circuit may, using different subsets of the multiple devices, charge a capacitor for a first period of time and then couple the switch node to the capacitor for a second period of time. A control circuit may sense, using a common circuit, different characteristics of a current through the inductor during respective operation modes, and adjust the first and second periods of time based on the different characteristics of the current and a current operation mode. |
| US10972006B2 |
Power supply device and control method for power supply device
A power supply device includes battery circuit modules each having a battery, a first switching element S1 connected in parallel to the battery, and a second switching element S2 connected in series to the battery between the battery and the first switching element S1, the second switching element S2 being turned off when the first switching element S1 is turned on, a battery circuit module group in which the battery circuit modules are connected in series, and a control circuit for outputting, at intervals of a certain time, a gate signal for turning on and off the first switching element S1 and the second switching element S2 to the battery circuit modules. |
| US10972005B2 |
Charge pump circuit, semiconductor device, and semiconductor memory device
A charge pump circuit that suppresses low boost efficiency is provided. The charge pump circuit 100 of the invention includes a main pump circuit CPn_M and a gate controlling pump circuit CPn_G controlling the main pump circuit CPn_M. The main pump circuit has the same basic configuration as the controlling pump circuit, which are both KER-type pump circuits. The controlling pump circuit controls the operation of a transistor of the main pump circuit after the main pump circuit is boosted, so that reverse current will not flow from the main pump circuit to the forward section of the pump circuit. |
| US10972003B2 |
Charge pump
The charge pump is provided, which comprises a power supply circuit and a frequency control circuit. The power supply circuit comprises at least one electric energy storage element, and charges the at least one electric energy storage element for producing a supply voltage. The frequency control circuit is coupled to the at least one electric energy storage element, and outputs an operating signal to the power supply circuit. The frequency control circuit adjusts, an operating frequency of the operating signal in according to the electricity stored in the at least one electric energy storage element for controlling charging of the at least one electric energy storage element to increase the electricity of the at least one electric energy storage element. |
| US10972001B2 |
Multi-terminal inductors for voltage regulators
Some embodiments include apparatuses having a switching circuit included in a buck converter; an output node; an inductor including a first portion having a first terminal coupled to the switching circuit, a second portion having a second terminal coupled to the output node, and a third terminal between the first and second portions; and a capacitor coupled to the second terminal, the second terminal to couple to a first additional capacitor, and the third terminal to couple to a second additional capacitor. |
| US10971996B2 |
Charge pump circuit with internal pre-charge configuration
A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage. |
| US10971995B2 |
Apparatus and method for monitoring a safety function of a machine or technical installation
Apparatus for voltage monitoring of a dual-channel device which implements or monitors a safety function of a machine or technical installation. The apparatus comprises an input for receiving an input voltage, a voltage regulator for generating a defined output voltage, and an output for providing the defined output voltage for the operation of the device. A voltage monitor compares a voltage present at the output with the defined output voltage and switches off the output in case the present voltage at the output deviates from the defined output voltage. A first interface and a second interface connect the voltage regulator to the dual-channels of the device, wherein the first interface and the second interface connect to a first processing channel and a second processing channel of the device separately so that the first processing channel and the second processing channel of the device can detune the voltage regulator independently. |
| US10971991B2 |
Power conversion device and power conversion system
A controller of each power conversion device in a power conversion system controls a switching element unit, based on a detected value of reactor current flowing through a filter reactor, a detected value of output voltage output between the terminals of a filter capacitor, and a detected value of output current flowing through an output reactor. The controller generates a voltage command based on the output current and the output voltage and generates a correction amount of the voltage command based on the output current in which a reference frequency component is removed. The controller generates a current command based on the addition value of the voltage command and the correction amount and controls the switching element unit such that the reactor current matches the current command. |
| US10971985B2 |
Actuator and method of producing actuator
An actuator may include a supporting body; a movable body; a first magnetic drive circuit; a second magnetic drive circuit. The first magnetic drive circuit may include a first coil and a first magnet. The second magnetic drive circuit may include a second coil and a second magnet. The actuator may further include a first yoke on a side of the first coil remote from the second coil; a second yoke on a side of the second coil remote from the first coil; and a third yoke between the first coil and the second coil. The first magnet may be held on a face of the first yoke or a face of the third yoke. The second magnet may be held on a face of the second yoke or a face of the third yoke. The third yoke may be thicker than the first and second yoke. |
| US10971984B2 |
Linear vibration motor
A linear vibration motor includes a fixed portion, a movable portion, and a suspension portion; the fixed portion further includes an outer frame, a coil set, a conductive sheet set, a connecting circuit and a terminal; the movable portion includes a bracket, a primary magnet set, at least a secondary magnet set; the suspension portion includes a pair of elastic members connected to the fixed portion and the movable portion, and provides a restoring force when the movable portion is displaced; the coil set and the primary magnet set provide a driving force to drive the movable portion to generate vibration; the conductive sheet set and the secondary magnet set provide damping when the movable portion moves. |
| US10971982B2 |
Moving core type reciprocating motor and compressor
A moving core type reciprocating motor is provided that may include a stator on which a coil may be wound and having an air gap; a magnet fixed to the stator; and a mover that includes a moving core disposed to face the magnet in the air gap and reciprocates with respect to the stator. The magnet may have a first pole and a second pole that are different poles arranged in a reciprocation direction of the mover, and a length of the first pole may be larger than a length of the second pole. |
| US10971977B2 |
Stator for rotary electric machine and rotary electric machine
Provided is a stator for a rotary electric machine which can suppress the mechanical effects of thermal expansion and contraction of a fixing member for fixing a temperature detector, on a temperature detection element. The stator for a rotary electric machine includes a stator coil, a temperature detection unit including a temperature detection element, a protection member extending in a longitudinal direction to cover the temperature detection unit, and a fixing member serving as a positioning mechanism for the temperature detection unit with respect to a stator coil. The fixing member includes a clamp portion for fixing the protection member, and the clamp portion clamps the protection member at a position where the clamp portion does not overlap the temperature detection element in a longitudinal direction of the protection member. |
| US10971974B2 |
Electric charging device with fluid cooling
A charging device for an internal combustion engine with a shaft, a compressor wheel arranged on the shaft, a stator housing and a stator. The stator is arranged within the stator housing. A rotor is arranged on the shaft and a cooling channel for accommodating a coolant extends axially between the stator housing and the stator. A split tube is provided between the rotor and stator. A first seal is provided in the axial direction between the stator housing and a first end of the stator and a second seal is provided in the axial direction between the stator housing and a first end of the split tube. Alternatively to the split tube, a separation tube is arranged between the stator and the stator housing so that the cooling channel is formed in the radial direction between the separation tube and the stator housing. |
| US10971973B2 |
Energy conversion apparatus
Energy conversion apparatus comprising: an electrical machine including a rotor arranged to rotate about an axis, the rotor defining a first cavity therein; power electronic circuitry arranged at least partially around the axis and defining a second cavity therein, the power electronic circuitry being positioned adjacent to the electrical machine; a heat pipe positioned within the first cavity of the rotor and within the second cavity defined by the power electronic circuitry, the heat pipe being arranged to receive thermal energy from the rotor; and a cooling arrangement positioned at least partially within the second cavity and arranged to receive thermal energy from the power electronic circuitry and from the heat pipe. |
| US10971968B2 |
Noiseless self-ventilated motor, in particular for a railway vehicle
The self-ventilated motor (10) comprises a casing (12) having an air inlet opening (18) and an air outlet opening (20) and delimiting an air passage between the air inlet opening (18) and the air outlet opening (20), drive means (13) comprising a shaft (22) housed in the casing (12), a ventilation propeller (24) connected to the shaft (22) upon rotation and housed in the air passage, and a noise reduction device (26). The noise reduction device (26) comprises a first noise reduction member (28), attached to the casing (12) at the air inlet opening (18), a second noise reduction member (30) arranged on the ventilation propeller (24), and a third noise reduction member (32) fixed to the casing (12) at the air outlet opening (20). |
| US10971967B2 |
Electric motor for an elevator system and elevator system comprising such a motor
An electric motor (20) for an elevator system (2) comprises a housing (25) extending in a longitudinal direction along a longitudinal axis (A) and a cover (22) attached to a front face of the housing (25). The cover (22) comprises an open space (24) formed around the longitudinal axis (A). At least one electric connector (38, 40), which is electrically connectable with component of the electric motor (20), is arranged within said open space (24). |
| US10971965B2 |
Motor and blower apparatus
A motor includes a rotor, a stator, and a circuit board below the stator. The stator includes an insulator to cover at least a portion of each of an upper surface, a lower surface, and circumferential side surfaces of each of teeth of the stator, coils each of which is defined by a conducting wire wound around a separate one of the teeth with the insulator therebetween, and a drawn-out wire drawn out from the coils and electrically connected to the circuit board. A lower portion of the insulator includes a guide radially outward of the coils and including a wall extending downward from a lower surface of the insulator and a bend extending radially outward from a lower end of the wall. At least a portion of the drawn-out wire extends in a circumferential direction along a radially outer surface of the wall. |
| US10971959B2 |
Stator for an axial flux machine with a stator ring composed of modules
This invention relates to a stator for an axial flux electromagnetic machine, with the stator forming a ring (1) having two substantially circular faces (1a, 1b) connected by a thickness comprising windings (3) regularly distributed in the ring (1). Each winding (3) is carried by a unit portion (4) having a core (5) around which the winding (3) is wound. The unit portions (4) are arranged concentrically edge-to-edge with respect to one another and have securing means (12, 12a, 14) with a support member (6) which is part or not of a casing housing the ring (1) carried either by axial and lateral faces of each unit portion (4) edge-to-edge or by at least one upper or lower face of with each unit portion being part of a substantially circular face. |
| US10971958B2 |
Method and apparatus for performing communication in wireless power transmission system
A wireless power transmitter includes a power conversion unit configured to transfer wireless power to a wireless power receiver by forming magnetic coupling with the wireless power receiver; and a communication/control unit configured to communicate with the wireless power receiver to control transmission of the wireless power and to perform transmission or reception of data, wherein the communication/control unit further configured to set a target power level based on an operation condition, receive, from the wireless power receiver, a received power packet (RPP) which informs a value of the wireless power received by the wireless power receiver, transmit a bit pattern to the wireless power receiver in response to the RPP, the bit pattern requesting communication initiated by the wireless power transmitter, and receive, from the wireless power receiver, a response packet to allow the communication initiated by the wireless power transmitter. |
| US10971954B2 |
Systems and methods for object detection
Systems and methods for object detection are provided. The system includes at least a coil, a small signal generator, a small signal receiver, and a processor. The small signal generator includes a digital-to-analog converter circuit with programmable impedance. The small signal generator is configured to select an output impedance for the digital-to-analog circuit for capacitive sensing or radio-frequency identification (RFID) tag detection; generate a small signal according to the output impedance; and provide the small signal to the coil. The small signal receiver receives the small signal and a response signal associated with the small signal and measures the response signal to generate a measured signal. The processor compares the measured signal with one or more reference signals and performs capacitive sensing and/or detect a RFID tag according to the comparison. |
| US10971953B2 |
Contactless power receiving device, contactless power transfer device, and contactless power transfer and receiving device
A contactless power receiving device includes a power receiving coil receiving power from a contactless power transfer device, a rectifier circuit rectifying the power to form a rectified output on a high potential side and a rectified output on a low potential side, a smoothing circuit receiving the rectified output on the high potential side and the rectified output on the low potential side, and a switching power supply converting a DC voltage from the smoothing circuit to a first voltage. The smoothing circuit includes a first inductor transmitting the rectified output on the high potential side, a second inductor transmitting the rectified output on the low potential side, and a smoothing capacitance element to which the rectified output on the high potential side and the rectified output on the low potential side are supplied, and the rectified output on the low potential side is connected to a ground potential. |
| US10971951B2 |
Electronic system having power adapter for wired and wireless charging
A universal power adapter may be provided to provide both a wireless charging signal and a DC signal for wired charging. The universal power adapter may include an AC/DC converter device, a first power circuit, a second power circuit, and a jack to provide a wireless charging signal and a DC signal. The AC/DC converter device to provide a DC signal based on an AC signal received from an external power source. The first power circuit to receive the DC signal and to provide a wireless charging signal based on the DC signal. The second power circuit to receive the DC signal and to provide a DC signal based on the DC signal. The jack may provide both the wireless charging signal and the DC signal. |
| US10971948B2 |
Modular element for a hybrid network of an aircraft
The modular element for a hybrid electrical power distribution and data communication network of an aircraft comprises a section of a bus and a set of data links extending substantially parallel along a length of the modular element. The bus section comprises connection points at different locations distributed along its length. The set of data links comprises connection points at different locations distributed along its length, each arranged in proximity to a connection point of the bus section. It also comprises a data link between each of the connection points and a cross-connect point. The bus section and the set of data links comprise interconnection points making it possible to link the modular element to first and second, other, modular elements arranged longitudinally in series with the modular element. |
| US10971947B2 |
System and method for controlling an electrical load
A system and method for controlling a number of load controllers (10), each of which is operatively connected to one or more electrical loads (6) that are connected to a grid, results in a reduction in tracking errors, which arise when aggregated local devices fail to deliver the expected amount of responsive load service. Each load controller (10) monitors the operating frequency of the grid network (8) and is adapted to adjust power consumption of one or more of its electrical loads (6) in response to excursions of the operating network frequency from its nominal value. The load controllers (10) are in communication with a remote controller (14) and aggregated together to provide a responsive load service. The remote controller (14) is adapted to monitor the deviation of grid frequency from its nominal value and to determine adjustments to the responsive load service delivered by the electrical loads of each load controller. The remote controller (14) thereafter sends a correction signal to each load controller (10), which causes the respective load controller (10) to apply a correction to its responsive load service by way of an offset to its power consumption adjustments. |
| US10971946B2 |
Wireless power receiver and wireless power transmitter
Disclosed is a wireless power receiver for receiving power wirelessly. According to an embodiment of the present disclosure, a wireless power receiver wirelessly receiving power may include a first power receiver receiving first power from a first power transmitter, a second power receiver receiving second power from a second power transmitter, and a shielder disposed between the first power receiver and the second power receiver to substantially shield influx of the first power into the second power receiver and to substantially shield influx of the second power into the first power receiver. |
| US10971944B2 |
Wireless charging apparatus using electromagnetic induction and wireless charging method using electromagnetic induction
An embodiment of the present invention provides a wireless charging apparatus and a method, in which a reception unit can charge even when an inner coil of the reception unit and an inner coil of a transmission unit are not positioned in parallel. An embodiment of the present invention provides a wireless charging apparatus and a method including: a transmission unit that includes a first coil that generates a magnetic field when power is applied; a reception unit that includes a second coil, and that charges a battery using induced current that is induced in the second coil when the magnetic field of the first coil is generated; a position sensing unit that measures position information for the first coil and the second coil; and a conversion unit that converts a direction of the magnetic field according to the position information for the first coil and the second coil. |
| US10971943B2 |
Medical device temperature estimation
Devices, systems, and techniques for monitoring the temperature of a device used to charge a rechargeable power source are disclosed. Implantable medical devices may include a rechargeable power source that can be transcutaneously charged. The temperature of an external charging device and/or an implantable medical device may be monitored to control the temperature exposure to patient tissue during a charging session used to recharge the rechargeable power source. In one example, a temperature sensor may sense a temperature of an internal portion of a device, wherein the housing of the device is not directly thermally coupled to the temperature sensor. A temperature for the housing of the device may then be estimated based on the sensed temperature provided by the non-thermally coupled temperature sensor. A processor may then control charging of the rechargeable power source based on the determined temperature for the housing. |
| US10971940B2 |
Battery longevity extension
Disclosed herein are system, method, and computer program product (computer readable medium) embodiments for extending battery longevity by improving partial-state-of-charge operation of batteries. An embodiment operates by determining, using at least one processor, that at least one first battery has stopped charging at a partial state of charge, in which the at least one first battery is associated with a first battery bank and is rechargeable, and charging, in response to receipt of a command issued from the at least one processor or another processor in response to the determining, the at least one first battery using at least one second battery, in which the at least one second battery belongs to a second battery bank that is not the first battery bank, by transferring charge from the at least one second battery to the at least one first battery. |
| US10971939B2 |
Adaptive cell-balancing
A cell balancing system includes sensing circuitry configured to sense a cell voltage of each of a plurality of cells of a battery. Cell balancing circuitry is configured to balance each of the plurality of cells in response to a respective cell balancing command for each of the plurality of cells. A comparison circuit configured to compare the sensed cell voltages for each of the plurality of cells to an adaptive threshold voltage. The comparison circuit generates a respective cell state for each of the plurality of cells to indicate a state of the respective cell voltage for each of the plurality of cells relative to the adaptive threshold voltage. A controller is configured to set the respective cell balancing command for each of the plurality of cells and to adjust the adaptive threshold voltage based on an evaluation of the cell states for the plurality of cells. |
| US10971936B2 |
Renewable energy generation and storage system using current loop adjustment
A renewable energy generation and storage system forms a current control loop for controlling a current charge operation and a current discharge operation to a plurality of energy storage cells at the same time. As a result, renewable energy from multiple sources may be stored while providing output voltage to a load, and therefore the renewable energy generation and storage system of the present invention may achieve energy generation and storage at the same time. |
| US10971935B2 |
Can bus terminating resistor arrangement
A power generation system including a controller area network (CAN) bus and a first power source having a first electrical generator, a first controller connected to the CAN bus, and a first resistor. The power generation system also includes a second power source having a second electrical generator, a second controller connected to the CAN bus, a second resistor, and a user-activated switch. The user-activated switch is movable between a first position, so that the second resistor acts as a terminating resistor to signify another end of the CAN bus and a second position so that the second resistor is prevented from acting as a terminating resistor. |
| US10971927B2 |
Current controlling device
There is described a device for controlling an amount of current within a power distribution network by manipulating the amount of magnetic flux in the device and thus the impedance experienced by the power distribution network across the device. This is achieved by winding a plurality of coils about a magnetically permeable core and by providing the device with a magnetically permeable bridge element that is movable between a fully-open position at which the net magnetic flux generated in the core by alternating currents in each coil is zero, and a fully-closed position at which a net magnetic flux is present in the core. |
| US10971926B2 |
Tape lifetime monitor in fault current limiter
An apparatus for controlling and monitoring the lifetime of a superconducting fault current limiter. The apparatus may include a processor; and a memory unit coupled to the processor, including a lifetime routine, where the lifetime routine is operative on the processor to monitor the superconducting fault current limiter. The lifetime routine may include a lifetime estimation processor to receive a set of fault information for a fault event of a superconductor tape of the superconducting fault current limiter, determine a present state of the superconductor tape based upon the set of fault information, and determine an estimated lifetime of the superconductor tape based upon the present state. The present state may be determined from additional information such as fault history on the superconducting fault current limiter, as well as a database of superconductor tape behavior with respect to various faults. |
| US10971925B2 |
Control method of susceptible inrush currents passing through a load switch, and corresponding electronic circuit
An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison. |
| US10971919B2 |
Electronic circuit-breaker for a load that can be connected to a low voltage DC-voltage network
The invention relates to an electronic circuit-breaker for a load (RL) that can be connected to a low-voltage dc-voltage network, the circuit-breaker consisting of assemblies provided between input terminals and the load and said assemblies comprising a voltage monitoring unit (TVS1, R1), a current monitoring unit (Shunt, OPV), semiconductor switch units (MOSFET) and controllers (uC) associated therewith. According to the invention, a series circuit consisting of a TVS diode (TVS1) and a resistor (R1) is connected to the input terminals, the resistor having a connection to a first connector (1) of a microcontroller (uC) and the resultant voltage drop at the resistor providing the microcontroller with an overvoltage identification signal if a breakdown voltage is reached at the TVS diode as a result of an overvoltage. A second connector (2) of the microcontroller has a connection to a first semiconductor switch unit (MOSFET), the first semiconductor switch unit being in series, as an elongate switch, with the load (RL), and the microcontroller disabling the switch in the event of an overvoltage detection signal. A shunt acting as a current monitoring unit is in series with the load, the voltage drop at the shunt being analysed by the microcontroller via a third connector (3) and if an overcurrent which exceeds a threshold value is identified, the load is switched off by means of the first semiconductor switch unit. In addition, a MOS-gated thyristor (MGT) is connected between the input terminals, the control input of said thyristor having a connection to a fourth connector (4) of the microcontroller, such that the MOS-gated thyristor can be activated in the event of an overvoltage identification signal. |
| US10971917B2 |
Primary-pulsed switching power supply
Disclosed is a primary-clocked switching power supply for converting an input voltage into an output voltage, comprising: a primary side circuit branch, where the input voltage can be applied; isolated from the primary side circuit branch, a secondary side circuit branch, where the output voltage is tappable; between the primary side and the secondary side circuit branch, a galvanic isolation; a fuse or circuit breaker arranged in the primary side circuit branch; a first switchable switch element arranged in the primary side circuit branch such that switching trips the primary side fuse or circuit breaker; and a monitoring unit connected with the first switch element and arranged in the primary side circuit branch and adapted to monitor a characteristic electrical signal determined by the second primary winding and, when the characteristic electrical signal exceeds a threshold value, to switch the first switch element. |
| US10971916B2 |
Space-limited protection module with at least two overvoltage protection elements in parallel current branches
The invention disclosure relates to a space-limited protection module with at least two overvoltage protection elements in parallel current branches, where the protection module includes a local multistage indicator for indicating at least one operating state, a warning state and a defect state, and where the parallel switched overvoltage protection elements are arranged on a circuit board in electrical connection to conductor tracks of the circuit board and attached in a thermally softenable manner. |
| US10971915B2 |
Mounting bracket systems for dead-end utility lines
Mounting brackets for dead-end utility lines and mounting bracket systems for dead-end utility lines are described in the present disclosure. Each mounting bracket can include a body with a front face and, a plurality of arms extending from the body with each arm comprises a hook that is configured to receive a dead-end utility line. The mounting brackets are configured to be mounted on a utility pole and to allow a plurality of dead-end utility lines to be mounted to a utility pole with a single mounting bracket. |
| US10971908B2 |
Enclosure for protecting electrical components, cables and the like
An enclosure for protecting electrical components, cables and the like. The enclosure has a plurality of faces which define a volume with an opening to provide access. One face has apertures for receiving fixing screws to fix the enclosure to a wall or surface. There is a lid to close the opening. Spacer members separate the enclosure from the surface. Each has a bore extending through it and a threaded portion extending from a surface of the face which engages the apertured face of the enclosure. For each spacer there is a cap for covering the aperture and sealing the apertured face. Also provided for each spacer is a retainer for threading onto the externally threaded portions when the spacer's threaded portion extend through the apertured face. |
| US10971905B2 |
Exhaust system for switchgear enclosure, and switchgear enclosure having the same
A switchgear enclosure includes an exterior housing. A plurality of compartments within the exterior housing includes at least a first switching device compartment, a bus compartment, and a first cable compartment. A plurality of interior partitions arranged to subdivide the exterior housing into the plurality of compartments includes at least a first partition between the first switching device compartment and the first cable compartment, and a second partition between the bus compartment and the first cable compartment. An exhaust system includes a vent path structure arranged within the exterior housing to at least partially surround the bus compartment and the first cable compartment, a channel formed between the vent path structure and the exterior housing, and a first vent device in the first partition. The first vent device is configured to fluidically connect the first switching device compartment to the channel via the vent path structure. |
| US10971903B1 |
Utility distribution enclosure
A utility distribution enclosure disclosed herein includes a container that defines an interior space that is interior of the container, a detent formed about inner surfaces of the container, and a partition positionably releaseably engageable with the detent to subdivide the interior space into a first subspace and a second subspace selectingly sized to accommodate a first utility interface and a second utility interface by positioning of the partition, in various aspects. The partition blocks interactions between the first utility interface and the second utility interface. |
| US10971899B2 |
Laser light source unit
A housing 10 is provided with a groove V1a into which an electrode 3b of a laser oscillation element 30a and an electrode 3a of a laser oscillation element 30b are inserted. Inside the groove V1a, there exists a conductive layer 12 configured to electrically connect the electrode 3b of the laser oscillation element 30a and the electrode 3a of the laser oscillation element 30b. |
| US10971894B2 |
Driver for high speed laser diode
Various embodiments of a laser driver are described herein. In an embodiment, a laser driver system includes: an external set of inductors including a first external inductor and a second external inductor; an internal set of inductors including a first internal inductor and a second internal inductor; and a DC-to-DC convertor configured to bias a first output path defined by the first external inductor and the first internal inductor and a second output path defined by the second external inductor and the second internal inductor. |
| US10971888B2 |
Optical amplifier
An optical amplifier which can suppress, without measuring signal beam power at individual wavelengths, wavelength-dependence of gain with respect to a signal beam into which multiple signal beams having respective wavelengths different from each other are multiplexed. The optical amplifier can suppress wavelength-dependence of gain by giving loss in accordance with a linear-loss slope to an amplified signal beam. The optical amplifier includes a variable tilt equalizer for varying a loss slope value representing the slope of the loss slope and a tilt control unit for controlling a loss slope value of the variable tilt equalizer. |
| US10971886B2 |
Laser apparatus
A laser apparatus includes a chamber accommodating a pair of discharge electrodes, a gas supply and exhaust device configured to supply laser gas to an interior of the chamber and exhaust laser gas from the interior of the chamber, and a controller. The controller performs first control to control the gas supply and exhaust device so as to suspend laser oscillation and replace laser gas in the chamber at every first number of pulses or first elapsed time, and second control to control the gas supply and exhaust device so as to suspend laser oscillation and replace laser gas in the chamber before the first control at every second number of pulses less than the first number of pulses or second elapsed time less than the first elapsed time. |
| US10971885B2 |
Scalable high power fiber laser
A modular and scalable high-power fiber laser system is configurable to generate 1 kW or more of laser output, and includes one or more separable pump modules separately disposed from each other, each pump module including a plurality of fiber-coupled component pump sources optically combined by one or more fiber-based pump module pump combiners, each pump module providing one or more pump module fiber outputs, and a gain module separately disposed from the one or more separable pump modules and including one or more gain module pump fiber inputs optically coupled to corresponding ones of the pump module fiber outputs, and including a gain fiber optically coupled to the one or more gain module pump fiber inputs, the gain fiber configured to generate a gain module fiber output power scalable in relation to the number and power of said pump module fiber outputs coupled to the gain fiber. |
| US10971883B2 |
Gas laser apparatus
A gas purification system may include: a circulation gas pipe in which a second end is connected at a first position to a second pipe through which gas is supplied from a gas supply source; a booster pump; a gas purification unit; a first tank in the circulation gas pipe; a first valve positioned between the gas supply source and the first position, the first valve having an open position and a closed position; and a second valve positioned between the first tank and the second end, the second valve having an open position and a closed position, the second valve configured to be in the closed position when the first valve is in the open position. |
| US10971882B2 |
Light source module
A light source module includes a light source configured to emit a first light beam, a first optical element having a first surface on which the first light beam is incident along a first direction, the first surface including a first region on which at least a portion of the first light beam is incident, and a second surface from which the first light beam is emitted, and a second optical element on which the first light beam having emitted from the first optical element is incident. The first light beam has a first width along a second direction and a second width along a third direction. The first width is greater than the second width. The first region has a protruding shape in a first cutting plane including the first and second directions, and has a recessed shape in a second cutting plane including the first and third directions. The second surface has a protruding shape in the first and second cutting planes. |
| US10971877B2 |
Busbars docking platform
A platform for connecting busbars has a loading unit having a blind hole on a docking surface for receiving a connecting rod, an action unit used for impacting the loading unit or a busbar to push the connecting rod into a pre-hole on the busbar, a limit unit used for stopping the busbar from moving along its length direction, and a support unit used for supporting the action unit and the limit unit. The connecting rod is assembled to the first busbar by the action unit combined the loading unit and then the connecting rod already assembled to the first busbar is assembled to the second busar by the action unit. |
| US10971871B2 |
Connector adaptation with impedance matching
A method and apparatus utilize a data connector, a connection adapter, and a matching transformer. The data connector receives a data signal from a communication line. The connection adapter, coupled to the data connector, receives the data signal with the data connector, adapts the data signal from the data connector to a coax connector, and communicates the data signal to the coax connector. The matching transformer, coupled to a coax cable, performs impedance matching between a first impedance associated with the coax connector and a second impedance associated with the coax cable communicating the data signal. |
| US10971866B2 |
Connector device with antenna connection
The present disclosure described devices, components, connectors, and cables that connect an audio-visual device to an external antenna. Some embodiments describe a device connector for connecting the audio-visual device to an external cable. The device connector may include a supply port that is configured to receive power, data signals, and/or some combination of power and data from a source external to the audio-visual device. The device connector may also include an antenna port that is configured to connect the audio-visual device to an external antenna that is, for example, part of the same. Additionally, the device connector may include a detection mechanism that detects the presence of an antenna connection in the antenna port. When an antenna connection is detected, the audio-visual device may be configured to use one or more external antennas connected via the antenna connection to send and receive, e.g., WiFi signals. |
| US10971865B2 |
Electrical connector with a multi-part shield
A cable with terminals in the present disclosure includes a shielded cable (80) and an outer conductor (40). The shielded cable (80) includes wires (81) and a shield. The outer conductor (40) includes a tube. The tube collectively covers the outer peripheries of the wires (81) exposed from the shield, and includes a first cover and a second cover. The first cover covers the wires from a first side, and the second cover covers the wires from a second side opposite to the first side with clearances (S) defined between the first and second covers. At least one of the first and second covers includes leakage suppressing portions (58). The leakage suppressing portions (58) extend toward a wire arrangement area (48) where the wires (81) are arranged in the tube. |
| US10971864B1 |
DIN rail shield
A shield device includes: an electrical conductor; an electrical insulator that is configured to electrically insulate the electrical conductor from a DIN rail and to hang the shield device from the DIN rail; a first shield connector configured to: directly contact at least 180 degrees of a first circumference of a first shield that surrounds at least two insulated conductors of a first section of a shielded cable; and electrically connect the first shield with the electrical conductor; and a second shield connector configured to: directly contact at least 180 degrees of a second circumference of a second shield that surrounds at least two insulated conductors of a second section of the shielded cable; and electrically connect the second shield with the electrical conductor. |
| US10971863B1 |
High speed connector assembly and electrical connector thereof
A high speed connector assembly and an electrical connector thereof are provided. The electrical connector includes an insulating housing and a plurality of signal terminals fixed in the insulating housing. The insulating housing is in an elongated shape defining a longitudinal direction, and defines an insertion direction perpendicular to the longitudinal direction. The signal terminals are arranged in two rows each parallel to the longitudinal direction, and the signal terminals in one of the two rows respectively face that in the other row. Each of the signal terminals includes a signal fixing segment engaged with the insulating housing, a signal contacting segment, and a signal soldering segment. The signal contacting segment has a main transmission point and a secondary transmission point, which are spaced apart from each other along the insertion direction. The main transmission point is closer to the signal fixing segment than the secondary transmission point. |
| US10971858B2 |
Electrical connector and electrical connector assembly
An electrical connector configured to be inserted into a mating connector in an insertion direction includes a housing having a receiving passage, a locking mechanism, and a releasing mechanism. The locking mechanism is rotatably mounted on a top wall of the housing by a pivot and has a locking portion. The locking portion is inserted into a mating housing of the mating connector to lock the electrical connector and the mating connector. The releasing mechanism provides a releasing force to drive the locking mechanism to move from a locked state to a released state to allow the electrical connector to be disengaged from the mating connector. |
| US10971857B2 |
Cable extraction tool
A tool 202 for extracting a cable plug 112 from a socket 203 including a cable remover portion 206 which actuates and disconnects the cable plug 112 is described and claimed. Various implementations include a user statically or dynamically actuating and gripping the plug 112 and mechanically or frictionally gripping, or both, the plug 112. In one implementation, the cable remover portion 206 includes a ball detent 302 and catch tabs 320 which actuate the cable clip 208 and catch the cable head 210 so that the plug 112 is mechanically gripped. In another implementation, a translational ramp 800 is supported in the cable remover portion 206 so that a user dynamically moves the ramp 800, which actuates the cable clip 208 and the force of the ramp 800 and cable remover 206 together frictionally grips the plug 112. |
| US10971856B1 |
Lever-type electrical connector
A lever-type electrical connector (102), a corresponding mating electrical connector (104) for accepting the lever-type electrical connector (102), and a lever-type electrical connector assembly (100) thereof are described herein. The lever-type electrical connector (102) has a first portion (300) with a first slot (302) configured to accept a rib protrusion (114) of the corresponding mating electrical connector (104) and a lever (304) pivotally mounted to the first portion (300) with cam grooves (408) on opposing interior surfaces configured to accept cam-follower protrusions (210) on opposite sides of the rib protrusion (114). |
| US10971855B2 |
Electrical connector with plug latching assembly
A latch assembly is provided in a receptacle in a pin-and-sleeve type electrical connector used to capture a plug of the pin-and-sleeve electrical connector. The latch assembly has a housing with a cover, a plurality of latches and a corresponding plurality of latch lever arm extending from a latch lever, such that pivotable movement of the latch lever is translated to rotational movement of the latches between a plug capture position and a plug release position. |
| US10971853B2 |
Bus bar holding structure, electrical connection box and wire harness
A bus bar holding structure includes a resin block main body, a first bus bar having a protruding portion, and a second bus bar. The resin block main body includes a bus bar assembling portion having a groove portion. The first bus bar and the second bus bar are accommodated in the bus bar assembling portion such that first side portions of the first bus bar and the second bus bar are located on a bottom side of the groove portion and second side portions of the first bus bar and the second bus bar are located on an opening side of the groove portion. The second bus bar is sandwiched between the second bus bar and a bottom of the groove portion when the first bus bar and the second bus bar are accommodated in the bus bar assembling portion. |
| US10971845B2 |
Rectangular impact-resistant elastic connector
A rectangular impact-resistant elastic connector includes an upper contact part, first and second side plates, first and second S-shaped lift force arms and a bottom plate, wherein the first and second side plates are connected with the bottom plate, the first S-shaped lift force arm has an end connected with the upper contact part and an end connected with one end of the first side plate, and the second S-shaped lift force arm has an end suspended below the upper contact part and an end connected with one end of the second side plate. The S-shaped lift force arm structures having the advantage of greater elasticity over other force arm structures under the same unit size are used to provide an elastic force, so that the size of the connector is reduced. The side plates protect the force arms, thus, improving the overall impact resistance of the connector. |
| US10971844B2 |
Connector including conductive voltage detection terminal branching from conduction path
A connector includes: a casing that has a housing space, a through hole communicating the housing space with an external space, and an electric wire insertion hole, and that holds a connection terminal connected to a counterpart device; a wiring material that has a distal end part inserted into the housing space via the electric wire insertion hole and a conductor part exposed from a covering at the distal end part, the exposed conductor part being curved at a curved part and connected to the connection terminal; and a conductive voltage detection terminal that has a connection part connected to the exposed conductor part at a position closer to the covering than a curved part and a voltage detection part facing the through hole, and that is provided by branching from a conduction path between the connection terminal and the conductor part. |
| US10971841B2 |
Board connector
A board connector (A) is provided with a housing (10) placed on a circuit board (P) and including a terminal holding wall (11) substantially at a right angle to the circuit board (P) and supporting walls (15) extending rearward from sides of the terminal holding wall (11). Terminal fittings (25, 26) penetrate through the terminal holding wall (11) and are connectable to the circuit board (P) behind the terminal holding portion (11). Fixing brackets are mounted on the supporting walls (15) and are fixable to the circuit board (P) by soldering. A reinforcing portion (20: 21 or 23) links the supporting walls (15) and a rear surface of the terminal holding wall (11). |
| US10971838B1 |
Combination structure of clamping member and circuit board for signal connector
A combination structure of a clamping member and a circuit board for a signal connector is disclosed. The clamping member includes two clamping members fixedly connected to two sides of the circuit board. Each clamping member has a pair of first positioning pins and a pair of second positioning pins. Thereby, the center of the guide pin can be guided and the guide pin won't be loosened, so as to improve the stability of the signal and reduce the loss. |
| US10971837B2 |
Substrate electrical connector with terminals in accommodating holes
An electrical connector includes a substrate and multiple terminals. The substrate is provided with multiple accommodating holes running through the substrate vertically. A shielding member is provided on a lower surface of the substrate. The terminals are correspondingly accommodated in the accommodating holes respectively. The terminals include multiple signal terminals and at least one ground terminal. An interval exists between the ground terminal and the shielding member. The ground terminal has a conducting portion extending downward out of a corresponding accommodating hole. The conducting portion is soldered to a main circuit board through a solder, and the solder is in contact with the conducting portion and the shielding member. According to the present invention, the conducting portion of the ground terminal is connected with the shielding member through the solder, thereby reducing a spurious charge, reducing the capacitance, and improving a high frequency. |
| US10971835B2 |
Electrical connector
An electrical connector is mounted on a circuit board and used to mate with a mating member. The electrical connector includes: a body made of a wave-absorbing material, the body having an upper surface, a lower surface and at least one first accommodating groove; and at least one ground terminal accommodated in the first accommodating groove. An upper end of the ground terminal is exposed to the upper surface and is in electrical contact with the mating member, and a lower end of the ground terminal is exposed to the lower surface and is electrically connected with the circuit board. |
| US10971834B1 |
Electrical connector
An electrical connector includes a housing which is provided with an installation cavity and a jack. A conductive clamp and a movable member are configured in the housing. The conductive clamp is provided with at least one pair of first clamping pieces and at least one pair of releasing pieces. The first clamping pieces and the releasing pieces extend into the installation cavity. The movable member is capable of moving back and forth along the installation cavity. A conducting wire is capable of passing through the jack and is inserted into one pair of first clamping pieces. The movable member is capable of moving forward along the installation cavity, and abutting on one pair of releasing pieces, to force the releasing pieces and drive the first clamping pieces to open outward, so that the conducting wire is capable of detaching from the first clamping pieces. |
| US10971833B2 |
Board connector
A board connector includes fixing members (60) to be mounted into a connector housing (10). Each fixing member (60) includes a plate-like housing mounting portion (61) to be arranged along a surface (12) of the connector housing (10) and a board fixing portion (62) connected to the housing mounting portion (61) and to be fixed to a surface of a circuit board (90) by soldering. The housing mounting portion (61) includes a flat plate (63) near the circuit board (90), a flat plate (64) distant from the circuit board (90) and a bent portion (65) between the respective flat plates (63, 64) and bulging in a plate thickness direction with respect to the flat plates (63, 64). The bent portion (65) is provided over an entire width of the housing mounting portion (61) in a plate width direction between the flat plates (63, 64). |
| US10971828B2 |
Insulation-displacement connector
An insulation-displacement connector including two cutting and connecting blades, each one provided with a section for inserting and centering of a cable, a cutting edge which extends from the section for centering and insertion, a base, and an arm for joining each blade to the base; where the cutting edges are inclined along the entire extension of the edges such that they cross one another, and where the cutting and connecting blades are not joined together at an end of the blades opposite to the joining end of the sections, but rather are joined to the arms such that the blades may be separated from one another according to a transverse direction. |
| US10971826B2 |
Wire with terminal
A wire with terminal (10) has a terminal (12), and a wire (14) extends rearward from the terminal (12). The terminal (12) includes a fixing portion (18) and a neck (20) extending rearward from the fixing portion (18). A base plate (22) extends rearward from a rear end of the neck (20) and has an insulation barrel (34) crimped to insulation coating (32). A laminated portion (26) has wire barrels (36) connected to a core (30). The laminated portion (26) is laminated on the base plate (22). An easily disassemblable portion (24) couples a rear (22A) of the base plate (22) and a rear (26B) of the laminated portion (26). Guides (28) allow displacement of the laminated portion (26) in a pulling direction D1 of the wire (14) while suppressing displacement of the laminated portion (26) in a lamination direction on the base plate (22). |
| US10971825B2 |
Antenna module and method of manufacturing the same
An antenna module includes: an integrated circuit (IC) configured to generate a radio frequency (RF) signal; and a substrate including an antenna portion providing a first surface of the substrate, and a circuit pattern portion providing a second surface of the substrate. The antenna portion includes first antenna members configured to transmit the RF signal, cavities corresponding to the first antenna members, through vias respectively disposed in the cavities and respectively electrically connected to the first antenna members, and a plating member disposed in at least one cavity among the cavities. The circuit pattern portion includes a circuit pattern and an insulating layer forming, for each of the through vias, an electrical connection path to the IC. |
| US10971824B2 |
Antenna element
The application provides an antenna element comprising a circuit board with a transmission line, the transmission line comprising at least a first conductor and a second conductor, a separate 3-dimensional, metallic or metallized ring-shaped structure mounted on a surface of the circuit board, a first galvanic contact between the first conductor and a first part of the separate 3-dimensional, metallic ring-shaped structure, and a second galvanic contact between the second conductor and a second part of the separate 3-dimensional, metallic ring-shaped structure, wherein at least one of the first galvanic contact and the second galvanic contact comprises at least two substantially L-shaped sections and an antenna array comprising several such antenna elements. |
| US10971821B2 |
Chip antenna module
A chip antenna module includes: a chip antenna including a body portion, a radiating portion, and a grounding portion, wherein the body portion is formed of a dielectric substance, and wherein the radiating portion and the grounding portion are disposed on different surfaces of the body portion from each other; and a substrate having a plurality of layers and including feeding pads bonded to the radiating portion, grounding pads bonded to the grounding portion, and dummy wiring layers disposed on at least one layer among the plurality of layers, below the feeding pads, wherein a resonance frequency of the chip antenna is determined by a number of the dummy wiring layers. |
| US10971820B2 |
Arrangement comprising antenna elements
An arrangement (10) comprising a first conductive antenna element (20), comprising at least one first slot (30; 31, 32, 33, 34; 35, 36) arranged in the first conductive antenna element (20), and a second conductive antenna element (80), comprising at least one second slot (90; 91, 92, 93, 94; 31; 32, 33, 34) arranged in the second conductive antenna element (80), is disclosed. At least one second slot (90; 91, 92) arranged in the second conductive antenna element (80) is coupled with at least one first slot (30; 35, 36) arranged in the first conductive antenna element (20) by means of at least one conductor (111, 112; 113, 114, 115, 116). |
| US10971819B2 |
Multi-band wireless signaling
An antenna system for transducing radio-frequency energy includes: a first antenna sub-system comprising a plurality of radiators and a ground conductor, each of the plurality of radiators being sized and shaped to transduce millimeter-wave energy between first wireless signals and first electrical current signals; and a second antenna sub-system comprising a first radiator configured to transduce sub-6 GHz energy between second wireless signals and second electrical current signals, wherein the first radiator comprises the ground conductor. |
| US10971818B2 |
Open cavity system for directed amplification of radio frequency signals
An apparatus is provided for transmission of RF signals between a transmitter and a receiver. The apparatus includes a transmitter comprising a first retroreflector having a first array of sub-wavelength retroreflective elements at one end of an open cavity for transmitting RF seed signals. The apparatus also includes a receiver comprising a second retroreflector having a second array of sub-wavelength retroreflective elements at an opposite end of the open cavity for receiving the transmitted seed signal, the transmitted RF seed signals being in form of a beam directed toward the receiver. |
| US10971817B2 |
Antenna-to-beamformer assignment and mapping in phased array antenna systems
In one embodiment of the present disclosure, a phased array antenna system includes a first portion carrying an antenna lattice including a plurality of antenna elements, wherein the plurality of antenna elements are arranged in a first configuration, a second portion carrying a beamformer lattice including a plurality of beamformer elements, wherein the plurality of beamformer elements are arranged in a second configuration different from the first configuration, and a third portion disposed between the first portion and the second portion carrying at least a portion of a mapping including a first plurality of mapping traces on a first surface providing at least a portion of the electrical connection between the plurality of antenna elements and the plurality of beamformer elements, wherein each of the plurality of antenna elements are electrically coupled to one of the plurality of beamformer elements. |
| US10971813B2 |
Switchable patch antenna
A switchable patch antenna comprises a planar conductor having an aperture (hole) formed in the middle of the planar conductor. Radiation of a sinusoidal signal is controlled by comparison of separate impedance values for two components that have separate impedance values. Each of the two components have one end coupled together at the terminal positioned at a center of the aperture and their other ends separately coupled to opposing edges of the aperture. A sinusoidal signal source is also coupled to the terminal positioned at the aperture's center. Further, when the impedance values of both components are substantially equivalent, radiation by the antenna of the provided signal and/or mutual coupling of other signals is disabled. Also, when an impedance value of one of the two components is substantially greater than the other impedance value of the other component, the provided signal is radiated and/or mutual coupling is enabled. |
| US10971812B2 |
Broadband antenna system
A broadband and multiband antenna of reduced dimension, preferably to be used as external antenna for vehicles is disclosed. The antenna system includes an antenna comprising: a planar ground plane, a planar radiating element having a configuration formed by a central segment and first and second lateral segments extending from the central segment. A feed connection line is connected between the central segment and an edge of the ground plane, and a ground connection line is connected between the central segment and said edge of the ground plane. |
| US10971811B1 |
5G membrane radio shroud
The present invention is a pole-mountable shroud assembly enclosing one or more wireless telecommunications transceivers and antennas. The shroud assembly is attached to the pole by a pole bracket, which is an elongated rectangular prism frame. The outer face of the pole bracket is open, so as to expose at least one intake fan supported by the pole bracket. The top and bottom ends of the pole bracket support top and bottom panels, respectively, with the bottom panel having multiple holes and/or vents, through which the intake fan(s) draw ambient air to cool the transceivers. A jacking means, such as a screw jack, connects the bottom panel to the pole bracket bottom end so that the panel separation distance is adjustable. A very thin (not more than one-tenth the minimum transmission wavelength) fabric membrane wraps around the top and bottom panels to the longitudinal sides of the pole bracket, so as to form a generally rectangular prism shaped shroud enclosure which surrounds the transceivers/antennas. The jacking means is operative to tension the fabric membrane around the shroud enclosure. |
| US10971809B2 |
Electronic device including antenna connected with conductive sheet of display panel
An electronic device includes glass comprising at least a front surface of the electronic device, a display panel disposed under the glass, a conductive sheet attached to the display panel or integrated into the display panel, a support including a first portion comprising a side surface of the electronic device and a second portion comprising a mounting space for parts, in which the first portion of the support includes a metal portion comprising a radiator, and insulation portions disposed at opposite ends of the metal portion, and the second portion of the support includes at least one via hole or recess, a printed circuit board (PCB) including a ground, wireless communication circuitry disposed on the PCB, at least one processor operatively connected with the wireless communication circuitry, a flexible printed circuit board (FPCB) electrically connected with the conductive sheet to operatively connect the display panel with the at least one processor, and a cover comprising a rear surface of the electronic device. The glass, the display panel, and the conductive sheet are seated on a first surface of the second structure of the supporting member. The PCB and the cover of the electronic device are seated on a second surface of the second portion. The second portion of the support electrically connects the support with the ground of the PCB by making contact with one of conductive contacts of the PCB on at least one point. The FPCB includes a first path extending from the first surface to the second surface through the at least one via hole or the recess of the support. The first path of the FPCB extending to the second surface electrically connects the conductive sheet with the ground of the PCB. The conductive sheet is electrically connected with the metal portion of the support through a selection part comprising selective connection circuitry. The wireless communication circuitry receives a signal having a specific frequency band based on an electrical path comprising the wireless communication circuitry, the metal portion of the support, the selection part, and the conductive sheet. |
| US10971807B2 |
Mobile device
A mobile device includes a metal mechanism element, a dielectric substrate, and a feeding radiation element. The metal mechanism element has an open slot. The open slot substantially has an L-shape. The dielectric substrate is adjacent to the metal mechanism element. The feeding radiation element has a feeding point. The feeding radiation element is disposed on the dielectric substrate. The feeding radiation element at least partially extends along the open slot. An antenna structure is formed by the feeding radiation element and the open slot of the metal mechanism element. The antenna structure covers a first frequency band, a second frequency band, and a third frequency band. |
| US10971803B2 |
Omnidirectional antenna system for macro-macro cell deployment with concurrent band operation
In one embodiment, an apparatus includes a first omnidirectional antenna for coupling to a first radio to establish a first macro cell and a second omnidirectional antenna for coupling to a second radio to establish a second macro cell. The first and second omnidirectional antennas are configured for concurrent 5 GHz radio operation while maintaining at least 40 dB of isolation between the first and second omnidirectional antennas. An antenna system and network device are also disclosed herein. |
| US10971802B2 |
Multiband base station antenna
The present invention relates to a base station antenna comprising: a reflective plate; at least one first band radiation element positioned on the upper surface of the reflective plate, including a first power feed unit, and having a first wavelength (λH); and at least one second band radiation element positioned on the upper surface of the reflective plate, including a second power feed unit, and having a second wavelength (λL), wherein the first power feed unit is connected to a power feed line on the lower surface of the reflective plate, and the power feed line is shorted with the reflective plate at a short point spaced apart at a preset interval from the first band radiation element. |
| US10971798B2 |
Semiconductor device package and method of manufacturing the same
A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed. |
| US10971793B2 |
Deployable structure for use in establishing a reflectarray antenna
A deployable structure for use in establishing a reflectarray antenna is provided that includes a flexible reflectarray and a deployment structure that includes an endless pantograph for deploying the flexible reflectarray from a folded, undeployed state towards a deployed state in which the flexible reflectarray is substantially planar. In a particular embodiment, the deployment structure includes a plurality of tapes that engage the endless pantograph and are used to establish a positional relationship between the deployed reflectarray and another component of the reflectarray antenna. |
| US10971792B2 |
First and second dielectric waveguides disposed in respective multi-layer substrates which are connected by a connection structure having choke structures therein
Provided is a structure configured to electrically connect multi-layer dielectric waveguides, each including a dielectric waveguide formed of conductor patterns and vias in a laminating direction of the multi-layer dielectric substrate, in which the vias for forming part of a waveguide wall of each of the dielectric waveguides are arranged in a staggered pattern in the multi-layer dielectric substrate side having choke structures formed so as to electrically connect the waveguides to each other. |
| US10971791B1 |
Transmission line for high power tuners
Impedance tuners used in high power measurements suffer fast heating and consequently mostly linear thermal expansion of the central conductor, which has a very small mass and is thermally isolated from the slabline walls and the tuner housing. This leads to false measurements or catastrophic tuner failure (short) of either the DUT or the tuner. Gold plated INVAR and SUPER-INVAR center conductor material is preferred to traditional stainless-steel rod. The body of the airline is made of high conductivity low cost Aluminum. INVAR type alloys quasi eliminate the thermal expansion, reducing it by a factor between 10 and 40 compared to Steel. Practical tests have shown significant improvement in thermal behavior. |
| US10971786B2 |
Isolative shield with positional control features for welded flexible cell tabs in an HV battery cell stack
A cell stack includes adjacent first and second battery cells respectively having a positive cell tab, a negative cell tab, and an outer surface. The outer surfaces are flush. The positive cell tab of the first battery cell protrudes from the outer surface of the first battery cell, and the negative cell tab of the second battery cell protrudes from the outer surface of the second battery cell. An isolative shield is positioned adjacent to the outer surfaces, and defines through-slots receiving therein a respective one of the cell tabs. A method includes providing the cell stack, inserting the cell tabs into the pair of through-slots of the isolative shield, positioning a primary surface of the isolative shield adjacent to the outer surfaces of the adjacent battery cells after inserting the cell tabs, and affixing the primary surface of the isolative shield to the cell stack. |
| US10971781B2 |
Secondary battery
A secondary battery is disclosed.According to the present invention, in a case in which the secondary battery is ignited, a gas and materials within the secondary battery may be smoothly discharged to improve safety when the secondary battery is ignited.In order to achieve the above-described object, according to an aspect of the present invention, a secondary battery includes: an electrode assembly; a battery can accommodating the electrode assembly; and a coating part applied to the battery can, wherein the battery can includes a slim part having a relatively thinner thickness than that of the other region of the battery can, and the coating part is applied to the slim part and made of a metal material having tensile strength less than that of the slim part. |
| US10971778B2 |
Battery pack
Disclosed is a battery pack configured to prevent its components such as a cell assembly from being broken or damaged even though a physical force such as vibrations and impacts is applied to the battery pack. The battery pack includes a cell assembly having a plurality of secondary batteries; an electronic component plate having a plate shape and configured to allow at least one electronic component to be mounted thereon; a lower housing configured to have an inner space with an open top and to accommodate the cell assembly and the electronic component plate therein; and an upper housing configured to cover the open top of the lower housing, wherein coupling members are respectively provided between a lower portion of the cell assembly and the lower housing, between an upper portion of the cell assembly and the electronic component plate, between the electronic component plate and the upper housing, and between the lower housing and the upper housing to couple and fix each other. |
| US10971777B2 |
Traction battery support assembly and method
An exemplary support assembly includes a first housing that supports a first battery structure, a second housing that supports a second battery structure, a cover, and a common attachment that secures together the first housing, the second housing, and the cover. An exemplary support method includes securing together a first housing, a second housing, and a cover with a common attachment. The first housing supports a first battery structure that is enclosed by the second housing. The second housing supports a second battery structure that is enclosed by the cover. |
| US10971775B2 |
Air electrode, metal-air battery, and method for producing air electrode
A method for producing an air electrode includes a kneading step of kneading an oxygen reduction catalyst, a conductive auxiliary agent, and a water-repellent resin (binder) in a water solvent; and a rolling step of rolling with a roller the kneaded product produced in the kneading step. The rolling step includes rolling the kneaded product with the roller several times in many directions (at least two or more different rolling directions). In the formed air electrode, the water-repellent resin is fiberized in the air electrode, and the fibers thereof are oriented in many directions to form a netlike shape. |
| US10971762B2 |
Electrode design for L-ion battery
A Li-ion battery includes a cathode; an anode having a primary active material, conductive carbon, binder, and reserve material; and a separator between the cathode and anode. The reserve material has a reaction potential between a lithium reaction potential and a primary active material reaction potential. The reserve material is configured to intercalate with lithium at the reaction potential responsive to the primary active material being fully intercalated to inhibit lithium plating on the anode. |
| US10971760B2 |
Hybrid solid-state cell with a sealed anode structure
A monolithic ceramic electrochemical cell housing is provided. The housing includes two or more electrochemical sub cell housings. Each of the electrochemical sub cell housing includes an anode receptive space, a cathode receptive space, a separator between the anode receptive space and the cathode receptive space, and integrated electron conductive circuits. A first integrated electron conductive circuit is configured as an anode current collector within the anode receptive space. A second integrated electron conductive circuit is disposed as a cathode current collector within the cathode receptive space. |
| US10971759B2 |
Device for battery formation
The present disclosure provides a device for battery formation, which comprises a base plate, a press plate, a positioning block and a connecting assembly. The press plate is connected with the base plate, the positioning block and the connecting assembly each are provided as plurality in number and the plurality of the connecting assemblies correspond to the plurality of positioning blocks. The positioning block has a main portion and a protruding portion, the main portion is provided between the base plate and the press plate, and the protruding portion extends from a surface of the main portion away from the press plate. The base plate is provided with a plurality of positioning holes, and the protruding portion of each positioning block is inserted into the positioning hole. Each connecting assembly is provided to the main portion of a corresponding positioning block and used for being connected to a battery. |
| US10971755B2 |
Secondary battery-use electrolytic solution, secondary battery, battery pack, electric vehicle, electric power storage system, electric power tool, and electronic apparatus
A secondary battery includes a cathode, an anode, and a nonaqueous electrolytic solution. The nonaqueous electrolytic solution includes a compound represented by M+[(Z1Y1)(Z2Y2)N]− (where M is a metal element, each of Z1 and Z2 is one of groups such as as a fluorine group, and each of Y1 and Y2 is one of groups such as a sulfonyl group), a compound such as a compound represented by R1-CN (where R1 is a monovalent hydrocarbon group), and a compound such as a compound represented by R22-(CN)n (where R22 is an n-valent hydrocarbon group, and n is an integer of 2 or more). A content of the compound represented by [(Z1Y1)(Z2Y2)N]− in the nonaqueous electrolytic solution is within a range of 2.5 mol/dm3 to 6 mol/dm3 both inclusive. |
| US10971753B2 |
Negative electrode for lithium metal battery, method of preparing negative electrode, and lithium metal battery including the same
A negative electrode for a lithium metal battery, the negative electrode including: a lithium metal layer including lithium metal or a lithium metal alloy; and a protective layer on at least a portion of the lithium metal layer, wherein the protective layer includes a plurality of composite particles having a particle size of greater than about 1 micrometer to about 100 micrometers or less, wherein a composite particle of the plurality of composite particles comprises a particle comprising an organic particle, an inorganic particle, an organic-inorganic particle, or combination thereof; and a coating layer disposed on at least a portion of a surface of the particle, the coating layer including an ion conductive material including an ion conductive oligomer including an ion conductive unit, an ion conductive polymer including an ion conductive unit, or a combination thereof. |
| US10971746B2 |
Fuel cell system for modulating offset of hydrogen pressure sensor and method for modulating offset of hydrogen pressure sensor
A fuel cell system for modulating an offset of a hydrogen pressure sensor is provided. The fuel cell system includes a stack with a plurality of cells and each cells includes a first electrode to which hydrogen is supplied, a second electrode to which oxygen is supplied, and a membrane electrode assembly arranged between the first and second electrodes to produce electricity by reaction between the hydrogen and the oxygen. The hydrogen pressure sensor is connected to each cell to sense a pressure of the hydrogen supplied to the first electrode. A controller that which of the cells is supplied with insufficient pressure of hydrogen and modulates the offset of the hydrogen pressure sensor connected to the cell to which the hydrogen is supplied with insufficient pressure, to then supply the hydrogen to the first electrode at an appropriate pressure. |
| US10971743B2 |
System and method for controlling performance of fuel cell stack
A system and method of controlling a performance of a fuel cell stack is provided. In particular, the output performance of the fuel cell stack is determined by comparing the difference between an initial voltage and a voltage after a predetermined time lapses with the difference between the initial voltage and a preset minimum voltage. |
| US10971741B2 |
Fuel cell system
A fuel cell system includes: a fuel cell; a fuel gas supply path supplying the fuel gas to the fuel cell; a recycling path returning discharged anode off-gas to an entrance of the fuel cell; an anode off-gas discharge path branching from the recycling path and discharging the anode off-gas to an outside; a first valve in the anode off-gas discharge path; a pressurizer pressurizing the anode off-gas; and a controller performing control to cause the pressurizer to act in at least one of a timing in execution of a purge action supplying the fuel gas from the fuel gas supply path and discharging the anode off-gas to the outside in a first valve open state and a timing in prescribed time after the purge action and assessing abnormality based on a pressure of the recycling path or anode off-gas discharge path or an action amount of the pressurizer. |
| US10971739B2 |
Common flow field type fuel cell separator, fuel cell separator assembly, and fuel cell stack
Disclosed herein are a common flow field type fuel cell separator, a fuel cell separator assembly, and a fuel cell stack, including a flow field connected to a manifold in which an inlet and an outlet for each of hydrogen, air, and cooling water are formed, and configured such that flows of the hydrogen, the air, and the cooling water are free from interfering with each other. |
| US10971733B2 |
Rapid sulfur melt diffusion into carbon host for making electrodes
A free-standing electrically conductive porous structure suitable to be used as a cathode of a battery, including an electrically conductive porous substrate with sulfur diffused into the electrically conductive porous substrate to create a substantially uniform layer of sulfur on a surface of the electrically conductive porous substrate. The free-standing electrically conductive porous structure has a high performance when used in a rechargeable battery. A method of manufacturing the electrically conductive porous structure is also provided. |
| US10971727B2 |
Solvated graphene frameworks as high-performance anodes for lithium-ion batteries
A lithium-ion battery includes: 1) an anode; 2) a cathode; and 3) an electrolyte disposed between the anode and the cathode and including lithium ions. The anode includes a graphene framework film including interconnected graphene sheets, and the graphene framework film has a specific surface area of 600 m2 g−1 or more. |
| US10971725B2 |
Lithium metal secondary battery containing elastic polymer foam as an anode-protecting layer
Provided is a lithium metal secondary battery comprising a cathode, an anode, an electrolyte-separator assembly disposed between the cathode and the anode, wherein the anode comprises: (a) an anode active material layer containing a layer of lithium or lithium alloy optionally supported by an anode current collector; and (b) an anode-protecting layer in physical contact with the anode active material layer and in ionic contact with the electrolyte-separator assembly, having a thickness from 10 nm to 500 μm and comprising an elastic polymer foam having a fully recoverable elastic compressive strain from 2% to 500% and pores having a pore volume fraction from 5% to 95% (most preferably 50-95%); wherein preferably the pores are interconnected. |
| US10971720B2 |
Positive electrode active material, lithium ion secondary battery, and method of producing positive electrode active material
A positive electrode active material includes secondary particles. The secondary particles include a plurality of primary particles. The primary particles include a lithium-containing composite metal oxide. Inside the secondary particles, an electron conducting oxide is disposed at at least a part of a grain boundary between the primary particles. The electron conducting oxide has a perovskite structure. |
| US10971718B2 |
Electrochemical energy storage devices
An energy storage device includes a cathodic material in an activated state; and an anodic material in an activated state; wherein: the cathodic material is covalently attached to, or confined within, a first polymer matrix, the first polymer matrix is configured to prevent or minimize substantial diffusion of the cathodic material in the activated state; and the anodic material is a phenazine, a phenothiazine, a triphenodithiazine, a carbazole, a indolocarbazole, a biscarbazole, or a ferrocene covalently attached to, or confined within, a second polymer matrix, the second polymer matrix is configured to prevent or minimize substantial diffusion of the anodic material in the activated state. |
| US10971714B2 |
Battery pack and a pre-assembled electrical connection unit for the battery pack
A pre-assembled electrical connection unit for a battery pack includes a bus bar defining a hole, and a cage defines a cavity. The unit also includes a fastener disposed in the cavity and the cage surrounds the fastener. The cage is secured to the bus bar, and the fastener is positioned in the hole and the cavity in an initial position. The fastener is movable to a final position relative to the cage which positions the fastener deeper in the hole of the bus bar. The unit is positioned relative to the battery pack, and the battery pack includes a module terminal. The module terminal includes a terminal nut that is accessible during an assembly process. The unit is placed over the terminal nut during the assembly process such that the fastener aligns with the terminal nut and secures the bus bar to the module terminal in the final position. |
| US10971710B2 |
All-solid battery and method of manufacturing the same
A method of manufacturing the all-solid battery includes steps of: forming a cathode layer; forming an anode layer; forming an electrolyte layer between the cathode layer and the anode layer; and forming an insulation layer using a baroplastic polymer at an edge portion of the battery. The step of forming the insulation layer comprises: forming a coating layer through coating of the edge portion of the battery with the baroplastic polymer; and shaping the baroplastic polymer through pressing of the coating layer. |
| US10971708B2 |
Release layer for preparation of ion conducting membranes
A method includes applying to a substrate a solution including a polymeric compound to form a release layer on the substrate; applying ion-conducting elements on the release layer; applying a matrix polymer on the release layer, wherein the matrix polymer surrounds at least some of the ion-conducting elements; and removing the release layer to separate the matrix polymer from the substrate such that the ion-conducting elements remain embedded in a carrier layer of the matrix polymer and form an ion-conducting membrane. |
| US10971698B2 |
OLED display panel and manufacturing method for the same
An OLED display panel and manufacturing method are provided. Through disposing a light-shielding film on the packaging cover plate to prevent the laser from illuminating on the electrodes of the MED substrate during the laser scanning of the sealant to effectively protect the electrode. A portion of the light shielding film that overlaps with the thin layer region of the sealant has gradually decreasing light transmittance, which can prevent the problem that the thin layer region of the sealant is scorched by excessive laser energy, sufficiently ensures that the packaging effect, and reduces the generation of particles. In addition, the surface of the light-shielding film irradiated with laser light is a frosted surface, which can cause diffused reflection of the laser light irradiated on the light-shielding film to prevent the laser from directly reflecting on the laser head and protect the laser head from being burned and damaged. |
| US10971696B2 |
Display device
A flexible display panel is disclosed. The flexible display panel includes a substrate and a pixel unit on a first surface of the substrate. An encapsulation layer is on the first surface of the substrate and covers the pixel unit. A support member is on a second surface of the substrate that is opposite the first surface. The support member overlaps an edge of the encapsulation layer. The support member reduces stress applied to areas of the flexible display panel that are vulnerable to cracking during bending of the flexible display panel. |
| US10971695B2 |
Multilayer reflection electrode film, multilayer reflection electrode pattern, and method of forming multilayer reflection electrode pattern
A multilayer reflection electrode film includes a Ag film that is formed of Ag or an Ag alloy; and a transparent conductive oxide film that is disposed on the Ag film, in which the transparent conductive oxide film is formed of an oxide that includes Zn and Ga and further includes one element or two or more elements selected from the group consisting of Sn, Y, and Ti. |
| US10971691B2 |
Display device and manufacturing method of the same
A display device comprises: a light emitting array including a plurality of light emitting elements on a substrate and an insulating pattern disposed between the light emitting elements; a color conversion array including a plurality of sub-color conversion parts corresponding to the respective light emitting elements; and a printed circuit board having a first contact electrode connected to each of the light emitting elements, the printed circuit board driving the light emitting elements, wherein the plurality of sub-color conversion parts include first to third sub-color conversion parts that convert the light provided from corresponding light emitting elements into lights of first to third colors and emitting the converted lights, wherein each of the plurality of light emitting elements is electrically insulated from an adjacent light emitting elements. |
| US10971687B2 |
Organic electroluminescent materials and devices
A compound selected from the group consisting of wherein at least one of RG or at least one of RJ of Formula II includes a structure of Formula III, wherein the structure of Formula II forms a direct bond to Formula III through a carbon of one of X21 to X24, a carbon of one of X25 to X28, or RN, or optionally, the structure of Formula II is linked to Formula III through a carbon of one of X21 to X24, a carbon of one of X25 to X28, or RN, by an aromatic linker An organic light emitting diode/device (OLED) with an organic layer disposed between an anode and a cathode. The organic layer includes a compound of Formula I or Formula II. The OLED can be incorporated into one or more of a consumer product, an electronic component module, and/or a lighting panel. |
| US10971686B2 |
Organic semiconductor element, polymer, organic semiconductor composition, and organic semiconductor film
Provided are an organic semiconductor element including an organic semiconductor film that includes a polymer having a repeating unit represented by the following Formula (1), the polymer, and an organic semiconductor composition and an organic semiconductor film including the polymer. In the formula, Z represent a 5-membered aromatic heterocycle. RC1 and RC2 each independently represent a halogen atom, an alkyl group, an alkenyl group, an alkynyl group, an aromatic hydrocarbon group, or an aromatic heterocyclic group. n1 and n2 each independently represent 0 or 1. RC3 to RC10 each independently represent a hydrogen atom, a halogen atom, an alkyl group, an alkenyl group, an alkynyl group, an aromatic hydrocarbon group, or an aromatic heterocyclic group. |
| US10971683B2 |
Methods for forming narrow vertical pillars and integrated circuit devices having the same
In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material. |
| US10971679B2 |
Magnetoresistive effect element
A magnetoresistive effect element, which includes: a first ferromagnetic layer as a magnetization fixed layer; a second ferromagnetic layer as a magnetization free layer; and a nonmagnetic spacer layer provided between the first ferromagnetic layer and the second ferromagnetic layer. The nonmagnetic spacer layer includes an Ag alloy represented by General Formula (1), and thereby lattice mismatch between the nonmagnetic spacer layer, and the first ferromagnetic layer and/or the second ferromagnetic layer is reduced, compared to lattice mismatch when the nonmagnetic spacer layer is formed of Ag, AgγX1-γ (1) where X indicates one element selected from the group made of Al, Cu, Ga, Ge, As, Y, La, Sm, Yb, and Pt, and 0<γ<1. |
| US10971676B2 |
Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region
A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly. |
| US10971675B2 |
Dual function magnetic tunnel junction pillar encapsulation
Magnetic tunnel junction pillars are encapsulated by an oxidized diffusion barrier layer. Oxygen within the encapsulating material is used to oxidize metallic residue outside the pillars, converting the residue to a non-conductive material such as a metal oxide or metal oxynitride. Selective deposition of manganese on the metal layers of the pillars can be followed by oxidation of the manganese to form a manganese oxide diffusion barrier. Alternatively, manganese deposition can be followed by deposition of silicon dioxide and subsequent annealing to form a manganese silicate diffusion barrier. |
| US10971673B2 |
Piezoelectric element, piezoelectric device, ultrasonic probe and electronic apparatus
A piezoelectric element has a first electrode layer, a piezoelectric layer on the first electrode layer, a second electrode layer on the piezoelectric layer, a third electrode layer on part of the second electrode layer and including third metal, and an insulating layer covering at least a part of the piezoelectric layer not provided with the second electrode layer and having an aperture exposing a part of the second electrode layer. The second electrode layer has a first layer including first metal and a second layer including second metal on the first layer. The second layer is exposed in the aperture. A difference in standard redox potential between the second metal and the third metal is smaller than a difference in standard redox potential between the first metal and the third metal. |
| US10971671B2 |
Thermoelectric conversion module and vehicle including the same
A thermoelectric conversion module may include a plurality of n type thermoelectric conversion materials and a plurality of p type thermoelectric conversion materials that are disposed alternately, and a plurality of electrodes that connects the plurality of thermoelectric conversion material disposed alternately on one side and on an opposite side alternately, wherein the plurality of electrodes includes a first electrode configured to electrically connect the n type thermoelectric conversion material and the p type thermoelectric conversion material by penetrating the n type thermoelectric conversion material and the p type thermoelectric conversion material to transfer heat obtained from a heat source to the plurality of thermoelectric conversion materials. |
| US10971668B2 |
Light-emitting device package including a lead frame
A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure. |
| US10971665B2 |
Photon extraction from nitride ultraviolet light-emitting devices
In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die. |
| US10971662B2 |
Light emitting diode package and method of manufacturing the same
A light-emitting diode (LED) package includes a light-emitting structure, a transmissive material layer on the light-emitting structure, and a support structure covering at least a portion of a side surface of the transmissive material layer, a side surface of the light-emitting structure, and at least a portion of a bottom surface of the light-emitting structure. |
| US10971649B2 |
Semiconductor device and light emitting device package comprising same
An embodiment relates to a semiconductor device and a light emitting device package including the same. The semiconductor device according to the embodiment may include: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer and including V-pits; an active layer disposed on the second semiconductor layer; a third semiconductor layer having a bandgap wider than that of the active layer on the active layer; a fourth semiconductor layer having a band gap narrower than that of third semiconductor layer on the third semiconductor layer; and a fifth semiconductor layer having a bandgap wider than that of the fourth semiconductor layer on the fourth semiconductor layer, wherein the third semiconductor layer and the fifth semiconductor layer include an aluminum composition, and the fifth semiconductor layer has a bandgap equal to or wider than that of the third semiconductor layer. |
| US10971648B2 |
Ultraviolet light-emitting element and light-emitting element package
An embodiment relates to an ultraviolet light-emitting device, a method for manufacturing the ultraviolet light-emitting element, a light-emitting element package, and a lighting device. An ultraviolet light-emitting element according to an embodiment includes: a first conductive type first semiconductor layer having a light extraction structure; an etching-blocking layer on the first conductive type first semiconductor layer; a first conductive type second semiconductor layer on the etching-blocking layer, an active layer on the first conductive type second semiconductor layer; a second conductive type semiconductor layer on the active layer; and an electron spreading layer disposed between the etching-blocking layer and the active layer, wherein the electron spreading layer includes a first conductive type or an undoped AlGaN-based or a GaN-based semiconductor layer, an undoped AlN, and a first conductive type AlGaN-based second semiconductor layer. |
| US10971643B2 |
Implementation of an optimized avalanche photodiode (APD)/single photon avalanche diode (SPAD) structure
A semiconductor device, sensor, and array of SPAD cubes are described. One example of the disclosed semiconductor device includes an array of single-photon avalanche diodes, each single-photon avalanche diode including an undepleted anode region, an undepleted cathode region, an active depleted region positioned between the anode region and cathode region, and at least one conductive trench extending between the anode region and cathode region. In some examples, the at least one conductive trench surrounds the active depleted region and reflects light back into the active depleted region such that one or more photons can be absorbed within the active depleted region even though an absorption coefficient of the light is greater than a thickness of the active depleted region. |
| US10971642B2 |
Opto-electronic unit composed of an opto-photonic platform
The solar photovoltaic photoconverter unit (1) comprises a light processing opto-photonic platform (2) realized by at least one transparent substrate (8) is having on, at least one, of its faces a digital diffractive grating constituted by slanted ribs (11) that are modulated to harvest a maximum of solar light at any angle of incidence to split it into several spectral sub-bands, to guide and to concentrate individually every one of these spectral sub-band, toward a separate output of the opto-photonic platform (2) for allowing its exploitation by a light-to-electricity conversion unit (3) that will have by optimization a grate overall conversion efficiency. The opto-photonic platform (2) also includes photonic converters (13) and (14) converting ultraviolet light into visible light and also infrared light in visible light for a better exploitation of the energy present in the solar light and so increasing the light to electricity conversion. The solar photovoltaic photoconverter unit (1) comprises also a light-to-electricity converter unit (3). |
| US10971639B2 |
Method of mounting an electrical component on a base part
A method of mounting an electrical component on a base part having an inclined support surface is provided, in which method a first wedge surface of a wedge element is arranged on the support surface and a lateral force is exerted on the wedge element so that the first wedge surface moves on the support surface until a second wedge surface of the wedge element remote from the support surface reaches a desired position, and wherein the electrical component is arranged on the second wedge surface. In this respect, a first fastening element of the wedge element is fixed to the base part and the lateral force is afterward no longer exerted. |
| US10971636B2 |
Photoelectric detection structure, manufacturing method therefor, and photoelectric detector
A photoelectric detection structure, a manufacturing method therefor, and a photoelectric detector. The photoelectric detection structure includes: a base substrate; an electrode strip, which is located on the base substrate; a semiconductor layer, which is located at a side of the base substrate that faces the electrode strip; an insulating layer, which is located between the electrode strip and the semiconductor layer, the insulating layer including a thickness-increased portion, and the thickness-increased portion being located on at least one edge of the electrode strip. |
| US10971635B2 |
Conductive polymer nanowires—graphene hybrids with improved optoelectronic properties
A photodetector including graphene and poly(3-hexylthiopene) (P3HT) nanowires is claimed. A method of making the hybrid photodetector is also claimed. |
| US10971634B2 |
Oxide semiconductor device and method of manufacturing oxide semiconductor device
An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer. |
| US10971632B2 |
High voltage diode on SOI substrate with trench-modified current path
A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region. |
| US10971628B2 |
FinFET device with T-shaped fin
A semiconductor device structure is provided. The semiconductor device structure includes an isolation feature over a substrate and a fin structure protruding from the substrate and partially surrounded by the isolation feature. The fin structure includes a first portion above the isolation feature and having a first width. The fin structure also includes a second portion extending from a top of the first portion and having a second width greater than the first width, so that the fin structure above the isolation feature has a T-shaped profile. The semiconductor device structure also includes a gate structure covering the first portion and the second portion of the fin structure. |
| US10971624B2 |
High-voltage transistor devices with two-step field plate structures
High-voltage transistor devices with two-step field plate structures and methods of fabricating the transistor devices are provided. An example high voltage transistor device includes: a gate electrode disposed over a substrate between a source region and a drain region, a first film laterally extending from over the gate electrode to over a drift region laterally arranged between the gate electrode and the drain region, a second film laterally extending over a portion of the drift region adjacent to the drain region and away from the gate electrode, and a field plate laterally extending from over the first film to over the second film. A first thickness vertically from a top surface of the gate electrode to a bottom surface of the field plate is smaller than a second thickness vertically from a top surface of the portion of the drift region to the bottom surface of the field plate. |
| US10971622B2 |
Transistor structures
A transistor structure includes a substrate and a fin structure on the substrate. The fin structure includes an undoped portion, a first doped portion, and a second doped portion. The transistor structure includes an electrode on the fin structure between the first doped portion and the second doped portion, and an insulating layer on the fin structure. The transistor structure includes a first trench in the insulating layer at a first side of the fin structure and between the electrode and the second doped portion, and a second trench in the insulating layer at a second side of the fin structure and between the electrode and the second doped portion. The first trench includes a first conductive material, and the second trench includes a second conductive material. |
| US10971621B2 |
Semiconductor device
A semiconductor device includes a semiconductor body, first and second electrodes, and first and second control electrodes. The first and second electrodes are provided on the semiconductor body. The first and second control electrodes each include a first portion positioned between the semiconductor body and the first electrode, a second portion positioned between the semiconductor body and the second electrode, and a third portion linked to the first and second portions. The semiconductor body includes first to fourth semiconductor layers. The second semiconductor layer is provided on the first semiconductor layer, and extends along the first to third portions. The fourth semiconductor layer is provided selectively on the second semiconductor layer, and extends along the second and third portions. The fourth semiconductor layer includes second conductivity-type impurities with a higher concentration than a concentration of second conductivity-type impurities in the second semiconductor layer. |
| US10971614B2 |
High electron mobility transistor with reverse arrangement of channel layer and barrier layer
A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer. |
| US10971608B2 |
Semiconductor device
A semiconductor substrate has a first surface and a second surface provided with an opening of a trench. A first-conductivity-type carrier storage layer is provided on the second surface side of a first-conductivity-type drift layer. A second-conductivity-type base layer is provided on the second surface side of the carrier storage layer and reaches the second surface. A first-conductivity-type impurity layer is provided on the second surface side of the base layer. A trench electrode is provided in the trench via an internal insulating film. The internal insulating film has a first thickness at a portion facing the base layer, has a second thickness at a portion facing the drift layer, and has the first thickness and the second thickness at a portion facing the carrier storage layer. The second thickness is thicker than the first thickness. |
| US10971603B2 |
Wavy channel flexible thin-film-transistor on a flexible substrate and method of producing such a thin-film-transistor
A method for producing a thin-film-transistor involves forming a flexible substrate on a rigid substrate, forming a plurality of fins and trenches in a structural layer arranged on the flexible substrate, forming a wavy gate layer, channel layer, source contact layer, and drain contact layer on each of the plurality of fins and each of a plurality of trenches of the structural layer, and removing the plurality of fins and trenches having the wavy gate, channel, source contact, and drain contact layers from the rigid substrate. |
| US10971602B2 |
High-k metal gate process and device
An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed. |
| US10971600B2 |
Selective gate spacers for semiconductor devices
Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material. |
| US10971599B2 |
Power semiconductor device with self-aligned source region
An auxiliary layer is formed above a semiconductor body surface of a semiconductor body, the auxiliary layer being coupled to the semiconductor body and having an auxiliary layer surface. Trenches extend from the auxiliary layer surface along a vertical direction through the auxiliary layer into the semiconductor body, wherein two facing trench sidewalls of two adjacent trenches laterally confine a mesa region of the semiconductor body along a first lateral direction, each adjacent trench including a trench section protruding out of the semiconductor body surface. The trenches are filled with a trench filler material which is planarized to expose the auxiliary layer. The auxiliary layer is removed to least partially while maintaining the protruding trench sections. The mesa region is subjected to an implantation tilted by an angle of at least 10°, the protruding trench sections of the adjacent trenches serving at least partially as a mask during the implantation. |
| US10971597B2 |
Self-aligned base and emitter for a bipolar junction transistor
Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter. |
| US10971596B2 |
Semiconductor device with reduced flicker noise
In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region. |
| US10971594B2 |
Semiconductor device having modified profile metal gate
A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height. |
| US10971592B2 |
Semiconductor device with gate electrode having side surfaces doped with carbon
A semiconductor device includes a gate insulating film on a semiconductor substrate, and a gate electrode on the gate insulating film. The gate electrode includes a first layer containing polycrystalline silicon, a second layer between the first layer and the gate insulating film and containing polycrystalline silicon and carbon, a third layer on an upper surface of the first layer and containing polycrystalline silicon and carbon, a fourth layer on a first side surface of the first layer and containing polycrystalline silicon and carbon, and a fifth layer on a second side surface of the first layer and containing polycrystalline silicon and carbon. |
| US10971587B2 |
GaN lateral vertical JFET with regrown channel and dielectric gate
A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel. |
| US10971586B2 |
Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same
In at least one cell region, a semiconductor device includes fins and at least one overlying gate structure. The fins (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fins have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region. |
| US10971585B2 |
Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates
Embodiments of the invention are directed to a nano sheet semiconductor device fabrication method that includes forming a gate spacer along a gate region of the nanosheet FET device. Channel nanosheet is formed such that each one has a desired final channel nanosheet width dimension (Wf). An inner spacer is formed between the channel nanosheets. Forming the gate spacer and the inner spacer includes, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material along a sidewall of the gate region, along sidewalls of the channel nanosheets, and within a space between the channel nanosheets. The gate spacer is formed from a portion of the layer of the spacer material along the sidewall of the gate region. The inner spacer is formed from a portion of the layer of the spacer material within the space between the channel nanosheets. |
| US10971584B2 |
Low contact resistance nanowire FETs
Systems and methods for forming a low contact resistance nanowire transistor are described. The transistor includes a gate formed over a substrate including a gate conductor. Gate spacers are formed on sides of the gate. At least one semiconductor nanowire is formed through the gate such that the at least one semiconductor nanowire extends through the gate conductor and the gate spacers and into source and drain regions grown from surfaces of the at least one semiconductor nanowire adjacent to sides of the gate to increase the surface area of the source drain region contacting the semiconductor nanowire. |
| US10971582B2 |
Method for forming a superjunction transistor device
A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer. |
| US10971581B2 |
Semiconductor device
A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring formed on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring. |
| US10971578B2 |
Capacitive electronic chip component
The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers. |
| US10971577B2 |
Adjustable multi-turn magnetic coupling device
According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn. The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor. |
| US10971568B2 |
Display device
The present disclosure provides a display device including a first display panel, a second display panel, at least one detection device, and a control module. The first display panel includes a first display area having first sub-pixel regions, the second display panel includes a second display area having second sub-pixel regions, and the second display panel is movable to at least partially overlap the first display panel. The detection device is disposed on at least one of the first and second display panels to detect a position of the other one and generate a relative position detection signal correspondingly. The control module is electrically connected to the detection device to receive the relative position detection signal and an image display signal from an image signal source, so as to generate a first display signal and a second display signal to respectively output to the first and second display panels. |
| US10971565B2 |
Pixel structure
A pixel structure includes a substrate, a thin film transistor disposed on the substrate and having a first end, a second end and a control end, a first signal line electrically connected to the first end of the thin film transistor, a second signal line electrically connected to the control end of the thin film transistor, a pixel electrode electrically connected to the second end of the thin film transistor, and a light shielding layer. At least one of the first end of the thin film transistor, the second end of the thin film transistor, the control end of the thin film transistor, the first signal line and the second signal line is formed of a conductive layer. The light shielding layer is disposed on a top surface and a sidewall of the conductive layer. The light shielding layer includes a photoresist and particles mixed within the photoresist. |
| US10971561B2 |
OLED display panel and display device
The present invention teaches an OLED display panel which includes an array substrate, an encapsulation cover, and an organic lighting unit sealed in between by encapsulation adhesive. The OLED display panel is characterized in that a chip bonding element is configured on the array substrate. The encapsulation cover is configured with electrically connected touch electrode layer and first connection electrodes. The organic lighting unit includes a pixel definition layer. Insulating support columns are disposed on the pixel definition layer. A second connection electrode is disposed on each support column electrically connecting the chip bonding element. Each support column reaches a first connection electrode so that the first connection electrode is electrically connected to the chip bonding element. The present invention also teaches a display device incorporating the above-described OLED display panel. |
| US10971560B2 |
Display device, apparatus and method for testing display device
Disclosed herein are a display device, an apparatus for testing a display device, and a method for testing a display device. A display device includes a first substrate having a display area and a non-display area defined thereon, the non-display area being on an outer side of the display area. The non-display area may include a plurality of test pads and a first dummy thin-film transistor electrically connected to the test pads. The first dummy thin-film transistor includes a dummy gate electrode, and a dummy source electrode and a dummy drain electrode insulated from the gate electrode and spaced apart from each other. A bending area is defined on the first substrate that at least partially traverses the display area and the non-display area, the bending area overlaps the first dummy thin-film transistor. |
| US10971556B1 |
Organic light-emitting display panel and organic light-emitting display device
An organic light-emitting display panel includes: pixel rows arranged sequentially along a first direction and high voltage signal lines extending along the first direction. Each pixel row includes pixel sets arranged along a second direction which intersects the first direction. Each pixel set includes first and second pixels arranged along the second direction. The first pixel includes first to third sub-pixels emitting different colors. The second pixel includes fourth to sixth sub-pixels emitting different colors. Each sub-pixel includes a pixel driving circuit and an organic light-emitting diode. The high voltage signal lines are electrically connected to the sub-pixels, so as to provide voltage signals to anodes of the organic light-emitting diodes for driving the sub-pixels to emit light. For the same pixel set, the third and fourth sub-pixels have the same color, and are electrically connected to the same third high voltage signal line. |
| US10971552B2 |
Display device
A display device may include a display module and a cushion layer. The display module may include a display panel, which includes a circuit layer, a light emitting device layer on the circuit layer, and an encapsulation layer encapsulating the light emitting device layer, and a window substrate, which is on the display panel. A pattern including a vibration attenuating line extending in a direction may be defined by the cushion layer, and the cushion layer may be below the display module. The vibration attenuating line may be spaced apart from an edge of the cushion layer by a first length, and the first length may be a value obtained by dividing a sound speed in the display module by a natural frequency of the display module. |
| US10971549B2 |
Semiconductor memory device having a vertical active region
Embodiments of the invention provide a semiconductor memory device. In some embodiments, the device includes a bottom electrode extending in a y-direction relative to top surface of a substrate and a top electrode extending in an x-direction relative to the top surface of the substrate. An active area is located at the cross-section between the bottom electrode and the top electrode and is located on vertical side walls extending in a z-direction of the semiconductor memory device with respect to the top surface of the substrate. An insulating layer is located in the active area in between the top electrode and the bottom electrode. |
| US10971547B2 |
Switch element, switching method and semiconductor device
This switch element includes a resistance change element, a first transistor, and a second transistor. The resistance change element includes: a metal deposition type resistance change film; a first electrode; and a second electrode. To the second electrode, a source or a drain of the second transistor is connected. The switch element has a first mode and a second mode, when a potential of the second electrode is made higher than that of the first electrode and the resistance change element is switched from the low resistance state to the high resistance state. The gate voltage is greater in the first mode than in the second mode, and a potential difference between the first and second electrodes is smaller in the first mode than in the second mode. |
| US10971545B2 |
Magnetoresistive stacks and methods therefor
A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks. |
| US10971543B2 |
Display device
A display device includes a substrate, an emissive layer; a plurality of color converting layers that share the emissive layer, a barrier arranged on the emissive layer between the plurality of color converting layers, a first insulating layer provided between the plurality of color converting layers and the emissive layer and a second insulating layer provided between the first insulating layer and the plurality of color converting layers. The barrier spatially separates the plurality of color converting layers from each other and the first insulating layer has a plurality of first openings respectively corresponding to the plurality of color converting layers. |
| US10971540B2 |
Method and systems for coupling semiconductor substrates
Systems and methods may be provided for coupling together semiconductor devices. One or more of the semiconductor devices may be provided with an array of bump contacts formed in an etch back process. The bump contacts may be indium bumps. The indium bumps may be formed by depositing a sheet of indium onto a surface of a device substrate, depositing and patterning a layer of photoresist over the indium layer, and selectively etching the indium layer to the surface of the substrate using the patterned photoresist layer to form the indium bumps. The substrate may be an infrared detector substrate. The infrared detector substrate may be coupled to a readout integrated circuit substrate using the bumps. |
| US10971539B2 |
Solid-state imaging device, method of driving solid-state imaging device, imaging system, and movable object
A solid-state imaging device includes a photon detector that operates in a Geiger mode and outputs an output signal in accordance with incidence of a photon, a quench element that causes the photon detector to transition to a non-Geiger mode in accordance with the output signal, a control unit that, when the photon detector transitions from a Geiger mode to a non-Geiger mode, switches the quench element from a detection mode, in which the quench element is in a relatively low resistance state and the photon detector detects a photon, to a hold mode, in which the quench element is in a relatively high resistance state and holds the output signal, and a signal processing circuit that performs a predetermined process on the output signal. |
| US10971538B2 |
PiN diode structure having surface charge suppression
A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes. |
| US10971537B2 |
Image sensors
An image sensor includes a semiconductor substrate including a pixel region and a pad region, a plurality of photoelectric conversion regions in the pixel region, an interconnect structure on a front surface of the semiconductor substrate, a pad structure in the pad region and on a rear surface of the semiconductor substrate, a through via structure in the pad region and electrically connected to the interconnect structure through the semiconductor substrate, and an isolation structure at least partially extending through the pad region of the semiconductor substrate from the rear surface of the semiconductor substrate. The isolation structure surrounds the pad structure and the through via structure in a plane extending parallel to the rear surface of the semiconductor substrate. |
| US10971535B2 |
Image sensor package
An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire. |
| US10971533B2 |
Vertical transfer gate with charge transfer and charge storage capabilities
In an embodiment, an image sensor includes a semiconductor region, a first doped region disposed over the semiconductor region, a ring shaped well disposed over the first doped region and surrounding parts of the first doped region, a second doped region formed within the ring shaped well and disposed over the first doped region, and a third doped region disposed over the second doped region. The ring shaped well is defined by a conductor surrounded by an insulator. The conductor is connected to a voltage terminal. The third doped region is more heavily doped than the second doped region, which is more heavily doped than the first region, and are all of the same doping type. The first doped region and the second doped region within the ring shaped well, form a potential barrier for controlling transfer of charge carriers from the first doped region to the third doped region. |
| US10971531B2 |
Pixels
A photodiode has an absorption layer and a cap layer operatively connected to the absorption layer. A pixel is formed in the cap layer and extends into the absorption layer to receive charge generated from photons therefrom. The pixel defines an annular diffused area to reduce dark current and capacitance. A photodetector includes the photodiode. The photodiode includes an array of pixels formed in the cap layer. At least one of the pixels extends into the absorption layer to receive charge generated from photons therefrom. At least one of the pixels defines an annular diffused area to reduce dark current and capacitance. |
| US10971529B2 |
Electronic device and manufacturing method of the same
An electronic device and manufacturing method of the electronic device are disclosed. The manufacturing method includes: providing a substrate; forming a thin film circuit on the substrate, wherein the thin film circuit comprises at least one thin film transistor and at least one conductive trace; forming at least one first connection pad on the substrate, wherein the first connection pad is electrically connected with the thin film transistor through the conductive trace; disposing the substrate on a driving circuit board, wherein the driving circuit board comprises at least one second connection pad adjacent to and corresponding to the first connection pad; and forming a conductive member covering at least a part of the second connection pad and the first connection pad, wherein the second connection pad is electrically connected with the first connection pad through the conductive member. |
| US10971525B1 |
TFT array substrate and manufacturing method thereof
The present invention teaches a TFT array substrate and its manufacturing method including the following steps. A data line and a ring-shaped source electrode are formed on a substrate. A first insulation layer is formed on the substrate. A ring trough exposing the source electrode is formed on the first insulation layer. A semiconductor active layer is formed in the ring trough. A channel is formed on the first insulation layer in an area surrounded by the ring trough. A gate line, a gate electrode in the channel, and a drain electrode connected to the semiconductor active layer are formed on the first insulation layer. A second insulation layer is formed on the first insulation layer, and a pixel via is formed on the second insulation layer. A pixel electrode is formed on the second insulation layer, and is connected to the drain electrode through the pixel via. |
| US10971523B2 |
Pixel array and fabrication method thereof
The present disclosure provides a pixel array and a fabrication method thereof. The pixel array includes a plurality of gate lines and a plurality of data lines which are arranged intersected and insulated and a pixel unit disposed at a position where each of the plurality of gate lines and each of the plurality of data lines are intersected. The pixel unit includes a thin film transistor (TFT). The width-to-length ratios of channels of the TFTs are sequentially increased in such a manner that the width-to-length ratios of the channels of the TFTs in the pixel units positioned in a same row (and/or a same column) are sequentially increased along a scanning direction of the gate line coupled to gate electrodes of the TFTs in the same row (and/or along a data writing direction of the data line coupled to the source electrodes of the TFTs in the same column). |
| US10971522B2 |
High mobility complementary metal-oxide-semiconductor (CMOS) devices with fins on insulator
The subject disclosure relates to high mobility complementary metal-oxide-semiconductor (CMOS) devices and techniques for forming the CMOS devices with fins formed directly on the insulator. According to an embodiment, a method for forming such a high mobility CMOS device can comprise forming, via a first epitaxial growth of a first material, first pillars within first trenches formed within a dielectric layer, wherein the dielectric layer is formed on a silicon substrate, and wherein the first pillars comprise first portions with defects and second portions without the defects. The method can further comprise forming second trenches within a first region of the dielectric layer, and further forming second pillars within the second trenches via a second epitaxial growth of one or more second materials using the second portions of the first pillars as seeds for the second epitaxial growth. |
| US10971520B2 |
Method for manufacturing semiconductor device
Provided herein is a method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: alternately stacked first material layers and second material layers on a lower structure; forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region; removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed; and forming, through the first holes, conductive patterns which fill respective interlayer spaces. |
| US10971516B2 |
Three-dimensional semiconductor memory devices and methods of fabricating the same
Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction. |
| US10971514B2 |
Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same
A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack. |
| US10971513B2 |
Three-dimensional semiconductor memory devices and method of manufacturing the same
A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate. |
| US10971511B2 |
Semiconductor memory
A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate. |
| US10971503B2 |
Structure and method for FinFET SRAM
A method for semiconductor fabrication includes forming mandrel patterns over a substrate using a first mask that defines the mandrel patterns, wherein the first mask includes at least four first patterns that are spaced from each other in a first direction, wherein each of the first patterns extends lengthwise in a second direction orthogonal to the first direction. The method further includes forming spacers on sidewalls of the mandrel patterns; removing the mandrel patterns, and performing a cut process using a second mask that includes at least four cut windows, each cut window in the second mask being an elongated shape extending lengthwise in the second direction and covering a side of one of the first patterns when the first and second masks are superimposed, the side extending in the second direction. |
| US10971502B2 |
SRAM structure
An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part. |
| US10971501B2 |
Memory structure and manufacturing method thereof
A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region. |
| US10971500B2 |
Methods used in the fabrication of integrated circuitry
A method used in fabrication of integrated circuitry comprises forming metal material outwardly of a substrate. At least a majority (i.e., up to and including 100%) of the metal material contains ruthenium in at least one of elemental-form, metal compound-form, or alloy-form. A masking material is formed outwardly of the ruthenium-containing metal material. The masking material comprises at least one of nine specifically enumerated materials or category of materials. The masking material is used as a mask while etching through an exposed portion of the ruthenium-containing metal material to form a feature of integrated circuitry that comprises the ruthenium-containing metal material. |
| US10971494B2 |
Semiconductor device and semiconductor integrated circuit
A semiconductor device includes: element isolation regions; a projecting semiconductor region; a plurality of first gate electrodes each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions and being component elements of a plurality of transistors; at least one second gate electrode formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off the transistor. |
| US10971493B2 |
Integrated circuit device with high mobility and system of forming the integrated circuit
An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; a fourth fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, a third portion, and a fourth portion of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure respectively. A first distance between the first fin structure and the second fin structure is different from a second distance between the third fin structure and the fourth fin structure. |
| US10971492B2 |
Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same
Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate. |
| US10971488B2 |
Active ESD clamp deactivation
A circuit includes electrostatic discharge (ESD) protection circuitry, triggering circuitry, transient detection circuitry, and deactivation circuitry. The ESD protection circuitry is coupled between a first rail and a second rail. The triggering circuitry is configured to generate an ESD activation signal when a voltage across the first rail and the second rail exceeds a voltage threshold. The ESD protection circuitry is configured to activate based on the ESD activation signal. The transient detection circuitry is configured to generate a deactivation signal when the voltage across the first rail and the second rail comprises a voltage change over time that is less than a transient threshold. The deactivation circuitry is configured to deactivate the triggering circuitry based on the deactivation signal. |
| US10971486B2 |
Semiconductor package and method of manufacturing the semiconductor package
A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad. |
| US10971484B2 |
Package-on-package (PoP) semiconductor package and electronic system including the same
A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area. |
| US10971481B2 |
Light-emitting device and backlight including light-emitting device
The light-emitting device includes a first light-emitting element having an emission peak wavelength of 430 nm or more and less than 490 nm, a second light-emitting element having an emission peak wavelength of 490 nm or more and 570 nm or less, a support body at which the first light-emitting element and the second light-emitting element are disposed, and a light-transmissive member containing a red phosphor and covering the first light-emitting element and the second light-emitting element. A content density of the red phosphor in the light-transmissive member in a space between the first and second light-emitting elements is higher in a part below an upper surface of the second light-emitting element than in a part above the upper surface thereof. |
| US10971479B2 |
Semiconductor package including stacked semiconductor chips
A semiconductor package includes: a substrate; a first interposer disposed over the substrate; a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack includes a plurality of first semiconductor chips stacked with an offset in a first direction; a second chip stack disposed on the first chip stack, wherein the second chip stack includes a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack includes a plurality of third semiconductor chips stacked with an offset in the second direction. |
| US10971478B2 |
Interposer design in package structures for wire bonding applications
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board. |
| US10971476B2 |
Bottom package with metal post interconnections
A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate. |
| US10971474B1 |
Package integration for high bandwidth memory
A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate. |
| US10971469B2 |
Semiconductor device including various peripheral areas having different thicknesses
Reliability of joining between semiconductor chips is improved by promoting filling of a sealing resin into a gap formed between the semiconductor chips.A semiconductor device includes: a first semiconductor chip, which has a plurality of first electrodes on a surface; a second semiconductor chip, which is disposed to be separated by a gap from the surface of the first semiconductor chip, and which includes an inner peripheral area that has a plurality of second electrodes connected to each of the first electrodes on a surface and an outer peripheral area that surrounds the inner peripheral area and has a thickness thinner than the thickness of the inner peripheral area; and a sealing resin, which is respectively filled between the surface of the first semiconductor chip and the inner peripheral area, and between the surface of the first semiconductor chip and the outer peripheral area. |
| US10971468B2 |
Automatic registration between circuit dies and interconnects
Processes for automatic registration between a solid circuit die and electrically conductive interconnects, and articles or devices made by the same are provided. The solid circuit die is disposed on a substrate with contact pads aligned with channels on the substrate. Electrically conductive traces are formed by flowing a conductive liquid in the channels toward the contact pads to obtain the automatic registration. |
| US10971466B2 |
High frequency module and communication device
A high frequency module includes a transmission power amplifier, a bump electrode connected to the transmission power amplifier, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view of the mounting board, a board main part placed outside the via conductor, and an insulating part placed inside the via conductor, and the bump electrode and the via conductor are connected while at least partially overlapping each other in the foregoing plan view, and the board main part and the insulating part are each composed of an insulating material of the same kind. |
| US10971463B2 |
Interconnection structure including a metal post encapsulated by a joint material having concave outer surface
A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. |
| US10971460B2 |
Integrated devices in semiconductor packages and methods of forming same
An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna. |
| US10971457B2 |
Semiconductor device comprising a composite material clip
A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad. |
| US10971450B2 |
Hexagonally arranged connection patterns for high-density device packaging
Hexagonally arranged connection patterns for device packaging allow high density circuitry dies to be assembled into packages of manufacturable size. The connection patterns may be patterns for solder ball arrays or other types of connection mechanisms under a semiconductor package. Despite the increased density of the connection patterns, the connection patterns meet the demanding crosstalk specifications for high speed operation of the high density circuitry. |
| US10971446B2 |
Semiconductor device and method of manufacture
A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure. |
| US10971437B2 |
Chip package structure and method for manufacturing the same
A chip package structure can include: a lead frame having a plurality of pins, a first die pad, and a second die pad; a first die and a second die, where a first surface of the first die is installed on the first die pad, and a first surface of the second die is installed on the second die pad; a plurality of pads installed on a second surface of the first die and a second surface of the second die; and bonding wires including a first set of bonding wires with each having one terminal connected to pads of the first die, and a second set of bonding wires with each having one terminal connected to pads of the second die for connectivity between the first die and the second die, and between the plurality of pins and the first die and the second die. |
| US10971434B2 |
Lead frame package having conductive surface with integral lead finger
Disclosed is a device including a lead frame having a body with a top surface and a bottom surface and lead fingers. Each lead finger has a first end and a second end. A semiconductor die is coupled to the body. A first flag is a first exposed portion of the body and integral with the first end of a first lead finger. The first flag and the first lead finger are a continuous material. A second flag is a second exposed portion of the body and integral with the first end of a second lead finger. The second flag and the second lead finger are a continuous material. An encapsulant covers the die, the bottom surface of the body, the first end of the lead fingers and a portion of the top surface of the body. The flags are separated and electrically isolated from one another by the encapsulant. |
| US10971433B2 |
Surface mounted type leadframe and photoelectric device with multi-chips
A surface mounted type leadframe includes a conductive base and an insulating material layer. The conductive base includes at least three connecting pads spaced apart from each other. First surface of the connecting pads are configured to form die bonding regions, and second surfaces of the connecting pads opposite to the first surfaces are configured to form soldering regions. The insulating material layer at least partially covers the first surfaces, surrounds the die bonding regions, and is filled in a gap between each two adjacent connecting pads. A photoelectric device with multi-chips adopting the surface mounted type leadframe is also provided. |
| US10971424B2 |
Power module and power convertor
A power module includes a recessed base plate having a hollow portion, at least one insulating substrate disposed in the hollow portion of the base plate, at least one semiconductor chip mounted on the at least one insulating substrate, and sealing resin for sealing a surface of the hollow portion side of the base plate, the at least one insulating substrate, and the at least one semiconductor chip. |
| US10971420B2 |
Method of forming a thermal shield in a monolithic 3-D integrated circuit
A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials. |
| US10971419B2 |
Method and apparatus for reducing noise on integrated circuit using broken die seal
A die seal is broken in at least one place for a conductor strip formed on each conductor layer. Accordingly, no current can flow in a circular pattern around the entire perimeter of the chip. In some embodiments, an angled slot is provided in the original die seal. The angled slots may be vertically aligned. Alternatively, the slots may be vertically staggered or straight. When vertically staggered, the slots on each conductor layer are vertically offset. |
| US10971415B2 |
Semiconductor device, manufacturing method for semiconductor device, semiconductor module, and power conversion device
In a semiconductor device using a wide bandgap semiconductor material having a bandgap larger than that of silicon, reliability of the semiconductor device is improved by achieving a structure in which electric field strength in the vicinity of an outer end portion of a semiconductor chip is relaxed. A side surface of the semiconductor chip CHP1a is formed of a region R1 including a first corner, a region R2 including a second corner, and a region R3 interposed between the region R1 and the region R2. At this point, in a case of defining a minimum film thickness of a high electric field-resistant sealing member MR in the region R3 as t1 and defining a maximum film thickness of the high electric field-resistant sealing member MR in the region R1 as t2, a relation of t2≤1.5×t1 is satisfied. |
| US10971405B2 |
Semiconductor devices and fabrication methods thereof
A method for fabricating a semiconductor device includes providing a base substrate, including a first region and a second region. The first region is located on each side of the second region, and a plurality of fin structures is formed in the first region and the second region. The method includes forming a first doped region and a second doped region in the first region and the second region, respectively in the plurality of fin structures. The concentration of doping ions in the first doped region is lower than that in the second doped region, and the doping ions in the first doped region and the second doped region are the same doping type. After forming the first doped region and the second doped region, the method includes forming a plurality of gate structures on the first doped region and the second doped region across the plurality of fin structures. |
| US10971404B2 |
Semiconductor device
A semiconductor device includes a semiconductor substrate, and a first transistor. The first transistor has a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate. A doping ratio determined as a concentration of the first lightly doped source/drain region divided by a concentration of the first channel region ranges from 1.0×1013 to 1.0×1017. |
| US10971403B2 |
Structure and method of forming fin device having improved fin liner
A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device. |
| US10971402B2 |
Semiconductor device including interface layer and method of fabricating thereof
A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer. |
| US10971401B2 |
Systems and methods for precision fabrication of an orifice within an integrated circuit
A method for fabricating an orifice in a semiconductor which can include: removing a first depth of the semiconductor using a first material removal technique and removing a second depth of the semiconductor using a second material removal technique. The method can optionally include: adding a sacrificial layer of material and reducing a depth of the semiconductor by a friction-based material removal technique. In examples, the method fabricates a wafer-scale processor with a set of fastening features. |
| US10971394B2 |
Maskless air gap to prevent via punch through
A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features. |
| US10971388B2 |
Chuck for edge bevel removal and method for centering a wafer prior to edge bevel removal
A chuck useful for supporting a wafer during an edge bevel removal (EBR) process comprises a rotatable center hub having a plurality of support arms extending outwardly from the rotatable center hub, support pins on ends of the support arms, gas passages extending through upper surfaces of the support pins, and gas conduits in the support arms. The gas conduits supply gas to the gas passages or apply a vacuum to the gas passages. The support arms can include alignment cams which are rotatable from an outer non-alignment position away from a periphery of the wafer to an inner alignment position at which the wafer is centered. During centering, the wafer is floated on a gas cushion which reduces wear of the support pins. |
| US10971380B2 |
De-bonding leveling device and de-bonding method
A debonding leveling device and a debonding method are for leveling during a process for debonding a first object and a second object. The first and second objects are retained by a first fixation plate (11) and a second fixation plate (21), respectively. The device includes: a mounting plate (30), disposed at an outer side of one of the first (11) and second (21) fixation plates; a connecting rod assembly (40) fixed around a center position of the mounting plate (30), the connecting rod assembly (40) connected to the one of the first (11) and second (21) fixation plates sequentially via a sliding pair (50) and a spherical pair (60) connected to the sliding pair (50); and at least three elastic assemblies (70) disposed between the mounting plate and the one of the first and second fixation plates, each of the elastic assemblies coupled to the mounting plate (30) and the one of the first (11) and second (21) fixation plates. The combination of the spherical pair and the sliding pair allows an adaptation of leveling objects to dynamic changes of the reference, and the elastic assemblies performs a leveling for the leveling objects in real-time based on an orientation of the reference. This entails a simple structure with a reasonable layout, which is easy to use in practice and is particularly helping in dynamic leveling applications without requiring an active control. |
| US10971379B2 |
Wafer bonding apparatus and wafer bonding system using the same
A wafer bonding apparatus includes a first bonding chuck to fix a first wafer on a first surface thereof, a second bonding chuck to fix a second wafer on a second surface thereof facing the first surface, a bonding initiation member at a center of the first bonding chuck to push the first wafer towards the second surface, and a membrane member including a protrusion protruding from a center portion of the second surface towards the first surface, and a planar portion defining the protrusion on an outer region surrounding the center portion. |
| US10971378B2 |
Method and device for bonding substrates
A method and corresponding device for bonding a first contact surface of a first substrate to a second contact surface of a second substrate. The method includes the steps of arranging a substrate stack, formed from the first substrate and the second substrate and aligned on the contact surfaces, between a first heating surface of a first heating system and a second heating surface of a second heating system. |
| US10971376B2 |
Printed circuit board with protective member and method of manufacturing semiconductor package having the same
A method of manufacturing a semiconductor package includes providing a substrate main body to which external connection terminals are attached, attaching a protective member to the substrate main body to cover the external connection terminals, mounting a semiconductor chip on a surface of the substrate main body that is opposite from the protective member, and removing the protective member from the substrate main body. |
| US10971364B2 |
Ultra-high modulus and etch selectivity boron carbon hardmask films
Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of boron-carbon films on a substrate. In one implementation, a method of processing a substrate is provided. The method comprises flowing a hydrocarbon-containing gas mixture into a processing volume of a processing chamber having a substrate positioned therein, wherein the substrate is heated to a substrate temperature from about 400 degrees Celsius to about 700 degrees Celsius, flowing a boron-containing gas mixture into the processing volume and generating an RF plasma in the processing volume to deposit a boron-carbon film on the heated substrate, wherein the boron-carbon film has an elastic modulus of from about 200 to about 400 GPa and a stress from about −100 MPa to about 100 MPa. |
| US10971360B2 |
Methods of forming a channel region of a transistor and methods used in forming a memory array
A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed. |
| US10971356B2 |
Stack viabar structures
Various methods and structures for fabricating a semiconductor structure. The semiconductor structure includes in a top layer of a semiconductor stack a semiconductor contact located according to a first horizontal pitch. A first metallization layer is disposed directly on the top layer and includes a metallization contact located according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that the location of the metallization contact is vertically mismatched from the location of the semiconductor contact. A second metallization layer is disposed directly on the first metallization layer. The second metallization layer includes a super viabar structure that forms an electrical interconnect, in the second metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first metallization layer. |
| US10971355B2 |
Substrates and methods for forming the same
A substrate includes a ceramic core, a first adhesion layer, a barrier layer, and a second adhesion layer. The first adhesion layer encapsulates the ceramic core and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the first adhesion layer has a first ratio. The barrier layer encapsulates the first adhesion layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the barrier layer has a second ratio that is different from the first ratio. The second adhesion layer encapsulates the barrier layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the second adhesion layer has a third ratio that is different from the second ratio. |
| US10971354B2 |
Drying high aspect ratio features
Methods of drying a semiconductor substrate may include applying a drying agent to a semiconductor substrate, where the drying agent wets the semiconductor substrate. The methods may include heating a chamber housing the semiconductor substrate to a temperature above an atmospheric pressure boiling point of the drying agent until a vapor-liquid equilibrium of the drying agent within the chamber has been reached. The methods may further include venting the chamber, where the venting vaporizes the liquid phase of the drying agent from the semiconductor substrate. |
| US10971346B2 |
Liquid trap or separator for electrosurgical applications
An apparatus for mass spectrometry and/or ion mobility spectrometry is disclosed comprising a first device arranged and adapted to generate aerosol, smoke or vapour from a target and one or more second devices arranged and adapted to aspirate aerosol, smoke, vapour and/or liquid to or towards an analyser. A liquid trap or separator is provided to capture and/or discard liquid aspirated by the one or more second devices. |
| US10971345B2 |
Mass spectrometer and mass spectrometry method
A mass spectrometer includes: a chamber; a support that, in a state in which, in a sample support body that includes a substrate in which a plurality of through-holes open in first and second surfaces are formed and a conductive layer that is at least provided on the first surface, the second surface thereof is in contact with a sample, supports the sample and the sample support body; a laser beam irradiation part that irradiates the first surface with a laser beam; a voltage application part that applies a voltage to the conductive layer; an ion detection part that, detects the ionized components of the sample in a space inside the chamber; a first light irradiation part that irradiates the sample with a first light from a side of the substrate; and an imaging part that obtains a reflected light image of the sample by the first light. |
| US10971339B2 |
Ion source and cleaning method thereof
An ion source includes a plasma chamber, and a suppression electrode disposed downstream of the plasma chamber, and is operable to irradiate the suppression electrode with an ion beam produced from a cleaning gas to clean the suppression electrode. Prior to cleaning, the ion source moves the suppression electrode or the plasma chamber in a first direction to increase a distance between the plasma chamber and the suppression electrode. |
| US10971335B2 |
Radio frequency (RF) power monitoring device and plasma enhanced (PE) system including the same
A radio frequency (RF) power monitoring device includes an RF sensor to monitor RF power transferred to a target load and an impedance of the target load and a transmission line to electrically connect the RF sensor to the target load and to transfer the RF power to the target load. A phase (φz) of the impedance of the target load is adjusted to satisfy a range of −30°+180°*n<φz<30°+180°*n (where n=−2, −1, 0, 1, or 2). |
| US10971332B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes a processing chamber configured to process a substrate, a plasma generator configured to generate a plasma, a transport unit configured to transport, to the processing chamber, the plasma generated by the plasma generator, and a scanning magnetic field generator configured to generate a magnetic field which deflects the plasma so as to scan the substrate by the plasma. The scanning magnetic field generator is configured to be capable of adjusting a center of a locus of the plasma. |
| US10971328B2 |
Charged particle beam device
This charged particle beam device is provided with: a plurality of detectors for detecting secondary particles, the detectors being disposed in a symmetrical manner around the optical axis of a primary charged particle beam closer to the charged particle source side than an objective lens; electrodes for forming an electric field oriented in directions corresponding to each of the plurality of detectors, the electrodes being provided on the travel routes of secondary particles from a sample to the detectors; and a control power supply for applying a voltage to the electrodes. Adjusting the voltage applied to each of the electrodes makes it possible to detect, upon deflecting, the secondary particles, and to control the range of azimuths of the secondary particles to be detected. |
| US10971323B1 |
Semiconductor X-ray target
A solid X-ray target for generating X-ray radiation is disclosed. The X-ray target includes at least one material selected from a list including trivalent elements; and at least one material selected from a list including pentavalent elements, wherein a first one of the materials is capable of generating the X-ray radiation upon interaction with an electron beam, and a second one of the materials forms a compound with the first one of the materials. An X-ray source including such an X-ray target and an electron source is also disclosed. |
| US10971322B2 |
Electron gun, X-ray generation apparatus, and X-ray imaging apparatus
An electron gun includes a cathode including an electron emitting portion, an extraction electrode for extracting electrons emitted from the electron emitting portion, and a focusing electrode for focusing the electrons extracted by the extraction electrode. The focusing electrode includes an outside electrode having a tubular shape, and an inside electrode arranged inside the outside electrode. The inside electrode defines a first space having a columnar shape, and includes a first surface on a side of the cathode, and a second surface on an opposite side of the first surface. An inside surface of the outside electrode and the second surface of the inside electrode define a second space. The inside electrode includes an electron passage hole, and a communicating portion which makes the first space and the second space communicate with each other. |
| US10971320B2 |
Switching device and control method
A switching device includes: an electronic trip unit; an actuator; a switching mechanism connected via the actuator to the electronic trip unit; a stationary contact; a mobile contact, which is coupled to the switching mechanism; and an alarm module. The alarm module includes: a first, a second, and a third connector; a first relay having a first contact which is connected to the first connector and having a second contact which is connected to the second connector; a second relay with a first contact which is connected to the third connector; and a control unit which is coupled on an output side to a control side of the first relay and to a control side of the second relay, and on the input side to the electronic trip unit. |
| US10971319B2 |
Snap fit circuit breaker and load center system
A circuit breaker and panel system includes a panel including a base pan having a plurality of base pan electrical connections. A circuit breaker including a housing having a plurality of circuit breaker electrical connections arranged to contact the base pan electrical connections when the circuit breaker is coupled to the base pan. The circuit breaker is rotatably coupleable with the base pan via a pivot joint for engaging the plurality of base pan electrical connections with the plurality of circuit breaker electrical connections per a predetermined electrical connection coupling sequence. One of the housing and the base pan includes a protrusion and the other of the housing and the base pan includes a corresponding recess which, when engaged with each other, retain the housing to the base pan to prevent reverse rotational movement of the breaker with respect to the base pan. |
| US10971308B2 |
Multilayer capacitor
A multilayer capacitor includes a body and external electrodes on external surfaces of the body. The body includes a plurality of internal electrodes alternately laminated with dielectric layers. The external electrodes are electrically connected to the internal electrodes. Edges of cover portions of the body are rounded. The rounded edges have a radius of curvature R and the body has a thickness T, such that R and T satisfy 10 μm≤R≤T/4. Among the plurality of internal electrodes, an internal electrode in each of the cover portions has a width less than that of an internal electrode of the central portion. |
| US10971306B2 |
Electronic component having an external electrode with a conductive resin layer
An element body of a rectangular parallelepiped shape includes a first principal surface arranged to constitute a mounting surface, a second principal surface opposing the first principal surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction. An external electrode is disposed on the element body. The external electrode includes a conductive resin layer. The conductive resin layer continuously covers one part of the first principal surface, one part of the end surface, and one part of each of the pair of side surfaces. A length of the conductive resin layer in the third direction is smaller than a length of the conductive resin layer in the first direction. |
| US10971304B2 |
Electronic component having metal frames
An electronic component includes a body; external electrodes respectively disposed on opposing surfaces of the body in a first direction thereof; and a pair of metal frames connected to the external electrodes, respectively, in which each of the metal frames includes a support portion bonded to the external electrodes, and a mounting portion extending in the first direction from a lower end of the support portion and spaced apart from the body and the external electrodes, and a length of the mounting portion in a second direction perpendicular to the first direction is greater than a length of the body in the second direction. |
| US10971302B2 |
Multilayer ceramic capacitor and manufacturing method of the same
A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: a relationship “M≥−0.00002×EM+0.0012” is satisfied, when a length of end margins in a direction in which the two end faces face with each other is EM [μm] and a ratio of Mo [atm %] to a B site element [atm %] of a main component ceramic in the end margins is M, wherein the end margin is a region, in which internal electrode layers connected to one of the external electrodes without sandwiching internal electrode layers connected to the other of the external electrode, face with each other, in the multilayer chip. |
| US10971301B2 |
Chip electronic component
A chip electronic component includes spacers that each have a predetermined thickness direction dimension on a mounting surface in a direction perpendicular to the mounting surface. The spacers each contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal. |
| US10971300B2 |
Double conductor single phase inductive power transfer tracks
An IPT track arrangement including a power supply and conductor electrically connected to the power supply, the conductor includes a plurality of loops located substantially adjacent one another, wherein the polarity in adjacent portions of the loops is the same, and wherein the power supply includes a one or more inverters which share the track load. |
| US10971299B2 |
Biorthogonal windings on transformer and common mode choke for network port
In one embodiment, an apparatus includes a plurality of transformers and a plurality of common mode chokes, each of the transformers and the common mode chokes comprising a magnetic core and windings wound around the magnetic core at generally opposite sides thereof. The transformers and common mode chokes are arranged in an array with the windings on each of the magnetic cores positioned generally orthogonal to the windings of adjacent magnetic cores in the array to reduce crosstalk and improve common mode noise rejection. |
| US10971295B2 |
Two part clamping and suspension mechanism for a split toroidal current transformer
The present disclosure relates to ensuring contact between core halves of a current transformer. For example, a current transformer (CT) may include a split core comprising a first core half having a first plurality of faces and a second core half having a second plurality of faces. Each face of the first core half may contact a corresponding face of the second core half to allow magnetic flux to flow through the split core to induce current on windings of the CT. The CT may include a first housing that houses the first core half and a second housing that the second core half. The CT may include a biasing element that biases the second core half towards the first core half to ensure that each face of the second core half contacts the corresponding face of the first core half. |
| US10971294B2 |
Fractal switching systems and related electromechanical devices
This invention entails the use of fractal shapes as cores for electromagnets, and a concurrent shape of a fractal for the windings which surround it. The novelty of this invention lies not only with the shaping, but the advantage of such shaping, which includes producing a smaller form factor electromagnet for the same desired magnetic field strength, when compared to a conventional electromagnet. It will be appreciated that a range of devices including electromagnets, based on such fractal shaping, are additionally novel and include but are not limited to solenoid switches, relays, and other devices in which the fractal electromagnets are used to make a change in state of some device. |
| US10971293B2 |
Spin-orbit-torque magnetization rotational element, spin-orbit-torque magnetoresistance effect element, and spin-orbit-torque magnetization rotational element manufacturing method
A spin-orbit-torque magnetization rotational element includes: a spin-orbit torque wiring layer which extends in an X direction; and a first ferromagnetic layer which is laminated on the spin-orbit torque wiring layer, wherein the first ferromagnetic layer has shape anisotropy and has a major axis in a Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends, and wherein the easy axis of magnetization of the first ferromagnetic layer is inclined with respect to the X direction and the Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends. |
| US10971290B2 |
Magnetic assembly and power supply system with same
A magnetic assembly includes plural first magnetic cores, plural coil windings and a second magnetic core. Each of the plural first magnetic cores includes plural legs and a first connection part. The first connection part is connected with first terminals of the plural legs. The first connection part of the first magnetic core at an upper position is located adjacent to second terminals of the plural legs of the adjacent first magnetic core at a lower position. Each coil winding is wound around at least one leg of the plural legs of the corresponding first magnetic core so as to form a magnetic element of the corresponding converter. The second magnetic core is stacked over the plural first magnetic cores. The second magnetic core is located adjacent to the second terminals of the legs of the topmost first magnetic core. |
| US10971289B2 |
Composite R-Fe-B series rare earth sintered magnet comprising Pr and W
Disclosed in the present invention is a composite R—Fe—B based rare-earth sintered magnet comprising Pr and W, wherein the rare-earth sintered magnet comprises an R2Fe14B type main phase, and R is a rare-earth element comprising at least Pr, wherein the raw material components therein comprise more than or equal to 2 wt % of Pr and 0.0005 wt %-0.03 wt % of W; and the rare-earth sintered magnet is made through a process comprising the following steps: preparing molten liquid of the raw material components into a rapidly quenched alloy; grinding the rapidly quenched alloy into fine powder; obtaining a shaped body from the fine powder by using a magnetic field; and sintering the shaped body. By adding a trace amount of W into the rare-earth sintered magnet, the heat resistance and thermal demagnetization performance of the Pr-containing magnet are improved. |
| US10971288B2 |
Incorporation of oxides into ferrite material for improved radio radiofrequency properties
Disclosed herein are embodiments of an enhanced resonant frequency hexagonal ferrite material and methods of manufacturing. The hexagonal ferrite material can be Y-phase hexagonal ferrite material, such as those including strontium. In some embodiments, oxides consistent with the stoichiometry of Sr3Co2Fe24O41, SrFe12O19 or CoFe2O4 can be used form an enhanced hexagonal ferrite material. |
| US10971285B2 |
Three-wire communication cable
Three-wire communication cables are useful for operation with a vehicle as vehicular data communication cables. The cables include a cable core formed of three insulated wires twisted together at a defined pitch and a jacket surrounding the cable core. The cables can meet Mobile Industry Processor Interface (“MIPI”) C-PHY℠ standard (Version 1.2) as well as International Standards Organization (“ISO”) 6722-1 (2011) and 14572 (2011). |
| US10971283B2 |
Flex flat cable structure and fixing structure of cable connector and flex flat cable
A flex flat cable structure includes metallic transmission lines having a power line and signal lines, first insulating jackets, a second insulating jacket, a third insulating jacket, and a shield layer. Each of the first insulating jackets encloses one of the metallic transmission lines. The second insulating jacket surrounds the first insulating jackets. The third insulating jacket encloses the first insulating jackets, and the second insulating jacket encloses the third insulating jacket. The shield layer is used to isolate the second insulating jacket from the third insulating jacket. The shield layer includes an insulating film, a first block layer, and a second block layer. |
| US10971282B2 |
Flex flat cable structure and flex flat cable electrical connector fix structure
A flex flat cable (FFC) structure includes metallic transmission wires arranged in parallel, first insulating jackets, and second insulating jacket. The metallic transmission wires includes one or more power wires and signal wires. The power wire is configured to transmit power. The signal wires are configured to transmit a data signal. Each of first insulating jackets encloses one of metallic transmission wires. The second insulating jacket surrounds the first insulating jackets. An embossment pattern is arranged on an external surface of the second insulating jacket. The embossment pattern includes meander lines in a top-view direction and in an extending direction for the metallic transmission wires. The meander lines are not arranged parallel. |
| US10971279B2 |
Manufacturing method of high thermal conductive hybrid film
A manufacturing method of a high thermal conductive hybrid film includes steps as follows. A graphene oxide solution including a plurality of graphene oxides is prepared. A nano-particle solution including a plurality of nano initial hybrid structures is prepared. A mixing process is provided, wherein the mixing process is for mixing the graphene oxide solution and the nano-particle solution to obtain a mixing solution. A preliminary-film forming process is provided, wherein the preliminary-film forming process is for filtrating the mixing solution and then remaining a mixture of the graphene oxides and the nano initial hybrid structures to form a preliminary film. A heating process is provided, wherein the heating process is for heating the preliminary-film to reduce the graphene oxides as a plurality of reduced graphene oxides and convert the nano initial hybrid structures into a plurality of nano hybrid structures. |
| US10971275B2 |
Passive electrical component for safety system shutdown using Ampere's Law
An electro-technical device includes a circuit including a coil connected to a voltage source for receiving a predetermined current therefrom and connected to an output device. The circuit includes a breakable junction and a photodiode for receiving a light signal from a fiber optic cable. The photodiode receives a light signal from a sensor. A permanent magnet includes a pole end opposing a common pole end of the coil, wherein when the coil receives an increased current from the photodiode, the coil creates an magnetic flux that repels against the common pole of the permanent magnet in order to cause the breakable junction to break and disrupt a connection between the voltage source and the output device. |
| US10971273B2 |
Identification of co-located artifacts in cognitively analyzed corpora
Techniques for cognitive corpora analysis are provided. Vector representations are generated by processing documents in a corpus using a passage encoder. One or more concepts are identified in the documents by processing the documents with the passage encoder, where the concepts are assigned respective importance scores by the passage encoder. Further, a selection of a document is received, and a sub-corpus of documents is generated by computing a similarity measure between the vector representation of the first document and the vector representation of at least one other document in the corpus. An overall importance score is generated for a first concept, with respect to the generated sub-corpus, by identifying a respective importance score of the first concept in at least two respective documents in the sub-corpus, and aggregating the respective importance scores. Finally, an indication of the generated overall importance score is provided. |
| US10971271B2 |
Method and system for personalized blood flow modeling based on wearable sensor networks
A method and system for personalized blood flow modeling based on wearable sensor networks is disclosed. A personalized anatomical model of vessels of a patient is generated based on initial patient data. Continuous cardiovascular measurements of the patient are received from a wearable sensor network on the patient. A computational blood flow model for simulating blood flow in the patient-specific anatomical model of the vessels of the patient is personalized based on the continuous cardiovascular measurements from the wearable sensor network. Blood flow and pressure in the patient-specific anatomical model of the vessels of the patient are simulated using the personalized computational blood flow model. Hemodynamic measures of interest for the patient are computed based on the simulated blood flow and pressure. |
| US10971270B2 |
Treatment recommendation decision support using commercial transactions
Mechanisms are provided to implement a cognitive medical decision support system that operates to analyze a set of commercial transactions executed by a patient to identify at least one of products or services purchased during each commercial transaction or an activity, associated with the commercial transaction, engaged in by the patient. The cognitive medical decision support system determines a lifestyle behavior pattern of the patient based on the products, services, or activities associated with the commercial transactions in the set of commercial transactions and evaluates an impact of the lifestyle behavior pattern to at least one of the overall health of the patient, a specific medical condition of the patient, or a specific previously prescribed treatment of the patient. The cognitive medical decision support system outputs a notification indicating the impact of the lifestyle behavior pattern. |
| US10971269B2 |
Treatment recommendation decision support using commercial transactions
Mechanisms are provided to implement a cognitive medical decision support system that operates to analyze a set of commercial transactions executed by a patient to identify at least one of products or services purchased during each commercial transaction or an activity, associated with the commercial transaction, engaged in by the patient. The cognitive medical decision support system determines a lifestyle behavior pattern of the patient based on the products, services, or activities associated with the commercial transactions in the set of commercial transactions and evaluates an impact of the lifestyle behavior pattern to at least one of the overall health of the patient, a specific medical condition of the patient, or a specific previously prescribed treatment of the patient. The cognitive medical decision support system outputs a notification indicating the impact of the lifestyle behavior pattern. |
| US10971268B2 |
Method of providing information for the diagnosis of pancreatic cancer using Bayesian network based on artificial intelligence, computer program, and computer-readable recording media using the same
The present invention provides a method of providing information necessary for diagnosing pancreatic cancer using an artificial intelligence-based Bayesian network, comprising: generating a statistical report by learning medical information of a pancreatic cancer patient; constructing a conditional probability table using statistics for each symptom of an actual pancreatic cancer patient; constructing a Bayesian network using the conditional probability table constructed using the statistics for each symptom; applying a Bayesian conditional probability to the Bayesian network; and deriving a probability of getting pancreatic cancer when there is a specific symptom from the pancreatic cancer patient, wherein medical information on pancreatic cancer patients may be statistical data obtained through artificial intelligence or machine learning. |
| US10971264B1 |
Patient tracking and dynamic updating of patient profile
Medical services are offered by various facilities near a patient's residence. The number of facility options continues to grow and the patients can now receive various different health care services. One example method of operation provides retrieving a schedule associated with sensor data being received from a number of sensors, receiving updated sensor data from the sensors at an updated sensor data receive time, comparing the updated sensor data to the schedule, identifying a time discrepancy between the schedule and the updated sensor data receive time, and creating an alert status based on the discrepancy. |
| US10971260B2 |
System and method for capturing dose information
A system for capture of dose delivery information is provided. The system includes a medication delivery device, a dose information capture device adapted to be attached to the medication delivery device, and a target element adapted to be attached to the medication delivery device. The target element comprises a magnet or ferrous element and the target element attaches to the medication delivery device on a dose delivery mechanism of the medication delivery device. The dose information capture device includes a magnetic position sensor adapted to detect a position of the target element. As an alternative to magnetic sensing, MEMS flow sensors, and the like may also be used. Exemplary systems preferably transmit dose information in real time to remote devices for further processing. |
| US10971258B2 |
Systems, methods, and apparatuses for managing adherence to a regimen
Methods, systems and apparatuses, including computer programs encoded on computer storage media, are provided for assisting users with adherence to a medication regimen. An attachable device includes a sensor module releasably attached to an adapter, which is in turn attached to a medication container using a connector. The sensor module can be removed from the adapter to change an included battery without removing the adapter from the medication container. The sensor module is in communication with a user device, such as a smart phone. A user can use an app on the user device to create a medicine regimen, or schedule, and send the schedule to the sensor module. The user can also set notification preferences on the user device to be sent to the sensor module. The sensor module includes audio and/or visual transducers that notify the user to take the medication at the scheduled times. The sensor module further includes one or more buttons that are pressed when a user opens the medication container. The button(s) are configured so the action of the user required to open the container also presses at least one button. The sensor module records the actions of the user, including when the medication container is opened, when a dose of the medication is missed, and when the user presses a mood indication button. The user actions can be transmitted to the user device, which can then transmit the recorded actions to a server. The sensor module may be configured to attempt communication with the user device on a periodic basis to conserve battery life. |
| US10971254B2 |
Medical condition independent engine for medical treatment recommendation system
Mechanisms are provided which configure a medical treatment recommendation system to implement a medical condition independent treatment recommendation model. The medical condition independent treatment recommendation model operates on medical condition independent scoring features that are independent of any specific medical condition. The mechanisms configure the medical treatment recommendation system to receive a medical condition cartridge providing at least one medical condition specific evaluation feature that is specific to a medical condition, and process patient information based on a combination of an application of the at least one medical condition specific evaluation feature, and an execution of the medical condition independent treatment recommendation model of the medical treatment recommendation system, to generate a treatment recommendation for a patient medical condition associated with the patient. The mechanisms then output the treatment recommendation for the patient. |
| US10971252B2 |
Linking entity records based on event information
A system links data objects associated with a common event and includes at least one processor. The system compares data objects associated with an entity and corresponding to a plurality of events for the entity, wherein the data objects are stored within a plurality of different source systems. Candidate data objects associated with a common event for the entity are identified based on the comparing. The candidate data objects are linked to form a set of data objects representing the common event for the entity. Embodiments of the present invention further include a method and computer program product for linking data objects associated with a common entity. |
| US10971243B2 |
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns. |
| US10971242B2 |
Sequential error capture during memory test
Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states. The register latches are arranged in series having respective latch inputs cascaded with preceding latch outputs operable to shift the error logic signals to a serial output according to a control signal that is common to the register latches. The system includes an aggregate latch operable to receive the serial output and having input logic configured to maintain a first state of the aggregate latch until the serial output is a second state. The system includes a built-in self-test (BIST) engine including stored instructions operable upon execution by the BIST engine to output the control signal. |
| US10971238B2 |
Three-dimensional semiconductor memory devices and methods of operating the same
Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line. Each of the cell strings includes a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line. In each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage. Related methods of operating three-dimensional semiconductor memory devices are also provided. |
| US10971235B2 |
Methods of operating memory devices based on sub-block positions and related memory system
A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address. |
| US10971228B2 |
Adaptive application of voltage pulses to stabilize memory cell voltage levels
A request to apply a plurality of voltage pulses to memory cells of a memory device can be received. A number of the voltage pulses can be applied the memory cells of the memory device, where a voltage pulse of the number of the voltage pulses places the memory cells of the memory device at a voltage level associated with a defined voltage state. A set of bit error rates associated with the memory cells of the memory device at the voltage level can be determined. Responsive to determining that the set of bit error rates does not satisfy a threshold condition, an additional number of the voltage pulses to the memory cells of the memory device can be applied. |
| US10971227B2 |
Preservation circuit and methods to maintain values representing data in one or more layers of memory
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. |
| US10971223B2 |
Phase change memory operation method and circuit
A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence. |
| US10971222B2 |
Dynamic bit-scan techniques for memory device programming
An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0. |
| US10971220B2 |
Write assist for a memory device and methods of forming the same
A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout. |
| US10971216B2 |
SRAM configuration cell for low-power field programmable gate arrays
A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node. |
| US10971212B2 |
Memory chip and control method thereof
A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path. |
| US10971206B2 |
Semiconductor memory device
A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal. |
| US10971204B2 |
Three-dimensional non-volatile ferroelectric memory
Disclosed is a three-dimensional non-volatile ferroelectric memory including a ferroelectric memory array structure, wherein the ferroelectric memory array structure includes multiple layers of ferroelectric memory cell array disposed in a stacked way, and each layer of the ferroelectric memory cell array includes ferroelectric memory cells arranged in rows and columns; wherein word lines and bit lines which are substantially orthogonal to each other are oppositely disposed on two sides of the corresponding ferroelectric memory cell respectively, and a reference ferroelectric body is disposed adjacent to the corresponding ferroelectric memory cell. A polarization direction of an electric domain in the ferroelectric memory cell is not perpendicular to an electric field direction of a write voltage signal applied to the word line and the bit line; and when the write voltage signal is applied between the word line and the bit line. |
| US10971200B2 |
Semiconductor circuit and operating method for the same
A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′. |
| US10971199B2 |
Microcontroller for non-volatile memory with combinational logic
A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software (e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors. |
| US10971198B2 |
Semiconductor system and method of operating the same
A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device compares a received signal with an original signal to generate a driving force control signal. The first semiconductor device also drives the original signal using a driving force in accordance with the driving force control signal to output an external transmission signal. The second semiconductor device receives the external transmission signal to generate a positive signal and a negative signal. The second semiconductor device also generates a restoration signal in response to the positive signal and the negative signal. The second semiconductor device additionally outputs the restoration signal as the external transmission signal to the first semiconductor device. |
| US10971197B2 |
Control circuit, semiconductor memory device, information processing device, and control method
To provide a control circuit capable of reliably generating a reference potential while suppressing increase in power consumption and cost. Provided is a control circuit that performs control to separate from a sense amplifier a second reference element set to a predetermined resistance state, which is different from a first reference element set to a predetermined resistance state and connected to the sense amplifier in generating a reference potential used for data read through the sense amplifier from a memory cell. |
| US10971196B1 |
Single-ended sense amplifier
A single-ended sense amplifier includes a virtual-supply voltage-adapted (VVDD-adapted) inverter circuit, a virtual-supply voltage-adapted (VVDD-adapted) voltage-level converter circuit (VLC), and a virtual-supply-voltage-adaptation circuit (VSVA). The single-ended sense amplifier receives a data signal input, a sensing-operation-enabling signal input, and a pre-charging control signal input to generate a final amplified signal output. There are a first virtual-supply node and a second virtual-supply node in the VVDD-adapted inverter circuit. There is a third virtual-supply node in the VVDD-adapted VLC. The VSVA connects both the first and third virtual supply voltage nodes. The output end of the virtual-supply voltage-adapted inverter circuit connects to the input end of the VVDD-adapted VLC. |
| US10971182B2 |
Magnetic powder, manufacturing method of magnetic powder, and magnetic recording medium
Magnetic powder includes: at least one epsilon-phase iron oxide-based compound selected from the group consisting of ε-Fe2O3 and a compound represented by Formula (1); and a surface treatment layer including a silane compound on at least a part of a surface. The magnetic powder has an average particle diameter of 8 nm to 20 nm. The content ratio of carbon atoms of the silane compound included in the surface treatment layer to iron atoms of the at least one epsilon-phase iron oxide-based compound selected from the group consisting of ε-Fe2O3 and the compound represented by Formula (1) is 0.05% to 0.5% in terms of the number of atoms. A manufacturing method thereof and applications thereof are also provided. In Formula (1), A represents at least one metal element other than Fe and a represents a number that satisfies a relationship of 0 |
| US10971181B2 |
Sputtering target for magnetic recording media
A sputtering target for magnetic recording media capable of producing a magnetic thin film in which the magnetic crystal grains are micronized and the distance between the centers of the grains is reduced while good magnetic properties are maintained. The target including metallic Pt and an oxide, with the balance being metallic Co and inevitable impurities, wherein the Co is contained in a range of 70 at % to 90 at % and the Pt is contained in a range of 10 at % to 30 at % relative to a total of metallic components in the sputtering target for magnetic recording media, the oxide is contained in a range of 26 vol % to 40 vol % relative to a total volume of the sputtering target for magnetic recording media, and the oxide is composed of B2O3 and one or more high-melting-point oxides having a melting point of 1470° C. or higher and 2800° C. or lower. |
| US10971179B1 |
Compact mode converter having first and second straight portions for a heat-assisted magnetic recording device
A write head includes an input coupler configured to receive light excited by a light source. A waveguide core is configured to receive light from the input coupler at a fundamental transverse electric (TE00) mode. The waveguide core has a first straight portion. The waveguide core has a mode converter portion comprising a branched portion extending from the first straight portion. The mode converter portion is configured to convert the light to a higher-order (TE10) mode, the mode converter portion spaced apart from the input coupler. The waveguide core has a second straight portion between the mode converter portion and a media-facing surface. The write head has a near-field transducer at the media-facing surface, the near-field transducer receiving the light at the TE10 mode from the waveguide and directing surface plasmons to a recording medium in response thereto. |
| US10971178B2 |
Vertically translating load/unload ramp mechanism for cold storage data storage device
An approach to a reduced-head hard disk drive (HDD) involves a load/unload (LUL) ramp subsystem that includes a ramp assembly that includes a rotatable latch link configured for mechanical interaction with a head-stack assembly (HSA) and a LUL ramp coupled with the latch link, configured such that in response to a force applied to the latch link by the HSA, the latch link rotates which disengages a magnetic latch and drives the LUL ramp to rotate into an operational state disengaged from any recording disk of a multiple-disk stack. The subsystem may further include a motor configured to drive rotation of a lead screw to which the ramp assembly is attached, to drive vertical translation of the ramp assembly, thereby providing for loading the vertically-translatable HSA onto and off of each of the disks of the disk stack. |
| US10971177B1 |
Heat-assisted magnetic recording device with multiple writers that write to the same disk surface at different time periods
A first heat-assisted magnetic recording (HAMR) writer writes to a surface of a magnetic disk using during an initial time period. A second HAMR writer is configured to write to the surface but not during the initial time period. The initial time period extends from a first time when the disk drive is first used to a second time when a near-field transducer of the first HAMR writer reaches a first wear threshold. During a subsequent time period after the initial time period, to the surface of the disk is written to using the second HAMR writer and not the first HAMR writer. |
| US10971174B2 |
Information processing apparatus, information processing method, and non-transitory computer readable recording medium
An information-processing apparatus includes a display displaying an image; a memory recording voice data having a voice pronounced at each of plural observation points of the image; a gaze detector generating gaze data by detecting a gaze of a user; a voice input device generating voice data associated with a time axis identical to that of the gaze data by receiving a voice of the user; and a processor to analyze a attention period where a attention degree of the gaze to each of the plural observation points is a predetermined value or greater, based on the gaze data, set a period where the voice is pronounced with respect to the voice data as an important voice period, based on the voice data, and generate calibration data based on a time lag between the attention period and the important voice period. |
| US10971166B2 |
Low latency audio distribution
A method includes receiving data in a first series of blocks each having a first number of audio samples and repackaging the data into a second series of blocks each having a second number of audio samples. The second number of audio samples is a non-integer fraction of the first number of audio samples. The method further includes transmitting the second series of blocks over a series of fixed duration time intervals, and adjusting the payload of adjacent time intervals to reduce jitter in the transmission of the second series of blocks. |
| US10971165B2 |
Method and apparatus for sinusoidal encoding and decoding
An audio signal encoding method is provided that comprises collecting audio signal samples, determining sinusoidal components in subsequent frames, estimating amplitudes and frequencies of the components for each frame, merging the obtained pairs into sinusoidal trajectories, splitting particular trajectories into segments, transforming particular trajectories to the frequency domain by way of a digital transform performed on segments longer than the frame duration, quantization and selection of transform coefficients in the segments, entropy encoding, outputting the quantized coefficients as output data, wherein segments of different trajectories starting within a particular time are grouped into Groups of Segments, and the partitioning of trajectories into segments is synchronized with the endpoints of a Group of Segments. |
| US10971163B2 |
Reconstruction of audio scenes from a downmix
Audio objects are associated with positional metadata. A received downmix signal comprises downmix channels that are linear combinations of one or more audio objects and are associated with respective positional locators.In a first aspect, the downmix signal, the positional metadata and frequency-dependent object gains are received. An audio object is reconstructed by applying the object gain to an upmix of the downmix signal in accordance with coefficients based on the positional metadata and the positional locators.In a second aspect, audio objects have been encoded together with at least one bed channel positioned at a positional locator of a corresponding downmix channel. The decoding system receives the downmix signal and the positional metadata of the audio objects. A bed channel is reconstructed by suppressing the content representing audio objects from the corresponding downmix channel on the basis of the positional locator of the corresponding downmix channel. |
| US10971153B2 |
Transcription generation from multiple speech recognition systems
A method may include obtaining first audio data originating at a first device during a communication session between the first device and a second device. The method may also include obtaining a first text string that is a transcription of the first audio data, where the first text string may be generated using automatic speech recognition technology using the first audio data. The method may also include obtaining a second text string that is a transcription of second audio data, where the second audio data may include a revoicing of the first audio data by a captioning assistant and the second text string may be generated by the automatic speech recognition technology using the second audio data. The method may further include generating an output text string from the first text string and the second text string and using the output text string as a transcription of the speech. |
| US10971152B2 |
Imaging control method and apparatus, control device, and imaging device
An imaging control method includes acquiring a device identifier of an imaging device; acquiring voice information; performing information comparison on content data included in the voice information based on the device identifier; analyzing the voice information to identify control information in response to the content data including matching information that matches the device identifier; generating a control command based on the control information; and transmitting the control command to the imaging device to control the imaging device to capture an image. |
| US10971146B2 |
Speech interaction device
A speech interaction device includes an ascertaining section and a control section. The ascertaining section ascertains a direction of a speech utterer by audio emitted by the speech utterer. The control section controls directionality of audio output through a speaker when outputting audio toward the speech utterer, such that directionality of audio in the direction ascertained by the ascertaining section is higher than directionality of audio in other directions. |
| US10971138B2 |
Break state detection for reduced capability devices
Systems, methods, and devices are described herein for placing secondary content into a break of unknown duration in a stream of primary content. In one aspect, the described techniques may include streaming a segment of primary content, for example, by a reduce capability client device, such as a mobile device or tablet. The device may receive information indicative of a break in the streaming of the primary content. The device may play secondary content based on receiving the information indicative of the break. The device may determine when a next segment of the primary content is available, and begin streaming the next segment of the primary content upon detecting that the second segment of the primary content is available. |
| US10971135B2 |
System and method for crowd-sourced data labeling
Systems, methods, and computer-readable storage devices for crowd-sourced data labeling. The system requests a respective response from each of a set of entities. The set of entities includes crowd workers. Next, the system incrementally receives a number of responses from the set of entities until one of an accuracy threshold is reached and m responses are received, wherein the accuracy threshold is based on characteristics of the number of responses. Finally, the system generates an output response based on the number of responses. |
| US10971132B2 |
Multimedia processing method and electronic system
An electronic system is provided. The electronic system includes a host, an audio output device and a display. The host includes an audio processing module, a relay processing module, a smart interpreter engine and a driver. The audio processing module is utilized for acquiring audio data corresponding to a first language from audio streams processed by an application program executed on the host. The smart interpreter engine is utilized for converting the audio data corresponding to the first language into text data corresponding to a second language. The relay processing module is utilized for transmitting the text data corresponding to the second language to the display for displaying. The driver is utilized for converting the data corresponding to the first language into an analog audio signal corresponding to the first language and transmitting the analog audio signal corresponding to the first language to the audio output device for playback. |
| US10971131B2 |
Method and apparatus for generating speech synthesis model
The present disclosure discloses a method and apparatus for generating a speech synthesis model. A specific embodiment of the method comprises: acquiring a plurality of types of training samples, each of the plurality of types of training samples including a text of the type, and a speech of the text having a style of speech corresponding to the type read by an announcer corresponding to the type; and training a neural network corresponding to a speech synthesis model using the plurality of types of training samples and an annotation of the style of speech in the each of the plurality of types of training samples to obtain the speech synthesis model, the speech synthesis model being used to synthesize speech of the announcer corresponding to each of the plurality of types having a plurality of styles. |
| US10971119B2 |
Double-layer dumb drum with sand belt adjusting function
A double-layer dumb drum with a sand belt adjusting function includes an upper-layer elastic body, a strike edge, an upper bottom plate, a sand belt adjusting device, an internal resonance chamber, an external resonance chamber, a lower-layer elastic body, and a lower bottom plate. The upper-layer elastic body is fixed to the top of the upper bottom plate; the internal and external resonance chambers are under the upper bottom plate; the sand belt adjusting device is installed in the internal resonance chamber; and the bottom of the internal resonance chamber is sealed by the external resonance chamber. A lower-layer elastic body is fixed to the top of the lower bottom plate; contact points are at the bottom of the external resonance chamber and abut against the top of the lower-layer elastic body; and connecting screws are connected between the upper and lower bottom plates. |
| US10971118B2 |
Guitar
A guitar comprises a body having a bottom and sides and a top. An outer perimeter of a top is attached to an upper rim of the sides, wherein an upper surface of the top is in tension due to bending of the top into a substantially domed shape and wherein the thickness of the top is thinner in the area of the outer perimeter than a central portion, thereby reducing the tension in the upper surface of the top in the area of the outer perimeter. |
| US10971116B2 |
Display device, control method for placement of a virtual image on a projection surface of a vehicle, and storage medium
A display device includes a light projection device which projects light including an image, an optical mechanism which is capable of adjusting a distance from a predetermined position to a position where the light is formed as a virtual image, a concave mirror which reflects light toward a reflector, a concave mirror actuator which adjusts a reflection angle of the concave mirror, and a control device which controls the light projection device and the concave mirror actuator, in which the control device adjusts a projection position on a projection surface of the light projected from the light projection device having an angle formed by a horizontal surface passing through a predetermined position on an image and a segment from the predetermined position to a position where the light is formed as a virtual image so as to curb fluctuation occurring due to movement of a vehicle. |
| US10971115B2 |
Foveated rendering system and method
A foveated rendering system for modifying content to be displayed includes a user profile obtaining unit operable to obtain a user profile comprising information about head motion and eye motion for a user, and a foveated rendering unit operable to apply a foveated rendering process to the content to be displayed in dependence upon obtained user profile information. |
| US10971112B2 |
Dynamically-themed display utilizing physical ambient conditions
Configuring a graphical user interface according to a user's preferences is described herein. Systems and methods are provided for generating a dynamically varying themed interface for a user environment; defining appropriate color palettes associated within a brand definition of the user environment; and, providing one or more configuration settings for the rendering engine. |
| US10971111B2 |
Providing a representation for a device connected to a display device
Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing a representation to a connected device. An embodiment operates by recognizing a new device connected to a display device, collecting device fingerprint information from the new device, and requesting a device class representation information determined based on the device fingerprint information. Another embodiment operates by receiving device fingerprint information from a display device via a network connection, wherein the device fingerprint information is collected from a device connected to a display device, and providing device class representation information to the display device via the network connection, when the device class representation information corresponding to the device fingerprint information is available. |
| US10971109B2 |
Image processing method, apparatus, device, and video image transmission system
An image processing method includes obtaining a first YUV image captured by an on-board image acquisition device operating in a log mode, converting the first YUV image to a second YUV image having a same image format as an image captured by the on-board image acquisition device operating in a normal mode, and transmitting the second YUV image. |
| US10971107B2 |
Display device
A display device is provided. A first pixel is coupled to a first scan line and a first data line and includes a first light-transmitting area. A second pixel is coupled to a second scan line and a second data line and includes a second light-transmitting area. The size of the second pixel is equal to the size of the first pixel. The area of the second light-transmitting area is different from the area of the first light-transmitting area. A first color area overlaps the first pixel. When first light passes through the first light-transmitting area and the first color area, the first light has a first color. A second color area overlaps the second pixel. When second light passes through the second light-transmitting area and the second color area, the second light has a second color, which is the same as the first color. |
| US10971102B2 |
Shift register unit and driving method, gate driving circuit, and display device
A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, an output circuit, a first node control circuit, and a second node control circuit. The input circuit is configured to provide an input signal to a first node in response to a first control signal; the output circuit is configured to output an output signal at an output terminal under control of a level of the first node; the first node control circuit is configured to reset the first node under control of a level of a second node; and the second node control circuit is connected to the second node, and is configured to provide a third control signal to the second node in response to a second control signal to control the level of the second node. |
| US10971100B2 |
Pixel driving circuit, display panel having the pixel driving circuit and driving method of display panel
The present disclosure provides a driving method of a display panel, the display panel including a plurality of pixels, each row of pixels correspond to a gate line, each column of pixels correspond to a data line, the driving method including: comparing a current frame of image with a previous frame of image to determine a non-changing row of the pixels, contents displayed by each pixel in the non-changing row for the current frame of image and contents displayed by each pixel in the non-changing row for the previous frame of image are the same; selecting a non-charging row from the non-changing row according to a predetermined time; providing, when displaying the current frame of image, an invalid signal to the gate line of the non-charging row during a scanning time for the gate line of the non-charging row to not to charge the non-charging row. |
| US10971098B2 |
Method and device for adjusting gray scale of display panel
The present disclosure discloses a method and a device for adjusting gray scale of a display panel, the method comprises: performing image acquisition on a display panel, and obtaining a current image; identifying an nonuniform block in the current image, and detecting an original output brightness and an original input gray scale of the nonuniform block; determining a target input gray scale corresponding to a preset target brightness according to an actual Gamma curve value, the actual Gamma curve value is obtained through testing the display panel; using a difference value between the original input gray scale and the target input gray scale as a gray scale compensation value of the nonuniform block. |
| US10971097B2 |
Display device
A display device includes a first substrate; and a circuit layer arranged on the first substrate and comprising a first scanning signal line driving circuit arranged on the side of a first side of the first substrate, a second scanning signal line driving circuit arranged on the side of a second side, a third scanning signal line driving circuit arranged between the first scanning signal line driving circuit and the second scanning signal line driving circuit, and each of a plurality of pixel circuits including a first pixel circuit and a second pixel circuit, the first pixel circuit being arranged in a region between the first scanning signal line driving circuit and the third scanning signal line driving circuit, and the second pixel circuit being arranged in a region between the third scanning signal line driving circuit and the second scanning signal line driving circuit. |
| US10971093B2 |
Pixel circuit and display device
A pixel circuit includes a storage capacitor, a first switch, and a second switch. The first switch is electrically connected to a first end of the storage capacitor, and configured to provide a data voltage to the first end of the storage capacitor according to a gate signal. The second switch is electrically connected between the first end of the storage capacitor and a second end of the storage capacitor, and configured to receive a first operating voltage from the second end of the storage capacitor and provide the first operating voltage to the first end of the storage capacitor. |
| US10971092B2 |
Driving method and driving device of display panel
A driving method and a driving device of a display panel are provided. The driving method includes: controlling a timing controller to output a start signal to a level shifter; configuring a parameter of a register of the level shifter; and controlling the level shifter to generate a drive signal according to the parameter upon receiving the start signal, and outputting the drive signal to a first drive circuit. |
| US10971091B2 |
Array substrate, display panel and driving method thereof, and display device
An array substrate, a display panel and a driving method thereof, and a display device are provided. The array substrate includes a plurality of pixel units arranged in an array, each of the plurality of pixel units includes at least four sub-pixel units corresponding to different colors. When the array substrate displays a frame of image, in each row of pixel units, polarities of pixel voltages received by two sub-pixel units corresponding to the same color in adjacent two pixel units are different; a polarity of each pixel voltage represents the magnitude of each pixel voltage relative to a common voltage. |
| US10971090B2 |
Method for preventing image sticking in display panel
The present invention discloses a method for a source driver, for preventing image sticking in a display panel coupled to the source driver. The source driver includes a first output driver and a second output driver having different polarities. The first output driver is configured with a first driving capability and the second output driver is configured with a second driving capability. The method includes the steps of: obtaining an effective voltage of a pixel in the display panel; and adjusting the second driving capability of the second output driver to be identical to the first driving capability of the first output driver, to allow the adjusted second driving capability to drive the effective voltage to reach a level having the same magnitude as a level of the effective voltage driven by the first source driver with the same variation of display data. |
| US10971087B2 |
Display device and method of driving the same
According to an aspect of the present disclosure, there is provided a display device including a display panel having a left-eye display area and a right-eye display area, and a timing controller configured to receive video signals having a first frequency to generate video data having a second frequency, where the second frequency is lower than the first frequency. |
| US10971086B2 |
Pulsed backlight systems and methods
Aspects of the subject technology relate to pulsed backlight operation for a display backlight. Backlight pulse patterns are provided that include steady state pulse patterns to be applied during operation of a liquid crystal display unit of the display at a corresponding frame rate. The backlight pulse patterns can be arranged to prevent visible artifacts such as flicker or strobing, particularly at or near a transition between LCD frame rates. In some scenarios, transition pulse patterns are provided. |
| US10971084B2 |
Display device, control method and apparatus thereof
Disclosed are a display device and a method control of the display. The method includes: selecting an initial duty and a target initial brightness which generate a color shift is less than or equal to a preset color shift value; calculating a corresponding initial grayscale according to the initial duty and the target initial brightness; searching for an initial data voltage corresponding to the initial grayscale according to a gamma curve, where the initial data voltage is associated with the initial duty and the target initial brightness; and performing a brightness adjustment, where the brightness adjustment comprises either a segmented or a mixed pulse width modulation dimming technique and power modulation dimming technique, where the brightness adjustment is performed in a brightness interval from the target initial brightness to maximum brightness. |
| US10971079B2 |
Multi-frame-history pixel drive compensation
Image data for a current image frame may be compensated for transient response variations due to changes to pixel values from one frame to another over time by performing pixel drive compensation. The pixel drive compensation may be performed using a current pixel value and a historical pixel value. The historical pixel value may be the same as a pixel value in the directly previous frame in some conditions, while in other conditions the historical pixel value may be modified from a previous image frame in light of a prior pixel value occurring before the previous image frame. In this way, drive compensation corresponding to image data of a subsequent image frame may be determined based at least in part on a multi-frame history. Even so, the memory bandwidth and/or power consumed to use a multi-frame history to determine a drive compensation may be reduced. |
| US10971078B2 |
Pixel measurement through data line
A system and method for determining the current of a pixel circuit and an organic light emitting diode (OLED). The pixel circuit is connected to a source driver by a data line. The voltage (or current) supplied to the pixel circuit by the source driver. The current of the pixel and the OLED can be measured by a readout circuit. A value of a voltage from the measured current can be extracted and provided to a processor for further processing. |
| US10971075B2 |
Display device and electronic device including the same
It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed. |
| US10971074B2 |
Displays with multiple scanning modes
An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be enabled to emit light in each frame. In the partial scanning mode, only a subset of the rows of the display may be enabled to emit light in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. To ensure uniform transistor stress across the display, the scanning driver for the display may scan the disabled rows in the partial scanning mode even though the rows will not be used to emit light. |
| US10971067B1 |
AMOLED pixel driving circuit, driving method and terminal
The invention provides an AMOLED pixel driving circuit, driving method and terminal. The AMOLED pixel driving circuit adopts a 6T1C structure, comprising a first TFT, i.e., driving TFT, a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a storage capacitor and an OLED; the scan signal, the first light-emitting control signal and the second light-emitting control signal are combined to successively correspond to a reset phase, a compensation phase and a light-emitting phase, so that the driving current flowing through the OLED is independent of the threshold voltage of the driving TFT and the positive power voltage. The invention compensates for the threshold voltage drift of the driving TFT and also for the voltage drop in positive power voltage. |
| US10971064B2 |
Display apparatus
A display apparatus includes a display panel including a plurality of pixels configured to display an image, each of at least one of the plurality of pixels including a pixel circuit and a light emitting device connected to the pixel circuit, wherein the pixel circuit includes a driving transistor controlling a driving current flowing at the light emitting device, a data supply transistor selectively providing a data voltage to a first node which is a source electrode of the driving transistor, a first light emitting control transistor selectively connecting the first node to a second node which is an electrode of the light emitting device, a first capacitor connected between the second node and a fourth node which is a gate electrode of the driving transistor, and a second capacitor connected between the second node and a gate electrode of the data supply transistor. |
| US10971061B2 |
Control scheme for a scanning display
Techniques are described for operating a display system comprising a light source and a scanning assembly. The light source includes a plurality of emitters arranged in a column and circuitry configured to drive the emitters based on image data. The scanning assembly includes a reflective surface facing the light source, the reflective surface being rotatable in at least one dimension. A control signal including periodic, non-linear pulses causes the reflective surface to rotate through a range of scan angles, thereby forming an output image based on reflection of emitted light. The image data is supplied to the light source in synchronization with the rotational movement of the reflective surface. Changes in rotation speed due to the non-linear nature of the control signal are compensated for by adjusting emission durations for different rows to provide different emission durations at different times based on changes in the linearity of the control signal. |
| US10971059B2 |
Display device and control method thereof
A display device and a control method thereof are provided. The display device includes a display panel divided into n regions along a horizontal viewing direction, wherein n is a positive integer and n≥2, a detection unit configured to detect a viewing angle corresponding to each of the n regions, the viewing angle being an angle between a sight line of a human eye and the display panel, and a control unit configured to adjust, based on the viewing angle, one or both of a grayscale voltage value of the region of the display panel corresponding to the viewing angle, and brightness of a part of a backlight of the display panel corresponding to the region corresponding to the viewing angle. |
| US10971058B1 |
Display apparatus
A display apparatus includes pixels, each of which includes first and second pixel driver circuits, first and second driver pads electrically connected to the first and second pixel driver circuits, respectively, a first LED element, first and second connection lines electrically connected to the first and second pixel driver circuits, respectively, and first and second repair pads electrically connected to the first and second connection lines, respectively. A first electrode of the first LED element is electrically connected to the first driver pad. The first repair pad, the second repair pad, the first driver pad, and the second driver pad are structurally separated. A first pixel of the pixels further includes a second LED element overlapping the first and second repair pads of the first pixel, and a first electrode of the second LED element is electrically connected to the second repair pad. |
| US10971056B2 |
Display device
Provided is a display device that individually corrects luminance of an image to be displayed in a part of an image display area and an image to be displayed in the other area. The display device includes a display unit to display an entire image, and a luminance correction controller to correct luminance of the entire image. The entire image is an image in which a first image displayed in a first display area being an area except a second display area is superimposed by a second image displayed in the second display area that is set in a part of the image display area. The luminance correction controller respectively corrects the luminance of the first and second images by using the first and second luminance correction coefficients. The display unit displays first and the second images each having corrected luminance respectively in the first and second display areas. |
| US10971055B2 |
Display adjustment method and display device
The present application discloses a display adjustment method and a display device. The method comprises steps of: obtaining a first pixel data of an image displayed by the display device; converting the first pixel data into a second pixel data after the first pixel data enters a timing controller; converting at least one of the second pixel data into sub-pixel data whose amount of stored data is reduced relative to the second pixel data to obtain a corresponding third pixel data; outputting the third pixel data. |
| US10971049B2 |
Display device, interface unit and display system
A display device includes: a connector unit including a plurality of receiving electrodes configured to receive an input signal from a plurality of transmission electrodes of an interface unit having a flat plate shape; a signal processor which determines an arrangement of an input data included in the input signal; and a display output portion which performs an image output processing according to the arrangement of the input data determined by the signal processor, wherein the plurality of receiving electrodes are disposed to face the plurality of transmission electrodes in each of a plurality of connection directions defined by in-plane rotation angles of the interface unit, in a predetermined region which the interface unit opposes, and wherein the signal processor determines the arrangement of the input data according to the connection direction of the interface unit. |
| US10971048B2 |
Signal transmission method, transmitting unit, receiving unit and display device
The present disclosure relates to a method and device for transmitting a signal in a display device. The display device comprises a timing controller and a source driver. The method is applied to any of a plurality of transmitting units of the timing controller. The plurality of transmitting units correspond to a plurality of receiving units of the source driver in a one-to-one relationship. The method comprises: obtaining a scrambled signal by scrambling, via a scrambler of the transmitting unit, a non-identification signal in a signal to be transmitted, the scrambled signal comprising an identification signal and a scrambled non-identification signal; and transmitting the scrambled signal to a corresponding receiving unit. A signal obtained by scrambling a signal X via the scrambler is X16+X5+X4+X3+1, X24+X4+X3+X+1 or X32+X7+X5+X3+X2+X+1. The present disclosure reduces distortion of an image displayed on a display panel. |
| US10971044B2 |
Methods and systems for measuring electronic visual displays using fractional pixels
Systems and methods for measuring characteristics of an electronic visual display are disclosed herein. A method configured in accordance with embodiments of the present technology for measuring an electronic visual display can include, for example, analyzing a region of interest (“ROI”) in an image taken of at least a portion of the electronic visual display. The method determines a center and bounds of the ROI that are, in general, floating point values rather than whole pixel locations. The method then samples whole imaging device pixels and/or fractional imaging device pixels within the bounds of the ROI and determines whether the pixels and/or fractional pixels fall within, outside, or partially within the ROI. Depending on the position of the pixels and/or fractional pixels relative to the ROI, the pixels and/or fractional pixels can be weighted and/or summed to determine an overall image characteristic for the ROI. |
| US10971042B2 |
Reliability test fixture for flexible display component and online reliability test device for flexible display component
Disclosed are a reliability test fixture and an online test device for a flexible display component. The fixture comprises a support and a rotating shaft rotatably mounted on the support. An engagement recess for fixing a flexible display component is provided in an axial direction on the surface of the rotating shaft. A test module used to detect an electrical parameter of an internal circuit of the flexible display component is disposed inside the rotating shaft. The test module has a test contact for electrically connecting to the flexible display component. During a test, the flexible display component is fixed in the engagement recess and is electrically connected to the test module. |
| US10971041B2 |
Electronic display device and information display method of same
Provided are an electronic display device and an information display method of same, the electronic display device enabling recognition by means of a tactile sensation or three-dimensional visual recognition with respect to an object. |
| US10971040B2 |
Display device and method for controlling display device
A projector includes: a projection unit having a light modulation device and projecting a projection image via the light modulation device; an image pickup unit picking up the projection image projected by the projection unit and generating picked-up image data; a decision unit deciding a first elimination execution time for which an elimination function to eliminate burn-in on the light modulation device is executed, based on the picked-up image data; and a processing unit executing the elimination function during the first elimination execution time decided by the decision unit. |
| US10971039B1 |
Display system for guitar sound hole
A display system for use in a sound hole of a guitar, the display system includes legs extending outwardly from a central point; a base connected to the legs; and a top plate rotationally connected to the base, the top plate having a weight such that the weight rotates to a bottom location during any manipulation of the base; the legs are to engage with the guitar to secure the display system within the sound hole. |
| US10971034B1 |
Dynamic partitioning of a refreshable braille display based on presence of ancillary alphanumeric content
A method of automatically partitioning a refreshable braille display based on presence of pertinent ancillary alphanumeric content. In an unpartitioned configuration, every braille cell of the refreshable braille display is used to output the primary alphanumeric content. When the refreshable braille display outputs a segment of the primary alphanumeric content having associated ancillary alphanumeric content, such as a footnote or a comment, the braille display is automatically partitioned into a first partition and a second partition. The braille cells of the first partition are allocated for outputting the primary alphanumeric content, while the braille cells of the second partition are allocated for outputting the ancillary alphanumeric content. |
| US10971033B2 |
Vision assistive device with extended depth of field
The present disclosure relates to a vision assistive device for use by blind or low vision users. The device includes an imaging unit for viewing objects positioned beneath the device. The device further includes a forwardly facing screen for displaying an enlarged view of the imaged object to the user. The imaging unit is configured to take multiple views of the object, each with a different area of focus. This can be accomplished by digitally changing the imaging sensor's area of focus or by pivoting the sensor via a focus motor. In either event, the resulting images are combined into a single, integrated, focused, and composite image. Combining images with differing areas of focus helps eliminate any blurry regions in the composite image. The device further includes a rearwardly positioned fin that facilitates positioning the device in multiple different orientations. In a first orientation, the device is vertically positioned upon a desktop. In a second orientation, the device is reclined and placed in the user's lap with the fin positioned between the user's legs. |
| US10971030B2 |
Remote physical training
A system and method perform remote physical training. The method includes receiving movements performed by an operator who is remotely located, and presenting the movements of the operator as movements performed by an avatar representing the operator in a virtual reality environment. The method also includes remotely monitoring the movements of the avatar, and providing real-time feedback on the movements to the operator. |
| US10971025B2 |
Information display apparatus, information display terminal, method of controlling information display apparatus, method of controlling information display terminal, and computer readable recording medium
According to one embodiment, there is provided an information display apparatus including a processor, the processor being configured to: designate a character string in a text displayed in a display unit in accordance with a user operation; determine whether a keyword is included in a part of the designated character string; generate, if it is determined that the keyword is included in the part of the designated character string, problem setting data based on the keyword included in the designated character string; and transmit the problem setting data to an external terminal. |
| US10971022B2 |
Drone user equipment indication
The disclosure relates to drone user equipment (UE) indications that may be conveyed to a wireless network. In particular, a UE that has flight capabilities (i.e., capabilities to operate as an unmanned aircraft system) and optional further capabilities to report a current height level may indicate such capabilities to the wireless network. As such, the wireless network may differentiate the drone UE from other UEs that only operate on the ground. Furthermore, the optional current height level may enable the wireless network to differentiate among drone UEs operating at different heights and/or from other UEs that are operating on the ground. The wireless network may further use the information indicating the flight capabilities either alone or in combination with the optional height information to configure power control parameters, manage interference, provide mobility management functions, generate neighbor lists, control beamforming, or implement a radio resource configuration or management procedure. |
| US10971017B2 |
Sensor fusion and information sharing using inter-vehicle communication
Methods, systems and apparatuses for inter-vehicle communication, fusion of sensor information, and information sharing resulting from inter-vehicle communication are disclosed along with control of one or more vehicles in response to information from one or more other vehicles. |
| US10971014B2 |
Bollard receiver identification
The disclosure relates generally to methods, systems, and apparatuses for automated or assisted driving and more particularly relates to identification, localization, and navigation with respect to bollard receivers. A method for detecting bollard receivers includes receiving perception data from one or more perception sensors of a vehicle. The method includes determining, based on the perception data, a location of one or more bollard receivers in relation to a body of the vehicle. The method also includes providing an indication of the location of the one or more bollard receivers to one or more of a driver and component or system that makes driving maneuver decisions. |
| US10971009B2 |
Extracting events and assessing their impact on a transportation network
Methods and arrangements for assessing impact of an event on a network. An event notification is received relative to traffic in the network. Metadata are extracted from the notification, and the extracted metadata are converted into a predetermined format for processing. The converted metadata are received, and an impact of the event on traffic in the network is determined. Other variants and embodiments are broadly contemplated herein. |
| US10971007B2 |
Road condition information sharing method
Embodiments of the present invention disclose a road condition information sharing method. The method includes: receiving, by a server, a road condition information request sent by a first terminal, where the road condition information request carries a road condition position of concern; determining, by the server, a second terminal according to the road condition position of concern, where the second terminal has a road condition recording capability, and a distance between the second terminal and the road condition position of concern is less than a preset threshold; and sending, by the server, a road condition sharing request to the second terminal, so that the second terminal shares a road condition according to the road condition position of concern. |
| US10971006B2 |
Target vehicle selection and message delivery in vehicular systems
According to an aspect, a method for selecting target vehicles for transmission by a vehicular message distribution entity is provided. Initially, map information and driving context information of a plurality of vehicles is maintained in a database of the vehicular message distribution entity in a communications system. Upon receiving from a first source vehicle a vehicular message comprising at least driving context information, the vehicular message distribution entity selects one or more vehicles in proximity of the first source vehicle from the plurality of vehicles based on geographical locations of said vehicles. Then, the vehicular message distribution entity further selects a first set of one or more target vehicles from the one or more vehicles based on driving context information and the map information. Finally, the vehicular message distribution entity causes sending the vehicular message to the first set using unicast transmission. |
| US10971005B1 |
Determining I2X traffic-participant criticality
For each pair of traffic participants (TPs) entering an intersection, a time to collision (TTC) value is calculated. A matrix of TTC values between TPs entering the intersection is created. A matrix of criticality values containing a respective criticality value for each pair of TPs is created. Each criticality value is determined as a function of both TTC and at least one additional weighting factor. A basic safety message (BSM) and/or a pedestrian safety message (PSM) is broadcast on behalf of at least one traffic participant based on having determined the criticality for each pair of traffic participants and having identified a near-miss and/or a potential-collision situation between traffic participants based on the respective criticality values in the matrix of criticality values. One or more warnings are provided to a pedestrian, a driver of a vehicle, and/or a cyclist based on the broadcasted BSM and/or PSM. |
| US10971004B2 |
Density based traffic light control system for autonomous driving vehicles (ADVs)
In one embodiment, a system receives vehicle information from one or more ADVs. The system determines a location and a heading of each ADV from the vehicle information of the ADV. For each of the ADVs, the system determines if the ADV is approaching a traffic light junction based on the location and the heading of the ADV. The system sends the vehicle information of the ADVs to a traffic light control system in response to determining the ADV is approaching the traffic light junction, where the vehicle information is used by the traffic light control system to direct a traffic flow at the traffic light junction, including adjusting a time duration of a light signal at one or more traffic lights disposed at the traffic light junction in advance of the ADVs arriving at the traffic light junction. |
| US10971003B2 |
Systems and methods for predicting pedestrian behavior
Exemplary embodiments described in this disclosure are generally directed to systems and methods for predicting a behavior of a pedestrian on the basis of a behavioral profile of the pedestrian. The behavioral profile may be generated in a personal communication device of the pedestrian (such as a smartphone) based on activities performed by the pedestrian such as walking on a sidewalk, stepping off the sidewalk to walk on a road, standing on a sidewalk waiting for a traffic light to change, stepping onto the road when waiting for a traffic light to change, and/or crossing a road when the traffic light is red. The behavioral profile may also be based on other factors such as a traffic citation, an accident report, a status of a driver's license, and/or physical characteristics of the pedestrian (age, gender, etc.). |
| US10970993B2 |
Method for managing the assistance to a person in response to the emission of an alert
A method for managing the assistance to a person in response to the emission of an alert includes emitting an alert from a piece of mobile equipment of a first user to a plurality of users; establishing a first two-way communication between the first equipment and a given terminal of the first set of an assisting user; automatic generating of a plurality of first notifications to a subset of terminals of the first set, each one of the notifications including at least one piece of data that identifies the assisting user; automatic generating of a plurality of second notifications to the second subset, each second notification including a status relative to the processing of the alert by the assisting user. |
| US10970992B2 |
Emergency notification apparatus and method
A system, apparatus and method for alerting an emergency responder to an emergency, which includes a processor obtaining data from at least one sensor, determining, that the data indicates an emergency condition, based on the determining, obtaining location information and a unique identifier, and communicating the location information and the unique identifier to a node via a network connection. |
| US10970988B2 |
Information processing apparatus, information processing system, method, and program
In an apparatus configured to monitor a person in a predetermined area, location information indicating a location of the person and information indicating a destination of the person in the predetermined area are acquired for each of a plurality of persons present in the predetermined area. A contact between the persons is detected using the location information. Using the information indicating the destination of each of the persons detected as having contacted, it is determined whether the contact is an unauthorized contact, and a determination result is output. |
| US10970985B2 |
Sensor device and system
Embodiments of a sensor device, method and system employ a multiplicity of environmental sensors as a single monitoring and alerting mechanism, operable to provide a profile of any contaminant in terms of various gases and particles in the atmosphere, quantified in terms of relative concentrations. In various embodiments, the sensor device can comprise hardware and firmware elements, including an electronic control system, a case, a shield and a cover. The environmental sensors can be secured as part of the electronic control system and the shield can be formed so as to facilitate proper channeling of air and sound for effective operation. |
| US10970978B2 |
Method for the broadcasting, by a watch, of an informative message relating to an evaluation of the quality of life of a wearer of said watch
A method for the broadcasting by a watch of an informative message relating to an evaluation of the quality of life of a wearer of the watch includes the following steps: recording, by the processing unit, of data describing at least one factual episode of at least one type of environmental event recorded during a given period; identifying at least one type of environmental event disturbing the quality of life of the wearer from processing of the descriptive data; estimating an evaluation index of the quality of life of the wearer according to an indicator of disturbance of the quality of life relating to each type of environmental event disturbing the quality of life identified, and design of the informative message including the estimated evaluation index in prediction of its broadcasting to the wearer. |
| US10970977B2 |
Radio tag reading device and method
A radio tag reading device includes a placement table, an antenna, a reader, a sensor, and a controller. The antenna is configured to communicate with wireless tags within a communication range covering a placement region of the placement table. The reader is configured to output commodity information based on a signal received by the antenna from wireless tags. The sensor is configured to detect a user near the placement region of the placement table. The controller is configured to start a reading operation by activating the reader and causing the antenna to start emitting radio waves upon the sensor detecting the user near the placement region. |
| US10970976B2 |
End user protection against ATM keypad overlay
Methods, systems, and computer program products for data entry device security are provided. Aspects include receiving an indication of a user presence at a data entry device, wherein the data entry device includes a surface with apertures, and wherein the apertures include a material with a reflection coefficient. A presence of a fraud device is determined by emitting, from beneath the surface, security light from a set of one or more emitters, wherein the security light has a security light luminous power. A reflection of the security light off the material is collected by a first set of one or more sensors, wherein the reflection has a reflection luminous power. A luminous power range is determined based on the security light luminous power and the reflection coefficient and based on the reflection luminous power being outside the luminous power range, security measures are engaged at the data entry device. |
| US10970975B2 |
End-to-end secured currency dispensing
A managing computing device positioned in an ATM can receive a dispense request for an amount of currency and account information from a user. A controller of a currency dispenser can generate a first number. The first number, the dispense request, and the account information can be sent to a remote, host computing device that shares a secret key with the controller. The host device can generate a first message authentication code (MAC) based on at least one of the first number and the amount of currency and can send it to the controller. The controller can generate a second MAC based on at least one of the first number and the amount of currency, confirm identity between the first and second MACs, and control the currency dispenser to dispense the amount of currency to the user. |
| US10970974B2 |
Amusement devices and games involving multiple operators, multiple players, and/or multiple jurisdictions
Various methods and apparatus related to gaming are described. Some embodiments relate to a multi-tiered game involving multiple participants. Some embodiments relate to players from a plurality of gaming operators playing games with one another. Other embodiments are described. |
| US10970973B1 |
Card-based electronic gaming systems and techniques for five-card draw poker
In one implementation, an electronic five-card draw poker gaming system using common physical cards includes a plurality of physical playing cards; a scanner that is configured to identify each of the plurality of physical playing cards as they are dealt; a plurality of player computing equipment with graphical displays that are programmed to provide individualized gaming interfaces for a plurality of players; and a gaming computing system that is communicably connected to the scanner and the plurality of player computing equipment to determine five-card draw poker gaming outcomes for each of the plurality of players based on commonly dealt cards and player actions. |
| US10970971B2 |
Regulated casino games and gaming machines configured to offer conditional wins and/or conditional win opportunities
A computer-implemented method of operating a computing device may comprise accepting, by the computing device, funds from a player and enabling the player to play a wager-based game using the accepted funds. The wager-based game may be configured to present a plurality of in-game assets for player interaction during the game, at least some of the plurality of in-game assets being configured as wagering opportunities, such that player interactions therewith generates wagers. Player interactions with the wagering opportunities may be received and wagers generated upon receiving player interactions with the wagering opportunities. During game play of the wager-based game, a conditional prize may be presented to the player, an award of which being predicated upon receiving future player interactions indicative of the player having caused a predetermined in-game action or in-game result to have occurred. Game play of the wager-based game may be continued and a determination may be made as to when the predetermined in-game action or predetermined in-game result occurs. The conditional prize may be awarded to the player when the predetermined in-game action or predetermined in-game result has been determined to have occurred and the wager-based game may forego awarding the conditional prize to the player when the accepted funds run out, when a player interaction is received that is indicative of a cash out event before the counted number of generated additional wagers equals the predetermined number of additional wagers or when a player interaction is received that is indicative of the player choosing to forego the award of the conditional prize. |
| US10970969B2 |
Wagering apparatus, methods and systems
A system, method and apparatus provides a unique betting product where multiple players or groups of players may construct and contribute to (“crowdfund”) one or more tickets and behave as a single “player”. Players make selections in one or more different events. Players who are in contention to win may be offered an opportunity to sell their tickets, in whole or in part, in response to a full or partial buy-out offer made at any time prior to completion of a wagering event. |
| US10970968B2 |
System and method for incentivizing the maintenance of funds in a gaming establishment account
The present disclosure relates generally to a system that provides zero, one or more benefits to a user in association with maintaining an amount of funds in one or more gaming establishment accounts associated with one or more system components. |
| US10970967B2 |
Electronic voucher ticket system
A voucher ticket system and method of use employing a bill validator installed into any suitable automated machine, including an Automated Teller Machine (ATM), a gaming machine, etc. The bill validator is integrated with a bill reader, a voucher ticket reader, a reader to obtain an electronic voucher ticket from a portable computing device, a printer, and any other supporting peripheral devices. The method processes a deposit, a withdrawal, a transfer and a management of a financial balance of each account. The electronic money handling terminal and the electronic money transaction server communicate through an electronic money handling terminal interface. Upon recognition of an electronic money account of a gaming player, the system receives a voucher ticket master ID issued by a voucher ticket management system at the cash-out, and proceeds with a cash out event to the electronic money account. |
| US10970963B2 |
Coin operated entertainment system
This invention in certain example instances relates generally to coin-operated video entertainment systems. More particularly, certain exemplary aspects of the invention provide methods and/or systems for controlling access to a portable coin-operated interactive entertainment device that may be used to play video games and access other forms of entertainment as well as providing features via such portable coin-operated interactive entertainment devices. |
| US10970962B2 |
Management system of substitute currency for gaming
A detection system including a control device detecting fraud performed in a game table by using a result of an image analysis performed by an image analyzing device is included. A substitute currency for gaming used for this detection system has a multi-layer structure in which a plurality of plastic layers having different colors are stacked, a coloring layer is included at least in the middle, and white layers or thin-color layers (may be layers having a color thinner than that of the coloring layer; not illustrated in the drawing) are stacked on both sides of the coloring layer disposed in the middle. |
| US10970960B2 |
Interactive video gaming system involving a matching feature and multiple pay tables and method of utilizing the same
A system and method for operating a casino-style video game with a matching feature whereby players seek to group like game icons with one another. The system may use multiple pay tables with a relevant pay table being selected based on the number of grouped game icons forming a winning pattern such that the greater the number of matched or grouped game icons, the greater the return to player (RTP) associated with the corresponding pay table. |
| US10970957B1 |
Systems and methods for simulating player behavior using one or more bots during a wagering game
A method includes initiating, by a processor, a simulated multiplayer game, and controlling, by the processor a display device to display a plurality of selectable items. The method also includes selecting, by the processor, a plurality of bots from a bot selection table, where the bot selection table includes a bot selection weight associated with each bot of the plurality of bots, and where each bot simulates a player behavior. The method also includes determining, by the processor and from a timed entry distribution table, an entry time for at least one bot of the plurality of bots in the simulated multiplayer game, and controlling, by the processor, the display device to simulate a selection, by the at least one bot, of at least one selectable item at the determined entry time. |
| US10970955B2 |
Accounting device and control program
An accounting device according to an embodiment includes an input device that receives an instruction to start a job. A first display device includes a first screen facing a first direction towards a person who operates the input device. A change machine includes a depositing port for receiving money and a dispensing port for dispensing money. A second display device includes a second screen facing a second direction different from the first direction and towards a person who deposits money into the depositing port or receives money from the dispensing port. When the instruction received by the input device is to start a predetermined job that is different from the accounting transaction and that includes depositing money into the change machine or dispensing money from the change machine, the processor causes information supporting execution of the predetermined job to be displayed on the second screen. |
| US10970949B2 |
Secure access control
An access controller combines one or more Secure Access Modules (SAMs) or other cryptographic processors with embedded storage, individually accessible by the controller such that waiting on the reply from one of the modules does not prevent accessing the others, a host CPU, running the computer program to perform authentication and access control, and a waiting queue, possibly in system memory, to put the request in when all SAMs are used. The state of the SAMs, possibly using system memory, is tracked to be able to find a free access module or to be able to match a response to the corresponding request. One or more connections (serial, network, wireless or otherwise) are used to connect to transparent smart card readers and door controllers. |
| US10970948B2 |
Systems, devices, and methods for access control and identification of user devices
Disclosed systems and methods provide access control and/or identification of user devices. A method may include receiving, by a processor circuit on a user's mobile device, a first user-profile including one or more first access rules governing the user's access rights to a point-of-entry device during non-emergency situations. The method may further include receiving, in response to an emergency event, a second user-profile including one or more second access rules governing the user's access rights to the point-of-entry device during emergency situations. When the user attempts to gain access to the point-of-entry device, the method may include determining a decision to grant or deny access to the point-of-entry device based on the first or second user-profile during non-emergency and emergency situations, respectively. Lastly the method may include transmitting the decision to grant or deny access to the point-of-entry device. |
| US10970947B1 |
System and method to provide a rear window wiper usage notification
One general aspect includes a method to provide a rear window wiper notification, the method including: when a rear window wiper is in an active state, via a processor, establishing a time duration; and when the rear window wiper remains in the active state throughout the time duration and after a conclusion of the time duration, via the processor, providing the rear window wiper notification in an interior cabin of a vehicle. |
| US10970943B2 |
Method and apparatus for a vehicle force indicator
The present disclosure relates to methods and apparatus to provide a vehicle force indicator responsive to one or more of: an amount of tilt of a motor vehicle, an amount of acceleration and/or deceleration of the motor vehicle and a correlation of tilt and speed with location of the motor vehicle. |
| US10970942B2 |
Fog data agent for connected cars
A fog data agent for a connected car includes a connector configured to couple to an on-board diagnostic port of the connected car, a microprocessor, a wireless communication interface coupled to the microprocessor, a cellular communication interface coupled to the microprocessor, a data storage device coupled to the microprocessor, and logic configured to receive data from the on-board diagnostic port, analyzes the data in real-time, and establish a bi-directional communication channel with a remote server via at least one of the wireless communication interface and the cellular communication interface to transmit a subset of the analyzed data to the remote server in response to the data analysis. |
| US10970941B2 |
All seeing one camera system for electronic tolling
A method of electronic tolling for a vehicle travelling on a road surface includes providing a single camera or a single array of cameras, arranging the single camera or the single array of cameras to have a field-of-view that is normal to the road surface and is defined by a plane that is parallel with the road surface, and capturing multiple images of the front, side, top and rear of the vehicle using the single camera or the single array of cameras in the field-of-view. The set of multi-perspective images can be used to identify a vehicle by reading the front and rear license plate and to determine a classification of the vehicle. The images may also be used to track the position of the vehicle on the road surface as the vehicle traverses the field-of-view. |
| US10970938B2 |
Method and apparatus for generating 3D information
Embodiments of the present disclosure provide a method and apparatus for generating information. A method may include: selecting a three-dimensional object model from a preset three-dimensional object model set based on a to-be-matched object image in a target two-dimensional image; determining, based on a normal vector of a ground plane of the target two-dimensional image, a plane equation of ground corresponding to the normal vector of the ground plane in a three-dimensional space; adjusting a rotation parameter and a translation parameter of the three-dimensional object model in the plane characterized by the plane equation; and generating, in response to determining that a contour of the adjusted three-dimensional object model matches a contour of the to-be-matched object image in the target two-dimensional image, three-dimensional information of an object corresponding to the to-be-matched object image based on the adjusted three-dimensional object model. |
| US10970935B2 |
Body pose message system
A person who is not using a hybrid reality (HR) system communicates with the HR system without using a network communications link using a body pose. Data is received from a sensor and an individual is detected in the sensor data. A first situation of at least one body part of the individual in 3D space is ascertained at a first time and a body pose is determined based on the first situation of the at least one body part. An action is decided on based on the body pose and the action is performed on an HR system worn by a user. |
| US10970933B2 |
Device, system and method for embedding one or more attributes in a graphical object
A system for embedding or attaching to one or more attributes to a graphical object may is disclosed. The system includes a user device configured to obtain a graphical object. The graphical object includes at least one of an image or a geolocation. The system also includes a server communicatively coupled to the user device. The server includes a marker subsystem configured to create at least one marker on the graphical object. The server also includes an embedding subsystem configured to embed one or more attributes in the graphical object. The one or more attributes includes a video, an augmented reality video, a 3-dimensional content, a hyperlink or a text. The server further includes a queue manager configured to process and upload the embedded graphical object. The server further includes an alert subsystem configured to generate a notification upon uploading of the embedded graphical object. |
| US10970927B2 |
Positionable emissions control watercraft
A positionable emissions control watercraft that may be placed near a serviced watercraft in a location that is away from the risk of falling cargo, while also eliminating a need for a spacer or a spacer barge, and allowing other service watercraft to access the serviced watercraft. |
| US10970925B2 |
Method for creating a curved covering from flat material
A method includes providing a three-dimensional representation of a doubly curved surface as a smooth function or triangulated mesh. The three-dimensional surface is cut into one or more panels representing each panel by a triangulated mesh. A two-dimensional approximation of the set of panels is created by representing the two-dimensional pattern as a triangulated mesh that is topologically equivalent to the three-dimensional meshes representing the panels. |
| US10970918B2 |
Image processing method and apparatus using a pixelated mask image and terminal orientation for a reflection effect
An image processing method and an apparatus relate to the field of image processing and add a diffuse reflection effect to a projection image in real time and reduce a calculation volume of adding the diffuse reflection effect. The method includes obtaining a first image that includes a diffuse reflection object, where the first image is an image obtained when the diffuse reflection object is illuminated by a light source, obtaining a mask image corresponding to the diffuse reflection object, obtaining orientation information of a terminal and obtaining a second image based on the orientation information, the first image, and the mask image, where the second image is an image that includes the diffuse reflection object and a diffuse reflection effect and that is generated by superposing the first image and the mask image moved based on the orientation information. |
| US10970911B2 |
Graphics processing chip with machine-learning based shader
Embodiments disclosed herein relate to a graphics processing chip for rendering computer graphics. The graphics processing chip may include a controller configured to manage operations of the graphics processing chip in accordance with a graphics-rendering pipeline. The operations may include geometry-processing operations, rasterization operations, and shading operations. The chip may further include programmable memory components configured to store a machine-learning model configured to perform at least a portion of the shading operations. The chip may also include a plurality of processing units configured to be selectively used to perform the shading operations in accordance with the machine-learning model. The chip may also include at least one output memory configured to store image data generated using the shading operations. |
| US10970900B2 |
Electronic apparatus and controlling method thereof
An artificial intelligence (AI) system using an artificial intelligence model learned according to at least one of machine learning, a neural network, or a deep-learning algorithm, and an application, and a method of controlling an electronic apparatus therefor are provided. The method includes acquiring a text based on a user input, determining a plurality of key terms from the acquired text, acquiring a plurality of first illustrations corresponding to the plurality of key terms, acquiring a second illustration by synthesizing at least two or more first illustration of the plurality of first illustrations, and outputting the acquired second illustration. |
| US10970892B2 |
Electronic apparatus for drawing figure based on function data stored in advance or based on drawing data received from server depending on type of figure to be drawn, and information processing method, system, and medium for same
An electronic apparatus includes a memory, a display, and a processor. The processor obtains an instruction on a figure-related process. If a type of a figure indicated by the instruction is a type unable to be drawn with function data stored in the memory, the processor: sends relevant data to at least one server; receives, from the server, drawing data generated by the server executing, based on the relevant data, an arithmetic operation required for the figure-related process; and performs the process on the display in accordance with the drawing data. If the type is a type able to be drawn with the function data, the processor executes an arithmetic operation required for the figure-related process using the function data without requesting the server to execute the arithmetic operation, and performs the process on the display in accordance with drawing data generated as a result of the arithmetic operation. |
| US10970891B2 |
Systems and methods for detecting and accommodating state changes in modelling
Techniques are described for automatically detecting and accommodating state changes in a computer-generated forecast. In one or more embodiments, a representation of a time-series signal is generated within volatile and/or non-volatile storage of a computing device. The representation may be generated in such a way as to approximate the behavior of the time-series signal across one or more seasonal periods. Once generated, a set of one or more state changes within the representation of the time-series signal is identified. Based at least in part on at least one state change in the set of one or more state changes, a subset of values from the sequence of values is selected to train a model. An analytical output is then generated, within volatile and/or non-volatile storage of the computing device, using the trained model. |
| US10970890B2 |
Maze solving method based on line-surface spatial relation
A maze-solving method includes converting extracted channel surface-shaped data into channel boundary lines; extending extension lines from two end points at a start point and at a terminal point, to two sides outside a maze, and constructing, outside the maze, a virtual connection line I and a virtual connection line II connecting base points on the extension lines of the start point and the terminal point; respectively enclosing a polygon I and a polygon II by means of the virtual connection line I and the channel boundary lines and by means of the virtual connection line II and the channel boundary lines, in which paths connecting the start point and the terminal point, between the polygon I and the polygon II are alternative solution paths for the maze; and selecting an alternative solution path with the shortest length as the optimal solution path for the maze. |
| US10970888B2 |
Information processing device, information processing method and program
According to an embodiment of the present technology, there is provided an information processing device including an acquisition unit configured to acquire multiple images to which position information showing an imaging position is attached, and a display control unit configured to display a first map on which a pointer indicating the imaging position shown by the position information is displayed while switching a reduced scale and a display area according to an operation of a user, and configured to display a second map of a fixed reduced scale together with the first map while causing a display area to cooperate with a display area of the first map. |
| US10970881B2 |
Fallback modes for display compression
Provided is a display stream codec for a display device including an encoder, wherein the encoder is configured to determine a fallback display mode as a display mode for a current block to be encoded, represent a mode signaling of the fallback display mode that is identical to a mode signaling of a regular display mode corresponding to the fallback display mode, encode the current block in accordance with the fallback display mode using a same signaling syntax as the corresponding regular display mode, and send the encoded current block. |
| US10970879B2 |
Formulation systems and methods employing target coating data results
A computer system for seeding a formulation engine receives spectrometric data from a target coating. The computer system processes the spectrometric data through a probabilistic colorant analysis. The probabilistic colorant analysis generates a set of colorants. Each colorant within the set of colorants is associated with a calculated probability that the associated colorant is present within the target coating. Additionally, the computer system adds at least a portion of the colorants within the set of colorants to a formulation engine. The portion of the colorants is added to the formulation engine in order of decreasing probability. Further, the computer system generates, from an output of the formulation engine, a coating formulation that is calculated to match the target coating within a predetermined qualitative threshold. |
| US10970878B2 |
Camera calibration using reference map
In one embodiment, a computing system accesses a number of features extracted from one or more first images. The extracted features are associated with at least one object captured in the first images. The first images are captured by a camera associated with a vehicle. The computing system identifies, in a reference map, reference features matching one or more of the features extracted from the first images. The reference features are associated with the at least one object captured in the first images. The computing system generates, for the camera, a calibration model by comparing the identified reference features in the reference map and the features that match the one or more reference features. The calibration model is used to calibrate second images captured by the camera associated with the vehicle. |
| US10970877B2 |
Image processing apparatus, image processing method, and program
An image processing apparatus, an image processing method, and a program that permit camera calibration with high accuracy by using a known object in images captured by a plurality of imaging sections. An estimation section estimates a 3D position of a road sign included in each of images captured by a plurality of cameras with respect to each of the imaging sections. A recognition section recognizes a positional relationship between the plurality of cameras on the basis of the 3D position of the road sign with respect to each of the cameras estimated by the estimation section. The positional relationship between the plurality of cameras recognized by the recognition section is used to correct the images captured by the plurality of cameras. |
| US10970876B2 |
Methods and apparatus for image locating relative to the global structure
Certain aspects of the present disclosure relate to methods and apparatus for implementing image locating relative to a global structure. The method generally includes mapping one or more close-up images of a structure to a 3D model of the structure, and indicating, on an overview image of the structure, the location of the one or more close-up images based on the mapping. |
| US10970875B2 |
Examination support device, examination support method, and examination support program
An image acquisition unit acquires an actual endoscopic image that is generated by an endoscope inserted into a tubular structure of a subject and represents an inner wall of the tubular structure, and a virtual endoscopic image that is generated from a three-dimensional image including the tubular structure of the subject and spuriously represents the inner wall of the tubular structure. A conversion unit converts an expression form of the actual endoscopic image into an expression form of the virtual endoscopic image. A similarity calculation unit calculates similarity between the converted actual endoscopic image and the virtual endoscopic image. |
| US10970871B2 |
Estimating two-dimensional object bounding box information based on bird's-eye view point cloud
Upon receiving a set of two-dimensional data points representing an object in an environment, a bounding box estimator estimates a bounding box vector representative of a two-dimensional version of the object that is represented by the two-dimensional data points. |
| US10970870B2 |
Object detection apparatus
An object detection apparatus includes: a camera; a map database; a radar sensor; and an electronic control unit configured to detect a first object in a camera image, detect a first relative position of the first object relative to the road structure in the camera image, detect a second object based on a result received by the radar sensor, detect a second relative angle and a relative distance between the host vehicle and the second object, estimate a second relative position of the second object relative to the road structure, determine, based on the first relative angle, the first relative position, the second relative angle, and the second relative position, whether the first and second objects belong to the same object, and recognize the first and second of as the same object, when it is determined that the first and second objects belong to the same object. |
| US10970866B2 |
Shape information generation apparatus, control apparatus, loading/unloading apparatus, logistics system, non-transitory computer-readable medium, and control method
A control apparatus includes a first information acquiring section that acquires three-dimensional information of a first region of surfaces of a plurality of objects, the information being obtained by imaging or scanning the plurality of objects from a first location; a second information acquiring section that acquires three-dimensional information of a second region of surfaces of the plurality of objects, the information being obtained by imaging or scanning the plurality of objects from a second location; and a combining section that generates information indicating three-dimensional shapes of at least a portion of the surfaces of the plurality of objects, based on the three-dimensional information of the first region acquired by the first information acquiring section and the three-dimensional information of the second region acquired by the second information acquiring section. |
| US10970861B2 |
Method of determining a transformation matrix
A method (200) of determining a transformation matrix for transformation of ranging data from a first coordinate system for the ranging sensor to a second coordinate system for an image sensor is disclosed. The method comprises providing (201) a ranging sensor and an image sensor; acquiring (202) a ranging frame sequence, and an image frame sequence; determining (203) points of motion in frames of each acquired frame sequence; for each frame in one of the frame sequences: evaluating (204) if a single motion point has been determined in the frame, and if a single motion point has been determined, evaluating (206) if a single motion point has been determined in a temporally corresponding frame of the other frame sequence and, in that case, pairing (207) the temporally corresponding frames, whereby a set of frame pairs is formed, and determining (209) the transformation matrix based on the set of frame pairs. |
| US10970856B2 |
Joint learning of geometry and motion with three-dimensional holistic understanding
Described herein are systems and methods for jointly learning geometry and motion with three-dimensional holistic understanding. In embodiments, such approaches enforce the inherent geometrical consistency during the learning process, yielding improved results for both tasks. In embodiments, three parallel networks are adopted to predict the camera motion (e.g., MotionNet), dense depth map (e.g., DepthNet), and per-pixel optical flow between consecutive frames (e.g., FlowNet), respectively. The information of 2D flow, camera pose, and depth maps, are fed into a holistic 3D motion parser (HMP) to disentangle and recover per-pixel 3D motion of both rigid background and moving objects. Various loss terms are formulated to jointly supervise the three networks. Embodiments of an efficient iterative training strategy are disclosed for better performance and more efficient convergence. Performance on depth estimation, optical flow estimation, odometry, moving object segmentation, and scene flow estimation demonstrates the effectiveness of the disclosed systems and methods. |
| US10970853B2 |
Determining method of a virtual velocity vector of a mobile engine, associated computer program product and determining system
This method for determining a virtual speed vector includes the steps of acquiring (110) a sequences of images of the surrounding environment from an image sensor defining an optical projection center that is substantially stationary relative to the mobile engine, analyzing (120) at least two successive images in order to determine, in each of the two images, a point, called epipole, representing the position in said image of the optical center of the image sensor at the moment of the acquisition of the other image, and for each analyzed image, determining (130) the position of the epipole of said image on a display usable to pilot the mobile engine and displaying (130), on the display, a symbol representative of the virtual speed vector in said position. |
| US10970852B2 |
Systems and methods for multi-signature countermeasure testing
Systems, methods, and computer-readable media are provided for an autonomous and fully automated method of validating multi-signature decoys that are configured to release infrared flares at multiple points after launch. In one aspect, a method includes capturing, using at least one image capturing device, raw image data of a launched decoy, the decoy having one or more segments configured to be released after launch and automatically processing the raw image data to (1) identify a release point for each of the one or more segments and (2) identify an infrared signature associated with each release point. The method further includes generating a visual display of the release point(s) of the one or more segments and the infrared signature(s) originating from the release point(s). |
| US10970850B2 |
Method and device for recognizing motion
A method and device for recognizing a motion of an object, the method including receiving event signals from a vision sensor configured to sense the motion, storing, in an event map, first time information indicating a time at which intensity of light corresponding to the event signals changes; generating an image based on second time information corresponding to a predetermined time range among the first time information, and recognizing the motion of the object based on the image. |
| US10970849B2 |
Pose estimation and body tracking using an artificial neural network
According to one implementation, a pose estimation and body tracking system includes a computing platform having a hardware processor and a system memory storing a software code including a tracking module trained to track motions. The software code receives a series of images of motion by a subject, and for each image, uses the tracking module to determine locations corresponding respectively to two-dimensional (2D) skeletal landmarks of the subject based on constraints imposed by features of a hierarchical skeleton model intersecting at each 2D skeletal landmark. The software code further uses the tracking module to infer joint angles of the subject based on the locations and determine a three-dimensional (3D) pose of the subject based on the locations and the joint angles, resulting in a series of 3D poses. The software code outputs a tracking image corresponding to the motion by the subject based on the series of 3D poses. |
| US10970847B2 |
Document boundary detection using deep learning model and image processing algorithms
Techniques are disclosed for document boundary detection (BD) from an input image using a combination of deep learning model and image processing algorithms. Quadrilaterals approximating the document boundaries in the input image are determined and rated separately using both these approaches: deep leaning using convolutional neural network (CNN) and heuristics using image processing algorithms. Thereafter, the best rated quadrilateral is selected from the quadrilaterals obtained from both the approaches. |
| US10970845B2 |
Image processing apparatus, image processing method, and storage medium
It is possible to calculate transformation parameters used for image combining with a small error and to reduce a distortion that appears in a combined image The image processing apparatus includes: a feature point extraction unit configured to extract feature points corresponding to each other between both images from each of a first image and a second image, which are images obtained by capturing a paper document and whose captured ranges are different from each other; an edge extraction unit configured to extract edges corresponding to each other between both images from each of the images; a vanishing point detection unit configured to detect a vanishing point of a plane to which the paper document belongs from each of the images; a transformation parameter derivation unit configured to derive transformation parameters for image combining by using coordinates corresponding to intersections of straight lines connecting the feature points and the vanishing point, and the edges; and an image combining unit configured to combine the first image and the second image by using the transformation parameters. |
| US10970842B2 |
Method and device for identifying pathological picture
The invention discloses a method and a device for identifying pathological pictures, wherein the method comprises: obtaining sample data including a positive sample that is a pathological picture of malignant lesion and a negative sample that is a picture of normal tissue or a pathological picture of benign lesion, with a lesion area marked on the pathological picture of a malignant lesion; dividing the sample data into a training set and a testing set; training a deep neural network model using the training set; testing a trained deep neural network model using the testing set; adjusting parameters of the trained deep neural network model according to a testing result; identifying the pathological picture using the trained deep neural network model. The invention can improve the efficiency and accuracy of pathological picture identification. |
| US10970841B2 |
Processing fundus images using machine learning models
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing fundus images using fundus image processing machine learning models. One of the methods includes obtaining a model input comprising one or more fundus images, each fundus image being an image of a fundus of an eye of a patient; processing the model input using a fundus image processing machine learning model, wherein the fundus image processing machine learning model is configured to process the model input comprising the one or more fundus image to generate a model output; and processing the model output to generate health analysis data. |
| US10970838B2 |
Hough transform-based vascular network disorder features on baseline fluorescein angiography scans predict response to anti-VEGF therapy in diabetic macular edema
Embodiments facilitate prediction of anti-vascular endothelial growth (anti-VEGF) therapy response in DME or RVO patients. A first set of embodiments discussed herein relates to training of a machine learning classifier to determine a prediction for response to anti-VEGF therapy based on a vascular network organization via Hough transform (VaNgOGH) descriptor generated based on FA images of tissue demonstrating DME or RVO. A second set of embodiments discussed herein relates to determination of a prediction of response to anti-VEGF therapy for a DME or RVO patient (e.g., non-rebounder vs. rebounder, response vs. non-response) based on a VaNgOGH descriptor generated based on FA imagery of the patient. |
| US10970837B2 |
Automated uncertainty estimation of lesion segmentation
Methods and systems are provided for automatically estimating image-level uncertainty for MS lesion segmentation data. A segmentation network is trained to segment MS lesions. The trained segmentation network is then used to estimate voxel level measures of uncertainty by performing Monte-Carlo (MC) dropout. The estimated voxel level uncertainty measures are converted into lesion level uncertainty measures. The information density of the lesion mask, the voxel level measures, and the lesion level measures is increased. A trained network receives input images, the segmented lesion masks, the voxel level uncertainty measures, and the lesion level uncertainty measures and outputs an image level uncertainty measure. The network is trained with a segmentation performance metric to predict an image level uncertainty measure on the segmented lesion mask that is produced by the trained segmentation network. |
| US10970834B2 |
Defect discovery using electron beam inspection and deep learning with real-time intelligence to reduce nuisance
A deep learning algorithm is used for defect discovery, such as for semiconductor wafers. A care area is inspected with the wafer inspection tool. The deep learning algorithm is used to identify and classify defects in the care area. This can be repeated for remaining care areas, but similar care areas may be skipped to increase throughput. |
| US10970833B2 |
Pipe image feature analysis using calibration data
One aspect provides a method, including: displaying, at a display screen, an image of an interior of a pipe, the image being obtained using a pipe inspection robot; accessing, using a processor, calibration data associated with the image; receiving, via an input device, user input marking at least a portion of the image; determining, using a processor, quantitative pipe feature data for at least one feature of the pipe using the marking and the calibration data; and providing, based on the determining, data associated with the at least one feature. Other aspects are described and claimed. |
| US10970831B2 |
Systems, devices, and methods for providing feedback on and improving the accuracy of super-resolution imaging
Systems, methods, and computer-readable media for feedback on and improving the accuracy of super-resolution imaging. In some embodiments, a low resolution image of a specimen can be obtained using a low resolution objective of a microscopy inspection system. A super-resolution image of at least a portion of the specimen can be generated from the low resolution image of the specimen using a super-resolution image simulation. Subsequently, an accuracy assessment of the super-resolution image can be identified based on one or more degrees of equivalence between the super-resolution image and one or more actually scanned high resolution images of at least a portion of one or more related specimens identified using a simulated image classifier. Based on the accuracy assessment of the super-resolution image, it can be determined whether to further process the super-resolution image. The super-resolution image can be further processed if it is determined to further process the super-resolution image. |
| US10970830B2 |
Image style conversion method, apparatus and device
The present disclosure relates to a method, an apparatus and a device for converting a style of an image, wherein the method comprises: acquiring a luminance component (Y) and chrominance components (U, V) in a YUV space of an image to be processed; performing a group convolution processing on the luminance component (Y) and the chrominance components (U, V) in the YUV space of the image to be processed to obtain content features and style features of the image to be processed; and performing a fusion processing on the content features, the style features and target style features of the image to be processed to convert the image to be processed into an image of a target style. |
| US10970828B2 |
Image processing apparatus, image processing system, image processing method, and recording medium
An image processing apparatus includes circuitry configured to: acquire a plurality of pieces of image data; determine, for each of the plurality of pieces of image data, a first representative color indicating a feature of a color representative of the image data, based on pixel values of the image data; calculate, based on the determined first representative color of the plurality of pieces of image data, a second representative color indicating a feature of a color representative of the plurality of pieces of image data; calculate, based on the first representative color and the second representative color of image data to be corrected, a correction parameter for color correction of the image data to be corrected among the plurality of pieces of image data; and perform the color correction on the image data to be corrected using the calculated correction parameter. |
| US10970823B2 |
System and method for detecting motion anomalies in video
A system for video anomaly detection partitions the input video into a set of input spatio-temporal regions according to parameters of the spatio-temporal regions of the training video indicative of a number of regions in each video frame defining a spatial dimension of each of the spatio-temporal regions and a number of video frames defining a temporal dimension of each of the spatio-temporal regions, and determines blurred, thresholded difference images for each of the input spatio-temporal regions to produce a set of blurred, thresholded difference images. Next, the system extracts a feature vector from each set of blurred, thresholded difference images to produce a set of input feature vectors, computes a smallest distance between each input feature vector and the training feature vectors corresponding to the same spatial region in the scene to produce a set of distances, and compares each distance from the set of distances with an anomaly detection threshold to detect anomalies in the input video of the scene. |
| US10970821B2 |
Image blurring methods and apparatuses, storage media, and electronic devices
Image blurring methods and apparatuses, storage media, and electronic devices can include: obtaining a main image and a secondary image obtained by photographing the same object with a dual-lens camera; obtaining depth data and depth confidence degree data according to the main image and the secondary image, the depth data indicating depth values of corresponding pixel points in the main image and the secondary image, and the depth confidence degree data indicating confidence degrees of the depth values in the depth data; correcting at least one depth value in the depth data according to the depth confidence degree data; and blurring the main image according to corrected depth data. |
| US10970820B2 |
System and method for deep learning image super resolution
In a method for super resolution imaging, the method includes: receiving, by a processor, a low resolution image; generating, by the processor, an intermediate high resolution image having an improved resolution compared to the low resolution image; generating, by the processor, a final high resolution image based on the intermediate high resolution image and the low resolution image; and transmitting, by the processor, the final high resolution image to a display device for display thereby. |
| US10970818B2 |
Sub-image based image generation
An image generation request is received, where the image generation request includes an image format of an image for generation. A static image corresponding to the received image generation request is obtained. Based on the image format, a plurality of sub-images for generation and corresponding to the image awaiting generation based on the image format is determined. Description information is obtained for each sub-image of the plurality of sub-images. Based on the description information for each sub-image, the plurality of sub-images are sorted as a plurality of sorted sub-images. The image is generated by generating, pre-processing, and adding each particular sub-image of the plurality of sub-images to an image file corresponding to the image format. |
| US10970817B2 |
Image magnifying apparatus
An image magnifying apparatus includes a processor configured to execute non-transitory machine readable instructions to configure the processor to, receive the image data, generate a first interpolation pixel between pixels of the image data, by applying a first interpolation method based on a high-band spectrum of the image data, generate a second interpolation pixel between pixels of the image data, by applying a second interpolation method not based on the high-band spectrum of the image data, identify a pattern of pixels of the image data by extracting peripheral pixels of an interpolation object position in the image data, select whether to apply the first interpolation method to the interpolation object position or whether to apply the second interpolation method to the interpolation object position, and output one of the first interpolation pixel and the second interpolation pixel, as an output interpolation pixel, based on the selection. |
| US10970813B2 |
Shaking image for registration verification
A method and system are described that allow a user to verify a registration proposal during an image-guided ophthalmic surgery. The system configured to perform the method has a processor and a non-transitory computer-readable medium accessible to the processor containing instructions executable by the processor to perform the method. |
| US10970807B2 |
Information processing apparatus and storage medium
An information processing apparatus includes an obtainment unit configured to obtain an image from an image capturing apparatus, a selection unit configured to select either of an estimation accuracy priority mode which prioritizes estimation accuracy of at least either one of a position and an orientation of the image capturing apparatus over a frame rate, and a frame rate priority mode which prioritizes the frame rate over the estimation accuracy, an estimation unit configured to estimate at least either one of the position and the orientation of the image capturing apparatus based on a feature of the image according to the mode selected by the selection unit, and a control unit configured to cause a display unit to display an image based on at least either one of the estimated position and the estimated orientation of the image capturing apparatus. |
| US10970804B2 |
Image processing device and image processing method for selecting regions based on gradiation for embedding a watermark
Certainty of detecting a watermark embedded in a color image is increased. Image data acquisition means of an image processing device acquires image data. Histogram generation means generates, based on pixel values of an image indicated by the image data acquired by the image data acquisition means, a histogram for each region in the image. Region selection means selects tom the image a region having a sparse color distribution in the histogram generated by the histogram generation means. Image processing means embeds a watermark in the region selected by the region selection means. |
| US10970801B2 |
Configuration method and system of indication device for driver-passenger matching
Embodiments of the disclosure provide a method for configuring indication devices in transportation services. The method includes receiving a first transportation request which includes a first passenger pick-up point located in a preset geographical area, and the first transportation request matches a first vehicle associated with a first indication device. The method also includes receiving a second transportation request which includes a second passenger pick-up point located in the preset geographical area, and the second transportation request matches a second vehicle associated with a second indication device. The method further includes determining a time difference between a first estimated time for the first vehicle to arrive in the preset geographical area and a second estimated time for the second vehicle to arrive in the preset geographical area, and sending first indication information to the first indication device and second indication information to the second indication device according to the time difference. |
| US10970799B2 |
Distributed ordering scheme in order management system
An order management system includes an ordering terminal, a checkout terminal, a server, and a kitchen terminal. The ordering terminal generates and transmits order data, a seat leaving command and a seat ID, in response to user inputs. The checkout terminal is configured to process payment for the order. The server is configured to: generate an order file including an order ID based on the order data, transmit checkout data including data in the order file to the checkout terminal, in response to the order ID from the checkout terminal, transmit seat data for seat selection, in response to payment completion data associated with the order ID, transmit a cook start command in response to assignment of one or more vacant seats associated with the order ID, and update the seat data based on the seat leaving command and the seat ID received from the ordering terminal. |
| US10970798B2 |
Aircraft dining systems and methods
An aircraft dining system and method are configured to allow a passenger for a scheduled flight of an aircraft to order one or more items from restaurants within an airport. The aircraft dining system includes an order fulfiller including an order fulfillment control unit that is configured to receive an order for an item from a restaurant within the airport from the passenger for the scheduled flight so that the item is delivered to the aircraft or an area proximate to the aircraft prior to the aircraft departing the airport. In at least one embodiment, an ordering device includes an ordering control unit that is configured to allow the passenger to submit the order. |