| Document | Document Title |
|---|---|
| US10958848B2 |
Electronic apparatus
A digital camera includes an image sensor that can receive a light beam from a subject in a first region (one block) and a second region (another block) and capture images in the first region and second region on different conditions and a control unit that controls image capture by applying multiple image capture conditions to a first process at least in the first region. |
| US10958847B2 |
Imaging device, image processing method, and image processing system
Provided is an imaging device, an image processing method, and an image processing system which obtains a sensing image and a viewing image by one imaging element. The imaging device includes a control unit that controls irradiation with invisible light, an imaging element that includes a first pixel that is capable of detecting the invisible light, and a second pixel that is capable of detecting visible light. The imaging device further includes an image generation unit that generates a first image including the invisible light component and a second image including a visible light component on the basis of a first pixel signal transmitted from the first pixel and a second pixel signal transmitted from the second pixel. |
| US10958846B2 |
Method, device and system for configuration of a sensor on a moving object
A method for configuring a sensor, which is adapted to be installed on a moving object, includes obtaining localization information of the sensor from a localization device, obtaining characteristic information and localization information of at least one element from a digital map, and choosing one or more elements of the at least one element in the digital map. The method also includes configuring the sensor according to the characteristic information and/or the localization information of the one or more chosen elements. |
| US10958845B2 |
Camera with rotatable sensor
Examples are presented herein that relate to rotation of a sensor assembly relative to a housing of a camera system. One example provides a camera system coupled to a display device, the camera system comprising a housing, a sensor assembly arranged within the housing and rotatable with respect to the housing, the sensor assembly comprising an image sensor configured to obtain image data for display by the display device, and a manual rotation mechanism coupled to the sensor assembly, the manual rotation mechanism configured to be manually actuated from outside the housing to rotate the sensor assembly with respect to the housing. |
| US10958844B2 |
Control apparatus and control method
A control apparatus for an imaging apparatus having a drive unit for tilting of an imaging element includes a tilt angle setting unit configured to set a tilt angle, and a control unit configured to perform control so as not to change a parameter that affects the tilt angle during tilt angle setting. |
| US10958842B2 |
Method of displaying images in a multi-dimensional mode based on personalized topics
A method and an electronic device for displaying images in a multi-dimensional mode based on personalized topics are provided. The method includes generating a plurality of personalized topics based on a plurality of images stored in the electronic device across a predetermined time period, and displaying the plurality of personalized topics along a timeline. |
| US10958841B2 |
Integrated image sensor and display pixel
In one example, a display includes an array of display pixels. Each display pixel includes at least one light-emitting diode. At least one of the display pixels includes an image sensor. |
| US10958840B2 |
Systems and methods for stabilizing videos
Visual content is captured by an image capture device during a capture duration. The image capture devices experiences change in position during the capture duration. The trajectory of the image capture device is smoothed based on a look ahead of the trajectory. A punchout of the visual content is determined based on the smoothed trajectory. The punchout of the visual content is used to generate stabilized visual content. |
| US10958839B2 |
Lighting device and imaging device
An object of the present invention is to provide a lighting device capable of properly performing a bounce motion and photography in the event of an unexpected motion. The lighting device of the present invention is a lighting device including a control unit that provides an instruction of an auto-bounce motion. When detecting an auto-bounce motion in S303, the control unit releases the brake of a motor for driving a light-emitting part and performs auto-bounce control in S304. When detecting that the bounce angle of the light-emitting part in the auto-bounce motion reaches a target position and the motor enters a stop period in S303, the control unit automatically switches to the application of an intermittently repeated regenerative brake to the motor. This can suppress a movement of the light-emitting part even in an accidental motion and perform a proper bounce motion with an easy manual operation. |
| US10958838B2 |
Method and device for electronic image stabilization of a captured image
In a method of electronic image stabilization, a processor buffers image data into a memory buffer, the image data being obtained by the processor from an image sensor disposed in an electronic device. The processor obtains motion data from a motion sensor disposed in the electronic device, wherein the motion data corresponds with a time of capture of the image data. The processor analyzes the motion data to determine a stabilization correction to apply to the image data. The processor applies the determined stabilization correction to the image data to achieve stabilized image data. The determined stabilization correction is applied, and the stabilized image data is achieved, by the processor without requiring a transfer of the image data from the memory buffer to a graphics processing unit. The stabilized image data is output. |
| US10958831B2 |
Image processing apparatus and control method of the same
An image that is based on an image with a first resolution is displayed on a selection screen, a display unit is caused to display a confirmation screen for confirming a processing target image selected on the selection screen, control is performed to generate an image with a second resolution higher than the first resolution and to display the generated image on the confirmation screen, and control is performed to extract an image having a first format and corresponding to the processing target image from a first image file, and to record the extracted image and the image with the second resolution, as a second image file. |
| US10958827B2 |
Image mark sensing systems and methods
Systems and methods use a digital microform imaging apparatus for sensing an image mark on the microform containing the image of a document. The use of an area sensor with an adjustable region of interest can be used to improve the detection speed of image marks as a roll of microform is being transported. |
| US10958824B2 |
Imaging apparatus and image processing method
An imaging apparatus and an image processing method capable of increasing correction accuracy of a phase difference detection pixel even in a case where the phase difference detection pixel is densely arranged in an imaging element in order to secure AF performance are provided. An imaging element includes normal pixels of RGB and first and second phase difference pixels of which opening portions are adjacently arranged to face each other in a horizontal direction and in which a G filter is arranged. A pixel value addition unit (64) generates an addition pixel corresponding to a virtual G pixel at a pixel position between the first and second phase difference pixels by adding pixel values of the pair of the first and second phase difference pixels. In a case where the first or second phase difference pixel is set as an in-focus pixel that is an interpolation target, an average value interpolation unit (62) uses the normal pixels surrounding a pixel position of the in-focus pixel and the addition pixel in a case of performing an interpolation operation on a pixel value at the pixel position of the in-focus pixel. |
| US10958822B2 |
Autofocus initialization based on target detection
A method for moving an optical device of an imaging device includes one or more depth sensors acquiring one or more depth measurements within a predefined spatial coordinate system. Each of the one or more depth measurements indicates a distance from the imaging device to an object within the predefined spatial coordinate system. The method further includes one or more orientation sensors determining orientation information of the imaging device within the predefined spatial coordinate system, estimating an object distance between the imaging device and the object based on the one or more depth measurements and the orientation information, and moving the optical device from a first position to a second position according to the object distance and a focal length of the optical device. |
| US10958815B1 |
Folded flex circuit board for camera ESD protection
Various embodiments disclosed herein include a folded flex circuit board that may be used in a camera module. In some embodiments, the folded flex circuit board may include a base portion and one or more tab portions that extend from the base portion. In various examples, the folded flex circuit board may be folded such that the tab portion(s) form at least a portion of one or more sides of a camera module. According to some embodiments, the folded flex circuit board may be configured to provide electrostatic discharge (ESD) protection to the camera module. |
| US10958812B2 |
Optical lens support
An image capture device in accordance with the present disclosure includes a cover coupled to a mount to surround a stereoscopic-camera unit. The stereoscopic-camera unit includes a circuit board coupled to a frame having a top brace, a bottom brace, and lens holders. The top brace and bottom brace each are formed a similar material as the circuit board (e.g., a FR4 material), such that the top and bottom braces share a similar coefficient of expansion with the circuit board. |
| US10958808B2 |
Image forming apparatus controlling color reproduction range and tone reproducibility
An image forming includes a dither processing unit that applies a dither matrix to an image; an exposure unit that exposes a photosensitive drum to form an electrostatic latent image based on the image to which the dither matrix has been applied; a development unit that develops, using a developing material on a developing roller, the formed electrostatic latent image; and a control unit that, based on a print setting change instruction by a user, increases a circumferential speed of the developing roller relative to the circumferential speed of the photosensitive drum and decreases a screen ruling of the dither matrix to be applied by the dither processing unit. |
| US10958807B1 |
Methods and arrangements for configuring retail scanning systems
The present technology relates to image signal processing. One aspect of the present technology involves analyzing reference imagery gathered by a camera system to determine which parts of an image frame offer high probabilities of—relative to other image parts—containing decodable watermark data. Another aspect of the present technology whittles-down such determined image frame parts based on detected content (e.g., a cereal box) vs expected background within such determined image frame parts. |
| US10958799B2 |
Image forming apparatus and method for controlling the same
An image forming apparatus includes a storage medium, an operation panel, and a controller. The storage medium stores therein a paper-type profile which includes paper information and control information. When an operation to make the paper-type profile belong to a medium family has been performed, the controller attaches, to the paper-type profile, information indicating the medium family to which the paper-type profile belongs. When an operation to make the paper-type profile belong to a device family has been performed, the controller attaches, to the paper-type profile, information indicating the device family to which the selected paper-type profile belongs. |
| US10958798B2 |
Image forming apparatus, display control method, and recording medium
An image forming apparatus includes an image forming device; and circuitry to receive an instruction to print an image based on image data according to print settings, and based on a determination that the print settings indicate to print the image on a recording sheet having a second size larger than a first size of the image, control a display to display a preview image that reflects a printed image of the image data, the preview image including a margin at least at one side of the printed image, the margin having a size determined based on the second size of the recording sheet. |
| US10958797B2 |
Image forming apparatus for forming image on recording paper
An image forming device includes: a display device; a storage device that stores finish icons indicating respective finished states of a plurality of types of printed material, function icons indicating respective functions of setting finished states of the printed materials, and a correspondence relationship between the finish icon and the function icon indicating the function of setting the finished state of the printed material indicated by the finish icon; and a control device that includes a processor and, by the processor executing a control program, functions as a controller. The controller reads out the finish icon from the storage device, causes the display device to display, on a screen thereof, the finish icon, reads out the function icon associated with the finish icon from the storage device based on the correspondence relationship, and causes the display device to display the function icon in association with the finish icon. |
| US10958795B2 |
Systems and methods for monitoring data and bandwidth usage
Access to a communications network may be provided via a data provider that may charge for access. In some cases, the access fee may be related to the amount of network resources consumed (e.g., amount of data downloaded or bandwidth used). In some cases, a user may have access to a particular amount of data provider resources and be required to pay an additional fee for using resources in excess of the particular amount. To assist the user in managing his data resource consumption, a resource utilization component may provide different alerts and notices informing the user of current consumption, expected future consumption, and recommendations for reducing data provider resources consumed (e.g., stopping particular processes or data provider requests, such as downloading media). If several electronic devices in a network are connected to the same data provider resources, a network component may manage the data provider resource use among the several electronic devices (e.g., allow only particular users or devices access). |
| US10958793B2 |
Devices, systems and methods for communications that include social media clients
Devices, systems and methods for communications that include social media clients are provided. In particular, a server operates a virtual client for communicating with clients of a social media server. The server receives a call request associated with a directory number of a call server, the call request to initiate a call associated with the directory number and a given client of the social media server. The server conducts the call by controlling: the virtual client to communicate with the given client, via the social media server; and the virtual client to communicate with a communication device associated with the directory number, via the call server. The server may also facilitate exchange of status updates between a given client of the social media server and the call server. The server may also facilitate calls between respective clients of different social media servers. |
| US10958792B2 |
Performing contextual analysis of incoming telephone calls and suggesting forwarding parties
A computer-implemented method includes: receiving, by a computing device, an incoming telephone call from a caller; identifying, by the computing device, a telephone number associated with the telephone call; obtaining, by the computing device, contextual data based on the telephone number, predicting, by the computing device, one or more reasons for the telephone call based on the contextual data; and displaying, by the computing device, the one or more reasons for the telephone call. |
| US10958789B2 |
Techniques for case allocation
Techniques for case allocation are disclosed. In one particular embodiment, the techniques may be realized as a method for case allocation comprising receiving, by at least one computer processor, at least one case allocation allocated using a first pairing strategy, and then reassigning, by the at least one computer processor, the at least one case allocation using behavioral pairing. |
| US10958784B1 |
Performing a custom action during call screening based on a purpose of a voice call
A user device may output an indication of an incoming call from a calling device. The user device may receive a request to screen the incoming call. The user device may analyze a transcription of voice input, received from the calling device, for one or more keywords related to a request for funds. The user device may output one or more input options, which permit a user of the user device to respond to the request for funds, including an input option to transfer funds from a first account associated with the user device to a second account associated with the calling device. The user device may detect a user interaction with the input option to transfer funds from the first account to the second account. The user device may transmit a request that causes funds to be transferred from the first account to the second account. |
| US10958781B2 |
Providing audio content to a device
The present disclosure describes receiving a trigger operation indication that content has been selected by a user device, and determining whether the content offers a recurring audio content data. The operation may also include retrieving a first audio content and transmitting the first audio content to the user device. |
| US10958780B1 |
Decentralized automatic phone fraud risk management
Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for phone fraud prevention. One of the methods includes adding a first identifier of a first phone event of a first user into a blockchain managed by one or more devices on a decentralized network. The first identifier of the first phone event is classified into a list of phone fraud identifiers. A second identifier of a second phone event involving a second user is received. The second identifier is compared with the list of phone fraud identifiers that includes the first identifier. In a case where the second identifier matches a phone fraud identifier in the list of phone fraud identifiers, the first user is notified that the second phone event involves a risk of phone fraud. |
| US10958778B1 |
Contact system for a computing platform
The present invention comprises system and method for configuring and displaying contact information in an easy-to-use fashion on a computing platform. The system includes the ability to select a contact for a phone call or text message with minimal user interaction. |
| US10958777B1 |
Methods and systems for stowed state verification in an electronic device
An electronic device includes one or more processors. When a first sensor delivers a first signal to the one or more processors indicating that the electronic device is in a stowed state, and a second sensor delivers a second signal to the one or more processors indicating that the electronic device is in a held state the one or more processors query the third sensor for a third signal indicating whether the electronic device is in the stowed state. The one or more processors perform a control operation when the third signal fails to indicate the electronic device is in the stowed state. The one or more processors omit performance of the control operation when the third signal indicates the electronic device is in the stowed state. |
| US10958776B2 |
Method and apparatus for interworking between electronic devices
An electronic device comprising: a memory; a communication unit for exchanging communications with a wearable device and an external device; and at least one processor that is operatively coupled to the memory, configured to: detect an event that is associated with a connection with the external device; identify a function that is associated with the external device in response to the event; and transmit to the wearable device an instruction for executing the function, wherein the instruction is transmitted via the communications unit. |
| US10958772B2 |
Method and apparatus for providing event of portable device having flexible display unit
A portable terminal is provided for operation in a first mode in which information is provided on a first curved surface area or a second mode in which information is provided on a second curved surface area, and controlling the display to provide, in response to an occurrence of an event while in the first mode, information related to the event on the first curved surface area, and provide, in response to the occurrence of the event while in the second mode, information related to the event on the second curved surface area. |
| US10958768B1 |
System providing faster and more efficient data communication
A system designed for increasing network communication speed for users, while lowering network congestion for content owners and ISPs. The system employs network elements including an acceleration server, clients, agents, and peers, where communication requests generated by applications are intercepted by the client on the same machine. The IP address of the server in the communication request is transmitted to the acceleration server, which provides a list of agents to use for this IP address. The communication request is sent to the agents. One or more of the agents respond with a list of peers that have previously seen some or all of the content which is the response to this request (after checking whether this data is still valid). The client then downloads the data from these peers in parts and in parallel, thereby speeding up the Web transfer, releasing congestion from the Web by fetching the information from multiple sources, and relieving traffic from Web servers by offloading the data transfers from them to nearby peers. |
| US10958762B2 |
Method for communicating a status of presence of a group of users in a virtual communication space provided by a communication server on a communication network
A method of communicating a presence state for a group of users having user terminals relating to their presence in a virtual communication space provided by a communication server on a communication network. The virtual space provides a plurality of distinct communication modes referred to as “activities” that can be shared by all of the users of said group. The method includes associating each activity of the virtual space with a graphics icon representing the activity, the icon being for displaying via a graphics interface implemented by any activity sharing client application that is installed in each user terminal. A presence state is determined for each user of the group. For each of the activities, a graphical representation for the associated icon is determined as a function of the presence state for the users relative to the activity, enabling visual identification of user(s) participating in the activity. |
| US10958760B2 |
Data processing system using pre-emptive downloading
A data processing system includes a processor and a local storage device connected to the processor. The data processing system is operated to identify one or more downloads for downloading to the local storage device. The system determines the amount of available space within the local storage device, selects a download from the identified download(s) that is smaller than the amount of available space within the local storage device, and downloads the selected download to the data processing system. The selected download is then stored in the local storage device, whilst not marking the space occupied by the selected download as being used. |
| US10958758B1 |
Using data analytics for consumer-focused autonomous data delivery in telecommunications networks
The present disclosure uses data analytics for consumer focused autonomous data delivery in a 5G (fifth generation cellular network technology) telecommunications network. Data usage information is received at a control system, and the data usage information includes information about data downloaded by users at a venue. The data usage information includes content information about the data downloaded, the data being downloaded using a 5G telecommunications network. The data usage information is analyzed to determine content delivery using a service orchestration layer of a 5G telecommunications network in concert with smart channel monitoring tools of compatible platforms. A predictive analysis is generated using the analysis of the data usage information. A data action is initiated pertaining to the content for downloading the content, based on the predictive analysis, before demand for the downloading of the content, to provide faster service to end users at the venue. |
| US10958757B2 |
Microservices request flow control synchronization
A set of requests for a shared dependent service are generated by a first cmicroservice of a set of collaborating microservices. A microservice request data set is received from request flow controller modules of other microservices of the set of collaborating microservices. The microservice request data set includes information indicative of requests to the shared dependent service made by the other collaborating microservices. A request flow controller module of the first microservice of the set of collaborating microservices synchronizes between the requests generated by the first microservice, and the requests indicated in the microservice request data set. The synchronized requests from the set of collaborating microservices to the shared dependent service are maintained according to processing capabilities of the shared dependent service. |
| US10958754B2 |
Method, apparatus, medium and system for caching data
According to an aspect, a method comprises maintaining, by a cache control unit in a first packet data network, white and black lists of data servers in a second packet data network that are allowed or unable to use a cache server in the first packet data network, respectively; monitoring data traffic to and from data servers in the second packet data network over an interface between the first and second packet data network; comparing the candidate data servers to the data servers in the white and black lists; and in response to a candidate data server being in neither list, performing the following: causing sending a cache request to the candidate data server and in response to receiving an acknowledgement to the cache request within a pre-defined time, adding the candidate data server to the white list, otherwise adding the candidate data server to the black list. |
| US10958751B2 |
Method for verifying a user association, intercepting module and network node element
Method for verifying an association between a user and a group of users sharing a common subscription, comprising intercepting a message between a user and a service provider; adapting the message with information to include a guarantee to the service provider that the message is sent from a location allowed by the common subscription. |
| US10958749B2 |
Method and device for pushing application message
A label of a message to be sent is detected as a message label for a non-real-time transmission. For a user device group associated with the message to be sent and based on a timely-response rate and a correction scheme, an optimal time period to respond to a message for each user device in the user device group is dynamically determined. Based on the optimal time period for each user device to respond to a message, the message to be sent is separately sent to a corresponding user device in the user device group. |
| US10958747B2 |
Digital component transmission
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for adjusting an eligibility value for transmitting a digital component. In one aspect, a computing system includes a server for identifying opportunities to transmit digital components to client devices. The server determines a first probability of a given outcome occurring following user interaction with the digital component when the digital component is transmitted to the client device. The server determines a second probability of the given outcome occurring if the digital component is not transmitted to the client device. The server generates an outcome incrementality factor for the digital component, including determining a ratio of the first probability relative to the second probability, and triggers adjustment of an eligibility value based on the outcome incrementality factor. The server then controls transmission of the digital component to the client device using the adjusted eligibility value. |
| US10958746B2 |
Application server-based social presence publishing
The use of application servers to publish the social presence information of users to a presence server of the wireless carrier network may reduce signaling and communication traffic between user devices and the wireless carrier network. The use of application servers may also provide social presence information publishing capabilities when user devices of users do not have such publishing capabilities or are otherwise unable to do so. An application server may receive one or more user-defined social presence settings of a user from an access portal provided by the application server. Social presence information is generated for the user based on the one or more user-defined social presence settings at the application server. The social presence information for the user is sent from the application server to a presence server of a wireless carrier network. |
| US10958744B2 |
Identifying and managing redundant digital content transfers
A computer system receives digital content for communication to a user. Digital fingerprints are calculated from the digital content. The fingerprints are compared to identify redundant digital content. Digital identifications associated with the digital fingerprints are communicated to a user device to determine whether the digital content exists in local storage. |
| US10958737B2 |
Systems and methods for distributing content
A system for multimedia content delivery includes one or more processors; and a storage medium storing instructions. When executed, the instructions may configure the one or more processors to perform operations including: delivering to a set of client devices a manifest including fake segment URLs; receiving, from a client device, a segment request including a client ID and a requested URL. The method may also include selecting content for the at least one of the client devices based on the client ID when determining the requested URL is unavailable; redirecting the segment request to a content address associated with the selected content; and providing the selected content to the at least one of the client devices. |
| US10958736B2 |
Information processing apparatus, method of controlling the information processing apparatus, and storage medium
An information processing apparatus comprises a plurality of network interface that are connectable to respective networks differing from each other; at least one memory that stores a set of instructions; and at least one processor that executes the instructions, the instructions, when executed, causing the information processing apparatus to perform operations comprising: setting, based on a user input, a network interface used for a given function, and a communication parameter of each network interface for a case that the each network interface is used for the given function; and executing the given function by using the set network interface by the setting. |
| US10958725B2 |
Systems and methods for distributing partial data to subnetworks
Computerized approaches for replicating a portion of a data set to a local repository associated with a subnetwork are disclosed. In one implementation, a method for a device associated with a subnetwork may include obtaining a portion of a data set from a central repository. The data set may be associated with one or more subnetworks, and the portion of the data set may be associated with the subnetwork. The method may further include obtaining a request for data originating from a node in the subnetwork. The requested data may include the portion of the data set, and data generated based on the portion of the data set, and the request may be destined for the central repository. The method may also include determining whether the central repository is unavailable to provide the requested data, and providing the requested data to the node if the central repository is unavailable. |
| US10958723B2 |
Cloud-end data multicast method and system, and computer device
A cloud-end data multicast method includes: obtaining a multicast packet, the multicast packet carrying a tenant identifier, a destination address, and a source address; and searching for a multicast group according to the tenant identifier and the destination address. The multicast group includes multicast members. The method also includes obtaining routes corresponding to the multicast members; generating a routing tree according to the routes corresponding to multicast members; and obtaining member addresses corresponding to the multicast members. The method also includes obtaining an address list containing addresses of target members that are identified to receive the multicast packet by performing address filtering according to the source address and the member addresses; encapsulating the multicast packet; and delivering the encapsulated multicast packet to the target members according to the address list and the routing tree. |
| US10958716B2 |
Distributed process management system, distributed process management method for suppressing number of messages between computers, and information processing apparatus
A distributed process management system includes an edge server configured to start and execute a process corresponding to contents of data when the data sent from a device is received; and a center server configured to manage a state of the process, wherein the edge server is configured to notify the center server of a start time and an amount of processing of the process each time the process is started, and the center server is configured to estimate an end time of the process based on the start time and the amount of processing and update the end time of the process, each time the start time and the amount of processing are notified. |
| US10958715B2 |
Relay apparatus, client apparatus, and computer-readable medium
A relay apparatus includes a storage, request data reception and transmission units, a mode data reception unit, a specified condition conversion unit, a content identifier reception unit, a generation unit, and a display data transmission unit. The storage stores a service identifier, access destination information, and a conversion routine for the format of a specified condition specifying content, for each of storage services. The request data reception unit receives a service identifier and a specified condition from a client apparatus. The mode data reception unit receives mode data specifying a client apparatus display format. The specified condition conversion unit converts the specified condition into a server format, which is transmitted by the request data transmission unit using access destination information. The content identifier reception unit receives content identifiers from the server, for which the generation unit generates display data. The display data transmission unit transmits it to the client apparatus. |
| US10958709B2 |
Method for transferring a file between a control device of a motor vehicle and a server device outside the vehicle, control device and motor vehicle
The present application relates to a method for transferring a file between a control device in a motor vehicle and a vehicle-external server device, the control device in the motor vehicle being connected to a communication device via a data network, which for the transfer of the file provides a radio link to the server device and which caches data of the file during the transfer. The invention provides that the file is divided into a plurality of file segments and a segment identifier is determined for each file segment, the segment identifiers are transferred via the radio link before the file is transferred, the file segments are individually requested independently of each other by a respective request command via the radio link, the request command including the segment identifier of the requested file segment, and then each requested file segment being transferred independently of the remaining file segments. |
| US10958708B2 |
Crowdsourcing big data transfer
A method for transporting data from a source location to a destination location includes receiving the data from at least one sender at the source location, the sender specifying at least one recipient at the destination location; splitting the data into a plurality of portions; and finding one or more couriers who will travel from the source location to the destination location. The method also includes: while at least a given courier is at the source location, sending at least one of the plurality of portions to a mobile device of at least the given courier; once the given courier travels to the destination location, receiving the at least one of the portions from the mobile device of the given courier; and once the plurality of portions of the data have been received at the destination location, sending the data set to the at least one recipient. |
| US10958707B2 |
Directional touch remote
The present system and method is particularly useful for remotely controlling a device having one or more menus via a remote touch interface having at least an unstructured primary input area. A user can provide inputs to a touch interface without needing to view the interface and yet still achieve the desired response from the remotely controlled device. The primary input area of the touch interface may or may not have a background display, such as on a touch screen, but the primary input area of the touch interface should be unstructured and should not have independently selectable items, buttons, icons or anything of the like. Since the touch interface is unstructured, the user does not have to identify any selectable buttons. Instead the user can input a gesture into the interface and watch the remotely controlled device respond. The system does not provide any other visual confirmation. |
| US10958702B1 |
Timeout optimization for streaming video
Systems, methods, and computer-readable media are disclosed for determining and applying a timeout for streaming video. Processing circuitry of a device may request video fragments to be downloaded and played, and if a requested fragment is not downloaded entirely before expiration of a timeout, the device may adjust the timeout to allow the download to complete. A timeout may be set based on available bandwidth and a size of a fragment requested for download, and the timeout may be extended based on network and/or device conditions. |
| US10958700B1 |
Methods, systems, and apparatuses for improved content delivery
Methods, systems, and apparatuses for improved content delivery are described herein. During delivery of content to one or more user devices of a content distribution network (CDN), a content session may be created for each user device. During each content session, each user device may send one or more upstream communications, such as heartbeat signals and bitrate requests, to the CDN. A monitoring module of the CDN may aggregate the upstream communications into session data. The monitoring module may use the session data to determine an impairment associated with content delivery to the one or more user devices. |
| US10958697B2 |
Approach to live multi-camera streaming of events with hand-held cameras
A system provides access to previously unassociated cameras that are concurrently at different specific locations at a single event, sending the real-time video and audio stream of said cameras to a central processing entity, transcoding and serving the real-time content to consumers in a way that associates the content as different camera angles of the same event, along with additional data from each camera owner such as twitter feeds. Also disclosed is a system for providing a user, via a client device, the ability to choose a desired feed for viewing the event and the ability to change the selected feed based a number of user-selected criteria. |
| US10958696B2 |
Device-resident media files
A device is configured for communications over an IP network. The device comprises a user interface, a memory interface for accessing information media files stored in a memory in the device or associated with the device, and a media file streamer. The device is configured to receive an instruction from the IP network during establishment of a call, during a call, or at termination of a call, the instruction identifying one or more of the media files. The device is configured to access the identified media file from the memory via the memory interface and to stream the identified media file to convey the information in the media file via the user interface. |
| US10958695B2 |
Methods, systems, and media for recommending content based on network conditions
In some embodiments, a method for recommending content based on network conditions comprises: receiving, from a first user device, a request to present media content recommendations on the first user device; in response to receiving the request, determining information indicating a user context associated with the first user device and network connectivity information associated with a connection status of the first user device over a communications network; identifying a group of media content items to recommend based on the user context and the network connectivity information; and causing recommendations for the group of media content items to be presented on the first user device. |
| US10958693B2 |
Methods and apparatuses for associating user identification information to chatbot capable frameworks
Embodiments herein relate to methods, a user equipment and a chatbot agent for associating/connection a user identification information to a chatbot capable framework user-specific identify. The method comprises: establishing a session with the chatbot agent over a chatbot capable framework, receiving a request to connect or associate the user identification information to the framework user-specific identity; providing the user identification information to the chatbot agent; receiving a message including information on the operator of the chatbot agent and further including the user identification information; and sending, to the chatbot agent, a confirmation message confirming that the user identification information be associated to the framework user-specific identity and further confirming that the user identification information be stored in a database of the operator. |
| US10958692B2 |
Security capability negotiation method, system, and equipment
A security capability negotiation method is provided that is applicable to perform security capability negotiation during a mobile network handover. Moreover, a security capability negotiation system is also provided. Consistent with the provided system and method, it may be unnecessary for the MME to know the security capability of the corresponding eNB in a certain manner during a handover from a 2G/3G network to an LTE network. Meanwhile, during the handover from the LTE network to the 3G network, the SGSN does not need to introduce new requirements. |
| US10958690B1 |
Security appliance to monitor networked computing environment
A security appliance is used to evaluate a software defined infrastructure. The security appliance includes a data ingestion and query engine. The data ingestion and query engine are configured to retrieve configuration and operational information associated with the software defined infrastructure, extract selective information from the retrieved configuration and operational information, and store extracted selective information in a plurality of data store. A policy compliance engine is configured to evaluate selectively stored information for compliance to a policy and generate a report based on the evaluation. The configuration and operational information include information related to asset configuration, audit event indicative of an initiation of an infrastructure related activity for the software defined infrastructure and network communication associated with the software defined infrastructure. |
| US10958688B2 |
Decentralized multi-channel discovery system through a plurality of data structures
Described herein are technologies related to an implementation of a decentralized discovery system that utilizes a plurality of fuse-nodes to facilitate delivery of content specific data to a user. The plurality of fuse-nodes is a proprietary owned database (or modules) that include relationship links to another fuse-node (s), and/or a particular channel, media, and contents, which further include social network-friends and social network activities of the social network-friend, etc. |
| US10958686B2 |
Domain specific language for threat-actor deception
The present disclosure describes enticing a threat-actor to execute an attack execution operation. According to one aspect of the subject matter described in this disclosure, a method for generating a domain-specific language (DSL) file is disclosed. The method may comprise determining, a framework based on an attack repository, determining a first primitive based on the framework, and determining a second primitive based on the framework. In one implementation, the first primitive and the second primitive are fundamental structures or constructs within a DSL. The method further comprises combining the first primitive and the second primitive into a DSL file. In one implementation, the DSL file is executed to create a computing environment that entices a first attacker to execute an attack execution operation within a given domain. |
| US10958685B2 |
Generation of honeypot data
Data is received that includes a plurality of fields. These fields are modified using at least one differential privacy algorithm to result in fake data. This fake data is subsequently used to seed and enable a honeypot so that access to such honeypot and fake data can be monitored and/or logged. Related apparatus, systems, techniques and articles are also described. |
| US10958678B2 |
Identity based behavior measurement architecture
A method includes generating a behavioral state for an endpoint device based on actor identities and corresponding subject identities for a plurality of operations wherein for each operation, a respective actor represented by a respective actor identity performs the operation upon a respective subject represented by a respective subject identity. Performance of a later operation by an actor with an actor identity upon a subject with a subject identity is recorded and the actor identity and the subject identity are used to determine that the performance of the later operation does not match the behavioral state and indicates a security risk. |
| US10958675B2 |
Method for the automated creation of rules for a rule-based anomaly recognition in a data stream
A method for creating rules for recognizing anomalies in a data stream of data packets. The method includes: providing a reference time signal having successive reference points in time; for at least two data portions from one or multiple data packets determined by a selected data packet type in a data stream section, ascertaining a time series of successive values of the relevant data portion, the values of the time series corresponding to the values of the relevant data portion or being a function of these values, the values of the relevant data portion each being assigned to a respective reference point in time of the respective reference points in time; carrying out a correlation method in order to ascertain, in each case, one correlation value for at least two different time series; creating a rule for the rule-based anomaly recognition method as a function of the ascertained correlation values. |
| US10958673B1 |
Multi-factor authentication augmented workflow
A system and method for a machine learning-based score driven automated verification of a target event includes: receiving a threat verification request; extracting a corpus of threat features; predicting the machine learning-based threat score; evaluating the machine learning-based threat score against distinct stages of an automated disposal decisioning workflow; computing the activity disposal decision, wherein the activity disposal decision informs an action to allow or to disallow the target online activity; receiving the machine learning-based threat score as input into an automated verification workflow; computing whether an automated verification of the target online activity is required or not based on an evaluation of the machine learning-based threat score against distinct verification decisioning criteria of the automated verification workflow; automatically executing the automated verification of the target online activity and exposing results of the automated verification to the subscriber for allowing or for disallowing the target online activity. |
| US10958671B2 |
Securing services in a networked computing environment
A computer-implemented method includes: detecting, by a user device, an event that indicates a potential security compromise of the user device; determining, by the user device, a service accessible on the user device; sending, by the user device, a breach notification to a service provider corresponding to the service accessible on the user device; receiving, by the user device, a security profile from the service provider; and restricting, by the user device, access to the service provider by a client of the service provider on the user device until the security profile is satisfied by a user completing a security challenge defined in the security profile. |
| US10958670B2 |
Processing system for providing console access to a cyber range virtual environment
Aspects of the disclosure relate to processing systems that generate a virtual air gap to facilitate improved techniques for establishing console access to a cyber range virtual environment. The computing platform may receive a request to generate a virtual air gap to facilitate brokering of a connection between a secure console host platform and a cyber range host platform. The computing platform may generate the virtual air gap, which may include a built-in kill switch. The computing platform may implement the virtual air gap, which may be configured to receive requests to establish a connection between the secure console host platform and the cyber range host platform and to grant the secure console host platform access to a broker. The broker may establish the connection, and the computing platform may terminate the connection in response to activation of the built-in kill switch. |
| US10958667B1 |
Determining computing system incidents using node graphs
Systems and methods for performing graph-based analysis of computing system threats and incidents, and determining response and/or mitigation actions for the threats and incidents, are described. In some embodiments, the systems and methods generate node graphs of computing system threat artifacts, and perform actions to identify recommended resolutions to the threats, based on information derived from the generated node graphs. |
| US10958663B2 |
Customized view of restricted information recorded into a blockchain
Systems, methods, and software are disclosed herein to generate a customized view of a blockchain transaction. A blockchain of block entries requested by a plurality of users from user devices is maintained in a distributed network of nodes. The block entries each comprise a plurality of data portions that are each associated with an access level. A request to view one or more data portions of a block entry is received which includes an access code associated with at least one access level. The access code in the request is evaluated with the blockchain of block entries to identify one or more data portions associated with the access level. A customized view of the block entry is generated which includes the one or more data portions associated with the access level. |
| US10958661B2 |
Multi-layer authentication system with selective level access control
Systems for providing multi-layer authentication are provided. In some examples, a system may receive data associated with a signal detected by a computing device. The signal may be emitted from a smart processing device. The received signal data may be compared to pre-stored signal data to determine whether a match exists. If not, an instruction disabling functionality of the smart processing device may be generated and transmitted to the smart processing device. If so, an instruction enabling functionality of the smart processing device may be generated and transmitted. The system may generate a request for next layer authentication data. The request may be transmitted to one or more computing devices and next layer authentication response data may be received. The next layer authentication response data may be compared to pre-stored next layer authentication data to determine whether a match exists. If not, an instruction disabling functionality of the smart processing device may be generated and transmitted. If so, an instruction enabling additional functionality of the smart processing device may be generated and transmitted. |
| US10958660B2 |
Information processing apparatus and access control method
An information processing apparatus includes a processor that executes a process including calculating, for each of a plurality of registered users from which feature values have been obtained in advance, an index value indicating a probability of an authentication target being that registered user based on a matching degree between a feature value extracted from authentication information obtained from the authentication target and a feature value of that registered user, setting a synthesized access right by synthesizing, based on the index value, an access right of a certain one of the plurality of users to a plurality of resources and an access right of a user different from the certain registered user from among the plurality of registered users to the plurality of resources, and permitting the authentication target an access to a resource to which an access is permitted in the synthesized access right. |
| US10958650B2 |
Data processing method, system, and apparatus, storage medium, and device
This application discloses a data processing method, system, and apparatus, a storage medium, and a device, and belongs to the field of database technologies. The method includes receiving, a trigger request; triggering, according to the trigger request, the first cloud encryptor to store a root key seed, an operating policy, a data key seed, and a data key identifier, and triggering the database proxy to store an encryption data dictionary, the operating policy indicating an operation policy of the first cloud encryptor. The method further includes receiving a data processing request from the client; sending first data that the data processing request requests to process and the data key identifier in the encryption data dictionary to the first cloud encryptor. The method further includes implementing the operating policy, processing the first data, and responding to the data processing request by using the second data. |
| US10958649B2 |
Systems and methods for internet-wide monitoring and protection of user credentials
Among other things, this document describes systems, methods, and apparatus for monitoring and protecting a user credential issued by an organization when that credential is used outside that organization's network security perimeter. For example, a reverse proxy server (RPS) receives a client request directed to a content provider's site. The RPS initiates a process that involves parsing the request message and extracting a user credential. The RPS locates a credential policy from the credential owner based on the user credential. The RPS can issue an API request to a credential service that is authoritative for the credential. That credential service may return a directive to the RPS specifying how to handle the client request message. Preferably, the operation is transparent to the content provider whose site was the target of the client's request message. Activity records can be presented in visualizations that enhance security analysts' tactical comprehension at a glance. |
| US10958646B2 |
Biometric authentication with body communication network
A method of authenticating a health measurement taken from a medical measurement device may include establishing a network connection between a computing device and a medical measurement device. The network connection may be established via contact of a user with electrodes of the computing device and contact of the user with electrodes of the medical measurement device. While user contact is maintained with the electrodes of the computing device, the electrodes of the medical measurement device, and a biometric sensor of the computing device health measurement data of the user may be received at the computing device from the medical measurement device. Also while contact is maintained, the user may be authenticated using a measurement of the biometric sensor of the computing device. The health measurement data may be signed based on the authenticating. |
| US10958642B2 |
Dynamic biometric authentication based on distributed ledger data
The disclosed exemplary embodiments include computer-implemented devices, apparatuses, and processes that, among other things, perform dynamic biometric authentication based on distributed ledger data. For example, a device may compute a first hash value based on first biometric data captured by a sensor unit, and may transmit a request to, and receive a response from, a computing system across a communications network via the communications unit. The request may cause the computing system to execute instructions maintained within the distributed ledger data, and to extract second biometric data maintained within an element of the distributed ledger data. The second biometric data may include a second hash, which the computing system may incorporate into the response. The device may authenticate an identity associated with the device when the first hash value corresponds to the second hash value incorporated within the response. |
| US10958640B2 |
Fast smart card login
Methods and systems for faster and more efficient smart card logon in a remote computing environment are described herein. Fast smart card logon may be used to reduce latency and improve security. For example, the system may reduce the number of operations (e.g., interactions) between a server device used for authentication and the client device. A remoting channel may be established between the server device and the client device. The server may receive, from the client device and/or via a personal computer/smart card (PC/SC) protocol, a message comprising an identifier for a smart card. The server device may replace the identifier for the smart card with a substitute identifier. Based on the substitute identifier, the server may determine one or more cryptographic service providers to use for one or more cryptographic operations associated with the smart card. One or more requests for cryptographic operations involving the smart card may be transmitted to the client device, such as via the cryptographic service provider and/or via the remoting channel. |
| US10958639B2 |
Preventing unauthorized access to secure information systems using multi-factor, hardware based and/or advanced biometric authentication
Systems for providing secure access to systems are provided. A computing device may receive a request to access functionality which may include login credentials of a user. Upon receiving the request to access functionality, the computing device may execute a scan of an area surrounding the computing device to detect any wearable devices within proximity of the computing device that are linked to the computing device. The authenticating information and, in some examples, detected, linked wearable device, may be validated. Based on the validation, authentication response data may be generated and transmitted to an authentication computing platform which may cause the authentication computing platform to validate the authentication response data and cause the computing device to connect to a client interface computing platform. After a connection between the computing device and client interface computing platform is established, interface data may be transmitted from the client interface computing platform to the computing device and one or more interfaces may be displayed on the computing device. |
| US10958633B2 |
Method and system for securely transmitting volumes into cloud
A first computing device is provided for transmitting one or more volumes via a secured connection. The first computing device includes a controller that is executable by one or more processors and is configured to instruct a cloud computing device to generate a worker virtual machine. The controller is also configured to provide authentication information to facilitate establishing of the secured connection between the controller and the worker virtual machine. The controller is further configured to instruct the cloud computing device to generate one or more target volumes associated with the cloud computing service and to associate the one or more target volumes with the worker virtual machine. The controller is further instructed to provide, irrespective of the content type of the volumes and the size of the volumes, the one or more volumes to the worker virtual machine via the secured connection. |
| US10958630B2 |
System and method for securely exchanging data between devices
An approach to exchanging data and identity between devices, securely, is provided. The approach includes data encryption, device management, a voting mechanism, message queuing, and encrypted data storing. Using the approach, a user can provide their identity to and share data with an external software or device in a secure manner. Also the user can decide where to store their encrypted data. |
| US10958624B2 |
Proxy auto-configuration for directing client traffic to a cloud proxy with cloud-based unique identifier assignment
Among other things, this document describes systems, methods and devices for providing a cloud proxy auto-config (PAC) function for clients connected to a private network, such as an enterprise network. The teachings hereof are of particular use with cloud hosted proxy services provided by server deployments outside of the private network (e.g., external to the enterprise or other organizational network). This document also describes systems, methods and devices for providing a proxy auto-config (PAC) function for clients connected to a third party network, such as when the client moves outside of the enterprise network. |
| US10958622B2 |
Hierarchical security group identifiers
In one example, a network element in a first network receives a network packet including a first security group identifier. The network element identifies the first security group identifier, determines that the first security group identifier is hierarchically correlated with a second security group identifier, and inserts the second security group identifier into the network packet. The network element forwards the network packet including the second security group identifier. |
| US10958619B1 |
System and method for private media casting on a shared network
A method includes receiving, at a proxy server, a multicast announcement through a first network. The multicast announcement is received from a casting device. The method further includes multicasting, from the proxy server, a modified version of the announcement to a second network. |
| US10958617B2 |
Systems and methods for using domain name system context based response records
A technique for resolving a uniform resource locator (URL) present on a social network website is presented. The technique includes detecting that a user's computing device is rendering a social network web page on the social network website, detecting a user activation of the URL present on the social network web page, where the URL present on the social network web page includes a domain name, obtaining a domain name system (DNS) resource record for the domain name, detecting, in the DNS resource record for the domain name, an entry for the social network website associated with a destination URL, retrieving content from the destination URL in response to at least the detecting that the user's computing device is rendering the social network web page and the detecting a user activation of the URL present on the social network web page, and causing the content to be displayed. |
| US10958616B2 |
Methods, systems, and computer readable media for network test configuration using virtual local area network (VLAN) scanning
Methods, systems, and computer readable media for network test configuration using VLAN scanning are disclosed. One method for network test configuration using VLAN scanning occurs at a first port of a network equipment test device. The method includes sending a plurality of address resolution protocol (ARP) requests to a system under test (SUT), wherein each of the plurality of ARP requests includes a different virtual local area network (VLAN) identifier (ID). The method also includes receiving an ARP response from the SUT, wherein the ARP response indicates a first VLAN ID associated with the SUT. The method further includes using the first VLAN ID when sending test packets to the SUT via the first port. |
| US10958610B2 |
Generating alerts based on predicted mood responses to received electronic messages
Embodiments include techniques to generate alerts based at least in part on predicted mood responses to received electronic communications that include receiving, using a processor system, a communication, and analyzing, using the processor system, contents of the communication. The techniques also include based at least in part on results of the analysis, predicting, using a machine learning system, a cognitive response of a recipient of the communication, and based at least in part on the predicted cognitive response, executing an alerting operation. |
| US10958605B1 |
Apparatus and method for alternate channel communication initiated through a common message thread
A server includes a processor and a memory storing a multiple channel message thread module with instructions executed by the processor to identify when participants at client devices are viewing a common message thread. An alternate channel communication prompt is supplied to the client devices. An alternate channel communication is delivered to the client devices in response to activation of the alternate channel communication prompt by at least one participant. |
| US10958603B2 |
Instant photo sharing via local area network setups
A computer-implemented method is presented for enabling instant and automatic photo sharing between computing devices. The method includes allowing a first user to operate a first computing device to create a plurality of images, the plurality of images including physical characteristics of a second user, transmitting a broadcast message to a plurality of second computing devices, determining whether a match occurs between the first computing device and one or more of the plurality of second computing devices, and establishing a local area network between the first computing device and matched second computing devices. The method further includes automatically and instantly transmitting the plurality of images to the matched second computing devices by priority and sequence determinations, and, upon completion of the transmittal of the plurality of images to the matched second computing devices, terminating the local area network. |
| US10958600B1 |
Systems and methods for multi-channel messaging and communication
A method is provided for operating a multi-channel messaging system. The method may provide automated conversation across multiple communication channels associated with a user by: selecting a first communication channel from the multiple communication channels, wherein the first communication channel is hosted by a first communication server; receiving, via an existing user interface of the first communication channel, a first user input via as part of a conversation with a chatbot, wherein the chatbot comprises a communication data structure comprising a plurality of communication paths; selecting a communication path based on the first user input; and generating a first feedback in response to the first user input according to the selected communication path. |
| US10958598B2 |
Method and apparatus for generating candidate reply message
The present disclosure discloses a method and apparatus for generating a candidate reply message. A specific embodiment of the method comprises: acquiring a text message of a currently received conversation; determining whether a pre-established conversation template matching the text message exists; and generating, in response to determining a conversation template matching the text message existing, a candidate reply message on the basis of the conversation template. According to the method provided by embodiments of the present disclosure, when the text message of the currently received conversation matches the pre-established conversation template, the candidate reply message is automatically generated, and a user may click the candidate reply message for reply, so that the time for the user to edit a reply message is saved, a period for the user to communicate with others is reduced, and the communication efficiency is improved. |
| US10958595B2 |
Cut-through bridge error isolation
A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage. |
| US10958591B2 |
Enhanced real-time linking methods and systems
Systems and methods for enabling links between various devices is provided. The systems and methods may include a platform that enables different devices to access spatial models of a resource. The platform may enable the different devices to define and/or modify assignment conditions for access rights to resources. Further, the platform may enable definition of assignment conditions before or after the access rights are available for assignment. |
| US10958585B2 |
Methods and apparatus for facilitating fault detection and/or predictive fault detection
Methods and apparatus for automatically identifying and correcting faults relating to poor communications service in a wireless system, e.g., in real time, are described. The methods are well suited for use in a system with a variety of access points, e.g., wireless and/or wired access points, which can be used to obtain access to the Internet or another network. Access points (APs), which have been configured to monitor in accordance with received monitoring configuration information, e.g. on a per access point interface basis, captures messages, store captured messages, and in collaboration with network monitoring apparatus which can be in an AP or external thereto, use message sequences to determine a remedial action to be automatically taken when poor service is likely as may be predicted based on the detected message sequence between a UE and one or more APs. |
| US10958583B2 |
Edge-node controlled resource distribution
This application describes apparatus and methods for using edge-computing to control resource distribution among access channels, such as a retail banking center. Edge-nodes may be configured to move a product display in response to detected or expected customer traffic flow in or near a retail location. Edge-nodes may be configured to redirect resources provided by a cloud computing environment to or away from the retail location. Based on customer traffic flow, edge-nodes may direct customers/resources to a retail location and ensure the retail location provides a predetermined quality of service. |
| US10958577B2 |
Route optimization using star-mesh hybrid topology in localized dense AD-HOC networks
Optimized routing in localized dense networks is provided. A packet is received at a first network device in a network. An optimal route for the packet to a neighbor network device in the network is determined using a Source Routing Table (SRT), wherein the SRT includes an optimized routing table and a standard routing table, and wherein the optimized routing table comprises a list of neighbor network devices that the first network device can route to directly and wherein the standard routing table comprises a ZigBee source routing table. The packet is routed using the optimal route. |
| US10958575B2 |
Dual purpose on-chip buffer memory for low latency switching
In one embodiment, an apparatus includes a buffer memory, at least one ingress port, at least one egress port, at least one processor, and logic integrated with and/or executable by the at least one processor, the logic being configured to communicate with a software-defined network (SDN) controller, store one or more look-up tables in a first portion of the buffer memory, receive a packet using an ingress port, and determine an egress port for the packet. In another embodiment, a method for switching packets in a SDN includes storing one or more look-up tables in a first portion of a buffer memory of a SDN-capable switching device, receiving a packet using an ingress port of the switching device, and determining an egress port for the packet. |
| US10958569B2 |
Server-assisted routing in network communications
A network node device and method of determining a communication route to one or more other network nodes through a network. The method includes sending current routing information to a network management server (NMS), and receiving new or supplemental routing information from the NMS, this supplemental routing information determined by the NMS based on the current routing information of the network node and of the one or more other network nodes. The supplemental routing information may include lateral route information identifying designated routing nodes that form lateral band(s) of nodes that span the network, each lateral band including gate node(s) as entrances/exits to the lateral band. The method may further include determining, based on the supplemental routing information, a route to one or more of the other network nodes. A lateral band may facilitate a route through a chokepoint or other abnormal topological layout. |
| US10958568B2 |
Topology aware load balancing engine
Concepts and technologies are disclosed herein for a topology aware load balancing engine. A processor that executes a load balancing engine can receive a request for a load balancing plan for an application. The processor can obtain network topology data that describes elements of a data center and links associated with the elements. The processor can obtain an application flow graph associated with the application and create a load balancing plan to use in balancing traffic associated with the application. The processor can create the load balancing plan to use in balancing traffic associated with the application and distribute commands to the data center to balance traffic over the links. |
| US10958563B2 |
Method and device to configure real-time networks
A method to configure nodes in a real-time network, which nodes are connected with links to each other directly or indirectly via other nodes and communicate with each other using said links by exchanging frames, wherein: (i) at least one node (a) associates at least one queue with at least one link, (b) is connected to said at least one queue, and (c) places frames in said at least one queue for transmission on the associated link, (ii) said at least one queue is associated with a gate which can be in an open or closed state, (iii) said at least one node selects frames that are placed in said at least one queue on the at least one link associated with said queue for transmission if the gate associated therewith is in the open state and does not select frames for transmission when said gate is in the closed state, (iv) said gate changes the state with the progress of time from open to closed and vice versa to form windows as indicated by configuration data, (v) said configuration data is produced by a tool capable of solving constraints in array theory, (vi) said tool accepts input formulated as constraints in array theory, (vii) said input is provided to said tool by human user input and/or by communication requests from one or more nodes in the real-time network, and (viii) said configuration data is communicated to one or more nodes in the real-time network, nodes which apply part or all of said configuration data as local configuration. |
| US10958559B2 |
Scaled inter-domain metrics for link state protocols
In general, techniques are described by which to provide a scaled end-to-end view of link metrics to integrate multiple non-uniform Interior Gateway Protocol (“IGP”) domains. For example, an Accumulated Interior Gateway Protocol (“AIGP”) attribute, a non-transitive BGP attribute, which includes a link metric assigned to a link within a first IGP domain, is scaled to conform to a metric scale of the second IGP domain. The AIGP attribute may also add link metric assigned to a link within the second IGP domain and may add static metrics of non-IGP links connecting the IGP domains. An IGP domain may set its IGP to the scaled AIGP attribute such that the link metric may include a uniformly scaled end-to-end view of link metrics across the IGP domains. Additionally, a sham-link is assigned a metric value in accordance with the scaling techniques. |
| US10958557B2 |
Automated deployment of a private monitoring network
A processor, based on detection of a configuration change to a central electronics complex (CEC) in a CEC group, automatically creates a monitoring network within the CEC. Automatically creating the monitoring network includes the processor issuing a request via a hardware management console (HMC) to the CEC to create a virtual switch implementing a virtual local area network (VLAN). The processor also issues a request via the HMC to the CEC to create, on a virtual input-output server (VIOS) hosted in the CEC, a virtual trunk adapter connected to the VLAN. In addition, the processor issues a request via the HMC to the CEC to create, on each of a plurality of logical partitions (LPARs) hosted in the CEC, a virtual network adapter connected to the VLAN. The processor can employ the network, for example, to monitor health of the LPARs and VIOS within the CEC via the HMC. |
| US10958554B2 |
Monitoring flow activity on a network device
Examples disclosed herein relate to monitoring flow activity on a network device. In an example, a neighbor table is maintained on a network device. The neighbor table may include a record of a neighbor network device and a hit bit corresponding to the neighbor network device. The hit bit may be used to represent a flow activity of the neighbor network device. A determination may be made whether a status of the hit bit corresponding to the neighbor network device is inactive. If the status of the hit bit is inactive, a flow entry corresponding to the neighbor network device may be deleted from an ASIC table on the network device. |
| US10958551B2 |
Jitter determination method and measurement instrument
A jitter determination method for determining at least one random jitter component of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving the input signal; determining a time interval error associated with the random jitter component; determining at least one statistical moment of the time interval error based on the determined time interval error, wherein the order of the statistical moment is two or larger; at least one of determining an impulse response based on the input signal and receiving the impulse response, the impulse response being associated with at least the signal source; and determining the standard deviation of the random jitter component based on at least one of the determined statistical moment and the determined impulse response. Moreover, a measurement instrument is described. |
| US10958549B2 |
Method and system for analyzing protocol message sequence communicated over a network
A method of analyzing protocol message sequence communicated over a network, involves receiving one or more protocol messages associated with a real-time communication session between a first network node and a second network node in the network. A set of packet attributes corresponding to the one or more protocol messages associated with the real-time communication session may be extracted. Each one of the set of packet attributes may be compared with a plurality of baseline attributes. At least one error condition in at least one protocol message received from the first network node may be determined based on the comparison. A corrective measure on the first network node may be performed based on the at least one error condition in the at least one protocol message received from the first network node. |
| US10958547B2 |
Verify a network function by inquiring a model using a query language
In some examples, a system can verify a network function by inquiring a model using a query language is described. In some examples, the system can include at least a memory and a processor coupled to the memory. The processor can execute instructions stored in the memory to transmit a plurality of packets into at least one network function that is unverifiable; describe the at least one network function using a model comprising a set of match action rules and a state machine; inquire the model using a query language comprising a temporal logic to obtain a query result indicating an expected behavior of the plurality of packets; and verify the at least one network function based on the query result and the expected behavior of the plurality of packets. |
| US10958538B2 |
Symmetric coherent request/response policy enforcement
A set of service level agreement (SLA) policies and service level definition (SLD) policies that are applied to a request message of a correlated request/response message pair are tracked. A response message of the correlated request/response message pair is detected. A corresponding set of platform-specific policy enforcement processing rules that are used to enforce the set of SLA policies and SLD policies on the response message are identified using the tracked set of SLA policies and SLD policies applied to the request message. The set of SLA policies and SLD policies are enforced on the response message using the identified corresponding set of platform-specific policy enforcement processing rules. |
| US10958537B2 |
Method for spatio-temporal monitoring
One exemplary aspect describes systems and methods for determining normal SLE behavior, determining when a SLE exhibits abnormal deterioration, and determining whether to take an action to mitigate what appears to be an indication of an abnormal SLE. |
| US10958534B2 |
User interfaces for presenting cybersecurity data
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for surfacing anomalous network activity on a user interface. An example method provides, for presentation on a user device, a user interface for analyzing network traffic from a customer network. The user interface is populated with network traffic data from the customer network for display to the user. An interactive first filter that is configurable for filtering network traffic based on prevalence of the destination domains of the network traffic is displayed to the user. A first user input configuring the first filter to a first prevalence value is received. In response, the network traffic data is filtered in the user interface to only include network traffic data that has a destination domain that is less prevalent than the first prevalence value. |
| US10958531B2 |
On-demand remote predictive monitoring for industrial equipment analysis and cost forecast
Sensor data is detected from at least one sensor selected and installed for detecting operating conditions of at least one equipment. The sensor data includes an operating condition of at least one equipment. The sensor is selected dependent on indications of a user restriction and a predictive model. A sensor data signal is generated dependent on the sensor data. The sensor data signal is transmitted to a network device for collecting the sensor data and transforming the collected sensor data into a formatted transmission signal having a format for transmission over a network to a network server. The network server receives the formatted transmission signal for performing on-demand service of at least one of analysis, reporting and visualization dependent on the operating condition. |
| US10958529B2 |
Clique network identification method and apparatus, computer device, and computer-readable storage medium
The present disclosure provides a method for identifying a clique network using a Pregel graph computing framework. The method includes determining, according to a data transfer feature of a target clique, a transmitting direction of attribute values of nodes; transmitting, an edge vector of the edge and an attribute value of the first node to the second node along the transmitting direction in a constructed data transmission relationship network, the edge vector comprising a plurality of data transfer eigenvalues; performing, weighted calculation on the edge vector received by the second node to obtain an optimal weighted edge; iterating, the above operations; and determining, according to attribute values of the nodes after the one or more iterations, nodes in the target clique, and determining attributes of the nodes in the target clique. |
| US10958526B2 |
Methods for managing bandwidth allocation in a cloud-based system and related bandwidth managers and computer program products
Methods for allocating bandwidth in a central cloud-based system are provided including receiving a request for a subscription for information stored in the central cloud-based system from a third-party customer and allocating one or more partitions in a queue to the third-party customer. The one or more partitions each have corresponding threads and a number of the one or more partitions is determined by an estimated amount of traffic associated with the requested subscription for the third-party customer. Information is provided meeting terms of the subscription to the third-party customer using the allocated one or more partitions in the queue and the corresponding threads. At least one of the receiving, allocating and providing is implemented by at least one processor. Related devices and computer program products are also provided. |
| US10958521B2 |
Method and apparatus for configuring a cloud storage software appliance
The embodiments disclosed herein relate to intelligent configuration of a cloud-service gateway based on a pattern recognition algorithm. A machine-learning model is trained to learn the patterns of correlation among many configuration parameters affecting the performance of the system when processing an observed or estimated workload. Training the model may be performed off-line with performance data observed during experiments performed with a variety of configurations and workloads. Once trained, the model may be used to recommend: (a) new configuration parameter values based on constraints of the system being configured, (b) an amount of work that can be performed at a certain performance level when the system is configured with certain parameter values, or (c) the expected performance level when running a certain workload on the system configured with certain configuration parameter values. |
| US10958520B2 |
Method for generating network optimizing information
There is provided a method for generating network optimizing information including the steps of identifying system devices that are comprised in a network, collecting metrics from the identified system devices, including collecting at least one metric relating to the operation, status, capability, limitations, expandability, scalability, or performance of the system devices, assessing the collected metrics according to a predetermined assessment protocol, generating a roster of metrics of interest, such metrics of interest being a group of the collected metrics that meet a selection criteria and not including other collected metrics that do not meet the selection criteria, and presenting each of the metrics of interest in a format suitable for a network operator to take corrective actions with regard to the identified non-compliant metrics or to capitalize on the identified optimization opportunities with respect to the network. |
| US10958519B2 |
Dynamic, load-based, auto-scaling network security microservices architecture
System, methods, and apparatuses used to monitor network traffic of a datacenter and report security threats are described. For example, one embodiment selects a first microservice of a first hierarchy, configures the microservices of a second lower-level hierarchy to remove the first microservice from load balancing decisions to the first hierarchy, moves the first microservice to another server, configures data plane connectivity to the first microservice to reflect a change in server, and configures the microservices of the second hierarchy to include the first microservice in load balancing decisions to the first hierarchy. |
| US10958518B2 |
Dynamic switching between hub mode and slave mode
In one aspect, a device includes at least one processor and storage accessible to the at least one processor. The storage includes instructions executable by the at least one processor to switch a hub device from a hub mode to a slave or pass-through mode responsive to one or more contextual triggers. |
| US10958517B2 |
Conflict-free change deployment
A new scalable approach to conflict-free deployment of changes across networks. The conflict rules or constraints may be modeled using policies and algorithms to determine an optimized schedule for change deployment. |
| US10958515B2 |
Assessment and dynamic provisioning of computing resources for multi-tiered application
Systems and methods for allocating computing resources for a multi-tiered application are disclosed. A computer-implemented method includes: determining, by a computing device, a topology of a multi-tiered application; determining, by the computing device, a modeled setting of a computing resource for the multi-tiered application based on the determined topology; determining, by the computing device, an actual usage of the computing resource by the multi-tiered application; and adjusting, by the computing device, an allocation of the computing resource to the multi-tiered application based on the actual usage and the modeled setting. |
| US10958506B2 |
In-situ OAM (IOAM) network risk flow-based “topo-gram” for predictive flow positioning
A system and method predict risks of failure or performance issues in a network to predictively position traffic flows in the network. For a traffic flow through a network, first data accumulated in a header of packets for the traffic flow is obtained, which header is populated by network elements along a path of the traffic flow through the network. Second data is obtained about the network in general including other network elements not along the path of the traffic flow. Machine learning analysis is performed to derive rules that characterize failure or performance risk issues in the network. The rules and topology data describing a topology of the network are applied to a model to create a topological graphical representation indicating failure or performance issues in the network that affect the traffic flow. A path for the traffic flow is modified based on the topological graphical representation. |
| US10958503B2 |
MIB-oriented protocol for HTTP management
Method for transmitting data packets between a network management station monitoring a network and network devices on which agents are installed, the network management station communicating with the agent of a network device via instructions; said method is characterized in that the network management station accesses a management information base of a network device by means of a configurable instruction and retrieves data packets corresponding to the configuration of the instruction. |
| US10958502B2 |
Port mapping
Systems, apparatuses, and methods are described for auto-discovery of port-to-port connectivity through correlative analysis on performance metrics. Statistical data corresponding to each port of routers and transport devices may be collected. The collected data may be processed such that missing data may be patched and time frames may be aligned. Statistical analysis may be performed on the collected data. Such statistical analysis may comprise generating a waveform based on the data and determining, e.g., correlations in the data. If the analyzed data of one port matches analyzed data of another port, the two ports may be determined to be connected to one another. A match may be based on meeting various criteria and/or thresholds. |
| US10958499B2 |
Transporting digital data in a distributed antenna system
A method of transporting digital data in an active distributed antenna system DAS. The method includes receiving data from at least one data source, processing the received data, and providing the processed data as digital real-valued passband data for further transport within the DAS. An apparatus and computer program configured to perform the method are also provided. |
| US10958493B2 |
Method and apparatus for transmitting and receiving time division duplex frame configuration information in wireless communication system
A method and an apparatus for transmitting and receiving Time Division Duplex (TDD) frame configuration information are disclosed. The base station transmits TDD frame configuration information as system information to a user equipment through a common control channel so as to dynamically change the TDD frame configuration according to uplink and downlink traffic conditions. The base station may deliver the same system information to all user equipments in the cell, removing ambiguity in User Equipment (UE) operations and avoiding interference. In comparison to an existing method of delivering TDD frame configuration information through system information update, the disclosed method enables user equipments to rapidly cope with traffic changes. In addition, user equipments may receive and apply TDD frame configuration information at the same time. |
| US10958490B2 |
Transponder with high-frequency demodulator optimized for analog-digital mixed operation
The invention relates to a transponder that transmits measurement values that does not have an energy source of its own, which draws energy from a radio field and that includes a novel input circuit to demodulate the high frequency. The novel circuit facilitates using the transponder for digital identification and measurement purposes respectively with a high level of efficiency. Intelligent coupling of a conventional full wave diode rectifier with an inductivity and a switching element, advantageously a MOSFET providing power for a digital circuit is facilitated as well as providing power for an analog quartz sensor, herein the power is always conducted into the path where it is required. Additionally the quartz sensor arrangement is activated or deactivated at will by precisely one switching element and an increased output voltage for the digital circuit is generated by smart modulation of the high frequency feed signal using the inductivity. |
| US10958485B1 |
Methods and systems for performing analysis and correlation of DOCSIS 3.1 pre-equalization coefficients
A method, apparatus and system for implementing pre-equalization equalizer tap analysis and correlation in a DOCSIS 3.1 network environment. The disclosed principles improve the pre-equalization analysis in the DOCSIS 3.1 environment by filtering out short distance reflections, which is required for the proper grouping and correlation of modems. |
| US10958484B1 |
Time-based decision feedback equalizer
In some examples, a time-based equalizer can be configured to receive an input signal from a channel. The input signal can be distorted by previously received input signals transmitted over the channel. The time-based equalizer can be configured to compensate for distortions in the input signal caused by at least one previously received input signal to provide an ISI compensated input signal. The time-based equalizer can be configured to compensate for the distortions by edge time shifting respective edges of the input signal in time over a time interval for detecting the input signal to new edge time locations based on a feedback signal and edge movement signals. The feedback signal can be generated based on at least one previously received input signal. |
| US10958482B2 |
Information transmission method and system, and convergence gateway
An information transmission method and system, and a convergence gateway, where the method includes receiving, by the convergence gateway, a service request from first user equipment, where the service request includes identity information of the first user equipment and service information of the first user equipment, obtaining, by the convergence gateway, first user permission information of the first user equipment in a first network according to the identity information of the first user equipment, and determining, by the convergence gateway based on the first user permission information, a forwarding manner for forwarding the service information to second user equipment. A convergence service for a private network and a public network is implemented using the convergence gateway such that indoor communication signal quality can be improved, and network construction costs can be reduced. |
| US10958481B2 |
Transforming a service packet from a first domain to a second domain
In an example, a hierarchical chaining gateway (hCG) includes a first communication interface corresponding to a first domain using a first chaining protocol, and a second communication interface corresponding to a second domain using a second and different chaining protocol. The hCG receives a service packet including a first service function chain header via the first communication interface. The hCG also identifies a key identifier in the service packet, and retrieves a second service function chain header based on the key identifier. Then, the hCG transforms the service packet by substituting the first service function chain header corresponding to first domain in the service packet with the second service function chain header corresponding to the second domain. Next, the hCG transmits the service packet including the second service function chain header via the second communication interface corresponding to the second domain. |
| US10958479B2 |
Selecting one node from several candidate nodes in several public clouds to establish a virtual network that spans the public clouds
Some embodiments establish for an entity a virtual network over several public clouds of several public cloud providers and/or in several regions. In some embodiments, the virtual network is an overlay network that spans across several public clouds to interconnect one or more private networks (e.g., networks within branches, divisions, departments of the entity or their associated datacenters), mobile users, and SaaS (Software as a Service) provider machines, and other web applications of the entity. The virtual network in some embodiments can be configured to optimize the routing of the entity's data messages to their destinations for best end-to-end performance, reliability and security, while trying to minimize the routing of this traffic through the Internet. Also, the virtual network in some embodiments can be configured to optimize the layer 4 processing of the data message flows passing through the network. |
| US10958478B2 |
Resilient polymorphic network architectures
Methods and systems for mutating a network topology on which various containers run. The system includes a host controller to assign each of a plurality of hosts an unchanging public virtual IP address that maps to changing real IP address, a threat detection module to detect a mutation stimuli, and a management module configured to receive a mutation policy and execute the mutation policy to enact a container mutation upon the threat detection module detecting the mutation stimuli. |
| US10958472B2 |
Direct access to bus signals in a motor vehicle
The disclosure relates to a control system for at least one motor vehicle, including a first control unit having a data interface for coupling the first control unit to a vehicle data bus, as well as having a first network interface for coupling the first control unit to a second control unit via an internet-protocol-based network. The control system also includes the second control unit having a second network interface for coupling the second control unit to the first control unit via the internet-protocol-based network. The second control unit is designed to send or receive at least one control signal that can be transmitted via the vehicle data bus by the first control unit via the vehicle data bus. |
| US10958471B2 |
Method and apparatus for detecting wire fault and electrical imbalance for power over communications cabling
In one embodiment, a method includes transmitting Power over Ethernet (PoE) in a PoE distribution system at a power greater than 100 watts, the distribution system comprising at least two pairs of wires, monitoring a thermal condition in the distribution system, periodically checking each of the wires for a fault, and checking for an electrical imbalance at the wires. An apparatus is also disclosed herein. |
| US10958470B2 |
Attributing bus-off attacks based on error frames
An error detector is configured to identify transmission errors and maintain a transmit error counter (TEC) value and corresponding network identifier for each of a plurality of electronic control units (ECUs) connected to a network bus. The error detector is configured to adjust the TEC values for the ECUs based on error frames and inform an intrusion detection system when an ECU changes error state. In this manner, the error detector is configured to help identify and attribute attacks by an impersonating node when a message is received containing the network identifier of a legitimate ECU that is in a Bus Off state. |
| US10958469B2 |
Methods and systems for increasing wireless communication throughput of a bonded VPN tunnel
The present disclosure provides for devices, systems, and methods which optimize throughput of bonded connections over multiple variable bandwidth logical paths by adjusting a tunnel bandwidth weighting schema during a data transfer session in response to a change in bandwidth capabilities of one or more tunnels. By making such adjustments, embodiments of the present invention are able to optimize the bandwidth potential of multiple connections being used in a session, while minimizing the adverse consequences of reduced bandwidth issues which may occur during the data transfer session. |
| US10958467B2 |
Ducking and erasing audio from nearby devices
A smart home device (e.g., a voice assistant device) includes an audio control system that determines a set of one or more audio devices to include nearby devices that are capable of providing audio streams that are audibly detected by a microphone of the smart home device. The audio control system initiates a voice-interaction mode for operating the smart home device to receive voice commands from a user and provide audio output in response to the voice commands. The audio control system transmits an audio control signal to nearby devices that configures each nearby device to implement one or more of: reducing a volume level associated with the audio streams generated by the nearby devices while the smart home device is operating in the voice-interaction mode; and transmitting, to the smart home device, audio stream data associated with a current audio stream generated for audible output by the nearby device. |
| US10958465B2 |
System, method, apparatus, and computer program product for configuring a network connected appliance to use online service
A system, method, apparatus, and computer program product for configuring a network connected appliance to use online services are disclosed. A method may include receiving an indication of a selected home automation system for a network connected appliance. The selected home automation system may be selected from multiple available home automation systems. The method may additionally include registering the network connected appliance to the selected home automation system. The method may also include enabling communication between the network connected appliance and the selected home automation system. |
| US10958464B2 |
Distributed rules engine
A plurality of devices of an enterprise are identified. For example, lights and door sensors are identified. The plurality of devices of the enterprise uses a plurality of gateways in a hierarchy of gateways to control the plurality of devices of the enterprise. A first rule for at least two of the plurality devices of the enterprise is received. For example, the first rule may be to turn on a light when door is opened. In response to receiving the first rule, a first lowest level gateway of the plurality of gateways in the hierarchy of gateways is determined for applying the first rule for the at least two of the plurality of devices of the enterprise. The first rule for the at least two of the plurality devices of the enterprise is sent to the first lowest level gateway. |
| US10958462B2 |
Using a central controller cluster to configure a distributed multicast logical router
For a managed network implementing at least one logical router having centralized and distributed components, some embodiments provide a method for configuring a managed forwarding element (MFE) executing on a first host machine to implement a distributed multicast logical router and multiple logical switches logically connected to the logical router in conjunction with a set of additional MFEs executing on additional host machines to process multicast data messages. The method receives a multicast group report from a data compute node (DCN) that executes on the first host, sends a summarized multicast group report indicating multicast groups joined by DCNs executing on the first host to a set of central controllers, receives data based on an aggregated multicast group report from the set of central controllers, and uses the data based on the aggregated multicast group report to configure the MFE to implement the distributed multicast logical router. |
| US10958461B2 |
SDN facilitated multicast in data center
A method implemented by a controller in a software defined network (SDN), the method comprising sending, to an overlay edge node, a query message comprising a client specific multicast address, receiving, from the overlay edge node, one or more report messages corresponding to the query message, wherein each of the one or more report messages comprises an address of each of one or more virtual machines (VMs) coupled to the overlay edge node, and updating membership of a multicast group, which is identified by the client specific multicast address, such that the one or more VMs are members in the updated membership of the multicast group. |
| US10958460B2 |
Connecting multiple networks for multicast groups
Techniques for connecting networks to facilitate distribution of data are described. For example, to distribute multicast data to members of a multicast group that span multiple networks, the techniques may identify a path between networks that each have a member of the multicast group, such as a shortest path between networks. The techniques may inform the networks on the path to establish a connection with an adjacent network. This may allow multicast data for a multicast group to be distributed to members of the multicast group that are located in separate networks. |
| US10958455B2 |
Method for sending/receiving data in a wireless packet communication system in which there is simultaneous communication with various terminals
A method and apparatus for transmitting a frame to at least one receiver in a wireless communication system is provided. The apparatus determines at least one data length in accordance with each receiver based on a number of symbol for the frame to be transmitted, determines a maximum data length among the at least one data length, and determines a length of the frame in time domain based on the maximum data length. The apparatus generates the frame in accordance with the length of the frame, the frame including a first signal field and at least one second signal field. The first signal field indicates the length of the frame and each second signal field indicates each data length. |
| US10958452B2 |
System and device including reconfigurable physical unclonable functions and threshold cryptography
A system and device, including reconfigurable physical unclonable functions (‘RPUFs’) and threshold cryptography, use cryptographic and physical means of security. A plurality of reconfigurable physical unclonable functions (‘RPUFs’) and a memory are connected to a processor that is configured to derive information associating the RPUFs with cryptographic shares of a sensitive value, store such information in the memory, and reconfigure a RPUF upon powering up of the device such that information stored in the memory is not valid for the reconfigured RPUF. |
| US10958449B2 |
Certificate application operations
Implementations of this disclosure provide for certificate application operations. An example method includes sending, from a terminal device, a subscription topic name to a gateway to establish a data transmission channel between the terminal device and the gateway; receiving by the terminal device, via the data transmission channel, a certificate installation instruction from a certificate server; generating, by the terminal device, a user certificate request based on the certificate installation instruction; sending the user certificate request to the certificate server; and receiving, via the data transmission channel, a user certificate from the certificate server. |
| US10958448B2 |
User authentication with self-signed certificate and identity verification and migration
In embodiments, an authentication server interfaces between a user device with a self-signed certificate and a verifying computer that accepts a user name and password. The user device generates a self-signed certificate signed by a private key on the user device. The self-signed certificate is transmitted to a verifying party computer over a network. The verifying party stores the self-signed certificate with user identification data. The user migrates trust to another device by providing the root certificate and intermediate certificate as a certificate chain to a second device, which then adds a new intermediate certificate to create a longer certificate chain with the same root certificate. In subsequent communications, the verifying party receives a certificate chain including the self-signed certificate from the second user device, and matches that with the user identification data stored in a database. |
| US10958447B2 |
Method, security device and security system
An apparatus, a security device, a security system comprising the security device and the apparatus, and a method for generating an apparatus-specific apparatus certificate for the apparatus includes coupling the security device to the apparatus, a one-time useable private signing key being stored in the security device, storing apparatus-specific identification information in the security device, accessing the private signing key in the security device, generating the apparatus-specific apparatus certificate depending on the stored identification information in the security device, the apparatus-specific apparatus certificate being signed using the private signing key, and preventing a further access to the private signing key such that it becomes possible to generate an apparatus-specific apparatus certificate for an apparatus with little complexity, in particular without using a public key infrastructure. |
| US10958444B2 |
Uniquely identifying and securely communicating with an appliance in an uncontrolled network
A service consumer that utilizes a cloud-based access service provided by a service provider has associated therewith a network that is not capable of being controlled by the service provider. An enterprise connector is supported in this uncontrolled network, preferably as an appliance-based solution. According to this disclosure, the enterprise configures an appliance and then deploys it in the uncontrolled network. To this end, an appliance is required to proceed through a multi-stage approval protocol before it is accepted as a “connector” and is thus enabled for secure communication with the service provider. The multiple stages include a “first contact” (back to the service) stage, an undergoing approval stage, a re-generating identity material stage, and a final approved and configured stage. Unless the appliance passes through these stages, the appliance is not permitted to interact with the service as a connector. As an additional aspect, the service provides various protections for addressing scenarios wherein entities masquerade as approved appliances. |
| US10958443B2 |
Confidential blockchain transactions
A computer-implemented method includes: determining assets held by a remitter, the assets to be spent in a remittance transaction between the remitter and one or more payees, in which each asset corresponds to a respective asset identifier, a respective asset amount, and a respective asset commitment value; determining a remitter pseudo public key and a remitter pseudo private key; determining a cover party pseudo public key, in which the cover party pseudo public key is obtained based on asset commitment values of assets held by the cover party; and generating a linkable ring signature for the remittance transaction. |
| US10958442B1 |
Secure digital communications
Disclosed in some examples are methods, systems, and machine readable mediums for secure end-to-end digital communications involving mobile wallets. The result is direct, secure, in-band messaging using mobile wallets that may be used to send messages such as payments, requests for money, financial information, or messages to authorize a debit or credit. |
| US10958441B2 |
Signature verification for a blockchain ledger
Implementations of this specification provide signature verification methods and apparatuses for a blockchain ledger. An example method includes receiving by a server, a signature verification instruction that comprises a verification object parameter and a hash value. The verification object parameter includes a third-party parameter, a platform parameter, or a time service certificate parameter, the verification object parameter indicates a type of a to-be-verified object, and the server is configured to store data by using the blockchain ledger. The server obtains the to-be-verified object based on the verification object parameter and the hash value. The type of the to-be-verified object includes a third-party digital signature, a server digital signature, or a time service certificate. The server sends the to-be-verified object to a client for verification by the client. |
| US10958436B2 |
Methods contract generator and validation server for access control of contract data in a distributed system with distributed consensus
Methods for access control of contract data in a distributed system are provided. The distributed system includes a contract generator, a validation server, a database and a distributed ledger which are in communication via a network, the method including the steps of: at the contract generator, receiving digital contract data from a first electronic device, determining a permission setting for accessing contract content associated with the digital contract data based on the digital contract data, and setting the permission setting to the validation server via the network, obtaining a validation link corresponding to the digital contract data from the validation server, generating contract information for digital contract data according to partial content of the digital contract data and the validation link, and storing the contract information in the distributed ledger. |
| US10958435B2 |
Providing security in an intelligent electronic device
Apparatuses, systems, and methods for providing security in an intelligent electronic device (IED) are provided. In one aspect of the present disclosure, an IED is provided including at least one processor that receives a communication via a communication interface, the communication including an unencrypted file and a digital signature. The at least one processor decrypts the digital signature to obtain a first value, executes a hash function on the unencrypted file to obtain a second value, determines if the first value and second value match, and updates at least one firmware package stored in at least one memory of the IED with the unencrypted file if it is determined that the first value and the second value match. |
| US10958433B2 |
Origin certificate based online certificate issuance
A method provides an origin certificate that can be issued as a digital certificate online. The method includes receiving an origin digital certificate and an encrypted client device private key from an offline certificate authority wherein the client device private key is encrypted according to a private key encryption key PrKEK. The method further includes receiving from the client device, a request for a client device digital certificate and the encrypted client device private key, selecting a digital certificate template for the client device, the digital certificate template having attributes that vary according to the client devices, building the client device digital certificate from the origin digital certificate and the selected digital certificate template, signing the client device digital certificate with an online certificate authority signing key, and transmitting the signed client device digital certificate and the encrypted device private key. |
| US10958432B1 |
Prime number prediction
A regression on a prime-indexed-prime finite difference generator function is used to predict prime numbers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US10958429B2 |
Method of performing device to device communication between user equipments
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). In accordance with an aspect of the present disclosure, a method of transmitting data in a device to device communication system is provided. The method includes determining whether a security feature is applied to one or more packet data convergence protocol (PDCP) data units, configuring the one or more PDCP data units based on the determined result, and transmitting the one or more PDCP data units to one or more receiving user equipments (UEs). |
| US10958427B2 |
Original key recovery apparatus and method
In the embodiments of the present invention, a transmit optical signal includes a reference optical signal and a quantum optical signal, optical splitting processing and coherent coupling are performed on the transmit optical signal by using a local oscillator optical signal to obtain at least two coherently coupled optical signals, and then optical-to-electrical conversion and amplification are separately performed on a first coherently coupled optical signal that includes the reference optical signal and a second coherently coupled optical signal that includes the quantum optical signal, to obtain a first electrical signal and a second electrical signal. Then, phase frequency information between the local oscillator optical signal and the reference optical signal is obtained from the first electrical signal, and an original key is recovered from the second electrical signal based on the phase frequency information. |
| US10958426B2 |
Improving security protocols
A computer implemented method of authenticating communication between a first node and a second node, using a function of combined information obtained from at least one of the nodes, the method comprising: sending a commitment message from the first node to the second node, the message containing content based on (at least) a first part of the combined information, which content commits the first node to a first value of the function, and wherein the first part of the combined information is communicated from the first node to the second node with a delay mechanism that only allows the first part of the information to be determined by the second node after a predetermined time; and in response to receiving notification at the first node that the second node has received the message, which receipt commits the second node to the first function value. |
| US10958424B1 |
Mechanism to allow third party to use a shared secret between two parties without revealing the secret
A system, such as an extension service, receives a first public key that is derivable based at least in part on a secret that is shared between at least a first device and a second device. The system, in an embodiment, derives a cryptographic key based at least in part on the first public key and transmits a second public key that enables another system to derive the cryptographic key. In an embodiment, the cryptographic key is a symmetric key and the system lacks access to a first private key that corresponds to the first public key. |
| US10958423B2 |
Automated changeover of transfer encryption key
The automated changeover of a transfer encryption key from one transfer encryption key to another. This occurs in an environment in which a set of computing systems are to share one or more keys (such as a private and public key pair). The transfer encryption key is used to encrypt communications of the key(s) such that the encrypted key(s) may be transferred over a transfer system without the transfer system having access to the key(s). In order to perform automated changeover of the transfer encryption key, one of the set of computing systems encrypts the next transfer encryption key with the prior transfer encryption key. The transfer system provides this encrypted message to the remainder of the set of computing systems, which may then decrypt the encrypted message using the prior transfer encryption key, to find the next transfer encryption key. |
| US10958420B2 |
Method and system for blockchain-implemented project management
A method for project management using a blockchain includes: receiving a project request including a project stream comprised of a plurality of role assignments and an ordering for the role assignments, wherein each role assignment indicates a corresponding public key; generating a first digital token; transmitting the first digital token to a first computing device associated with a public key corresponding to a first role assignment based on the ordering; receiving data from the first computing device including a data file, return token, and digital signature; validating the return token based on the first digital token; validating the digital signature using the public key corresponding to the first role assignment; transmitting the data file to a node in a blockchain network; and transmitting a second digital token to a second computing device associated with a public key corresponding to a second role assignment based on the ordering. |
| US10958419B2 |
Method to establish distributed ledger networks with multiple access levels for an incident
A computer-implemented method is provided to submit incident data to distributed ledger networks. A request for a new incident record relating to an incident is received. The request includes at least one attribute relating to the incident. A jurisdiction of the new incident is determined. Nodes that are associated with the jurisdiction are identified. The identified nodes are invited to join a public distributed ledger network or a private distributed ledger network. The new incident record is submitted to the private distributed ledger network. |
| US10958417B2 |
Protecting sensitive data in a distributed ledger system using blockchain hierarchies
A blockchain hierarchy comprises an arrangement of blockchains organized in a tree-like manner such that a blockchain at a lower level feeds data to a blockchain at a relatively higher level. At least one blockchain comprises a private autonomous group of peers that are involved in a particular task. Within that particular group of peers, preferably one of the peers is elected as a leader entity, which has the capability of also joining another private or public blockchain, e.g., one at a higher level in the hierarchy. The leader entity includes a capability to enforce a data protection policy within the blockchain that it leads. To this end, the leader filters or declassifies data based on some task-specific (or blockchain-specific) data protection policy, and it then makes that data available to one or more other blockchains in the hierarchy (directly or indirectly). |
| US10958413B2 |
Signal transmission method and system and retimer
A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device. |
| US10958408B2 |
Transmit-and-receive module
A transmit-and-receive module includes a power amplifier, a low-noise amplifier, first and second phase shifter circuits, and a correction circuit. The power amplifier amplifies power of first and second transmit signals. The low-noise amplifier amplifies first and second received signals without increasing noise. The first and second phase shifter circuits adjust impedance for the first received signal and that for the second received signal. The correction circuit supplies a canceling signal to an output node of the second phase shifter circuit. The canceling signal is used for canceling the first transmit signal passing through a receive filter. |
| US10958407B2 |
Frequency division duplexing hybrid automatic repeat request with mini-slots
Methods, systems, and devices for wireless communication are described. A transmitting device may identify a duration of a slot used for communications with a receiving device. The transmitting device may determine that the communications with the receiving device comprises frequency division duplexing (FDD) communications. The transmitting device may transmit communications to the receiving device during a first portion of the slot, a duration of the first portion being less than the duration of the slot and the duration of the first portion is based at least in part on the determination that the communications comprise FDD communications. The transmitting device may select, based at least in part on the determination that the communications comprise FDD communications and that the communications are transmitted during the first portion of the slot, a hybrid automatic repeat request (HARQ) scheme to use during the communications. |
| US10958405B2 |
Method and apparatus for transmitting and receiving wireless signal in wireless communication system
The present invention relates to a wireless communication system, more specifically, to a method and an apparatus therefor, the method comprising the steps of: merging a first cell having a first TTI and a second cell having a second TTI, the length of the second TTI being N (N>1) times the length of the first TTI; receiving data scheduling information for the second cell in the first TTI of the first cell; and establishing data communication on the basis of the data scheduling information in the second TTI of the second cell corresponding to the first TTI of the first cell, wherein the first TTI for the first cell is any one TTI from among the N number of TTIs of the first cell corresponding to the second TTI of the second cell. |
| US10958404B2 |
Discovery reference signal configuration and scrambling in licensed-assisted access
The disclosure provides for receiving a downlink transmission for wireless communications. A user equipment (UE) may receive, on a primary component carrier, an indication that a subframe of a secondary component carrier includes a discovery reference signal. During the subframe, the UE may receive, on the secondary component carrier over an unlicensed spectrum, a transmission including the discovery reference signal. The UE may rate match the transmission based on the indication. The disclosure further provides for discovering timing information during wireless communications. The UE may receive on a primary component carrier, an indication that a set of subframes of a carrier of a neighboring cell includes a discovery reference signal. The UE may determine a subframe to receive the discovery reference signal based on the indication. The UE may receive during the subframe, the discovery reference signal from the neighboring cell in an unlicensed spectrum. |
| US10958402B2 |
Techniques for reducing communication errors in a wireless communication system
A technique for operating a wireless communication device includes transmitting a scheduling request from the wireless communication device and receiving, following the scheduling request, an uplink grant that assigns an uplink channel to the wireless communication device. The uplink grant may include one or more fields indicating whether only channel quality information is to be transmitted and/or if data is to be transmitted. |
| US10958399B2 |
Terminal device, infrastructure equipment and methods
A terminal device for use with a wireless telecommunications network, the terminal device comprising: transceiver circuitry configured to receive data from the wireless telecommunications network, and a controller configured: to control the transceiver circuitry to receive control information, a control channel and a data channel wherein, the control information defines the period of time between the control channel and the data channel, and to ignore a subsequent control channel received during the period of time following the control channel. |
| US10958398B2 |
Method and system for multi-carrier packet communication with reduced overhead
A method and system for minimizing the control overhead in a multi-carrier wireless communication network that utilizes a time-frequency resource is disclosed. In some embodiments, one or more zones in the time-frequency resource are designated for particular applications, such as a zone dedicated for voice-over-IP (VoIP) applications. By grouping applications of a similar type together within a zone, a reduction in the number of bits necessary for mapping a packet stream to a portion of the time-frequency resource can be achieved. In some embodiments, modular coding schemes associated with the packet streams may be selected that further reduce the amount of necessary control information. In some embodiments, packets may be classified for transmission in accordance with application type, QoS parameters, and other properties. In some embodiments, improved control messages may be constructed to facilitate the control process and minimize associated overhead. |
| US10958391B2 |
Tone plans for wireless communication networks
Methods and apparatuses for communicating over a wireless communication network are disclosed herein. One example apparatus includes a memory that stores instructions. The apparatus further includes a processor coupled with the memory. The processor and the memory are configured to determine a total bandwidth for a transmission of a message, the total bandwidth including a plurality of tones. The processor is further configured to divide the plurality of tones in the total bandwidth into one or more 26-, 52-, 106-, 242-, or 996-tone blocks. The processor is further configured to determine an indication. The indication assigns one or more of the one or more tone blocks to a first wireless communication device. The apparatus further includes a transmitter configured to transmit the indication to at least the first wireless communication device or a second device. |
| US10958389B2 |
Method and system for providing diversity in a network that utilizes distributed transceivers with array processing
A communication device that comprises a plurality of distributed transceivers, a central processor and a network management engine may be configured based on one or more diversity modes of operations. The diversity modes of operations may comprise a spatial diversity mode, a frequency diversity mode, and/or a polarization diversity mode. Diversity mode configuration may comprise forming, based on selected diversity mode, a plurality of communication modules from the plurality of distributed transceivers, wherein each of the plurality of communication modules may comprise one or more antennas and/or antenna array elements, and one or more of said plurality of distributed transceivers associated with said one or more antennas and/or antenna array elements. The plurality of communication modules may be utilized to concurrently communicate multiple data streams. The multiple data streams may comprise the same data. |
| US10958388B2 |
Method and apparatus for transmitting data using a multi-carrier in a mobile communication system
The present invention relates to a method and apparatus for transmitting data using a multi-carrier in a mobile communication system. The method of transmitting data in user equipment of a wireless communication system using a carrier aggregation technique according to an embodiment of the present invention includes the steps of setting secondary cells included in an S-TAG (Secondary-Timing Advance Group) configured of only secondary cells (SCells), deactivating a downlink timing reference cell in the S-TAG; determining whether other activated secondary cells exist besides the deactivated downlink timing reference cell in the S-TAG, and when the other activated secondary cells exist in the S-TAG, setting one of the other activated secondary cells as a new downlink timing reference cell. According to the present invention, uplink transmission speed can be increased in the user equipment and user QoS can be improved by transmitting data using one or more uplink carriers in the terminal. |
| US10958385B2 |
Method and system for supporting multiple hybrid automatic repeat request processes per transmission time interval
A method and apparatus may be used for supporting multiple hybrid automatic repeat request (H-ARQ) processes per transmission time interval (TTI). A transmitter and a receiver may include a plurality of H-ARQ processes. Each H-ARQ process may transmit and receive one TB per TTI. The transmitter may generate a plurality of TBs and assign each TB to a H-ARQ process. The transmitter may send control information for each TB, which may include H-ARQ information associated TBs with the TBs. The transmitter may send the TBs using the associated H-ARQ processes simultaneously per TTI. After receiving the TBs, the receiver may send feedback for each of the H-ARQ processes and associated TBs indicating successful or unsuccessful receipt of each of the TBs to the transmitter. The feedback for multiple TBs may be combined for the simultaneously transmitted H-ARQ processes, (i.e., TBs). |
| US10958384B2 |
Method for transmitting HARQ-ACK signal in wireless communication system, and apparatus therefor
The present invention discloses a method for a terminal receiving re-transmitted data in a wireless communication system. In particular, the method may comprise the steps of: receiving from a base station a plurality of transport blocks that include a plurality of code block groups; the respective code block groups mapping and transmitting first HARQ-ACK signals with respect to the respective plurality of code block groups on the basis of an order in which the respective plurality of transport blocks are received, and an order that is included in the respective plurality of transmission blocks; and receiving one or more code block groups that are re-transmitted based on the transmitted first HARQ-ACK signals. |
| US10958383B2 |
Time based redundancy version determination for grant-free signaling
Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to methods and apparatus for rate-matching a stream of bits encoded using polar codes. An exemplary method generally includes determining, based on a time of a transmission, a redundancy version (RV) of data to be transmitted in the transmission and transmitting the determined RV of the data via a wireless medium at the time. |
| US10958381B2 |
Uplink signal transmission method and user equipment, and uplink signal reception method and base station
A base station receives uplink data and a first demodulation reference signal (DMRS) in a physical multiple access (MA) resource, and attempts to decode the uplink data, using the first DMRS. When the base station fails to decode the uplink data, the base station transmits an ACK/NACK for a first MA signature corresponding to the first DMRS among multiple MA signatures. When the ACK/NACK for the first MA signature is a NACK and the received power level of the first DMRS is higher than or equal to a threshold, the base station transmits a MA signature reselection command for the first MA signature together with the ACK/NACK. When the ACK/NACK for the first MA signature is a NACK and the received power level of the first DMRS is lower than the threshold, the base station transmits a MA signature maintenance command for the first MA signature together with the ACK/NACK. |
| US10958380B2 |
Method of transmitting and receiving data channel for new radio and apparatus using the same
Provided is a method of transmitting and receiving a data channel for the next-generation/5G radio access network. The method may include: receiving setting information about a code block group (CBG) for retransmission of the data channel from a base station; and receiving downlink control information (DCI) including scheduling information about the data channel from the base station, wherein the DCI includes transmission direction information about the CBG. |
| US10958378B2 |
Method for communication apparatus processing an in-band emission interference signal when the communication apparatus operating in FDR mode tranceives signals using FDM manner
A method for a base station processing an in-band emission interference signal caused when the base station operating in a Full Duplex Radio (FDR) mode transceives signals using a Frequency Division Multiplexing (FDM) manner includes transmitting a downlink signal in a flexible downlink duration of an uplink band; and processing the in-band emission interference signal caused by transmission of the downlink signal in an uplink duration of the uplink band, wherein the processing of the in-band emission interference signal is performed by puncturing a corresponding resource of the uplink duration, wherein the resource on the downlink signal is transmitted is mirrored to the corresponding resource of the uplink duration from a Direct Current (DC) subcarrier as a reference. |
| US10958375B2 |
Transmitting apparatus and signal processing method thereof
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. |
| US10958373B2 |
Sequences for signaling acknowledgments and negative acknowledgements
A joint channel estimation and data detection technique for decoding an uplink control channel using resource elements that are redundant in acknowledgement and negative acknowledgement uplink control channel transmissions is disclosed. To improve the performance of a decoder, channel estimation can be performed using reference signals (pilot symbols) to determine the characteristics of a channel at given locations within a subframe. For some uplink control channel formats, however, there aren't dedicated locations for reference signals/symbols, and so channel estimation is not performed. Since the acknowledgement and negative acknowledgement resource elements may be identical, at identical locations within the two different types of messages, the mobile device can replace the resource elements at the redundant locations with reference signals, thus the receiver can perform channel estimation using the reference signals, which can improve the performance of decoding the rest of the acknowledgement, negative acknowledgement transmission. |
| US10958372B2 |
Radio link adaptation in communication systems
Method, preferably implemented in a transmission node (81, 91, 11), for performing link adaptation of a radio link (106, 108, C1), comprising: determining (72) an estimation error of an estimated quality of the radio link (106, 108, C1), adapting (74) a Modulation and/or Coding Scheme, referred to as MCS, decision input value, which is based on the estimated quality of the radio link, by increasing the MCS decision input value if the determined estimation error exceeds a predetermined threshold, selecting (75) a MCS based on the MCS input value as adapted. |
| US10958371B2 |
System and methods for coherent PON architecture and burst-mode reception
An optical network communication system utilizes a passive optical network including an optical hub having an optical line terminal, downstream transmitter, an upstream receiver, a processor, and a multiplexer. The upstream receiver includes a plurality of TWDMA upstream subreceivers. The system includes a power splitter for dividing a coherent optical signal from the optical hub into a plurality of downstream wavelength signals, a long fiber to carry the coherent optical signal between the optical hub and the power splitter, and a plurality of serving groups. Each serving group includes a plurality of optical network units configured to (i) receive at least one downstream wavelength signal, and (ii) transmit at least one upstream wavelength signal. The system includes a plurality of short fibers to carry the downstream and upstream wavelength signals between the power splitter and the optical network units, respectively. Each upstream subreceiver receives a respective upstream wavelength signal. |
| US10958370B2 |
Optical repeater and control method for optical repeater
In order to provide a compact and low power consumption optical repeater capable of amplifying a plurality of wavelength ranges, the optical repeater is provided with: an excitation means which generates excitation light in a single wavelength range; a first light amplification means which is excited by the excitation light and the amplification band of which is a first wavelength range; and a second light amplification means which is excited by the excitation light and the amplification band of which is a second wavelength range different from the first wavelength range. |
| US10958368B2 |
Telecommunications apparatus and methods
A wireless telecommunication system includes base stations for communicating with terminal devices. One or more base stations support a power boost operating mode in which a base station's available transmission power is concentrated in a subset of its available transmission resources to provide enhanced transmission powers as compared to transmission powers on these transmission resources when the base station is not operating in the power boost mode. A base station establishes an extent to which one or more base stations in the wireless telecommunications system support the power boost operating mode conveys an indication of this to a terminal device. The terminal device receives the indication and uses the corresponding information to control its acquisition of a base station of the wireless telecommunication system, for example by taking account of which base stations support power boosting and/or when power boosting is supported during a cell attach procedure. |
| US10958366B2 |
Method of recording a forthcoming telebroadcast program
Method of recording a program, a broadcasting of which is advertised by a trailer, the recording method comprising the steps: of continuously recording a telebroadcast program while it is being viewed by the user while preserving the recording at least over a recording period preceding a present viewing instant; when the trailer of the forthcoming telebroadcast program is broadcast, of receiving a recording request signal; of analyzing the recording of the telebroadcast program while it is being viewed over the recording period preceding the reception of the recording request signal so as to obtain programming parameters; of recording the forthcoming telebroadcast program by using the programming parameters. |
| US10958355B2 |
Optical receiver circuit
An optical receiver circuit includes an input terminal receiving current signal from photodetector; a trans-impedance amplifier converting the current signal into voltage signal; an inductor having one end connected to the input terminal and another end connected to the input of the trans-impedance amplifier; a first variable resistor having a first end connected to the other end of the inductor, a second end receiving bias voltage, and a third end receiving a control signal, where the first variable resistor varies a resistance between the first end and the second end in accordance with the control signal; and a second variable resistor having a first end connected to the one end of the inductor, a second end receiving bias voltage, and a third end receiving a control signal, where the second variable resistor varies a resistance between the first end and the second end in accordance with the control signal. |
| US10958349B2 |
Virtual subscriber line terminal station device and control method for virtual subscriber line terminal station device
A virtual subscriber line terminal station device includes a software component including software to be added in accordance with a service requirement; and hardware having general-purpose functions; wherein the hardware includes a communication unit that receives a bandwidth allocation request transmitted by a subscriber line termination device; and the software component includes a bandwidth allocation component. The bandwidth allocation component has an individual unit that, based on an algorithm for allocating bands, computes a bandwidth to be allocated to the subscriber line termination device that transmitted the bandwidth allocation request; a common unit that, in accordance with the bandwidth allocated by the individual unit, allocates the bandwidth to the subscriber line termination device; and an interface between the individual unit and the common unit. The common unit converts the bandwidth allocation request received by the communication unit to a format that can be used by the individual unit. The individual unit computes the bandwidth to be allocated to the subscriber line termination device that transmitted the bandwidth allocation request that is converted, by the common unit, to a format that can be used by the individual unit. |
| US10958348B2 |
Method for manufacturing modular multi-function active optical cables
A method of making modular multi-function active optical cables (AOC) that enables multiple functions with minimal non-recurring engineering is described herein. In a non-limiting embodiment, one or more modular boards may be assembled into an assembly at a first end and a second end of the modular multi-function active optical cable, where each modular board may include at least a first connector. An electrical connector may be connected to the assembly using an interface to connect the electrical connector to the first connector associated with each module board. A hybrid cable assembly then may be connected between the assembly at the first end and the second, where the hybrid cable assembly includes one or more optical fibers and one or more electrical conductors. |
| US10958347B2 |
Full duplex bidirectional transmission on coaxial cable in CATV network
Systems and methods for achieving full duplex bidirectional transmission across coaxial cable in a hybrid fiber-coaxial cable TV network. Some preferred systems and method will attenuate reflections propagated within the coaxial cable. Other preferred systems may echo-cancel reflections propagated within the coaxial cable. |
| US10958344B2 |
Interference suppression with mitigation of intermodulation distortion
A method of interference suppression with intermodulation distortion mitigation includes processing an RF signal comprising an RF signal of interest and an RF interfering signal to produce a first and second RF drive signal each with a desired RF interference signal power and having a 90 degree relative phase. The first RF drive signal is imposed onto a first optical signal with a modulator to generate a first modulated optical signal so that the modulator has a large-signal behavior that is characterized by a Bessel function of the first kind J1(ϕ), wherein the desired power at a frequency of the interference signal of the first drive signal is chosen to correspond to a zero of the Bessel function of the first kind J1(ϕ). The second RF drive signal is imposed onto a second optical signal with a modulator to generate a second modulated optical signal so that the modulator has a large-signal behavior that is characterized by a Bessel function of the first kind J1(ϕ), wherein the desired power at a frequency of the interference signal of the second drive signal is chosen to correspond to another zero of the Bessel function of the first kind J1(ϕ). The first and second modulated optical signal are combined with an optical power ratio that is selected to suppress third-order intermodulation distortion products in an electrical signal generated by detecting the optically combined first and second modulated optical signals. |
| US10958343B1 |
Method and apparatus for distortion correction in optical communication links
In some embodiments, an apparatus includes an optical transmitter module that can be electrically coupled to an electrical serializer/deserializer and a controller. The optical transmitter module can include an electrical detector that can receive an in-band signal. The electrical detector can send to the controller a first power error signal and a second power error signal based on the in-band signal. The controller can send a correction control signal to the electrical serializer/deserializer based on the first power error signal and the second power error signal such that the electrical serializer/deserializer sends a pre-emphasized signal to the optical transmitter module based on the correction control signal. In such embodiments, the first power error signal, the second power signal and the correction control signal are out-of-band signals. |
| US10958342B1 |
Method and system for managing interference caused by rogue node in optical camera communication network
A method and system for identifying and mitigating interference caused by a rogue transmission source in an Optical Camera Communication (OCC) network is disclosed. The method includes receiving information from a plurality of transmission sources. Each of the plurality of transmission sources is within a capture area of a camera. Each of the plurality of transmission sources comprises a set of light sources configured to display one of a plurality of color codes. The method further includes detecting, through the camera, an interference between a serving transmission source associated with the camera and a non-serving transmission source. The serving transmission source belongs to the plurality of transmission sources. The method further includes establishing the non-serving transmission source as the rogue transmission source, when the non-serving transmission source is not registered with a master coordinator within the OCC network. |
| US10958336B2 |
Phased array antenna for use with low earth orbit satellite constellations
Examples disclosed herein relate to a phased array antenna system for use with a Low Earth Orbit (“LEO”) satellite constellation. The phased array antenna system has a plurality of antenna panels positioned in a dome and an antenna controller to control the plurality of antenna panels, the controller directing a first antenna panel to transmit a first signal and a second antenna panel to transmit a second signal to a LEO satellite, the first signal having a first phase and the second signal having a second phase different from the first phase. |
| US10958334B1 |
Routing for non-geostationary orbit (NGSO) satellite systems
A Non-Geostationary Satellite Orbit (NGSO) satellite system is described that implements one or more user route tables and a plurality of pre-calculated backbone route tables at its satellites. The user route tables track user connectivity to the satellites, and each of the backbone route tables defines a snapshot of a time-varying backbone topology seen by a particular satellite. During operation, a satellite selects different backbone route tables as the topology changes over time, and receives updates to the user route tables when connectivity changes occur between the users and the satellites. The decoupling of the user route tables from the backbone route tables at the satellite reduces the computational burden on the NGSO system, as the backbone route tables are calculated in advance and the NGSO system is subsequently tasked with a computationally lower burden of performing real-time updates to the user route tables. |
| US10958333B2 |
Apparatus and method for performing relay communication in wireless communication system
The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method and apparatus for performing a relay communication are provided. A remote user equipment (UE) according to the present disclosure is configured to acquire a first parameter related to relay load from each of a plurality of relay candidate UEs, to select a relay UE which will perform a relay communication with the remote UE from among the plurality of relay candidate UEs based on the first parameter acquired from each of the plurality of relay candidate UEs, and to perform the relay communication with the selected relay UE. The first parameter is generated based on cellular communication load between a base station (BS) connected to a corresponding relay candidate UE and the corresponding relay candidate UE. |
| US10958332B2 |
Wi-Fi hotspot repeater
WiFi repeater devices described provided herein. An example device includes an enclosure that is configured to be mounted to a window that divides an outdoor area from an indoor area. The enclosure houses a 5 GHz WiFi client radio coupled with a high order MIMO (multiple input, multiple output) antenna, the high order MIMO antenna transmitting and receiving data from a 5 GHz access point located in the outdoor area, and a 2.4 GHz WiFi access point radio coupled with a MIMO (multiple input, multiple output) antenna, the MIMO antenna transmitting and receiving data from 2.4 GHz UEs located in the indoor area. |
| US10958330B2 |
Apparatus and method for estimating direction in wireless communication system
A communication system is provided. The communication system supports higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A first apparatus in a wireless communication system is provided. The apparatus includes an antenna array, at least one transceiver, and at least one processor. The transceiver is configured to transmit signals by using a beam set, and receive a signal for indicating at least one beam in the beam set from a second apparatus. The processor is configured to determine an auxiliary beam pair, based on the at least one beam. The transceiver is configured to transmit reference signals to the second apparatus by using the auxiliary beam pair, and receive feedback information relating to the auxiliary beam pair from the second apparatus. The at least one processor is configured to determine, based on the feedback information, a communication direction relating to the second apparatus. |
| US10958323B1 |
MIMO radar system with dual mode output power amplification
An automotive radar system that is switchable between one or more high power modes and one or more increased channel modes. The radar system includes multiple transmit antennas, an integrated circuit including a transmit chain generating a positive transmit signal and a negative transmit signal that together form a differential transmit signal, and a coupling interface. The coupling interface configurably couples the differential transmit signal to two transmit antennas of the multiple transmit antennas to selectively drive the two transmit antennas in either a differential mode or in a power-combining mode that combines power from the positive transmit signal and negative transmit signal to drive a first transmit antenna of the multiple transmit antennas while isolating a second transmit antenna of the two transmit antennas. |
| US10958319B2 |
Receiving method and receiving apparatus
All data symbols used in data transmission of a modulated signal are precoded by switching between precoding matrices so that the precoding matrix used to precode each data symbol and the precoding matrices used to precode data symbols that are adjacent to the data symbol along the frequency axis and the time axis all differ. A modulated signal with such data symbols arranged therein is transmitted. |
| US10958312B2 |
MIMO antenna module and MIMO antenna unit for distributed antenna system
An embodiment of an antenna module includes a substrate, a first antenna, and a second antenna. The first antenna is disposed on the substrate and is configured to radiate a first signal having a wavelength and a first polarization. And the second antenna is disposed on the substrate and is configured to radiate a second signal having the wavelength and a second polarization that is approximately orthogonal to the first polarization. For example, such an antenna module can include, as the first antenna, a T antenna configured to transmit and receive data that forms a first part of a MIMO-OFDM data symbol, and can include, as the second antenna, an F antenna configured to transmit and receive data that forms a second part of the MIMO-OFDM data symbol. |
| US10958309B2 |
Systems, methods and apparatuses for prevention of relay attacks
The systems, methods and apparatuses described herein provide an apparatus configured for preventing relay attacks on a communication link between the apparatus and a communication partner. The apparatus may comprise a communication port, a timer and a processor. The processor may be configured to generate a request, transmit the request through the communication link using the communication port and start counting time using the timer, receive a response via the communication port and stop the timer, receive authentication data via the communication port, authenticate the authentication data, compare the counted time with a predefined threshold, compare a first field within the request with a second field within the response and determine whether there is a relay attack. |
| US10958307B2 |
Directional coupling device and methods for use therewith
Aspects of the subject disclosure may include, for example, a coupling device including a first antenna that radiates a first RF signal conveying first data; and a second antenna that radiates a second RF signal conveying the first data from the at least one transmitting device. The first RF signal and second RF signal form a combined RF signal that is bound by an outer surface of a transmission medium to propagate as a guided electromagnetic wave substantially in a single longitudinal direction along the transmission medium. Other embodiments are disclosed. |
| US10958305B2 |
Communication terminal and communication method
A wireless communication terminal apparatus wherein CoMP communication can normally be performed without increasing the overhead of an upstream line control channel. In this apparatus, a spreading unit primarily spreads a response signal by use of a ZAC sequence established by a control unit. A spreading unit secondarily spreads the response signal, to which CP has been added, by use of a block-wise spread code sequence established by the control unit. The control unit controls, in accordance with sequence numbers and a hopping pattern established therein, the circular shift amount of the ZAC sequence to be used for the primary spread in the spreading unit and the block-wise spread code sequence to be used for the secondary spread in the spreading unit. The hopping pattern established in the control unit is a hopping pattern common to a plurality of base stations that CoMP-receive the response signal. |
| US10958303B2 |
Spreading a response signal using a first set of orthogonal sequences and a reference signal using a second set of shorter orthogonal sequences
A radio communication apparatus includes spreading circuitry that spreads a response signal using a first set of orthogonal sequences to produce a spread response signal. Each orthogonal sequence in the first set has a first length. The spreading circuitry also spreads a reference signal using a second set of orthogonal sequences to produce a spread reference signal. Each orthogonal sequence in the second set has a second length that is shorter than the first length. A radio transmitter transmits the spread response signal and the spread reference signal. |
| US10958297B2 |
Interference mitigation in a communications network
There is provided mechanisms for mitigating interference in a communications network. A method is performed by a network node. The method comprises obtaining a packet. The packet has been wirelessly received in an uplink direction by a transmission and reception point of the network node and from a packet sender. The packet is indicative of scheduled transmission of a further packet within a predefined time interval from the transmission and reception point has wirelessly received the packet. The method comprises determining beamforming weights such that interference caused by transmission from the transmission and reception point of the network node in a downlink direction being reversed to the uplink direction is less than a threshold interference value. The method comprises initiating transmission in at least one beam using the determined beamforming weights. The beamforming weights are used for the transmission at least within the predefined time interval. |
| US10958291B2 |
Transmission method and reception device
The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like. |
| US10958290B2 |
Location of interleaver with LDPC code
Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data. |
| US10958288B2 |
Decoder for low-density parity-check codes
Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P≥PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits. |
| US10958285B2 |
Dynamic voltage reference for delta-sigma analog-to-digital converter (ADC) with temperature trim calibration
A calibratable switched-capacitor voltage reference and an associated calibration method are described. The voltage reference includes dynamic diode elements providing diode voltages, input capacitor(s) for sampling input voltages, base-emitter capacitor(s) for sampling one diode voltage with respect to a ground, dynamically trimmable capacitor(s) for sampling the one diode voltage with respect to another diode voltage, and an operational amplifier coupled to the capacitors for providing reference voltage(s) based on the sampled input and diode voltages and on trims of the trimmable capacitor(s). The voltage reference can be configured as a first integrator of a modulator stage of a delta-sigma analog-to-digital converter. |
| US10958283B2 |
AD conversion circuit, imaging device, and endoscope system
An AD conversion circuit includes a comparison circuit, a first DA conversion circuit including a plurality of resistance elements, and a first voltage output circuit. A comparator of the comparison circuit outputs a signal that represents a result of comparing a first voltage of a first input terminal with a second voltage of a second input terminal. A first combined resistance value of the first DA conversion circuit and the first voltage output circuit seen from a second terminal of the first capacitance element is a first value when the first capacitance element holds a first signal. The first combined resistance value is a second value when the comparator compares the first voltage with the second voltage. The first value is less than the second value. |
| US10958281B1 |
Analog-to-digital convertor (ADC) with a synthesized delay stage
Embodiments may relate to a circuit for use in an analog-to-digital converter (ADC) circuit. The circuit may include a first residue amplifier stage and a second residue amplifier stage. The circuit may further include a synthesized delay stage with a digital-to-analog converter (DAC) electrically positioned between a signal input and the input of the second residue amplifier stage. The circuit may further include a resistor electrically positioned between the signal input and the input of the second residue amplifier stage. Other embodiments may be described or claimed. |
| US10958278B2 |
Techniques in phase-lock loop configuration in a computing device
Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency. |
| US10958276B2 |
Digital phase locked loop for low jitter applications
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. |
| US10958270B2 |
Physical unclonable device and method of maximizing existing process variation for a physically unclonable device
A physically unclonable function (PUF) device and a method for maximizing existing process variation for a physically unclonable device are provided. The method of maximizing process variation of the PUF device includes: modeling a physically unclonable function (PUF) device, comprising a plurality of PUF cells, selecting the size of transistors in the PUF device to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells, varying the material of the PUF device, and driving the PUF device with a predetermined voltage. The physically unclonable device includes: a plurality of PUF cells, configured to generate an output. Each of the plurality of PUF cells includes a harvester circuit, configured to generate a bit line and a complementary bit line. The harvester circuit is selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells; and a sense amplifier having a plurality of transistors configured to receive a first input signal and a second input signal from the harvester circuit. |
| US10958267B2 |
Power-on clear circuit and semiconductor device
A power-on clear circuit includes a first inverter unit including a constant current transmission unit having one end supplied with a first power supply voltage, and a first transistor having a first terminal connected to a second line kept at a fixed potential, a second terminal connected to the other end of the constant current transmission unit, and a control terminal receiving application of a second power supply voltage which varies to follow the first power supply voltage; a second inverter unit that operates on the basis of the first power supply voltage, and to which a potential of a first node is input, the first node is connected between the other end of the constant current transmission unit and the first terminal of the first transistor; and a signal outputting unit that outputs a power-on clear signal in accordance with an output of the second inverter unit. |
| US10958264B2 |
Circuit system for controlling an electrical consumer
A circuit system for controlling an electrical consumer, the circuit system including an up-down counter, and the circuit system being configured to generate a control signal for controlling the electrical consumer, in particular for shutting off the electrical consumer, as a function of a counter content of the up-down counter. The circuit system includes a controllable clock divider circuit, with the aid of which the circuit system is configured to predefine a counting direction and a counting speed of the up-down counter as a function of at least one variable characterizing an actual current and/or a nominal current of the electrical consumer. |
| US10958259B2 |
Pulse width modulation output stage with dead time control
A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code. |
| US10958257B1 |
System and method for adjusting duty cycle of a signal
A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output. |
| US10958256B1 |
Fifty percent duty cycle detector and method thereof
A fifty percent duty cycle detector includes a single-ended-to-differential converter (S2D) configured to receive a first clock and output a second clock and a third clock that are complementary; a controllable swap circuit configured to receive the second clock and the third clock and output a fourth clock and a fifth clock in accordance with a logical control signal; a time-to-digital converter (TDC) configured to receive the fourth clock and the fifth clock and output a digital word; and a finite state machine configured to receive the digital word and output the logical control signal and a ternary decision. |
| US10958250B2 |
Semiconductor device
A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together. |
| US10958245B2 |
Acoustic filter using acoustic coupling
A filter circuit includes a first input node and a second input node for receiving an input signal, and a first output node and a second output node for providing an output signal. A first series acoustic resonator is coupled in series between the first input node and the first output node. At least one coupled resonator filter (CRF) includes first and second transducers, which may be acoustically coupled to one another. The first transducer has a first electrode coupled to the first input node, a second electrode coupled to the second input node, and a first piezoelectric layer between the first electrode and the second electrode. A second transducer has a third electrode coupled to the first output node, a fourth electrode coupled to the second output node, and a second piezoelectric layer between the third electrode and the fourth electrode. |
| US10958243B2 |
Filter including bulk-acoustic wave resonator
A filter includes a plurality of series portions each including one or more series resonators, and a plurality of shunt portions each including one or more shunt resonators. At least one of the plurality of shunt portions includes two shunt resonators connected to each other in anti-series, and antiresonance frequencies of the two shunt resonators are arranged externally of a passband. |
| US10958241B2 |
Extractor
An extractor includes a band pass filter and a band elimination filter. In the band pass filter, an IDT electrode in at least one of a first series arm resonator and a first parallel arm resonator that are arranged at a series arm and a parallel arm, respectively, closest to a common terminal is a first IDT electrode in which neither a plurality of first electrode fingers nor a plurality of second electrode fingers is partially missing, and an IDT electrode in at least one of the first series arm resonator or the first parallel arm resonator that does not include the first IDT electrode, second series arm resonators, and second parallel arm resonators is a second IDT electrode in which at least one of a plurality of electrode fingers and a plurality of second electrode fingers is partially missing. |
| US10958236B2 |
Hybrid acoustic wave resonator and preparation method therefor
A hybrid acoustic resonator. An interdigital electrode is provided in a first region of a surface of a piezoelectric film facing away from a substrate, and forms an interdigital transducer. At least two trenches are provided in a second region of the surface of the piezoelectric film facing away from the substrate. A bulk-acoustic-wave propagation portion is formed between adjacent trenches. A bulk-acoustic-wave electrode is provided on a side surface of the bulk-acoustic-wave propagation portion, and there is an air gap at a surface of the bulk-acoustic-wave electrode facing away from the bulk-acoustic-wave propagation portion. Thereby, the hybrid acoustic resonator includes both the surface acoustic resonator and the bulk acoustic resonator. An acoustic wave in the bulk-acoustic-wave propagation portion and an acoustic wave in the interdigital transducer are both transmitted along a transversal direction. |
| US10958233B2 |
Common mode filter
Disclosed herein is a common mode filter that includes a winding core part and first and second wires wound in a same direction around the winding core part. A predetermined one turn of the first wire crosses a predetermined one turn of the second wire a plurality of times. |
| US10958232B2 |
LC filter
Disclosed herein is an LC filter that includes a conductive substrate, a first capacitive insulating film having one surface covered with the conductive substrate and other surface covered with a first capacitive electrode, a first inductor pattern having one end connected to the first capacitive electrode, a first terminal electrode connected to other end of the first inductor pattern, and a common terminal electrode connected to the conductive substrate. |
| US10958228B2 |
Dynamically adjusting common mode rejection ratio
A circuit having a dynamically adjustable common mode rejection ratio. The circuit has a high common mode rejection ratio without the need for input transformers. The circuit's ability to adjust the circuit's common mode rejection ratio is enhanced by the circuit's high input impedance. The circuit includes first and second input terminals, and output terminals. A positive leg runs from the first input terminal to the first output terminal, the positive leg including a resistor, and a negative leg runs from an input terminal to an output terminal. The digital signal processor controls a potentiometer on one of the legs to dynamically adjust the common mode rejection ratio of the circuit. |
| US10958224B2 |
Method and device for providing a bias voltage in transceivers operating in time division multiplexing operation
Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver. |
| US10958223B2 |
Amplifier
There has been a problem that linearity is degraded in the conventional amplifier when the idle current is reduced in order to lower the power consumption.An amplifier of the present invention includes: a bias circuit to cause a bias current to flow; an amplifying element to amplify a signal by causing an output current corresponding to the bias current to flow; a bias current subtracting circuit to detect the signal and subtract, from the bias current, a current based on an amplitude of the signal detected; and a bias current adding circuit having an operation starting point higher than an operation starting point of the bias current subtracting circuit, and to detect the signal and add, to the bias current, a current based on an amplitude of the signal detected. |
| US10958216B2 |
Semiconductor device and operation method thereof
A device is disclosed that includes a semiconductor substrate, a bottom electrode disposed on a first surface of the semiconductor substrate, an insulating layer disposed on a second surface that is opposite to the first surface, of the semiconductor substrate, a current-to-voltage converter, a first electrode and a second electrode that are separate from each other and disposed on the insulating layer. The first electrode is configured to be applied with an input signal, and the second electrode is configured to output an output current signal that is associated with the input signal, the input signal is configured to have a voltage level that is variable, and the output current signal is configured to have a peak current value and a valley current value. The current-to-voltage converter is configured to receive the output current signal to generate an output voltage signal. |
| US10958214B2 |
Phase noise reduction in voltage controlled oscillators
A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices. |
| US10958213B2 |
Pullable clock oscillator
A clock oscillator includes with a pullable BAW oscillator to generate an output signal with a target frequency. The BAW oscillator is based on a BAW resonator and voltage-controlled variable load capacitance, responsive to a capacitance control signal to provide a selectable load capacitance. An oscillator driver (such as a differential negative gm transconductance amplifier), is coupled to the BAW oscillator to provide an oscillation drive signal. The BAW oscillator is responsive to the oscillation drive signal to generate the output signal with a frequency based on the selectable load capacitance. The oscillator driver can include a bandpass filter network with a resonance frequency substantially at the target frequency. |
| US10958211B1 |
Systems and methods for power management
Devices and methods for providing a mobile source of power for many different types of situations are provided. A portable emergency alternating current (AC) energy (PEACE) Supplier can serve as a mobile source of power for users with photovoltaic (PV) and/or energy storage systems during power outage situations caused by normal or extreme scenarios. A Supplier can also be used to provide power when weather conditions result in insufficient solar energy for the user's needs. |
| US10958208B2 |
Photovoltaic module mounting assembly having a pin constraint
A mounting assembly for a photovoltaic (PV) module, and systems including such mounting assemblies, are described. In an example, the mounting assembly includes a top support and a bottom support having respective mounting walls, and holes through the mounting walls. A pin assembly may extend through the holes in the mounting walls to constrain the supports, for example, relative to a torque member of a solar-tracking PV system. The pin assembly may include end collars to engage and distribute loading from the torque member. |
| US10958203B2 |
Method for calibrating frequency of driving voltage waveform for linear resonance device and related device
There are provided a method, a system and a device for calibrating a frequency of a driving voltage waveform for a linear resonance device. An actual sampling frequency is continuously corrected, so that a difference between a measured natural frequency of the linear resonance device obtained during a calibration process and a frequency of a standard driving voltage waveform stored in a driving chip for the linear resonance device is in a predetermined range. The driving chip outputs a driving waveform at a finally corrected actual sampling frequency, to drive the linear resonance device. Further, only an actual sampling frequency is required to be adjusted, and it is not required to modify waveform data stored in the driving chip for the linear resonance device. |
| US10958200B1 |
System and method for operating a wind turbine power system during low wind speeds to improve efficiency
A method for operating a wind turbine power system that supplies real and reactive power to a grid includes operating a generator of the wind turbine power system up to a first speed limit. The method also includes monitoring a wind speed at the wind turbine power system. When the wind speed drops below a predetermined threshold, the method includes reducing the first speed limit of the generator to a reduced speed limit of the generator. Further, the method includes operating the generator at the reduced speed limit for as long as the wind speed remains below the predetermined threshold so as to optimize a tip-speed-ratio of the wind turbine power system during low wind speeds, thereby increasing power production of the wind turbine power system at low wind speeds. |
| US10958199B2 |
Movement, electronic timepiece, and motor drive control method
Provided is a motor drive circuit capable of driving a stepper motor even if the load on the stepper motor varies. A motor drive circuit has a first drive circuit that outputs a first drive signal to the driver; a second drive circuit that outputs a second drive signal to the driver; a controller that controls the first drive circuit and second drive circuit. The first drive circuit is configured to output a first drive signal based on the current value of current flow of a coil of a stepper motor. The second drive circuit is configured to output multiple types of second drive signals that differ by the supply time of drive current supplied to the coil. Based on a result of driving by the first drive circuit, the controller selects the type of second drive signal the second drive circuit outputs. |
| US10958197B2 |
Motor drive circuit, method of controlling same, and storage medium
The technique of the present disclosure has an object to perform PWM control of DC motors with a CPU and a motor drive circuit connected by a smaller number of serial interfaces, and provides a motor drive circuit comprising: energization control units to switch the directions of energization of motors by using switching elements to be driven by PWM signals; a reception unit to receive data indicating energization of the motor and the duty ratio of the PWM signal for each energization control unit from a computation apparatus by serial communication; a first signal generation unit to generate a motor control signal for controlling energization of the motor and the duty ratio based on the data for each energization control unit; and a second signal generation unit to generate the PWM signal having the duty ratio set according to the corresponding motor control signal for each energization control unit. |
| US10958192B2 |
Energy conversion system and method
An energy conversion system comprises a generator which generates electrical power in response to movement, wherein the generator comprises first and second elements which generate energy in an energy generation mode. In some examples, these can be brought into and out of contact with each other by a drive mechanism so that the energy conversion system has an (e.g.) intermittent charging mode in which the first and second 5 elements are brought into contact by the drive mechanism and an energy generation mode in which the first and second elements are out of contact. The relative speed, the spacing between, or the relative orientations or positions of the first and second elements are controlled during the energy generation mode to decrease the variation in output power or voltage of the generator. This system controls the physical positions or the motion of the 10 elements of the generator during the energy generation mode in order to implement a more constant power or voltage generation. This enables any required power conversion circuitry to be simplified. |
| US10958186B2 |
Load control device for high-efficiency loads
A load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor (such as, a triac) coupled between the source and the load, a gate coupling circuit arranged to conduct current through a gate terminal of the thyristor, and a control circuit configured to control the gate coupling circuit. The control circuit may control the gate coupling circuit to conduct a pulse of current through the gate terminal to render the thyristor conductive at a firing time during a present half cycle of the AC power source, and allow the gate coupling circuit to conduct at least one other pulse of current after the firing time during the present half cycle. |
| US10958184B2 |
Uninterruptible power supply and method of operation
An uninterruptible power supply (UPS) is provided that includes a split direct current (DC) link having a first capacitor coupled between a positive DC link terminal and a first node, and a second capacitor coupled between the first node and a negative DC link terminal. The UPS also includes a rectifier coupled to an input of the split DC link and a controller coupled to the rectifier. The rectifier includes first, second, and third legs, wherein each leg is configured to convert a first alternating current (AC) voltage received from an AC source into a DC voltage to be provided to the split DC link, and a fourth leg configured to balance DC link voltages of the first and second capacitors. The controller is configured to maintain functionality of the rectifier during at least one of a partial utility power outage, a full utility outage, and a failure of at least one of the first, second, third, and fourth legs. |
| US10958180B2 |
DC-DC converter for wide input voltage
A DC-DC converter includes an inductor, a rectifier module, a first bridge arm topology and a second bridge arm topology and a third bridge arm topology in parallel as well as a capacitor, wherein the first bridge arm topology includes a first switching tube and a fourth switching tube in series, the second bridge arm topology includes a second switching tube and a fifth switching tube in series, and the third bridge arm topology includes a third switching tube and a sixth switching tube in series; the inductor has one end connected to a coupling point formed by connecting the first switching tube and the fourth switching tube in series, and the other end connected to a coupling point formed by connecting the second switching tube and the fifth switching tube in series. |
| US10958179B2 |
Reduced voltage switching of a main switch in flyback power converters
Reduced voltage switching of a main switch in flyback power converters. Example embodiments are methods including: driving a primary current with a first polarity in a primary winding of a transformer, and a secondary winding of the transformer arranged for flyback operation; creating, by the primary current, a charge voltage on an auxiliary winding of the transformer; charging, by the charge voltage, a capacitance coupled to the auxiliary winding; ceasing the driving of the primary current and discharging an energy in a field associated with the secondary winding to provide an output voltage of the power converter; inducing a primary current with a second polarity in the primary winding by coupling the capacitance to the auxiliary winding; and reducing voltage across a main switch coupled to the primary winding, the reducing by the primary current with the second polarity. |
| US10958176B2 |
Systems and methods of CCM primary-side regulation
Example embodiments of the systems and methods of CCM primary-side regulation disclosed herein subtract an estimate of the secondary IR drop from each output voltage sample. This allows a fixed sample instant to be set (with regard to the beginning of the off or flyback interval), and removes the need to hunt for or adjust to an optimum sample instant, or one with minimum IR drop error. The estimate of the IR drop may be adjusted on a cycle-by-cycle basis, based on the commanded primary peak current, knowing that the peak secondary current will be directly proportional by the turns ratio of the transformer. For improved accuracy, an adjustment may be made for the decay of secondary current during the delay to the sample instant, if the inductance value is known. |
| US10958174B1 |
Light load detector circuit for inductive DC-DC converter
A power converter and method to detect a light load condition at an output of the power converter are presented. The power converter may have an inductor and a resistive element connected between an input of the power converter and an input of the inductor. The power converter may have a first chopping unit to generate a chopped voltage signal at an output of said first chopping unit, wherein the chopped voltage signal is generated by chopping an inductor voltage at the input of said inductor based on a duty cycle of the power converter. The power converter may have a reference current source, wherein the reference current source and a replica resistive element are arranged in series. The power converter may have a comparator unit to generate, based on the reference potential and based on the chopped voltage signal, a signal indicative of said light load condition. |
| US10958173B2 |
Fixed frequency buck-boost power converter control
The present disclosure provides for a processing element configured to couple to a first ramp generator and a second ramp generator and control the first ramp generator while a power converter is operating in a buck-boost mode of operation to generate a first ramp signal beginning at a first value and increasing to a second value during a first clock cycle and generate the first ramp signal beginning at the first value and increasing to a third value during a second clock cycle following the first clock cycle and control the second ramp generator while the power converter is operating in the buck-boost mode of operation to generate a second ramp signal beginning at a fourth value and decreasing to a fifth value during the first clock cycle and generate the second ramp signal beginning at the fourth value and decreasing to a sixth value during the second clock cycle. |
| US10958169B2 |
Power converter with robust stable feedback
A power converter includes an input node on an input side of the power converter, an output node on an output side of the power converter, a switch coupled to the input node and having a switch control node, an inductor coupled to the switch and to the output node, and a feedback compensation and control circuit between the output node and the switch control node. The feedback compensation and control circuit includes two or more programmable resistors to adjust one or more gains of i) a proportional-integral-derivative portion, and ii) a bandpass filter portion of the feedback compensation and control circuit. The feedback compensation and control circuit receives an output voltage from the output node and generates a compensated feedback signal based on the output voltage from the output node and the one or more gains, the switch control node being controlled based on the compensated feedback signal. |
| US10958167B2 |
Current sensing in an on-die direct current-direct current (DC-DC) converter for measuring delivered power
Current sensing in an on-die direct current-direct current (DC-DC) converter for measuring delivered power is disclosed. A DC-DC converter converts input voltage to output current at an output voltage coupled to a load circuit. The DC-DC converter includes a high side driver (HSD) circuit to drive the output current in a first stage, and a low side driver (LSD) circuit to couple the power output to a negative supply rail (GND) in a second phase, output current being periodic. The DC-DC converter includes an amplifier circuit to equalize an output voltage and a mirror voltage. Based on the mirror voltage, the current sensing circuit generates mirror current that corresponds to driver current. The mirror current can be measured as a representation of the output current delivered to the load circuit. A plurality of the DC-DC converters can provide multi-phased current to the load circuit for providing power to the load circuit. |
| US10958165B1 |
High-conversion-efficiency reconfigurable series-parallel switched-capacitor voltage converter
A high-conversion-efficiency reconfigurable series-parallel switched-capacitor voltage converter includes N−1 control units and is capable of realizing a voltage conversion ratio in a range from 1:1 to N:1 between a second conversion terminal and a first conversion terminal. When the voltage conversion ratio between the first conversion terminal and the second conversion terminal of the reconfigurable series-parallel switched-capacitor voltage converter is Nx:1, the N−1 control units are divided into k+1 control modules. k control switch tubes are configured to respectively correspond to the preceding k control modules. Each one of the preceding k control modules comprises m control units, and the last control module comprises t control units; m=Nx−1; k and t satisfy N−1=m×k+t; k and m are both 0 or are both positive integers; and t is as small as possible. |
| US10958156B2 |
Electronic circuit, power conversion device, driving device, vehicle, and elevator
Provided is a semiconductor device including: a semiconductor element including a first electrode, a second electrode, and a gate electrode; a surge voltage measuring unit electrically connected to the first electrode or the second electrode and configured to measure a surge voltage; a variable resistor electrically connected to the gate electrode; a comparator configured to compare a surge voltage measurement value, which is acquired by measuring the surge voltage generated by a first pulse applied to the gate electrode by the surge voltage measuring unit, with a surge voltage target value; a determination unit configured to determine a setting value of a resistance value of the variable resistor based on the comparison result by the comparator; and an instruction unit configured to instruct the setting value to the variable resistor. |
| US10958154B2 |
Wireless receiver rectifier low side current limited operation
In accordance with aspects of the present invention, a wireless power circuit is presented. In some embodiments, the wireless power circuit includes one or more high-side transistors; one or more low-side transistors coupled in series with the one or more high-side transistors, wherein the one or more low-side transistors can be controlled as current sources. |
| US10958151B2 |
Distributed control of a multiphase power converter
Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed. |
| US10958141B2 |
Air conditioning blower motor unit
Three substrate side terminal members are provided on a circuit substrate on which electronic components for controlling a brushless motor are disposed. Two of the substrate side terminal members protrude on a side in close proximity to bearing retaining members, and the remaining one substrate side terminal member protrudes on a side separated from the bearing retaining members. Ends of flexible wire members, the other ends of which are held in engagement with stator side terminal members, are held in engagement with the three substrate side terminal members. |
| US10958138B2 |
Motor
A motor includes a shaft that extends in an axial direction, a rotor including a field magnet, a stator, a resolver positioned farther toward one side of the motor in the axial direction than the rotor and the stator, and a shield including at least a portion is between the rotor and the resolver in the axial direction. The shield includes a bottom portion of which at least a portion is between the rotor and the resolver in the axial direction and which includes a through-hole through which the shaft passes, and a convex portion that extends from the bottom portion toward the other side in the axial direction. A front end portion of the convex portion is positioned farther toward an inner side of the motor in a radial direction than an outer circumferential portion of the field magnet when viewed in the axial direction. |
| US10958136B2 |
Drive apparatus
A drive apparatus includes a motor that includes a motor shaft disposed along a first central axis that extends in one direction, a housing that includes a first housing portion housing the motor and that is capable of storing oil, and a liquid cooling portion disposed in thermal contact with an inverter electrically coupled to the motor, the liquid cooling portion including a refrigerant liquid flowing therein. The housing includes a contact portion with which the liquid cooling portion is in thermal contact. At least a portion of the contact portion is disposed below an oil surface of the oil stored in the housing. |
| US10958134B2 |
Compact electric machine with combined rotor carrier and clutch housing
An electric machine includes a stator assembly, a rotor positioned within the stator assembly, and a rotor carrier coupled to the rotor. The rotor carrier includes a hub portion, a first cylindrical portion coupled to the hub portion and defining a first diameter that is less than an inner diameter of the rotor, and a second cylindrical portion extending from the first cylindrical portion and defining a second diameter that is greater than the inner diameter of the rotor. A first clutch is positioned within the rotor carrier and engages an inner surface of the first cylindrical portion of the rotor carrier. A second clutch is positioned within the rotor carrier and engages an inner surface of the second cylindrical portion of the rotor carrier. |
| US10958132B2 |
Motor and electric power steering device
A motor includes a heat sink including an inner region, and an outer region located radially outward from the inner region. An axial thickness of the inner region is larger than an axial thickness of the outer region, the bottom surface of the outer region is located axially above the bottom surface of the inner region, and the inner region and the electronic component at least partially overlap in an axial direction. A bus bar holder is located axially below the outer region and overlaps the inner region in a radial direction. |
| US10958130B2 |
Motor and electric power steering device
A motor includes a rotor, a stator, a housing, and a flange. The housing includes a first cylindrical portion, a contact portion extending radially inward from an axial lower end of the first cylindrical portion, a second cylindrical portion that extends axially downward from a radial inner edge of the contact portion and has a smaller outer diameter than the first cylindrical portion, and a bottom portion extending radially inward from an axial lower end of the second cylindrical portion. The flange includes a flange cylindrical portion, and a flange flat portion extending radially outward from an axial lower end of the flange cylindrical portion. The flange cylindrical portion is fixed to an outer surface of the second cylindrical portion and an upper end of the flange cylindrical portion contacts with an outside lower surface of the contact portion. |
| US10958126B2 |
Machine unit, component piece and intermediate element, and method for connecting and/or disconnecting a connection line
A machine unit, component piece and intermediate element, and method for connecting and/or disconnecting a connection line to/from a machine unit, wherein a region includes an intermediate element and a component piece is substantially enclosed between an electrical machine and a functional element of the machine element, where the component piece can be removed or folded away from the intermediate element, where after the component piece is removed from the intermediate element, the sheathed region is advantageously accessible for connection by way of a connection line, and where a transmitter, for example, is connectable via the connection line to permit connection of the connection line in the sheathed region without the functional element having to be removed such that an electrical machine that includes the functional element can also be serviced in locations that are difficult to access. |
| US10958119B2 |
Rotary electric machine, rotary electric machine system, and machine
A rotary electric machine in an embodiment includes a stator, and a rotor capable of rotating around a rotation center. The rotor includes a first rotor core, a second rotor core, and a magnet. The first rotor core includes first rotor magnetic poles that are arranged being spaced apart from one another in a circumferential direction and that face first stator magnetic poles, and is annular. The second rotor core includes second rotor magnetic poles that are arranged being spaced apart from one another in the circumferential direction and that face second stator magnetic poles, and is annular. The magnet is located between the first rotor core and the second rotor core and provided with a slit-like magnet separation portion that separates at least a part thereof in the circumferential direction, and is annular. |
| US10958110B2 |
Parallel voltage and current multiple amplitude shift key demodulation
Systems, methods and apparatus for wireless charging are disclosed. A method for decoding data includes demodulating voltage or current waveform in each tank circuit of a plurality of inductive power transfer circuits to obtain at least one demodulated signal from each tank circuit, capturing a bit sequence from each demodulated signal by clocking signal state of each demodulated signal through a direct memory access (DMA) circuit, streaming bit sequences received from the DMA circuit into a plurality of data streams, and decoding one or more messages from the plurality of data streams. |
| US10958109B2 |
Wireless power transmitter and receiver
A method in which a power transmitter comprising multi coils transmits wireless power, includes detecting a second power receiver while transmitting power to a first power receiver, determining at least one primary coil appropriate for power transmission, determining whether the second power receiver supports a shared mode protocol using the determined at least one primary coil, and transmitting, if the second power receiver supports a shared mode protocol, power to the first and second power receivers according to the shared mode protocol, wherein the shared mode protocol is a protocol that simultaneously manages information exchange between the power transmitter and a plurality of power receivers. |
| US10958107B2 |
Non-contact power supply device and non-contact power supply method
According to one embodiment, a non-contact power supply device includes an inverter circuit configured to convert power supplied from a direct current (DC) power supply into alternating current (AC) power, a resonant circuit configured to supply the AC power to an external power receiving device in a non-contact manner, a current sensor electrically connected the inverter circuit, a voltage subtractor circuit configured to detect a voltage difference between a predetermined reference voltage and a voltage value of the AC power as detected by a voltage sensor in the external power receiving device, a current subtractor circuit configured to detect a current difference between a predetermined reference current and a current value of the AC power as detected by the current sensor, and a controller configured to control the inverter circuit to reduce the voltage difference and the current difference when the voltage is outside a predetermined range. |
| US10958104B2 |
Inverter for inductive power transmitter
An inductive power transmitter comprising a plurality of autonomous resonant inverters, wherein each inverter outputs a voltage to a respective transmitter coil/coils for inductive power transfer; and a magnetic coupling structure between the respective transmitter coils, wherein the magnetic coupling structure is configured to determine a phase shift between the output voltage of each inverter. |
| US10958103B2 |
Stackable battery pack system with wireless charging
A rechargeable battery pack system includes a charging base and rechargeable battery packs. The charging base includes an electrical connector for receiving electrical power and a set of electrical contacts. The rechargeable battery packs each include a rechargeable battery, electrical circuitry, and an inductive coil for wirelessly transmitting power to an electronic device. The rechargeable battery packs each include a first set of electrical contacts to electrically contact the charging base for receiving electrical power from the charging base when the battery pack is stacked on top. The rechargeable battery packs further include a second set of electrical contacts for providing electrical power to another rechargeable battery pack when the other rechargeable battery pack is stacked on top. The second set of electrical contacts is activated for providing the electrical power to the other rechargeable battery pack only after receiving a proper identity code from the other rechargeable battery. |
| US10958102B2 |
Electromagnetic-inductive power supply apparatus
Disclosed is an electromagnetic-inductive power supply apparatus, which switches so that a plurality of coils winding around a current transformer core is connected in series to a rectification unit based on the voltage induced in the current transformer, thereby producing the power within the set range even in a state where the voltage outside the reference is induced. The disclosed electromagnetic-inductive power supply apparatus senses the voltage induced in the current transformer and switches the plurality of unit coils is connected to the rectification unit based on the voltage sensed. |
| US10958096B2 |
Power supply system
A power supply system including: a first battery connected to a first load; a second battery; a DC-DC converter connecting the first battery and the second battery; and a connection switching unit including a first switch configured to connect the first battery to a second load and a second switch configured to connect the second battery to the second load. The connection switching unit is configured to switch selectively to a first mode in which the first switch is closed and the second switch is opened and a second mode in which the first switch is opened and the second switch is closed. |
| US10958091B2 |
Power supply device
A power supply device comprises a first boost converter configured to transmit electric power with conversion of a voltage between an electric load side and a power storage device side; a second boost converter connected in parallel to the first boost converter relative to an electric load and configured to transmit electric power with conversion of a voltage between the electric load side and the power storage side; and a control device configured to control the first boost converter and the second boost converter. At a predetermined time, the control device performs a loop current control that controls the first boost converter and the second boost converter such that a loop current flows in a closed circuit including the first boost converter and the second boost converter. |
| US10958087B2 |
Battery protection system
A battery protection system with a voltage sensing circuit for sensing the voltage of a battery and disconnecting all loads from the battery, including the voltage sensing circuit itself, when the voltage of the battery drops below a preset limit or when a battery charger is connected to the battery. The battery protection system reconnects the voltage sensing circuit upon disconnection of the battery charger. |
| US10958080B2 |
Method and apparatus for transmitting wireless power
A method and apparatus are provided for operating a wireless power transmitter. The method includes controlling the wireless power transmitter to wirelessly transmit power for charging a first power receiver, and while transmitting the power, receiving a search signal from a second power receiver, transmitting a search response signal corresponding to the search signal, and receiving, from the second power receiver, a request join signal including at least one piece of information associated with a power requirement of the second power receiver. Based on identifying that the wireless power transmitter is capable of providing the power having an amount greater than the power requirement of the second power receiver, the method further includes transmitting a charge start command to the second power receiver. |
| US10958073B2 |
Reactive power control equipment and reactive power control method
The invention provides reactive power control equipment that controls the reactive power adjusted by a synchronous condenser coupled to an electric power grid and the reactive power of the electric power supplied to the electric power grid, to optimally control the reactive power in each load terminal point (power consumption area), considering instability of the electric power supplied from renewable energy power generation equipment. The above equipment includes an input portion that inputs information of reactive power including reactive power adjusted by an automatic voltage regulator of automatically adjusting a voltage of electric power generated by an electric power generator and supplied to an electric power grid, reactive power adjusted by a synchronous condenser coupled to the electric power grid, reactive power of electric power generated by the renewable energy power generation equipment, and reactive power set in each load terminal point (consumer area) of consuming the electric power; a calculation unit that calculates each setting value of reactive power adjusted by the synchronous condenser and the automatic voltage regulator, using the information of the reactive power input in the input portion; and an output portion that outputs the setting values of the reactive power calculated by the calculation unit respectively to the synchronous condenser and the automatic voltage regulator. |
| US10958068B2 |
DC transmission system and DC/DC converter used in the same
A DC transmission system transmits AC power generated by a generator to an AC distribution grid and a DC distribution grid using DC power. The DC transmission system includes an AC/DC converter, a DC/DC converter, and a DC/AC converter. The AC/DC converter outputs DC power by converting AC power from the generator. The DC/DC converter boosts a first voltage of the DC power outputted from the AC/DC converter, into a second voltage. The DC/AC converter outputs, to the AC distribution grid, AC power by converting the DC power outputted from the DC/DC converter. When the second voltage changes, the DC/DC converter controls the first voltage in response to the change in the second voltage. |
| US10958064B2 |
Surge voltage reducing member with reduced size
A surge voltage reducing member includes: a magnetic body including a long-side portion and short-side portions continuously formed at both ends of the long-side portion in a longitudinal direction; and a plurality of conductive paths wound around the long-side portion. Each of the conductive paths is wound in parallel along the longitudinal direction of the long-side portion. |
| US10958062B2 |
Systems and methods for dynamically switching a load of a current transformer circuit
Current transformer circuit systems and methods dynamically switch a load. The current transformer circuit includes a current source circuit including at least one current transformer to produce a current output wave. A burden circuit includes at least one burden resistor and a voltage sensor, at least a portion of the current output wave to be passed through the burden resistor, and the voltage sensor to sense a voltage across the respective at least one burden resistor. A switch circuit includes at least one switch, the switch circuit coupled to the burden circuit. A microcontroller circuit includes a microcontroller, the microcontroller circuit coupled to a power circuit and the switch circuit, the microcontroller being configured to control the switch circuit to dynamically switch a secondary loading of the at least one current transformer between the burden resistor and a low resistance load. |
| US10958061B2 |
Method and device for protection from internal arcs in an electrical distribution system, and electrical cabinet including such a device
A method includes detecting any light beam from 300 nm to 430 nm within the distribution system and, when this beam is detected, generating a signal indicating the presence of an internal arc inside the system; analyzing the characteristics of the light beam based on the signal and, if these characteristics meet required conditions for characterizing an internal arc fault, sending an internal arc fault signal, then; in the presence of an internal arc fault, attenuating its effects in the distribution system. Between the detecting and the analyzing, the visible and infrared portions of this beam are removed, these portions being likely to arise from ionized gases ejected by outlets of a low-voltage circuit breaker interrupting a short-circuit current. A protection device for carrying out this method includes a light detector associated with current-measuring sensors, and protection means including a main circuit breaker, a short-circuiter and a relay. |
| US10958055B2 |
Circuit assembly and electrical junction box
A circuit assembly includes a busbar substrate with busbars and a resin part that is in intimate contact with the busbars, a press-fit member that is made of metal with a thickness greater than the thickness of the busbars, and is press-fitted in the busbar substrate, an electronic component connected to the press-fit member, solder that connects the busbars and the press-fit member, and a solder accumulating portion that is formed with the resin part, and in which the solder is accumulated. |
| US10958054B2 |
Power conversion device
A power conversion device includes a wire connected to an electrical component, a casing to accommodate therein the electrical component, the casing being provided with an opening through which the wire is led out, a cover component removably attached to an exterior of the casing to cover the opening, and provided with a wiring hole through which the wire passes, and a pressing plate that is a fixing component to fix the wire inside the cover component. The cover component is attachable in two or more different orientations. |
| US10958051B1 |
Electrical conduit connector
A connector for coupling a conduit to an electrical enclosure includes a body and a lock nut. The body extends longitudinally between a proximal enclosure end and a distal conduit end. The body has an enclosure port at the enclosure end, a conduit port at the conduit end, and an internal passage extending between the enclosure port and the conduit port. The enclosure end has radially opposed first and second retention tabs. The body has external body threads located distally of the retention tabs. Each of the retention tabs extend radially outward of a longitudinal projection of the external threads. The lock nut is mated with the external body threads. The lock nut has an enclosure engagement end opposed to distal facing enclosure engagement sides of the retention tabs. The lock nut is rotatable on the external body threads to advance the enclosure engagement end toward the retention tabs. |
| US10958046B2 |
Double walled high voltage insulator cover for mitigating leakage current
For protecting wildlife from high voltage conductors proximate to a utility pole, dielectric covers are used to cover fuse cutouts, bushings, or other connections to insulators. Such covers include a vertical slot for receiving an energized wire so the cover can be installed using a hot-stick while the wire is energized. To eliminate leakage currents flowing across the cover under high voltage conditions, which previously led to localized melting of the cover, inner walls of the cover are molded that are laterally separated from the outer walls of the cover. The double wall design eliminates leakage currents due to the extra dielectric wall and air gap, and the inner wall is not subject to contamination from conductive pollutants. The double wall design also increases the insulating properties of the cover. |
| US10958040B1 |
Fabrication of ellipsoidal or semi-ellipsoidal semiconductor structures
A method for fabricating an ellipsoidal or semi-ellipsoidal semiconductor structure includes steps of providing a semiconductor substrate and fabricating an ellipsoidal or semi-ellipsoidal cavity structure on the semiconductor substrate. The cavity structure encompasses a seed surface of the semiconductor substrate. The method includes a further step of growing the ellipsoidal or semi-ellipsoidal semiconductor structure within the ellipsoidal or semi-ellipsoidal cavity structure from the seed surface of the semiconductor substrate. Fabricating the cavity structure includes arranging a droplet comprising a sacrificial material on the semiconductor substrate, forming a layer of a coating material on the semiconductor substrate and the droplet, and selectively removing the sacrificial material of the droplet to expose the cavity structure. |
| US10958034B2 |
Narrowband depolarized fiber lasers
Depolarized fiber lasers and respective methods are provided for increasing the SBS (stimulated Brillouin scattering) threshold. The laser source is constructed by a frequency-broadened seed source having a frequency bandwidth of less than 50 GHz, and the depolarization of the seed source is carried out at time scales shorter than 10 ns. At least one amplifier is configured to receive and amplify radiation from the frequency-broadened seed source and deliver the amplified radiation in the optical fiber. Depolarization may be achieved in various ways (e.g., using an interferometer with added length to one arm) and is kept at time scales shorter than tens of nanoseconds, typically shorter than 5-10 ns, which distinguish it from random polarization having polarization changes at longer time scales. Polarization maintaining fibers may be used to further increase the SBS by separating the polarizations states. |
| US10958031B1 |
Terminal un-seated tester for smart kitting of wired connectors
Wired connector assembly systems and methods involve fixing a connector in an assembly station and following, by an assembler, a set of instructions indicating a set of wires and a respective set of terminal portions of the connector in which the set of wires are to be seated. A controller of the assembly station then monitors a pulling force on the connector via each seated wire to verify proper wire-terminal portion seating. After completing the set of instructions, including verifying each proper wire-terminal portion seating, the connector is released from the assembly station and a fully assembled wired connector is obtained. |
| US10958029B2 |
Electromagnetic crimp terminal, manufacturing method of electromagnetic crimp terminal, and connecting terminal
An electromagnetic crimp terminal includes an electric wire and a terminal plate. The electric wire includes a conductor portion, an insulation portion which covers the conductor portion, and an exposed portion which is a part of the conductor portion exposed from the insulation portion. The terminal plate includes a crimped portion. The crimped portion is crimped onto the exposed portion. The crimped portion includes a first side edge and a second side edge. A vicinity of the first side edge and a vicinity of the second side edge overlap each other. |
| US10958027B2 |
Electrical connection box
Provided is an electrical connection box according to which it is possible to suppress the occurrence of mistakes in a manufacturing process, and it is possible to reliably prevent the occurrence of faulty products. The electrical connection box to be used in a vehicle includes a terminal having an inner-fitting plate portion that is fit into and held in a slit of a holding member; and multiple substrate connection portions that protrude along a surface of the inner-fitting plate portion from one side edge of the inner-fitting plate portion. The terminal has a shape that is asymmetrical in a direction in which the multiple substrate connection portions are arranged side by side. |
| US10958025B2 |
Pivoting plug adapter
A pivoting plug adapter provides a conductive connection between first and second plugs. The adapter includes a pair of sub-assemblies attached to one another in a pivotal mechanical connection with each sub-assembly housing conductive elements. One plug extends from one sub-assembly and the other plug extends from the other sub-assembly. A central conductive sleeve extends between the respective sub-assemblies coaxial to the axis of rotation. A bias member is positioned between sub-assemblies to bias them away from one another. Another bias member is positioned within a sub-assembly as a member of the conductive path between the plugs. One or more of the bias members may be wave washers. The sub-assemblies are pivotal about the central axis to vary the position of the plugs relative to one another while maintaining conductive communication. |
| US10958024B2 |
Managed electrical connectivity systems
A connector arrangement includes a plug nose body; a printed circuit board positioned within a cavity of the plug nose body; and a plug cover that mounts to the plug nose body to enclose the printed circuit board within the cavity. The printed circuit board includes a storage device configured to store information pertaining to the electrical segment of communications media. The plug cover defines a plurality of slotted openings through which the second contacts are exposed. A connector assembly includes a jack module and a media reading interface configured to receive the plug. A patch panel includes multiple jack modules and multiple media reading interfaces. |
| US10958023B2 |
Electrical device, electrical distribution system, and methods of assembling same
An electrical device having a bus side and a load side is provided. The electrical device includes a plurality of conductive line terminals disposed on the bus side of said electrical device, and a plurality of electrical connectors. Each electrical connector of the plurality of electrical connectors includes a first end coupled to a respective line terminal of the plurality of line terminals, a second end distal from the first end, and a connector clip disposed at the second end. Each connector clip is configured to engage a bus bar to electrically couple the electrical device to the bus bar, and includes a first contact segment and a second contact segment spaced apart from the first contact segment. The first and second contact segments are configured to deflect towards one another from a relaxed position to a depressed position when inserted into a connector channel defined by the bus bar. |
| US10958017B2 |
Contact element for a connector
The invention relates to a contact element (1) for a connector (2), having: an at least partially electrically conductive housing (3) for connection to an earth conductor (4.2) of an electrical cable (4), and at least one inner conductor part (6) for connection to at least one signal lead (4.4) of the electrical cable (4). In a contact region (9) of the housing (3) at the front in the insertion direction, there are at least two resilient tongues (10, 11), wherein the resilient tongues (10, 11) are each secured movably at a first, free end (10.1, 11.1) and immovably at a second end (10.2, 11.2). There are two groups of resilient tongues (10, 11), wherein the resilient tongues (10) of a first group are arranged such that the free ends (10.1) thereof face a front end (9.1) of the contact region (9), and the resilient tongues (11) of a second group are arranged such that the free ends (11.1) thereof face away from the front end (9.1) of the contact region (9). |
| US10958016B2 |
Ultra high speed signal cable connector and assembly method thereof
An ultra high speed signal cable connector includes an insulating housing, a PCB fixedly mounted inside the insulating housing, and at least one row of cables without grounding wires welded to the PCB. The end portion of a connecting finger of the PCB extends out of the insulating housing, and the PCB is provided with a signal bonding pad and a grounding wire bonding pad. Each cable without grounding wires includes a plurality of electric wires, a conductive jacket for wrapping the plurality of electric wires together, and an insulating jacket wrapped on the outer layer of the conductive jacket. Each electric wire includes a core wire and an insulating layer wrapped on the outer layer of the core wire. One ends of the core wires are welded on the signal bonding pad; a section of insulating jacket is stripped from the foremost end of each cable without grounding wires to expose the conductive jacket. The conductive jackets are electrically and fixedly connected to the grounding wire bonding pad. According to the ultra high speed signal cable connector provided by the present disclosure, there is no need to weld the grounding wire during welding, the welding efficiency can be significantly improved, the connector is compact in structure, small in occupied space and high in strength, and the inner mold is adopted to wrap the welding spots between the cables and the PCB, so that the welding spots are protected, and the electrical performance is significantly improved compared with that of the existing products. |
| US10958015B1 |
Vehicle heater decoupling system
A vehicle heater decoupling system that facilitates an automated decoupling of the vehicle heater with a power cord plug operably coupled thereto. The present invention includes a receptacle that is configured with a disconnection member. The disconnection member is operably coupled to electrical connection members that are electrically coupled to the power cord plug. A sensor is present to provide detection of the power cord plug. A controller is disposed within the passenger compartment of the vehicle and is coupled to the electrical system of the vehicle. The controller is configured to detect the operational status of the motor of the vehicle specifically whether the motor is running or idle. The controller detects the ignition of the motor and the state of the receptacle and upon detection of the ignition of the motor and the first state the controller transmits a signal to eject the power cord plug. |
| US10958013B1 |
Waterproof connector
A connector mainly includes a main base body, one end of which has a guide sleeve, the other end of the main base body has a butting holes, and the guide sleeve is connected with a connecting module. The connecting module further includes a connecting base which includes a connecting element. The connecting module further includes a butting seat correspondingly engages the guide sleeve, and a conductive module is housed inside the main base body. The conductive module further includes a central pin, and the central pin is provided with a second waterproof gasket. The second waterproof gasket for the central pin extending therethrough and abuts against a side of a convex seat. The central pin extends through a sleeve which is correspondingly connected with a conductive base, and the central pin is sleeved in the sleeve and the conductive base. Finally, the conductive module is further correspondingly sleeved with a fixing seat and a protective sleeve in sequence. A waterproof layer protrudes outward on the outer peripheral surface. |
| US10958012B2 |
Cover assembly for a telecommunications connector
A cover assembly (100) is disclosed that can be installed onto and removed from a telecommunications connector (200) without requiring the connector (200) from being removed from its mounted position and without requiring an associated cover plate (120) from being removed from its mounted position. The cover assembly (100) can include a base portion (150) that defines an opening that entirely surrounds a cover portion (110). In one example, the cover portion (110) is attached to the base portion (150) via a living hinge (118). In one aspect, the base portion (150) acts as a color cap while the cover portion (110) acts as a dust cover. In one example, the base portion (150) is provided without a cover portion (110) such that the cover assembly (100) simply acts as a color cap. |
| US10958008B2 |
Separable clasp connectors and die sets and methods for locking and unlocking such connectors
A separable clasp connector is provided that has first and second parts that are pivotable with respect to one another by a die set. The clasp connector includes one or more die alignment features to ensure proper alignment with the die set so as to apply an unlocking force in a predetermined direction. Die sets and methods also provided to move a separable clasp connector back-and-forth among a locked position and an unlocked position. |
| US10958007B2 |
High speed, high density electrical connector
A broadside coupled connector assembly has two sets of conductors, each separate planes. By providing the same path lengths, there is no skew between the conductors of the differential pair and the impedance of those conductors is identical. The conductor sets are formed by embedding the first set of conductors in an insulated housing having a top surface with channels. The second set of conductors is placed within the channels so that no air gaps form between the two sets of conductors. A second insulated housing is filled over the second set of conductors and into the channels to form a completed wafer. The ends of the conductors are received in a blade housing. Differential and ground pairs of blades have one end that extends through the bottom of the housing having a small footprint. An opposite end of the pairs of blades diverge to connect with the wafers. The ends of the first and second sets of conductors and the blades are jogged in both an x- and y-coordinate to reduce crosstalk and improve electrical performance. |
| US10958006B2 |
Contact element and method for production thereof
A contact element comprises an electrically conductive layer and a masking layer. A contact side of the contact element is at least partly covered by the masking layer and the electrically conductive layer. The electrically conductive layer and the masking layer form a contact surface having alternating regions of the masking layer and the electrically conductive layer. |
| US10958000B2 |
Printboard contact grip
A printed circuit board connector includes a cable attachment portion configured to be coupled with a cable and a printed circuit board attachment section configured to be coupled with a printed circuit board. The printed circuit board attachment section is configured to be coupled with the printed circuit board via a snap-fit connection. |
| US10957999B1 |
Stacking cabled input/output slots
One or more stacking cabled I/O slots may be installed in a stacked arrangement on a computing device, such as in an I/O expansion socket of a computing device motherboard. Slot detection and population logic associated with each of the one or more stacking cabled I/O slots enables signaling from each installed stacking cabled I/O slot, in order for its presence and location relative to any other installed stacking cabled I/O slot to be identified to and recognized by the computing device. High speed data signals through an installed stacking cabled I/O slot are coupled to the computing device via a cable, while power and logic signals are exchanged between the computing device and the one or more stacking cabled I/O slots via connections to the I/O expansion socket. |
| US10957998B2 |
Press-fit terminal, connector for board, and board-equipped connector
An object is to, for physical properties, holding force, contact area, and insertion force in a trade-off relationship, set the holding force to 37 N or more, the contact area to 0.72 mm2 or more, and the insertion force to 90 N or less. A press-fit terminal is to be press-fitted into a through hole formed in a circuit board. A press-fit part includes a beam and an eye hole that is surrounded by the beam. The beam includes two parallel parts that are parallel to each other. In the press-fit part, G1/G2 is 0.20 or more and 1.05 or less where a front-side spring strength is G1 [mm3] and a rear-side spring strength is G2 [mm3] calculated under the following conditions, and G is 0.007 mm3 or more and 0.012 mm3 or less where a spring strength G [mm3] is G1+G2. |
| US10957993B2 |
Connector structure
A connector structure includes a case seat assembly and plug assemblies. Two ends of the case seat assembly are formed with channels. Each plug assembly has a conductive section and a wire connection member. The wire connection member is formed with a receiving space for receiving a pressing leaf spring. Each pressing leaf spring has an abutment end. A lateral protrusion section is disposed on the abutment end. Multiple unlocking assemblies are disposed beside the wire connection member. Each unlocking assembly has a push member formed with a push block. The lateral protrusion section is positioned in a sliding path of the push block along the channel, whereby the lateral protrusion section can be pushed to drive the abutment end to release a conductive wire. |
| US10957991B2 |
Planar array antenna and communications device
Embodiments of this disclosure disclose a planar array antenna, including at least one first radiation array arranged along a first direction. The first radiation array includes at least one first radiation unit and at least one radiation unit pair, the first radiation unit and the radiation unit pair are disposed on an axis of the first radiation array, the radiation unit pair includes at least two second radiation units, and the at least two second radiation units are symmetric with respect to the axis of the first radiation array. In addition, the embodiments of this disclosure further disclose a communications device to which the planar array antenna is applied. |
| US10957988B2 |
Slot array antenna, and radar, radar system, and wireless communication system including the slot array antenna
A slot array antenna includes: a first conductive member having a first conductive surface and a plurality of slots therein, the slots being arrayed in a first direction and in a second direction which intersects the first direction; a second conductive member having a second conductive surface which opposes the first conductive surface; a plurality of waveguide members arrayed between the first and second conductive members along a direction which intersects the first direction, each waveguide member having an conductive waveguide face which extends along the first direction so as to oppose at least one of the slots; and an artificial magnetic conductor in a subregion which is within a region between the first and second conductive members but outside of a subregion containing the waveguide members. Neither an electric wall nor an artificial magnetic conductor exists in a space between two adjacent waveguide faces among the waveguide members. |
| US10957984B2 |
Wireless communication device
A wireless communication device for transmitting/receiving a high-frequency signal having a predetermined communication frequency. The wireless communication device includes an antenna pattern having an inductance component, an RFIC element connected electrically to the antenna pattern and a capacitive coupling portion capacitively coupling specific confronting regions facing each other of the antenna pattern at multiple points on the antenna pattern, to make up an LC parallel resonant circuit. |
| US10957982B2 |
Antenna module formed of an antenna package and a connection member
An antenna module includes a ground layer including a through-hole; a feed via disposed to pass through the through-hole; a patch antenna pattern spaced apart from the ground layer and electrically connected to one end of the feed via; a coupling patch pattern spaced apart from the patch antenna pattern; a first dielectric layer to accommodate the patch antenna pattern and the coupling patch pattern; a second dielectric layer to accommodate at least a portion of the feed via and the ground layer; and electrical connection structures disposed between the first dielectric layer and the second dielectric layer to separate the first dielectric layer from the second dielectric layer. |
| US10957976B2 |
Pedestal apparatus having antenna attached thereto capable of biaxial motion
Disclosed is a pedestal apparatus having an antenna attached thereto capable of biaxial motion. The pedestal apparatus according to one embodiment may comprise: a body; a first drive unit, arranged on the lower part of the body, for transmitting driving power; a second drive unit, arranged on the lower part of the body, for transmitting driving power; a first drive gear arranged on the upper part of the body and receiving driving power from the first drive unit; a second drive gear arranged on the upper part of the body opposite the first drive gear, and receiving driving power from the second drive unit; and a driven gear which rotates by receiving driving power from the first and second drive gears, and to which an antenna is connected, wherein the antenna can move biaxially in accordance with the rotational directions of the first and second drive gears. |
| US10957973B2 |
Antenna module
The present disclosure improves, in an antenna module, the isolation characteristic between an output signal from an antenna and an input signal. An antenna module includes a dielectric substrate having a first surface and a second surface, an antenna formed on the first surface, a radio frequency element configured to supply a radio frequency signal to the antenna, and a signal terminal formed into a columnar shape using a conductive material. The signal terminal is connected to the radio frequency element by a wiring pattern in the dielectric substrate. The signal terminal is disposed outside an excitation region generated in an excitation direction of an output signal. |
| US10957972B2 |
Audio device
An audio device (e.g., hearing aid) can optionally have a radio-frequency antenna that includes an antenna structure on a flexible printed circuit board. The antenna structure can have one or metal traces disposed on the flexible printed circuit board, the antenna structure extending over an area that substantially coincides with the area of the flexible printed circuit board. The flexible printed circuit board is foldable into a three-dimensional structure that can be disposed in a folded configuration in an audio device (e.g., hearing aid). |
| US10957971B2 |
Feed to waveguide transition structures and related sensor assemblies
Waveguide module assemblies for vehicles, such as radar sensor waveguide feed to waveguide transition assemblies. In some embodiments, an antenna module may comprise an antenna assembly that includes a resonating element and a waveguide component that defines, at least in part, a waveguide configured to guide electromagnetic energy radiating from the resonating element. The resonating element of the antenna assembly may directly feed electromagnetic energy into the waveguide defined by the waveguide component. |
| US10957969B2 |
Integrated antennas for portable electronic devices
Aspects of the subject technology relate to electronic devices with antennas. The antenna may be a display-integrated antenna. An antenna feed for the antenna may be located in a recess in a sidewall of a housing of the device. The antenna feed may be coupled to transceiver circuitry on a logic board of the device by a pair of flex circuits. A first one of the pair of flex circuits may form a portion of an antenna feed assembly. A second one of the pair of flex circuits may be an impedance-matching flex having an end that is soldered to the main logic board. The antenna may be coupled to a conductive portion of the housing of the device. |
| US10957968B2 |
Deployable and retractable antenna array module
A method, wireless communication device (WCD), and computer program product deploys an additional, retractable antenna to enhance signal communication within an identified network. A processor executes an antenna deployment module (ADM) in order to determine a link status based on a quality and/or a strength of communication signals propagated via at least one stationary antenna. In response to the link status indicating that coverage of a second/target network is available or that a quality of a signal propagated within a first network is less than a threshold level, the ADM provides a deployment signal to a deployment component. In response to receiving the deployment signal, the deployment component deploys the retractable antenna by extending the retractable antenna from a stowed position to a deployed position. The ADM enables the WCD to communicate within the selected network via the deployed retractable antenna using a higher quality communication signal. |
| US10957962B2 |
Magnetoresistive effect device
A magnetoresistive effect device includes an input port, an input-side signal line, an MR unit including a magnetoresistive effect element and a magnetic-field generating signal line, and an output unit including a magnetoresistive effect element, an output-side signal line, and an output port. The magnetoresistive effect device further includes a DC application terminal. The magnetoresistive effect element is connected to the output port via the output-side signal line in the output unit. The input-side signal line is arranged so that a high frequency magnetic field generated from the input-side signal line is applied to the magnetoresistive effect element in the MR unit. In the MR unit, the magnetoresistive effect element is connected to the magnetic-field generating signal line. The magnetic-field generating signal line is arranged so that a high-frequency magnetic field generated from magnetic-field generating signal line is applied to the magnetoresistive effect element in the output unit. |
| US10957958B2 |
Dielectric resonator and dielectric filter
A dielectric resonator includes a dielectric block, an external conductor, and wall-surface conductors. The dielectric block has a rectangular parallelepiped shape including a first surface and a second surface opposed to each other. The dielectric block includes a through hole extending from the first surface to the second surface. The external conductor is disposed on an outer surface of the dielectric block. The wall-surface conductors are disposed on a wall surface defining the through hole. The wall-surface conductor includes a first portion of the through hole adjacent to the first surface and a second portion of the through hole adjacent to the second surface. The first and second portions of the wall-surface conductors are separated by a separation distance. |
| US10957953B2 |
Lithium oxygen battery and electrolyte composition
A battery employing lithium-oxygen chemistry may include an anode comprising lithium, an electrolyte, and a porous cathode. The electrolyte may include a lithium-containing salt; a partially fluorinated ether, such as 2,2-bis(trifluoromethyl)-1,3-dioxolane; and a co-solvent selected from the group consisting of ethers, amides, nitriles, and combinations thereof. In some examples, the electrolyte does not include a cyclic carbonate ester, a sulfolane, or a sulfolane derivative. The porous cathode allows oxygen to come into contact with the electrolyte. |
| US10957950B1 |
Heating module, heating method for battery module, and heating system
The present application discloses a heating module, a heating method for a battery module, and a heating system. The heating module includes: an energy storage unit, a first switch unit, a second switch unit and a control unit. The energy storage unit, a first battery unit in a battery module and the first switch unit may form a first heating loop; the energy storage unit, a second battery unit in the battery module, and the second switch unit may form a second heating loop. The control unit may control the first switch unit or the second switch unit, so as to sequentially switch on, between the first heating loop and the second heating loop, a heating loop where a battery unit with a higher state of charge is located and a heating loop where a battery unit with a lower state of charge is located. |
| US10957948B2 |
Housing for at least one battery module and battery module assembly
The present invention relates to a housing for at least one battery module, preferably for an arrangement of battery modules, with the at least one battery module comprising a plurality of battery cells arranged in a fluid cooled frame. The invention further relates to a battery module assembly comprising at least one battery module installed in a housing. |
| US10957947B2 |
High-voltage detection circuit, detector, battery device and vehicle
The present invention provides a high-voltage detection circuit, detector, battery device and vehicle, the high-voltage detection circuit includes: a controller including a first signal input port, a second signal input port, and a signal output port; a current detection sub-circuit for sampling a current signal of internal side of a main negative switch and for transmitting the current signal to the first signal input port; a switch detection sub-circuit, a first end of the switch detection sub-circuit being configured to sample a first electric signal of external side of a to-be-detected switch, and a second end of the switch detection sub-circuit being configured to transmit the first electric signal to the second signal input port; and a switch driving sub-circuit, configured for sampling a switch control signal via the signal output port and generating a switch driving signal according to the switch control signal. |
| US10957945B2 |
Battery state detection method and system thereof
A battery state detection method includes: presetting at least one discharge method and at least one discharge condition of a battery set for estimating a battery state, with the discharge condition including a discharge voltage, discharge time or a relative battery impedance variation; executing a partial discharge procedure of the battery set and measuring partial discharge data; and directly calculating battery state data of the partial discharge data under the discharge method and the discharge condition. The battery state data include a SOH (state of health) datum, a SOC (state of charge) datum or a residual discharging time datum. The detection of the battery set is suitable for a manual operation system, a remote control monitoring system or an automatic scheduling system. |
| US10957940B2 |
Semi-solid electrodes with a polymer additive
Embodiments described herein relate generally to electrochemical cells having semi-solid electrodes that include a gel polymer additive such that the electrodes demonstrate longer cycle life while significantly retaining the electronic performance of the electrodes and the electrochemical cells formed therefrom. In some embodiments, a semi-solid electrode can include about 20% to about 75% by volume of an active material, about 0.5% to about 25% by volume of a conductive material, and about 20% to about 70% by volume of an electrolyte. The electrolyte further includes about 0.01% to about 1.5% by weight of a polymer additive. In some embodiments, the electrolyte can include about 0.1% to about 0.7% of the polymer additive. |
| US10957937B2 |
Three-terminal copper-driven neuromorphic device
Three-terminal solid state Cu-ion actuated analog switching devices are provided. In one aspect, a method of forming a switching device includes: depositing a channel layer on a substrate; forming a source contact and a drain contact on opposite ends of the channel layer; forming a solid electrolyte on the channel layer over the source contact and the drain contact; and depositing a gate onto the solid electrolyte, wherein the source contact, the drain contact, and the gate are three terminals of the switching device. A switching device and a method of operating a switching device are also provided. |
| US10957934B2 |
Transfer apparatus using electrostatic attraction and transfer method using electrostatic attraction
A transfer apparatus using an electrostatic attraction includes an electrostatic chuck for attracting and placing a workpiece as a transfer member on a placement surface by electrostatic attraction. The electrostatic chuck is grounded by an earth via a ground electrode after the electrostatic chuck receives electric power from a power supply surface of a power source via power receiving electrodes of the electrostatic chuck, so that the electrostatic chuck is configured to attract and place the workpiece on the placement surface by electrostatic attraction in a state where electrostatic balance is broken. |
| US10957933B2 |
Setter plates and manufacturing methods for ceramic-anode solid oxide fuel cells
In various embodiments, techniques for fabricating solid oxide fuel cells utilize setter plates composed of or having outer surfaces composed of materials unreactive with species found in the layers of the cell. |
| US10957930B2 |
Solid alkaline fuel cell including inorganic solid electrolyte enabled to permeate water
A solid alkaline fuel cell has a cathode that is supplied with an oxidant which contains oxygen, an anode that is supplied with a fuel which contains hydrogen atoms, and an inorganic solid electrolyte that is disposed between the anode and the cathode and that exhibits a hydroxide ion conductivity. The inorganic solid electrolyte enables the permeation of water of greater than or equal to 80 μg/min·cm2 and less than or equal to 5400 μg/min·cm2 per unit surface area of a cathode-side surface. |
| US10957926B2 |
Fuel cell system and control method of fuel cell system
A fuel cell system includes a motor driving a compressor that supplies air to a fuel cell, a turbine assisting the compressor, a bypass valve that opens and closes the bypass flow path, and a controller. When a required air flow rate is equal to or higher than a threshold value, the controller closes the bypass valve and controls the motor to cause the air to flow through the fuel cell at a flow rate corresponding to the required air flow rate. When the required air flow rate is lower than the threshold value, the controller opens the bypass valve to cause the air to flow through the bypass flow path and controls the motor to cause the air to flow through the fuel cell at the flow rate corresponding to the required air flow rate. |
| US10957925B2 |
Method of running-in operation of fuel cell
First, a reaction gas is supplied to a fuel cell stack including a laminate of solid polymer electrolyte fuel cells and power generation is performed so that a temperature of the fuel cell stack reaches 65° C. or higher (heating power generation step). Next, the reaction gas is supplied to the fuel cell stack and the power generation is performed under a condition in which relative humidity is 100% or more (cleaning power generation step). Cooling water of room temperature may be supplied to the fuel cell stack from the outside before the cleaning power generation step is performed after the heating power generation step is completed, or after the cleaning power generation step is completed (quenching step). |
| US10957920B2 |
Fuel cell vehicle
A fuel cell vehicle capable of generating electric power in an optimum wet state is provided. A fuel cell vehicle including a fuel cell, a radiator configured to cool a coolant which has been warmed by cooling the fuel cell and send it back to the fuel cell, a grille shutter configured to adjust a flow rate of air taken into the radiator from an air intake, a sensor configured to measure an impedance of the fuel cell, and a control unit configured to control the grille shutter to open and close. The control unit controls the grille shutter to open when a measured value of the impedance becomes greater than or equal to a predetermined threshold. |
| US10957918B2 |
Stable electrolyte matrix for molten carbonate fuel cells
A method of making an electrolyte matrix includes: preparing a slurry comprising a support material, a coarsening inhibitor, an electrolyte material, and a solvent; and drying the slurry to form an electrolyte matrix. The support material comprises lithium aluminate, the coarsening inhibitor comprises a material selected from the group consisting of MnO2, Mn2O3, TiO2, ZrO2, Fe2O3, LiFe2O3, and mixtures thereof, and the coarsening inhibitor has a particle size of about 0.005 μm to about 0.5 μm. |
| US10957916B2 |
Porous carbon sheet and precursor fiber sheet thereof
A precursor fiber sheet includes short carbon fibers having an average length of 3 to 10 mm, natural pulp having an ash content of 0.15 mass % or less, and a heat-carbonizable resin, and a porous carbon sheet is obtained by carbonizing the precursor fiber sheet. This enhances gas diffusibility and water removal properties of the porous carbon sheet and has high mechanical strength and few appearance defects even when the bulk density of the porous carbon sheet is lowered. |
| US10957913B2 |
Gauntlet lead-acid battery systems
A lead-acid battery electrode including a tubular bag. The tubular bag includes a textile fabric, wherein the textile fabric includes a consolidated binder with thermoplastic properties and at least one electrically conductive additive. |
| US10957912B2 |
Method of extending cycle-life of a lithium-sulfur battery
The invention provides a method of improving the cycle-life of a rechargeable alkali metal-sulfur cell. The method comprises implementing an anode-protecting layer between an anode active material layer and a porous separator/electrolyte, and/or implementing a cathode-protecting layer between a cathode active material and the porous separator/electrolyte, wherein the anode-protecting layer or cathode-protecting layer comprises a conductive sulfonated elastomer composite having from 0.01% to 40% by weight of a conductive reinforcement material and from 0.01% to 40% by weight of an electrochemically stable inorganic filler dispersed in a sulfonated elastomeric matrix material and the protecting layer has a thickness from 1 nm to 100 μm, a fully recoverable tensile strain from 2% to 500%, a lithium ion conductivity from 10−7 S/cm to 5×10−2 S/cm, and an electrical conductivity from 10−7 S/cm to 100 S/cm when measured at room temperature. |
| US10957911B2 |
Negative electrode comprising multiple protection layers and lithium secondary battery comprising same
The present invention relates to a negative electrode including a multi-protective layer and a lithium secondary battery including the same. The multi-protective layer is capable of effectively transferring lithium ions to a lithium metal electrode while physically suppressing lithium dendrite growth on the electrode surface, and does not cause an overvoltage during charge and discharge since the protective layer itself does not function as a resistive layer due to excellent ion conductivity of the multi-protective layer, and therefore, is capable of preventing battery performance decline and securing stability during battery operation. |
| US10957908B2 |
Electrode for lithium ion battery, lithium ion battery, and method for producing electrode for lithium ion battery
The objective of the present invention is to provide an electrode for a lithium ion battery which has excellent electron conductivity even when the thickness of the electrode is increased. The electrode for a lithium ion battery according to the present invention includes a first principal surface located on a separator side of the lithium ion battery, and a second principal surface located on a current collector side, wherein the electrode has a thickness of 50 to 5000 μm, and the electrode includes, between the first principal surface and the second principal surface, short fibers (A) having an average fiber length of 50 nm or more and less than 100 μm, long fibers (B) having an average fiber length of 100 μm or more and 1000 μm or less, and active material particles (C), and the short fibers (A) and the long fibers (B) are electroconductive fibers. |
| US10957905B2 |
Porous silicon flake anode material for li ion batteries
A silicon based material in the form of sheet-like silicon porous particles in an electrically conductive material matrix wherein said silicon particles contain nano-sized pores, and a method of producing thereof, are disclosed. The material and the method allow obtaining Li ion batteries with high electric charge capacity and improved cycling performance of the battery anode. |
| US10957897B2 |
Composite cathode active material, and cathode and lithium battery comprising composite cathode active material
A composite cathode active material, a cathode including the composite cathode active material, and a lithium battery including the cathode are provided. The composite cathode active material includes a core including a lithium metal oxide and a coating layer on the core, wherein the lithium metal oxide includes two or more transition metals including nickel (Ni), an amount of Ni within one mole of the two or more transition metals included in the lithium metal oxide is about 0.65 mol or greater, the coating layer includes LiF, and a resistance of the composite cathode active material is lower than that of the core. |
| US10957882B2 |
Vapor deposition mask, production method therefor, and production method for organic EL display device
A vapor deposition mask is provided with: a resin film, which has at least one of first to third opening patterns in which first to third openings, for forming first to third subpixels that configure one pixel of a display panel, are disposed with a fixed periodicity; and a metal support layer, which is bonded to the resin film and has an opening pattern for fourth openings that are formed so as to be able to encompass all of the first to third openings of the resin film. In regions of the resin film exposed by the fourth openings of the metal support layer, one or two of the first to third openings of the resin film are formed. |
| US10957881B2 |
Method and apparatus for producing flexible OLED device
According to a flexible OLED device production method of the present disclosure, a multilayer stack (100) is provided which includes a glass base (10), a functional layer region (20) including a TFT layer (20A) and an OLED layer (20B), and a synthetic resin film (30) provided between the glass base (10) and the functional layer region (20) and bound to the glass base (10). In a dry gas atmosphere whose dew point is not more than −50° C., the multilayer stack (100) is separated into a first portion (110) and a second portion (120), and a surface (30s) of the synthetic resin film (30) is exposed to the dry gas atmosphere, the first portion (110) including the functional layer region (20) and the synthetic resin film (30), the second portion (120) including the glass base (10). The first portion (110) is transported from the dry gas atmosphere to a reduced-pressure atmosphere R, and a protection layer (60) is formed on the surface (30s) of the synthetic resin film (30) in the reduced-pressure atmosphere R. |
| US10957877B2 |
Organic light emitting diode display
An organic light emitting diode display device includes: a substrate including a plurality of pixel regions which each include an emission region and a non-emission region around the emission region; a plurality of scattering portions disposed on the substrate, corresponding to the emission region, and spaced apart from each other; a first overcoat layer disposed on the substrate having the plurality of scattering portions and including a plurality of concave portions which respectively correspond to the plurality of scattering portions; a first electrode disposed on the first overcoat layer in each of the plurality of pixel regions; and an organic light emitting layer and a second electrode sequentially disposed on the first electrode. |
| US10957870B2 |
Organic light emitting device
A region of a device is provided that includes a first material and a second material. The first and second materials may be co-dopants of an emissive material or region. The first material may have an energy gap of not more than about 100 meV between the first excited singlet state and the first excited triplet state. Excitons that transition to the T1 state can be activated to the S1 state due to the relatively small energy gap. This thermal activation process is fast enough that non-radiative decay from the T1 state to the S0 state is minimal or negligible, thus allowing for sensitization up to and including 100%. The second material may be a phosphorescent-capable material, and may act as a sensitizer to the first material. |
| US10957869B2 |
Organic luminescent materials containing cycloalkyl ancillary ligands
Organic luminescent materials containing cycloalkyl ancillary ligands is disclosed, which can be used as emitters in the emissive layer of an organic electroluminescent device. The organic luminescent materials is metal complexes which comprise a new series of cycloalkyl containing acetylacetone type ancillary ligands. These novel ligands can effectively improve the lifetime of the device, change the sublimation characteristics and improve device performance. Also disclosed are an electroluminescent device and a formulation. |
| US10957867B2 |
Display device
A display device includes a display module, a protective member under the display module, and an adhesive member between the display module and the protective member. The display module includes a folding area foldable along a folding axis, a first non-folding area, and a second non-folding area, and the folding area is between the first and second non-folding areas. A first thickness of the protective member overlapping with the folding area is less than a second thickness of the protective member overlapping with the first non-folding area and a third thickness of the protective member overlapping with the second non-folding area. |
| US10957862B2 |
Condensed cyclic compound for organic light-emitting device, and organic light-emitting device including the compound
A condensed cyclic compound represented by Formula 1: wherein, in Formula 1, groups and variables are the same as described in the specification. |
| US10957859B2 |
Heterocyclic compounds for use in electronic devices
The present invention relates to heterocyclic compounds and to electronic devices, especially organic electroluminescent devices, comprising these compounds. |
| US10957856B2 |
Method and apparatus for manufacturing organic el display panel
Disclosed is a method for manufacturing an organic EL display panel in which a plurality of organic electroluminescence elements each including an organic layer are arranged on an upper side of a substrate. The method includes applying an ink obtained by dissolving or dispersing an organic material in a solvent to a preset application area over the substrate, and cooling the ink applied in the applying within a period until the ink is dried, to lower an ink temperature to a second temperature lower than a first temperature of the ink at a time of application thereof. |
| US10957855B2 |
Apparatuses including electrodes having a conductive barrier material and methods of forming same
Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions. |
| US10957850B2 |
Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication
A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer. |
| US10957849B2 |
Magnetic tunnel junctions with coupling-pinning layer lattice matching
Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ a first pinning layer and a second pinning layer with a synthetic anti-ferrimagnetic layer disposed therebetween. The first pinning layer in contact with the seed layer can contain a single layer of platinum or palladium, alone or in combination with one or more bilayers of cobalt and platinum (Pt), nickel (Ni), or palladium (Pd), or combinations or alloys thereof, The first pinning layer and the second pinning layer can have a different composition or configuration such that the first pinning layer has a higher magnetic material content than the second pinning layer and/or is thicker than the second pinning layer. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing. |
| US10957848B2 |
Heusler compounds with non-magnetic spacer layer for formation of synthetic anti-ferromagnets (SAF)
Devices are described that include a multi-layered structure that comprises three layers. The first layer is a magnetic Heusler compound, the second layer (acting as a spacer layer) is non-magnetic at room temperature and comprises alternating layers of Ru and at least one other element E (preferably Al; or Ga or Al alloyed with Ga, Ge, Sn or combinations thereof), and the third layer is also a magnetic Heusler compound. The composition of the second layer is represented by Ru1−xEx, with x being in the range from 0.45 to 0.55. An MRAM element may be constructed by forming, in turn, a substrate, the multi-layered structure, a tunnel barrier, and an additional magnetic layer (whose magnetic moment is switchable). |
| US10957847B2 |
Multilayered spacer structure for a magnetic tunneling junction and method of manufacturing
A semiconductor structure is disclosed. The semiconductor structure includes: an Nth metal layer; a bottom electrode over the Nth metal layer; a magnetic tunneling junction (MTJ) over the bottom electrode; a top electrode over the MTJ; a spacer, including: a first spacer layer including SiN with a first atom density, the first spacer layer laterally encompassing the MTJ; and a second spacer layer including SiN with a second atom density different from the first atom density, the second spacer layer laterally encompassing at least a portion of the first spacer layer; and an (N+1)th metal layer over the top electrode. A method for manufacturing a semiconductor structure is also disclosed. |
| US10957844B2 |
Magneto-electric spin orbit (MESO) structures having functional oxide vias
Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines. |
| US10957841B2 |
Capping layer for reducing ion mill damage
A method of fabricating an electrical contact junction that allows current to flow includes: providing a substrate including a first layer of superconductor material; removing a native oxide of the superconductor material of the first layer from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, in which the capping layer prevents reformation of the native oxide of the superconductor material in the first region; forming, after forming the capping layer, a second layer of superconductor material that electrically connects to the first region of the first layer of superconductor material to provide the electrical contact junction that allows current to flow. |
| US10957840B2 |
Apparatus, and process for cold spray deposition of thermoelectric semiconductor and other polycrystalline materials and method for making polycrystalline materials for cold spray deposition
An apparatus and method perform supersonic cold-spraying to deposit N and P-type thermoelectric semiconductor, and other polycrystalline materials on other materials of varying complex shapes. The process developed has been demonstrated for bismuth and antimony telluride formulations as well as Tetrahedrite type copper sulfosalt materials. Both thick and thin layer thermoelectric semiconductor material is deposited over small or large areas to flat and highly complex shaped surfaces and will therefore help create a far greater application set for thermoelectric generator (TEG) systems. This process when combined with other manufacturing processes allows the total additive manufacturing of complete thermoelectric generator based waste heat recovery systems. The processes also directly apply to both thermoelectric cooler (TEC) systems, thermopile devices, and other polycrystalline functional material applications. |
| US10957838B2 |
Thermoelectric element material and method for manufacturing the same
A thermoelectric element material according to the present invention includes a quantum dot portion including a large number of quantum dots. The quantum dot portion includes carriers therein, the carriers serving to carry an electric current. Of the large number of quantum dots, adjacent quantum dots are separate from each other and are close to each other to an extent allowing the carriers to move between the quantum dots. |
| US10957835B2 |
Light emitting element and method for fabricating the same
A light emitting element is disclosed. The light emitting element includes: an LED chip including a light emitting semiconductor stack and first and second electrode pads disposed under the light emitting semiconductor stack and spaced apart from each other; a substrate mounted with the LED chip and including a first electrode corresponding to the first electrode pad and a second electrode corresponding to the second electrode pad; a first solder portion connecting the first electrode pad and the first electrode; and a second solder portion connecting the second electrode pad and the second electrode. The first solder portion and the second solder portion are formed without escaping from the mounting area of the LED chip on the substrate by heating a solder material to its melting point or above with an IR laser. |
| US10957825B2 |
Lighting module and lighting apparatus having thereof
A lighting module according to an embodiment of the invention includes: a substrate; a plurality of light emitting devices disposed in N rows (N is an integer of 1 or more) on the substrate; a first resin layer covering the plurality of light emitting devices; a first diffusion layer disposed on the first resin layer and diffusing light emitted from the first resin layer; and a second diffusion layer disposed on the first diffusion layer and diffusing light emitted from the first diffusion layer, wherein the first diffusion layer includes a diffusing agent, and the second diffusion layer includes at least one of a phosphor and ink particles. |
| US10957822B2 |
Light emitting device and method of manufacturing same
A light emitting device includes: a substrate; a light emitting element disposed on the substrate; a light transmissive member having a plate shape and having an upper face and a lower face that is larger than the upper face, disposed such that the lower face opposes a light emission face of the light emitting element; a light reflecting member covering lateral faces of the light transmissive member; and a light shielding frame covering lateral faces of the light transmissive member via the light reflecting member. The light shielding frame has an opening. An outer perimeter of the lower face of the light transmissive member is positioned outward of an inner perimeter of the opening in a plan view as seen from above. |
| US10957819B2 |
Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure
A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase. |
| US10957813B2 |
Method for producing optoelectronic semiconductor components and optoelectronic modules, and optoelectronic semiconductor component and optoelectronic module
In an embodiment, a method for producing a plurality of optoelectronic semiconductor components is disclosed, wherein the method includes inserting a plurality of optoelectronic semiconductor chips with a suitable orientation into a linear feeding device, conveying the optoelectronic semiconductor chips to an injection device having an outlet opening, encapsulating the optoelectronic semiconductor chips with at least one cladding layer in the injection device and pressing the encapsulated optoelectronic semiconductor chips out of the outlet opening, wherein a compound of optoelectronic semiconductor chips is formed in which the optoelectronic semiconductor chips are connected to one another by the at least one cladding layer and separating the compound into a plurality of optoelectronic semiconductor components each component having an optoelectronic semiconductor chip which is at least partially encapsulated by the at least one cladding layer. |
| US10957811B2 |
Ultra-broad spectrum detector integrated with functions of two-dimensional semiconductor and ferroelectric material
An ultra-broad spectrum detector integrated with functions of a two-dimensional semiconductor and a ferroelectric material, where the device includes a substrate, a two-dimensional semiconductor, a source electrode, a drain electrode, a ferroelectric material and a gate electrode; the two-dimensional semiconductor, the source electrode and the drain electrode are arranged on an upper surface of the substrate, and the source electrode and the drain electrode are respectively arranged at two ends of an upper surface of the two-dimensional semiconductor; two sides of the two-dimensional semiconductor are respectively connected with the lower-layer metal of the source electrode and the lower-layer metal of the drain electrode; the ferroelectric material is arranged on the upper surfaces of the two-dimensional semiconductor, the source electrode and the drain electrode; and the lower surface of the gate electrode is connected with the upper surface of the ferroelectric material. |
| US10957807B2 |
PLZT thin film capacitors apparatus with enhanced photocurrent and power conversion efficiency and method thereof
The exemplified systems, and method thereof, includes PLZT thin film (Pb0.95La0.05Zr0.54Ti0.46O3) paired with a bottom metal and top transparent conductive oxide, that forms a capacitor structure with enhanced photocurrent and power conversion efficiency. The exemplified systems use metal electrode (platinum) as bottom electrode and a transparent oxide (Indium Tin Oxide—ITO) as the top electrode. In some embodiments, the capacitor structure are used in a solar cells, ultraviolet sensors, or UV indexing sensors. In some embodiments, the capacitor structure are energy generation or for medical diagnostics (e.g., for skin care application). |
| US10957806B2 |
Monolithically integrated high voltage photovoltaics with textured surface formed during the growth of wide bandgap materials
A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands. |
| US10957802B2 |
Methods of forming tight pitch stack nanowire isolation
Methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanoset is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to form gate structure. |
| US10957800B2 |
Semiconductor device
A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer. |
| US10957798B2 |
Nanosheet transistors with transverse strained channel regions
A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack. |
| US10957795B2 |
Vertical field effect transistor having two-dimensional channel structure
A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided. |
| US10957792B2 |
Semiconductor device with latchup immunity
A semiconductor device includes a body region of a second conductivity type, a body contact region of the second conductivity type formed in the body region and having a higher average doping concentration than the body region, a source region of a first conductivity type opposite the second conductivity type formed in the body region adjacent the body contact region, a drift zone of the first conductivity type spaced apart from the source region by a section of the body region which forms a channel region of the semiconductor device, and a gate electrode configured to control the channel region. The body contact region extends under a majority of the source region in a direction towards the channel region and has a doping concentration of at least 1e18 cm−3 under the majority of the source region. Additional semiconductor device embodiments and methods of manufacture are described. |
| US10957791B2 |
Power device with low gate charge and low figure of merit
A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell. |
| US10957780B2 |
Non-uniform gate dielectric for U-shape MOSFET
A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance. |
| US10957777B2 |
Semiconductor structure and manufacturing method thereof
A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess. |
| US10957776B2 |
Method of fabricating MOSFET
A method for fabricating MOSFET is disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon. |
| US10957773B1 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions. The semi-insulating layer contacts the second electrode, the first conductive layer, and the third electrode. |
| US10957771B2 |
Transistor device with a field electrode that includes two layers
Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. The field electrode includes a first layer and a second layer. The second layer includes a different conductive material as the first layer. A portion of the second layer is disposed above and directly contacts a portion of the first layer. |
| US10957770B2 |
Method for manufacturing compound semiconductor device
A semiconductor layer (2,3) is provided on a substrate (1). A gate electrode (4), a source electrode (5) and a drain electrode (6) are provided on the semiconductor layer (3). A first passivation film (7) covers the gate electrode (4) and the semiconductor layer (3). A source field plate (9) is provided on the first passivation film (7), and extends from the source electrode (5) to a space between the gate electrode (4) and the drain electrode (6). A second passivation film (10) covers the first passivation film (7) and the source field plate (9). An end portion on the drain electrode (6) side of the source field plate (9) is curved to be rounded. |
| US10957766B2 |
Fin-based strap cell structure
Fin-based well straps are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin structure doped with a first dopant concentration of the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin structure doped with a second dopant concentration of the first type dopant and second source/drain features of the first type dopant. The second dopant concentration is greater than (for example, at least three times greater than) the first dopant concentration. |
| US10957763B2 |
Gate fill utilizing replacement spacer
A semiconductor structure includes a substrate and a channel stack disposed over a portion of a top surface of the substrate, the channel stack including two or more nanosheet channels, inner spacers disposed above and below outer edges of the two or more nanosheet channels, work function metal disposed between the inner spacers above and below each of the two or more nanosheet channels, and a dielectric layer disposed between the work function metal and the inner spacers and two or more nanosheet channels. The semiconductor structure further includes source/drain regions disposed over the top surface of the substrate surrounding the channel stack and a gate region disposed over a top surface of the channel stack, the gate region including the work function metal and a gate metal disposed over the work function metal. The semiconductor structure further includes a capping layer and contacts. |
| US10957761B2 |
Electrical isolation for nanosheet transistor devices
Self-limiting cavities are formed within a crystalline semiconductor substrate and beneath a stack of semiconductor layers used to form a nanosheet transistor device. Inner ends of the cavities merge beneath the stack while the outer ends thereof adjoin isolation regions within the substrate. The cavities are filled with electrically insulating material to provide bottom device isolation. Source/drain regions are grown in vertical trenches extending through the stack of semiconductor layers following formation of dielectric inner spacers. The bottom ends of the trenches adjoin the electrically insulating material within the cavities. |
| US10957758B2 |
Semiconductor device
To improve the turn-off withstand capability of a semiconductor device. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the semiconductor substrate and through which current flows between upper and lower surfaces of the semiconductor substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion, and arrayed next to the transistor portion along a predetermined array direction in a top view of the semiconductor substrate; and an edge termination structure portion provided between a peripheral end of the semiconductor substrate and the active portion in the top view. In the top view, at at least part of the edge termination structure portion, which part facing the transistor portion in the direction of extension orthogonal to the array direction, a first-conductivity type first cathode region is provided in contact with the lower surface. |
| US10957753B2 |
Display device
A display device includes a substrate including an outer area neighboring a border; and an insulating layer positioned over the substrate and including a plurality of openings positioned over the outer area. The openings are arranged to be spaced from each other in a direction. The display device further includes a wavy line extending in the direction and passing the plurality of openings. |
| US10957747B2 |
Electronic panel and method for manufacturing the same
An electronic device includes an electronic panel including an active area and a pad area and including an input sensing member and a circuit board overlapping at least a side of the pad area. The electronic panel includes a first conductive layer, a second conductive layer, a first organic insulation layer disposed between the first conductive layer and the second conductive layer, a pattern layer disposed on the second conductive layer, overlapping the plurality of second conductive patterns, and including a plurality of organic patterns, and a second organic insulation layer covering the pattern layer and the second conductive layer. The pattern layer covers an upper surface of the second conductive layer. |
| US10957745B2 |
Touch display device
A touch display device includes a display panel including a plurality of first pixels and a plurality of second pixels alternately disposed along a first direction, and a touch screen layer disposed on the display panel, the touch screen layer including a plurality of first touch electrodes having a zigzag shape and disposed between one of the first and second pixels along a second direction crossing the first direction, in which a first pixel of the first pixels and a second pixel of the second pixels have different sizes from each other, and a first distance from a first touch electrode of the first touch electrodes to the first pixel is different from a second distance from the first touch electrode to the second pixel. |
| US10957743B2 |
Optoelectronic array device having an upper transparent electrode
A matrix-array optoelectronic device includes a substrate on which a matrix array of what are called bottom electrodes is deposited; an active structure, which is preferably continuous and organic, arranged above the matrix-array of bottom electrodes, the structure being suitable for detecting light; and at least one what is called top electrode lying above the active structure, the top electrode being transparent to the light emitted or detected by the active structure; and at least one conductive element that is borne by the substrate without interposition of the active structure and that is connected to the top electrode by at least one vertical interconnection, the conductive element having an electrical conductivity greater than that of the top electrode. The device may also comprise a layer made of scintillator material, the layer being fastened to the top electrode, so as to form an x-ray imager. |
| US10957741B2 |
Multitier arrangements of integrated devices, and methods of forming sense/access lines
Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements. |
| US10957740B2 |
Memory device and method of manufacturing the same
A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer. |
| US10957739B2 |
Resistance variation element, semiconductor device, and manufacturing method
Provided is a resistance variation element including a resistance variation film of a metal depositing type, a first electrode which contacts with a first surface of the resistance variation film in a predetermined first region and supplies metallic ions via the first region, and a second electrode laminated on a second surface of the resistance variation film. The first region includes a recessed region surrounded by a simple closed curve or a region surrounded by a plurality of simple closed curves. A line segment which passes through a point outside of the first region, ends of which exist on the simple closed curve, and each point of which in the vicinity of both the ends other than both the ends is outside of the first region, exists, and an edge of the first electrode is formed in a part of the simple closed curve including both the ends. |
| US10957735B2 |
LED display
An LED display includes a wafer-level substrate, a first adhesive layer, a plurality of first light-emitting assemblies, and a first conductive structure. The wafer-level substrate includes a plurality of control circuits, each of which has a conductive contact. The first adhesive layer is disposed on the wafer-level substrate. Each first light-emitting assembly includes a plurality of first LED structures disposed on the first adhesive layer. The first conductive structure is electrically connected between the corresponding first LED structure and the control circuit. Thereby, each first light-emitting assembly including a plurality of first LED structures and a wafer-level substrate having a plurality of control circuits can be connected to each other through a first adhesive layer. |
| US10957728B2 |
CMOS image sensor structure with crosstalk improvement
A semiconductor device includes a semiconductor substrate, a device layer over the semiconductor substrate, a first color filter in a top surface of the device layer and adjacent to an edge of the device layer, and a second color filter in the top surface of the device layer. The second color filter has substantially the same thickness and the same color as the first color filter. |
| US10957724B2 |
Single-photon avalanche diode image sensor with photon counting and time-of-flight detection capabilities
A back side illuminated image sensor may operate using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation for single photon detection. The image sensor may be implemented using two layer stacking with a silicon on insulator (SOI) chip. The chip-to-chip electrical connections between the top level image sensing chip and the second level ASIC circuit chip may be realized at each pixel with a single bump connection per pixel. A light level signal may be obtained from pixels that have photon counting capabilities while a distance measurement signal for 3-dimensional imaging may be obtained from pixels that have time-of-flight (ToF) detection capabilities. Both types of pixels may be integrated within the same array and use the same SPAD structure placed on the top chip. |
| US10957721B1 |
Manufacturing method for CMOS LTPS TFT substrate
The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability. |
| US10957717B2 |
Pixel array
A pixel array includes first signal lines, second signal lines, active components, pixel electrodes, and selection lines. The second signal lines are intersected with and electrically insulated to the first signal lines. Each active component is electrically connected to one of the first signal lines and one of the second signal lines. Each pixel electrode is electrically connected to one of the active components. The selection lines are intersected with the first signal lines to form a plurality of first intersections and second intersections. The selection lines are electrically connected to the first signal lines at the first intersections but electrically insulated to the first signal lines at second intersections. The selection lines are electrically insulated to the second signal lines. At least one of the second signal lines is disposed between each selection line and any one of the active components. |
| US10957716B2 |
Array substrate, liquid crystal display panel, and organic electroluminescence display panel
An array substrate includes a gate line including a first metal film being arranged on an upper layer side through a first insulating film with respect to a semiconductor film, a source line including a second metal film arranged on a lower layer side through a second insulating film with respect to the semiconductor film and intersecting the gate line, a gate electrode including the first metal film, a channel region including a part of the semiconductor film and superimposing the gate electrode, a source region and a drain region formed by reducing a resistance of a part of the semiconductor film, and a source superimposing line formed by reducing a resistance of a part of the semiconductor film, continued to the source region and having at least one part superimposed with the source line, the source superimposing line being connected to the source line through contact holes opened and formed at a plurality of positions sandwiching the gate line of the second insulating film. |
| US10957710B2 |
Three dimensional semiconductor memory including pillars having joint portions between columnar sections
According to one embodiment, a semiconductor memory includes a plurality of conductors stacked with insulators being interposed therebetween and a pillar through the plurality of conductors. The pillar includes a first columnar section, a second columnar section, and a joint portion between the first columnar section and the second columnar section. The pillar comprises portions that cross the respective conductors and that each function as part of a transistor. The plurality of conductors include a first conductor. The first conductor is closest to the joint portion among the plurality of conductors through the second columnar section, and includes a bending portion formed along the joint portion. |
| US10957709B2 |
Systems including memory cells on opposing sides of a pillar
Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a NAND architecture. The array includes a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell curving around a first curved side of a substantially vertical pillar and terminating at an isolation region, and a plurality of series-coupled second non-volatile memory cells, each second non-volatile memory cell curving around a second curved side of the substantially vertical pillar and terminating at the isolation region. Respective ones of the first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells. |
| US10957706B2 |
Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same
A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack. |
| US10957705B2 |
Three-dimensional memory devices having a multi-stack bonded structure using a logic die and multiple three-dimensional memory dies and method of making the same
A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically coupled to nodes of the array of first memory stack structures through a first subset of first metal interconnect structures included within the first memory die. A second memory die is bonded to the first memory die. The second memory die includes an array of second memory stack structures. The CMOS circuit includes a second peripheral circuitry electrically coupled to nodes of the array of second memory stack structures through a second subset of first metal interconnect structures included within the first memory die and through second metal interconnect structures included within the second memory die. The logic die provides peripheral devices that support operation of memory stack structures in multiple memory dies. |
| US10957699B2 |
Integrated assemblies which include two different types of silicon nitride, and methods of forming integrated assemblies
Some embodiments include an integrated assembly which has bitline structures that extend along a first direction. The bitline structures include conductive bitlines, and include insulative shells which extend over the conductive bitlines and along sidewalls of the conductive bitlines. The insulative shells include a first silicon nitride composition. The bitline structures are spaced from one another by intervening regions. Semiconductor structures and insulative spacers are within the intervening regions. The semiconductor structures and insulative spacers alternate with one another along the first direction. The insulative spacers include a second silicon nitride composition which is characterized as having a faster etch rate than the first silicon nitride composition by a mixture which contains sulfuric acid and hydrogen peroxide. Some embodiments include methods of forming integrated assemblies. |
| US10957697B2 |
Polysilicon structure including protective layer
A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers. |
| US10957696B2 |
Self-aligned metal gate with poly silicide for vertical transport field-effect transistors
A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET). |
| US10957695B2 |
Asymmetric gate pitch
The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures. |
| US10957692B2 |
Asymmetric transient voltage suppressor device and methods for formation
A transient voltage suppression (TVS) device, may include: a substrate base formed in a substrate, the substrate base comprising a semiconductor of a first conductivity type; and an epitaxial layer, disposed on the substrate base, on a first side of the substrate, and comprising a semiconductor of a second conductivity type. The epitaxial layer may include: a first portion, the first portion having a first layer thickness; and a second portion, the second portion having a second layer thickness, less than the first layer thickness, wherein the first portion and the second portion are disposed on a first side of the substrate, and wherein the first portion is electrically isolated from the second portion. |
| US10957681B1 |
Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array
Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry. |
| US10957675B2 |
Lighting-emitting device filament
A light emitting device filament includes a substrate having a first surface and a second surface opposite to the first surface and extending in one direction, at least one light emitting device chip disposed on the first surface, and an auxiliary pattern disposed on the second surface and disposed at a position corresponding to the light emitting device chip. |
| US10957672B2 |
Package structure and method of manufacturing the same
A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant. |
| US10957670B2 |
Package-on-package and package connection system comprising the same
An electronic component module includes a semiconductor package having a first surface provided as a mounting surface and a second surface opposing the first surface, and including a semiconductor chip, a component package having a first surface facing the second surface of the semiconductor package, and a second surface opposing the first surface of the component package, the component package including a passive component, and a connector disposed on the second surface of the component package and having a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface. |
| US10957666B2 |
Pre-molded leadframes in semiconductor devices
In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed. |
| US10957665B2 |
Direct C4 to C4 bonding without substrate
A method for manufacturing a 3D integrated circuit is provided. A manufacturing system provides a first integrated circuit having a first surface and a first via extending to the first surface. The manufacturing system applies a first controlled collapse chip connection (C4) solder bump to the first via. The manufacturing system provides a second integrated circuit having a second surface and a second via extending to the second surface. The manufacturing system applies a second C4 solder bump to the second via. The manufacturing system overturns the second integrated circuit onto the first integrated circuit and aligns the first C4 solder bump with the second C4 bump. The manufacturing system heats the first C4 solder bump and the second C4 solder bump until the first via contact is soldered to the second via. |
| US10957663B2 |
Spoked solder pad to improve solderability and self-alignment of integrated circuit packages
A center pad or paddle that is shaped with three or more curved spires which are symmetrical in form about axis that radiate from the center of the integrated circuit package, which takes advantage of the surface tension of solder to produce increased rotational align forces and increased centering forces during package soldering when aligned to a matching shaped pad on the surface of a circuit board. |
| US10957662B2 |
Semiconductor package
A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved. |
| US10957655B2 |
Integrated circuit with inductors having electrically split scribe seal
An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion. |
| US10957653B2 |
Methods for manufacturing semiconductor arrangements using photoresist masks
Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region. |
| US10957651B2 |
Package level power gating
A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated. |
| US10957650B2 |
Bridge support structure
A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads. |
| US10957644B2 |
Integrated structures with conductive regions having at least one element from group 2 of the periodic table
Some embodiments include an integrated structure having a conductive region which contains one or more elements from Group 2 of the periodic table. Some embodiments include an integrated structure which has a conductive region over and directly against a base material. The conductive region includes one or more elements from Group 2 of the periodic table, and has a pair of opposing sidewalls along a cross-section. A capping material is over and directly against the conductive region. Protective material is along and directly against the sidewalls of the protective region. |
| US10957641B2 |
Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium. |
| US10957636B2 |
Semiconductor device
A semiconductor device includes leads, a switching element, a control element that controls the switching element, and a resin member covering the switching element, the control element and parts of the respective leads. The leads include a drain lead connected to a drain electrode of the switching element, a source lead connected to a source electrode of the switching element, and at least one control lead connected to the control element. The resin member includes a drain exposed portion at which the drain lead is exposed, a source exposed portion at which the source lead is exposed, and a control exposed portion at which the control lead is exposed. The distance in a first direction between the drain exposed portion and the source exposed portion is larger than the distance in the first direction between the control exposed portion and the source exposed portion. |
| US10957631B2 |
Angled die pad of a leadframe for a molded integrated circuit package
A leadframe comprising a plurality of leads, each of the plurality of leads having a proximal end and a distal end opposite the proximal end, the distal ends positioned along a linear axis. The leadframe further comprises a die pad closer to the proximal ends than the distal ends of the plurality of leads and including an edge positioned along a plane that intersects the linear axis at an angle less than 90 degrees. |
| US10957624B2 |
Micro heat transfer arrays, micro cold plates, and thermal management systems for cooling semiconductor devices, and methods for using and making such arrays, plates, and systems
Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal management systems including cold-plates, pumps and heat exchangers. These devices and systems may be used to provide cooling of semiconductor devices and particularly such devices that produce high heat concentrations. The heat transfer arrays may include microjets, microchannels, fins, and even integrated microjets and fins. |
| US10957617B2 |
Semiconductor device
A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin. |
| US10957611B2 |
Semiconductor package including lid structure with opening and recess
A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die. |
| US10957608B2 |
Guided scanning electron microscopy metrology based on wafer topography
A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about the wafer, which was obtained with the wafer topography measurement system. A metrology sampling plan can be generated for the wafer. This metrology sampling plan can include locations in the wafer topography data above the topography threshold. The scanning electron microscope can scan the wafer using the metrology sampling plan and identify defects. |
| US10957606B2 |
Manufacturing method of complementary metal oxide semiconductor transistor and manufacturing method of array substrate
Disclosed is a manufacturing method of a complementary metal oxide semiconductor transistor, comprising a step of implementing a channel doping to an N-type channel region. The step comprises: preparing a low temperature polysilicon layer on a substrate, and patterning the low temperature polysilicon layer to form the N-type channel region correspondingly above a light shielding pattern; coating a negative photoresist on the substrate, and using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate to form a negative photoresist mask plate exposing the N-type channel region after development; implementing the channel doping to the N-type channel region with shielding of the negative photoresist mask plate. Further disclosed is a manufacturing method of an array substrate, applied with the aforesaid manufacturing method of the complementary metal oxide semiconductor transistor. |
| US10957605B2 |
VFET device design for top contact resistance measurement
The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided. |
| US10957601B2 |
Self-aligned fin recesses in nanosheet field effect transistors
Semiconductor devices and methods of forming the same include etching a stack of alternating channel and sacrificial layers to form a fin. The etch depth is controlled by a signal layer embedded in a substrate under the stack. Source and drain regions are formed on ends of the channel layers. The sacrificial layers are etched away and a gate stack is formed over and between the channel layers. |
| US10957596B2 |
Caterpillar trenches for efficient wafer dicing
A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening within a mask formed on a substrate to protect an electronics device disposed on the substrate during isotropic etching, and isotropically etching through the at least one opening to form at least one wafer dicing channel, including laterally etching a collection of nested trenches including trenches each having a non-circular cross-section from a first surface of the substrate to a second surface of the substrate opposite the first surface. |
| US10957595B2 |
Systems and methods for precision fabrication of an orifice within an integrated circuit
A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique. |
| US10957594B2 |
Manufacturing method of semiconductor chip
A manufacturing method of a semiconductor chip is provided. The method includes: forming a first metal pattern over a substrate and within a chip region and a scribe line region of the substrate, wherein the chip region is surrounded by the scribe line region; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all portions of the metal material layer within the scribe line region and a portion of the metal material layer within the chip region, so as to form a second metal pattern within the chip region; forming a third metal pattern, wherein the second metal pattern within the chip region is covered by the third metal pattern, and the third metal pattern is located over the first metal pattern within the scribe line region; and performing singulation along the scribe line region, to form the semiconductor chip. |
| US10957591B2 |
Process of forming semiconductor device
A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) on a secondary surface of the substrate and within a substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate. |
| US10957590B2 |
Method for forming a layer
Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved. |
| US10957587B2 |
Structure and formation method of semiconductor device with conductive feature
A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material. |
| US10957585B2 |
Semiconductor device and method of forming the same
A method is provided. Plural semiconductor fins are formed on a substrate, and plural trenches each of which is formed between two adjacent semiconductor fins. A silicon liner layer is deposited to be conformal to the semiconductor fins and the trenches. The silicon liner layer is deposited by using a silane compound. Then, an oxide layer is deposited on the silicon liner layer to fill the trenches and cover the semiconductor fins, in which depositing the oxide layer forms water in the oxide layer. Next, a surface of the silicon liner layer is reacted with the water, so as to remove the water from the oxide layer. |
| US10957582B2 |
Self aligned via and pillar cut for at least a self aligned double pitch
A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening. |
| US10957579B2 |
Integrated circuit devices including a via and methods of forming the same
Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a first conductive layer on a substrate and selectively forming a second insulating layer on the first insulating layer. The first insulating layer may include a recess, and the first conductive layer may be in the recess of the first insulating layer. The second insulating layer may include a first opening exposing a surface of the first conductive layer. The methods may also include forming a third insulating layer on the second insulating layer and the first conductive layer, forming a second opening extending through the third insulating layer and exposing the first conductive layer, and forming a second conductive layer in the second opening. |
| US10957570B2 |
Article storage facility
An advancing/retracting mechanism includes a first arm, a second arm, a first coupling part that couples the first arm and the second arm, and a second coupling part that couples a supporting body and the first arm. A transfer device is configured to move the supporting body back and forth with the first coupling part located on a first side relative to the second coupling part, by rotating the first arm and the second arm. In a first region, which is a region in the depth direction and includes an end on the front side of the rack body, a distance from the width directional center to the first supporting portion is longer than a distance from the width directional center to the second supporting portion. |
| US10957569B2 |
Access to one or more levels of material storage shelves by an overhead hoist transport vehicle from a single track position
An improved automated material handling system that allows an overhead hoist supported by a suspended track to access Work-In-Process (WIP) parts from storage locations beside the track. The automated material handling system includes an overhead hoist transport vehicle for transporting an overhead hoist on a suspended track, and one or more storage bins for storing WIP parts located beside the track. Each storage bin is either a movable shelf or a fixed shelf. To access a WIP part from a selected shelf, the overhead hoist transport vehicle moves along the suspended track to a position at the side of the shelf. Next, the movable shelf moves to a position underneath the overhead hoist. Alternatively, overhead hoist moves to a position above the fixed shelf. The overhead hoist is then operated to pick a desired WIP part directly from the shelf, or to place one or more WIP parts directly to the shelf. Once the WIP part is held by the overhead hoist, the overhead hoist transport vehicle moves the WIP part to a workstation or processing machine on the product manufacturing floor. |
| US10957567B2 |
Method, computer program product and system for detecting manufacturing process defects
A system, computer program product and a method for detecting manufacturing process defects, the method may include: obtaining multiple edge measurements of one or more structural elements after a completion of each one of multiple manufacturing phases; generating spatial spectrums, based on the multiple edge measurements, for each one of the multiple manufacturing phases; determining relationships between bands of the spatial spectrums; and identifying at least one of the manufacturing process defects based on the relationships between the bands of the spatial spectrums. |
| US10957566B2 |
Wafer-level inspection using on-valve inspection detectors
A system and method for wafer-level inspection using on-valve inspection detectors to detect defects on a semiconductor wafer surfaces during a semiconductor device manufacturing process is disclosed herein. In some exemplary embodiments, a method for wafer-level inspection includes: transporting a semiconductor wafer through a transfer port of a processing chamber; scanning a surface of the semiconductor wafer automatically using at least one on-valve inspection detector arranged on a vacuum valve providing access through the transfer port; generating at least one surface image of the surface of the semiconductor wafer; and analyzing the at least one surface image to detect defects on the surface of the semiconductor wafer. |
| US10957561B2 |
Gas delivery system
A gas delivery system for a substrate processing system includes a first manifold and a second manifold. A gas delivery sub-system selectively delivers gases from gas sources. The gas delivery sub-system delivers a first gas mixture to the first manifold and a second gas mixture. A gas splitter includes an inlet in fluid communication with an outlet of the second manifold, a first outlet in fluid communication with an outlet of the first manifold, and a second outlet. The gas splitter splits the second gas mixture into a first portion at a first flow rate that is output to the first outlet and a second portion at a second flow rate that is output to the second outlet. First and second zones of the substrate processing system are in fluid communication with the first and second outlets of the gas splitter, respectively. |
| US10957556B2 |
Nonvolatile semiconductor memory device and method of manufacturing the same
According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded. |
| US10957555B2 |
Processing method for producing photomask with double patterns and storage medium thereof
A process method for producing a photomask with double patterns. The processing method includes obtaining a contact distribution pattern, having multiple contacts. The contacts are sorted into multiple contact blocks in array type, pair type and isolation type. The contacts are decomposed into a first patterning group and a second patterning group, which are configured to interpose to each other. The numbers of contacts of the first patterning group and the second patterning group are equal within an error range. The first patterning group and the second patterning group are check whether or not having adjacent two contacts with a distance less than a minimum distance. If it is less than a minimum distance, one of the adjacent two contacts is changed from a current one of the first patterning group and the second patterning group to another. The first/second patterning groups are output to from first/second photomasks. |
| US10957551B2 |
Fin-like field effect transistor patterning methods for increasing process margins
Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof). |
| US10957550B2 |
Semiconductor structure and formation method thereof
A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region. |
| US10957549B2 |
Methods of forming semiconductor devices using mask materials, and related semiconductor devices and systems
A method of forming a semiconductor device comprises patterning a mask material adjacent to an array of transistors, forming an electrically conductive material between adjacent portions of the patterned mask material, forming an additional mask material over the patterned mask material to form a mask structure, the additional mask material having an arcuate cross-sectional shape, removing a portion of the additional mask material to reduce a spacing between adjacent portions of the additional mask material, and forming capacitor structures in openings between the mask structure. Additional methods of forming a semiconductor device, and related semiconductor devices and related systems are also disclosed. |
| US10957548B2 |
Method of etching copper indium gallium selenide (CIGS) material
Methods for dry plasma etching thin layers of material including Cu(In, Ga)Se, e.g., CIGS material on semiconductor substrates are provided. A method of etching a CIGS material layer such as copper indium gallium selenide film, includes: flowing an etching gas including a mixture of gases into a process chamber having a substrate disposed therein, the substrate including a copper indium gallium selenide layer having a patterned film stack disposed thereon, the patterned film stack covering a first portion of the copper indium gallium selenide layer and exposing a second portion of the copper indium gallium selenide layer; and contacting the copper indium gallium selenide layer with the etching gas to remove the second portion and form one or more copper indium gallium selenide edges of the first portion. |
| US10957542B2 |
Method of processing wafer
A method of processing a wafer includes a grinding step of grinding a reverse side of a wafer that has first insulating films covering via electrodes, an electrode protruding step of protruding the via electrodes covered with the first insulating films from the reverse side by supplying a first etching gas turned to a plasma, an insulating film forming step of covering the reverse side with a second insulating film, a via electrode exposing step of supplying a second etching gas turned to a plasma to expose the via electrodes after having formed a resist film having openings overlapping the via electrodes, and an electrode forming step of forming electrodes connected to the via electrodes. |
| US10957541B2 |
Short pulse fiber laser for LTPS crystallization
Laser pulses from pulsed fiber lasers are directed to an amorphous silicon layer to produce a polysilicon layer comprising a disordered arrangement of crystalline regions by repeated melting and recrystallization. Laser pulse durations of about 0.5 to 5 ns at wavelength range between about 500 nm and 1000 nm, at repetition rates of 10 kHz to 10 MHz can be used. Line beam intensity uniformity can be improved by spectrally broadening the laser pulses by Raman scattering in a multimode fiber or by applying varying phase delays to different portions of a beam formed with the laser pulses to reduce beam coherence. |
| US10957540B2 |
Semiconductor epitaxy bordering isolation structure
A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation. |
| US10957538B2 |
Method of forming and transferring thin film using SOI wafer and heat treatment process
The present invention relates to a method of forming and transferring a thin film. The method of forming and transferring a thin film according to one embodiment may include a step of bonding a carrier wafer coated with a polymer bonding material to the top of a silicon-on-insulator (SOI) wafer formed by sequentially laminating a backside silicon layer, a buried oxide layer, and a silicon layer; a step of etching the backside silicon layer using the buried oxide layer as an etching barrier, and then selectively etching the buried oxide layer; a step of separating the carrier wafer from the polymer bonding material, and bonding a target wafer including an oxide layer to the bottom of the silicon layer through direct bonding; and a step of transferring the silicon layer to the top of the target wafer including the oxide layer by removing the polymer bonding material. |
| US10957537B2 |
Methods to design and uniformly co-fabricate small vias and large cavities through a substrate
A method of forming concurrently openings in a substrate or wafer or a portion of substrate or wafer openings therein at least one of the openings has a relatively high aspect ratio and another one of the openings has a relatively low aspect ratio, the method comprising: bonding the substrate or wafer or a portion of substrate or wafer to a carrier substrate; forming a ring trench in the substrate or wafer or in a portion of the substrate or wafer, the ring trench having an outer perimeter that corresponds an outer perimeter of the another one of the openings having said relatively low aspect ratio and having an inner perimeter spaced from the outer perimeter by a predetermined distance; forming an opening in said substrate or wafer or in a portion of substrate or wafer having said high aspect ratio concurrently with the forming of the ring trench; and separating the substrate or wafer or in a portion of the substrate or wafer from the carrier substrate. |
| US10957533B2 |
Methods for etching a structure for semiconductor applications
Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate. |
| US10957532B2 |
Method and apparatus for deposition of low-k films
Methods and apparatus for forming a conformal SiOC film on a surface are described. A SiCN film is formed on a substrate surface and exposed to a steam annealing process to decrease the nitrogen content, increase the oxygen content and leave the carbon content about the same. The annealed film has one or more of the wet etch rate or dielectric constant of the film. |
| US10957530B2 |
Freezing a sacrificial material in forming a semiconductor
The present disclosure includes apparatuses and methods related to freezing a sacrificial material in forming a semiconductor. In an example, a method may include solidifying, via freezing, a sacrificial material in an opening of a structure, wherein the sacrificial material has a freezing point below a boiling point of a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to a particular temperature range. |
| US10957527B2 |
Mass analyzer
A mass analyzer for scanning sample gases is disclosed. The mass analyzer comprises an ionizer for generating ions from a sample; a mass filter with an accumulator section integrated in the mass filter and accumulates filtered ions prior to ejecting from the mass filter; and an ion detector that is configured to detecting ejected ions from the mass filter. The mass filter may include a quadrupole array and the accumulator section includes an ion trap array. |
| US10957525B2 |
Trap fill time dynamic range enhancement
A method of mass and/or ion mobility spectrometry is disclosed that comprises accumulating ions for a first period of time (T1) one or more times so as to form one or more first groups of ions, accumulating ions for a second period of time (T2) one or more times so as to form one or more second groups of ions, wherein the second period of time (T2) is less that the first period of time (T1), analysing the one or more first groups of ions to generate one or more first data sets, analysing the one or more second groups of ions to generate one or more second data sets, and determining whether the one or more first data sets comprise saturated and/or distorted data. If it is determined that the one or more first data sets comprise saturated and/or distorted data, then the method further comprises replacing the saturated and/or distorted data from the one or more first data sets with corresponding data from the one or more second data sets. |
| US10957523B2 |
3D mass spectrometry predictive classification
A method for analyzing a multidimensional data set includes generating a multidimensional mass spectrometry data set from a sample; and generating an matrix representing the multidimensional mass spectrometry data set such that a first dimension and a second dimension of the multidimensional mass spectrometry data set correspond to a matrix cell location, and an ion intensity corresponds to a matrix cell value; and determining a class of the matrix from a plurality of matrix classes using a trained neural network matrix classifier. |
| US10957522B2 |
Electron multiplier production method and electron multiplier
An electron multiplier production method including a main body portion, and a channel provided in the main body portion to open at one end surface and the other end surface of the main body portion and emits secondary electrons includes a first step of preparing a main body member including the one end surface and the other end surface, a communicating hole for the channel through which the one end surface and the other end surface communicate being provided in the main body member, a second step of forming the channel by forming a deposition layer including at least a resistive layer on an outer surface of the main body member and an inner surface of the communicating hole using an atomic layer deposition method, and a third step of forming the main body portion by removing the deposition layer formed on the outer surface of the main body member. |
| US10957520B2 |
Long-life high-power terminals for substrate support with embedded heating elements
A connection terminal for a heating element of a substrate support in a substrate processing system include a contact plate configured to be electrically connected to a contact pad of the heating element within a ceramic layer of the substrate support. A wire connection portion extends from the contact plate and is configured to receive and retain a wire arranged to provide electrical power to the heating element. At least one of the contact plate and the wire connection portion comprises a first material having a first coefficient of thermal expansion (CTE) that is within 20% of a second CTE of the ceramic layer. |
| US10957518B2 |
Chamber with individually controllable plasma generation regions for a reactor for processing a workpiece
A plasma reactor includes a processing chamber having a lower processing portion having an axis of symmetry and an array of cavities extending upwardly from the lower processing portion. A gas distributor couples plural gas sources to a plurality of gas inlets of the cavities, and the gas distributor includes a plurality of valves with each valve selectively connecting a respective gas inlet to one of the plural gas sources. Power is applied by an array of conductors that includes a respective conductor for each respective cavity with each conductor adjacent and surrounding a cavity. A power distributor couples a power source and the array of conductors, and the power distributor includes a plurality of switches with a switch for each respective conductor. |
| US10957517B2 |
Substrate treating apparatus and temperature control method for gas distribution plate
Disclosed is a substrate treating apparatus including a chamber having a process space therein in which a substrate is treated, a substrate support assembly located in the chamber and including a support plate that supports the substrate, a gas supply unit that supplies gas into the chamber, a gas distribution plate that distributes the gas and supplies the gas into the process space, and a temperature control unit that controls temperature of the gas distribution plate. The temperature control unit includes a heating member that heats the gas distribution plate, a cooling member that cools the gas distribution plate, and a control member that controls the heating member and the cooling member, based on a correlation coefficient regarding an interaction of the heating member and the cooling member and a disturbance coefficient regarding an external influence. |
| US10957510B2 |
Device for generating a source current of charge carriers
A device for generating a source current of charge carriers and a method for stabilizing a source current of charge carriers are disclosed. In an embodiment the device includes at least one field emission element configured to emit charge carriers, which lead to an emission current in the field emission element, at least one extraction electrode configured to apply an extraction voltage in order to extract the charge carriers from the field emission element, wherein a first part of the extracted charge carriers contributes to the source current, and a second part of the extracted charge carriers impinges on the extraction electrode and leads to an extraction current in the extraction electrode and a control device configured to reduce fluctuations of a controlled variable Q which is a characteristic for the source current, wherein Q is a function of a difference between the emission current and the extraction current. |
| US10957507B2 |
Mechanism for indirect access to an actuator on an apparatus disposed within a housing
The present disclosure envisages a mechanism (100) for indirect access to an actuator (210) on an apparatus (200) disposed within a housing (300). The mechanism (100) comprises a bushing (10), a spring-loaded shaft (20), an arm (30), a first stopper (40) and a pedestal (50). The spring-loaded shaft (20) passes through the bushing (10) and is configured to reciprocate through the annular passage (12). An arm (30) is disposed within the housing (300), and is coupled to the shaft (20). The first stopper (40) is received on the shaft (20) operatively below the arm (30). The pedestal (50) is disposed between the arm (30) and the first stopper (40). The pedestal (50) is configured to facilitate abutment of the arm (30) with the actuator (210). The arm (30) is configured to press the actuator (210) when the shaft (20) is linearly displaced. |
| US10957505B2 |
Disconnect switch assemblies with a shared actuator that concurrently applies motive forces in opposing directions and related circuit breakers and methods
A disconnect switch assembly includes first and second disconnect switches with each of the first and second disconnect switch including a housing, a fixed main contact in the housing, and a movable main contact in the housing in cooperating alignment with the fixed main contact. Each of the movable main contacts is coupled to a (common) first actuator. A second actuator is coupled to the housing of the first disconnect switch and a third actuator is coupled to the housing of the second disconnect switch. The first actuator is configured to concurrently apply first and second motive forces (in opposing but in-line directions) to the movable contacts of the first and second disconnect switches. The second and third actuators are configured to apply a motive force to the housings that is in a direction opposing a respective motive force applied by the first actuator to the movable main contacts. |
| US10957500B2 |
Keyboard backlighting with reduced driver circuitry
Systems and methods for selective keyboard backlighting with reduced driver circuitry are provided. In one example embodiment, a method includes, inter alia, simultaneously controlling, with a control signal, an output of a first light emitting element that illuminates only one key of a plurality of keys of a keyboard and an output of a second light emitting element that illuminates only one key of the plurality of keys, and maintaining, with a current mirror circuit, uniformity between the output of the first light emitting element and the output of the second light emitting element. |
| US10957494B2 |
Solid electrolytic capacitor
A solid electrolytic capacitor including: a capacitor element including an anode part provided on a first end side, and a cathode part provided on a second end side opposite the first end, so as to be adjacent to the anode part; and a cathode lead connected to the cathode part. The capacitor element has, on a surface of the cathode part, either one or both of a first protective layer and a second protective layer, the first protective layer being electrically insulating and provided on the first end side, the second protective layer being electrically insulating and provided on the second end side. The cathode part and the cathode lead are connected to each other via an electrically conductive adhesive layer. |
| US10957491B2 |
Electrolytic capacitor-specific electrode member and electrolytic capacitor
An electrolytic capacitor-specific electrode member is used for an electrolytic capacitor, and formed in a wire shape. The electrolytic capacitor-specific electrode member has an outer surface including at least one or more first cavity portions opened to outside, and at least one or more second cavity portions opened at least to the first cavity portions. The second cavity portions are smaller in opening diameter represented by a circle equivalent diameter than the first cavity portions. |
| US10957489B2 |
Medium and method of manufacturing electronic component
A medium is accommodated in a container together with an electronic component body including an underlying electrode layer. The medium treats a surface of the underlying electrode layer while vibration is applied to the container. The medium is spherical or substantially spherical. The medium has a diameter not smaller than about 0.2 mm and not greater than about 2.0 mm. The medium contains tungsten. |
| US10957488B2 |
Multilayer ceramic electronic component
A multilayer ceramic electronic component includes: a ceramic body and first and second external electrodes on external surfaces of the ceramic body. The ceramic body includes first and second internal electrodes facing each other with dielectric layers interposed therebetween. The ceramic body includes an active portion in which capacitance is formed and cover portions on upper and lower surfaces of the active portion, respectively. The ratio of the thickness of the first and second external electrodes to the thickness of the cover portion is proportional to the inverse of the cube root of the ratio of the Young's Modulus of each of the first and second external electrodes to the Young's modulus of the cover portion. |
| US10957482B2 |
Manufacturing process for gradient coil sub-assemblies
An MRIS gradient coil sub-assembly comprising a first coil layer comprising a first conducting coil portion, a second coil layer comprising a second conductive coil portion electrically connected with the first conductive coil portion so that the first and second conductive coil portions act together as one coil, and a B-stage material consolidation layer sandwiched between the first and second coil layers. A method including laminating a first punched sheet metal conductive saddle coil portion and a second punched sheet metal conductive saddle coil portion together by bonding the first and second punched sheet metal conductive saddle coil portions on opposing sides of a B-stage material insulation layer, and electrically connecting the first punched sheet metal conductive saddle coil portion to the second punched sheet metal conductive saddle coil portion in parallel so that the first and second conductive saddle coil portions act together as one saddle coil. |
| US10957480B2 |
Large area power transmitter for wireless power transfer
A method and system for wireless power transfer are provided. The method includes adapting first and second variable form factor transmitters into at least first and second sets of cross-coupled segments, respectively, disposed about a pre-determined wireless power transfer area and spatially offset from one another by a preselected spatial offset that minimizes inductive coupling between the first and second sets of cross-coupled segments, transmitting, from first and second radio frequency (RF) power sources electrically coupled to the first and second sets of cross-coupled segments, respectively, RF power across the pre-determined wireless power transfer area via near electromagnetic fields of the variable form factor transmitters such that a magnetic field associated with the near electromagnetic fields rotates in a pattern having a preselected shape. |
| US10957479B2 |
Coil component
A coil component includes a first outer magnetic body, a first outer insulator, a first inner magnetic body, an inner insulator, a second inner magnetic body, a second outer insulator, and a second outer magnetic body stacked sequentially, and a coil in the inner insulator and an internal magnetic body inside the coil. Volumes A, B, C, and D of the first and second outer insulators, the inner insulator, the coil, and the internal magnetic body, respectively, and volume E of the first outer magnetic body, the first inner magnetic body, the second inner magnetic body, and the second outer magnetic body satisfy 0.05≤A≤0.07, 0.2≤B≤0.4, 0.01≤C≤0.08, 0.03≤D≤0.05, and 0.4≤E≤0.71, where 0.05B≤C≤0.2B and A+B+C+D+E=1. |
| US10957478B2 |
Electronic component
An electronic component includes insulator layers having first and second sides respectively extending in first and second directions from a first point, and outer conductor layers extends in the first and second direction from the first point. Each of the outer conductor layers has second and third points. One of the outer conductor layers has a fixing portion inside a region having a third side connecting the second and third points, and fourth and fifth sides respectively extending from the second point in the reverse first direction and from the third point in the reverse second direction. |
| US10957475B2 |
Coil component
A hybrid coil component in which a magnetic core generally included in a wire-wound type inductor and a core included in a multilayer type inductor are combined with each other. A winding coil may be wound around a magnetic core manufactured in advance and an encapsulant having a stacked structure of a plurality of magnetic sheets may encapsulate the winding coil wound around the magnetic core. In this case, a magnetic flux generated in the winding coil is arranged to be parallel to long axes of magnetic particles contained in the magnetic core and the encapsulant. |
| US10957473B2 |
Dual winding superconducting magnetic energy storage
A superconducting magnetic energy storage system (SMES). The SMES includes a toroidally wound super conducting magnet having a toroidal magnetic core with a charging winding and a discharging winding. The charging winding and discharging winding are wound on the toroidal magnetic core. The SMES also includes a DC power source, the DC power source operable to provide DC current to the charging winding of the toroidally wound superconducting magnet, and a modulator operably connected to the DC power source and the charging winding, the modulator operable to modulate at least a portion of the DC current applied to the charging winding of the superconducting magnet. The energy is stored in a magnetic field of the superconducting magnet by applying a current to the charging winding of the superconducting magnet, and energy is withdrawn from the magnetic field by a current flowing in the discharging winding. |
| US10957472B2 |
Method for manufacturing shunt resistor
A manufacturing method of shunt resistor according to the present invention includes a step of calculating a difference between an initial resistance value and a desired resistance value as a resistance value to be adjusted, a step of providing a plurality of recess forming members capable of forming recesses each having a characteristic size in the surface of a resistive alloy plate, a recess determining step of determining the size and the number of the recesses necessary to be formed at the surface of the resistive alloy plate, and a recess forming step of forming the recesses according to the size and the number determined in the recess determining step by using the corresponding recess forming members. |
| US10957465B2 |
Wire harness with sewing and manufacturing method of wire harness
The wire harness includes a sheathing member that is formed in a sheet shape, at least one electric wire that is arranged on a first principal surface side of the sheathing member, and a sewing thread that sews the electric wire to the sheathing member. A partial region of the sheathing member that is arranged along an extension direction of the electric wire is in a flat state, while another at least partial region of the sheathing member that is arranged along the extension direction of the electric wire is curved in a direction intersecting with the extension direction of the electric wire. |
| US10957455B2 |
Computer implemented identification of genetic similarity
A method, software, database and system for attribute partner identification and social network based attribute analysis are presented in which attribute profiles associated with individuals can be compared and potential partners identified. Connections can be formed within social networks based on analysis of genetic and non-genetic data. Degrees of attribute separation (genetic and non-genetic) can be utilized to analyze relationships and to identify individuals who might benefit from being connected. |
| US10957453B2 |
WCD system alert issuance and resolution
In one embodiment, a WCD is described. The WCD includes a support structure configured to be worn by a patient and a processor coupled to the support structure. The WCD also includes an energy storage module configured to store an electrical charge and in communication with the processor. The WCD also includes a discharge circuit coupled to the energy storage module, the discharge circuit in communication with the processor and configured to discharge the stored electrical charge through a body of the patient. The processor is configured to detect an event at the WCD, classify the detected event, and determine an alarm onset time of the detected event based at least in part on the event classification. The processor is further configured to issue the alarm after the alarm onset time. |
| US10957451B2 |
Patient healthcare interaction device and methods for implementing the same
Methods, apparatus, and systems are disclosed to improve selection of medical treatment. An example apparatus includes a user interface to receive health information for a patient and a data analyzer to access historical patient information stored in a database, and determine a condition based on comparing historical patient information stored in a database to the health information for the patient. The example apparatus includes a machine learning engine to recommend a treatment plan, including: a data analytic algorithm server to determine success rates of the treatment plan for the condition; and a model generator to generate a patient model, wherein the patient model predicts effects of the treatment plan. The example apparatus includes a communications interface to facilitate scheduling an appointment with a clinician. The example apparatus includes the user interface to receive health tracking information from the patient indicative of the treatment plan effectiveness and store the health tracking information. |
| US10957444B2 |
Apparatus for tomography repeat rate/reject rate capture
A system for capturing possible repeats or rejections of images occurring during tomographic imaging accommodates the wide variety of imaging protocols by providing groupings of common imaging protocol types and highlighting outliers of this grouping. The grouping may consider text descriptions of the images and their series, machine parameters such as tomographic and localizer scans, and overlap between images of any given series. |
| US10957440B2 |
Reusable disposable and dialysis apparatus therefor
The invention pertains to a reusable disposable (1) for usage within a medical treatment process by a corresponding medical apparatus (A) and a corresponding medical apparatus. The reusable disposable (1) for usage within a medical process by a medical apparatus (A), the reusable disposable (1) comprises first memory means (MEM1) for storing predetermined data, whereby the first memory means are programmed during production of the reusable disposable (1), whereby the first memory means (MEM1) are secured against any or any unauthorized alteration after production, second memory means (MEM2) for storing patient identity data, whereby the second memory means is a write-once memory, whereby re-usage of the reusable disposable is only allowed with respect to same patient identity data. |
| US10957439B2 |
Group performance monitoring system and method
The present invention provides group performance monitoring systems and methods. In one exemplary embodiment, a group monitoring device includes a display configured to display, during an athletic activity, a plurality of individual performance metrics relating to a plurality of individuals engaged in the athletic activity, each individual performance metric relating to one of the plurality of individuals; and an input to manipulate the display. |
| US10957438B2 |
Managing insulin administration
A method includes obtaining blood glucose measurements and blood glucose times of a patient from a blood glucose meter and executing a patient management program configured to display on a screen a graphical user interface having a trend window of the blood glucose measurements on the time line. The patient management program is configured to receive, in the trend window magnifying inputs for a magnification window superimposed on a segment of the timeline to specify a date range for a magnified window. The patient management program is further configured to display the magnified window including the blood glucose measurements of the patient from the specified date range and display a first information window including quantitative information associated with the blood glucose measurements from the specified date range. |
| US10957433B2 |
Clinical concept identification, extraction, and prediction system and related methods
A method includes the steps of determining a first concept from a text of a medical record from an electronic health record system, the first concept relating to a patient, identifying a match to the first concept in a first list of concepts, wherein the first list of concepts is not a predetermined authority, referencing the first concept with an entity in a database of related concepts, identifying a match to a second concept in a second list of concepts, the second list of concepts not directly linked to the first list of concepts except by a relationship to the entity, wherein the second list of concepts is the predetermined authority, and providing the second concept as an identifier of the patient's medical record. |
| US10957429B2 |
Healthcare analysis stream management
Apparatus, systems and methods for pre-processing, analyzing, and storing genomic data through a scalable, distributed analysis system across a network is presented. |
| US10957428B2 |
Automated clinical documentation system and method
A method, computer program product, and computing system for automating a monitoring process is executed on a computing device and includes obtaining encounter information of a patient encounter. The encounter information is processed to determine if the encounter information is indicative of a potential medical situation. An inquiry is initiated concerning the potential medical situation. |
| US10957425B1 |
Systems for creating and modifying a file for an entity, and systems for locating records in the file
Described herein are various technologies pertaining to generating and modifying a file for an entity, wherein the file includes a file record, and further wherein the file record includes binary data and a schema that is usable to hydrate a record based upon the binary data. The file is modified by appending file records to one another, where file records optionally correspond to different record creation systems. Described herein are also various technologies pertaining to locating a record in the file. |
| US10957422B2 |
Genetic and genealogical analysis for identification of birth location and surname information
A system identifies ancestral birth locations or surnames estimated to be associated with an individual's ancestors using an individual's genetic sample. The system identifies users who are genetic matches to the individual and determines whether and how often a birth location or surname appears in the pedigrees of those users. Birth locations or surnames that appear frequently throughout the pedigrees of genetically matching users may represent birth locations or surnames that are affiliated with the individual's ancestors. The system determines whether the frequency of appearance of a birth location or surname is statistically significant to eliminate biases for certain birth locations or surnames that appear more frequently than others. The birth location or surname may be provided to the individual based on an also-determined enrichment score. |
| US10957417B2 |
On-die memory power analytics and management
Systems, apparatuses, and methods for on-die memory power analytics and management are described. In some examples, the memory analytics and management may include a frequency-dependent analysis or simulation model of a memory die to determine an operating characteristic of the die. A set of ports of the memory die may be selected and one or more alternating current (AC) excitation signals may be applied to the ports to determine an impedance associated with the ports. The impedance may be used to determine one or more parameters (e.g., scattering, impedance) to analyze a die and for subsequently managing power distribution on the die. Analytics on a subset of ports on a die may be used to simulate the electrical response of the entire memory die and thus manage power delivery for the die. |
| US10957416B2 |
Methods and apparatus for maintaining characterized memory devices
Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. |
| US10957415B2 |
NAND flash memory and reading method thereof
An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command. |
| US10957410B1 |
Methods and apparatus for facilitated program and erase of two-terminal memory devices
A method for facilitating erase or program operations on two-terminal memory devices includes substantially simultaneously initiating erase cycle or program cycle for two-terminal memory devices from a first plurality of two-terminal memory devices, monitoring erase detect or program detect conditions for each of the two-terminal memory devices, and before detecting erase detect or program detect conditions for all of the two-terminal memory devices, the method includes detecting an erase detect or a program detect condition for the first two-terminal memory device from the first plurality of two-terminal memory devices, and initiating an erase cycle or a program for a second two-terminal memory device for a second plurality of two-terminal memory devices, in response to detecting the erase detect or program detect condition for the first two-terminal memory device. |
| US10957409B1 |
Method of performing programming operation and related memory device
A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string. |
| US10957406B2 |
Memory system that determines a type of stress of a memory device
According to some embodiments, a memory system includes a memory device including a plurality of memory cells capable of storing a plurality of bit data corresponding to a plurality of levels, respectively, and a controller configured to read data from the memory device, perform an error correction when there is an error in the read data, and determine a variation in a level before and after error correction of the read data. |
| US10957405B2 |
Memory system configured to update write voltage applied to memory cells based on number of write or erase operations
A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value. |
| US10957403B2 |
Semiconductor device including a voltage generation circuit configured with first and second current circuits for increasing voltages of first, second, and third output nodes
A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node. |
| US10957400B1 |
Memory system
A memory controller performs a reference read on a plurality of memory cells using reference read voltages, generates a histogram indicating the number of memory cells in different threshold voltage bins based on results of the reference read, estimates actual read voltages based on the histogram and a first estimation function, and reads data using the actual read voltages. When reading of the data with the actual read voltages estimated using the first estimation function fails, the memory controller estimates actual read voltages using a second estimation function different from the first estimation function and reads the data with the actual read voltages estimated using the second estimation function. |
| US10957396B2 |
Synapse string and synapse string array for neural networks
Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron. |
| US10957393B2 |
Apparatus and methods for performing concurrent access operations on different groupings of memory cells
Method of operating a memory, and apparatus configured to perform similar methods, including performing a first access operation having a plurality of phases on a first grouping of memory cells, receiving a command to perform a second access operation having a plurality of phases on a second grouping of memory cells while performing a particular phase of the plurality of phases of the first access operation, pausing the first access operation in response to completion of the particular phase of the plurality of phases of the first access operation, performing an initial phase of the plurality of phases of the second access operation while the first access operation is paused, and performing a next subsequent phase of the plurality of phases of the first access operation and a next subsequent phase of the plurality of phases of the second access operation concurrently. |
| US10957390B2 |
Semiconductor device
A semiconductor device 50 of the invention includes a supply voltage VCC, a plurality of registers 14, a PMOS transistor P, an AND gate 12, and a determination circuit 16. The registers 14 include a first register and a second register. The first register can keep data, and the second register can keep a check bit. The PMOS transistor P and the AND gate 12 are both connected between the supply voltage VCC and the registers 14, and both control the supply from the supply voltage VCC to the registers 14. The determination circuit 16 determines whether the check bit kept in the second register is correct or not in a DPD (deep-power-down) mode. An operating margin of the second register is worse than that of the first register. While the determination circuit 16 determines that the check bit kept in the second register is incorrect, the PMOS transistor P provides the supply voltage VCC to the registers 14. |
| US10957389B2 |
Multifunctional memory cells
The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material. |
| US10957383B2 |
Memory cell sensing based on precharging an access line using a sense amplifier
Methods, systems, and devices for operating a memory device are described. A sense amplifier may be used to precharge an access line to increase the reliability of the sensing operation. The access line may then charge share with the memory cell and a capacitor, which may be a reference capacitor, which may result in high-level states and low-level states on the access line. By precharging the access line with the sense amplifier and implementing charge sharing between the access line and a capacitor, the resulting high-level state and the low-level states on the access line may account for any offset voltage associated with the sense amplifier. |
| US10957378B1 |
Control circuit and control method thereof for pseudo static random access memory
A control circuit and a control method thereof adapted to a pseudo static random access memory are provided. The control circuit includes a write data determining circuit and a clock generating circuit. The write data determining circuit counts and compares data input times and actual data write times of the pseudo static random access memory to generate a write matching signal, and generates a write counting clock signal according to counting operation of the data input times of the pseudo static random access memory. The clock generating circuit generates a preamble signal according to the write matching signal and the write counting clock signal, and generates a column address strobe clock signal and a control signal according to the preamble signal. The clock generating circuit determines whether to dynamically delay the preamble signal to delay or omit a pulse of a column selection line signal. |
| US10957374B2 |
Memory cells and arrays of memory cells
A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells. |
| US10957372B2 |
Switching skyrmions with VCMA/electric field for memory, computing and information processing
A fixed magnetic skyrmion in a memory or Boolean logic or non-Boolean computing element is reversibly switched or switchable (1) with only an electric field and without a magnetic field or spin current; and (2) using voltage control of magnetic anisotropy (VCMA) to reduce the spin current needed to switch the skyrmion. Some embodiments switch between four states: two skyrmion states and two ferromagnetic states. Other embodiments switch between two states which are both skyrmionic, in which case the switching process may use ferromagnetic intermediate states, or both ferromagnetic, in which case the switching process may use skyrmionic intermediate states, or between a Skyrmion and ferromagnetic state. Boolean and non-Boolean logic devices are also provided which are based on these switching methods. |
| US10957370B1 |
Integration of epitaxially grown channel selector with two terminal resistive switching memory element
A magnetic memory array having an epitaxially grown vertical semiconductor selector connected with a two terminal resistive switching memory element via a bottom electrode such as TaN. An electrically conductive contact such as tungsten (W) or TaN can be included between the vertical semiconductor channel and the TaN bottom electrode. The electrically conductive contact and the TaN bottom electrode can both be formed by a damascene process wherein an opening is formed in an oxide layer and a metal is deposited into the opening. A chemical mechanical polishing process can then be performed to remove portions of the metal that extend out of the opening in the oxide layer over the oxide surface. |
| US10957366B2 |
Circuits and methods for compensating a mismatch in a sense amplifier
Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel. |