Document Document Title
US10715698B1 System and method for processing documents using mobile payment to instantly activate privilege
A system and a method for processing documents using mobile payment to instantly activate privilege are provided with a mobile device, a cloud server, a proxy server and a document-processing device connected to a network. Users can hold the mobile device to approach the document-processing device to perform corresponding operation in generation of a setting of parameters. The cloud server acquires the setting of parameters through the network and transmits the setting of parameters to the proxy server in exchange for dedicated pictogram authentication information. The document-processing device provides pictogram information according to the pictogram authentication information. The mobile device performs and completes a payment procedure according to the pictogram information. The cloud server then instantly transmits an execution command to drive the document-processing device so as to enhance operational convenience and efficiency.
US10715694B2 Image forming instruction device, image forming instruction method, and non-transitory computer readable medium for borderless and non-borderless printing
An image forming instruction device includes a selector that selects either a setting for borderless printing or a setting for non-borderless printing based on print data. In a further modification of the invention, the selector may select either the setting for borderless printing or the setting for non-borderless printing based on an image on an outer edge of the print data.
US10715692B2 Systems and methods for localizing a user interface based on an input document
The present disclosure discloses methods and systems for localizing a user interface of a device such as a multi-function device, the multi-function device presents a user interface in a pre-defined language. The method includes receiving a document, the document includes text information in a local language of a user. Then, the document is analyzed to identify the local language of the user. Upon identification, the pre-defined language of the user interface is changed to the identified local language of the user. The local language enables the user to operate the multi-function and/or perform one or more functions using the local language.
US10715683B2 Print quality diagnosis
In some examples, print quality diagnosis may include aligning corresponding characters between a scanned image of a printed physical medium aligned to a master image associated with generation of the printed physical medium to generate a common mask. Print quality diagnosis may further include determining, for each character of the scanned image, an average value associated with pixels within the common mask, and determining, for each corresponding character of the master image, the average value associated with pixels within the common mask. Further, print quality diagnosis may include determining, for each character of the common mask, a metric between the average values associated with the corresponding characters in the scanned and master images.
US10715680B2 Charging method and device involved in a protocol data unit (PDU) session
Embodiments of this application provide a charging method. The method includes that a session management function determines, a data flow within a protocol data unit, PDU, session and a charging key corresponding to the data flow within the PDU session, wherein a plurality of user plane functions are involved in the PDU session. For each of the plurality of user plane functions, the session management function sends to an online charging system, a quota request for a charging key without available quota for the UPF.
US10715677B2 Techniques to extend a doorbell chime
Methods, systems, and devices for security and/or automation systems are described. In some embodiments, the methods may include detecting an input at a doorbell, and communicating the detected input to a doorbell signal generating component associated with the doorbell based at least in part on the detecting. The methods may further include generating a first alert at the doorbell signal generating component associated with the doorbell. In some embodiments, the methods may further include communicating the detected input to one or more alert components associated with the security and/or automation system based at least in part on the detecting, and generating a second alert at the one or more alert components associated with the security and/or automation system.
US10715676B2 Distributed sensor system
A distributed sensor network that utilizes the cabling infrastructure installed for a Distributed Antenna System (“DAS”) to collect environmental data about a building. In this sensor network, an array of sensors are placed in line with the DAS communication cabling so that additional cabling is not required. The sensors use “out of band” frequencies or low level signaling so as to not interfere with the DAS signals to communicate the sensor data to the DAS head-unit.
US10715675B2 Transmission apparatus, transmission system, transmission method, and program
An apparatus which allows smooth conversation with improved sound quality to be performed independently of the magnitude of noise or the like in a vehicle. A transmission system is provided, which transmits a sound signal from a first microphone provided corresponding to a first position to a speaker provided corresponding to a second position. A transmission apparatus, a transmission method, and a program include: an evaluating unit which evaluates at least one of a level of a direct sound transmitted from the first position to the second position without intervention of the first microphone and the speaker, a noise level, and an operating state of a noise source; and a delay setting unit which sets a transmission delay from the first microphone to the speaker based on an evaluation result of the evaluating unit.
US10715669B2 Systems and methods for controlling transfer of contacts in a contact center
Managing contact transfer requests in a contact center with a processor of the contact center receiving a request to transfer a contact to a destination within the contact center. Next, the processor determines in real time, one or more first characteristics related to a source of the request and one or more second characteristics related to the destination of the request. Ultimately, based on the one or more first characteristics and the one or more second characteristics, the processor performs one of: a) transferring the contact to the destination, or b) preventing transfer of the contact to the destination.
US10715668B1 Learning based metric determination and clustering for service routing
Techniques are described for generating metric(s) that predict survey score(s) for a service session. Model(s) may be trained, through supervised or unsupervised machine learning, using training data such as communications from previous service sessions between service representative(s) and individual(s), and survey scores provided by the serviced individual to rate the session on one or more criteria (e.g., survey questions). The model(s) may be trained to output, based on an input session record, metric(s) that each correspond to a survey score that would have been provided by the individual had they completed the survey. The model may be a concatenated model that combines a language model output from a language classifier recurrent neural network, and an acoustic model output from an acoustic feature layer convolutional neural network. Individuals can be clustered according to the metric(s) and/or other factors, and the cluster(s) can be employed for routing incoming service requests.
US10715663B2 Management of agent sessions for omnichannel predictive outbound
As “call centers” continue to be replaced with omnichannel contact centers, managing a plurality of simultaneous media channels becomes more important. Contacting a customer on one channel and, at the customer or agent's request, initiating a second channel that delays the interaction will having limited acceptance and, in some jurisdictions, may be illegal. By nailing-up an agent half-communication with a number of channels, agents maintain a perpetual connection comprising an agent half-communication to a server, such as one serving as a media anchor point, share point, etc. The customer half-connection is established to a server and the agent, already connected, is joined. As a result, the customer experiences a greatly reduced delay between the time they answer and being greeted by an agent, regardless of the media type or types utilized.
US10715660B2 Caller ID verification using call identification and block lists
In an illustrative embodiment, a user device may block all the phone numbers used by an enterprise. When an enterprise wants to call the user, the enterprise may notify the user device through a separate secure channel that an enterprise phone number is in the process of making a phone call to the user device. The secure channel may include an authentication server that may request the user device to unblock the enterprise phone number. An incoming phone call from the enterprise phone number therefore can be trusted. After the phone call is terminated, the user device may again block the enterprise phone number. An attacker may not have access to the authentication server and a phone call from the attacker with a spoofed enterprise phone number (now blocked) may be dropped by the user device.
US10715658B1 Telephone call-back device
Disclosed is a telephone call-back device that can provide a means for the recipient of a robocall incoming phone call to take action. The telephone call-back device includes an activation device, a call source utility, and a call-back utility. The activation device is a button or switch that a user can activate when they receive a robocall. Once the activation device is activated, the call source utility identifies a source phone number of the robocall incoming phone call. The call-back utility initiates one or more robo call-back outgoing phone calls to be sent to the source phone number. The call-back utility can be programmed to try to send many robo call-back outgoing phone calls to the source phone number to try to swamp the phone number with robo call-back outgoing phone calls.
US10715653B2 Systems and methods for providing geolocation services
The present invention provides a system for providing geolocation services in a mobile-based crowdsourcing platform. The system includes a plurality of remote mobile devices configured to communicate and exchange data with a geolocation service based on the crowdsourcing, or polling, of users of such mobile devices to determine location and movement of the users within a specific environment. For example, in an outdoor environment such as a parking lot, the system can track the location of a user's vehicle within the lot and provide the user with an exact position of their vehicle upon the user returning to the parking lot. In the instance of an indoor environment, such as an airport, the system provides a messaging/location alert service for persons within the airport, where any given person's location within the airport can be determined and correlated with an impending departure of a flight for which they are associated.
US10715645B2 Mobile device impact protection
A mobile application communicates with an accelerometer in a mobile device to detects when a mobile device has been dropped. When the application detects that the device is dropped, it activates one or more protective features in the device. The protective features may result in physical changes in the device itself. For example, the protective feature may include activating the vibration feature of the device and increasing the voltage supplied to the vibration feature so that the device is vibrating at an increased vibration intensity when it contacts the ground. The vibrations can help to deflect, absorb, or otherwise mitigate the impact force imparted on the device from the contact surface or ground.
US10715643B2 Systems and/or methods for intelligent and resilient failover for cloud computing environments
A cloud computing system includes computing nodes that execute a shared application and/or service accessible by client computing devices over a network. A resilience multiplexer is configured to: receive signals (e.g., from a cloud controller, registry service, error handler, and/or failover service) indicative of potential problems with components of the system and/or network; identify a rule to be executed to determine how to respond to the potential problem, based on attributes of the received signal including which component generated it and what information is included in/otherwise associated with it, and other network-related data; execute the identified rule to determine whether a failover is or might be needed; if a failover is needed, selectively trigger a failover sequence; and if a failover only might be needed, initiate a resilience mode. In resilience mode, information regarding the potential problem is communicated to other components, without immediately initiating a failover sequence.
US10715642B2 Interface device and receiver including the same
An interface device disclosed herein transmits a data signal in sync with a clock signal, and includes: a reception unit performing demodulation processing and error correction processing on an input carrier wave and outputting signals resulting from these types of processing; a transport stream (TS) packet acquisition unit acquiring a TS packet included in the outputs of the reception unit; a variable-length packet acquisition unit acquiring a variable-length packet included in the outputs of the reception unit; and a first selector selecting either the TS packet or the variable-length packet and outputting the selected packet as the data signal.
US10715636B2 Loyalty switch
A loyalty switch for examining loyalty messages and routing the loyalty messages to one or more loyalty hosts and examining responses and routing the responses back to stores. Such a switch has configurable number of selector handlers pool, and the switch accepts a connection from stores and reads loyalty host information from master data to establish the connection with a loyalty host and to route messages. Each selector handler in the switch has multiple store objects that contain a routing map and connection information from companies' sites and the loyalty host.
US10715634B2 System and method for creating virtual interfaces based on network characteristics
A network-configuring system creates stable virtual interfaces for groups of neighboring network nodes. During operation, the system can obtain network-neighborhood information from one or more network neighbors. This network-neighborhood information includes duplex-neighborhood information that indicates at least a set of neighboring devices to the network neighbor, and a set of remote network nodes which are accessible via a respective neighbor. The system can use the network-neighborhood information to determine one or more groups of network neighbors with common network characteristics, such that a respective group includes one or more mutually-connected network peers. The system can then define a virtual interface for a respective group of stable network neighbors, such that the virtual interface's member nodes include the local network node and the respective group's mutually-connected network peers.
US10715632B2 Systems and methods for parallel and scalable processing of telemetry data from connected dispensing machines
The present disclosure is directed to systems and methods for parallel and scalable processing of messages containing telemetry data at an administrator system. The administrator system can receive a large number of messages containing telemetry data from many dispenser machines in a short amount of time. To receive and process those messages, the systems and methods of the present disclosure provide a message queuer to queue the messages (or at least the telemetry data in the messages) in a plurality of queues and a different thread or process for each of the plurality of queues. Each thread or process can pull messages out of its assigned queue in order and process the telemetry data of the messages. The threads or processes can run on one or more central processing unit cores at the administrator system. This setup allows for horizontal scaling in terms of message processing throughput.
US10715630B2 Common information model interoperability system
A Common Information Module (CIM) interoperability system includes a server device coupled to a network. A remote access controller in the server device is coupled to server component(s), and includes a CIM provider coupled via a CIM provider communication subsystem to a REpresentational State Transfer (REST)-CIM provider. The REST-CIM provider receives a REST request generated by a client device and redirected to the REST-CIM provider by the server device, and converts the REST request to CIM request. The REST-CIM provider then makes a call to the CIM provider that includes the CIM request and is based on a type of HTTP method request in the REST request. When the REST-CIM provider receives a CIM response from the CIM provider, it converts Common Manageability Programming Interface (CMPI) response data in that CIM response to JavaScript Object Notation (JSON) objects, and provides the JSON objects to the server device.
US10715629B2 Seamless context switch
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for switching contexts in a browser-based application. In one aspect, a system includes a browser execution module configured to receive a request to load a browser-based application with first context data, request application data and the first context data, and receive the application data and the first context data. The system includes a state machine module configured to generate a state machine to access and store context data and load the application with the first context data by storing the first context data in the state machine. The system further includes a state change module configured to intercept a request to load the application with second context data for a second application account, request the second context data, and updated the application with the second context data by storing the second context data in the state machine.
US10715628B2 Attribute operating method and device
The present document discloses an attribute operating method and device. In the above method, receiving a request message from a sending end, herein, parameter information carried in the request message includes: operating indication information, a resource address to be operated, an information type to be operated, and an information content to be operated; determining to operate on an attribute according to the operation indication information and the information type; and executing an operation corresponding to the attribute by using the resource address and the information content. On the basis of the technical solution provided by the present document, the execution of any attribute operation can be implemented without re-creating resources.
US10715626B2 Account routing to user account sets
New account routing to user account sets is described. A system creates multiple accounts profiles corresponding to multiple sets of accounts, based on multiple attributes associated with each account of the multiple sets of accounts. The system calculates multiple account scores for an account based on comparing multiple attributes associated with the account against the corresponding multiple accounts profiles, wherein the account is not in the multiple sets of accounts. The system identifies a highest account score of the multiple account scores. The system routes the account to a user associated with a set of accounts corresponding to the highest account score.
US10715624B2 Optimized N-stream sequential media playback caching method and system
A method of caching data for a set of streams serviced from a data storage device, said method including receiving requests for a set of streams, determining a number of zones in a cache based on the number of streams requested, determining a respective consumption rate for each stream, and allocating the zones in the cache with respective sizes such that the zones are scheduled to be refreshed within a same active operation period of the data storage device.
US10715618B2 Compressibility estimation for lossless data compression
A network node includes a processor programmed to parse at least a portion of an input block having a plurality of segments, determine whether at least one of the plurality of segments matches a segment stored in a history buffer, and predict a compressibility of the input block based at least in part on whether at least one of the plurality of segments matches a segment stored in the history buffer.
US10715611B2 Device context-based user interface
Device context-based user interface techniques are described. In one or more embodiments, a context is determined for a device based on a configuration of hardware associated with the device. When the configuration of hardware associated with the device changes, the context of the device may also change. Based on the determined context of the device, a user interface configuration may be selected for display. For example, when the device is connected to a mouse or a keyboard a user interface configuration may be selected that facilitates interactions performed substantially with a mouse and keyboard. However, when a mouse and keyboard are not connected to the device, but touch functionality of the device is used, a user interface configuration may be selected that facilitates interactions performed substantially using the touch functionality. A user interface for an application may be configured using the selected user interface configuration.
US10715603B2 Systems and methods for sharing application data between isolated applications executing on one or more application platforms
Systems, methods, and software are disclosed herein for facilitating dynamic sharing of application data among multiple isolated applications executing on one or more application platforms. In an implementation, a method of operating an application platform executing an application to consume application data generated by other applications executing on one or more application platforms is disclosed. The method includes receiving an instruction to invoke the application in a runtime environment. The instruction is generated by a data sharing and decision service platform based on one or more application data feeds provided by the other applications registered with the data sharing platform. The method further includes processing the instruction to automatically invoke the application in the runtime environment and, once the application is invoked, directing the party application to perform the action.
US10715599B2 Internet of things (IoT) platform and application framework
A status of an Internet of Things (IoT) device included in a local area cloud is identified. The local area cloud includes IoT devices that are connected in a wireless local area network (WLAN), and one IoT device functions as a leader of the local area cloud. A cloud server associated with the IoT device is identified and information identifying the status is forwarded to the cloud server via a wireless wide area network (WWAN). The cloud server selects an action to be performed by the IoT device and forwards data identifying the action. The leader receives and distributes information identifying the action to the IoT device via the local area cloud. The action may include actions by multiple IoT devices in the local area cloud or IoT devices included in multiple local area clouds. A user may input data to control the cloud server.
US10715597B2 Methods and systems to create a network-agnostic SDN-based cloud gateway for connectivity to multiple cloud service providers
Network-agnostic SDN-based cloud gateways are adapted for connecting a customer's SD cloud gateway to multiple cloud service providers (CSPs). A dynamic, on-demand, software defined, policy based cloud connectivity gateway is created for all kinds of networks and end points that can be used to connect to multiple CSPs at the same time from a single user interface. Network capacity on both the customer gateway and CSP connection points are adjusted through a user interface based on predefined policies such as automatic increasing of network connections based on actual cloud usage, limiting network capacity on a certain link based on time, application, and other conditions, and distributing traffic and changing the routing based on predetermined policies such as time of day, utilization, and performance.
US10715595B2 Remotes metadata extraction and transcoding of files to be stored on a network attached storage (NAS)
A method may comprise monitoring files (files, folders, documents of any type) to be sent to a remote storage to identify those that belong to selected file types and extracting metadata from those that belong to the selected file type(s), which may then be transcoded. Identifiers of the transcoded files and corresponding extracted metadata may be sent to a storage database. The transcoded files may be sent to be stored in the remote storage such that, upon receiving a file request and at least one criterion, the remote storage searches the database to find identifier(s) of the transcoded file(s) whose extracted metadata satisfies the criterion. Responsive to the received file request, one or more transcoded files may be made available whose identifier(s) were found during the search of the database. Alternatively or in addition, links to the transcoded files that correspond to found identifier(s) may be made available.
US10715589B2 Data stream distribution method and apparatus
The present invention discloses a data stream distribution method and apparatus. In the method, a load balancer may access data in a data stream according to an instruction in a distribution rule that is sent by an application server according to an interface protocol or configured on the load balancer according to an interface protocol; determine, according to a keyword generated according to the accessed data, an application server that processes the data stream; and send the data stream to the determined application server. Therefore, the load balancer may access the data in the data stream according to an instruction in a common distribution rule, to distribute the data stream, thereby reducing complexity of data stream distribution performed by the load balancer.
US10715587B2 System and method for load balancing computer resources
A networked computational architecture for provisioning of virtualized computational resources. The architecture is accessible by a client application run on a client device. The architecture includes a hardware layer having a plurality of server devices, each server device having at least one physical processor having a local memory. A resource controller is provided and operable to allocate a plurality of server devices to a client application for data processing and to assign control information to the client application. The control information specifies the required allocation of a data processing workload to each server device allocated to the client application. The architecture is configured such that client applications send the data processing workload directly to each server in accordance with the control information. Thus, a networked architecture is load balanced indirectly without requiring a load balancer to be located in the data path between the client and the server.
US10715580B2 Grouping content based on geographic data
A method includes detecting content items stored locally on a client device, each content item including a time stamp and geospatial metadata; identifying one or more sets of content items based on their time stamps being within a first predetermined time range; determining, for each set of content items, a geographic location associated with the content items of the set based on the geospatial metadata of each content item; generating a list of all geographic locations associated with the sets of content items; selecting subsets of content items based on determining that the time stamps associated with each content item of the subset are within a second predetermined time range; determining, from the selected subsets of content items, non-overlapping subsets of content items based on a parent geographic location associated with the selected subset; and sending instructions to categorize content items into the non-overlapping subsets of content items.
US10715578B2 Projector system and projector setting method
The disclosure proposes a projector system and a projector setting method. The projector system includes: a plurality of projectors including a first projector and at least one second projector, wherein the first projector is connected to the at least one second projector via a network. The first projector receives a plurality of set values and stores the set values as a configuration. The first projector acquires an Internet Protocol address corresponding to the at least one second projector. The first projector receives a copy command, and transmits the configuration to the at least one second projector according to the Internet Protocol address of the at least one second projector. The at least one second projector performs a setting operation according to the configuration. The projector setting method suitable for the projector system. In the disclosure, the configuration can be copied between a plurality of projectors faster and more conveniently.
US10715574B2 Systems and methods for frame duplication and frame extension in live video encoding and streaming
Embodiments of the invention provide for live encoding systems that can replicate a current encoded frame instead of re-encoding said current frame, and then adjust the replicated frame to different bitrates, resolutions, and/or contexts as necessary for the several different adaptive bitrate streams. In addition, various embodiments of the invention can extend a duration of a current frame being repackaged and/or re-encoded. Utilizing these and other techniques, live encoding systems in accordance with embodiments of the invention can more efficiently handle gaps in received data, slower feeding of data, and/or heavy loads on server hardware.
US10715573B2 Media playing method, terminal device, and computer storage medium based on two players
The present disclosure discloses a media playing method, a terminal device, and a computer storage medium. The method includes dividing content of a target file in a time dimension to obtain N number of target sub-files, where N is an integer greater than or equal to 2; obtaining a first time point, and determining an nth target sub-file in the N number of target sub-files based on the first time point, where n being an integer greater than or equal to 1 and less than or equal to N. The method also includes setting a first player and a second player, and controlling the first player and the second player to alternatingly obtain and output the nth target sub-file and at least one target sub-file that is after the nth target sub-file.
US10715567B2 Method and apparatus for providing state information
Methods and apparatus are provided for providing state information of a digital apparatus. State information for a user of the digital apparatus is determined based on the user's intention to perform communication. The state information is transmitted to a server. A display request for a contact list is received. A screen having a plurality of user items is displayed. Each of the plurality of user items corresponds to a respective one of a plurality of users in the contact list. At least one of the plurality of user items includes identification information of a user corresponding to the at least one of the plurality of user items, state information of the corresponding user that is received from the server, and at least one category indicator representing at least one recommended communication service category determined based on the state information of the corresponding user.
US10715562B2 Synchronization based on device presence
An architecture that can facilitate initiation of an automatic synchronization operation based upon presence information in connection with a wireless communications network is provided. For example, when certain mobile devices register with a particular network entity (e.g., a femtocell) that services a particular target location (e.g., place of residence), then such registration can be leveraged to indicate presence at the target location. Accordingly, synchronization between the mobile device and other devices can be automatically initiated, without requiring input or effort by a user, or even that the user remembers to perform the synchronization operation. Moreover, the synchronization operation can be wireless, so connection cables need not be maintained or employed.
US10715560B1 Custom traffic tagging on the control plane backend
Custom traffic tagging on a control plane backend is disclosed. Information associated with a video session is obtained. Based at least in part on at least some of the obtained information associated with the video session, additional metadata to associate with the video session is determined. The additional metadata is determined from metadata obtained from one or more disparate sources. The video session is associated with the determined additional metadata.
US10715556B2 Real-time policy distribution
In one example, there is disclosed a domain master for a data exchange layer (DXL), including: a hardware platform configured to execute instructions; and one or more memories having stored thereon instructions to instruct the hardware platform to: communicatively couple to the DXL; provide a DXL messaging service including native support for request-response (1:1) transactions via a publish-subscribe (1:N, N>1) fabric; provide DXL domain master services for a DXL domain; and provide DXL-based real-time policy and task distribution for DXL endpoints of the DXL domain.
US10715555B1 Hierarchical multi-transaction policy orchestrated authentication and authorization
A system and method for authentication policy orchestration may include a user device, a client device, and a server. The server may include a network interface configured to be communicatively coupled to a network. The server may further include a processor configured to obtain, from a client device via the network, a transaction request for a transaction, determine an authorization requirement for the transaction request based, at least in part, on a plurality of authorization policies, individual ones of the plurality of authorization policies being separately configurable by at least one of a relying party and an authorizing party, and complete the transaction based on the authorization requirement having been met.
US10715550B2 Method and device for application information risk management
Target application information for validation is received at a network device from user equipment. The received target application information is validated. Risk information associated with the validated target application information is determined. Based on the determined risk information, prompt information is returned to the user equipment.
US10715549B2 Systems and methods for AIDA based role models
The present disclosure describes systems and methods for using a model for a predetermined role for simulated phishing campaigns. A campaign controller communicates simulated phishing communications to one or more devices of a user using a model that the campaign controller selects from a plurality of models in a database that have been established for predetermined roles of a company. The model is selected based on one or more attributes of the user that are identified by the campaign controller. The campaign controller identifies one or more attributes of each user of a plurality of users for the simulated phishing campaign, and the campaign controller selects a respective model for each user based on the attributes of each user, wherein the models are not all the same for all of the users.
US10715545B2 Detection and identification of targeted attacks on a computing system
Malicious activity data is obtained, that is indicative of attempted attacks on a computing system. Clusters of targets are identified and it is determined whether the malicious activity preferentially targets one cluster of targets over other. Also, low prevalence attacks are identified and it is determined whether a low prevalence attack has a high concentration in one or more of the target clusters. If the malicious activity either preferentially targets a cluster, or a low prevalence attack has a high concentration in a cluster, then the attack is identified as a targeted attack, so that remediation steps can be taken.
US10715544B2 Method, apparatus and system for calculating a risk score of a user request by a user on a web application
A method comprising partitioning a space of user requests into subsets, and determining a risk score for a user request based on the evolution of the number of user requests in the subset of user requests to which this user request belongs.
US10715542B1 Mobile application risk analysis
An electronic device comprising one or more processors; a storage medium communicatively coupled to the one or more processors, the storage medium having stored thereon logic that, upon execution by the one or more processors, performs operations comprising: (1) receiving, via a first electrical signal, application data from a mobile agent installed on a mobile device, (2) querying, via a second electrical signal, a database for a risk level of each of one or more applications of the mobile device listed in the application data, and (3) determining a threat level for the mobile device based on one or more of: (i) the risk level of at least one of the one or more applications, (ii) usage information of the at least one of the one or more applications, or (iii) configuration information of the mobile device is shown.
US10715539B1 Request header anomaly detection
A system and a method are disclosed for detecting an unacceptable HTTP requests by scanning the headers of the HTTP requests.
US10715538B2 Transient transaction server
A networked computer system enables one or more transactions to be executed securely. An initiator sends a service request to a control server. The control server creates or selects an existing transaction server for the sole purpose of executing the transaction requested by the service request. If the transaction server is pre-existing, it may be in an inaccessible state and then be made accessible in response to receiving the service request. The control server informs the initiator of the created transaction server. The initiator (and possibly one or more other authorized participants) engages in the transaction with the transaction server, independently of the control server. The transaction server terminates, such as upon completion of the transaction, the expiration of a timeout period, or satisfaction of another server termination criterion. The use of such a one-time transaction server increases security, privacy, and anonymity.
US10715535B1 Distributed denial of service attack mitigation
Provided herein are identification of a distributed denial of service attack and automatic implementation of preventive measures to halt the distributed denial of service attack. At substantially the same time as the attack, valid users/customers (e.g., devices) are provided quality of service and continued access to a website experiencing the distributed denial of service attack. Further, service to temporary or unknown users (e.g., devices) with public access to the website is suspended during the duration of the distributed denial of service attack.
US10715530B2 Security and permission architecture
When a user inputs an action request, such as a requested command, to be performed on a target machine, a management system receives the request and verifies it with a separate authentication and permission system. The verified command request is sent to the target machine. An authentication worker on the target machine accesses a set of policies, local to the target machine, to identify a least privileged execution environment in which the requested command can be performed. The authentication worker on the target machine launches the requested command within the identified least privileged execution environment on the target machine.
US10715529B2 Method, apparatus, and computer program product for privacy management
An apparatus for privacy management may include a processor. The processor may be configured to access one or more privacy options. In this regard, each privacy option may be configured to provide members of one or more groups access to content. The processor may also be configured to provide for selection of a privacy option in association with the content. Associated methods and computer program products may also be provided.
US10715528B1 Multi-factor location-based and voice-based user location authentication
A system is provided that determines a location of a user based on various criteria. The system may detect the location of a user based on the location of the user's voice and the location of the user's device, as determined using a beacon signal. The system may process data representing the user's voice and device locations using a model to determine a confidence that a user is at a particular location. Based on the determined location, the system may perform various actions.
US10715525B2 Computer implemented methods and apparatus for providing access to an online social network
Disclosed are systems, apparatus, methods, and computer-readable storage media for providing access to an online social network. The online social network can be specific to an organization having one or more internal users. In some implementations, a request message is received from a requesting user to access social network data of the online social network. The requesting user is identified as an external user of the organization, and it is determined that the requesting user has an authorized status. Access to only a portion of the social network data is provided to the authorized requesting user.
US10715521B2 Biometric face recognition based continuous authentication and authorization system
A method and system for continuously authenticating a user working from a remote location is provided. The method includes providing user an interface to login through his login credentials to company domain. The login credentials are authenticated by a company's remote server. Once the user is authenticated the server pushes user's secondary authentication details to user's device and invokes a secondary authentication system. The secondary authentication system may include a webcam that initiates once user is logged in and continuously monitors biometric parameters for continued authentication of the user.
US10715519B1 Adaptive method for biometrically certified communication
A communication device and method for authentication of a message being transmitted from the communication device. The method includes receiving, by a messaging utility, content of a message provided for transmission from the communication device. Based on a determination that the message requires user authentication before the message is transmitted to a recipient, the method further includes selecting, based on contextual data, one or more biometric capturing components of the communication device; triggering at least one selected biometric capturing component to capture a corresponding biometric input from a user of the communication device; and transmitting the message when the biometric input as belonging to an authorized user of the communication device. In one embodiment, a clearinghouse service authenticates a biometric input from a user of the communication device in order to certify the user and/or the message.
US10715516B1 Time-series database user authentication and access control
Methods and apparatuses are described for time-series database user authentication and access control. A server computing device receives a request from a remote computing device to access a time-series database coupled to the server computing device, wherein the request includes one or more authentication credentials associated with the remote computing device. The server computing device validates the one or more authentication credentials associated with the remote computing device. The server computing device connects to an access control layer associated with the time-series database. The access control layer authorizes the remote computing device to access data in the time-series database based upon an access profile associated with the validated authentication credentials. The server computing device retrieves data from the time-series database in response to the request.
US10715511B2 Systems and methods for a secure subscription based vehicle data service
Secure subscription based vehicle data services are provided. In one embodiment, a device comprises: a non-volatile memory comprising an embedded public key (EPK) that comprises a public key of a public-private key pair associated with a data service system not onboard the vehicle; a protocol that initiates a communication session that includes a session validation sequence that causes a processor to transmit a session request message and validate an authenticity of a session reply request using the EPK; the protocol includes a session initiation sequence that causes the processor to: transmit an initiation request message to the data service system that includes a key derivation key, and apply the key derivation key to a key derivation function to generate a message authentication key. The processor authenticates uplink messages exchanged with a host data service using the message authentication key.
US10715510B2 Secure device notifications from remote applications
Methods and systems for securely delivering notifications from remote applications to client devices are described herein. A computing device may listen for notifications from a remote application and receive notification data from the remote application. The computing device may select a notification service for delivery of the notification data to the client device. The computing device may send, to the selected notification service, at least a portion of the notification data for delivery to the client device. At least a portion of the notification data may be encrypted prior to sending to the selected notification service.
US10715506B2 Method and system for master password recovery in a credential vault
A method at a computing device for enabling access to a credential vault if a master password for the credential vault is lost, the method including selecting at least one credential from within the credential vault; encrypting one of the master password or a vault key for the credential vault with the selected at least one credential, thereby creating a recovery file; and storing the recovery file, wherein the selected at least one credential can be used to decrypt the recovery file to enable access to the credential vault.
US10715505B2 End-to-end encryption in a software defined network
A first information comprising an identification of an encryption algorithm supported by a first component from the first component of a software defined network (SDN) is received at a controller of the SDN. A set of policies and a set of encryption algorithms are sent to the first component. A policy determines a cryptographic operation applicable to a path in the SDN between the first component and a second component of the SDN. The first component comprises an originating point of the path and the second component comprises a destination point of the path.
US10715502B2 Systems and methods for automating client-side synchronization of public keys of external contacts
Systems and methods for automating client-side synchronization and discovery of public keys and certificates of external contacts include a key synchronizer at a client device. The key synchronizer obtains, from the client device, an external contact associated with an external domain outside of a local domain of the client device and then identifies, based on the external domain, a public key registry outside of the local domain. The key synchronizer obtains, from the public key registry, a registry-supplied public key or digital certificate for the external contact and then stores the registry-supplied key as a locally-stored key in the local key store such that the client device can obtain and apply the locally-stored key to secure an email targeting the external contact as a recipient of the email.
US10715501B2 Providing secure data transmission over a universal serial bus (USB) interface
An example includes a computing device including a controller configured to communicably couple the computing device to a peripheral computing device. The controller includes an encryption unit configured to encrypt input data received from the peripheral computing device before sending the input data to an application running on the computing device, and a decryption unit configured to decrypt output data received from the application before sending the output data to the peripheral computing device. The computing device also includes a memory device including a data structure that directs the flow of the data between the peripheral computing device and the application. The data structure includes an encryption enable field and an encryption key field for controlling the encryption and decryption units of the controller.
US10715499B2 System and method for accessing and managing key-value data over networks
A device for storing key-value (KV) data includes non-volatile memory and a controller. The controller includes a decapsulator and a KV mapper to receive network data communicated over a network, for example using a layer 2 protocol. The decapsulator is configured to decapsulate a payload from the network data, the payload including a key-value pair and first information. The KV mapper is configured to receive the key-value pair and the first information decapsulated from the network data, and determine, based on the received key-value pair and first information, a first location of the non-volatile memory. The controller is further configured to store KV data corresponding to the key-value pair at the first location of the non-volatile memory based on the first information.
US10715497B1 Digital safety box for secure communication between computing devices
Techniques are described for generating and executing a digital safety box to provide secure communication between two computing devices. The digital safety box comprises an encryption key, and an executable code that defines a content holder and performs encryption of content stored in the content holder with the encryption key for secure communication. A receiver computing device generates the digital safety box including the executable code and the encryption key for a requesting sender computing device. The digital safety box may be one-time use and include a unique encryption key and a unique executable code. Upon receiving the digital safety box, the sender computing device executes the executable code of the digital safety box as an application that enables the sender computing device to store content in the defined content holder, encrypt the data with the encryption key, and generate a sealed digital safety box including the encrypted content.
US10715496B2 Client network access provision by a network traffic manager
In one embodiment, a computer implemented method provides a client computing device network access to a private network by a network traffic manager, and the method includes: obtaining context parameters related to a context of the client computing device; selecting as a function of the context parameters one or more policies as selected policies, wherein each policy is associated with one or more network entitlement rules defining network access rules to a networking device or an application in the private network according to the policy; retrieving the one or more network entitlement rules associated with the selected policies; and providing the network traffic manager with the one or more network entitlement rules, thereby providing the client computing device the network access.
US10715495B2 Congestion control during communication with a private network
Example methods are provided for a first endpoint to perform congestion control during communication with a second endpoint over a public network, the second endpoint being in a private network. The method may comprise generating a plurality of tunnel segments containing unreliable transport protocol data destined for the second endpoint; and determining whether congestion control is required based on a data amount of the plurality of tunnel segments and a congestion window associated with a tunnel connecting the first endpoint with the private network. The method may further comprise, in response to determination that congestion control is required, performing congestion control by dropping at least some of the plurality of tunnel segments; otherwise, sending the plurality of tunnel segments through the tunnel supported by the reliable transport protocol connection.
US10715492B2 Flow table processing method and apparatus
This application discloses a flow table processing method and the method is applicable to a software-defined networking SDN. After determining that M virtual machine ports are added to a security group, an SDN controller generates a first matching flow table set, a second matching flow table set, and an action flow table of the security group. The first matching flow table set and the second matching flow table set together implement matching of the security group. The action flow table of the security group includes a packet action for a packet that successfully matches the security group. The method provided in this application lowers complexity of a flow table used to implement security group matching, and improves security group matching efficiency.
US10715489B2 Management server, connection support method, and non-transitory computer-readable recording medium encoded with connection support program
A management server disposed outside a firewall and supporting connection of communications between a control target device disposed inside the firewall and a cloud server disposed outside the firewall, includes a server-side session establishing portion to, based on a request from a relay device disposed inside the firewall, establish a session with the relay device, a device information acquiring portion to acquire device information about the control target device from the relay device via the established session, and an update determining portion to, in response to reception of a request of connecting to the control target device from the cloud server, determine whether to update the device information. The device information acquiring portion includes an upon-session-establishment acquiring portion to acquire the device information when a session with the relay device is established, and an upon-session-request acquiring portion to acquire the device information after updating the device information is determined.
US10715488B2 Automated website generation via integrated domain registration, hosting provisioning, and website building
Methods of the present inventions allow for generating and providing an enhanced domain name. An exemplary method may comprise providing an enhanced domain to a second party. The enhanced domain may comprise a domain name, a web space automatically enabled and associated with the domain name, and at least one application automatically enabled and associated with the domain name.
US10715487B2 Methods and systems for creating new domains
Systems and methods for creating a new domain, such as a top-level domain or a second-level domain, make use of a Domain Manager that enables a user to enter data that is necessary or optional to implement the creation of a new domain. Systems such as, for example, a Registry and one or more Registrars, may use the data defined by the Domain Manager to create a new domain.
US10715485B2 Managing dynamic IP address assignments
Various systems and processes may be used to manage Internet Protocol (IP) addresses that are dynamically assigned. In particular implementations, systems and processes for managing IP addresses that are dynamically assigned may include the ability to determine whether an identifier for a web service has been received from a customer having one or more virtual machines in a service provider network, the web service being accessible by the customer's virtual machines over an external communication network. The systems and processes may also include the ability to determine a number of IP addresses for the web service, identify virtual machines of the customer that are allowed to communicate with the web service, generate one or more IP address lists for the identified virtual machines, and update security tables for the identified virtual machines with the IP address lists at server computers hosting the identified virtual machines.
US10715484B1 Domain management and synchronization system
A domain management system that manages domain names, network addresses, and other aspects of a computing network domain is provided. The domain management system obtains domain data, such as domain name system (“DNS”) records, from any number of network-accessible providers of the domain data, such as DNS servers. The domain management system can store, transform, and synchronize the domain data among the network-accessible providers, even if the network-accessible providers do not all use or recognize the same format and/or content of domain data.
US10715482B2 Wide area service discovery for internet of things
A cloud-based DNS-SD architecture may link together separate LANs to form a virtual discovery zone from a service discovery perspective that includes a cloud based DNS-SD server separate from regular Internet DNS, and asleep node handling, among other things. In an example, a cloud based DNS-SD server is separate from the regular Internet DNS servers. This cloud DNS-SD server may run as a private Infrastructure as a Service (IaaS) specifically for service discovery in the virtual discovery zone.
US10715478B2 Event-based comment grouping for content items
A method for event-based comment grouping for content items is disclosed. The method includes identifying, by a processing device, user comments corresponding to a content item, the user comments comprising playback timestamps having selectable links to access a portion of the content item that is associated with a respective time interval, dividing the content item into a plurality of content item segments that are associated with respective time intervals, grouping the user comments to associate with respective content item segments based on the playback timestamps of the user comments, selecting a content item segment of the content item segments based on interactions with the user comments, and providing a subset of the grouped user comments associated with the selected content item segment for display during playback of the content item.
US10715472B2 System and method for unit-of-order routing
In accordance with an embodiment, a system and method provides a messaging service implementing a unit-of-order guarantee in a multitenant application server environment. The system and method of implementing unit-of-order utilizes an improved path service for routing all messages having a particular unit-of-order to the same member of the cluster. The improved path service allows for scalability of the cluster and reduced resource utilization, thereby improving the performance of a clustered computing system providing the messaging service.
US10715466B2 Systems and methods for locating application-specific data on a remote endpoint computer
According to one aspect, a system for locating application-specific data that includes a server, a broker, and an agent. An operator may define a command using the server, and this command may be sent to the broker. The broker may then send the command to the agent operating on an end-point system. The agent may then conduct an application-specific data search on the end-point system in respect of the user command. Search results may then be sent to the broker. The broker may then sent the search results to the server.
US10715465B1 Asset tracking systems and methods
An asset tracking system has a plurality of anchors. A tag communicates with the anchors as it is moved by a user being tracked by the system, and data based on communication between the tag and at least one of the anchors is transmitted to a server. The server determines a location of the tag based on the data and detects an occurrence of an event based on the location. The server also transmits to each of the anchors a tag alert message having a tag identifier identifying the tag and an event indicator associated with the occurrence of the event. At least one of the anchors transmits the tag identifier and the event indicator to the tag, which issues a warning to the user in response to tag alert message.
US10715464B2 System and method for monitoring tooling activities
An apparatus or system and method or process for displaying tool or die data or other tool or processing information on a display window of a webpage. A method for displaying tool data from a reciprocating tool includes positioning a monitor with respect to the reciprocating tool and the monitor recording data from the reciprocating tool. The data is communicated and then stored in a remote data storage location as stored tool data. The stored tool data is processed and then displayed, for example in the window of the webpage.
US10715462B2 First and second ICN network nodes and method therein for generating data content
A method performed by a first Information Centric Networking (ICN) network node for generating a number of data contents to a number of respective communication devices is provided. The first ICN network node operates in an ICN network 100. The first ICN network node aggregates (501) a number of requests received from a second ICN network node, based on that each request according to a common part of the request is associated with the same theme of the data content being requested by each of the respective communication device. Each aggregated request further comprises a respective customized part associated with the data content. The customized part is requesting the data content to be customized for being consumed in the respective communication device. The first ICN network node locates (502) a set of components corresponding to the requested data content according to the common part, and then generates (503) a number of transformed data contents based on the aggregated requests and the located set of components. Each respective transformed data content fulfils the requested common part and the requested customized part of each respective request and is customized for being consumed in the respective communication device.
US10715461B2 Network control to improve bandwidth utilization and parameterized quality of service
Systems and methods for scheduling network communications in a managed network can include a Network Controller discovering a plurality of network nodes; the Network Controller classifying the discovered network nodes into two or more classifications of node for node-level prioritization of network communications; the Network Controller receiving reservation requests from at least some of the plurality of network nodes, wherein the reservation requests request one or more time slots for their respective network nodes in an upcoming communication window; and the Network Controller assigning time slots in the upcoming communication window to one or more network nodes in response to reservation requests, wherein the assignment is based on a priority of the network nodes and wherein the priority is assigned to the nodes according to their classification.
US10715458B1 Organization level identity management
User identities can managed at an organization level, instead of across multiple individual resource accounts. In a resource provider environment, access to various resources and services may require users to have identities with specific resource accounts. Users can instead be associated with organization accounts, or virtual accounts that are not associated with specific resources or services. The organization accounts are attached at the appropriate location(s) in an organizational hierarchy. A user having an organization account can project the identity in any sub-account in the organization hierarchy. This can include any lower-level resource account, or can child accounts under a relevant branch of the hierarchy. A user can validate against the organization account, and receive access to the relevant service or resources using the identity projected in the corresponding resource account.
US10715453B2 Method and network node for congestion management in a wireless communications network
Method in and a network node (160; 110; 401a, 600) for congestion management of a transport network (130) comprised in a wireless communications network (100). The wireless communications network (100) further comprises a base station (110; 401a) configured to receive data being transported via a data transport path (132; 404a,d) of the transport network (130) and to transmit the received data to one or more wireless devices (120) served by the base station (110; 401a). The network node obtains (302; 409; 501) an indicator indicating at least a risk for occurrence of downlink data congestion in the data transport path (132; 404a,d). To reduce said at least risk, the network node then controls (304; 411; 502) the base station (110; 401a) to reduce and/or limit a throughput rate of data being transmitted to the one or more wireless devices (120). The data is received by the base station (110; 401a) via the data transport path (132, 404a,d).
US10715446B2 Methods and systems for data center load balancing
Methods and systems for collecting congestion information at a switch of a leaf-spine network. The switch processes a path finding packet. Congestion information is obtained relating to congestion between ports of the switch. The congestion information is inserted into the payload of the path finding packet. The switch multicasts the path finding packet.
US10715438B2 Dynamic access-point link aggregation
An access point that provides link aggregation is described. During operation, this access point receives a message that may include a Dynamic Host Configuration Protocol (DHCP) response with an Internet protocol (IP) address of a gateway for an electronic device to access a network and a media access control (MAC) address of the electronic device. Based on the MAC address and/or at least a characteristic of the electronic device (such as a configuration, a capability and/or an operating system of the electronic device), the access point may determine a different IP address of another gateway for the electronic device to access the network. Moreover, the access point may modify the DHCP response by substituting the IP address of the other gateway for the IP address of gateway in a modified DHCP response. Next, the access point provides the modified DHCP response to the electronic device.
US10715434B2 Apparatus and method for transmitting and receiving signal in multimedia system
A method of operating a transmitting apparatus in a multimedia system is provided. The method includes inputting at least one network layer packet, generating a link layer packet based on the at least one network layer packet, and transmitting the link layer packet, wherein the link layer packet includes a header including information indicating whether the link layer packet includes a single network layer packet and information indicating an identifier related to the at least one network layer packet.
US10715433B2 Information processing apparatus and information processing method
An information processing apparatus includes a plurality of virtual machines each having a function of sending an address request for communication data to an outside, and sending communication data to a destination address received as a response to the address request. The apparatus further includes a communication debugger that logs first communication data between the virtual machine and another virtual machine. Upon receiving an address request from the virtual machine, the communication debugger sends an address of the communication debugger as the destination address, to the virtual machine, and logs the communication data sent from the virtual machine.
US10715431B2 Methods and apparatuses for routing data packets in a network topology
The embodiments herein relate to methods and routers. One method includes: receiving a data packet from a source host router connected to a source host, said packet comprising a source IP address of the source host and a destination IP address of a destination host, the data packet being received on an interface of the source edge router identified by a virtual private network identity, VRF-ID; extracting, from a configuration information on said interface, of the source edge router, a zone-identity, zone-ID, of a destination edge router to which a destination host router is associated, wherein the destination host router is connected to the destination host, adding the zone-ID and the VRF-ID at Layer 2.5 of the data packet; and sending the data packet towards the destination edge router having the assigned zone-ID.
US10715429B2 Apparatus, system, and method for packet switching
An apparatus is provided for control of a plurality of forwarding switches using a network controller. The network controller executes a routing configuration application that analyzes interconnections between the forwarding switches to identify a topology of the network, determine label switched paths (LSPs) between the forwarding switches, and transmits the next hop routes to the forwarding switches. The forwarding switches use the next hop routes to route packets through the network according to a multiprotocol label switching (MPLS) protocol. Each LSP includes one or more next hop routes defining a forwarding address associated with one forwarding switch to an adjacent forwarding switch.
US10715428B2 Resource reservation techniques for point-to-multipoint tunnels on a ring network
Techniques are described for signaling a resource reservation point-to-multipoint (P2MP) label switched path (LSP) in a ring network. For example, the techniques include sending a single resource reservation request message without the ingress needing to send multiple resource reservation request messages, one for each leaf network device of the P2MP ring LSP. The resource reservation request message includes a leaf identification object from which network devices of a P2MP ring LSP may explicitly or implicitly identify themselves as prospective leaf network devices of the P2MP ring LSP. A network device determined to be a leaf network device may send a resource reservation response message back to the ingress network device of the P2MP ring LSP and send a modified resource reservation request message (if explicit) and/or the same resource reservation request message (if implicit) to a next hop network device along the P2MP ring LSP.
US10715424B2 Network traffic management with queues affinitized to one or more cores
Techniques of network traffic management in a computing device are disclosed. One example method includes receiving, at a main processor, a request from a network interface controller to perform network processing operations for packets assigned by the network interface controller to a queue of a virtual port of the network interface controller. The method also includes, in response to receiving the request, causing one of multiple cores of the main processor with which the queue of the virtual port is affinitized to perform the network processing operations to effect processing and transmission of the packets to an application executing in a virtual machine hosted on the computing device.
US10715412B1 Systems and methods for monitoring of overall latency
There is provided, a computer-implemented method of monitoring overall latency, comprising: monitoring a sequence of images of an actuator controlled by a user interface presented on a display of a client terminal, detecting, in a first image of the sequence of images, a first visual indication denoting termination of a user triggered activation of movement of the actuator via the user interface, detecting, in a second image of the sequence of images, a second visual indication denoting termination of the movement of the actuator in response to the termination of the user triggered activation, computing an overall latency from a timestamp associated with the second image and a timestamp associated with the first image, and when the overall latency is above a threshold, adjusting at least one system parameter of a system connecting the client terminal with the actuator and with a camera that captures the sequence of images.
US10715411B1 Altering networking switch priority responsive to compute node fitness
An apparatus includes a local compute node connected to a first networking switch by a direct local link. The first switch reduces its priority in response to determining that that the first networking switch is currently unable to establish the bi-directional communication with the local compute node through the direct local link. If the reduced priority of the first networking switch is greater than a priority of each of at least one additional networking switch in a cluster, then the first networking switch operates as a master networking switch for the cluster. If the reduced priority of the first networking switch is less than the priority of any of the at least one networking switch, then the first networking switch operates as a standby networking switch and one of the atleast one additional networking switch having the highest priority is operated as the master networking switch for the cluster.
US10715406B2 Flow sample
A network anomaly may be detected by comparing the network behavior of a packet to an expected network behavior. The network behavior may be determined using a packet sample of a packet matching a flow rule that includes a sampling rule.
US10715401B2 User interface for viewing items in a synchronization system
In a synchronization system, the present invention provides an improved user interface through which a user can view and manage settings associated with the user's account in the synchronization system. In the preferred embodiment, a column is displayed for each electronic device associated with the user's account in the synchronization system. In each column is a visual representation of items (e.g., folders) that are (1) backed up, remotely accessible and/or synchronized in the synchronization system and (2) located on the electronic device associated with such column. For each item that is synchronized across multiple devices, all the visual representations of such item in the columns are aligned across a single row in the interface. In the preferred embodiment, there is an arrow, or other visual indicator, between the visual representations of such items to indicate that the items are synchronized.
US10715394B2 Data aggregation based on a heirarchical tree
At each delegate device and each non-delegate device of a logical device hierarchy, a data cube is generated. The logical device hierarchy includes more than one level, and each level includes one or more groups, and each group includes one delegate device and one or more non-delegate devices. At each delegate device, data cubes are received from the one or more non-delegate devices associated with the same group. At each delegate device, data cubes are received from delegate devices of a different group, and that delegate device is the parent of the delegate devices associated with a different group. At each delegate device, the received data cubes are aggregated into a weighted data cube. From each delegate device, the weighted data cube are outputted to the parent of the delegate device.
US10715388B2 Using a container orchestration service for dynamic routing
The disclosure generally describes methods, software, and systems for using resources in the cloud. An integration flow (iFlow) is deployed as a resource by a cloud integration system. The resource is assigned by a container orchestration service to one or more pods. An iFlow definition that is mapped to the resource is copied into a corresponding pod by a pod sync agent. A unique label is assigned by the pod sync agent to each resource based on iFlows deployed into the pod. A service is created as an endpoint to the resource by the cloud integration system with a rule redirecting calls to the one or more pods containing the resource.
US10715386B2 Method and apparatus for regulating communication parameters
A method and equipment for regulating communication parameters are provided. The method includes that: a first equipment establishes a communication with a second equipment according to preset configurations of communication parameters; the first equipment regulates the configurations of one or more of the communication parameters according to a network state and/or service state in a communication process; and the first equipment sends communication parameter regulation indication information to the second equipment, the communication parameter regulation indication information indicating a result of regulation performed by the first equipment on the configurations of the one or more of the communication parameters. Therefore, performance and applicability of a wireless communication system may be improved.
US10715380B2 Setting a reminder that is triggered by a target user device
Disclosed are systems, methods, and non-transitory computer-readable storage media for setting a reminder triggered by a target device. A requesting device sends a request to a server to set a reminder triggered by a target device. The request includes parameters, such as a location and a condition that define when the reminder is triggered. The server sends instruction to the target device to set the reminder based on the parameters. When the condition such as arrival is met by the target device in relation to the location the target device sends a message to the server that the reminder has been triggered. The target device can set a geo-fence to determine the position of the target device in relation to the location, and the requesting user can dictate the size of the geo-fence. The server sends a notification to the requesting device that the reminder has been triggered.
US10715379B2 System for decomposing events from managed infrastructures with bitwise operation
A system is provided for decomposing events from managed infrastructures. A first engine is configured to receive message data from a managed infrastructure that includes managed infrastructure physical hardware that supports the flow and processing of information, the at least one engine is configured to determine common characteristics of events and produce clusters of events relating to the failure of errors in the managed infrastructure. Membership in a cluster indicates a common factor of the events that is a failure or an actionable problem in a physical hardware of the managed infrastructure directed to supporting the flow and processing of information. The first engine is configured to create one or more situations that is a collection of one or more events or alerts representative of the actionable problem in the managed infrastructure. A second engine is configured to determine one or more common steps from events and produces clusters relating to events. The second engine determines one or more common characteristics of events and produces clusters of events relating to the failure or errors in the managed infrastructure. An anomaly engine is configured to perform bitwise operations.
US10715377B2 Domain name services servers management to share data efficiently
A method and system for implementing domain name services (DNS) is described. In one aspect a query from a user device for access to a particular resource record may be received and forwarded to an authoritative DNS device. A reply to the query may be received from the authoritative DNS device. Information of the reply also may be distributed to other DNS devices.
US10715376B2 Enhanced IQ mismatch correction function generator
An IQ mismatch correction function generator configured to generate an enhanced IQ mismatch correction function to improve the compensation for IQ mismatch, and an IQ signal receiver with the IQ mismatch correction function generator, wherein the enhanced IQ mismatch correction function is determined based on an initial IQ mismatch correction function derived from IQ mismatch estimates corresponding to frequency bins where signals are present and error of the initial IQ mismatch correction function by comparing the values of the initial IQ mismatch correction function with IQ mismatch estimates corresponding to a respective bin of the frequency bins.
US10715375B2 Modulation method, decoding method, modulation device, and demodulation device
A modulation device includes a mapping circuit configured to map information bits to signal points on a plurality of concentric rings, when a signal space arrangement in which the number of signal points on all of the plurality of rings is the same is used as a basis, reduce the number of signal points on an innermost ring or a plurality of rings from inner to outer rings from among the plurality of rings, generate a new ring outside the signal space arrangement used as the basis, and arrange, on the generated ring, signal points which achieve the same frequency utilization efficiency as that of the signal space arrangement used as the basis.
US10715373B2 Method and device for transmitting/receiving synchronization signal in wireless cellular communication system
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present invention is a method by which a base station transmits a signal in a wireless communication system for efficiently performing an initial access procedure of a terminal, the method comprising the steps of: generating the synchronization signal on a basis of subcarrier spacing used in the synchronization signal; and transmitting the synchronization signal to the terminal.
US10715370B2 Test device and test method for testing a communication
A test device for testing a communication between an access point and at least one station is provided. The test device comprises a communication recorder configured to record the communication between the access point and the at least one station, and a communication analyzer configured to analyze the recorded communication by looking for a burst of a specific type of one specific station of the at least one station. In this context, the communication analyzer is further configured to measure a deviation of an actual communication frequency of the burst of the specific type from a predefined communication frequency.
US10715361B1 Delay compensation using broadband gain equalizer
An electronic circuit can include a gain adjustment circuit (e.g., a gain “equalizer” circuit), such as to compensate for a variation in insertion loss over a specified range of frequencies. For example, such a gain adjustment circuit can provide an insertion loss characteristic having a specified slope. Such a slope can include a positive slope where insertion loss increases with respect to frequency, or a negative slope where insertion loss decreases with respect to frequency, as illustrative examples. A gain equalization technique can be used to compensate for variation in insertion loss versus frequency between different circuit paths, such as in relation to a switchable delay line having two or more selectable paths, such as for phase shifting applications. A gain adjustment circuit can be configured to provide relatively flat or constant time-domain delay versus frequency, such as inhibiting or reducing dispersion.
US10715360B2 Data scrambling method and scrambling apparatus
A data scrambling method and a scrambling apparatus, where the method includes a scrambling apparatus scrambling a data stream including a first data block and a second data block. The first data block and the second data block may belong to a same sub-data stream, or may belong to different sub-data streams. A specification of the data stream when the first data block and the second data block belong to a same sub-data stream is different from a specification of the data stream when the first data block and the second data block belong to different sub-data streams, and the scrambling apparatus can scramble data streams of different specifications.
US10715357B2 Adaptation of a transmit equalizer using management registers
Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.
US10715355B2 Processing module for a communication device and method therefor
A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the generated validation pattern to generate channel estimate validation information.
US10715348B2 Method for processing user information detected by at least one detection device of a system
A method for processing user information detected by at least one detection device of a device, in which information concerning at least one user detected by the at least one detection device is transmitted to a number of databases, and in which the information detected by the at least one detection device is at least partially associated with a user profile, and in which all information stored on the number of databases which has been detected by the at least one detection device and associated with the user profile is retrieved from the number of databases, and as a function of a result of an authentication of the user is output to the user on at least one output unit for processing.
US10715345B2 Communication control device, communication device, computer program product, information processing apparatus, and transmitting method for managing devices in a group
According to an embodiment, a communication control device is connected to communication devices and includes a storage, a generator, and an output unit. The storage is configured to store group information containing a group ID of a group and device IDs of the communication devices belonging to the group. The generator is configured to generate compressed information in which the device IDs are compressed. The output unit is configured to output, when the group information is updated, to all communication devices identified by the device IDs included in the group information after updating and to a plurality of communication devices including one or more of the communication devices identified by the device IDs not included in the group information after updating, output information containing identification information for identifying the group after updating and compressed information in which the device IDs included in the group information after updating are compressed.
US10715343B1 Device monitoring for conference reservation cancellation
Methods, systems, and computer-readable media for device monitoring for conference reservation cancellation are disclosed. A location value is associated with a reservation for a scheduled conference associated with a scheduled starting time and a scheduled ending time. A voice-capturing device is associated with the location value, and the voice-capturing device is configured to send voice input to a service provider environment over a network. Voice input is not received from the voice-capturing device within a duration of time between the scheduled starting time and the scheduled ending time. The reservation is canceled based on determining that the voice input is not received from the voice-capturing device within the duration of time between the scheduled starting time and the scheduled ending time.
US10715340B2 Non-volatile memory with security key storage
A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.
US10715339B1 Distributed key management for trusted execution environments
Disclosed herein are methods, systems, and apparatus, for securely executing smart contract operations in a trusted execution environment (TEE). One of the methods includes establishing, by a key management (KM) TEE of a KM node, a trust relationship with a plurality of KM TEEs in a plurality of KM nodes based on performing mutual attestations with the plurality of KM TEEs; initiating a consensus process with the plurality of KM TEEs for reaching consensus on providing one or more encryption keys to a service TEE of the KM node; in response to reaching the consensus with the plurality of KM TEEs, initiating a local attestation process with a service TEE in the KM node; determining that the local attestation process is successful; and in response to determining that the local attestation process is successful, providing one or more encryption keys to the TEE executing on the computing device.
US10715337B2 Secure crypto module including conductor on glass security layer
A conductor on glass security layer may be located within a printed circuit board (PCB) of a crypto adapter card or within a daughter card upon the crypto adapter card. The conductor on glass security layer includes a glass dielectric layer that remains intact in the absence of point force loading and shatters when a point load punctures or otherwise contacts the glass dielectric layer. The conductor on glass security layer also includes a conductive security trace upon the glass dielectric layer. A physical access attempt shatters a majority of the glass dielectric layer, which in turn fractures the security trace. A monitoring circuit that monitors the resistance of the conductive security trace detects the resultant open circuit or change in security trace resistance and initiates a tamper signal that which may be received by one or more computer system devices to respond to the unauthorized attempt of physical access.
US10715334B2 Methods and apparatus for validating a digital signature
Various embodiments include one or more of systems, methods, software, and data structures for validating a digital signature, wherein common information in a certification chain is maintained in one entry of a Document Secure Store (DSS). The DSS separates the Long Term Validation (LTV) information from the digital signature, allowing amendment of and addition to the LTV information in the DSS after a digital signature is applied to a document.
US10715330B1 Cryptologic blockchain-based custody and authorization tracking for physical concessions
A system supports authorization and custody tracking for physical concessions. In some cases, a physical concession or other physical object may be tracked to ensure that custodians that gain possession of the physical concession have proper authorization. Further, custody tracking may ensure that a particular custodian is issued the authorized amount of physical concession(s). Authorization circuitry may, via a peer network, access proof of authorization and custody status stored on a blockchain. Based on the proof of authorization and custody status, the authorization circuitry may determine whether issuance of the physical concession to a receiving custodian is allowed. After allowing/disallowing issuance of the physical concession, tracking circuitry may send, via the peer network, a request to update the blockchain.
US10715326B2 Systems and methods for managing networked commitments of secure entities
The invention relates to a method of managing commitments between entities forming the nodes of a network, each entity being housed in a computer processing unit, characterized in that it comprises the following steps: —establishing commitments (ENij) between commitment provider entities (Ei) and commitment beneficiary entities (Ej), one and the same entity being able to be both a commitment provider in relation to one or more other commitment beneficiary entities and a commitment beneficiary in relation to other commitment provider entities, —upon the default of an commitment on the part of a defaulting commitment provider entity, noted from a beneficiary entity benefiting from this same commitment, communicating to the provider entity from said beneficiary entity, and at least one other entity (upstream entity) whose defaulting provider entity is beneficiary, an indication of default of a commitment, and, —in response to this communication, altering at least one commitment whose defaulting provider entity is beneficiary. The invention is also aimed at various systems and methods capable, in a secure manner, of implementing programs or commitments which are executable at the level of a set of nodes of a network, for various applications.
US10715325B2 Secure, real-time based data transfer
A method for real-time-based transfer of data telegrams from a verified transmitter to a verified receiver without delays, wherein (a) each data telegram to be transferred from the transmitter to the receiver is provided with an additional data index, (b) each received data is stored in a memory, along with the associated additional data index, (c) after elapse of a predetermined time interval, or after transference of a defined number of data telegrams, the transmitter transfers a second time data telegram already transferred to the receiver which has an additional signature, and where the data telegram transferred the second time is additionally encrypted by the transmitter, and (d) after receiving the signed data telegram transferred the second time, the signed data telegram transferred the second time is compared with the corresponding data telegram stored in the memory to verify the transmitter, and where (e) steps a) to d) are repeated.
US10715322B2 System and method for updating data in blockchain
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for updating data in blockchain are provided. One of the methods includes: obtaining one or more requests for updating a plurality of pieces of data in one or more blockchains and updating the plurality of pieces of data in the one or more blockchains.
US10715314B2 Cloud file system
A cloud storage system supporting user agnostic encryption and deduplication of encrypted files is described. Further the cloud storage system enables users to share a file, a group of files, or an entire file system with other users without a user sending each file to the other users. The cloud storage system further allows a client device to minimize the utilization of bandwidth by determining whether the encrypted data to transfer is already present in the cloud storage system. Further the cloud storage system comprises mechanisms for a client device to inform the cloud storage system of which data is likely to be required in the future so that the cloud storage system can make that data available with less latency one the client device requests the data.
US10715313B2 Systems and computer-based methods of document certification and publication
A method is implemented in a networked computer system that is connected to document issuers and validators and interacts with a blockchain. It comprises generating a master key assigned to an issuer, certifying a document through a first process including generating a document persistence key, encrypting document data with an encryption algorithm and an encryption key derived from three keys (the master key, the document persistence key and an intermediate key), registering encrypted document data in the blockchain, and generating a web address carrying recovery information of the certified document; reading the document through a second process accessible to the web address, the second process including recovering the encrypted data in the blockchain and accessing the three keys, decrypting the encrypted data using the encryption key derived from the three keys, and displaying the document; and upon request from a legitimate holder of the document erasing the persistence key.
US10715307B1 Embedded time of day receiver for clock transmission
In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.
US10715303B2 Apparatus and a method for managing full-duplex communication between a base station and a plurality of user equipments
The invention relates to an apparatus (301) for managing full-duplex communication between a base station (BS0) and a set of user equipments (101a,b), the base station (BS0) comprising a plurality of transmitter antennas, the plurality of transmitter antennas being associated with a downlink communication channel H between the base station (BS0) and the set of user equipments (101a,b) and a plurality of interference channels Gi between the base station (BS0) and a plurality of neighboring base stations (BSi).
US10715302B2 Channelization for signal boosters
Technology for a channelization device of a wideband repeater is disclosed. The channelization device can include a first diplexer and a second diplexer. The channelization device can include a plurality of switchable signal paths between the first diplexer and the second diplexer operable to perform channelized passive filtering of signals in defined bands. The channelization device can include a plurality of switchable pass through signal paths between the first diplexer and the second diplexer operable to pass through signals in the defined bands without filtering of the signals. The channelization device can be configured to perform channelized passive filtering of signals with no amplification of the signals.
US10715300B2 Demodulation reference signal indicating and receiving methods, transmit end, and receive end
A demodulation reference signal (DMRS) indicating method, a DMRS receiving method, and an apparatus are described. A transmit end determines, from a plurality of groups of demodulation reference signal DMRS configuration information, DMRS configuration information corresponding to a current DMRS transmission scheme. The transmit end obtains DMRS indication information based on the DMRS configuration information, where each group of DMRS configuration information includes a plurality of pieces of DMRSs configuration information. The transmit end sends the DMRS indication information. The described method and the apparatus are implemented to match a plurality of New Radio (NR) scenarios. The described operations can satisfy a requirement for transmitting more layers of data and reduce indication overheads.
US10715299B2 Sequence generation and transmission method based on time and frequency domain transmission unit
A method and a user equipment for transmitting control information in a communication system are discussed. The method according to an embodiment includes multiplying a transmission information symbol s for the control information by a frequency direction sequence c(k) to generate a first output sequence s(k), where s(k)=s*c(k), k=0, . . . , Nk−1, and Nk corresponds to a number of subcarriers included in a resource block allocated for an uplink control channel; multiplying the first output sequence s(k) by a time direction sequence x(n) to generate a second output sequence s(k, n), where s(k, n)=s(k)*x(n), n=0, . . . , Nn−1, and Nn corresponds to a number of symbols used for transmission of the control information in a transmission time interval; and transmitting the second output sequence s(k, n) through the uplink control channel in the transmission time interval.
US10715296B2 Method and apparatus for allocating and transmitting time and frequency resource for resource request indicator
Method and apparatus are provided to allocate a time and frequency resource of a resource request indicator (RRI) and to transmit an RRI. Codes are allocated for an RRI and other (such as non-RRI) uplink control signaling. The RRI and other uplink control signaling can be multiplexed in the same time and frequency resource, such as through multiplexing in a code division manner.
US10715294B2 Method and apparatus for sending and receiving control channel in wireless communication system
In a wireless communication system, a control channel is required in order to use limited resources effectively. However, the control channel resource is part of the system overhead, and thus reduces the data channel resource used for data transmission. In the long term evolution (LTE) system based on OFDM, one sub frame the consists of fourteen OFDM symbols wherein a maximum of three OFDM symbols are used for the control channel resource and remaining eleven OFDM symbols are used for the data channel resource. Therefore, the quantity of energy that can be transmitted for the control channel resource is extremely limited compared to the data channel resource. For this reason, the coverage of the control channel becomes less than that of the data channel, and even if a user can successfully receive the data channel, reception failure of a control channel sometimes results in failure of data recovery. In the present invention, in order to expand the coverage of the control channel to at least the coverage of the data channel, the time resource of the transmission resource wherein the control channel is transmitted is expanded and allocated for sending and receiving the control channel. By way of methods for extending the time resource are provided a method wherein a plurality of sub frames are used to transmit one control channel, and a method wherein a part of a data channel is used for the control channel.
US10715287B2 Communication apparatus and control information receiving method
In a base station, a control unit and a data size regulation unit control the data size of downstream assignment control data and upstream assignment control data in the PDCCH signal based on the communication format used between the base station and a terminal, the number of base station antennas (M) (nonnegative number), the number of terminal antennas (N) (nonnegative number), the bandwidth of the downstream band, and the bandwidth of the upstream band. Specifically, the control unit determines it is unnecessary to adjust the aforementioned data size when the selected communication format is first established between multiple antennas and when where there are multiple for one of M and N and only one for the other. The quality of downstream assignment control data is prevented from degrading, while preventing the number of blind determinations from increasing on the receiving side of the downstream control channel signal.
US10715286B2 Separate reporting of RF and BB capabilities of a mobile user equipment in a wireless communications system supporting carrier aggregation
An inventive UE carrier aggregation (CA) capability reporting signalling model allows UEs (30) aggregating large numbers of component carriers to transmit CA-relevant capabilities to the network more efficiently than the current (legacy) signalling model. Rather than reporting CA/MIMO/CSI/NAICS capabilities separately for each supported band combination, including fallback configurations, embodiments of the present invention either report UE Radio Frequency (RF) and Baseband (BB) related capabilities separately, or report them disassociated from CA band configurations. This approach avoids the need to signal the full UE (30) set of capabilities for each of (possibly many) supported band combinations. Furthermore, fallback capabilities are signalled implicitly, eliminating the need to transmit this data.
US10715283B2 Apparatus and method of transmitting and receiving HARQ ACK/NACK information for new radio
Provided are a method of transmitting and receiving HARQ ACK/NACK feedback information in a next-generation/5G radio access network. The method may include receiving, from a base station, HARQ timing indication information to a plurality of the downlink channels, receiving, from the base station, uplink (UL) control channel resource indication information for HARQ feedback to each DL data channel, and transmitting the HARQ information through one or the plurality of the UL control channels indicated by the UL control channel resource indication information in the same slot when the HARQ timing indication information indicates the same slot.
US10715276B2 Bandwidth constrained communication systems with optimized low-density parity-check codes
In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.
US10715273B2 Joint channel estimation and data detection technique to decode 5G uplink control channel
A joint channel estimation and data detection technique for decoding an uplink control channel using resource elements that are redundant in acknowledgement and negative acknowledgement uplink control channel transmissions is disclosed. To improve the performance of a decoder, channel estimation can be performed using reference signals (pilot symbols) to determine the characteristics of a channel at given locations within a subframe. For some uplink control channel formats, however, there aren't dedicated locations for reference signals/symbols, and so channel estimation is not performed. Since the acknowledgement and negative acknowledgement resource elements may be identical, at identical locations within the two different types of messages, the mobile device can replace the resource elements at the redundant locations with reference signals, thus the receiver can perform channel estimation using the reference signals, which can improve the performance of decoding the rest of the acknowledgement, negative acknowledgement transmission.
US10715269B2 Channel frequency spreading device and method for CDMA system, and mobile communication system
The present invention discloses a channel frequency spreading device for a CDMA system, including: an orthogonal sequence generating module, configured to generate orthogonal sequence sets; a storage module, connected to the orthogonal sequence generating module, and configured to store the orthogonal sequence sets; a control module, connected to the storage module, and configured to read available orthogonal sequences in the orthogonal sequence sets when receiving a user request control signal; and a channel machine, connected to the control module, and configured to receive user request data, and perform frequency spreading on the user request data according to the available orthogonal sequences and then output. The channel frequency spreading device for a CDMA system can improve the number of the sequences allocated by the cell, and solve the problem that the excessive users cannot communicate normally.
US10715264B2 Method and apparatus for supporting RS-SINR measurement in wireless communication system
A method and apparatus for performing reference signal signal-to-interference and noise ratio (RS-SINR) measurements in a wireless communication system is provided. A user equipment (UE) receives an indication of certain subframes for performing RS-SINR measurements from a network via a higher layer, and performs the RS-SINR measurements in the certain subframes.
US10715263B2 Information processing apparatus, method and non-transitory computer-readable storage medium
An information processing apparatus includes a memory, and a processor coupled to the memory and configured to obtain location information indicating locations of a wireless transmitter and a wireless receiver, simulate a first power of a first reception signal at the wireless receiver in a condition that a radio signal is transmitted from the wireless transmitter, identify a first probability distribution model in accordance with the first reception signal, identify a first parameter of the first probability distribution model in accordance with the first power and a propagation environment defined by the locations of the wireless transmitter and the wireless receiver indicated by the location information, and based on the first probability distribution model using the first parameter, simulate a second power of a second reception signal at around the wireless receiver.
US10715261B2 Method and apparatus for antenna array calibration using on-board receiver
A method and apparatus for providing feedback for cancellation of signal impairment in a plurality of separate transmit paths of a transmitter are disclosed. According to one aspect, a method includes receiving a plurality of outbound signals transmitted to the antenna array, the received outbound signals having traversed separate transmit paths of the transmitter. The method also includes converting the plurality of received outbound signals to a corresponding plurality of parallel baseband signals. The corresponding plurality of parallel baseband signals are serialized into a serial feedback signal.
US10715260B1 Photonic monopulse comparator
An integrated photonics monopulse comparator includes an array of squinted monopulse elements, each monopulse element producing an RF signal in response to a received inbound signal and each RF signal having a squinted RF voltage. The comparator includes a laser source for producing a wavelength division multiplexed (WDM) optical signal comprising multiple components having discrete wavelengths. The component signals may be multiplexed and demultiplexed and routed through cascading optical phase modulators, each phase modulator connected to a monopulse element and capable of modulating a component signal according to the voltages of the RF signals produced by the corresponding monopulse element. The resulting modulated component optical signals undergo coherent photodetection by arrays of paired photodiodes, each pair receiving component signals of like wavelength. The output signals of each array are proportional in voltage to sums and differences from which arrival angles of the inbound signal may be calculated.
US10715256B1 Recovery of phase-modulated data from an optical signal via intensity measurements
An apparatus includes an optical data receiver to receive a phase-modulated optical signal and to demodulate data therefrom. The optical data receiver includes an optical power splitter, first and second optical intensity detectors, and a digital signal processor. The digital signal processor is connected to receive digital values of intensity measurements of each of the optical intensity detectors. The first optical intensity detector is connected to receive light from the optical power splitter via a first optical path, and the second optical intensity detector is connected to receive light from the optical power splitter via a second optical path. The first and second optical paths have channel functions with different frequency dependencies.
US10715253B2 Associating content with one or more light beacons based on geographical indicator
A system is configured to receive a geographical indicator, to determine at least one light beacon (61-69) based on the geographical indicator, to output information (82) identifying the at least one light beacon, to receive a selection of one or more (61-68) of the at least one light beacon, to receive a content item or a reference to a content item in relation to the one or more light beacons, and to associate the content item with the one or more light beacons. The association causes the one or more light beacons to transmit data via visible light which enables reproduction of the content item.
US10715251B2 Free-space optical communications using few-mode pre-amplified receivers
A free-space optical (FSO) communication system includes a transmitter including a modulated light source and transmit optics for emitting a modulated optical signal into a FS channel toward a receiver. A receiver is coupled to receive the modulated optical signal including receive optics coupled to a few-mode (FM) pre-amplifier that is coupled to a demodulator.
US10715242B1 Grouping antenna elements to enhanced an antenna array response resolution
Apparatuses, methods, and systems for grouping antenna elements to enhance an antenna array response resolution, are disclosed. One method includes selecting a plurality of groups of antenna elements from an antenna array, wherein each group includes a plurality of antenna elements of the antenna array, determining an optimal phase setting for a beam directed from each group to a target device, and characterizing each of the groups including adjusting a phase of an electronic signal passing through each of the antenna elements of the group based on the optimal phase setting of the group, adjusting an amplitude ai of the electronic signal the passing through each of the antenna elements of the group to compensate for a loss of antenna array gain of the antenna array due to grouping of the antenna elements, and storing the adjusted phase and adjusted amplitude for each of the antenna element.
US10715230B2 Transmission method, transmission device, reception method and reception device
A transmission method includes generating a first precoded signal and a second precoded signal by performing a precoding process on a first baseband signal and a second baseband signal, outputting a third signal by inserting a pilot signal into the first precoded signal, outputting a fourth signal by applying a first phase change to the second precoded signal, outputting a fifth signal by inserting a pilot signal into the fourth signal, and outputting a sixth signal by applying a second phase change to the fifth signal.
US10715226B2 Apparatus and method for control signalling in uplink precoding
An apparatus and a method for control signaling are disclosed. The method comprises communicating (402) with one or more user terminals utilising Time Division Duplexing, estimating (404) uplink precoder parameters for the one or more user terminals, the parameters comprising an uplink precoder matrix and a scaling factor and transmitting (406) the uplink precoder parameters utilising a downlink pilot signal and downlink control signalling.
US10715224B2 Terminal, base station, wireless communication system and channel state information acquisition method
A base station is capable of wireless communication with a plurality of terminals, the base station includes a memory that holds information on P (P: an integer of 3 or more) terminals currently connected to the base station, a determination unit that determines L (L: an integer satisfying 2≤L
US10715223B2 Multi VAP simultaneous multi-user transmissions
A transmission method based on Institute of Electrical and Electronics Engineers (IEEE) 802.11 Multi-User (MU) Multiple-Input and Multiple-Output (MIMO). The method includes transmitting, by a plurality of Virtual Access Points (VAPs), respective acknowledgement requests to stations, wherein at least two of the stations are associated with different VAPs of the plurality of VAPs; and transmitting, by the stations to the VAPs, respective block acknowledgements.
US10715222B2 Multi-input multi-output pilot signals
A device controls each antenna to transmit at least one first UL pilot signal and to receive, for each first UL pilot signals DL data encoded according to the respective first UL pilot signal. The receive properties of the DL data are combined and a second UL pilot signal is determined based on the combined receive properties. The second UL pilot signal is repeatedly transmitted. The techniques may be applied in a massive multi-input multi-output scenario.
US10715221B2 Method and apparatus for feeding back information about channel between antenna arrays
A method for feeding back information about a channel between antenna arrays is provided, which includes: receiving, by a first network device, sub-channel channel information of N×M sub-channels that is sent by a second network device, where an antenna array of the first network device includes M panels, an antenna array of the second network device includes N panels, the channel between the first network device and the second network device includes the N×M sub-channels, M is a positive integer that is greater than or equal to 2, N is and N is a positive integer, M and N are not to be 1 at the same time, and the M panels and the N panels each includes at least two antennas; generating channel information of the channel between the first network device and the second network device according to the sub-channel channel information of the N×M sub-channels.
US10715220B2 Multiple input multiple output distributed antenna system architectures
One embodiment is directed to a multiple input, multiple output (“MIMO”) telecommunications system comprising a plurality of signal paths. The system further comprises mixers located in the plurality of signal paths, the mixers being coupled to oscillators for producing a plurality of signals occupying non-overlapping frequency bands and representative of wireless signals. The system further comprises a summer coupled to the plurality of signal paths for summing the plurality of signals to form summed signals. The system further comprises a shared analog-to-digital converter for converting the summed signals to digital signals.
US10715219B2 Apparatus and methods for transmission and reception of data in multi-antenna systems
Methods and apparatus adapted to address asymmetric conditions in a multi-antenna system. In one embodiment, the multi-antenna system comprises a wireless (e.g., 3G cellular) multiple-input, multiple-output (MIMO) system, and the methods and apparatus efficiently utilize transmitter and receiver resources based at least in part on a detected asymmetric condition. If an asymmetric condition is detected by the transmitter on any given data stream, the transmitter can decide to utilize only a subset of the available resources for that stream. Accordingly, the signal processing resources for that data stream are adapted to mirror the reduction in resources that are necessary for transmission. The transmitter signals the receiver that it will only be using a subset of the resources available, and the receiver adapts its operation according to the signaling data it receives. The multi-antenna system can therefore reduce power consumption as well as increasing spectral efficiency on the network.
US10715217B2 Downlink signal pre-correction method and device
A method and a device for pre-correction of a downlink signal are provided. The method comprises: on the basis of an obtained uplink frequency offset value of a first RRU and a second RRU corresponding to each client, determining a set of uplink frequency offset values corresponding to each RRU; when a downlink pre-correction period is reached, calculating an average uplink frequency offset value of the RRU; and on the basis of the average uplink frequency offset value of the RRU and a downlink pre-correction value in a previous pre-correction period, determining a downlink pre-correction value of the RRU in the current downlink pre-correction period.
US10715216B2 Network of electronic devices assembled on a flexible support and communication method
A smart button for use in a network formed on a garment includes a housing and an antenna carried within the housing to communicate with elements of the network. A functional element is carried within the housing. An electronic circuit is carried within the housing and coupled to the antenna and the at least one functional element. The housing is formed by a stem carrying a head, and the antenna is housed within the head.
US10715213B1 Leakage detection for OFDM system with fixed pilot
Cable network test instruments are disclosed. The test instruments are configured to collect signal data across a frequency band and analyze the collected data to determine whether orthogonal frequency division multiplexing (OFDM) signal leakage is present. Methods of identifying OFDM signal leakage are also disclosed.
US10715210B1 Synchronization signal repetition pattern for a discovery reference signal in narrowband communications
There is a need for a mechanism that increases the UE's chance of properly receiving the NPSS and/or NSSS when frequency hopping is used for narrowband communications in the unlicensed frequency spectrum. The present disclosure provides a solution by transmitting the NPSS and NSSS using a synchronization signal repetition pattern in order to increase the detection probability for the DRS, so that synchronization and/or cell acquisition may be achieved with a reduced number of visits to the anchor channel, thereby reducing synchronization delay and increasing the QoS.
US10715207B2 System and method for demodulating code shift keying data utilizing correlations with combinational PRN codes generated for different bit positions
A Global Navigation Satellite System (GNSS) receiver demodulates code shift keying (CSK) data utilizing correlations with combinational pseudo-random noise (PRN) codes generated for different bit positions. The GNSS receiver receives a signal including a PRN code modulated by CSK to represent a symbol (i.e., CSK modulated symbol). The GNSS receiver maintains a plurality of receiver codes, each representing a different shift in chips to the PRN code. The GNSS receiver performs a chip-by-chip linear combination of a group of receiver codes for each bit position of the CSK modulated symbol. The GNSS receiver correlates the received signal with each combinational PRN code to produce a binary value that is the CSK modulated symbol.
US10715204B2 Reconfigurable electrical balance duplexer (EBD) supporting frequency division duplex (FDD) and time division duplex (TDD)
Systems, methods, and devices for operating in either frequency division duplexing (FDD) or time division duplexing (TDD) for wireless communications using the same electrical balance duplexer (EBD) circuitry in a transceiver device are provided. A series of switches may selectively couple components of the EBD, such as a low noise amplifier (LNA), a power amplifier (PA), and balancing impedance, to ground based on selected operation mode (e.g., FDD or TDD) while reducing insertion loss of the receiver (RX) and transmitter (TX) signals. Tuned matching network blocks for the LNA and PA may be used in addition to the series of switches to provide impedance matching for additional reduction of insertion loss.
US10715201B2 Receiving module, transmitting module, and radio frequency system
A receiving module and related products are provided. The receiving module is disposed adjacent to an antenna group corresponding to the receiving module and includes one or more signal receiving channels, a first transfer switch, and a second transfer switch. Each of the one or more signal receiving channels includes a filter and a low noise amplifier coupled with the filter. The first transfer switch is coupled with the one or more signal receiving channels and is configured to be coupled with an antenna in the antenna group. The second transfer switch is coupled with the one or more signal receiving channels and is configured to be coupled with a transmitting module and/or a radio frequency transceiver. The first transfer switch or the second transfer switch includes an n1Pn2T switch, and n1 is a positive integer and n2 is an integer greater than or equal to 2.
US10715197B2 Exterior cover
An exterior cover of an electronic device includes a cradle cover to which the electronic device is fitted, a top cover that opens or closes a front face of the electronic device, and a connecting member interconnecting the top cover and the cradle cover. The top cover is configured to be conformally engaged with the cradle cover and to maintain the conformally engaged state. An exterior cover for an electronic device includes a cradle cover to which the electronic device is fitted, a top cover that opens or closes a front face of the electronic device, and a connecting member interconnecting the top cover and the cradle cover, wherein the top cover is configured to be conformally engaged with the cradle cover.
US10715192B2 Signal processing apparatus, signal processing method, and storage medium
A signal processing apparatus includes a unit configured to generate noise cut data by deducting a predetermined noise value from values of respective signals constituting input data and a stochastic resonance processing unit configured to subject the noise cut data to a predetermined stochastic resonance processing. The predetermined stochastic resonance processing is processing to output, in a method of synthesizing a result of parallelly performing steps of adding new noise to the noise cut data to subject the resultant data to a binary processing, a value obtained in a case where the parallel number is infinite.
US10715191B2 Method for characterizing nonlinear distortion of transmitter, associated transmitter and characterization circuit thereof
A method for characterizing nonlinear distortion of a transmitter, an associated transmitter and a characterization circuit thereof are provided. The method includes: utilizing a transmitting chain circuit within the transmitter to generate an output signal according to a test signal; utilizing a loop back circuit within the transmitter to generate a loop back signal according to the output signal; calculating a plurality of distorted indices respectively corresponding to a plurality of test samples of the test signal according to a plurality of loop back samples of the loop back signal, wherein the plurality of test samples correspond to the plurality of loop back samples, respectively; dividing the plurality of distortion indices into multiple groups according to power of the plurality of test samples; calculating an average value of distortion indices within each group of the multiple groups; and characterizing the nonlinear distortion of the transmitter according to the average value.
US10715187B2 Antenna bandwidth enhancement for an electronic device
Techniques are disclosed for configuring a broadband antenna system. An example electronic device includes a first antenna operating at a first frequency range and coupled to a first transceiver via a first signal path comprising a first indirect feed. The electronic device also includes a second antenna operating at a second frequency range and coupled to a second transceiver via a second signal path comprising a second indirect feed, wherein the first frequency range is lower than the first frequency range. The electronic device also includes a third antenna operating at the second frequency range and coupled to a third transceiver via a second signal path comprising a third indirect feed. Additionally, the first antenna is coupled to the first antenna and the second antenna by a capacitive coupling element.
US10715180B1 Circuit for error correction and method of same
A circuit for error correction comprises a first RS syndrome generator to generate a first RS syndrome for a RS(n, k) code according to a received symbol stream to be decoded, wherein k and n are respective the number of data symbols and the total number of code symbols in the received symbol stream to be decoded; a first decision unit communicatively coupled to the first RS syndrome generator and configured to determine whether there are at least N symbols in the first RS syndrome that equal 0, wherein N is related to a code distance of the RS(n, k) code; and a first adder communicatively coupled to the first decision unit and configured to output a corrected decoded codeword by adding the first RS syndrome to the received symbol stream to be decoded if there are at least N symbols in the first RS syndrome that equal 0.
US10715179B2 Low density parity check code for terrestrial cloud broadcast
Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value.
US10715177B2 Lossy compression drive
A method for lossy data compression, the method including receiving raw data at a storage device, receiving a request to compress flag, accessing an onboard data compression algorithm library containing various data compression algorithms respectively corresponding to lossy data compression schemes, selecting one of the data compression algorithms based on a number of parameters, running the selected data compression algorithm either online such that the raw data is compressed by the storage device when it is received, and is then stored on the storage device as compressed data, or offline such that the raw data is stored at the storage device, is later compressed by the storage device according to the selected data compression algorithm, and is resaved at the storage device as compressed data.
US10715175B2 Systems and methods for encoding and decoding
Various embodiments of the invention provide systems, devices, and methods for decompressing encoded electronic data to increase decompression throughput using any number of decoding engines. In certain embodiments, this is accomplished by identifying and processing a next record in a pipeline operation before having to complete the decompression of a current record. Various embodiments take advantage of the knowledge of the method of how the records have been encoded, e.g., in a single long record, to greatly reduce delay time, compared with existing designs, when decompressing encoded electronic data.
US10715171B1 Voltage-mode DAC driver with parallel output resistance tuning
A voltage-mode digital-to-analog converter (DAC) includes input circuitry and an array of output impedance units disposed in parallel. The input circuitry receives a digital word of N bits. A selectable number of the output impedance units are activated to produce a desired aggregate output impedance. The selectable number is free to be a number different than N.
US10715166B2 System and method for high-sample rate transient data acquisition with pre-conversion activity detection
Diverse applications in particle physics experiments and emerging technologies such as Lidar are driving performance increase and cost reduction in giga-hertz sampling-rate high-resolution data conversion. In applications such as these, critical aspects of the data may occur only during relatively short nanosecond portions of observation periods lasting microseconds. Data acquisition architectures that key in on regions of the data containing activity, digitize the data, and provide info to accurately measure the position of the data in time relative to a time reference are described. These architectures may facilitate system implementation and reduce overall system cost.
US10715162B2 Background calibration of random chopping non-idealities in data converters
Random chopping is an effective technique for data converters. Random chopping can calibrate offset errors, calibrate offset mismatch in interleaved ADCs, and dither even order harmonics. However, the non-idealities of the (analog) chopper circuit can limit its effectiveness. If left uncorrected, these non-idealities cause severe degradation in the noise floor that defeats the purpose of chopping, and the non-idealities may be substantially worse than the non-idealities that chopping is meant to fix. To address the non-idealities of the random chopper, calibration techniques can be applied, using correlators and calibrations that may already be present for the data converter. Therefore, the cost and digital overhead are negligible. Calibrating the chopper circuit can make the chopping more effective, while relaxing the design constraints imposed on the analog circuitry.
US10715160B1 Low noise analog-to-digital converter
Noise sources in an ADC circuit can include kT/C noise of a sampling capacitor, noise coupling on to sampling capacitors from digital circuits, and amplifier noise. Also, charge injection from mismatch in sample switches can cause offsets. These various noise sources can be largely canceled or reduced using described techniques. As a result, the size of the sampling capacitors can be greatly reduced, while still achieving significantly improved noise performance and power efficiency for the overall converter.
US10715150B1 Inductor-less divide-by-3 injection locked frequency divider
A frequency divider circuit includes an oscillator comprising a plurality of delay elements coupled in series with each other, a first coupling circuit coupled to a first oscillator node and including a control terminal to receive a first retiming signal, and a first multiplexer including inputs coupled to receive the input signal and a complementary input signal, a control terminal coupled to a second oscillator node, and an output to provide the first retiming signal. The first multiplexer may be configured to alternate between injecting the input signal into the first oscillator node based on rising edges of the input signal and injecting the input signal into the first oscillator node based on falling edges of the input signal in response to a logic state of an oscillation waveform appearing at the second oscillator node.
US10715146B2 Integrated circuit with level shifter
A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.
US10715145B2 Bidirectional analog multiplexer
An analog multiplexer includes inputs and one output. A switching circuit is coupled between each input and the output. Each switching circuit includes an NMOS switching module, having an on state and an off state, and a control module supplied by a first supply voltage and operating to reduce leakage currents of the NMOS switching module when in the off state. The control module further operates to make the first NMOS switching module bidirectional irrespective of voltages present at the input and at the output.
US10715142B2 Low-voltage differential signal driver and receiver module with radiation hardness to 300 kilorad
An LVDS device wherein driver and receiver functionalities are integrated in the same package, signals are routed from the individual driver and receiver elements inside the package such that all inputs are one side of the package, and all outputs are on the opposite side of the package, allowing for an optimized signal flow through the package. All required capacitors and resistors are integrated inside the package; no external electronic components are required. All of the above novelties also contribute to a 6:1 reduction in size compared to current state-of-the-art, for the same number of communication channels. Embodiments include a packaging topology adaptable to extreme environments, including radiation tolerant to 300 kRad (based on the die technology), so that module operational temperature is in a range of −55° C. to +100° C. and storage temperature can be as low as −184° C.
US10715140B2 Laminated light guide and electrical component carrier
A laminated light guide and component carrier includes a light guide of a light transmissive polymeric material. The light guide has a pocket in a first face. First electrical traces are printed on the first face. A light emitting diode is positioned in the pocket and supported on the light guide by attachment legs which extend outward from the pocket electrically connecting the light emitting diode to the first electrical traces. A light reflector is formed as a texturally modified area of the light guide directly aligned with the light emitting diode. A capacitive touch sensor is printed on a light guide second face and connected to second electrical traces defining capacitive touch traces printed on the second face. A window region of the light guide is defined where the capacitive touch sensor is aligned with the light reflector and the light emitting diode.
US10715136B2 Current sense devices and associated methods
A current sense device includes a reference transistor for electrically coupling to a power transistor, a sense transistor for electrically coupling to the power transistor, and control circuitry. The control circuitry is configured to (a) control current through the sense transistor such that a voltage at the sense transistor has a predetermined relationship to a voltage at the power transistor, and (b) control current through the sense transistor according to one or more operating conditions at the reference transistor, to compensate for aging of the power transistor.
US10715135B2 Advanced gate drivers for silicon carbide bipolar junction transistors
A gate driver circuit comprises a sensor, an amplifier, a regulator and a gate driver. The sensor is configured to sense a collector-emitter voltage and includes a first resistor and a second resistor connected in series, a high voltage diode connected between the series connected first and second resistors and a first capacitor connected parallel to the second resistor. The amplifier is configured to amplify a sensor output voltage and includes a non-inverting operational amplifier controlled by means of a plurality of resistors, a voltage follower connected to an output terminal of the non-inverting operational amplifier through a first diode and a third resistor connected across the first diode and the voltage follower. The regulator is configured to regulate a regulator output voltage based on an amplifier voltage. The gate driver is configured to connect/disconnect the regulator output voltage to the base terminal of the BJT.
US10715134B2 Power module, reverse-conducting IGBT, and drive circuit
A power module which includes a power semiconductor chip that includes an IGBT and a freewheeling diode formed in the same chip, and the power module includes a drive circuit that is connected to the power semiconductor chip and drives the IGBT on/off. The power module is configured by packaging the power semiconductor chip and the drive circuit, and is characterized by further including a capacitor and a switch element disposed in series between the emitter of the IGBT and the ground of the drive circuit. The switch element connects the emitter and the ground in the case where the drive circuit has the IGBT perform a turn off switching operation.
US10715131B2 Switching power device
A switching power device (100) is provided which comprises: a normally-ON transistor (12), a normally-OFF metal-oxide-semiconductor field-effect transistor (MOSFET) (14), the normally-OFF MOSFET (14) being connected in series to a source terminal (12S) of the normally-ON transistor (12), and a driver (16) connected to and arranged to drive a gate terminal (12G) of the normally-ON transistor (12). A switching transistor (28) can then be positioned between the source terminal (12S) of the normally-ON transistor (12) and a common connection (30) of the driver (16) to protect the switching power device (100) from deleterious over-voltage and over-current spikes.
US10715124B2 Glitch-free clock generator and method for generating glitch-free clock signal
A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.
US10715123B1 Error correction for stepwise signal modification circuits
Circuits and methods for correction of errors in multi-stage stepwise signal modification circuits. Embodiments of the invention also provide flexibility to correct accuracy errors over a range of conditions, such as differences in signal frequency and/or temperature. A first embodiment includes sorting actual values of a multi-stage stepwise signal modification circuit to generate a monotonic listing of actual values; mapping input codes to a new order of codes corresponding to the sorted actual values; and providing mapping functionality to convert each input code into a mapped output code. A second embodiment includes searching, for each ideal value corresponding to an input code, all actual values of a multi-stage stepwise signal modification circuit for the actual value closest to the ideal value; mapping input codes to a new order of codes corresponding to the closest actual values; and providing mapping functionality to convert each input code into a mapped output code.
US10715122B2 Voltage-controlled delay generator
An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.
US10715120B2 Semiconductor apparatus
A semiconductor apparatus includes a first voltage detection circuit configured to generate a first voltage detection signal in response to the voltage level of a first voltage, a current control signal and a second voltage detection signal; and a storage and output circuit configured to generate a power control signal and the current control signal in response to the voltage detection signal.
US10715115B2 Circuits and methods for preventing bias temperature instability
Circuits and methods for balancing Bias Temperature Instability (BTI) are disclosed. An inverter circuit comprises an inverter input node configured to receive an inverter input signal, wherein the inverter input node is coupled to gates of an inverter pair, wherein the inverter pair includes an inverter pair n-type metal-oxide-semiconductor (NMOS) transistor and an inverter pair p-type metal-oxide-semiconductor (PMOS) transistor, an inverter output node configured to provide an inverter output signal, wherein the inverter output signal is an inversion of the inverter input signal, and at least one balancing transistor configured to balance a voltage at a source of the inverter pair PMOS, a source of the inverter pair NMOS, or any combination thereof.
US10715114B1 Filter and operating method thereof
A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal. Therefore, the filter of the present invention and its method of operation can provide an accurate filtered signal output function.
US10715108B2 Filter device and multiplexer
A filter device includes a first ladder filter including serial resonators disposed in a terminal-to-terminal path and parallel resonators disposed in connection paths, a first acoustic wave resonator disposed in parallel to the parallel resonator, and a second acoustic wave resonator disposed in parallel to the serial resonator. Resonance points and anti-resonance points of the first and second acoustic wave resonators are both positioned on the lower frequency side or the higher frequency side of a pass band of the first ladder filter, and on the same side of the pass band of the first ladder filter, when viewed from the pass band of the first filter.
US10715097B2 Multiplexer and communication apparatus
A multiplexer includes a first filter disposed on a first signal path, a second filter disposed on a second signal path different from the first signal path, the second filter having a passband different from that of the first filter, a common connection point at which the first signal path and the second signal path are connected to each other, and an inductor disposed in series on a path connecting the common connection point and the first filter, the path being a portion of the first signal path. On the first signal path, a distance connecting the common connection point and the inductor is shorter than a distance connecting the inductor and the first filter.
US10715096B1 Capacitance-to-voltage interface circuit
Systems and methods for converting a capacitance signal into a band-limited voltage signal for improved signal processing are disclosed herein. Such systems can include a capacitance-to-voltage converter configured to convert a capacitive signal from a capacitive device that operates at a mechanical frequency into a raw voltage signal, a clock generator configured to convert the mechanical frequency into one or more clock signals, and a filter component configured to apply a band-pass filter response to the raw voltage signal to convert the raw voltage signal into a band-limited voltage signal. The clock generator can be configured to apply the one or more clock signals to the filter component to drive a first pole and a second pole of the band-pass filter response to track the mechanical frequency of the capacitive device such that the geometric mean of the first pole and the second pole is substantially equal to the mechanical frequency.
US10715092B2 Power management in transceivers
Various embodiments are directed to apparatuses and methods to generate a first signal representing modulation data and a second signal representing an amplitude of the modulation data, the first signal and the second signal to depend on an output signal and vary a power supply voltage to a gain stage in proportion to the amplitude of the modulation data.
US10715087B2 CMOS wideband RF amplifier with gain roll-off compensation for external parasitics
The present disclosure relates to an integrated wideband Radio Frequency (RF) amplifier, based on a complementary metal oxide semiconductor (CMOS) technology. In an embodiment the amplifier addresses the shortcomings of conventional wideband amplifiers and is based on a distributed amplifier (DA) topology which typically exhibit severe performance degradation when externally loaded with parasitic circuit elements. In an embodiment of the present invention a buffer amplifier at the output of a conventional DA is able to compensate the impact of parasitic elements. The disclosed circuit can be implemented by fabricating the wideband RF amplifier integrated circuit (IC) on a 130 nm CMOS technology or other comparable CMOS technologies.
US10715086B2 Amplifier circuit
An amplifier circuit includes a first transistor, a second transistor, a first pathway and a second pathway. The first transistor amplifies an external signal that is input from outside the amplifier circuit. The second transistor amplifies a detection signal that detects a level of the external signal. The first pathway is connected between a collector of the first transistor and a base of the second transistor to supply the detection signal that is output from the collector of the first transistor to the base of the second transistor. The second pathway is connected between an emitter of the first transistor and the base of the second transistor to supply a bias voltage from the emitter of the first transistor to the base of the second transistor.
US10715073B1 Robot electronics unit (REU) motor controller board (MCB)
The present invention relates to a Robot Electronics Unit (REU) motor controller board (MCB) with a trapezoid wave design, which can utilize power efficiently and reduce electromagnetic interference. The MCB uses a modulator or Buck Converter to regulate the voltage before it is passed to the motors used in robotic arms in space applications. The REU MCB includes: a commutator disposed on the MCB and connected to a three-phase induction motor; and a modulator disposed on the MCB and which precedes the commutator, the modulator which utilizes pulse width modulation (PWM) to regulate a voltage to the commutator and provide a predetermined current to the commutator. The modulator regulates the voltage by stepping it down from a 100V power input signal before the voltage is passed to the motor. The output of the modulator includes a trapezoid waveform design which controls the motor and reduces electromagnetic interference.
US10715071B2 Method and apparatus for generating motor drive signal
A method for generating a motor drive signal is disclosed, which includes: obtaining a non-resonance frequency sine signal, and inputting the non-resonance frequency sine signal into a first system; processing, by the first system, the non-resonance frequency sine signal to obtain a correction input signal; inputting the correction input signal into a second system, and processing, by the second system, the correction input signal to obtain an output signal in the same mathematical form as the non-resonance frequency sine signal, wherein the first system is an inverse system of the second system; and using the output signal of the second system as the motor drive signal. The present disclosure further provides an apparatus for generating a motor drive signal. The method and apparatus for generating a motor drive signal enable the motor to have a smooth output effect after being excited by the non-resonance frequency sine signal.
US10715069B2 Discharge control device
A discharge control device performs discharging of a capacitor, in a state in which a battery is not connected to an inverter that drives a motor, by causing electric charges accumulated in the capacitor connected to the inverter to be consumed by windings of the motor. The discharge control device performs the discharging of the capacitor by sequentially generating command values for voltages applied to a α axis and a β axis while causing a voltage phase in an αβ stationary coordinate system having a rotation axis of a rotor of the motor as an origin and defined by the α axis and the β axis orthogonal to each other to be inverted in a predefined period.
US10715061B2 Motor control device
A motor control device includes: a PWM controller that PWM-controls an inverter driving a three-phase motor and including three arm portions, each including a high-side switching element and a low-side switching element connected in series with each other between a first power supply line and a second power supply line connected to a potential lower than a potential of the first power supply line. In an energizing period and a non-energizing period in a case where the three-phase motor is energized from the first power supply line through the PWM-control of the inverter, during a first predetermined period in the energizing period immediately before transition from the energizing period to the non-energizing period, the PWM controller performs a SWEEP of a signal applied to one of the high-side switching element and the low-side switching element, and performs a synchronous rectification control.
US10715058B2 Piezoelectric device and electronic apparatus
A piezoelectric device includes an insulating substrate, a piezoelectric vibration device that is mounted on a device mounting pad, a metal lid member that seals the piezoelectric vibration device in an airtight manner, an external pad that is arranged outside the insulating substrate, an oscillation circuit, a temperature compensation circuit, and a temperature sensor. The lid member and the temperature sensor or the lid member and the IC component are connected to each other so as to be heat-transferable, and a heat transfer member having thermal conductivity higher than that of the material of the insulating substrate is additionally included.
US10715055B2 Power semiconductor circuit having a field effect transistor with low energy losses
A power semiconductor circuit comprising a field effect transistor having a drain, a source and a gate as terminals, and further comprising a control device having a drive device and an undervoltage detection circuit. The drive device drives the field effect transistor and is electrically connected to the gate of the field effect transistor. The undervoltage detection circuit generates an undervoltage detection signal if a power semiconductor voltage present between the drain and the source of the field effect transistor falls below a specific voltage value. The drive device switches on the field effect transistor when a switch-on command for switching on the field effect transistor and the undervoltage detection signal are present. The invention provides a power semiconductor circuit with low energy loss.
US10715053B2 Power conversion apparatus in which an inductance of a last off closed circuit is smaller than an inductance of a non-last off closed circuit
A power conversion apparatus is provided in which an upper arm semiconductor device, a lower arm semiconductor device and a capacitor. At least either upper arm semiconductor device or lower arm semiconductor device constitutes a parallel-connected body. In an opposite arm against the parallel-connected body, a permissible element is provided. In the switching elements that constitute the parallel-connected body, a last off element and a non-last off circuit are identified. Inductance of a last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor is smaller than inductance of a non-last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor.
US10715051B2 Resonant power conversion device including an adjustment amount calculator
A resonant power conversion device includes: series-connected filter capacitors disposed at an input side and transformers, a power conversion circuit disposed between a primary side of the transformer and the filter capacitor, and a power conversion circuit disposed between a primary side of the transformer and the filter capacitor. The resonant power conversion device further includes: an adjustment amount calculator for calculating an adjustment amount indicating a delay time of a rise of a pulse of a control signal to a switching element or a switching element in accordance with a voltage difference between the filter capacitors; and a controller for, in accordance with the adjustment amount, causing a delay in the rise of the pulse of the control signal to the switching element or the switching element, and outputting the rise-delayed control signal to the switching elements.
US10715044B1 Single stage multi-outputs circuit and a method thereof
A control circuit of a power converter providing at least a first output voltage and a second output voltage, having: a first loop control circuit, configured to provide a first error amplifying signal based on the first output voltage and a first reference voltage; a second loop control circuit, configured to provide a second error amplifying signal based on the second output voltage and a second reference voltage; a saturation detecting circuit, configured to provide a saturation indicating signal based on the first error amplifying signal and a saturation reference signal; and a first current source circuit, configured to charge an output terminal of the second error amplifier based on the saturation indicating signal.
US10715043B2 Single inductor multiple output power converter with overload control
A single inductor multiple output SIMO power converter and method are presented. The converter has a single inductor and at least two output terminals which are denoted as first output terminal and second output terminal. The SIMO power converter also has a first switching element and a second switching element. The first switching element is coupled between an output terminal of the inductor and the first output terminal of the SIMO power converter. The second switching element is coupled between the output terminal of the inductor and the second output terminal of the SIMO power converter. The SIMO power converter also has a control circuit to detect an overload condition at the first output terminal, and to generate control signals for controlling the switching of the first switching element and the second switching element based on the detected overload condition.
US10715038B1 Apparatus and method for frequency quintupling
A circuit includes a first TSCP (tri-stage charge pump), a second TSCP, a third TSCP, a fourth TSCP, a fifth TSCP, and a load. The first TSCP receives a first phase and a third phase of a five-phase clock and outputs a first current to an output node. The second TSCP receives a second phase and a fourth phase of the five-phase clock and outputs a second current to the output node. The third TSCP receives a third phase and a fifth phase of the five-phase clock and outputs a third current to the output node. The fourth TSCP receives a fourth phase and the first phase of the five-phase clock and outputs a fourth current to the output node. The fifth TSCP receives a fifth phase and the second phase of the five-phase clock and outputs a fifth current to the output node. The load terminates the output node.
US10715036B2 DC-DC transformer with inductor for the facilitation of adiabatic inter-capacitor charge transport
In a power converter, a switching network having switches that operate at a common frequency and duty cycle interconnects circuit elements. These circuit elements include capacitors that are in a capacitor network and a magnetic filter. When connected to the capacitors by a switch from the switching network, the magnetic filter imposes a constraint upon inter-capacitor charge transfer between the capacitors to maintain the filter's second terminal at a voltage. The switching network transitions between states. These states include a first state, a second state, and a third state. In both the first state and the third state, the first magnetic-filter terminal couples to the capacitor network. In the second state, which occurs between the first and third state, the switches ground the first magnetic-filter terminal.
US10715031B2 Power converter
In order to achieve small noise and small vibration, as well as a small size and a low cost in a power converter including a capacitor module, there is provided a power converter including a power module and a capacitor module. The capacitor module includes: a plurality of capacitor elements each having a flat wound surface; an exterior case; a resin filler; and a restraint point. The exterior case has arranged therein an inclusion serving as a beam in a direction orthogonal to a flat wound surface of at least one capacitor element of the plurality of capacitor elements, and the at least one capacitor element, and the restraint point is arranged substantially in front of the flat wound surface via the inclusion.
US10715025B2 Radial magnetic cycloid gear assemblies, and related systems and methods
A magnetic cycloid gear assembly includes an outer magnet drum comprising a plurality of outer drum magnets having a first number of magnetic pole pairs. The assembly also includes a first inner magnet drum comprising a first plurality of inner drum magnets having a second number of magnetic pole pairs. The assembly also includes a second inner magnet drum comprising a second plurality of inner drum magnets having a third number of magnetic pole pairs. Each of the first and second inner drums has an inner magnet drum axis that is offset from an outer magnet drum axis. The assembly further includes a plurality of drive mechanisms, each mechanism being operatively coupled to each of the first and second inner drums. The plurality of drive mechanisms is configured to drive each of the first and second inner magnet drums to revolve in an eccentric manner about the outer drum axis.
US10715023B2 Vibratory actuator, wearable terminal, and incoming call notification function device
The purpose of the present invention is to provide a vibratory actuator the size of which can be reduced and which effectively produces vibrations felt by a user. The vibratory actuator has: a stationary body which has a curved surface section curved in a concave shape to be placed along the skin; and a movable body which is disposed on the curved surface section so as to be able to move with respect to the stationary body in a reciprocating manner along the curved surface section, thereby imparting a vibratory stimulus caused by the reciprocating motion to mechanoreceptors in the skin tissue via the curved surface section.
US10715022B2 Actuator and electric beauty device
The purpose of the present invention is to provide an actuator that has a simple configuration and can stably achieve high output without the occurrence of magnetic saturation. This actuator has: a movable body provided with a cylindrical magnet section having alternately N-pole faces and S-pole faces on the peripheral surface surrounding a rotation shaft; and a fixed body provided with, pole tooth surfaces of the same number as the N-pole faces and the S-pole faces, and a coil that excites the pole tooth sections. The movable body has as a turning reference position a position at which the center of the pole tooth surfaces in the circumferential direction and the switching position of the pole faces of the magnet section face each other, and is held to the fixed body so as to be turnable back and forth around the rotation shaft in the circumferential direction.
US10715021B2 Mobile capsule device and control method thereof
A mobile capsule device 10 comprises a long capsule body 11 having a permanent magnet 13 movable in the lengthwise direction with respect to the long capsule body and a coil for driving the permanent magnet 13, while a propulsion force is generated entirely by applying an alternate current to the coil and performing back and forth movements of the permanent magnet 13. The coil has first and second coil parts 15 and 16 arranged circumferentially in front and back of the permanent magnet 13, and a frequency of an alternate current applied to the first and second coil parts 15 and 16 is made to accord with a resonance frequency of the capsule device 10 generated by a back and forth vibration of the permanent magnet 13. Thereby, a self-propelled, mobile capsule device 10 which is downsized, compact and efficient and a control method thereof can be provided.
US10715019B2 Dual axis motor
A dual axis motor a first epicyclic gear, a second epicyclic gear, a rim gear, an inner rotor, an outer rotor, a brake and a stator assembly. The second epicyclic gear is operative to mesh with the first epicyclic gear and move in around the first epicyclic. The inner rotor is fixedly connected to the first epicyclic gear. The outer rotor fixedly is connected to the second epicyclic gear. The stator assembly spaced from the inner rotor by a first gap and spaced from the outer rotor by a second gap. The motor provides a resultant torque to driven device. The resultant torque is provided by the inner rotor, outer rotor, the brake, or by sudden deceleration of one or more elements within the dual axis motor. The gear ratio provided by the first and second epicyclic gear allow for an enhanced speed range while providing high starting torque.
US10715018B2 Alternator device
An alternator device for converting mechanical energy into electrical energy, including first rotating disk comprising first coils ducts; second rotating disk including second coil ducts; a magnet located intermediate the first and second rotating disks to generate first magnetic field having first magnetic pole at the first coil ducts and second magnetic field having second magnetic pole opposite the first magnetic pole at the second coil ducts; and a coil base intermediate the first and second rotating disks, the coil base to receive coils aligned with the first and second coil ducts; wherein the first and second rotating disks are adapted to rotate along a rotation axis while the magnet and the coil base remain in static position, rotation of the rotating disks enabling a rotational movement of the magnetic fields through the coils for generation of electric current within the coils, and a method of manufacturing such device.
US10715016B2 Winding device and winding method
A winding device includes a winding core configured to take up a wire, wherein the winding core includes an inner winding core configured to be rotated by a rotating part and an outer winding core configured to surround the inner winding core and rotate together with the inner winding core.
US10715014B2 Electric motor
A low voltage high current permanent magnet DC electromagnetic heteropolar motor, including (a) at least one permanent magnet rotor; (b) a shaft in mechanical communication with the rotor such that axial rotation of the rotor causes axial rotation of the shaft; (c) at least one stator winding; (d) a plurality of switches, each functioning to provide commutation switching for the stator so as to generate a torque on the rotor and thereby cause said axial rotation of the shaft, wherein a terminal voltage of said machine is equal to the voltage of one electrochemical cell, and wherein the power of said machine is at least 1 kW.
US10715013B2 Compact high speed generator having respective oil and air cooling passages
A method for generating electrical power may include the steps of rotating a rotor of a generator at a speed in excess of about 12,000 revolutions per minute (rpm) to about 25,000 rpm and producing power with the generator at a rate in excess of about 800 kilowatts (kW). The generator has a power/weight ratio no smaller than about 3 kW/lbs. A rotor is cooled with cooling oil internally circulated through the rotor of the generator so that contact of cooling oil with external surfaces of the rotor may be precluded. The stator is also cooled with oil that is prevented from contacting the external surfaces of the rotor. Pressurized airflow may be produced in a gap between the rotor and a stator of the generator to preclude entry of cooling oil into the gap.
US10715007B2 Devices and methods for increasing energy and/or power density in composite flywheel energy storage systems
A flywheel formed of a composite material having fibers, oriented substantially in a circumferential direction around the flywheel, embedded in a matrix material. The flywheel having an inner surface, an outer surface, and a thickness therebetween and defining an axis of rotation. A plurality of load masses are distributed circumferentially on the inner surface at a longitudinal segment along the axis. A rotation of the flywheel about the axis with a rotational velocity generating hoop stress in the fibers in the circumferential direction and through-thickness stress is generated in the matrix material in a radial direction. Each load mass produces a force on the inner surface operative to reduce the maximum through-thickness stress in the matrix material as the flywheel rotates about the axis. The rotational velocity otherwise sufficient to produce structural failure of the matrix material produces structural failure of the fibers and not the matrix material.
US10715006B2 High power flywheel system with rotor having a flowable back iron and a composite structure support
A flywheel energy storage system includes a rotating assembly having a plurality of magnets and a longitudinal axis about which the rotating assembly rotates and static assembly having a stator configured to magnetically interact with the plurality of magnets of the rotating assembly. The rotating assembly includes a rotor back iron supporting the plurality of magnets and disposed further from the longitudinal axis in a radial direction than the plurality of magnets. The back iron being formed of a material having a first stiffness, relative permeability of at least 10, and an electrical conductivity 10% or less than the electrical conductivity of magnetic steel. There is composite structure supporting the rotor back iron and disposed further from the longitudinal axis in a radial direction than the rotor back iron. The composite structure comprises a composite material having a second stiffness, which is greater than the first stiffness.
US10715002B2 Ammonia-resistant motor used for closed-type refrigerating compressor
An ammonia-resistant motor used for a closed-type refrigerating compressor comprising a stator and a rotor; during work, the stator and the rotor of the motor are immersed in the ammonia refrigerant; the winding, the slot wedge and the slot insulation are locked through self-lock fasteners, thereby preventing them from moving in the slot; the self-lock fasteners are fluorine plastic fasteners; the end portion of the motor winding is wound with a layer or multi-layers of fluorine plastic tape, and the outer layer of the fluorine plastic tape is provided with a binding tube; the binding tube is made from fluorine plastic, and the tensile strength of the binding tube is greater than that of the fluorine plastic tape.
US10715001B2 Dynamo-Electric Machine
To improve insulation reliability of a dynamo-electric machine. A stator or a dynamo-electric machine using the stator according to the present invention includes a stator iron core in which a plurality of slots aligned in the circumferential direction are formed, a plurality of segment coils inserted into the slots and formed nearly into a U-shape, and an insulator arranged between the segment coils, and the insulator has a part of the insulator formed thicker than the other part of the insulator.
US10714999B2 Rotor with lattice structure
A rotor for an electric machine, comprising an outer shell for receiving magnets, and a three-dimensional lattice structure arranged within the outer shell where the three-dimensional lattice structure has a unit cell comprising at least a strut and varies in all directions in space including in an axial direction of the rotor.
US10714992B2 Motor including plurality of rotor parts
A motor includes a stator including windings and a rotor. The windings include a first winding and a second winding connected in series. The rotor includes a plurality of rotor parts arranged in an axial direction. Each of the rotor parts includes a first magnet pole unit including a permanent magnet and a second magnet pole unit opposing the second winding at a rotational position of the rotor where the first magnet unit opposes the first winding. The second magnet pole unit applies a weaker magnetic force to the stator than the first magnet pole unit. The rotor parts each include an equal number of magnet poles. The first magnet pole units of the rotor parts are located at positions deviated from one another in a circumferential direction. The second magnet pole units of the rotor parts are located at positions deviated from one another in the circumferential direction.
US10714991B2 Claw pole type motor
An automotive single-phase electrical motor of a claw pole type includes a rotating motor rotor which rotates around a rotating axis, a stator defined by a pair of annular stator bodies, and a stator coil arrangement which magnetizes the stator bodies. The stator bodies includes a first stator body having a radial arm and at least two magnetic claws, and a second stator body having a radial arm and at least two magnetic claws. The at least two magnetic claws of the first stator body mesh with the at least two magnetic claws of the second stator body so that the stator bodies mate with each other. The stator coil arrangement is provided as a satellite of the stator bodies. The radial arm of the first stator body and the radial arm of the second stator body are magnetically connected to each other at the stator coil arrangement.
US10714988B2 Permanent magnet design to enable higher magnetic flux density
A hybrid permanent magnet includes a first magnet (M1) having a first magnetic material and a second magnet (M2) having a second magnetic material different from the first magnetic material. The M2 magnet is deposited or assembled on a north pole surface and/or a south pole surface of the M1 magnet and the volume of the M2 magnet is less than or equal to the volume of the M1 magnet.
US10714983B2 Near-field microwave wireless power system
A wireless power system may use a wireless power transmitting device to transmit wireless power to a wireless power receiving device. The wireless power transmitting device may have microwave antennas that extend along an axis in a staggered arrangement. In the staggered arrangement, the microwave antennas are positioned on alternating sides of the axis. Each microwave antenna is elongated along a dimension that is perpendicular to the axis. Multiple antennas may overlap a wireless power receiving antenna in the wireless power receiving device. Control circuitry may use oscillator and amplifier circuitry to provide antennas that have been overlapped by the wireless power receiving antenna with drive signals. The drive signals may be adjusted based on feedback from the wireless power receiving device to enhance power transmission efficiency. The system may have a wireless power transmitting device with inductive wireless power transmitting coils.
US10714975B2 Dual band wireless power reception unit
A dual band wireless power reception unit is disclosed. The wireless power reception unit according to one embodiment comprises: a first resonator; a second resonator connected to the first resonator in parallel; a single rectifier having, as an input, a node in which outputs of the first resonator and the second resonator are connected to each other in parallel; at least one switch having a first output, a second output, and an input, wherein the second output is connected to the ground; at least one capacitor connected to the second resonator in parallel, and of which one terminal is connected to the first output of the switch and the other terminal is connected to the rectifier input; and a frequency sensor sensing an input frequency from the rectifier input, and of which an output is connected to the input of the switch.
US10714973B2 Uninterruptible power operating apparatus
An uninterruptible power operating apparatus includes an energy storage element, a charging circuit, a DC/DC converting circuit, a first DC/AC converting circuit, a driving circuit and a switching element. The DC/DC converting circuit is electrically connected with the energy storage element to convert its first DC energy to a second DC energy. The first DC/AC converting circuit is electrically connected with the DC/DC converting circuit. The driving circuit is electrically connected between an AC power source and a load. The switching element is electrically connected between the DC/DC converting circuit and the driving circuit. When the AC power source outputs power normally, the switching element is turned off, and the driving circuit receives energy from AC power source. When the power outputted from the AC power source is interrupted or abnormal, the switching element is turned on, and the driving circuit receives the second DC energy through the switching element.
US10714968B2 Power control apparatus, power control system, and power control method
A problem to be solved is to optimize a storage schedule in which changes in power (W) stored in an energy storage apparatus with time are determined, and an output upper limit (W) of a renewable energy power supply. In order to solve the problem, the invention provides a power control apparatus (10) that stores in an energy storage apparatus an amount of power exceeding an output upper limit instruction value (W), which is determined by an electricity company in power (W) generated by a power generation apparatus, the power control apparatus (10) including a decision unit (11) that decides a storage schedule in which changes in the power (W) to be stored in the energy storage apparatus with time within a predetermined period of time are determined, on the basis of prediction data on changes in the power (W) generated by the power generation apparatus with time within the predetermined period of time and values of various types of power classified on the basis of the output upper limit instruction value (W) within the predetermined period of time.
US10714966B2 Isolation switch operation
A vehicle includes a starter motor having a dedicated power source, an electric machine, and a controller configured to, responsive to a command for the motor to start an engine, open a switch to isolate the motor and source from a network electrically connected with the machine, and responsive to voltages on both sides of the switch falling within a predetermined range, close the switch to charge the source.
US10714964B2 Charging a battery of a computing device
A method of charging a battery of a computing device includes determining an amount of charge remaining in a battery coupled to the computing device. The method further includes, in response to a determination that the amount of charge remaining in the battery has decreased more than a first predetermined percentage since connection to a power source during a first predetermined amount of time, adjusting a power state of at least one power consuming circuit of the computing device other than the battery.
US10714963B2 Charging system, charging method, and device
Provided are a charging system, charging method, and device, said charging system comprising a battery; a first rectifier, configured to output a first voltage with a first pulsating waveform; a switch unit, configured to modulate the first voltage; a transformer, configured to output a second voltage with a second pulsating waveform; a second rectifier, configured to output a third voltage with a third pulsating waveform, and the third voltage is configured to be applied to the battery charge the battery; a first current sampling circuit, configured to sample current to obtain a current sampling value; and a control unit configured to output the control signal to the switch unit, adjust the amplification factor of the operational amplifier, and adjust a duty ratio of the control signal according to the current sampling value, such that the third voltage meets a charging requirement of the battery.
US10714961B2 Power supply apparatus, control apparatus, and control methods thereof
A power supply apparatus which can supply electrical power to a power reception apparatus in a non-contact manner, the power supply apparatus comprises a communication unit configured to be communicably connected to a control apparatus; a power supply unit configured to be able to output first electrical power to be supplied to a power source of the power reception apparatus and second electrical power that is smaller than the first electrical power, and is to be supplied to a communication unit of the power reception apparatus; and a control unit configured to control output of the second electrical power based on a control signal that has been received from the control apparatus, and is for performing control such that the second electrical power is not output from a plurality of power supply apparatuses at the same time.
US10714955B2 Methods and systems for automatic electric vehicle identification and charging via wireless charging pads
A cloud system is configured to execute method operations for communicating with connected vehicles of users having user accounts with the cloud system. One example method includes receiving a signal from of an electric vehicle that is associated to a user account. The signal of the electric vehicle is received in response to the electric vehicle parking over a charging pad of a charging unit, and the charging unit is one of a plurality of charging units located in various geo-locations. The method includes sending instructions to the charging unit to enable initiation of charge transfer to a battery of the electric vehicle upon the cloud system confirming that the user account for the electric vehicle is enabled for automatic charging upon parking over said charging pad of the charging unit. The method includes receiving data from the charging unit indicative of a discontinuing of the charge transfer by the charging pad responsive to detecting that the electric vehicle is no longer parked over said charging pad.
US10714948B2 Method and system for charging multi-cell lithium-based battery packs
A method and system for charging multi-cell lithium-based batteries. In some aspects, a battery charger includes a housing, at least one terminal to electrically connect to a battery pack supported by the housing, and a controller operable to provide a charging current to the battery pack through the at least one terminal. The battery pack includes a plurality of lithium-based battery cells, with each battery cell of the plurality of battery cells having an individual state of charge. The controller is operable to control the charging current being supplied to the battery pack at least in part based on the individual state of charge of at least one battery cell.
US10714945B2 Charge control circuit using battery voltage tracking, and a device having the same
A charge control circuit includes: a charge current control circuit configured to receive an input voltage at a first node, output a sensing current to a second node, and turn on a power transistor; a comparator configured to compare a voltage level of the second node with a voltage level of a third node, wherein the third node receives a charging current from the power transistor; a current mirror configured to generate a mirror current corresponding to the sensing current; and an amplifier configured to receive a first feedback voltage based on the mirror current, and amplify a difference between the first feedback voltage and a reference voltage to generate a switch control signal, wherein in response to the switch control signal and a plurality of control signals, the charge current control circuit is configured to decrease the sensing current and turn on the power transistor.
US10714944B2 Charger circuit and power conversion circuit thereof
A charging circuit includes a power conversion circuit, an inductor, and at least one conversion capacitor. The power conversion circuit includes a conversion switch circuit and a conversion control circuit. The conversion switch circuit includes an upper switch, a lower switch, and at least one auxiliary switch. In a switching conversion mode, the conversion control circuit operates the conversion switch circuit to switch the inductor to plural voltage levels repetitively for converting an input power to a charging power to charge a battery by switching power conversion. In a capacitive conversion mode, the conversion control circuit operates the conversion switch circuit to switch the conversion capacitor between two of voltage division nodes periodically for converting the input power to the charging power by capacitive power conversion.
US10714939B2 Longitudinal voltage source and direct current transmission system with a longitudinal voltage source
A longitudinal voltage source interconnects into a first line and a second line and feeds a longitudinal voltage into each of the two lines. The voltage source has first and second H-bridge circuits, each with four switches, and with outer terminals and center terminals. The center terminals are connectable to disconnected locations of the first and second lines. A capacitor has a first capacitor terminal connected to the two first output terminals of the two H-bridge circuits and a second capacitor terminal connected to the two second output terminals of the two H-bridge circuits. One or more switching modules are connected between the first capacitor terminal and the first output terminals of the first and second H-bridge circuits, and one or more switching modules are connected between the second capacitor terminal and the second output terminals of the first and second H-bridge circuits.
US10714934B2 Electrostatic discharge protection device, detection circuit and protection method thereof
An ESD protection device includes a detection circuit and a clamping circuit. The detection circuit is configured to output a first control signal and a second control signal according to a first voltage and a second voltage that is different from the first voltage, in which if an ESD event occurs, the detection circuit is configured to perform an inverse operation according to the second voltage, in order to generate the first control signal and the second control signal. The clamping circuit is configured to be turned on according to the first control signal and the second control signal, in order to provide a discharging path for a current associated with the ESD event.
US10714930B1 Digital electricity using carrier wave change detection
A power-distribution system can detect a transmission-line electrical fault, and the power source can be electrically isolated from the transmission line before a human or equipment is substantially harmed or damaged. A controller on the source side is responsive to one or more sensors that provide a signal indicative of the voltage across the transmitter side of the transmission line. A source-disconnect device operable by the controller electrically isolates the source from the transmission line. A signal-generator circuit is configured to superimpose a higher-wavelength carrier waveform with the source-output waveform on the transmission line. The controller determines the normal impedance of the transmission line from measurement and detects a transmission-line fault, as indicated by a change in carrier waveform reflections or energy content of the carrier waveform and generates a command to open the source-disconnect device upon detection of the fault.
US10714925B2 Self-powered electronic fuse with storage capacitor that charges with minimal disturbance of load current through the fuse
A two-terminal electronic fuse device involves two switches, four diodes, switch control circuitry, and a storage capacitor, connected in a particular topology. When AC current flows through the fuse, a charging current charges the storage capacitor. Energy stored in the storage capacitor is then used to power the switch control circuitry. If the voltage on the storage capacitor drops, then the switches are opened briefly and at the correct time. Opening the switches allows the charging current to flow. By opening the switches and charging the storage capacitor only at times of low current flow through the fuse, the disturbance of load current flowing through the fuse is minimized. If an overload current condition is detected, then the fuse has tripped and first and second switches are opened. If the capacitor does not need charging and there is no overload condition, then the switches remain closed.
US10714919B2 Wallbox installation tool
As described herein, a wall box installation tool may include a template body, one or more hollow pegs, a guide ring, and/or one or more template cards. The template cards may be configured to be installed on a front surface of the template body. A template card may define a plurality of holes therethrough. The guide ring may be configured to be installed within a pre-drilled hole in a wall. Each template card may be associated with a respective electrical device configuration. A subset of bores extending through the hollow pegs may be accessible via the template card when the template card is installed on the front surface of the template body. The wall box installation tool may include one or more fasteners that are configured to install a template card onto the front surface of the template body.
US10714918B2 Compact electrical junction box connector system
A junction box connector system includes conduit connectors with hollow bodies that secure to pieces conduit and to each other to from a connector cavity. The junction box connector system also includes an interconnect member with interconnect conductors and electrical contacts that fit within the connector cavity and provide electrical conductivity between the sets of wires from the pieces of conduit.
US10714917B2 Splice plate for connecting cable bus enclosures
A splice plate for adjustable angled connections between adjacent sections of cable bus enclosures having a first portion for adjustably connecting to a first siderail of a first cable bus enclosure, and a second portion for connecting to a second siderail of an adjacent second cable bus enclosure; at least one straight slot included in said first portion for receiving a connecting bolt to interconnect said first siderail and said plate, wherein a position of said connecting bolt within said straight slot is movable to allow changes of connection angle; at least one arc slot included in said first portion for receiving connecting bolts to interconnect said first siderail and said plate, wherein a position of said connecting bolts within said arc slot is movable to allow changes of connection angle in cooperation with said straight slot; whereby an angle of connection between said first and second cable bus enclosures is selectively adjustable by changing the position of said connecting bolts in said slots on said first portion of said plate.
US10714915B2 Vertical cable manager with slam-shut door
A vertical cable manager includes a base frame and a door. The base frame has upper and lower support legs and upper and lower crossbars between the support legs. The door has retractable hinge pins at corners of the door. The crossbars have hinge rod receptacles to receive respective hinge pins and elastic latch members having a flexible arm and a catch portion. The catch portions secure the hinge pins in the hinge rod receptacles with the door closed and are deflectable through elastic deformation of the flexible arm to allow travel of the hinge pins through the hinge rod receptacles and past the catch portions when the door is moved from an open to a closed position.
US10714914B2 Stripping apparatus and stripping station
A stripping apparatus and a stripping station capable of reducing cycle time for steps of stripping an insulation coating from a conducting wire material are provided. A stripping apparatus configured to strip an insulation coating WL from a conducting wire material W, including the insulation coating WL and cross-section of which orthogonal to a longitudinal direction has a rectangular shape, the stripping apparatus includes: an upper mold 150 provided with a stripping blade configured to strip the insulation coating WL; a lower mold 110 configured to support the conducting wire material W from a lower side thereof; a pressing member 130 configured to prevent displacement of the conducting wire material W; and a rotation mechanism configured to rotate the conducting wire material W around a rotational axis C1 that is parallel to a axial center of the conducting wire material W.
US10714912B2 Switch cabinet with a side panel, a related method and a related bay of switch cabinets
A switch cabinet which has a plurality of vertical frame profiles, whereby outer vertical planes (V) are defined, wherein at least one side panel of the switch cabinet is arranged in at least one of the vertical planes (V), characterized in that the side panel consists at least partially of a fabric with metallic or metallically coated threads or fibers. Furthermore, a related method and a related bay of cabinets are described.
US10714909B2 Expandable bused elbow for connecting modular metering equipment
An expandable bused elbow is provided for connecting modular metering equipment around an inside corner. The expandable bused elbow comprises an enclosure configured to fit in a gap between modular equipment. The enclosure has a box assembly with a sliding mechanism that enables expansion of the box assembly. The expandable bused elbow further comprises a first bussed interior assembly enclosed within the enclosure having a first bottom end and a second bussed interior assembly enclosed within the enclosure having a second bottom end. The first bussed interior assembly has a first bussing expansion mechanism that enables expansion of the first bussed interior assembly. The second bussed interior assembly has a second bussing expansion mechanism that enables expansion of the second bussed interior assembly. The expandable bused elbow further comprises a center corner assembly disposed in a middle space between the first bussed interior assembly and the second bussed interior assembly.
US10714905B2 Spark plug for internal combustion engine
A spark plug for an internal combustion engine includes a housing, an insulator, a center electrode, a ground electrode, and a plug cover. The housing has a cylindrical shape. The insulator is held on an inner side of the housing. The insulator has a cylindrical shape. The center electrode is held on an inner side of the insulator. The ground electrode forms a discharge gap with the center electrode. The plug cover, together with the housing, configures an auxiliary combustion chamber in which the discharge gap is arranged. The plug cover includes a spray hole that communicates between the inside and outside of the plug cover. The ground electrode is connected to a plurality of locations on an auxiliary-chamber inner wall surface that includes surfaces of the housing and the plug cover that are exposed to the auxiliary combustion chamber.
US10714903B2 Emitter array with variable spacing between adjacent emitters
In some implementations, a VCSEL array may include a plurality of VCSELs that each operates concurrently and emits light at a same wavelength. A first distance between a first pair of adjacent VCSELs, of the plurality of VCSELs, may be different from a second distance between a second pair of adjacent VCSELs of the plurality of VCSELs. The first pair of adjacent VCSELs may be located closer to a center of the VCSEL array than the second pair of adjacent VCSELs. At least one of temperature non-uniformity or optical power non-uniformity among the plurality of VCSELs may be reduced as compared to another VCSEL array, with a same physical footprint as the VCSEL array, comprising uniformly spaced VCSELs.
US10714900B2 Ex-situ conditioning of laser facets and passivated devices formed using the same
Edge-emitting laser diodes having mirror facets include passivation coatings that are conditioned using an ex-situ process to condition the insulating material used to form the passivation layer. An external energy source (laser, flash lamp, e-beam) is utilized to irradiate the material at a given dosage and for a period of time sufficient to condition the complete thickness of passivation layer. This ex-situ laser treatment is applied to the layers covering both facets of the laser diode (which may comprise both the passivation layers and the coating layers) to stabilize the entire facet overlay. Importantly, the ex-situ process can be performed while the devices are still in bar form.
US10714898B2 Semiconductor light emitting element
The present semiconductor light emitting element is a semiconductor light emitting element including an active layer, an upper cladding layer and a lower cladding layer that sandwich the active layer, and a phase modulation layer optically coupled to the active layer, in which the phase modulation layer includes a basic layer and a plurality of different refractive index regions that are different in refractive index from the basic layer, and the plurality of different refractive index regions are disposed so as to form a pattern in a region outside a light line on a reciprocal lattice space in the phase modulation layer.
US10714897B2 Distributed feedback semiconductor laser
A distributed feedback semiconductor laser of includes a semiconductor stacked body and a first electrode. The semiconductor stacked body includes a first layer, an active layer that is provided on the first layer and is configured to emit laser light by an intersubband optical transition, and a second layer that is provided on the active layer. The semiconductor stacked body has a first surface including a flat portion and a trench portion; the flat portion includes a front surface of the second layer; the trench portion reaches the first layer from the front surface; the flat portion includes a first region and a second region; the first region extends along a first straight line; the second region extends to be orthogonal to the first straight line; and the trench portion and the second region outside the first region form a diffraction grating having a prescribed pitch along the first straight line. The first electrode is provided in the first region.
US10714890B1 Transmitter optical subassembly arrangement with vertically-mounted monitor photodiodes
The present disclosure is generally directed to a multi-channel TOSA with vertically-mounted MPDs to reduce TOSA housing dimensions and improve RF driving signal quality. In more detail, a TOSA housing consistent with the present disclosure includes at least one vertical MPD mounting surface that extends substantially transverse relative to a LD mounting surface, with the result being that a MPD coupled to the vertical MPD mounting surface gets positioned above an associated LD coupled to the LD mounting surface. The vertically-mounted MPD thus makes regions adjacent an LD that would otherwise be utilized to mount an MPD available for patterning of conductive RF traces to provide an RF driving signal to the LD. The conductive RF traces may therefore extend below the vertically-mounted MPD to a location that is proximate the LD to allow for relatively short wire bonds therebetween.
US10714887B1 Compact laser cavity and methods of manufacture
Provided herein are systems and methods of manufacture and operation for a compact laser to achieve high-intensity output pulses. These compact laser resonators and methods rely upon separate and distinct functions of the laser resonator to be operated in balance such that the functions, while deleterious when separate are supportive of laser generation and growth when combined within a small volume laser resonator as described herein. The combined elements of the described laser resonator include a delicate balance that allows the laser to operate between plane-parallel operation and unstable operation. This operation mode further allows distinct methods of construction and operation that allow the compact laser to be reliably assembled and tested during assembly. Therefore, despite requiring a delicate balance of disparate elements, the described laser resonator results in a compact robust laser.
US10714885B2 Method of making a plurality of printed circuit boards from a single circuit board sheet
A solder paste is printed on a first surface of a sheet. Connectors are mounted on a first surface of a first board and a second surface of a second board. The sheet is inverted. A solder paste is printed on a second surface of the sheet. Connectors are mounted on a second surface of the first board and a first surface of the second board. The solder paste printed onto the second surface of the sheet is melted. The first board is separated from the second board. The first and second board have the same connector layout. A first connector soldered to the first surface of the first board and a second connector soldered to the second surface of the second board are disposed at a location where the sheet can be bent and broken along the separation line.
US10714883B2 Electrical line arrangement with flat conductor rail and tolerance compensation
An electrical line arrangement for a vehicle including a dimensionally stable flat conductor rail and a contact part housing fitted on the flat conductor rail such that it at least partially engages around the flat conductor rail. A contact part which makes contact with the flat conductor rail can be accommodated or is accommodated in the contact part housing. The line arrangement includes a mounting rail having a mounting flange for connection to the vehicle and a first connecting flange through which the contact part housing is held on the mounting rail in an interlocking manner in such a way that enables movement in a translatory manner along the mounting rail.
US10714882B2 Connector mateable with a mating connector and including a contact with a narrow portion to achieve a reduced contact width
A connector mateable with a mating connector includes at least one contact and a contact-holding member. The contact has resiliently deformable first and second support, first and second contact, and a coupling portions. The first and second contact portions, movable in an up-down direction perpendicular to a front-rear direction, are supported by the first and second support portions, respectively. The first support portion has first and second edges in a width direction perpendicular to the front-rear and up-down directions, the edges facing first and second orientations, respectively, which are opposite to each other of the width direction. The coupling portion couples the first and second support portions, and has upper main and bent portions. The upper main portion has upper front wide, fixed to the holding member to be immovable in the width direction, front narrow and base portions.
US10714881B2 Angled coaxial connectors for receiving electrical conductor pins having different sizes
An electrical connector for receiving a central conductor of a coaxial cable adapter includes first and second body portions, a first electrical contact, and a coupling element. The first body portion is configured to define a first bore extending in a first axial direction, and the second body portion is configured to define a second bore extending in a second axial direction, the second axial direction being angled relative to the first axial direction. The electrical contact is configured to be disposed in the first body portion, and the conductive coupling element in contact with the electrical contact. The second body portion is configured to receive a coaxial cable adapter, and the conductive coupling element is configured to receive a central conductor of the adapter, and the coupling element includes a wall having a first portion with a first inner diameter and a second portion with a second inner diameter, the second inner diameter being smaller that the first inner diameter. The conductive coupling element includes a plurality of spring fingers that, in a rest position, extend radially inward from the first portion of the coupling element to define an opening having a diameter that is smaller than the second inner diameter such that the coupling element is configured to receive the central conductor having a diameter equal to or less than the second diameter and provide an electrical connection between the electrical contact and the central conductor.
US10714880B1 Powered wall plate
A powered wall plate with at least two wall plate electrical current features behind the rear surface of the wall plate, each with a receiving prong, and a plug-in module with at least two electrical plugs and two arms, each arm with an electrical current transfer contact configured to removably mate with the receiving prong. A plurality of LED lights is located along a bottom edge of the front surface, a photocell is exposed on the front surface of the wall plate, and a control switch has an on position, an off position, and an auto position. A transformer housing may extend forward of the front surface and includes a circuit therein operatively coupled to a USB port on a perpendicular surface of the transformer housing. The USB port is configured to provide power when power is supplied to the at least two electrical plugs.
US10714876B2 Electrical connector having a middle shielding plate with engaging arms for locking to a terminal module unit
An electrical connector includes: a terminal module including a first unit having a first row of contacts, a second unit having a second row of contacts, and a shielding plate between the first and second units, each of the first and second units including a rear base and a front tongue, the rear base of the first unit being locked to the rear base of the second unit; and a shielding shell enclosing the terminal module, wherein the shielding plate has a pair of engaging arms, and the first unit has at a junction between the base and the tongue thereof two side portions locked to the pair of engaging arms.
US10714875B2 Electrical receptacle connector
An electrical receptacle connector includes an insulated housing in a metallic shell. First and second receptacle terminals are on the insulated housing. The receptacle terminals include first and second high-speed signal terminals. The metallic shell includes a receptacle cavity for receiving the insulated housing, an insertion opening being in communication with the receptacle cavity, pins at two sides of the metallic shell and outwardly extending, and an external protruding structure on a bottom surface for connecting to a circuit board. The external protruding structure forms an enclosed structure. Therefore, the seamless configuration improves the reduction to electromagnetic interference.
US10714873B2 Plug with protective conductor bridge
The disclosure relates to a plug (1) to be mechanically and electrically connected to a corresponding mating plug, comprising a housing (2), a protective conductor bridge (3), and a plug insert. The housing (2) comprises at least one connecting section (9) to be connected to the plug insert, and the plug insert is mounted on the at least one connecting section (9). The protective conductor bridge (3) can be inserted from above into the housing (2) or into retaining frame (4).
US10714872B2 Connector structure enabling replacement of a shield twisted pair cable and an unshield twisted pair cable without large structural change
A connector structure enables replacement of an STP cable (10B) and a UTP cable (10A) without a large structural change. UTP connection terminals (21A) connected to respective wires (11) of the UTP cable (10A) are accommodated in accommodating portions (26) of a UTP dielectric (22A) such that insertion areas (53) for male terminals (91) are close to each other in a width direction. STP connection terminals (21B) connected to respective wires (11) of the STP cable (10B) are accommodated in accommodating portions (26) of an STP dielectric (22B) such that insertion areas (53) for male terminals (91) are farther apart in the width direction than in the case of the UTP connection terminals (21A). The UTP connection terminals and the STP connection terminals that are accommodated in the accommodating portions (26) have protrusions (34) that are oriented in the same direction when.
US10714868B2 Waterproof connector for a board
It is aimed to suppress a projecting amount from a printed board. A male connector (M) is mounted on a printed board (P). A male connector housing (30) is formed with an inner receptacle (31) formed into a tubular shape open in one direction and fittable in a sealed state into a space between a terminal accommodating portion (4) and an outer tube portion (6) in a female connector (F) and an outer receptacle (33) formed into a tubular shape open in the same direction as the inner receptacle (31) while surrounding the inner receptacle (31), the outer tube portion (6) of the female connector (F) is fittable between the inner receptacle (31) and the outer receptacle (33), and the outer receptacle (33) is mountable on the printed board (P).
US10714867B2 Waterproof connector
A waterproof connector capable of maintaining high waterproof properties even under high water pressure is provided. The waterproof connector includes: a connector main body having connection terminals held by a housing; a casing having a connector accommodating portion in which the connector main body is accommodated; and a sealing material fixed to an outer peripheral portion of the housing and preventing water from entering between the housing and the casing. The sealing material includes a peripheral abutting portion configured to abut against an inner peripheral surface of the connector accommodating portion, and a rear abutting portion configured to abut against a rear wall portion of the connector accommodating portion, and the housing includes a sealing material supporting surface configured to support a rear surface portion of the rear abutting portion.
US10714866B2 Electrical connector assembly with protective guiding outer housing
An electrical connector assembly includes: an electrical connector including a terminal module, a shielding shell enclosing the terminal module, an insulative cover enclosing the shielding shell, and a sealing member disposed at a front portion of the insulative cover; and an outer housing accommodating the electrical connector, wherein the insulative cover has a plurality of humps engaging an inner surface of the outer housing, and the sealing member is compressed between the front portion of the insulative cover and the inner surface of the outer housing.
US10714865B2 Connector housing with a connecting mechanism to prevent electromagnetic leakage near the insertion port
A connector housing comprises a plurality of walls enclosing a receiving space and defining an insertion port. Each of a pair of adjacent walls of the plurality of walls has one of a pair of connecting mechanisms at adjacent edges of the pair of adjacent walls near the insertion port. The pair of connecting mechanisms are complementary to each other and the adjacent edges of the pair of adjacent walls are connected to each other by the connecting mechanisms.
US10714862B1 Electrical socket
The present disclosure discloses an electrical socket having a housing and at least two electrodes disposed in the housing. Each of the two electrodes is respectively provided with a through hole. An elastic buckle is disposed in the housing and comprises two elastic pieces disposed oppositely, wherein each of the two elastic pieces is respectively provided with a first peg corresponding to the through hole. A slider is provided in the housing, a part of the slider extends into the housing and between the two elastic pieces of the elastic buckle, and the slider is configured for pushing the two elastic pieces of the elastic buckle and driving the first peg to insert into the through hole for limiting pins, which is inserted in the electrodes.
US10714860B2 Joint connector
A joint connector includes shorting members (30), a housing body (HB) having a shorting member accommodating portion (50) for holding the shorting members (30), and a shorting member retainer (70). The shorting member (30) includes a base (32) extending in a shorting direction and shorting-side terminals (34, 36) projecting from this base (32) in a fitting direction. The shorting member retainer (70) is mounted into the housing body (HB) in a mounting/detaching direction intersecting both the shorting direction and the fitting direction. The shorting member retainer (70) includes shorting member constraining portions (74) configured to cross the shorting members (30) in the mounting/detaching direction to restrict movements of the shorting members (30) in the fitting direction.
US10714859B2 Receptacle electrical connector
A receptacle electrical connector includes a plurality of first terminals, a plurality of second terminals, a main insulator, a secondary insulator, a shielding plate and a shielding shell. The main insulator has a plurality of first terminal grooves and a plurality of second terminal grooves. Each first terminal accommodated in the corresponding first terminal groove is fitted with the corresponding first terminal groove in interference and in face-to-face contact. Each second terminal accommodated in the corresponding second terminal groove is fitted with the corresponding second terminal groove in interference and in face-to-face contact. The secondary insulator is engaged with the main insulator to limit each first terminal in the corresponding first terminal groove and to limit each second terminal in the corresponding second terminal groove. The shielding plate is located between the first terminals and the second terminals. The shielding shell surrounds the main insulator.
US10714858B2 Connector and electronic apparatus
A connector includes a casing configured to include a first contactor, a slider capable of insertion into the casing and configured to include a second contactor, an elastic body provided in the casing, the elastic body causing the slider to protrude from the casing, and a movable spherical body rotatably provided at a tip of the slider, wherein, when the slider is inserted into the casing, the first contactor comes in contact with the second contactor and the slider is moved in an intersecting direction that intersects an insertion direction of the slider.
US10714857B2 Connector with retention feature
A cable assembly and associated connector are provided. The cable assembly includes a connector and a length of cable for conducting an electrical current. The connector includes a connector body and a cap threadably engaging the connector body. The cap and connector body each include abutment surfaces arranged to interact with one another to provide a retention feature such that the cap is not inadvertently removed from the connector body.
US10714853B2 Semiconductor storage device
According to one embodiment, a semiconductor storage device includes a housing, a plurality of terminals, signal terminals, a controller, signal wiring, and a memory. The housing has a first face and a second face opposite to the first face. The plurality of terminals is exposed to the first face, extends in a first direction, and is spaced apart in a second direction intersecting with the first direction. A signal terminal included in the plurality of terminals has a first end in the first direction, and a second end opposite to the first end in the first direction, the second end being closer to a contact position with a socket contact than the first end. The controller is located in the housing. The signal wiring extends from the first end in the housing and electrically connects the first end and the controller. The memory is electrically connected to the controller in the housing.
US10714850B2 Electrical connector assembly
In accordance with one embodiment, first and second electrical connectors are configured as vertical electrical connectors that are configured to mate to each other so as to define a right angle electrical connector assembly. Ground shields and electrical contacts of various embodiments are also disclosed.
US10714843B2 Electric wire with terminal and method for manufacturing electric wire with terminal
A method for manufacturing an electric wire with a terminal includes forming a bonded part in which outer peripheral surfaces of strands are bonded to one another on an end portion of a core wire having the strands, in an electric wire in which the end portion is exposed from a covering; installing the bonded part onto a crimp terminal including a bottom part and a pair of caulking pieces extending from the bottom part and facing each other; crimping the caulking pieces to the bonded part, by sandwiching the crimp terminal and the electric wire between a first mold supporting the crimp terminal and a second mold moving relative to the first mold; and cutting a tip end portion projecting to outside from the caulking pieces in the bonded part by a cutting unit, while the caulking pieces are pressing the bonded part toward the bottom part.
US10714839B2 Active wideband antenna
A wideband active antenna system comprising an antenna having N outputs and a nominal bandwidth, each of the N outputs being directly coupled to an associated buffer amplifier, with a distance between the N outputs and a first active stage of each associated buffer amplifier preferably being maintained as short as reasonably possible and preferably no greater than ¼ wavelength of any transmission and/or receiving frequency of the wideband active antenna system and/or preferably no greater than 0.1 wavelength of any transmission and/or receiving frequency in an extension band of frequencies lower than a lowest frequency in the nominal bandwidth of the antenna.
US10714838B2 Array antenna apparatus and method of manufacturing the same
An array antenna apparatus includes: a wiring substrate having a plurality of fed patch antennas and a plurality of active element circuits electrically connected to the plurality of fed patch antennas, respectively; and a plurality of antenna substrates each having a parasitic patch antenna. The plurality of antenna substrates are joined onto one wiring substrate. Thereby, it becomes possible to provide an array antenna apparatus that can be reduced in size and has excellent antenna characteristics.
US10714830B2 Digital phase shifter switch and transmission line reduction
A digital phase shifter is described where each bit of the phase shifter has a circuit block including one PIN diode in parallel with one transmission line. The phase shifter requires only one PIN diode and one transmission line per bit circuit block. Each PIN diode behaves like a simple switch for phase shifting. When the PIN diode is forward biased (“on” state), current flows through the PIN diode and the RF signal is not phase shifted. When the pin diode is not forward biased (“off” state), current flows through the transmission line parallel to the PIN diode and the RF signal is phase shifted by the transmission line. The digital phase shifter may have n circuit blocks in series, and adjacent PIN diodes may share a current when both are on. The phase shifter may be implemented in a phased array or reflect array antenna including multiple phase shifters.
US10714828B2 Microwave analog cancellation for in-aperture simultaneous transmit and receive
A system for transmitting and receiving electromagnetic waves simultaneously. A portion of a signal to be transmitted through a transmitting antenna element is diverted from a transmit signal path, processed by an adjustable filter, and coupled into receive signal path. The adjustable filter is adjusted to approximate the channel that the leakage signals go through to get from the transmitter to the receiver so that the signal coupled into the receiving path through the filter partially cancels the parasitic leakage from the transmit signal path to the receive signal path.
US10714824B2 Planar surface wave launcher and methods for use therewith
In accordance with one or more embodiments, a planar surface wave launcher includes a substrate having a planar substrate surface. A planar antenna having first and second antenna elements on the planar substrate surface, the first and second antenna elements having edges on an aperture side of the planar surface wave launcher and opposing edges, is configured to transmit and receive first guided electromagnetic waves on a surface of a transmission medium. A conductive ground plane is provided on the planar substrate surface and coplanar to the planar antenna, the conductive ground plane having a mating edge with a shape conforming to the opposing edges of the first and second antenna elements, the mating edge electrically isolated from the opposing edges of the first and second antenna elements, wherein the transmission medium is spaced a distance apart from, and parallel to, the conductive ground plane.
US10714823B2 Low-profile, wideband, high gain spiral radiating element above an artificial magnetic conductor ground plane
Antenna structure with a curvilinear radiating element and a circularly symmetric high impedance surface ground plane. The curvilinear radiating element has a first diameter in a plane of the curvilinear radiating element and the circularly symmetric high impedance surface ground plane has a second diameter in a plane of the circularly symmetric high impedance surface ground plane. The curvilinear radiating element is positioned proximate the circularly symmetric high impedance surface ground plane with the plane of the curvilinear radiating element parallel to the plane of the circularly symmetric high impedance surface ground plane. A surface of the curvilinear radiating element is separated from a surface of the circularly symmetric high impedance surface ground plane by a distance.
US10714821B2 Antenna structure
An antenna structure includes a central grounding line and a spiral antenna. The central grounding line is linear and has two end portions provided with a grounding point and a first open point, respectively. The spiral antenna has two end portions provided with a feeding point and a second open point, respectively. The spiral antenna winds around the central grounding line while extending in the direction from the grounding point to the first open point, with the second open point positioned proximate to the first open point, wherein the spiral antenna and the central grounding line are spaced apart by an axial distance, thereby allowing the antenna structure to receive and transmit a radio frequency signal with circular polarization.
US10714819B2 AM/FM directional antenna array for vehicle
An antenna array for use in a passenger vehicle. Four of the roof support pillars are used as antenna elements. Each of the four pillars is electrically connected or coupled to one end of a corresponding meanderline component. The other end of each meanderline is in turn coupled to a radio receiver, typically through a combining network.
US10714816B2 Antenna mounting arrangement for a work vehicle
A work vehicle includes a roof panel forming a portion of a cab of the work vehicle. The work vehicle also includes a headliner disposed between the roof panel and an interior of the cab. In addition, the work vehicle includes a spatial locating antenna positioned between the roof panel and the headliner, such that a top side of the roof panel is positioned above the spatial locating antenna relative to a ground surface. Furthermore, the top side of the roof panel extends beyond a lateral extent and a longitudinal extent of the spatial locating antenna.
US10714813B2 Electronic device including cover having antenna module coupled thereto
An electronic device having a space formed between a front face and a rear face thereof is provided. The electronic device includes a first cover disposed on the front face, a second cover disposed on the rear face, a frame surrounding a periphery of the first cover and a periphery of the second cover, at least one antenna module coupled to a first face of the second cover, and a printed circuit board disposed in the space and having a front face electrically connected to the at least one antenna module.
US10714812B2 Multi-resonant antenna structure
The present disclosure generally relates to any device capable of wireless communication, such as a mobile telephone or wearable device, having one or more antennas. The antenna has a structure with multiple resonances to cover all commercial wireless communications bands from a single antenna with one feed connection to the main radio system. The antenna is usable where there are two highly efficient, closely spaced resonances in the lower part of the frequency band. One of those resonances can be adjusted in real time by using a variable reactance attached to the radiator while the other resonance is fixed.
US10714811B2 Antenna device
An antenna device, including a circuit board, electronic components, a functional component module, an antenna module and a feed line, is provided. The electronic components are disposed on the circuit board and include a microprocessor and a wireless communication chip. The functional component module includes a carrier and a metal member disposed on the carrier. The antenna module includes a feed point, a ground point and a radiator, the feed and ground points are disposed on the carrier and electrically connected to both sides of the metal member respectively, and the ground point is electrically connected to the ground layer of the circuit board. The radiator includes at least a part of the metal member, while the feed line can transmit a wireless signal to the feed point to feed into the radiator. Therefore, the metal member can serve as the radiator to conserve the space of accommodating another radiator.
US10714810B2 Antenna apparatus for use in wireless devices
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An antenna for decreasing a signal loss caused by a dielectric loss in an antenna by decreasing a space of the antenna in a wireless device and improving performance of the antenna is provided. The antenna includes a first radiator, and a second radiator installed on a cover of the wireless device to radiate a radio signal radiated by the first radiator, the second radiator separate from and facing the first radiator.
US10714808B2 Tilt adapter for diplexed antenna with semi-independent tilt
A tilt adapter configured to facilitate a desired tilt of a first radio frequency (RF) band and a second RF band of an antenna is disclosed. The antenna supports two or more frequency bands, in which the vertical tilt of each of the supported frequency bands is separately controlled by a coarse level of phase shifting, but commonly controlled by a fine level of phase shifting.
US10714804B2 Coaxial wiring device and transmission/reception integrated splitter
Conventional coaxial wiring devices present a problem in that the management of the manufacturing process therefor is difficult. A coaxial wiring device according to the present invention includes a first member, a second member, and a conductor plate. The first member (10) and the second member (30) include, when a line that connects a first port and a second port is denoted by a reference line, a first groove (11) that has a central point on the reference line and extends in a direction that intersects with the reference line; a second groove (12) that connects one end (FN1) of the first groove (11) and the first port; a third groove (13) that connects the other end (FN2) of the first groove (11) and the first port and has a shape that is line symmetrical to the second groove (12) with respect to the reference line; a fourth groove (14) that connects one end (FN1) of the first groove (11) and the second port; and a fifth groove (15) that connects the other end (FN2) of the first groove (11) and the second port and has a shape that is line symmetrical to the fourth groove (14) with respect to the reference line.
US10714803B2 Transmission medium and methods for use therewith
Aspects of the subject disclosure may include, for example, a cable can include a core, a plurality of strips of cladding disposed on the core, and a coupler that facilitates inducing electromagnetic waves that propagate along the core, where a first dielectric constant of the core exceeds a second dielectric constant of each strip of cladding of the plurality of strips of cladding, and where the electromagnetic waves propagate along the core without requiring an electrical return path. Other embodiments are disclosed.
US10714802B2 Transmission line device
A transmission line device includes: a plurality of electrically conductive members stacked with interspaces therebetween, the plurality of electrically conductive members including three or more electrically conductive members; and a plurality of artificial magnetic conductors each located between two adjacent electrically conductive members among the plurality of electrically conductive members. Among the plurality of electrically conductive members, at least one electrically conductive member located between two endmost electrically conductive members is shaped as a plate having at least one slit. At least a portion of the plurality of artificial magnetic conductors is located around the at least one slit to suppress leakage of an electromagnetic wave propagating along the at least one slit.
US10714801B2 Band-pass filtering structure and antenna housing
The present invention discloses a band-pass filtering structure and an antenna housing. The band-pass filtering structure includes a functional layer structure, where the functional layer structure includes two or more first dielectric layers and a second dielectric layer that is disposed between two first dielectric layers, a plurality of first conductive geometric structures displayed in a periodical arrangement are disposed on the first dielectric layer, a plurality of second conductive geometric structures displayed in a periodical arrangement are disposed on the second dielectric layer, the first conductive geometric structure includes two crossly-disposed conductive strips, and the second conductive geometric structure is a closed conductive geometric structure. The present invention resolves a technical problem that filtering performance of an existing band-pass filter is poor due to unreasonable structural design.
US10714797B2 Multilayer thermal laminate with aerogel for battery cell enclosures
A multilayer thermal laminate with aerogel is used for a battery cell enclosure to improve thermal properties and to reduce thermal inhomogeneity in the form of localized hotspots that exceed a desired rated temperature, thereby enabling a more compact design within rated thermal design limits for a given electrical performance.
US10714794B2 Lithium ion secondary battery and method of producing the lithium ion secondary battery
A lithium ion secondary battery includes a housing. An electrode group and an electrolytic solution are in the housing. The electrode group is immersed in the electrolytic solution. The electrode group includes a positive electrode including a positive electrode active material layer and a negative electrode including a negative electrode current collector and a negative electrode active material layer. The negative electrode active material layer is disposed on a surface of the negative electrode current collector. A metal piece is electrically connected to the negative electrode current collector. The metal piece is disposed at a position at which at least a part of the metal piece is immersed in the electrolytic solution. An oxidation-reduction potential of the metal piece is within an overdischarging voltage range and is lower than an oxidation-reduction potential of the negative electrode current collector.
US10714793B2 Rechargeable battery assembly and terminal device
The present disclosure provides a rechargeable battery assembly and a terminal device. The terminal device is equipped with a rechargeable battery assembly. The rechargeable battery assembly comprises a battery main body (110), at least one temperature measurement element (120), and a processor. The battery main body comprises a cell (112) and at least two battery tabs (114). A charging current from a charging device is transmitted to the cell through the battery tabs. One temperature measurement element is corresponding to one battery tab, and the temperature measurement element is used for detecting the temperature of the corresponding battery tab, and transmitting, to the processor (140), temperature information indicating the temperature of the corresponding battery tab. The processor is used for acquiring the temperature information from the temperature measurement element, and for determining the temperature of the cell according to the temperature information.
US10714792B1 Integrally-formed rechargeable battery and production method thereof
The present invention discloses an integrally-formed rechargeable battery and a production method thereof. The integrally-formed rechargeable battery includes an integrally-formed metal sleeve, which serves as a negative electrode conductor of the lithium battery. The integrally-formed metal sleeve is a cylindrical case, an end surface of one side of the integrally-formed metal sleeve is of a closed structure, and an end surface of the other side of the integrally-formed metal sleeve is an annular portion with a hole in the middle, A cell assembly is installed within the integrally-formed metal sleeve. The cell assembly includes a cell, a circuit board, an exposed charging interface and a positive electrode conductor. The positive electrode conductor is exposed from the hole in the middle of the annular portion.
US10714789B2 All-solid state battery
An all-solid state battery including at least one short-circuit current shunt part and a plurality of electric elements, the short-circuit current shunt part and the electric elements being stacked, wherein the shunt part includes a first and a second current collector layers, and an insulating layer between the first and second current collector layers, all being stacked, each of the electric elements includes a cathode current collector layer, a cathode material layer, a solid electrolyte layer, an anode material layer, and an anode current collector layer, all of these layers being stacked, the first current collector layer connected with the cathode current collector layer, the second current collector layer connected with the anode current collector layer, the electric elements are electrically connected with each other in parallel, and a plurality of sheets of metal foil, the one being arranged on a side wherein a nail penetrates in nail penetration testing.
US10714787B2 Lithium ion secondary battery
Provided is a lithium ion secondary battery including a power generating element that includes at least one positive electrode plate, at least one negative electrode plate, and at least one separator. A ratio B/A (mΩcm) of volume resistivity B (mΩcm3) of the power generating element to an area A (cm2) per one positive electrode plate is 0.4 or more and less than 0.9.
US10714781B2 Moving body
A moving body configured to reduce a damage on a mounting state of an intercooler even when traveling or similar situation is provided. The moving body includes an intercooler bracket that has a pair of arms extending from a stack frame. At distal end sides of the respective arms, an intercooler is mounted to the respective arms. At base end sides of the respective arms, the intercooler bracket is secured to the stack frame. A connecting portion that connects the pair of arms is integrally formed with the pair of arms.
US10714780B2 Separator having a plurality of riblet elements connected by a plurality of connecting bars, and fuel cell stack comprising the same
The present invention relates to a separator and a fuel cell stack comprising the same, and according to one aspect of the present invention, there is provided a separator comprising: a plurality of riblet elements arranged to be spaced apart at a predetermined interval; and a plurality of connecting bars connecting two adjacent riblet elements, wherein each of the riblet elements comprises a contact portion having a predetermined area, and a first partition wall and a second partition wall each extended from both sides of the contact portion, the space formed by the first partition wall, the contact portion and the second partition wall is opened along the connection direction of the connecting bar, and at least two riblet elements are provided such that each of the contact portions has a different area.
US10714779B2 Proton conducting electrolyte composition and method of preparation thereof
The present invention relates to an electrolyte composition and method of making thereof. The proton conducting electrolyte composition i.e. Sr1-xBaxCe0.5Zr0.35Y0.1Sm0.05O3-δ, comprises combination of doped BaCeO3 and BaZrO3 by their doping in Sr, Y, and Sm, wherein x=0 to 0.99, and δ=0 to 0.1. The proton conducting electrolyte is used as at least one component, among others, of Solid Oxide Fuel Cells such Solid Oxide Fuel Cell (SOFC) can easily be operated at intermediate temperature about 600° C. thereby making the SOFC cost effective and reliable and showing highest power density.
US10714778B2 Membrane-electrode assembly for fuel cells having improved durability and a polymer electrolyte membrane fuel cell including the same
Disclosed are a membrane-electrode assembly for fuel cells with improved durability and a polymer electrolyte membrane fuel cell including the same. The membrane-electrode assembly includes an antioxidant, Sm-doped cerium oxide in the electrolyte membrane, which has a controlled microstructure through high-temperature heat treatment, thereby providing both superior antioxidant activity and excellent long-term stability.
US10714776B2 Fuel cell system and control method for fuel cell system
A fuel cell system includes a battery, a fuel cell configured to generate power in accordance with a load, an inverter configured to convert power output from the fuel cell into alternating-current power and supply the alternating-current power to a motor, and a converter configured to control voltage between the inverter and the fuel cell using power output from the battery. The fuel cell system includes a voltage control unit configured to control the converter such that the voltage between the inverter and the fuel cell does not fall below a voltage lower limit of the inverter, and a lower limit voltage control unit configured to, when power required by the motor increases, cause the voltage between the inverter and the fuel cell to fall below the voltage lower limit of the inverter.
US10714772B2 Fuel cell system with improved leak detection
A fuel cell system comprises a fuel cell, a cooling system, a rotating speed acquisition part acquiring a rotating speed of the refrigerant pump, a power consumption acquisition part acquiring a power consumption of the refrigerant pump, and a controller configured to receive a rotating speed acquired by the rotating speed acquisition part and control the refrigerant pump. The controller has stored therein a predetermined correspondence between rotating speeds of the refrigerant pump and power consumption threshold values. The controller executes a refrigerant leak decision process for deciding presence or absence of a refrigerant leak while executing constant rotating speed control for the refrigerant pump, and in the refrigerant leak decision process, with reference to the correspondence by using a rotating speed value acquired by the rotating speed acquisition part, the controller determines a power consumption threshold value corresponding to the rotating speed value, and decides that a refrigerant leak has occurred if a power consumption value acquired by the power consumption acquisition part is equal to or lower than the power consumption threshold value corresponding to the rotating speed value.
US10714770B2 Fuel cell system
A fuel cell system comprises a fuel cell; a fuel cell controlling converter; an oxidizing gas supplier that is configured to supply an oxidizing gas to the fuel cell; and a controller that is configured to control a voltage and a current value of the fuel cell. In a first power generation state, the controller sets the voltage and the current value of the fuel cell according to a required output, based on a current-voltage characteristic of the fuel cell. In a second power generation state, the controller sets the voltage and the current value of the fuel cell according to the required output and a required amount of heat, to a voltage and a current value that provide a lower power generation efficiency than a power generation efficiency in the first power generation state. The controller reduces the required amount of heat in a process of changing over a power generation state from the second power generation state to the first power generation state. The controller reduces a decrement in the required amount of heat per unit time when the required output is equal to or higher than a reference value, compared with a decrement when the required output is lower than the reference value.
US10714768B2 Motor vehicle with a fuel cell
The fuel cell system of a motor vehicle has a fuel cell, comprising an anode side and a cathode side, a compressor, which is rotationally connected to a motor and connected by a feed line to the cathode side of the fuel cell, and a turbine, which is connected by an exhaust air line to the cathode side and which furthermore is rotationally connected only to a generator, which is connected at the output side to a second inverter and a low-voltage battery.
US10714767B2 Fuel cell air system safe operating region
Methods, systems, and device for controlling air flow within a vehicle for electrical generation. The air control system includes at least one of an air compressor, a back pressure valve or a bypass valve that controls air flow. The air control system includes one or more components. The air control system includes an electronic control unit. The electronic control unit is configured to obtain an air flow target and an air pressure ratio target and determine that the one or more components will operate outside a safe operating region. The electronic control unit is configured to determine a mediated air flow target and a mediated air pressure ratio target that causes the one or more components to operate within the safe operating region. The electronic control unit is configured to adjust the at least one of the air compressor, the back pressure valve or the bypass valve.
US10714764B2 Stainless steel sheet for fuel cell separators and method for producing the same
A stainless steel sheet for fuel cell separators including a substrate made of stainless steel sheet, and low-electrical-resistivity metal particles, where the substrate has a textured structure formed on a surface thereof with the average interval between the projected parts of the textured structure being 10 nm or more and 300 nm or less, the low-electrical-resistivity metal particles have an average particle size of 50 nm to 1.0 μm, the low-electrical-resistivity metal particles are attached to the surface of the substrate having the textured structure at a density of 1.0 particle or more for 1 μm2, and a ratio of the average particle size of the low-electrical-resistivity metal particles to the average interval between the projected parts is 1.0 to 15.0.
US10714761B2 Catalyst layer for fuel cell, and fuel cell
A fuel cell catalyst layer includes a plurality of carbon particles, a plurality of catalyst particles, and at least one plate-shaped carbon member disposed between the plurality of carbon particles. The plurality of catalyst particles are supported on surfaces of the plurality of carbon particles. The plate-shaped carbon member may be replaced with a rod-shaped carbon member.
US10714759B2 Current collector-catalyst monolithic three-dimensional nanofiber network for Li-air batteries and manufacturing method thereof
Disclosed is an electrode for lithium-air batteries without using a binder and a carbon additive and a method of manufacturing the same, and more specifically, provided is a nanofiber network-based current collector-catalyst monolithic porous air electrode which has an improved specific surface area and high air permeability as the energy density per weight is increased and the diameter, porosity, and thickness of the nanofibers are controlled by utilizing a significantly light polymer and carbon based material.
US10714755B2 Coating liquid for cathode active material, method for making the same, and method for coating cathode active material
The present disclosure relates to a method for making a cathode active material coating liquid including steps: forming a phosphate ester solution by adding a phosphate ester in an alcoholic solvent; and introducing an aluminum salt to the phosphate ester solution, the aluminum salt being soluble to the alcoholic solvent, and the aluminum salt reacting with the phosphate ester to form a homogeneous clear solution. The present disclosure also relates to a cathode active material coating liquid and a method for coating the cathode active material.
US10714751B2 Negative electrode for lithium ion secondary battery and lithium ion secondary battery
A negative electrode for a lithium ion secondary battery including a current collector and a negative electrode active material layer on the current collector, wherein the negative electrode active material layer includes: a first composite particle with a first graphite core particle and a first non-graphite-based carbon material coating a surface thereof; and a second composite particle with a second graphite core particle and a second non-graphite-based carbon material coating a surface thereof, and wherein an average particle diameter of the first composite particles is 5-30 μm; an average particle diameter of the second composite particles is 2-25 μm, and is smaller than the average particle diameter of the first composite particles; the mixing ratio of the first composite particle A and the second composite particle B is 50:50-95:5 in mass ratio; and a density of the negative electrode active material layer is 1.4-1.7 g/cm3.
US10714750B2 Porous carbon materials and production process thereof, and adsorbents, masks, adsorbing sheets and carriers
By a process for producing a porous carbon material from a plant-derived material as a raw material, said process including carbonizing the plant-derived material at 800° C. to 1,400° C. and then applying a treatment with an acid or alkali, a porous carbon material having a value of specific surface area of at least 10 m2/g as measured by the nitrogen BET method, a silicon content of at most 1 wt % and a pore volume of at least 0.1 cm3/g is obtainable from a plant-derived material, which has a silicon content of at least 10 wt %, as a raw material. Also provided is a process for producing a porous carbon material equipped with excellent functionality so that the porous carbon material can be used, for example, as an anode material for batteries, an adsorbent, masks, adsorbing sheets, or carriers.
US10714746B2 Conductive composition for electrode, electrode using same, and lithium ion secondary battery
A conductive composition for electrode is provided that is excellent in conductivity and dispersibility. Further, an electrode for lithium ion secondary battery with lower plate resistance and a lithium ion secondary battery excellent in rate characteristics are provided that use this conductive composition. A conductive composition for electrode, including: carbon nanofiber with a median diameter D50 value by volume from 0.1 to 8 pm; an active material; and a binder enables production of an electrode for lithium ion secondary battery with lower plate resistance and a lithium ion secondary battery excellent in rate characteristics.
US10714744B2 Composite carbon materials comprising lithium alloying electrochemical modifiers
The present application is generally directed to composites comprising a hard carbon material and an electrochemical modifier. The composite materials find utility in any number of electrical devices, for example, in lithium ion batteries. Methods for making the disclosed composite materials are also disclosed.
US10714740B2 Cathode active material for lithium secondary battery and lithium secondary battery comprising the same
The present invention relates to a cathode active material for lithium secondary battery and a lithium secondary battery including the same, and more specifically it relates to a cathode active material for lithium secondary battery in which the lithium ion diffusion path in the primary particles is formed to exhibit directivity in the center direction of the particles, and a lithium secondary battery including the same. The cathode active material for lithium secondary battery of the present invention has a lithium ion diffusion path exhibiting specific directivity in the primary particles and the secondary particles, and thus not only the conduction velocity of the lithium ion is fast and the lithium ion conductivity is high but also cycle characteristics are improved as the crystal structure hardly collapses despite repeated charging and discharging.
US10714739B2 Lead storage battery
Disclosed is a lead-acid battery including: a battery container; an electrolyte and an electrode plate group in the battery container; and a battery container cover that hermetically seals an opening of the battery container, wherein the electrode plate group includes a positive electrode plate including a positive electrode active material, a negative electrode plate including a negative electrode active material, and a separator interposed between the positive electrode plate and the negative electrode plate, the battery container cover is provided with a liquid port, a liquid port plug that closes the liquid port, and a sleeve that hangs down from the liquid port to a prescribed liquid surface height of the electrolyte, a sodium ion concentration contained in the electrolyte is 1 mmol/L to 90 mmol/L, and a specific surface area of the positive electrode active material is 5 m2/g to 9 m2/g.
US10714738B2 Manufacturing method for selenium preloaded mesoporous carbon cathode for alkali metal-selenium secondary battery
A method of producing a pre-selenized (selenium-preloaded) active cathode layer for a rechargeable alkali metal-selenium cell; the method comprising: (a) preparing an integral layer of mesoporous structure having pore sizes from 0.5 nm to 50 nm (preferably from 0.5 nm to 5 nm) and a specific surface area from 100 to 3,200 m2/g; (b) preparing an electrolyte comprising a solvent and a selenium source; (c) preparing an anode; and (d) bringing the integral layer and the anode in ionic contact with the electrolyte and imposing an electric current between the anode and the integral layer (serving as a cathode) to electrochemically deposit nanoscaled selenium particles or coating on the graphene surfaces. The selenium particles or coating have a thickness or diameter smaller than 20 nm (preferably <10 nm, more preferably <5 nm or even <3 nm) and preferably occupy a weight fraction of at least 70% (preferably >90% or even >95%).
US10714737B2 Anode layer and all solid lithium battery
A main object of the present disclosure is to provide an all solid lithium battery with excellent capacity durability. The above object is achieved by providing an anode layer to be used in an all solid lithium battery, the anode layer comprising: a metal particle capable of being alloyed with Li, as an active material; and the metal particle has two kinds or more of crystal orientation in one particle.
US10714734B2 Cap for battery terminal
Disclosed is a non-lead conductive cap for a battery terminal and battery. The battery may comprise a battery housing and a positive and negative terminal, the positive and negative terminal being accessible through the battery housing; wherein the positive and negative terminal further comprise an electrically conductive cap mounted on both the positive and negative terminal, wherein the electrically conductive cap does not comprise lead.
US10714731B2 Connection module
A connection module is a flat-shaped connection module that is to be attached to a power storage element group formed by aligning a plurality of power storage elements with positive and negative electrode terminals and includes a first bus bar module, a second bus bar module, and insulating fixing members. The first and second bus bar modules include sheet members that hold the plurality of bus bars arranged in an alignment direction of the power storage elements. The fixing members are coupled to the sheet members to integrate and fix the first bus bar module and the second bus bar module.
US10714730B2 Welding process for a battery module
A battery module is disclosed that includes a stack of battery cells, where each battery cell has a terminal, and the terminal has a first alloy of a metal. The battery module has a bus bar that includes a body having a second alloy of the metal, nickel plating on at least a portion of the body, and an indentation disposed on the body, where a thickness of the nickel plating is between 0.2% and 20% of an overall thickness of the body, and a weld physically and electrically coupling the respective terminal to the bus bar. The indentation has a depth between 10% and 90% of the overall thickness, an area of the indentation is between 5% and 20% of an overall area of the body, and the nickel plating enables the weld to be stronger than a weld between the first and second alloys.
US10714727B2 Lithium-sulfur battery
A lithium-sulfur battery includes a cathode, an anode, a lithium-sulfur battery separator and an electrolyte. The lithium-sulfur battery separator includes a pristine separator (PSL) and a functional layer (FL). The FL is located on a surface of the PSL. The FL includes a plurality of carbon nanotubes and a plurality of MoP2 nanoparticles uniformly mixed with each other.
US10714726B2 Lithium-sulfur battery separator
A lithium-sulfur battery separator includes a pristine separator (PSL) and a functional layer (FL). The FL is located on a surface of the PSL. The FL includes a plurality of carbon nanotubes and a plurality of MoP2 nanoparticles uniformly mixed with each other.
US10714725B2 Separator for nonaqueous electrolyte secondary battery
Provided is a separator that is used in a nonaqueous electrolyte secondary battery, and that exhibits high impregnation ability with respect to a nonaqueous electrolyte solution. The separator for a nonaqueous electrolyte secondary battery disclosed herein is provided with: a porous substrate; a first coat layer formed on a pair of main surfaces and on an inner surface of the porous substrate; and a second coat layer formed on the first coat layer, at least on one main surface of the porous substrate. The first coat layer has higher hydrophilicity than the porous substrate. The second coat layer has higher hydrophobicity than the porous substrate. The hydrophilicity of an inner surface of the separator for a nonaqueous electrolyte secondary battery is higher than the hydrophilicity of the second coat layer, in a central region of the separator for a nonaqueous electrolyte secondary battery in the thickness direction thereof.
US10714720B2 Vent housing for advanced batteries
A system includes a vent housing configured to be installed on a lower housing of a battery module at a first side of the vent housing. The vent housing has a main body having an opening on a second side of the vent housing and an internal chamber coupled to the opening. The internal chamber includes a first wall having an internal burst vent configured to open at a first pressure threshold and a second wall having a ventilation vent comprising a gas-selective permeability layer.
US10714714B2 Electrical energy store, specifically a battery cell, with spatially-optimized electrode interconnection
An electrical energy store having a spatially-optimized electrode interconnection. The electrical energy store (1) comprises flat electrodes (3), flags (7) projecting laterally from the electrodes (3), and external terminals (9). A plurality of electrode regions are respectively stacked, one on top of another, to form an electrode stack (14). A plurality of flags (7) are arranged one on top of another in a flag stack (15), and are respectively materially bonded, both mutually and with an associated external terminal (9). The energy store is characterized in that each flag (7) of a plurality of flags (7) in a flag stack (15), which is bonded to the associated external terminal (9), is materially bonded to a respectively adjoining flag (7) in a region in which the flag (7) is oriented in an inclined direction at an angle (α) to the surface (11) of the associated external terminal (9).
US10714713B2 Clamping device for battery cells as well as battery module, battery, battery system, vehicle and method for producing a battery module
The present invention relates to a clamping device (300) for battery cells (100), characterized by: a container that comprises a space (310) with a variable volume for receiving a fluid, the container being designed such that a battery cell (100) or a plurality of battery cells (100) can be clamped. The invention also relates to a battery module, a battery, a battery system, a vehicle and a method for producing a battery module (20; 30; 40; 50; 60).
US10714708B2 Display and method of manufacturing the same
An organic light-emitting display apparatus and a method of manufacturing the same are provided. An organic light-emitting display apparatus includes: a substrate including an emission region and a non-emission region surrounding the emission region; a display device in the emission region of the substrate; an insulating layer in the non-emission region and including a hole having a lower portion having a first width and an upper portion having a second width less than the first width; and an encapsulation member covering the display device and the insulating layer and filling an inside of the hole.
US10714707B2 Organic light-emitting display apparatus and fabrication method thereof
An organic light-emitting display apparatus includes a display substrate and a thin film encapsulation layer on the display substrate. The display substrate includes at least one hole, a thin film transistor, a light-emitting portion electrically connected to the thin film transistor, and a plurality of insulating layers. The light-emitting portion includes a first electrode, an intermediate layer, and a second electrode. The display substrate includes an active area, an inactive area between the active area and the hole, and a plurality of insulating dams. Each insulating dam includes at least one layer. The inactive area includes a first area different from a laser-etched area and a second laser-etched area.
US10714704B2 Foldable display device and method of manufacturing the same
Discussed is a foldable device including a first flexible substrate, a touch unit under the first flexible substrate, a second flexible substrate facing the first flexible substrate, a light-emitting element unit on the second flexible substrate, and an adhesive layer for attaching the first flexible substrate and the second flexible substrate together. The touch unit includes a first touch wiring layer under the first flexible substrate, a first insulating layer covering the first touch wiring layer and the first flexible substrate, a second touch wiring layer under the first insulating layer, and a second insulating layer covering the second touch wiring layer and the first insulating layer. The second insulating layer includes an opening for exposing a part of an edge of the first insulating layer to the adhesive layer.
US10714703B2 Organic light emitting diode display device
An organic light emitting diode (OLED) display includes: a substrate including a plurality of organic light emitting elements; an adhesive member on at least a portion of an upper surface of the substrate; a flexible circuit board adhered to the upper surface of the adhesive member and having a portion bent to be mounted to a lower surface of the substrate; and a light blocking member at the upper surface of the substrate, wherein the light blocking member is laterally offset from the adhesive member.
US10714702B2 Organic light emitting diode having connecting layer including material corresponding to carriers in carrier transport layer
The present disclosure provides an organic light emitting diode (OLED) and a manufacturing method of the same, and a display device. The OLED comprises a first portion and a second portion which are manufactured by different processes and sequentially stacked, wherein the first portion comprises a first carrier transport layer, a first light emitting layer, and a connecting layer between the first light emitting layer and the second portion, which are sequentially stacked, the second portion comprises a second carrier transport layer, the first light emitting layer comprises an N-type base material and a P-type base material, and the connecting layer comprises a material corresponding to carriers in the first carrier transport layer. The OLED provided by the present disclosure can not only make light emission stable, maintain a good efficiency of light emission, but obtain light with an ideal color and prevent a phenomenon of “unexpected emission of light”.
US10714697B1 Perovskite nanocrystal deposits
A method for making a nanostructure includes preparing a perovskite precursor in a solvent where the perovskite concentration ranges from about 0.5M to about 1.5M. A substrate is coated in the perovskite precursor, and the perovskite precursor is annealed onto the substrate, thereby forming the nanostructure including the substrate with perovskite nanocrystal deposits.
US10714682B2 Ruthenium removal composition and method of producing magnetoresistive random access memory
An object is to provide a ruthenium removal composition capable of dissolving Ru while suppressing dissolution of CoFeB, and a method of producing a magnetoresistive random access memory (MRAM) using the same. A ruthenium removal composition of the present invention contains orthoperiodic acid and water, and the pH is 11 or more. It is preferable that the content of orthoperiodic acid in the ruthenium removal composition is 0.01% to 5% by mass with respect to the total mass of the composition.
US10714679B2 CMP stop layer and sacrifice layer for high yield small size MRAM devices
An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.
US10714672B2 Vertical transmon qubit device
Techniques for a vertical transmon qubit device are provided. In one embodiment, a chip surface base device structure is provided that comprises a first superconducting material physically coupled to a crystalline substrate, wherein the crystalline substrate is physically coupled to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystalline substrate. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.
US10714656B2 Light-emitting device
The present disclosure provides a method for making a light-emitting device. The method includes steps of providing a first substrate; forming a first semiconductor layer on the first substrate; providing a second substrate; forming an intermediate layer on the second substrate, wherein a refractive index of the intermediate layer is between a refractive index of the second substrate and a refractive index of the first semiconductor layer; and bonding the first semiconductor layer and the intermediate layer.
US10714654B2 Solar cell and method for manufacturing the same
A solar cell includes a semiconductor substrate containing impurities of a first conductive type; a tunnel layer positioned on the semiconductor substrate; an emitter region positioned on the tunnel layer and containing impurities of a second conductive type opposite the first conductive type; a dopant layer positioned on the emitter region and formed of a dielectric material containing impurities of the second conductive type; a first electrode connected to the semiconductor substrate; and a second electrode configured to pass through the dopant layer, and connected to the emitter region.
US10714653B2 Compound semiconductor solar cell and method of manufacturing the same
Disclosed is a method of manufacturing a compound semiconductor solar cell according to an embodiment of the invention. The method of manufacturing the compound semiconductor solar cell according to the embodiment of the invention includes forming a plurality of compound semiconductor layers of at least two elements and including a base layer and an emitter layer, the base layer including a first conductivity type dopant to have a first conductivity type and the emitter layer including a second conductivity type dopant to have a second conductivity type. The forming of the plurality of compound semiconductor layers includes at least one of a process-temperature change period and a growth-rate change period.
US10714646B2 Photoelectric conversion material containing organic semiconductor material, and photoelectric conversion element
A photoelectric conversion material includes a compound represented by Formula (1): where, X is selected from the group consisting of a hydrogen atom, a deuterium atom, a halogen atom, an alkyl group, and a cyano group; and Y represents a monovalent substituent represented by Formula (2): where, R1 to R10 each independently represent a hydrogen atom, a deuterium atom, a halogen atom, an alkyl group, or an aryl group; or two or more of R1 to R10 bond to each other to form one or more rings, and the remainders each independently represent a hydrogen atom, a deuterium atom, a halogen atom, an alkyl group, or an aryl group; * denotes the binding site of Y in Formula (1); and Ar1 is selected from the group consisting of structures represented by Formulae (3): where ** denotes a binding site of Ar1 with N in Formula (2).
US10714644B2 Voltage matched multijunction solar cell
A voltage matched multijunction solar cell having first and second solar cell stacks that are electrically connected parallel to each other. The first solar cell stack is optimized for absorption of incoming solar light in a first wavelength range and the second solar cell stack is optimized for absorption of incoming solar light in a second wavelength range, wherein the first and the second wavelength range do not or at most only partially overlap each other.
US10714637B2 DC power conversion circuit
The inventive technology, in certain embodiments, may be generally described as a solar power generation system with a converter, which may potentially include two or more sub-converters, established intermediately of one or more strings of solar panels. Particular embodiments may involve sweet spot operation in order to achieve improvements in efficiency, and bucking of open circuit voltages by the converter in order that more panels may be placed on an individual string or substring, reducing the number of strings required for a given design, and achieving overall system and array manufacture savings.
US10714635B2 Fast recovery inverse diode
An inverse diode die has a high reverse breakdown voltage, a short reverse recovery time Trr, and is rugged in terms of reverse breakdown voltage stability over long term use in hard commutation applications. The die has an unusually lightly doped bottomside P type anode region and also has an N− type drift region above it. Both regions are of bulk wafer material. An N+ type contact region extends down into the drift region. A topside metal electrode is on the contact region. A P type silicon peripheral sidewall region laterally rings around the drift region. A topside passivation layer rings around the topside electrode. A bottomside metal electrode is on the bottom of the die. The die has a deep layer of hydrogen ions that extends through the N− drift region. The die also has a shallow layer of ions. Both ion layers are implanted from the bottomside.
US10714634B2 Non-volatile split gate memory cells with integrated high K metal control gates and method of making same
A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.
US10714631B2 Semiconductor structure and methods for crystallizing metal oxide semiconductor layer
The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.
US10714629B2 Transistor, semiconductor memory device, and method of manufacturing transistor
According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.
US10714627B2 Bottom gate type thin film transistor, method of manufacturing the same, and display apparatus
Provided is a bottom gate type thin film transistor including on a substrate (1) a gate electrode (2), a first insulating film (3) as a gate insulating film, an oxide semiconductor layer (4) as a channel layer, a second insulating film (5) as a protective layer, a source electrode (6), and a drain electrode (7), in which the oxide semiconductor layer (4) includes an oxide including at least one selected from the group consisting of In, Zn, and Sn, and the second insulating film (5) includes an amorphous oxide insulator formed so as to be in contact with the oxide semiconductor layer (4) and contains therein 3.8×1019 molecules/cm3 or more of a desorbed gas observed as oxygen by temperature programmed desorption mass spectrometry.
US10714623B2 Approach for an area-efficient and scalable CMOS performance based on advanced silicon-on-insulator (SOI), silicon-on-sapphire (SOS) and silicon-on-nothing (SON) technologies
Device architectures for a Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor (SOI-MOSFET) were defined. They incorporated configurations of Body-Tied-Source that drastically increased the conductance that an Impact-Ionizations current sees from the body of an SOI-MOSFET. This consequently permitted the SOI-MOSFET to effectively operate at far higher operating biases.
US10714622B2 Liquid crystal display device and electronic device including the same
A liquid crystal display device is provided in which the aperture ratio can be increased in a pixel including a thin film transistor in which an oxide semiconductor is used. In the liquid crystal display device, the thin film transistor including a gate electrode, a gate insulating layer and an oxide semiconductor layer which are provided so as to overlap with the gate electrode, and a source electrode and a drain electrode which overlap part of the oxide semiconductor layer is provided between a signal line and a pixel electrode which are provided in a pixel portion. The off-current of the thin film transistor is 1×10−13 A or less. A potential can be held only by a liquid crystal capacitor, without a capacitor which is parallel to a liquid crystal element, and a capacitor connected to the pixel electrode is not formed in the pixel portion.
US10714619B2 PMOS FinFET
A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.
US10714618B2 Finfet with various shaped source/drain regions
A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern.
US10714611B2 Silicon carbide semiconductor device
A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.
US10714603B2 Semiconductor device
A semiconductor device is provided that includes: an edge termination portion provided in the peripheral portion of a semiconductor substrate; and an active portion surrounded by the edge termination portion, wherein the active portion includes: a plurality of gate trench portions arrayed along a predetermined array direction; a plurality of dummy trench portions provided between a gate trench portion closest to the edge termination portion among the plurality of gate trench portions and the edge termination portion; mesa regions located between each of the plurality of dummy trench portions; and accumulation regions with a first conductivity-type provided in at least a part of the mesa regions.
US10714599B2 Semiconductor device and method for fabricating the same
A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure.
US10714591B2 Gate structure for a transistor device with a novel pillar structure positioned thereabove
One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.
US10714589B2 Method for producing a transistor
A method produces a transistor, in particular a gallium nitride transistor based on high electron mobility. After a structured metal layer has been formed in a first gate region by a temporarily formed structured first photoresist layer, an intermediate layer has been deposited and a second insulation layer has been deposited, a second photoresist layer is structured in order to expose a second gate region, wherein subsequently a first field plate and a second field plate are formed as buried field plates on respective sides of the second gate region.
US10714588B2 Metal gate process for FinFET device improvement
In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.
US10714576B2 Semiconductor device and method for manufacturing the same
A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.
US10714575B2 Semiconductor device having interfacial layer and high K dielectric layer
A transistor includes a channel region, a gate stack, and source and drain structures. The channel region comprises silicon germanium and has a first silicon-to-germanium ratio. The gate stack is over the channel region and comprises a silicon germanium oxide layer over the channel region, a high-κ dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-κ dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio. The second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio. The channel region is between the source and drain structures.
US10714574B2 Shielded trench devices
A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region that contacts a shield region in an epitaxial or crystalline layer of the device.
US10714561B2 Display device
A display device, includes a substrate; first to fourth subpixels sequentially arranged on the substrate; a first power line on a left side of the first subpixel and shared by the first and second subpixels; a sensing line between the second subpixel and the third subpixel and shared by the first to fourth subpixels; a second power line on a right side of the fourth subpixel and shared by the third and fourth subpixels; and a first data line on the left side of the first subpixel, a second data line on a right side of the second subpixel, a third data line on a left side of the third subpixel, and a fourth data line on the right side of the fourth subpixel. The first and second power lines and the sensing line are disposed on a layer different from the first to fourth data lines.
US10714559B2 Organic light emitting diode, method of manufacturing the same, and organic light emitting display including the same
According to an exemplary embodiment of the present disclosure, an organic light emitting element includes: a first electrode; a second electrode overlapping the first electrode; and an emission layer disposed between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a metal layer including a first material, an oxidation layer including a second material and disposed on two opposing surfaces of the metal layer, and a barrier layer disposed at a surface of the oxidation layer, and the second material has a smaller Gibbs free energy than that of the first material.
US10714556B2 Transistor substrate and display device including the same
A transistor substrate may include a base substrate, and a switching transistor and a driving transistor provided on the base substrate. The driving transistor includes: an active pattern provided on the base substrate and including a source region, a drain region spaced apart from the source region, and a channel region provided between the source region and the drain region; a gate electrode at least partially overlapping the active pattern; a gate insulating film provided between the active pattern and the gate electrode; a source electrode insulated from the gate electrode and connected to the source region; a drain electrode insulated from the gate electrode and connected to the drain region; and at least one dummy hole adjacent to the channel region.
US10714555B2 Light emitting device and electronic equipment including a light reflection layer, an insulation layer, and a plurality of pixel electrodes
A light emitting device includes a transistor, a light reflection layer, a first insulation layer that includes a first layer thickness part, a second layer thickness part, and a third layer thickness part, a pixel electrode that is provided on the first insulation layer, a second insulation layer that covers a peripheral section of the pixel electrode, a light emission functional layer, a facing electrode, and a conductive layer that is provided on the first layer thickness part. The pixel electrode includes a first pixel electrode which is provided in the first layer thickness part, a second pixel electrode which is provided in the second layer thickness part, and a third pixel electrode which is provided in the third layer thickness part. The first pixel electrode, the second pixel electrode, and the third pixel electrode are connected to the transistor through the conductive layer.
US10714554B2 Electroluminescent display device integrated with image sensor
Disclosed is an electroluminescent display device integrated with image sensors, including: a display panel having a plurality of pixels; a display panel driving circuit configured to write data of an input image into the pixels during a display mode so as to display the input image with the pixels; and a sensor processing circuit configured to apply a reverse bias to Organic Light Emitting Diodes (OLEDs) disposed in at least some of the pixels during a sensor mode so as to process sensor signals received from the pixels.
US10714551B2 Flexible organic light-emitting display device and method of manufacturing the same
Provided are a flexible organic light-emitting display device and a method of manufacturing the same. The flexible organic light-emitting display device includes a metal oxide infiltrated layer as part of at least one of a plurality of organic layers stacked on and around an organic light-emitting device.
US10714550B2 Organic light-emitting display apparatus having protected emission layer
An organic light-emitting display apparatus prevents the quality of an image being displayed thereon from being deteriorated as a result of contamination of an organic emission layer. The display apparatus includes a substrate with a display area and a periphery area. A first insulating layer, disposed over the substrate, has a first opening in the periphery area. A first electrode is disposed within the display area, over the first insulating layer. A first bank is disposed over the first insulating layer and has a second opening through which a center of the first electrode is exposed. A second bank is disposed over the first insulating layer and is separated from the first bank. The first opening is disposed between the first bank and the second bank. An intermediate layer is disposed over the first electrode. A second electrode is disposed over the intermediate layer and the first bank.
US10714543B2 Optical fingerprint identification device and display panel
Disclosed are an optical fingerprint identification device and a display panel including the same. The optical fingerprint identification device includes a light emitting structure and a photosensitive sensor. The light emitting structure includes a transparent first electrode, an opaque second electrode, an electroluminescent layer between the first electrode and the second electrode, and a through hole penetrating the first electrode, the electroluminescent layer and the second electrode. The photosensitive sensor is disposed on a side of the second electrode facing away from the electroluminescent layer, and is configured to receive light rays transmitted through the through hole and acquire fingerprint information according to the received light rays.
US10714541B2 Electro-optical device, manufacturing method of electro-optical device, and electronic apparatus
An electro-optical device includes a first substrate including a plurality of light-emitting elements and a color filter provided corresponding to the plurality of light-emitting elements and a second substrate being a light-transmissive substrate and disposed facing the first substrate with an adhesive provided between the first substrate and the second substrate. An adhesive surface of the color filter of the first substrate is provided with protrusions and recesses in a stripe pattern.
US10714536B2 Method to form memory cells separated by a void-free dielectric structure
Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
US10714533B2 Substrate free LED package
A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies.
US10714531B2 Infrared detector devices and focal plane arrays having a transparent common ground structure and methods of fabricating the same
Focal plane arrays and infrared detector device having a transparent common ground structure and methods of their fabrication are disclosed. In one embodiment, a front-side illuminated infrared detector device includes a contact layer and a detector structure adjacent to the contact layer. The detector structure is capable of absorbing radiation. The front-side illuminated infrared detector device further includes a common ground structure adjacent the detector structure, wherein the common ground structure is transmissive to radiation having a wavelength in a predetermined spectral band, and the common ground structure has a bandgap that is wider than a bandgap of the detector structure. The front-side illuminated infrared detector device further includes an optical layer adjacent the common ground structure.
US10714527B2 Photoelectric conversion apparatus, sensor unit, and image forming apparatus
A photoelectric conversion apparatus is provided. The apparatus comprises a substrate including two light receiving regions in which light receiving devices are arranged; electrode pads arranged on the substrate; and a readout circuit arranged on the substrate and configured to read out signals from the light receiving regions. The electrode pads include an output pad for outputting a signal, and a power supply pad for supplying power to the light receiving regions or the readout circuit. Each of the light receiving regions has a shape in which a first direction is taken as a longitudinal direction, the light receiving regions are arranged along a second direction with an interval therebetween, the second direction intersecting the first direction, and one or more pads of the electrode pads is sandwiched by the light receiving regions in the second direction.
US10714526B2 Solid-state imaging device, manufacturing method thereof, and electronic apparatus
Disclosed is a solid-state imaging device including: a solid-state imaging element which outputs an image signal according to an amount of light sensed on a light sensing surface; a semiconductor element which performs signal processing with respect to the image signal output from the solid-state imaging element; and a substrate which is electrically connected to the solid-state imaging element and the semiconductor element, in which the semiconductor element is sealed by a molding resin in a state of being accommodated in an accommodation area which is provided on the substrate, and in which the solid-state imaging element is layered on the semiconductor element via the molding resin.
US10714520B1 Manufacturing an on-chip microlens array
A method for monolithically fabricating a light field sensor with an array of microlens. Each microlens is formed directly on a surface including a plurality of pixels of the light field sensor formed on a wafer. The manufacturing system performs a preparation of the surface including the plurality of pixels formed on the wafer. The manufacturing system deposits a layer of photoresist on the surface of the wafer. The manufacturing system performs a patterning on the deposited layer to form one or more blocks of cured photoresists. The manufacturing system performs a thermal curing of the one or more blocks of uncured photoresists to form an array of microlens of the light field sensor. Each microlens covers at least one of the plurality of pixels of the light field sensor formed on the wafer.
US10714518B2 Imaging device
An imaging device includes: a container including a bottom plate and a side wall provided on an outer circumferential portion of the bottom plate; a step portion which is formed in a top outer circumferential portion of the side wall and includes: a horizontal surface that is located at a lower position than a top surface of the side wall; and a side surface that connects the top surface of the side wall to the horizontal surface; an imaging element mounted on the bottom plate; a glass lid which is bonded to the top surface of the side wall with a first adhesive layer; and a cover frame which is disposed on the step portion and bonded to the side surface of the step portion and an outer circumferential surface of the glass lid with a second adhesive layer.
US10714515B2 Solid-state image sensing apparatus, electronic device, and transportation equipment
An image sensing apparatus is provided. The apparatus comprises pixels each including a photoelectric conversion element arranged in a semiconductor layer which has a first surface and a second surface and a wiring layer arranged below the first surface. Each of the pixels includes a first reflection film arranged below the first surface, an interlayer film arranged so as to cover the second surface, a second reflection film arranged inside the interlayer film and a microlens which is arranged above the interlayer film. An aperture is arranged in a portion, of the second reflection film, which overlaps the photoelectric conversion element. An area of the aperture is smaller than an area of the photoelectric conversion element, and each of the pixels further includes a deflecting portion configured to deflect light between the aperture and the second surface.
US10714512B2 Thin film transistor, method for fabricating the same, and display device
The disclosure discloses a thin film transistor, a method for fabricating the same, and a display device so as to avoid a source and a drain from being oxidized while the thin film transistor is being fabricated, to thereby improve the performance of the thin film transistor. The method for fabricating a thin film transistor includes: forming an active layer pattern on a base substrate, and a source-drain metal layer located above the active layer pattern and with a same pattern as the active layer pattern, using one patterning process; forming a first insulation layer above the source-drain metal layer; and patterning the source-drain metal layer and the first insulation layer using one patterning process so that portion of the active layer pattern corresponding to a channel area is exposed to form a source pattern and a drain pattern.
US10714509B2 Display panel and display device
The present disclosure provides a display panel including a display area and a non-display area, a base substrate, a plurality of thin film transistors, a plurality of touch signal lines, a first test signal line area, an array substrate row driving circuit, a second test signal line area, a ground line area and an insulating layer. The thin film transistor includes a gate, a gate insulating layer, a source and a drain. The non-display area includes a first side and a second side; the array substrate row driving circuit respectively forms a first gap and a second gap with the first test signal line area and the second test signal line area, an orthographic projection of the ground line area on the base substrate is in the projection of the second test signal line area in the base substrate. The present disclosure also provides a display device.
US10714506B2 Photodetector and driving method thereof, display panel and display device
A photodetector, a driving method thereof, a display panel and a display device are disclosed in the field of display technology. The photodetector includes photosensitive element, a voltage divider, a switch circuitry and a detection transistor. The photosensitive element and the voltage divider are connected in series between two power terminals. The gate of the detection transistor is connected to a first voltage dividing node between the photosensitive element and the voltage divider. Therefore, when the resistance of the photosensitive element becomes smaller under illumination, the voltage of the first voltage dividing node correspondingly rises, and the detection transistor is turned on and may output a current to a read line under the driving of a DC power terminal. The magnitude of the current is determined by the magnitude of the voltage of the first voltage dividing node. Since the current output by the detection transistor under the driving of the DC power terminal is large, the influence of the leakage current of the detection transistor on the output current may be negligible, thereby effectively improving the accuracy of fingerprint identification based on the output current.
US10714504B2 Low temperature poly-silicon thin film transistor array substrate and method of producing the same
The present disclosure proposes a method of producing an LTPS TFT array substrate. The method is about stacking of a gate insulating layer and an interlayer insulating layer for providing conditions for formation of a gate trench. In addition, stacking of the gate insulating layer and the interlayer insulating layer is produced with some blocks of forming a hole on the gate insulating layer and the interlayer insulating layer to form a hole pattern, filling the gate trench, and producing gate lines. In this way, the formation of the gate lines and the formation of the hole pattern on the gate insulating layer and the interlayer insulating layer are done using the same mask. The method of the present disclosure reduces the number of masks required compared with the method of the related art, thereby reducing the production costs.
US10714503B2 Display device including transistor and manufacturing method thereof
An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.
US10714501B2 Co-integration of bulk and SOI transistors
An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
US10714500B2 Electronic device and method of manufacturing the same
Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.
US10714495B2 Three-dimensional semiconductor memory devices including through-interconnection structures
A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.
US10714493B2 Semiconductor plug protected by protective dielectric layer in three-dimensional memory device and method for forming the same
Embodiments of 3D memory devices with a semiconductor plug protected by a dielectric layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the memory stack. The memory string includes a semiconductor plug in a lower portion of the memory string, a protective dielectric layer on the semiconductor plug, and a memory film above the protective dielectric layer and along a sidewall of the memory string.
US10714492B2 Methods for forming multi-division staircase structure of three-dimensional memory device
Embodiments of methods for forming a staircase structure of a three-dimensional (3D) memory device are disclosed. In an example, a first plurality of stairs of the staircase structure are formed based on a first photoresist mask. Each of the first plurality of stairs includes a number of divisions at different depths. After forming the first plurality of stairs, a second plurality of stairs of the staircase structure are formed based on a second photoresist mask. Each of the second plurality of stairs includes the number of divisions. The staircase structure tilts downward and away from a memory array structure of the 3D memory device from the first plurality of stairs to the second plurality of stairs.
US10714489B2 Method of programming a split-gate flash memory cell with erase gate
A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.
US10714488B2 Using three or more masks to define contact-line-blocking components in FinFET SRAM fabrication
A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.
US10714487B2 Semiconductor device and manufacturing method of a semiconductor device
A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.
US10714484B2 SRAM structure
An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a plurality of second well regions with a second doping type, a third well region with the second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions, and a plurality of memory cells. The first well regions, the second well regions, and the third well region are formed in a semiconductor substrate. The third well region is adjacent to the second well regions. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the third well region. The second well pick-up regions are shared by the third well region and the second well regions. The memory cells are formed on the first and second well regions.
US10714482B1 Method of fabricating dynamic random access memory
A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes forming a gate trench in a substrate. An isolation structure is formed in the substrate and defines a plurality of active regions arranged in a column in a first direction. A buried word line structure is formed to fill the gate trench and extend along the first direction and across the plurality of active regions and the isolation structure. A plurality of first fin structures is formed in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure. A dielectric layer is formed on the substrate to fill the gate trench and cover the buried word line structure.
US10714481B2 Semiconductor structure having air gap between gate electrode and distal end portion of active area and fabrication method thereof
A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.
US10714478B2 Semiconductor devices with peripheral gate structures
A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.
US10714477B2 SiGe p-channel tri-gate transistor based on bulk silicon and fabrication method thereof
A p-channel tri-gate transistor has a silicon fin that protrudes from a bulk silicon substrate, a thin silicon-germanium active layer is formed on three sidewalls of the silicon fin, and a hole well is formed between the gate insulating film and the silicon fin in the active layer surrounded by the tri-gate by a valence band offset electric potential against the silicon fin for moving holes collected in the hole well along the active layer with a high hole-mobility. Thus, it is possible to have the effects of not only an ultra-high speed, low power operation, but also a body biasing through an integral structure of the silicon fin-body. The p-channel tri-gate transistor can be fabricated together with an n-channel FinFET transistor in one substrate by the same CMOS process.
US10714475B2 Semiconductor device and manufacturing method thereof
A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.
US10714474B2 High voltage CMOS with triple gate oxide
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
US10714473B2 Semiconductor device
A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
US10714471B2 Semiconductor device and fabrication method thereof
A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.
US10714470B2 Method and apparatus of forming high voltage varactor and vertical transistor on a substrate
Fabricating a semiconductor device includes receiving a substrate structure including a substrate. The substrate structure further includes a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate. The substrate structure further includes a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion. A mask is applied to the portion of the bottom spacer formed on the first bottom source/drain. The portion of the bottom spacer formed on the second bottom source/drain of the varactor portion is removed. The mask is removed from the portion of the bottom spacer formed on the first bottom source/drain. A gate oxide is deposited on the vertical transistor portion and the varactor portion.
US10714468B2 Optical integrated circuit systems, devices, and methods of fabrication
An optical integrated circuit device includes a semiconductor substrate and a first waveguide made of a first material and disposed over the semiconductor substrate. The first waveguide includes a parallel region and a tapered region. The optical integrated circuit device further includes a first cladding structure disposed over and surrounding the parallel region of the first waveguide, a first extension made of the first material and disposed over the semiconductor substrate, and an electrostatic discharge (ESD) protection structure electrically coupled to the first extension. The first extension physically contacts the parallel region of the first waveguide. The first extension includes a first portion within the first cladding structure and a second portion outside the first cladding structure.
US10714466B1 Layout pattern for magnetoresistive random access memory
A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
US10714465B2 Motor drive circuit, semiconductor apparatus, and electronic device
An H bridge circuit that is connected to nodes N1 and N2 for a power source and nodes N3 and N4 for a motor includes: a PchMOS transistor that is disposed in an N-type first region and is connected between N1 and N3; an NchMOS transistor that is disposed in an N-type second region and is connected between N2 and N3; a PchMOS transistor that is disposed in an N-type third region and is connected between N1 and N4; and an NchMOS transistor that is disposed in an N-type fourth region and is connected between N2 and N4, in a P-type semiconductor substrate. The distance between the first region and third region is smaller than the distance between the first region and second region, smaller than the distance between the third region and fourth region, and smaller than the distance between the second region and fourth region.
US10714464B2 Method of selectively transferring LED die to a backplane using height controlled bonding structures
Selective transfer of dies including semiconductor devices to a target substrate can be performed employing local laser irradiation. Coining of at least one set of solder material portions can be employed to provide a planar surface-to-surface contact and to facilitate bonding of adjoining pairs of bond structures. Laser irradiation on the solder material portions can be employed to sequentially bond selected pairs of mated bonding structures, while preventing bonding of devices not to be transferred to the target substrate. Additional laser irradiation can be employed to selectively detach bonded devices, while not detaching devices that are not bonded to the target substrate. The transferred devices can be pressed against the target substrate during a second reflow process so that the top surfaces of the transferred devices can be coplanar. Wetting layers of different sizes can be employed to provide a trapezoidal vertical cross-sectional profile for reflowed solder material portions.
US10714462B2 Multi-chip package with offset 3D structure
Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.
US10714459B2 Light emitting device with LED stack for display and display apparatus having the same
A light emitting device for a display includes a substrate and first, second, and third LED sub-units, a first transparent electrode between the first and second LED sub-units and in ohmic contact with the first LED sub-unit, a second transparent electrode between the second and third LED sub-units and in ohmic contact with the second LED sub-unit, a third transparent electrode between the second transparent electrode and the third LED sub-unit and in ohmic contact with the third LED sub-unit, at least one current spreader connected to at least one of the first, second, and third LED sub-units, electrode pads disposed on the substrate, and through-hole vias formed through the substrate, in which at least one of the through-hole vias is formed through the substrate and the first and second LED sub-units.
US10714458B2 Multi-LED system
A multi-LED system includes a carrier; and a plurality of light-emitting diodes arranged on the carrier, wherein the carrier has a main body, and a plurality of electrical components are embedded in the main body.
US10714456B2 Dual sided fan-out package having low warpage across all temperatures
Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.
US10714454B2 Stack packaging structure for an image sensor
According to an aspect, a stack packaging structure includes a substrate, a semiconductor device coupled to a surface of the substrate, an image sensor device coupled to the semiconductor device such that the semiconductor device is disposed between the surface of the substrate and the image sensor device, at least one bond wire connected to the image sensor device and the surface of the substrate, a inner molding disposed between the surface of the substrate and the image sensor device, where the semiconductor device is encapsulated within the inner molding, and an outer molding disposed on the surface of the substrate, where the at least one bond wire is encapsulated within the outer molding.
US10714453B2 Semiconductor package including semiconductor chip
A semiconductor package includes a first semiconductor chip disposed on a substrate. A first upward pad is disposed on an upper surface of the first semiconductor chip. A second semiconductor chip is arranged with an offset above the first semiconductor chip. A first downward pad is disposed on a lower surface of the second semiconductor chip. A first bonding wire connects the first upward pad and the substrate. A first inter-chip connector is interposed between the first upward pad and the first downward pad. A side surface of the second semiconductor chip is arranged above the first upward pad.
US10714452B2 Package structure and method of manufacturing the same
The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.
US10714448B2 Chip module with porous bonding layer and stacked structure with porous bonding layer
A chip module includes a body, a bump, and a first bonding layer. The bump is disposed on the body. The first bonding layer is disposed on the bump. The first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous.
US10714447B2 Electrode terminal, semiconductor device, and power conversion apparatus
An electrode terminal includes a body and a first bonding part. The body includes a first metal material. Then, the first bonding part is bonded to one end of the body, and includes a second metal material which is a clad material other than the first metal material. The first bonding part is ultrasonically bondable to a first bonded member. An elastic part which is elastically deformable is provided between the one end of the body and the other end of the body.
US10714446B2 Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such
An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.
US10714440B2 Fan-out semiconductor package
A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.
US10714437B2 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.
US10714434B1 Integrated magnetic inductors for embedded-multi-die interconnect bridge substrates
An embedded magnetic inductor coil is at least partially exposed in a recess that seats an embedded multi-chip interconnect bridge die on the coil. The embedded multi-chip interconnect bridge die provides a communications bridge between a dominant semiconductive device and a first semiconductive device.
US10714427B2 Secure chips with serial numbers
An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.
US10714425B2 Flexible system integration to improve thermal properties
In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.
US10714424B2 Method of forming metal interconnection
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.
US10714420B1 High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations
Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor. The truncated via contacts allow for higher density via contact connections to the capacitor electrodes in regions which have a dense array of wiring of a single polarity, where interlevel via contacts cannot be utilized to provide contacts to the capacitor electrodes.
US10714419B2 Non-planar metal-insulator-metal capacitor formation
A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer formed on a base structure that has one or more recesses, each comprising contours formed at two or more planar levels. The first dielectric layer is formed along the contours of the one or more recesses. A first electrode is formed on the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the first electrode. A second electrode is formed over the second dielectric layer. The first electrode, the second dielectric layer and the second electrode form a non-planar capacitor.
US10714418B2 Electronic device having inverted lead pins
An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.
US10714416B2 Semiconductor package having a circuit pattern
A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first insulation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.
US10714414B2 Planarizing RDLS in RDL—First Processes Through CMP Process
A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.
US10714413B2 Leadframe assembly for a semiconductor device
The present disclosure relates to a lead frame assembly for a semiconductor device. The leadframe assembly includes a clip frame structure with a die connection portion configured and arranged for contacting to one or more contact terminals on a top side of a semiconductor die; and one or more electrical leads extending from the die connection portion at a first end. The die connection portion includes a hooking tab extending therefrom configured and arranged to engage with a wire loop of a wire pull test equipment. The disclosure also relates to an interconnected matrix of such leadframe.
US10714401B2 Printed circuit board and semiconductor package including the same
A semiconductor package including a package substrate including a mounting region and at least one through-hole arranged in the mounting region, and a semiconductor chip mounted on the mounting region, the semiconductor chip including a first side and a second side, the second side of the semiconductor chip being opposite to the first side of the semiconductor chip, the at least one through-hole of the package substrate being closer to the second side of the semiconductor chip than the first side of the semiconductor chip may be provided.
US10714397B2 Semiconductor device including an active pattern having a lower pattern and a pair of channel patterns disposed thereon and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.
US10714391B2 Method for controlling transistor delay of nanowire or nanosheet transistor devices
A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure including an initial volume of second channel material; reducing said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.
US10714390B2 Wafer dicing using femtosecond-based laser and plasma etch
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
US10714389B2 Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration
Semiconductor devices and methods to fabricate the devices are provided. For example, a semiconductor device includes a back-end-of-line (BEOL) structure formed on a semiconductor substrate. The BEOL structure further includes at least one metallization layer comprising a pattern of elongated parallel metal lines. The pattern of elongated metal lines comprises a plurality of metal lines having a minimum width and at least one wider metal line having a width which is greater than the minimum width.
US10714387B2 Integrated circuit devices and method of manufacturing the same
An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.
US10714381B2 Semiconductor device having composite structures and fabrication method thereof
A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes forming a first composite structure, including a plurality of first composite layers, on a substrate, and forming a second composite structure, including a plurality of second composite layers on a surface portion of the first composite structure. The method also includes forming a first mask layer covering a sidewall of the second composite structure and a surface portion of the first composite structure and exposing at least another surface portion of the first composite structure. In addition, the method includes forming a second mask layer, on a surface portion of the second composite structure and spaced apart from the first mask layer by a first annular opening. Further, the method includes etching a top first layer of the first composite layers and a top first layer of the second composite layers.
US10714378B2 Semiconductor device package and manufacturing method thereof
Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.
US10714374B1 High-precision printed structures
An example of a printed structure comprises a target substrate and a structure protruding from a surface of the target substrate. A component comprising a component substrate separate and independent from the target substrate is disposed in alignment with the structure on the surface of the target substrate within 1 micron of the structure. An example method of making a printed structure comprises providing the target substrate with the structure protruding from the target substrate, a transfer element, and a component adhered to the transfer element. The component comprises a component substrate separate and independent from the target substrate. The transfer element and adhered component move vertically toward the surface of the target substrate and horizontally towards the structure until the component physically contacts the structure or is adhered to the surface of the target substrate. The transfer element is separated from the component.
US10714365B2 Liquid processing apparatus
A liquid processing apparatus includes a processing unit, a first supply route, a first device, a second supply route, a second device, a housing, and an external housing. The processing unit processes a substrate by using processing liquid including first and second processing liquids. The first supply route is for supplying the first processing liquid to the processing unit. The first device is for supplying the first processing liquid to the first supply route. The second supply route is for supplying the second processing liquid to the processing unit. The second processing liquid has higher temperature than the first processing liquid. The second device is for supplying the second processing liquid to the second supply route. The housing accommodates the processing unit. The external housing accommodates the first and second devices, and is adjacent to the housing. The external housing includes a partition wall between the first and second devices.
US10714364B2 Apparatus and method for inspecting wafer carriers
An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing having an opening on a wall of the housing; a load port outside the housing; a robot arm inside the housing; and a processor. The load port is coupled to the wall and configured to load a wafer carrier for inspection. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.
US10714361B2 Method of fabricating a semiconductor package using an insulating polymer layer
A method of fabricating semiconductor packages includes forming an insulating polymer layer on a substrate to cover a plurality of conductive patterns on the substrate, planarizing the insulating polymer layer by pressing the insulating polymer layer downward by using at least one pressure member, and patterning the planarized insulating polymer layer to expose at least parts of the plurality of conductive patterns.
US10714360B2 Method for manufacturing a module and an optical module
A method for manufacturing a module including N layers of stacked resin is provided, wherein N is a natural number of two or more. In the method, resin of a first layer is cured to a degree that does not fully harden the resin of the first layer. Resin of a Mth layer is stacked on resin of a (M−1)th layer, wherein M is a natural number of two or more and less than N. The resin of the Mth layer is cured to a degree that does not fully harden the resin of the Mth layer. Stacking the resin of the Mth layer and curing the resin of the Mth layer are repeated. Then, resin of Nth layer is stacked, and all of the N layers of stacked resin are fully hardened.
US10714356B2 Plasma processing method
Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.
US10714354B2 Self limiting lateral atomic layer etch
Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.
US10714346B2 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes in a following order: a first forming step where a gate electrode is formed on a first main surface side of a semiconductor base substrate with a gate insulation film interposed therebetween and, thereafter, an interlayer insulation film is formed to cover the gate electrode; a second forming step where a metal layer in a state of being connected with the gate electrode is formed over the interlayer insulation film; an irradiating step where a lattice defect is formed inside the semiconductor base substrate by irradiating an electron beam to the semiconductor base substrate in a state where the metal layer is set to a ground potential; a dividing step where the metal layer is divided into a plurality of electrodes; and an annealing step where the lattice defect in the semiconductor base substrate is repaired by heating the semiconductor base substrate.
US10714341B2 Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch
Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.
US10714340B2 Method for processing workpiece
According to an embodiment, a wafer W includes a layer EL to be etched, an organic film OL, an antireflection film AL, and a mask MK1, and a method MT according to an embodiment includes a step of performing an etching process on the antireflection film AL by using the mask MK1 with plasma generated in a processing container 12, in the processing container 12 of a plasma processing apparatus 10 in which the wafer W is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film SX on the surface of the mask MK1, and steps ST6a to ST7 of etching the antireflection film AL by removing the antireflection film AL for each atomic layer by using the mask MK1 on which the protective film SX is formed.
US10714337B2 Process for growing nanowires or nanopyramids on graphitic substrates
A process for growing nanowires or nanopyramids comprising: (I) providing a graphitic substrate and depositing AlGaN, InGaN, AlN or AlGa(In)N on said graphitic substrate at an elevated temperature to form a buffer layer or nanoscale nucleation islands of said compounds; (II) growing a plurality of semiconducting group III-V nanowires or nanopyramids, preferably III-nitride nanowires or nanopyramids, on the said buffer layer or nucleation islands on the graphitic substrate, preferably via MOVPE or MBE.
US10714331B2 Method to fabricate thermally stable low K-FinFET spacer
A method for forming a thermally stable spacer layer is disclosed. The method includes first disposing a substrate in an internal volume of a processing chamber. The substrate has a film formed thereon, the film including silicon, carbon, nitrogen, and hydrogen. Next, high pressure steam is introduced into the processing chamber. The film is exposed to the high pressure steam to convert the film to reacted film, the reacted film including silicon, carbon, oxygen, and hydrogen.
US10714327B2 System and method for pumping laser sustained plasma and enhancing selected wavelengths of output illumination
A system for pumping laser sustained plasma and enhancing one or more selected wavelengths of output illumination generated by the laser sustained plasma is disclosed. In embodiments, the system includes one or more pump modules configured to generate pump illumination for the laser sustained plasma and one or more enhancing illumination sources configured to generate enhancing illumination at one or more selected wavelengths. The pump illumination may be directed along one or more pump illumination paths that are non-collinear to an output illumination path of the output illumination. The enhancing illumination may be directed along an illumination path that is collinear to the output illumination path of the output illumination so that the enhancing illumination is combined with the output illumination, thereby enhancing the output illumination at the one or more selected wavelengths.
US10714325B2 Glow discharge ion source
A mass spectrometer is disclosed comprising a glow discharge device within the initial vacuum chamber of the mass spectrometer. The glow discharge device may comprise a tubular electrode located within an isolation valve, which is provided in the vacuum chamber. Reagent vapour may be provided through the tubular electrode, which is then subsequently ionised by the glow discharge. The resulting reagent ions may be used for Electron Transfer Dissociation of analyte ions generated by an atmospheric pressure ion source. Other embodiments are contemplated wherein the ions generated by the glow discharge device may be used to reduce the charge state of analyte ions by Proton Transfer Reaction or may act as lock mass or reference ions.
US10714322B2 IRMS sample introduction system and method
A sample introduction system for a spectrometer comprises a desolvation region that receives or generates sample ions from a solvent matrix and removes at least some of the solvent matrix from the sample ions. A separation chamber downstream of the desolvation region has a separation chamber inlet communicating with the desolvation region, for receiving the desolvated sample ions along with non-ionised solvent and solvent ion vapours. The separation chamber has electrodes for generating an electric field within the separation chamber, defining a first flow path for sample ions between the separation chamber inlet and a separation chamber outlet. Unwanted solvent ions and non-ionised solvent vapours are directed away from the separation chamber outlet. The sample introduction system has a reaction chamber with an inlet communicating with the separation chamber outlet, for receiving the sample ions from the separation chamber and for decomposing the received ions into smaller products.
US10714311B2 Individual beam detector for multiple beams, multi-beam irradiation apparatus, and individual beam detection method for multiple beams
An individual beam detector for multiple beams includes a thin film in which a passage hole smaller than a pitch between beams of multiple beams and larger than the diameter of a beam is formed and through which the multiple beams can penetrate, a support base to support the thin film in which an opening is formed under the region including the passage hole, and the width size of the opening is formed to have a temperature of the periphery of the passage hole higher than an evaporation temperature of impurities adhering to the periphery in the case that the thin film is irradiated with the multiple beams, and a sensor arranged, at the position away from the thin film by a distance based on which a detection target beam having passed the passage hole can be detected by the sensor as a detection value with contrast discernible.
US10714310B2 Methods and apparatus for high throughput SEM and AFM for characterization of nanostructured surfaces
A system and method is provided for of characterizing nanostructured surfaces. A nanostructure sample is placed in an SEM chamber and imaged. The system and method locates one of the nanostructures using images from the SEM imaging, excises a top portion of the nanostructure, places said top portion on a substrate such that the nanostructures are perpendicular to the substrate and a base of the top portion contacts the substrate, performs high energy ion beam assisted deposition of metal at the base to attach the top portion to the substrate, SEM imaging the top portions in the SEM chamber, determining coordinates of the top portions relative to the substrate from the SEM imaging of the top portions, placing the substrate in an AFM chamber, and performing AFM imaging of the top portions using the coordinates previously determined.
US10714306B2 Measuring a height profile of a hole formed in non-conductive region
A system, computer program product and a method for measuring a hole. The method may include charging a vicinity of the hole having a nanometric width; obtaining, multiple electron images of the hole; wherein each electron image is formed by sensing electrons of an electron energy that exceeds an electron energy threshold that is associated with the electron image; wherein electron energy thresholds associated with different electron images of the multiple electron images differ from each other; receiving or generating a mapping between height values and the electron energy thresholds; processing the multiple electron images to provide hole measurements; and generating three dimensional measurements of the hole based on the mapping and the hole measurements.
US10714304B2 Charged particle beam apparatus
A charged particle beam device is provided that performs proper beam adjustment while suppressing a decrease in MAM time, with a simple configuration without adding a lens, a sensor, or the like. The charged particle beam device includes: an optical element which adjusts a charged particle beam emitted from a charged particle source; an adjustment element which adjusts an incidence condition of the charged particle beam with respect to the optical element; and a control device which controls the adjustment element, wherein the control device determines a difference between a first feature amount indicating a state of the optical element based on the condition setting of the optical element, and a second feature amount indicating a state where the optical element reaches based on the condition setting and executes adjustment by the adjustment element when the difference is greater than or equal to a predetermined value.
US10714300B2 Stationary anode for an X-ray generator, and X-ray generator
A stationary anode for an X-ray generator, in particular of an X-ray imaging device or an X-ray therapy or spectroscopy device, includes a main anode body and an internal cooling duct, running in the axial direction, for conveying a cooling fluid to a heat exchange surface of the main anode body. A nozzle, disposed at the end of the cooling duct, is inventively positioned with respect to the heat exchange surface via stop elements such that, between the heat exchange surface and the nozzle, a gap is formed which extends over an angular range of 360° about the axial direction.
US10714299B2 Thermoelectrically-cooled x-ray shield
Disclosed herein is a system for x-ray backscatter inspection. The system comprises an interior cavity. The system also comprises a non-conductive fluid contained within the interior cavity. The system additionally comprises a power source within the interior cavity and submerged in the non-conductive fluid. The system further comprises an x-ray cathode within the interior cavity, submerged in the non-conductive fluid, and coupled to the power source. The system also comprises an x-ray anode within the interior cavity, submerged in the non-conductive fluid, and positioned to receive an electron emission from the x-ray cathode to generate an x-ray emission. The system additionally comprises a thermoelectric cooler surrounding the interior cavity and operable to draw heat from the non-conductive fluid.
US10714294B2 Metal protective layer for electron emitters with a diffusion barrier
An emitter with a diameter of 100 nm or less is used with a protective cap layer and a diffusion barrier between the emitter and the protective cap layer. The protective cap layer is disposed on the exterior surface of the emitter. The protective cap layer includes molybdenum or iridium. The emitter can generate an electron beam. The emitter can be pulsed.
US10714291B2 Relay
The pressing member is configured to move to an off-position and an on-position. When the pressing member is located at the off-position, the first contact and the second contact come into a non-contact state. When the pressing member is located at the on-position, the first contact and the second contact come into a contact state by press of the pressing member against the contact piece. The actuator moves the pressing member from the off-position to the on-position via an overshoot position located beyond the on-position. The contact piece includes a body, and a low rigidity portion having rigidity lower than rigidity of the body. The pressing member presses the low rigidity portion.
US10714289B2 Electromagnetic relay
An electromagnetic relay is provided with a housing; a first fixed contact terminal and a second fixed contact terminal; a movable contact, a movable shaft with one end connected to the movable contact, and a coil spring placed between the movable contact and an insulating wall in a chamber in the housing. The coil spring configured to bias movable contact points toward the opposing fixed contact points. The movable contact includes a contact body which includes a connection hole configured to receive the movable shaft and allow the movable shaft to travel relatively in the contact movement direction. The movable shaft includes a second holder that together with the first holder retains the coil spring.
US10714287B2 Fuse element
A fuse element for an electric circuit, arranged on a circuit board of the electric circuit, has a surface area for fastening and establishing an electric contact on the circuit board, a first deforming area adjacent the surface area, a second deforming area connected to the first deforming area via a central area, the second deforming area including a contact area that abuts the circuit board, and a hook-shaped element insertable into an opening adjacent the contact area, the hook-shaped element is insertable into the opening by elastic deformation of the fuse element in the direction of the circuit board and, after insertion of the hook-shaped element into the opening and positive holding of the hook-shaped element on a lower surface of the circuit board, the first and second deforming areas exert an elastic force on the surface area in the direction away from the circuit board.
US10714286B2 Magnetically activated switch having magnetostrictive material
Switch assemblies and a switching method are disclosed. In some embodiments, a switch assembly may include a first contact element, and a second contact element operable with the first contact element. The first and second contact elements form an open circuit in a first configuration and form a closed circuit in a second configuration. At least one of the first contact element and the second contact element includes a magnetostrictive material. During operation, a magnetic field from a magnet causes the magnetostrictive material to deform or change shape/dimensions, thus causing the first and second contact elements to open or close. In some embodiments, the switch assembly is a micro-electro-mechanical-system (MEMS) switch.
US10714283B2 Switch for an electrical device
The invention relates to a switch for an electrical device, in particular for an electrical tool, comprising a slide control for setting a rotational speed of the electrical device, a switch housing, and at least one circuit board arranged in the switch housing for holding electrical components of the slide control. According to the invention, a movably supported operating element of the slide control is inserted into a contact chamber of the switch housing in a sealed manner through a first feed-through and is led out of the contact chamber in a sealed manner through a second feed-through in all adjustment positions of the operating element. Thus, a switch that ensures reliable function even under ambient conditions of high contamination is provided.
US10714279B1 Keyboard device
A keyboard device includes a substrate and several keycaps disposed on the substrate. The substrate includes a long slit and an elastic bridge connecting member. The long slit divides the substrate into a first plate having a first side edge and a second plate having a second side edge opposite to the first side edge. A gap is between the first side edge and the second side edge. The elastic bridge connecting member is connected between the first side edge and the second side edge. The first plate is movable relative to the second plate. The first side edge includes a first stopping member, the second side edge includes a second stopping member, and a certain interval is between the first stopping member and the second stopping member.
US10714275B2 Illuminated visible break
An assembly for use in an electrical power distribution system includes a housing that includes an interior space; an electrical apparatus in the interior space, the electrical apparatus including an electrical connection mechanism that is configured to move between at least two positions; an observation port through the housing, the observation port being configured to allow visual observation of the electrical connection mechanism in the interior space from an exterior of the housing; and an optical guide between the interior space and a light source. The light source is outside of the interior space and the optical guide is configured to deliver light from the light source to the interior space when the light source emits light.
US10714274B2 Medium voltage circuit switch or breaker
A medium voltage circuit switch or breaker includes: at least one movable contact; a fixed contact; and a mechanical or magnetical drive system, which moves the at least one movable contact to a closed or opened position by a movement of a rod and/or a lever. The mechanical or magnetical drive system is linked to a switching generating signal. The mechanical or magnetical drive system includes at least one pyrotechnical actuator or gas generator. The pyrotechnical actuator or the gas generator is linkable to the switching generating signal of the mechanical or magnetical drive system.
US10714273B2 Graphene supercapacitor design and manufacture
Improvements in design and manufacturing techniques to produce a graphene based prismatic supercapacitor of very high capacitance with very high energy density storage able to outperform and replace the cutting edge batteries available in the market today.
US10714272B2 Graphene frameworks for supercapacitors
The present disclosure provides supercapacitors that may avoid shortcomings of current energy storage technology. Provided herein are materials and fabrication processes of such supercapacitors. In some embodiments, an electrochemical system comprising a first electrode, a second electrode, wherein at least one of the first electrode and the second electrode comprises a three dimensional porous reduced graphene oxide framework.
US10714270B2 Photoelectric conversion device and method for manufacturing the same
The present embodiments provide a flexible, lightweight and highly efficient photoelectric conversion device and further provide a manufacturing method thereof. The photoelectric conversion device according to the embodiment comprises a laminate structure of a substrate, an ITO electrode, a photoelectric conversion layer and a counter electrode. When subjected to surface X-ray diffraction analysis, the ITO electrode shows an X-ray diffraction profile characterized in that the peak at a diffraction peak position in the range of 2θ=30.6±0.5° has a half-width of 1.0° or less. The ITO electrode in the device can be formed by forming an amorphous-phase ITO film on the substrate and then by subjecting the film to annealing treatment at a temperature of 200° or less.
US10714269B2 Method of making coated substrates
Methods' and compositions for making coated substrates using a co-solvent method are disclosed. Embodiments of the present disclosure relate in general to methods and compositions for making thin films of organometallic halides. According to one aspect, organometallic halides are deposited from solution on the surface of a substrate at temperatures between about 10 C and 50 C. According to one aspect, organometallic halides are deposited from solution on the surface of a substrate at room temperature.
US10714259B2 Method for making a multilayered ceramic capacitor
A method for forming an MLCC with an identification mark consisting of non-active internal electrodes which can be used to determine chip orientation for mounting or reeling. The method includes printing layers, forming a stack of the layers, sintering the stack, dicing the stack and forming external terminations.
US10714258B2 Stationary induction apparatus
A stationary induction apparatus includes a winding formed of a plurality of winding layers disposed in a central axis direction, an insulating barrier and an insulating oil. The insulating barrier includes a first extension extending radially outwardly of the winding and partitioning the outer peripheral ends, a second extension bent from an end of the first extension, extending toward one side in the central axis direction, and covering at least a part of one outer peripheral end of the outer peripheral ends, a third extension bent from an end of the second extension and extending radially outwardly of the winding, and a fourth extension bent from an end of the third extension, extending toward the other side in the central axis direction, and covering at least a part of the other outer peripheral end of the outer peripheral ends. The fourth extension faces the second extension with a spacing therebetween.
US10714255B2 Common mode choke coil
A common mode choke coil includes a core and a first winding, a second winding, and a third winding that are wrapped around the core. A number of turns in the third winding is less than a number of turns in the first winding and a number of turns in the second winding.
US10714254B2 Electronic component
An electronic component includes a body, a first inductor, and a low expansion portion. The body includes a laminated body including a plurality of insulating layers laminated in a lamination direction. The insulating layers contain a first resin as a material. The first inductor includes a first inductor conductor layer that adjoins one of the insulating layers. The low expansion portion has a coefficient of linear expansion lower than a coefficient of linear expansion of the plurality of insulating layers. The low expansion portion contains a second resin as a material. At least part of the low expansion portion is embedded in the laminated body. The second resin has a coefficient of linear expansion that is lower than a coefficient of linear expansion of the first resin.
US10714243B2 Variable resistance circuit, oscillator circuit, and semiconductor device
Provided is a variable resistance circuit in which the resistance value of the variable resistance circuit can be accurately adjusted, by reducing the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistances of switch circuits even if the switch circuits that each bypass a resistor included in a ladder resistor circuit are switched between an OFF state and an ON state. This variable resistance circuit includes: a ladder resistor circuit including a plurality of resistors; a first switch circuit connected in series to one end of one resistor of the plurality of resistors; and a second switch circuit connected in parallel to a series circuit of the one resistor and the first switch circuit. When one of the first and second switch circuits is turned on, the other of the first and second switch circuits is turned off.
US10714238B2 Joint for superconducting wire
The problem is to attain a joint for multi-core superconducting wires having a high critical current property. The joint for superconducting wires of the present invention has a first sintered body containing MgB2 configured to fix a plurality of superconducting wires, and a second sintered body containing MgB2 configured to joint the superconducting wires.
US10714228B2 Method for producing a microstructure component, microstructure component and x-ray device
A method for producing a microstructure component, a microstructure component and an x-ray device are disclosed. In the method, a plurality of punctiform injection structures are inserted in a grid in a first substrate direction and a second substrate direction, standing at right angles thereto, into a first surface of a wafer-like silicon substrate. The injection structures are lengthened into drilled holes in the depth direction of the silicon substrate in a first etching step. A second surface of the silicon substrate is then at least partly removed for rear-side opening of the drilled holes in a second etching step and in a third etching step, an etching medium acting anisotropically is poured alternately through the drilled holes from both surfaces of the silicon substrate, so that drilled holes arranged next to one another in the first substrate direction connect to form a column running in the first substrate direction.
US10714227B2 Rotating radiation shutter collimator
A shutter for controlling radiation exposure includes a rotatable member. The rotatable member is rotatable between an open position and a closed position. The rotatable member includes a passageway, wherein the passageway is positioned to receive radiation in the open position and is not positioned to receive radiation in the closed position. In the closed position, the rotatable member may substantially block or absorb the radiation. The passageway may collimate the radiation into a beam of radiation. The rotatable member may include a plurality of passageways positioned to receive radiation in the open position. The rotatable member may be rotatable between a plurality of open positions, each open position corresponding to at least one passageway. The open positions may align the source of radiation with different passageways in the rotatable member to form a different beam shape, a different number of beams, a different beam direction, or combinations thereof.
US10714214B2 Medical assistance device, operation method and operation program for medical assistance device, and medical assistance system
There are provided a medical assistance device, an operation method of a medical assistance device, a non-transitory computer-readable recording medium, and a medical assistance system capable of improving work efficiency by reducing the burden on a user. A recommended data range output unit receives a program ID of a diagnostic assistance program from a request receiving unit. The recommended data range output unit reads a recommended data range corresponding to the received program ID from a recommended data range list, and transmits the recommended data range to a screen generation unit. The screen generation unit includes a check box and a period designating bar for designating designated data items and a designated data period, which form a designated data range, and generates a medical data display screen on which displays of recommended data items and a recommended data period, which forms a recommended data range, are made.
US10714211B2 Apparatus and method for improving chemical process efficiency and promoting sharing of chemistry information
Apparatus and method for improving chemical process efficiency and promoting sharing of chemistry information for guiding and encouraging scientific researchers and institutions to develop and share more efficient chemical processes. Technical solution comprises: by means of execution and assessment analysis of relevant chemical processes of target compound or target compound system and provision of application program and website having social and electronic transaction functions installed on mobile device for scientific researchers on basis of Internet technology, sharing, transaction and assessment of relevant chemical processes of and chemistry information about compound can be disclosed are implemented, and users are guided and encouraged to share chemistry information and experience via electronic transaction system, developing more efficient chemical processes, reducing resource waste, promoting research and development efficiency, improving research and development efficiency of unknown innovative chemical processes and compounds.
US10714208B2 Computer systems for treating diseases
The present invention relates to computer-implemented methods and system for analysing a biomarker which cycles in a subject. In some other aspects, the present invention relates to analysing a biomarker which at least initially increases or decreases in amount in a subject following a treatment for a disease. In further aspects, the present invention relates to computer-implemented methods and systems for determining a preferred time to administer a therapy to treat a disease in a subject. The present invention also relates to computer program product to implement the methods. Further, the present invention relates to methods of determining the timing of treating a disease in a subject in which the immune system is cycling.
US10714206B2 Selectors on interface die for memory device
Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.
US10714205B1 Multi-purposed leak detector
Detecting a word line leakage in a non-volatile memory array. Various methods include: in a first step, enabling a M-bit “coarse” digital-to-analog converter (DAC) logic of an N-bit analog-to-digital converter (ADC) to, according to a clock signal of the coarse DAC, compare a reference voltage and a biased input voltage of a load current of the memory array, wherein the reference voltage is dependent upon the voltage level at which the input voltage becomes non-linear, and, in a second step, if the input voltage is greater than or equal to the reference voltage, enabling a P-bit “fine” ramp digital-to-analog converter (DAC) logic of the ADC to enable drawing a second current from the load current to ramp down the input voltage and to begin a counter and conduct leakage detection with the ADC when the input voltage is in the range between a first voltage and a second voltage.
US10714204B1 Shift register unit, driving method thereof, gate driving circuit and display device
A shift register unit including a first node control circuit, a second node control circuit, an energy-storing circuit, a first voltage pull circuit, a second voltage pull circuit, and an output circuit. The first node control circuit is configured to transfer a reset signal at a reset signal terminal to a first node in response to the reset signal at the reset signal terminal being active. The second node control circuit is configured to transfer an inactive voltage at a first voltage terminal to the first node in response to a potential at a second node being active. The output circuit is configured to transfer a clock signal at a clock signal terminal to a signal output terminal in response to the potential at the second node being active.
US10714198B1 Dynamic 1-tier scan for high performance 3D NAND
A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.
US10714197B1 Memory device and program verification method thereof
A memory device and a program verification method thereof are provided. The write verification method includes: reading a previous page to obtain first read data, writing input data to a current page, reading the previous page or the current page to obtain second read data, and analyzing at least one of the first read data and the second read data to determine whether to back up at least one of the first read data and the input data to a redundant block of the memory device.
US10714189B2 Atomicity management in an EEPROM
A method of verifying the atomicity of an operation of data update in an EEPROM, includes, during a data writing operation of writing the data, the steps of: initializing at least one first flag to a first value and storing this value in the EEPROM; erasing the data from the EEPROM; writing a value of the data into the EEPROM; and writing at least one second value of the first flag into the EEPROM.
US10714188B2 Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
US10714186B2 Method and apparatus for dynamically determining start program voltages for a memory device
In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.
US10714182B2 Semiconductor memory device
A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.
US10714179B2 Hybrid memory devices
In some examples, a hybrid memory device includes multiple memory cells, where a given memory cell of the multiple memory cells includes a volatile memory element having a plurality of layers including electrically conductive layers and a dielectric layer between the electrically conductive layers, and a non-volatile resistive memory element to store different data states represented by respective different resistances of the non-volatile resistive memory element, the non-volatile resistive memory element having a plurality of layers including electrically conductive layers and a resistive switching layer between the electrically conductive layers of the non-volatile resistive memory element.
US10714176B2 Read-write cycle execution based on history
Aspects of the present disclosure configure a media controller of a memory component to skip execution of a read-write cycle for specific data if the media controller has not observed at least one prior data modification request from a memory sub-system controller that causes modification of the specific data. For example, a media controller of a first memory component can be configured to include a data modification tracker to monitor a memory channel for data modification requests to a second memory component and to track data modification requests that have been observed by the media controller on the memory channel, where the memory channel may be one shared by the first and second memory components.
US10714173B2 System and method for performing memory operations in RRAM cells
A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.
US10714172B2 Bi-sided pattern processor
A bi-sided pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a memory array and a pattern-processing circuit. The preferred pattern processor further comprises a semiconductor substrate with opposing first and second surfaces. The memory array is disposed on the first surface, whereas the pattern-processing circuit is disposed on the second surface. The memory array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of inter-surface connections.
US10714170B2 Semiconductor memory device and memory system
According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.
US10714169B1 System and method for programming non-volatile memory during burst sequential write
A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
US10714163B2 Methods for mitigating transistor aging to improve timing margins for memory interface signals
An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.
US10714155B2 Charge pump circuit with low reverse current and low peak current
A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.
US10714152B1 Voltage regulation system for memory bit cells
Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuitry. The circuit receives a logic supply voltage rail and compares the logic supply voltage rail to threshold voltage(s) using the comparator(s). Comparison signal(s) from the comparator(s) are coupled to the control logic. The control logic generates mode control signals based on the comparison signal(s) and based on a programmable dynamic range that is desired for a memory bitcell supply voltage rail. The mode control signals are provided to the power stage circuitry which generates the memory bitcell supply voltage rail from the logic supply voltage rail. A voltage level of the memory bitcell supply voltage rail can be above, below, or the same as the logic supply voltage rail.
US10714151B2 Layered semiconductor device, and production method therefor
The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.
US10714150B2 Flexible memory system with a controller and a stack of memory
Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.
US10714148B2 SSD storage module, SSD component, and SSD
A SSD storage module comprising a printed circuit board, an encapsulating colloid, and an electronic circuit welded on an inner surface of the printed circuit board and having a data storage function; the encapsulating colloid is formed on the inner surface of the printed circuit board and is configured for seamlessly encapsulating the electronic circuit, an outer surface of the printed circuit board is provided with a plurality of metal contact pieces, the plurality of metal contact pieces are electrically connected with the electronic circuit, and the plurality of metal contact pieces comprise a plurality of SATA interface contact pieces. The encapsulating colloid seamlessly encapsulates the electronic circuit and isolates the electronic circuit from the air, such that a problem that the electronic circuit is directly exposed to the air, and performances of components of the electronic circuit may be affected, thereby resulting in an unstable functionality of a SSD can be avoided.
US10714145B2 Systems and methods to associate multimedia tags with user comments and generate user modifiable snippets around a tag time for efficient storage and sharing of tagged items
Example methods and apparatus to add a tagged snippet of multimedia content to a playlist are disclosed. An example apparatus comprises an automatic content recognition search service to search a fingerprint database to find a match between query fingerprints for a snippet of multimedia content captured from a multimedia program at a timestamp and reference fingerprints of matching reference multimedia content stored in the fingerprint database, a tag service to generate a tag representing the snippet of multimedia content, wherein the tag, the timestamp, meta information associated with the matching reference multimedia content, and a monitored variable for a number of viewers of the snippet of multimedia content are stored in a database storage as a tagged snippet of multimedia content, and to add the tagged snippet of multimedia content to a playlist for an identified multimedia program if the number of viewers of the tagged snippet exceeds a threshold.