| Document | Document Title |
|---|---|
| US10396770B2 |
Active triac triggering circuit
A power supply unit for use with thermostats or other like devices requiring power. A power supply unit may be designed to keep electromagnetic interference emissions at a minimum, particularly at a level that does not violate governmental regulations. A unit may be designed so that there is enough power for a triggering a switch at about a cross over point of a waveform of input power to the unit. Power for triggering may come from a storage source rather than line power to reduce emissions on the power line. Power for the storage source may be provided with power stealing. Power stealing may require switching transistors which can generate emissions. Gate signals to the transistors may be especially shaped to keep emissions from transistor switching at a minimum. |
| US10396769B2 |
Apparatus and method for clock signal frequency division using self-resetting, low power, linear feedback shift register (LFSR)
Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state. |
| US10396767B2 |
Semiconductor device
A semiconductor device includes an input determination circuit. The input determination circuit includes: a comparator that is driven based on a first reference potential and includes an input voltage terminal and a reference voltage terminal; a reference voltage generation circuit that inputs a reference voltage that is generated from a connection point between a constant current source and a resistor to the reference voltage terminal of the comparator, the constant current source and the resistor being interposed between a second reference potential that is separated from the first reference potential and a third potential that is higher than the first reference potential and the second reference potential; and a first low pass filter that is interposed between a signal input system that is connected to the input voltage terminal of the comparator and the second reference potential. |
| US10396763B2 |
Current-controlled CMOS logic family
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. |
| US10396759B2 |
Filter and multiplexer
A filter includes: a first substrate; first and second piezoelectric thin film resonators located on the first substrate, each of the resonators including first and second electrodes facing each other across a piezoelectric film, a crystal orientation from the first electrode to the second electrode of the piezoelectric film being the same between the resonators, the first electrodes of the resonators connecting to each other in a connection region between resonance regions where the first and second electrodes face each other across the piezoelectric film, the second electrodes of the resonators failing to connect to each other, and an area of the resonance region being approximately the same between the resonators, a second substrate mounting the first substrate across an air gap; and a ground pattern located on the second substrate and not overlapping with the first electrode located in the resonance regions and the connection region. |
| US10396757B2 |
Acoustic wave device
An acoustic wave device includes: a first piezoelectric substrate; a first IDT that includes a plurality of first electrode fingers and is located on a first surface of the first piezoelectric substrate; a second piezoelectric substrate that is located above the first surface; and a second IDT that is located on a second surface of the second piezoelectric substrate, and includes a plurality of second electrode fingers that are non-parallel to the plurality of first electrode fingers, the second surface of the second piezoelectric substrate facing the first surface across an air gap. |
| US10396752B2 |
MEMS device
A MEMS device that suppresses variations in a resistance value caused by contracting vibrations in a direction in which a holding portion extends. The MEMS device includes a frame, a rectangular plate that receives an input of a driving signal, and holding portions that anchor the rectangular plate to the frame. The frame and the rectangular plate are both rectangular in shape. The holding portions are provided extending toward the frame from central areas of the opposing sides of the rectangular plate, and anchor the rectangular plate to the frame. A resistive film is formed in a region that follows a straight line connecting the holding portions that anchor the rectangular plate to the frame and that corresponds to no more than half a maximum displacement from a vibration distribution. |
| US10396741B2 |
Headset with programmable microphone modes
A method and system for a headset with programmable modes, where the headset comprises a speaker and a beamforming microphone: sensing an ambient sound level near the headset, and configuring the headset in one of a plurality of modes by configuring a beam pattern of the beamforming microphone based on at least the sensed ambient noise level. A user of the headset may configure the headset in the one of the plurality of modes or it may be automatically configured. The beamforming microphone may comprise an array of sound sensing elements. The headset may be configured in a quiet mode when the sensed ambient sound level is below that of a desired sound source and may be configured with a wide beam pattern. The headset may be configured in a loud mode when the sensed ambient sound level is above that of a desired sound source. |
| US10396740B2 |
Microphone driving device and digital microphone including the same
The present disclosure relates to a microphone driving device and a digital microphone including the same. A microphone driving device according to an embodiment of the inventive concept includes a voltage-to-current converter, a current-to-voltage converter, an analog-to-digital converter, a digital amplification unit, and a gain controller. The voltage-to-current converter converts an acoustic signal to an output current signal based on a gain control signal. The current-to-voltage converter converts the output current signal to an amplified voltage signal. The analog-to-digital converter converts the amplified voltage signal to a digital signal. The digital amplification unit amplifies the digital signal to an amplified digital signal based on the gain control signal. The gain controller generates a gain control signal. The microphone driving device and the digital microphone including the same according to the inventive concept may have a wide dynamic range and reduce the influence of noise. |
| US10396737B2 |
Wide dynamic range amplifier system
Amplifier systems and methods are provided that include a fixed gain amplification stage coupled to an adjustable attenuation stage further coupled to a variable gain amplification stage. A controller controls an amount of attenuation provided by the adjustable attenuation stage and an amount of gain provided by the variable gain amplification stage to maintain any of various noise, efficiency, and/or linearity requirements of the amplifier system. |
| US10396735B2 |
Amplifier system with digital switched attenuator
A broadband amplifier assembly is provided that includes a fixed gain amplifier coupled to an adjustable attenuator which is further coupled to a power amplifier. The adjustable attenuator includes a plurality of attenuation cells directly coupled in series between the input and the output of the adjustable attenuator. |
| US10396731B2 |
Selective amplification of frequency multiplexed microwave signals using cascading multi-path interferometric Josephson directional amplifiers with nonoverlapping bandwidths
A cascading selective microwave directional amplifier (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies. Different operating bandwidths have different corresponding center frequencies. A series coupling is formed between first Josephson device from the set and an nth Josephson device from the set. The series coupling causes the first Josephson device to amplify a signal of a first frequency from a frequency multiplexed microwave signal (multiplexed signal) in a first signal flow direction through the series coupling and the nth Josephson device to amplify a signal of an nth frequency in a second signal flow direction through the series, where the second signal flow direction is opposite of the first signal flow direction. |
| US10396727B2 |
LC network for a power amplifier with selectable impedance
Exemplary embodiments including an amplifier circuit that includes a radio-frequency (RF) amplifier comprising an input terminal and an output terminal, the RF amplifier being configured to amplify, across a wideband frequency range, an RF signal applied to the input terminal to generate an amplified RF signal at the output terminal. The amplifier circuit also includes a first impedance matching network connected to the RF amplifier output terminal. The first impedance matching network includes a first reactive circuit, having substantially fixed impedance, connected between the RF amplifier input terminal and ground; a second reactive circuit; and a switching device configured to couple the second reactive circuit to the first reactive circuit in an ON state, and to decouple the second reactive circuit from the first reactive circuit in an OFF state. In some embodiments, the amplifier circuit can include a second impedance matching network connected to the RF amplifier input terminal. |
| US10396720B2 |
High-frequency amplifier apparatuses
High-frequency amplifier apparatuses suitable for producing output powers of at least 1 kW at frequencies of at least 2 MHz for plasma excitation are disclosed. These high-frequency amplifiers include two transistors, the source or emitter connections of which are each connected to a ground connection point. The transistors can have an identical design and are arranged on a multilayer printed circuit board. The apparatus also includes a power transformer, the primary winding of which is connected to the drain or collector connections of the transistors. The primary winding and the secondary winding of the power transformer are each in the form of planar conductor tracks which are arranged in different upper layers of the multilayer printed circuit board. |
| US10396719B2 |
Integrated circuit device
A circuit device includes a differential circuit including differential input terminals; a differential amplifier circuit in which differential input nodes are connected to the differential input terminals; a first power supply terminal supplied with a first voltage; a second power supply terminal supplied with a second voltage; a common terminal; a first resistive element of which one end is connected to one differential input terminal and another end is connected to the common terminal; a second resistive element of which one end is connected to the first supply terminal and another end is connected to the common terminal; a third resistive element of which one end is connected to one differential input terminal and another end is connected to the second supply terminal; a bonding wire, and a capacitor of which one end is connected to the second supply terminal and another end is connected to the common terminal. |
| US10396718B2 |
Bias control circuit and power amplification module
Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor. |
| US10396716B2 |
Modulated supply amplifier with adjustable input parameter configuration
An amplifier may include control circuitry that may track a first input signal parameter and, in response, adjust a value of a second input parameter. Input parameter tracking and adjustment may facilitate control of output parameters for the amplifier. For example, an envelope-tracking amplifier may track input signal amplitude and adjust other input parameters in response. The adjustments may facilitate control of output parameters, such as gain or efficiency. The amplifier may further include calibration circuitry to determine adjustment responses to various tracked input parameters. |
| US10396715B2 |
High power radio-frequency switching topology and method
Aspects and examples described herein provide a radio-frequency switching circuit, switching device, and related methods. In one example, a radio-frequency switching device includes an input path configured to receive a radio-frequency signal, a plurality of output paths each configured to provide the radio-frequency signal, and a plurality of radio-frequency sub-networks each coupled to the input path and configured to direct the radio-frequency signal, each of the plurality of sub-networks including at least a first radio-frequency circuit having a first series of directly biased transistors, a second radio-frequency circuit having a second series of directly biased transistors, and a direct current blocking network interposed between the first radio-frequency circuit and the second radio-frequency circuit, each output path of the plurality corresponding to at least one of the plurality of radio-frequency sub-networks. |
| US10396714B2 |
Reconfigurable low-noise amplifier (LNA)
A reconfigurable low-noise amplifier (LNA) is disclosed. The reconfigurable LNA includes amplifier circuitry having a gate terminal coupled to an input terminal, a source terminal coupled to a fixed voltage node, and a drain terminal coupled to an output terminal. The reconfigurable LNA further includes a gamma inverting network (GIN) coupled between the input terminal and the fixed voltage node, wherein the GIN has a first switch configured to disable the GIN during operation at first frequencies within a lower frequency band relative to a higher frequency band and to enable the GIN during operation at second frequencies within the higher frequency band. |
| US10396710B2 |
Monitoring and evaluating performance and aging of solar photovoltaic generation systems and power inverters
Techniques for detailed monitoring and evaluation of individual subsystems within solar photovoltaic power generation systems are provided. In one aspect, a method for monitoring a photovoltaic system having at least one array of photovoltaic panels and at least one inverter system configured to convert output from the panels from DC to AC includes the steps of: obtaining sensor data from the photovoltaic system; computing an efficiency of the panels and an efficiency of the inverter system using the sensor data; computing an aging parameter for the panels using the efficiency of the panels; computing an aging parameter for the inverter system using the efficiency of the inverter system; determining whether the aging parameter for the panels or for the inverter system exceeds a predetermined threshold level; and taking action if either the aging parameter for the array or for the inverter system exceeds the predetermined threshold level. |
| US10396708B2 |
Maintaining a solar power module
A solar power system includes a plurality of solar power cells mounted on an outer surface of a spherical frame, the spherical frame including an inner surface that defines an interior volume; a heat sink that includes a hollow housing mounted within the interior volume of the spherical frame; and a phase change material positioned in the hollow housing of the heat sink, the phase change material thermally coupled to the inner surface of the spherical frame to receive heat from the outer surface of the spherical frame. |
| US10396703B2 |
Solar panel float and connected member thereof
The present invention provides a solar panel float in which an increase in the number of components is prevented and which is easy to assemble. A float for mounting a solar panel is provided with: an annular float portion; a first support portion that supports an edge on one side of the solar panel; and a second support portion that supports an edge on the other side of the solar panel. The first support portion includes a first support plate portion rising from a wall surface on one side of an inner periphery of the annular float portion. The first support plate portion is formed of a cut-and-raised piece that has been cut and raised, from a flat plate portion integrally formed so as to close the inner periphery during molding of the annular float portion, using a lower-side portion of the flat plate portion as a bending-fulcrum point. |
| US10396702B2 |
Motor drive control device
A motor drive control device is a device which drives and controls a permanent magnet synchronous motor in which each phase is independently controlled, and includes a 0-axis current calculation unit which calculates and outputs a 0-axis current iz on the basis of a motor current; a 0-axis current determination unit which compares and determines a reference 0-axis current value izs, which is the 0-axis current value when the temperature of a permanent magnet provided in the permanent magnet synchronous motor is a reference temperature with the calculated 0-axis current iz; and a switching signal generation unit which drives and controls inverters on the basis of the result of comparison determination of the 0-axis current determination unit. |
| US10396700B2 |
Multi-motor system, freezer comprising the same, and methods for controlling thereof
A multi-motor system, including a plurality of ECMs. The ECMs include a main ECM and a plurality of subordinate ECMs. A first temperature detection unit and a second temperature detection unit detect a temperature T1 and a temperature T2 at different positions, respectively; the main ECM automatically selects an operation parameter according to temperature differences between the temperature T1 and the temperature T2. The main ECM informs each subordinate ECM of the temperature T1 and the temperature T2, and each subordinate ECM selects an operation parameter according to the temperature T1 and the temperature T2. In operation, the main ECM informs each subordinate ECM of the temperature T1 and the temperature T2, and each subordinate ECM selects an operation parameter in accordance with the temperature T1 and the temperature T2. |
| US10396699B2 |
Anomaly diagnosing device and anomaly diagnosing method
An anomaly diagnosing device diagnoses an anomaly in a single motor driven by multiple motor drive units. The multiple motor drive units supply AC currents to multiple multi-phase windings of the motor to drive the motor. The anomaly diagnosing device includes: a power consumption calculator for calculating power consumption in each of the multi-phase windings; a power difference calculator for calculating a difference in power consumption between the multi-phase windings; and a determination unit for determining that an anomaly is occurring when the absolute value of the difference has exceeded a threshold for a predetermined period of time. |
| US10396694B2 |
System and method for minimizing reactive current to limit rotor modulation index on a power converter
The present subject matter is directed to a system and method for operating an electrical power circuit connected to a power grid. The power circuit includes a power converter electrically coupled to a generator. The method includes monitoring at least one speed condition of the generator during operation of the power circuit. Another step includes determining one or more voltage conditions of the power circuit. The method also includes calculating a maximum reactive current for the generator as a function of at least one of the speed condition or the one or more voltage conditions. Thus, the method also includes operating the generator based on the maximum reactive current so as to prevent an actual modulation index of the power converter from exceeding a predetermined threshold. |
| US10396689B2 |
PCB-based motor starter
A PCB motor controller comprises relays mounted on a PCB and interconnected to power traces in or on the PCB to receive incoming three-phase power and to output three-phase power to a motor. Control power traces in or on the PCB connect the relays to control circuitry, also mounted on the PCB. A power supply is mounted on the PCB and connected to the control circuitry to provide power for its operation and for switching of the relays. The relays are switched in accordance with a point-on-wave (POW) switching scheme, allowing for the use or relays and the PCB, which may not otherwise be suitable for motor control applications. |
| US10396686B2 |
Converter including multiple controllable two-pole submodules connected in series
A converter comprises a plurality of controllable two-pole sub-modules connected in series. At least some of the sub-modules each comprises a first and a second sub-module connection, a first, a second, a third and a fourth controllable switch, and a storage dipole, which comprises a first and a second dipole connection, an energy store and a controllable switching device, wherein the controllable switching device has a first selectable switching state, in which the storage dipole outputs no energy, and a second selectable switching state, in which the store of the storage dipole can take up or discharge energy. The sub-module has a selectable conduction state, in which the controllable switching device of the storage dipole assumes the first switching state and the first to fourth switches are switched such that a current flows through the sub-module on two parallel branches. |
| US10396685B2 |
Modular multi-stage converter
Some embodiments may include a multi-stage converter comprising: a branch connected between a positive busbar and a negative busbar; and a control device. The branch has two arms connected in series. The arms each comprise a series circuit including a plurality of two-pole submodules, an energy store, and a communication connection to the control device. The communication connection transmits state of charge of the energy store and a switching instruction for the respective submodule. For at least a subset of the submodules, the communication connection comprises a common communication connection with a plurality of insulation paths having an insulation capability in each case of at most 5 kV. |
| US10396683B2 |
Modular multilevel converter
A Modular Multilevel Converter (MMC) includes multiple sub-modules connected in series with each other and a controller for controlling on/off switching of the sub-modules, in which the multiple sub-modules include N sub-modules that participate in the operation of the MMC and M redundant sub-modules for replacing at least one N sub-modules when the at least one N sub-modules fail, and the controller switches on a sub-module if a carrier signal assigned thereto is higher than a preset reference signal, and switches off the sub-module if the carrier signal assigned thereto is lower than the preset reference signal. |
| US10396681B1 |
Multilevel inverters with increased number of output steps
A device, method, and non-transitory computer readable medium that determines a multilevel inverter circuitry comprising Nsource DC voltage sources and at least 2Nsource+5 controlled switching devices. The number of output voltage levels and the maximum output voltage of the multilevel inverter circuitry can be variable and depend on a trade-off among voltage rating of switches, variety of DC sources, and control strategy. A hybrid modulation scheme is employed to reduce the total harmonic distortions. |
| US10396680B1 |
Direct current voltage regulation of permanent magnet generator
An aircraft power generation unit to generate direct current (DC) power provided to a load includes a permanent magnet generator (PMG) that includes first, second, third and fourth sets of windings, each of the winding sets including three windings and a rectifier section with four six pulse rectifiers the produce outputs of Vdc1 to Vdc4 respectively and a common local output bus. The unit also includes an output bus configured to be connected to the load and including a positive output bus rail and a negative output bus rail and a controller that receives an input signal from at least one of the output sets and selectively couples either the common local output bus and fourth rectifier negative rail to the output bus negative rail and one or more of the first to third six-pulse rectifiers to the output bus positive rail to provide a constant voltage to the load. |
| US10396677B2 |
Forward fed boost converter for flyback switched mode power supply and method thereof
Various embodiments relate to a flyback type SMPS including a primary side controller on a primary side, a first switch on the primary side and a transformer including a primary side winding on the primary side, a secondary side winding on a secondary side and an auxiliary winding on the primary side connected to a first switching regulator wherein the first switching regulator is supplied during a primary stroke from the auxiliary winding when the first switch is on. |
| US10396674B2 |
Flyback power converter circuit and primary side controller circuit thereof
A flyback power converter includes a transformer having a primary winding for receiving an input power, a secondary winding for generating an output power, and an auxiliary winding for generating a supply voltage, a primary side switch coupled to the primary winding, a high voltage start-up switch coupled to the input voltage and the controller supply voltage, and a primary side controller powered by the controller supply voltage. The primary side controller includes a multi-function pin coupled to a control terminal of the high voltage start-up switch, a high voltage start-up circuit for controlling the high voltage start-up switch to be ON through the multi-function pin when the controller supply voltage is lower than a threshold, and a protection control circuit which is coupled to an protection sensing signal through the multi-function pin; the protection control circuit operates the flyback power converter according to the protection sensing signal. |
| US10396670B1 |
Device and method for controlling power supply with correction behaviour in a power circuit
A device and method for controlling a power supply. The method includes: a first correction signal is generated according to a down-slope waveform and a second correction signal is generated according to an up-slope waveform, in a period of the switching element. Therefore, two kinds of corrections can be performed by using an oscillator, while the area of the circuit can be reduced and the cost of the integrated circuit can be decreased. |
| US10396669B2 |
Power converter measuring the average rectified primary current
A power converter controller and methods for its operation are provided that can control a self-oscillating power converter that uses a Bipolar Junction Transistor (BJT) as a switch by manipulating the current flowing in a control winding. The controller is able to determine the optimum time to remove a short circuit applied to the control winding, as well as being able to determine the optimum time to pass current through the control winding. The controller can further draw power from the power converter using the control winding. The controller is capable of maintaining the midpoint voltage of the power converter in the case that the converter has more than one switch. The controller estimates the output power of the converter without requiring a connection to the secondary side of the converter transformer. The controller further controls entry and exit into a low-power mode in which converter oscillations are suppressed. |
| US10396668B1 |
Power converter
A power converter disclosed herein may include power conversion circuits connected in parallel and a cutoff switch provided in each of the power conversion circuits. The cutoff switch may be configured to cut off connection of corresponding one of the power conversion circuits from other power conversion circuit. In the power converter disclosed herein, the cutoff switches of the power conversion circuits may be housed in a first module. |
| US10396667B2 |
DC-DC converter including an intermittent overcurrent protection circuit
There is provided a DC-DC converter which is safe and secure, but yet with low power consumption. The DC-DC converter is configured such that an overcurrent protection circuit is operated intermittently only for a predetermined period of time based on a signal output from an output control circuit to turn on a switching element. |
| US10396666B1 |
Systems and methods for adjusting one or more thresholds in power converters
System controller and method for a power converter. For example, the system controller includes a first current controller configured to receive a first input signal and generate a first output signal based at least in part on the first input signal, a second current controller configured to receive a compensation signal and a second input signal and generate a second output signal based at least in part. on the second input signal, and a drive signal generator configured to receive the first output signal and the second output signal, generate a first drive signal based at least in part on the first output signal and the second output signal, and generate a second drive signal based at least in part on the first output signal and the second output signal. |
| US10396665B2 |
On-chip DC-DC power converters with fully integrated GaN power switches, silicon CMOS transistors and magnetic inductors
Fully integrated, on-chip DC-DC power converters are provided. In one aspect, a DC-DC power converter includes: a SOI wafer having a SOI layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one first portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one GaN transistor formed on the substrate in the first portion of the SOI wafer; at least one CMOS transistor formed on the SOI layer in the second portion of the SOI wafer; a dielectric covering the GaN and CMOS transistors; and at least one magnetic inductor formed on the dielectric. A method of forming a fully integrated DC-DC power converter is also provided. |
| US10396662B2 |
Direct current link circuit
A device for converting power from a floating source of DC power to a dual direct current (DC) output, the device includes: positive and negative input terminals connectable to the floating source of DC power; and positive and negative, and ground output terminals connectable to the dual DC output that may feed an inverter. The inverter may be either a two or three level inverter. A charge storage device may be connected in parallel to, and charged from, the positive and negative input terminals. A resonant circuit may be also connected between the charge storage device and the dual DC output. The resonant circuit may include an inductor connected in series with a capacitor. The charge storage device may discharge through the resonant circuit by switching through to either the negative output terminal or the positive output terminal. |
| US10396661B2 |
Power supply control apparatus
In a power supply control apparatus, when a semiconductor switch is switched ON, a charging circuit increases a base voltage. A first switch is ON if a differential voltage obtained by subtracting a gate voltage from a base voltage is at least a first reference voltage, and is OFF if the differential voltage is smaller than the first reference voltage. If the first switch is ON, a battery or a capacitor charges parasitic capacitors of the semiconductor switch. |
| US10396649B2 |
Switching device and switching apparatus including the same
A switching device for stabilizing an electric output of a solar panel is provided, and includes a voltage converter circuit, a switch circuit connected between the solar panel and the voltage converter circuit, and a control unit. The voltage converter circuit converts input voltage and current received from the solar panel through the switch circuit into output voltage and current. The control unit calculates an input electric power and an output electric power based on values of the input voltage and current and values of the output voltage and current, and controls the switch circuit to switch between a closed state and an open state according to the input electric power and the output electric power. |
| US10396640B2 |
Blower with bearing tube
A method for forming windings of a stator assembly in a blower includes providing a stationary portion for the blower including a tube adapted to support a rotor and using the tube as a mandrel to form the windings of the stator assembly. |
| US10396637B2 |
Electric motor and radiator fan module comprising an electric motor of this type
The present invention relates to an electric motor, the electric motor including: a stator, which is composed of layered metal sheets, a motor support made of an electrically conductive material, a cable connection comprising an earth line cable, and at least one connecting and contacting element made of an electrically conductive material, wherein the connecting and contacting element is configured and arranged on the electric motor such that it provides an earth connection between the stator and the motor support or between the stator and the earth line cable of the cable connection, and wherein the stator and the motor support are fastened to one another independently of the connecting and contacting element. |
| US10396630B2 |
System and method for cooling windings of generator rotor
A system for cooling windings of generator rotor is presented. The system includes a cooling passage including inlet and outlet radial bores radially extending into rotor shaft extension, inlet and outlet axial bores axially extending within rotor shaft extension, first and second radial bores radially extending from cavities under two retaining rings into rotor shaft extension, and an axial passage through windings from cavity under retaining ring at turbine end side to cavity under retaining ring at excitation end side. A coolant flows through the cooling passage and directly cools windings by traveling through entire windings. The system uses non-explosive fluid as coolant eliminating using hydrogen as coolant and provides sufficient direct cooling of windings of a high power density generator rotor without extensive piping. |
| US10396625B2 |
Protector for preventing motor damage
A protector for preventing motor damage is revealed. The protector includes a link member linked to a driving part of a motor and having a mounting groove and a first insertion hole, an elastic damping member that is placed in the mounting groove and disposed with a second insertion hole, and a driver member arranged with a projecting block and used for driving a passive member. One surface of the driver member is covered on the mounting groove to form a receiving space. The projecting block is mounted in the second insertion hole whose inner edge is closely attached to an outer edge of the projecting block. The damping member is compressed in the receiving space so that an outer edge thereof is tightly attached to an inner edge of the mounting groove and the driver member. Thereby the motor operates normally no matter the passive member is locked. |
| US10396624B2 |
Electromagnetic torque motor with high torque and limited angle
The torque motor as disclosed depends on decreasing the gap between a surface on a fixed part and a corresponding inclined facing surface on a rotating part, where the gap width is proportional to its distance from the angle vertex, in magnifying the electromagnetic force and its resulting torque. Therefore, the surface on the fixed part starts directly at—or close to—a point in align with the rotating part center of rotation, and hence the gap width is minimum at the start point and increases away from this point due to the inclination angle. The motor includes features, such as, utilizing many pairs of facing surfaces, many electromagnetic circuits; arrange the surfaces in pairs for balanced forces, works in one or two directions, the two directions electromagnetic circuits installed in one or two levels, and precautions and ways to avoid magnetic field interference and leakage. |
| US10396623B2 |
Motor shaft, motor and motor assembly
A motor includes: a motor shaft including a press-fitting surface; and a first annular projection group and a second annular projection group formed in the press-fitting surface of the motor shaft. The first annular projection group and the second annular projection group are separated from each other in an axial direction, a distance between an adjacent two of annular projections in the first annular projection group and a distance between an adjacent two of annular projections in the second annular projection group are smaller than a distance between the first annular projection group and the second annular projection group in the axial direction. |
| US10396621B2 |
Electric compressor
An electric compressor includes a compression mechanism that compresses refrigerant, an electric motor that drives the compression mechanism, a drive circuit that drives the electric motor, a housing that forms therein a motor chamber in which the electric motor is accommodated, a cover that is attached to the housing, a rotary shaft, and a relay terminal portion. The cover is configured to cooperate with the housing to form a drive circuit chamber in which the drive circuit is accommodated. Rotation of the electric motor is transmitted to the compression mechanism through the rotary shaft. The relay terminal portion provides electrical connection between a wire of the drive circuit and a wire of the electric motor. The housing includes a partition wall that separates the motor chamber and the drive circuit chamber from each other. The relay terminal portion is disposed between the partition wall and the rotary shaft. |
| US10396620B2 |
Rotating electrical machine connection component and method of manufacturing the same
A rotating electrical machine connection component includes a plurality of linear conductors, and a first molded resin portion that covers portions of the plurality of linear conductors and connects the plurality of linear conductors to each other. Each of the plurality of linear conductors includes a first straight portion extending out of the first molded resin portion in a direction parallel to a rotational axis of the rotor and connected to the terminal block, a second straight portion extending out of the first molded resin portion in a different direction from the first straight portion and a bent portion bent between the first and second straight portions. Of each of the plurality of linear conductors, a part of the first straight portion, the bend portion and a part of the second straight portion are covered by the first molded resin portion. |
| US10396619B2 |
Electric motor
An electric motor includes a conductive shaft extending along an axis of rotation and passing through a back yoke to be fixed to one of a stator and a rotor. At least one bearing includes a conductive inner ring fixed to the shaft and a conductive outer ring rotatably coupled to the inner ring. A conductive bearing housing extends so as not to be located in a first area at one side with respect to the stator along an axial direction extending along the axis of rotation but to be located in a second area at the opposite side along the axis direction. The bearing housing is fixed to the outer ring of the bearing and to the other of the stator and the rotor. An electric motor is configured to be oppositely spaced from a plate electrically grounded in the axial direction. |
| US10396617B2 |
Electronically commutated direct current motor with individual terminals and plastic parts
An electronically commutated direct current motor with a housing, a housing cover, a bearing shield, a rotor and a stator, wherein the rotor includes a shaft and a permanent magnet and the stator consists of single terminals, which are provided with terminal insulation. The direct current motor ensures a space-saving construction connection of motor components or components with the housing of the electronic commutated direct current motor, conforming to its class, wherein additional connections or sealing elements are not required, wherein a firm and sealed connection can be manufactured upon demand and an easy integration of other functions and interfaces is possible. |
| US10396616B2 |
Electric motor and switching unit therefor
An electric motor has a switching unit with a number of contact wires and an annular frame part. The contact wires are arranged to form an interconnect ring for the coil ends of a stator winding and the ends of the wires being connected by insulation displacement contacts. Each of the contacts have two insulation displacement limbs for connecting at least two of the wire ends, the limbs being spaced apart, thus forming an insulation displacement slot therebetween. The frame part of the switching unit has a number of plug-in pockets for receiving the insulation displacement contacts, the number corresponding to the number of insulation displacement contacts. |
| US10396615B2 |
Electric machine stator lamination with dual phase magnetic material
A stator lamination for an electric machine has a circular lamination with an annular bore therethrough; winding slots therethrough; and, slot closures disposed adjacent to the winding slots. The stator lamination is formed of a dual magnetic phase material, such that the magnetic property of the lamination can have a first state and a magnetic property in a second state, wherein the second state is different than the first state. The slot closures regions are treated so as to transition to the second state. A method of manufacturing an electric machine component is also disclosed. |
| US10396614B2 |
Rotating electrical machine stator
A stator of a rotating electrical machine includes: a plurality of annularly arranged stator cores; a stator winding attached to slots of the stator cores; and a shell (22) that retains the stator cores. In the stator of the rotating electrical machine, the ends of coil terminal wires (19), (20) on the innermost circumferential side and the outermost circumferential side of each slot are oriented in the axial direction of the stator; and side surfaces of the ends of the terminal wires (19), (20) are brought into contact with each other and are welded above the coil end (21) of the stator winding. |
| US10396610B2 |
Laminated core arrangement and electric machine with such a laminated core arrangement
A laminated core arrangement for an electric machine includes a laminated core having at least two part cores which are arranged in an axial direction. Each of the part cores has a plurality of polygonal individual sheets, with at least one of the individual sheets being round and disposed between the part cores. The at least one round individual sheet has a diameter which is less than or equal to an inner circle of the polygonal individual sheets. Permanently-excited magnets are disposed around a circumference of the laminated core. |
| US10396609B2 |
Permanent magnet-embedded type rotary electric machine with rotor having slots and rotor surface grooves
Magnetic flux short-circuit preventing slits extend from opposite ends of two permanent magnets in an outer circumferential surface of a rotor toward a center of a magnetic pole. Grooves formed in the outer circumferential surface can be located at a distance from each other symmetrically with respect to the center of the magnetic pole and at a distance from a groove of an adjacent magnetic pole in the outer circumferential surface. Relations are established as θf=n×τs and θs=n×τs where τs designates a pitch of stator winding slots, which pitch is converted into an angle around a rotation center, θf designates an angle between the magnetic flux short-circuit preventing slits, θs designates an angle between the grooves, and n designates a predetermined integer. Thereby, a permanent magnet-embedded type rotary electric machine in which the influence of a manufacturing error can be minimized so that cogging torque can be reduced stably. |
| US10396606B2 |
Systems and methods for wirelessly powering or communicating with sterile-packed devices
Systems and methods are disclosed herein that can allow for wirelessly powering and/or communicating with a sterile-packed electronic device without removing the electronic device from its sterile packaging and while maintaining the sterility of the electronic device. In some embodiments, a base station with a power transmitter wirelessly transfers power to a power receiver of the electronic device, for example using inductive, capacitive, or ultrasonic coupling. The base station or another external device can also be used to wirelessly program or interrogate the electronic device. Battery charging circuits and switching circuits for use with said systems and methods are also disclosed. |
| US10396603B2 |
Power receiving apparatus that wirelessly receives power, control method of the same, and storage medium
A power receiving apparatus that is capable of communicating with a power transmitting apparatus with wireless power transmission capability, the power receiving apparatus comprises: a detection unit configured to detect a state of the power receiving apparatus; a communication unit configured to, in order to establish connection to other apparatuses including the power transmitting apparatus, transmit information indicating an existence of the power receiving apparatus to the other apparatuses, or receive information indicating an existence of the other apparatuses from the other apparatuses; and a control unit configured to control transmission and reception of the information, wherein in order to enable establishment of connection to the power transmitting apparatus, the control unit switches between transmission and reception of the information based on whether the state of the power receiving apparatus is a predetermined state. |
| US10396601B2 |
Piecewise RF power systems and methods for supplying pre-distorted RF bias voltage signals to an electrode in a processing chamber
A radio frequency power system is provided that includes bias modules, a switch, a matching network, and a control module. The bias modules are configured to generate respectively DC bias voltages. The switch is configured to (i) receive current from the bias modules, and (ii) control flow of the current from the bias modules to generate a radio frequency bias voltage signal. The matching network is configured to (i) receive the radio frequency bias voltage signal, and (ii) based on the radio frequency bias voltage signal, supply at least a portion of a radio frequency output voltage signal to an electrode of a substrate support in a processing chamber. The control module is connected to the switch and configured to control a state of the switch based on the radio frequency output voltage signal to shape a waveform of the radio frequency bias voltage signal. |
| US10396600B2 |
Power transmitter, resonance-type contactless power supply and control method therefor
A resonance-type contactless power supply adjusts a phase difference of an inverter control signal in a current cycle in a manner the same as that in a previous cycle in a case that a power parameter in the current cycle and that in the previous cycle satisfy a predetermined relationship, and adjusts the phase difference of the inverter control signal in the current cycle in a manner opposite to that in the previous cycle in a case that the power parameter in the current cycle and that in the previous cycle don't satisfy the predetermined relationship. The power parameter represents system efficiency. Thus, a suitable input current or voltage of the transmitter-side resonant circuit is determined by scanning actually, so that the system can operate at optimal efficiency. |
| US10396598B2 |
Methods and apparatus for wireless power and communication transfer
An aspect of this disclosure is an apparatus for receiving power wirelessly. The apparatus comprises a power receiver circuit that receives power from a magnetic field of a transmitter to provide to a load. At least one receiver component is coupled with the power receiver circuit and operates based on at least one operation parameter. A sensor measures at least one of a current and a voltage at the load. A controller estimates a first voltage induced by the magnetic field based on the at least one measured current and measured voltage and the at least one operation parameter. The controller also estimates a second voltage based on the at least one operation parameter, the second voltage corresponding to a voltage at which the power receiver circuit operates with an efficiency level that exceeds a threshold efficiency. The communication circuit communicates the estimated voltages to the transmitter. |
| US10396597B2 |
Driving circuit and wireless power transmitter including the same
The present disclosure relates to a driving circuit and a wireless power transmitter including the same. In view of the fact that a transmitter-side coupling circuit exhibits a high resistance when an AC current having a frequency far away from its operating frequency is applied to input terminals, the present disclosure connects a plurality of transmitter-side coupling circuits which operates at different operating frequencies in parallel at output terminals of the same inverting circuit. The controller controls an operating frequency of the AC current output from the inverting circuit to drive different one of the transmitter-side coupling circuits to operate. Thus, one driving circuit can drive the transmitter-side coupling circuits which operate at different operating frequencies or under different technical standards to supply electric energy. The driving circuit is compatible with wireless power receivers which operate at different operating frequencies, and thus has improved compatibility. |
| US10396594B2 |
Single phase power factor correction system and method
A single phase grid correction system for correcting the power factor of an electrical power grid. The grid has a generator, transmission lines connecting the generator to distribution nodes, feeder lines radiating from each node, and groups of consumers connected to each feeder line. A capacitor bank is located at a number of consumer's premises, indoors, either beside or forming part of the consumer's normal single phase electric panel. A set of remotely controlled switches at the consumer's premises permits the capacitor banks to be switched in and out of grid connection and also allows non-essential high energy consuming loads, not necessarily inductive, to be switched on and off the grid. The grid correction systemic are widely distributed at consumer's premises throughout the grid. By remotely controlling the switches, the utility operator can switch capacitor banks at selected consumer premises in or out of the grid to provide or remove reactive power as needed, and can also selectively remove load from the grid to reduce the likelihood of sudden uncontrollable load shedding. |
| US10396591B2 |
Standby control circuit and operating method thereof, playing apparatus
The present disclosure discloses a standby control circuit and an operating method thereof, and a playing apparatus. The standby control circuit includes a controller and a standby power supply, the controller is configured to transmit a power-on signal to enable the playing apparatus to enter into a power-on state, the controller is further configured to transmit a standby signal to enable the playing apparatus to enter into a standby state, and the standby power supply is configured to supply power to a micro control unit of the playing apparatus under the condition that the playing apparatus is in the power-on state and stop supplying power to the micro control unit of the playing apparatus under the condition that the playing apparatus is in the standby state. |
| US10396588B2 |
Receiver for wireless power reception having a backup battery
The present disclosure provides devices and methods for wireless power transmission. These devices and methods may extend the battery life of electronic devices such as tablets, smartphones, Bluetooth headsets, smart-watches among others. An example method may include, when a receiver coupled to an electronic device is within a threshold distance from a transmitter: (i) receiving a plurality of wireless power transmission waves transmitted by the transmitter, (ii) converting the plurality of wireless power transmission waves into usable electricity, and (iii) providing the usable electricity to a backup battery of the receiver to at least partially charge the backup battery. Further, when the receiver is not within the threshold distance from the transmitter, and after providing the usable electricity to the backup battery to at least partially charge the backup battery, draining the backup battery to provide power to the battery of the electronic device. |
| US10396585B2 |
Universal inductive charging system for a portable electronic device
Disclosed is an inductive charging system for a portable electronic device, the system incorporating at least one induction coil and having a receiving face for the application of the device including a receiving coil positioned on the receiving face in electromagnetic contact with the induction coil. The receiving face includes multiple series of tabs defining at least discontinuously a perimeter corresponding to the device, the tabs of each series projecting from the receiving face in a first position being movable from the first position to a second position in which each tab is retracted into the receiving face under an application of a force corresponding to that exerted on this tab by the device when applied against the receiving face. |
| US10396579B2 |
GaN circuit drivers for GaN circuit loads
An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node. |
| US10396573B2 |
Portable battery pack charging system, method for recharging a battery pack, and adapter therefor
A method for recharging a battery pack (40; 40′) includes attaching a portable charger (120) to a user, which portable charger comprises or is attached to a self-contained power supply (130, 140) and wherein a first charging port (132, 146) of the portable charger is disposed, e.g., on a belt (144) worn by the user, hanging the battery pack on the belt while the battery pack is physically engaged and in electrical communication with a power tool (10; 10′), and initiating a transfer of power from the charger to the battery pack when the first charging port is at least proximal to a second charging port (85, 148) that is in electrical communication with at least one battery cell (50) of the battery pack. A portable charging system capable of performing this method, as well as an adapter for use in performing this method, are also disclosed. |
| US10396572B2 |
Power transmission device and power transmission method
A power transmission device includes: a power reception unit that receives electric power from outside; a power transmission line that transmits the electric power received with the power reception unit to a battery; a transmission cut-off switch that cuts off the power transmission line, a transmission control circuit that uses the electric power received in the power reception unit as operation power, receives a battery state signal indicating a state of the battery, and switches conduction and non-conduction of the transmission cut-off switch on the basis of the battery state signal; and a cut-off control circuit that monitors the received electric power from the power reception unit by receiving electric power from the battery, and forcibly puts the transmission cut-off switch in a non-conductive state when the received electric power is less than a specified value. |
| US10396571B2 |
Adaptive overvoltage protection for adaptive power adapters
A power adapter includes a protocol integrated circuit (IC) on a secondary side of a transformer and a controller IC on a primary side of the transformer. The power adapter has an output voltage that changes depending on the charging voltage requirement of an electronic device (e.g., mobile device) connected to receive power from the power adapter. The power adapter includes an adaptive overvoltage protection mode that sets an overvoltage protection threshold to a low level during startup and thereafter sets the overvoltage protection threshold to a higher level after detecting proper operation of the protocol IC. |
| US10396568B2 |
Battery charger with user interface
A battery single charger may accommodate Li-type and Ni-type batteries, having default charge settings and user-adjustable charge parameters in an ‘advanced mode’. Lithium Polymer (LiPo) batteries equipped with RFID technology and integrated balance taps may communicate with a device such as a battery charger equipped with similar technology providing information such as chemistry type, cell count, recommended charge rates, number of charges on the battery, among other types of information. Several safety features may be included. |
| US10396564B2 |
Electric power transmission system including modulators and demodulators, and controller
A system includes: a first modulator that modulates a first electric power at a first modulation frequency; a second modulator that modulates a second electric power at a second modulation frequency; a transmission line through which a transmission power obtained by combining a plurality of modulated electric powers is transmitted; a first demodulator that demodulates the transmission power at a first demodulation frequency to generate a third electric power; and a second demodulator that demodulates the transmission power at a second demodulation frequency to generate a fourth electric power. The first modulation frequency and the second modulation frequency are different from each other. |
| US10396563B2 |
Renewable energy load management and power balancing system and operation
A system and process of its operation for monitoring and managing load circuits connected to a renewable energy generation system are disclosed. A programmable load manger circuit continuously monitors the available energy from the generation system and manages the load circuits connected to the system in a manner such that the energy demand from the active load circuits is below the level of available energy. The load circuits can be prioritized and programmed such that the lower priority loads are deactivated prior to the higher priority loads when the available energy from the generation system is not sufficient to satisfy demand from all the active load circuits. When the renewable energy generation system incorporates more than one generator, a load balancing control algorithm, continuously monitoring the load connected to the system and allocates the load in a balanced manner to each of the generators in the system. |
| US10396558B2 |
Surge suppression system for medium and high voltage
A system of surge suppressor units is connected at multiple locations on a power transmission and distribution grid to provide grid level protection against various disturbances before such disturbances can reach or affect facility level equipment. The surge suppressor units effectively prevent major voltage and current spikes from impacting the grid. In addition, the surge suppressor units included various integration features which provide diagnostic and remote reporting capabilities required by most utility operations. As such, the surge suppressor units protect grid level components from major events such as natural geomagnetic disturbances (solar flares), extreme electrical events (lightning) and human-generated events (EMPs) and cascading failures on the power grid. |
| US10396554B2 |
Power distribution control within a modular converter system using efficiency calculations
A method is disclosed for controlling power distribution from a plurality of inverters to one or more loads. The method comprises determining, using one or more computer processors, a plurality of possible combinations of the plurality of inverters to meet load demands corresponding to the one or more loads. Each possible combination of the plurality of possible combinations includes a respective set of one or more inverters of the plurality of inverters. The method further comprises accessing, from a memory coupled with the one or more computer processors, one or more predefined efficiency functions associated with the one or more inverters; selecting, based on the one or more predefined efficiency functions, a combination from the plurality of possible combinations; and transmitting control signals to the set of one or more inverters corresponding to the selected combination to thereby power the one or more loads. |
| US10396552B2 |
Sequentially operated modules
Method, modules and a system formed by connecting the modules for controlling payloads are disclosed. An activation signal is propagated in the system from a module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to external power source such as AC power. The system may use remote powering wherein few or all of the modules are powered from the same power source connected to the system in a single point. The power may be carried over dedicated wires or concurrently with the conductors carrying the activation signal. The payload may be a visual or an audible signaling device, and can be integrated within a module or external to it. The payload may be powered by a module or using a dedicated power source, and can involve randomness associated with its activation such as the delay, payload control or payload activation. |
| US10396549B2 |
Semiconductor device
Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor. |
| US10396546B2 |
Residual current protection device
A residual current protective device for an electric circuit having at least one electrical consumer comprises a residual current determination component, a leakage current determination component and an interruption component. The residual current determination component is configured to determine an amperage difference between the amperage of a current flowing to the at least one electrical consumer and the amperage of a current flowing from the at least one electrical consumer. The leakage current determination component is configured to determine the amperage of a leakage current flowing out of the electric circuit to earth (ground). The interruption component is configured to interrupt the electric circuit if the difference between the determined amperage difference and the determined amperage of the leakage current exceeds a preset limit value. |
| US10396545B2 |
Insulation monitoring device having voltage monitoring and underlying method
The invention relates to an insulation monitoring device and to a method for conforming-to-standards monitoring of an insulation resistance of an ungrounded single-phase or multi-phase power supply system having at least two active conductors. According to the invention, the insulation monitoring device comprises a voltage monitoring circuit for permanently registering the conductor voltage to ground potential for at least one active conductor. If an excess voltage is detected on an active conductor, the voltage monitoring circuit generates a shut-down signal so as to shut down the power supply system. |
| US10396539B2 |
Modular cable protector
A plurality of modular cable protectors can be removably connected in series by complementary end connectors at each end. Each cable protector also includes a number of tool engagement features that that can be removably engaged by a tool that enables a user to exert an upward force to disengage the end connectors on adjacent cable protectors. For example, the tool engagement features can be slots in the top surface of the cable protector with undercuts adjacent to the lower ends of the slots. A tool with vertical rods is manually inserted into the slots to disengage the cable protectors. Horizontal projections at the bottom of the vertical rods engage the undercuts in the slots, and allow the user to disengage adjacent cable protectors by lifting upward on the tool. |
| US10396536B2 |
Tool used for connecting busbars
The invention relates to an electric device, especially to a tool used for connecting busbars, said tool comprises an electric motor driving unit and an electric control unit; said tool further comprises a stationary portion removably connects to a busbar, a movable portion removably connects to a busbar and a loading portion for clamping connecting rods. Said movable portion is movably connected to a first and second stationary shaft of said stationary portion, said movable portion is connected to a movable shaft by a screw pair, said movable portion is fixedly connected to said electric motor driving unit, said movable shaft is driven to rotate around its axis by said electric motor driving unit, said loading portion is movably connected to said second stationary shaft and slides between a body of said stationary portion and a body of said movable portion, said loading portion rotates around said second stationary shaft. It is achieved that a plurality of connecting rods are simultaneously mounted to busbars and that two busbars are connected in a form of butt-and-butt connecting. |
| US10396533B1 |
Containerized power flow control systems
A containerized power flow control system is described, for attachment to a power transmission line or substation. The system includes at least one container that is transportable by road, rail, sea or air. A plurality of identical impedance injection modules is operable while mounted in the container, wherein each of the modules is configurable to inject a pre-determined power control waveform into the power line. |
| US10396532B1 |
Contact device for transmitting electrical energy
The present invention relates to a contact device for transmitting electrical energy from a preferably spatially fixed bus bar to a tap-off device which is movable along the bus bar or is likewise spatially fixed. For this purpose, the sliding contact elements are configured in the form of sliding clip elements so that the connecting housing of the contact device is clippable onto the bus bar without using tools. |
| US10396531B2 |
Frame profile for a frame rack of a switch cabinet, and a corresponding frame rack
The invention relates to a frame profile for a frame rack of a switch cabinet, wherein the frame profile has: a first and a second profile web, wherein a free end of the first profile web has a first sealing edge, and a free end of the second profile web has a second sealing edge, a first mounting side with fixing receptacles, which first mounting side is spaced apart from the first sealing edge by a first dimension of a first connecting side of the first profile web, which connects the first mounting side to the first sealing edge, a second mounting side with fixing receptacles, which second mounting side is spaced apart from the second sealing edge by a second dimension of a second connecting side of the second profile web, which connects the second mounting side to the second sealing edge, characterized in that at least one of the profile webs has an undercut. |
| US10396529B2 |
VCSELs having mode control and device coupling
A VCSEL can include: an active region configured to emit light; a blocking region over or under the active region, the blocking region defining a plurality of channels therein; a plurality of conductive channel cores in the plurality of channels of the blocking region, wherein the plurality of conductive channel cores and blocking region form an isolation region; a top electrical contact; and a bottom electrical contact electrically coupled with the top electrical contact through the active region and plurality of conductive channel cores. At least one conductive channel core is a light emitter, and others can be spare light emitters, photodiodes, modulators, and combinations thereof. A waveguide can optically couple two or more of the conductive channel cores. In some aspects, the plurality of conductive channel cores are optically coupled to form a common light emitter that emits light (e.g., single mode) from the plurality of conductive channel cores. |
| US10396528B2 |
Laser device and methods for manufacturing the same
Provided is a laser device according to an embodiment of the inventive concept. The laser device includes: a semiconductor substrate; a germanium single crystal layer on the semiconductor substrate; and a pumping light source disposed on the germanium single crystal layer and configured to emit light toward the germanium single crystal layer, wherein the germanium single crystal layer receives the light to thereby output laser. |
| US10396526B2 |
Display apparatus
A display apparatus is provided. The display apparatus is a retinal scanning type display apparatus, and includes a low output laser whose operational current is less than that of a standard output laser; a shunting element that is connected in parallel with the low output laser; and a drive circuit that supplies a current to the low output laser and the shunting element. The drive circuit is a drive circuit for the standard output laser capable of adjusting a current value on a discrete basis in a range of an operational current that is higher than the operational current of the low output laser. |
| US10396521B2 |
Laser
A laser includes a traveling wave laser cavity with an active section, a pulse stretcher, and a pulse compressor. The pulse stretcher is coupled to the waveguide before the active section and the pulse compressor is coupled to the waveguide after the active section. |
| US10396517B1 |
Tapping apparatus for transmitting electrical energy
The invention relates to a tapping apparatus for transmitting electrical energy from a, preferably spatially fixed, busbar to a tapping device which can be moved along the busbar or is also spatially fixed, comprising at least one connection housing, the busbar being mechanically connected or connectable to the tapping device by means of the connection housing, and a current tapping apparatus which comprises sliding contact elements for collecting electrical energy from the busbar, the current tapping apparatus being mechanically rigidly connected to the connection housing, and furthermore the connection housing comprising at least one base support, on which at least two control circuit boards are mounted, or said two control circuit boards themselves forming the base support. |
| US10396514B2 |
Power distribution unit retention device
The present disclosure is directed to a PDU retention device comprising a rectangular frame having a central cutout portion, a first protrusion extending from the frame into the cutout portion, a guidance fixture permitting the frame to move along a path, and a second protrusion extending from the frame away from the central cutout portion. |
| US10396503B2 |
Differential connector and housing component thereof
The present invention relates to the field of electrical connectors, and in particular to a differential connector and a housing component thereof. The differential connector comprises a housing component and two or more differential modules. Each differential module comprises an insulator, differential pairs and ground contacts. The housing component comprises a housing. A plugging hole corresponding to a plug-in end of the differential pair is provided on the housing. An end shield corresponding to the plug-in end of the differential pair is provided on the housing. The end shield is provided with a shield groove extending along a plugging direction of the plug-in end of the differential pair. Openings of shield grooves face toward the same direction. The plug-in end of the differential pair is provided in the shield groove so as to be isolated from a plug-in end of an adjacent differential pair of the same differential module. |
| US10396499B1 |
Electric connector
An electric connector includes an insulating body which includes terminal slots formed in an abutting chamber inside thereof, and the abutting part includes two arms extended from two opposite rear sides thereof in the same direction, and an accommodation space formed between the two arms; and, a terminal holder integrally formed with the conductive terminals of the terminal set is combined between the two arms, and each conductive terminal has a predetermined length, and includes a contact part inserted through the terminal slot and into the abutting chamber, a solder part disposed behind the contact part and exposed to the accommodation space, and a terminal arm with a given length formed between the contact part and the solder part. The length of the solder part is lower than the length of each arm. The solder parts can be electrically connected to an abutting side of a signal transmission part. |
| US10396498B2 |
Power adapter
A power adapter, comprising an adapter body, a power cord and a snap-fitting cover, the adapter body is provided with a socket, the power cord is provided with a plug plugged in and connected with the socket, and the snap-fitting cover includes the snap-fitting portion and the fixing portion, the fixing portion is movably connected to the end of the adapter body, the snap-fitting portion is provided with a groove which is shapely matched with the plug, and a groove is snap-fitted to the outer side of the plug. The snap-fitting cover is connected with the plug and the adapter body at the same time to retain the plug and the adapter body, and the plug is not easily disengaged from the socket of the adapter body under the external forces, thereby making the use of the power adapter more stable and reliable. |
| US10396496B2 |
Connector
The present invention relates to a connector, in particular plug connector, for the releasable connection of two lines along a connector axis, having a line, a connection mechanism which has a sleeve and a drag element, and a holding element for holding a counterpart connector to be connected, wherein the sleeve is displaceable over the drag element, the holding element and over the line, wherein the drag element and the sleeve are each displaceable between a first position and a second position along the connector axis and the sleeve is designed to actuate the drag element, by means of an axial displacement of the sleeve, in order to connect the connector to, or release the connector from, a counterpart connector. |
| US10396488B2 |
System consisting of a plug connector module frame and adapter elements
The invention relates to a system consisting of a plug connector module frame with a plurality of latching elements along two module frame side walls for fastening contact carrier modules, which have a mating latching geometry corresponding to the latching elements, and one or more adapter elements, for toolless fastening to the module frame side wall or walls, in order to fasten thereto contact carrier modules with a mating latching geometry which does not correspond to the latching elements, i.e. is different therefrom. |
| US10396483B2 |
Terminal and connector for connecting board including the same
The present disclosure relates to a terminal capable of preventing deformation due to a load applied upon being in contact with a board, and the terminal includes a body, and a contact positioned inside the body and being in contact with the strip of the board. The contact includes a first bending portion bent backwardly from the front end of the body and elastic-deformed when being in contact with the board, a first inclined portion extending backwardly from the first bending portion, a second bending portion bent forwardly from a rear end of the first inclined portion and being in contact with the board, a second inclined portion extending forwardly from the second bending portion, and a support portion bent at a front end of the second inclined portion and limiting the deformation of the first bending portion when being in contact with the body. |
| US10396477B2 |
Fastening device for connector in automotive light equipment
A fastening device to maintain a connector engaged in an electronic assembly, the fastening device including a body, a first clip member that engages in a first opening, the first clip member having a first shank that protrudes substantially perpendicularly from the body, and a first arm that protrudes the first shank towards the body, a second clip member that engages in a second opening, the second clip member having a second shank that protrudes substantially perpendicular from the body, and a pair of second arms that protrudes from the second shank towards the body, and a head affixed to the body that contacts the connector and maintains the connector engaged in the electronic assembly. |
| US10396475B2 |
Vice-type terminal block for interconnecting two thimbles and associated connection
A vice-type terminal block for electrically connecting a pair of lugs by clamping them together. Each lug includes a barrel extending along an axis and a radially extending flange connected to the barrel. The flange has, on the opposite side to where the barrel is located, an electrical contact surface normal to the axis. The vice-type terminal block includes two opposing plates and a clamping system. Each plate includes a slot for receiving one of the lugs such that the flange of the lug is on one side of the plate, whereas the barrel is on the other side. The pair of lugs are supported such that their electrical contact surfaces face one another and are aligned. |
| US10396473B2 |
Battery terminal connector with different shapes for positive and cable and negative cable
A battery terminal connector includes a clamp with extended arms to engage with varying size of terminal post of a battery. A connector extending from the clamp has either a protruded or hollow end depending on whether the clamp is engaged with a positive or negative terminal. A cable connecting a terminal of an external device is shaped to accommodate the connector to supply current to the external device from the battery. The battery terminal connector providing a connecting and cable shaped differently depending on whether it is connected to a positive or negative terminal post of the battery reduces accidents caused by mistakenly cross connecting a positive terminal of the battery to a negative terminal of the external device, and vice versa. |
| US10396472B2 |
Crimped and welded connection
A method for producing a permanent mechanical and electrical connection between a stranded wire and a connecting element, one end of the stranded wire being welded to the connecting element, the end of the stranded wire being introduced into a crimping recess of the connecting element prior to welding, and the connecting element being additionally crimped with the stranded wire. Crimped welded joints produced using this method are taught. |
| US10396469B1 |
Method for manufacturing three-dimensional electronic circuit
An electronic circuit is made by selectively depositing an electrically conductive material seed layer conformally upon a three-dimensional substrate via the plurality of apertures of a three-dimensional mask. The substrate is then plated with more of the same electrically conductive material, or a different electrically conductive material, on the seed layer. In the case of electroplating, a nonconductive support structure is incorporated into a conductive clamp for making electrical connection to the seed layer. An environmentally protective layer may be deposited upon the electrically conductive material to such an extent that the electronic circuit remains solderable. The three-dimensional mask may be fabricated by an additive manufacturing technique. |
| US10396468B2 |
Antenna having increased side-lobe suppression and improved side-lobe level
An embodiment of an antenna includes first and second transmission lines, first antenna elements, and second antenna elements. The first transmission line is configured to guide a first signal such that the first signal has a characteristic of a first value, and the second transmission line is configured to guide a second signal such that the second signal has the same characteristic but of a second value that is different than the first value. The first antenna elements are each disposed adjacent to the first transmission line and are each configured to radiate the first signal in response to a respective first control signal, and the second antenna elements are each disposed adjacent to the second transmission line and are each configured to radiate the second signal in response to a respective second control signal. Such an antenna can have better main-beam and side-lobe characteristics, and a better SIR, than prior antennas. |
| US10396466B2 |
Microwave system
A microwave system comprising a center fed parabolic reflector; a radio transceiver, said transceiver disposed on a circuit board and coupled to a radiator, said radiator disposed on the circuit board and extending orthogonally from a surface of the circuit board. Embodiments also include directors on the circuit board and a sub-reflector comprising a thin plate disposed on a weather proof cover and said sub-reflector having a substantially concave surface with a focus directed towards the radiator. The circuit board may be physically integrated within the feed mechanism of the center fed parabolic reflector and the radio transceiver is configured to provide OSI layer support. |
| US10396462B2 |
C-band conformal antenna using microstrip circular patches and methods thereof
A conformal antenna includes a dielectric substrate. A plurality of circular micro strip antenna patches are arranged on the dielectric substrate and coupled to a coaxial feed circuit. The conformal antenna is configured to operate in a frequency range of about 4.0 GHz to about 8.0 GHz. A method of designing a conformal antenna is also disclosed. |
| US10396455B2 |
Antenna assembly for providing interference mitigation
An antenna assembly may include a right hand circularly polarized (RHCP) antenna, a left hand circularly polarized (LHCP) antenna, an RF nuller operably coupling the RHCP antenna and LHCP antenna to a difference element, and a digital nuller operably coupled to the difference element. |
| US10396450B2 |
Electronic apparatus with limited spurious radio emissions
The invention relates to an electronic apparatus including at least one electronic board provided with an external coupling connector and a radio transmission device comprising at least one antenna tuned to a predetermined frequency, the connector having a metal casing connected to an earth of the electronic apparatus. At least one metal tab is attached to the metal casing of the connector in order to project laterally from the casing so as to attenuate, in the vicinity of the antenna, a spurious electromagnetic field produced by the connector during operation, the tab having a length suitable for resonating at the predetermined frequency. |
| US10396449B2 |
Photovoltaic element with an included resonator
A photovoltaic element comprises a semiconductor structure comprising a first layer comprised of a first semiconductor material with minimum electromagnetic damping and a second layer comprised of a second semiconductor material with electromagnetic damping. An upper plane of the first layer comprises an incidence plane of an electromagnetic wave onto the semiconductor structure and the second layer continues beyond the first layer in a direction of propagation of electromagnetic radiation to receive at least a portion of the electromagnetic radiation having passed through the first layer. The photovoltaic element further comprises at least one resonator comprising a first part extending along the upper plane of the first layer and a second part extending within the first layer and the second layer. The reference electrode bordering at least a portion of the second layer is coupled to the second layer in the direction of propagation of the electromagnetic wave. |
| US10396443B2 |
Integrated antenna in an aerial vehicle
Disclosed is a cross loop antenna system for an aerial vehicle. In one embodiment, the cross loop antenna system includes a cross bar antenna and a ground plane. The cross bar antenna includes two thin coplanar perpendicular bars that intersect in the middle and are parallel to the ground plane. Each bar couples to the ground plane at each end, comprising an antenna loop. Thus, the cross loop antenna system comprises two intersecting single-fed loops. The antenna can operate at a wavelength that is approximately twice the length of the bars. In such an embodiment, the antenna system may be resonant. The distance between the bars and the ground plane may be relatively small, thus minimalizing the vertical profile of the antenna. The antenna may be operated as a dual-band antenna and may produce an omnidirectional radiation pattern. An aerial vehicle may include two such antennas. |
| US10396441B2 |
Communication device and manufacturing method thereof
A communication device and a manufacturing method thereof are disclosed. The communication device includes a top cover, a housing, a bottom cover, a first magnetic isolation layer, and a short distance communication module. The housing is made of a metal material or an electrically conductive material. The top cover, the housing, and the bottom cover are assembled to construct an accommodating space from top to bottom. The first magnetic isolation layer is formed on a surface of the housing facing the accommodating space. The short distance communication module is disposed in the accommodating space. The communication device can prevent electromagnetic waves from being affected by the housing. |
| US10396434B2 |
Electronic device with antenna
An electronic device is provided. The electronic device includes a housing including a first surface, a second surface, and a side plate surrounding part of a space between the first surface and the second surface, a display disposed in the housing, a first plate attached to or integrated into the display, a second plate facing in the third direction and positioned adjacent to the side plate, a flexible printed circuit board (FPCB) including a first planar portion coupled to the first plate, and a second planar portion coupled to the second plate and angled from the first planar portion, a printed circuit board (PCB) interposed between the display and the second surface, and a mid-plate disposed in the housing, wherein the second planar portion of the FPCB is interposed between a side surface of the mid-plate and the second plate separated from each other by a gap. |
| US10396433B2 |
Mobile terminal
A mobile terminal is disclosed. The mobile terminal includes a housing having an accommodation space, the housing including a metal frame; a mainboard received in the accommodation space and including a ground point provided on a surface thereof; an antenna system grounded through the mainboard. The antenna system includes a main antenna including a low-frequency feeding portion and a high-frequency feeding portion both of which are respectively connected to the metal frame; and a matching system configured on the metal frame for adjusting the frequency band of the antenna system. The high-frequency feeding portion is isolated from the low-frequency feeding portion through a LC filtering system. |
| US10396427B2 |
Dual polarized wideband LTE thin film antenna
A thin film, flexible, co-planar waveguide (CPW), dual-polarized antenna structure suitable to be mounted on vehicle glass and that has particular application for MIMO LTE applications in the frequency band of, for example, 0.46-3.8 GHz. The antenna structure includes two U-shaped antenna radiating elements that receive signals that are linearly polarized in two orthogonal horizontal (H) and vertical (V) directions, where the radiating elements are separated by a ground plane line. |
| US10396421B2 |
Slot coupled directional coupler and directional filters in multilayer substrate
Traveling-wave directional filters (DFs) with multiple coupling slots are disclosed. A traveling-wave directional filter may include two terminating conductive strips in a top circuit layer of a substrate, a loop resonator in a bottom layer of a substrate, and a shared ground plane. Coupling slots in the ground plane may couple the conductive strips via the loop resonator. |
| US10396417B2 |
Battery arrangments for gas turbine engines
A battery arrangement for a gas turbine engine, the battery arrangement comprising: a wall of the gas turbine engine; a thermal battery coupled to the wall and arranged to receive thermal energy from gas of the gas turbine engine; and charging circuitry configured to supply electrical energy to the thermal battery to recharge the thermal battery. |
| US10396412B2 |
Power storage module
A power storage module includes power storage elements and cooling members that are in contact with the power storage elements to transfer heat. The cooling member includes an enclosing member, refrigerant, and an absorbing member absorbing the refrigerant, and the enclosing member includes a first sheet member and a second sheet member that are connected in a liquid tight manner, and the refrigerant and the absorbing member are arranged within the enclosing member. The cooling member is arranged to be inclined with respect to a horizontal plane such that a section thereof being in contact with the power storage element to transfer heat is on a lower level. |
| US10396407B2 |
Secondary battery internal temperature estimation device and secondary battery internal temperature estimation method
A secondary battery internal temperature estimation device that estimates a secondary battery's internal temperature regardless of the secondary battery's type or state of degradation, the device including: a control unit that estimates the secondary battery's internal temperature on the basis of a relational equation showing a relationship between an external temperature and the secondary battery's internal temperature. A control unit calculates element values of an equivalent circuit of the secondary battery, determines a coefficient of the relational equation on the basis of the element values of the equivalent circuit calculated by the control unit, and applies the coefficient obtained by the control unit to the relational equation. The control unit estimates the secondary battery's internal temperature on the basis of the relational equation to which the coefficient has been applied by the control unit. |
| US10396405B2 |
Bus bar for a battery connector system
A bus bar for electrically connecting adjacent battery cells of a battery module includes a base having a first leg and a second leg connected by a flexible joint. The flexible joint is folded-over such that the first leg is above the second leg. A first terminal tab extends from the first leg. The first terminal tab is configured to be terminated to a corresponding battery terminal of a first of the battery cells. A second terminal tab extends from the second leg. The second terminal tab is configured to be terminated to a corresponding battery terminal of a second of the battery cells. The first and second terminal tabs are arranged side-by-side with the first terminal tab being vertically positionable independent of the second terminal tab by the flexible joint. |
| US10396404B2 |
Electrochemical cell with bipolar faradaic membrane
An electrochemical cell includes a negative electrode having a first liquid phase having a first active metal, a positive electrode having a second liquid phase having a second active metal, and a liquid electrolyte having a salt of the first active metal and a salt of the second active metal. The electrochemical cell also includes a bipolar faradaic membrane, disposed between the negative electrode and the positive electrode, having a first surface facing the negative electrode and a second surface facing the positive electrode. The bipolar faradaic membrane is configured to allow cations of the first active metal to pass through and to impede cations of the second active metal from transferring from the positive electrode to the negative electrode and is at least partially formed from a material having an electronic conductivity sufficient to drive faradaic reactions at the second surface with the cations of the positive electrode. |
| US10396403B2 |
Electrochemical energy storage device
The present disclosure provides an electrochemical energy storage device, which comprises a cell, an electrolyte and a package. The electrochemical energy storage device further comprises a binding material positioned between the cell and the package. The binding material comprises an adhesive layer and a covering layer. The adhesive layer is directly or indirectly adhered and positioned on an outer surface of the cell, and a surface of the adhesive layer which is far away from the cell is an adhesive surface; the covering layer is positioned on the adhesive surface of the adhesive layer, the covering layer is dissolved or swollen into the electrolyte in whole or in part so as to expose the adhesive surface of the adhesive layer, therefore the adhesive layer can make the cell adhered with the package. The covering layer is a polar molecule, the polar molecule comprises one or more selected from the group consisting of —F, —CO—NH—, —NH—CO—NH—, and —NH—CO—O—. The electrochemical energy storage device of the present disclosure may not only fixedly connect the cell to the package so as to resolve the problems during the drop test, but also may resolve the problem that the cell is difficult to put into the package because the two surfaces of the binding material are both adhesive, the electrochemical energy storage device also has an excellent cycle performance and an excellent charge-discharge performance under a high rate. |
| US10396401B2 |
Stacking apparatus and stacking method
A stacking apparatus having a cylindrical conveyance drum holding and rotating to covey a separator and an electrode conveyance unit conveying a positive electrode in a tangential direction of the conveyance drum so that the positive electrode overlaps the separator. To the outer circumferential surface of the conveyance drum, there are defined a suction area for drawing the separator that is non-rotatably positioned on an upstream side of a rotation direction of the conveyance drum with respect to a location to which the positive electrode in conveyed and a non-suction area for removing the separator that is non-rotatably positioned on a downstream side of the rotation direction of the same. The separator in the suction area is conveyed to the non-suction area, is removed from the outer circumferential surface, and is transferred onto the positive electrode, thereby gradually stacking the separator on the positive electrode. |
| US10396397B2 |
Graphene compound, method for forming graphene compound, and lithium-ion storage battery
A material that can be used in a wide temperature range is provided. A graphene compound includes graphene or graphene oxide and a substituted or unsubstituted chain group, the chain group includes two or more ether bonds, and the chain group is bonded to the above graphene or graphene oxide through a Si atom. Alternatively, a method for forming a graphene compound includes a first step and a second step after the first step. In the first step, graphene oxide and a base are stirred under a nitrogen stream. In the second step, the mixture is cooled to room temperature, a silylating agent that has a group having two or more ether bonds is introduced into the mixture, and the obtained mixture is stirred. The base is butylamine, pentylamine, hexylamine, diethylamine, dipropylamine, dibutylamine, triethylamine, tripropylamine, or pyridine. |
| US10396395B2 |
Solid electrolyte material and method for producing the same
To improve the stability of an electrolyte, among the sulfide solid electrolytes of Li—P—S—X based (X is at least one of F, Cl, N and OH) containing no metal element other than lithium, a new solid electrolyte having a possibility to have high ion conductivity and a method for producing for obtaining the same easily. The disclosure achieves the object by providing a solid electrolyte material including a sulfide composition represented by a composition formula Li4−4y−x−zP4+1+y−xP5+xS4−zXz (Li4−4y−x−zP1+yS4−zXz), wherein 0.2≤x<1.0, 0≤z≤0.2, and 0≤y≤0.075, and X is at least one of F, Cl, N and OH, and the solid electrolyte material has a peak at a position of 2θ=17.8°±0.1°, 19.1°±0.1°, 21.7°±0.1°, 23.8°±0.1° and 30.85°±0.1° in X-ray diffraction measurement using a CuKα ray, and method for producing the same. |
| US10396392B2 |
Electrochemical cell
An electrochemical cell, including: a first current collector including a first collecting section in contact with a first electrode and including a first connecting section; a second current collector overlapping with the first current collector and including a second collecting section in contact with a second electrode and including a second connecting section; wherein the first and second current collectors are mutually connected via their first and second connecting sections and a distance between the first and second connecting sections is equal to or smaller than 50% of the distance between the first and the second collecting sections. |
| US10396387B2 |
Carbon nanotube based microbial fuel cells and methods for generating an electric current
A microbial fuel cell and a method for generating an electric current using the microbial fuel cell are disclosed. The microbial fuel cell comprises a housing provided with multiple cell compartments. The cell compartments includes an anode compartment having an anode in a side, and a cathode compartment having a cathode on another side separated by an ion exchange membrane. The anode is a glassy carbon modified with a multi-walled carbon nanotube/tin oxide nanocomposite configured to attach a biocatalyst, immersed in a solution. The cathode is a platinum electrode immersed in another solution. The anode and cathode are electrically connected to one another via a resistance to generate electricity. The large specific surface area and biocompatibility of the multi-walled carbon nanotube/tin oxide nanocomposite anode in the microbial fuel cell increases the bacterial biofilm formation and charge transfer efficiency. |
| US10396386B2 |
Method and apparatus for generating electrical power using sunlight and microorganisms
Systems and methods are presented for generating and storing electric power in which a microbial solar cell is provided in a sealed container with photosynthetic organisms that generate reactants of the microbial fuel cell and the products of the microbial fuel cell from sunlight received through the container. |
| US10396385B2 |
Ion exchanging membrane, method for manufacturing the same, and energy storage device comprising the same
The present invention relates to an ion exchange membrane, a method for manufacturing the same, and an energy storage device including the same, and the ion exchange membrane includes a porous support including a plurality of pores and an ion conductor filling the pores of the porous support, in which the porous support includes micropores having a size of 31 to 1000 μm. The ion exchange membrane may achieve high energy efficiency in the case of being applied to an energy storage device such as a vanadium redox inflow battery due to high charge/discharge cycle durability, high ion-conductivity, and excellent chemical and thermal stability. |
| US10396370B2 |
Passive tortuous path drain
A passive tortuous path drain for a directing fluid flow from an enclosure includes a drain body having a front face and a back face. The front face defines a curved trenched channel having a first curved channel end and a second curved channel end. The front face also defines a second trenched channel. The drain body defines at least one egress opening in fluid communication with the second trenched channel. The first curved channel end and a second curved channel end are in fluid communication with the second trenched channel. Characteristically, the drain is adapted to be positioned adjacent to a drain opening in an enclosure such that liquid flows from the drain opening to the curved trenched channel and then to the second trenched channel exiting through the egress opening. |
| US10396368B2 |
PEM fuel cell stack
A fuel cell includes a cathode flow field plate, an anode flow field plate, and a membrane electrode assembly (MEA) sandwiched between the cathode and anode flow field plate. The cathode flow field plate has a flat side and an opposed channel side that the MEA is sandwiched between the anode flow field plate and the flat side of the cathode flow field plate. The cathode flow field plate further has a plurality of flow channels formed at the channel side for enabling fluid flowing along the flow channels to promote electrochemical reaction through the MEA so as to generate electrical energy. |
| US10396367B2 |
Fuel cell separator
Provided is a fuel cell separator obtained by molding a composition that contains an epoxy resin and a graphite powder, wherein: the epoxy resin contains a main resin, a curing agent, and a curing accelerator; the main resin contains a biphenyl novolak-type epoxy resin having an ICI viscosity of 0.03-0.12 Pa·s at 150° C.; and the curing agent is a novolak-type phenol resin having a weight-average molecular weight of 420-1,500 and a dispersion degree of 2.0 or less. |
| US10396362B2 |
Electrode active material slurry, preparation method thereof, and all-solid secondary battery comprising the same
Provided is an electrode active material slurry including a clustered complex and a slurry, wherein the clustered complex includes an electrode active material, a solid electrolyte, a conductive material, and a first binder, and the slurry includes a solvent and a second binder.The electrode active material slurry may include the clustered complex including the first binder and the slurry including the second binder so as to decrease a surface area of the overall complex, such that adhesion property with the current collector may be sufficiently secured even by using a small amount of binder, and performance of the all-solid secondary battery may be further improved. |
| US10396358B2 |
Nonaqueous electrolyte secondary battery
The nonaqueous electrolyte secondary battery provided by the present invention has a positive electrode 50 that has a positive electrode active material layer 54, a negative electrode 60 that has a negative electrode active material layer 64, and separators 70, 72 interposed between the positive electrode active material layer 54 and the negative electrode active material layer 64. The positive electrode active material layer 54 contains a positive electrode active material and an inorganic phosphate compound that contains an alkali metal and/or an alkaline-earth metal. A phosphate ion scavenger that scavenges a phosphate ion is disposed between the positive electrode active material layer 54 and the negative electrode active material layer 64 and/or in the negative electrode active material layer 64. |
| US10396355B2 |
Negative electrode active material for secondary battery and method for manufacturing same
Provided is an anode active material for a secondary battery and a method of fabricating the anode active material. A silicon-based active material composite according to an embodiment of the inventive concept includes silicon and silicon oxide obtained by oxidizing at least a part of the silicon, and an amount of oxygen with respect to a total weight of the silicon and the silicon oxide is restricted to 9 wt % to 20 wt %. |
| US10396353B2 |
Negative electrode active material for non-aqueous electrolyte secondary battery, negative electrode for non-aqueous electrolyte secondary battery, non-aqueous electrolyte secondary battery, and method of producing negative electrode material for non-aqueous electrolyte secondary battery
A negative electrode active material for a non-aqueous electrolyte secondary battery, including negative electrode active material particles containing a silicon compound (SiOx where 0.5≤x≤1.6), the negative electrode active material particles being coated with a carbon coating composed of a substance at least partially containing carbon, the carbon coating having a density ranging from 1.2 g/cm3 to 1.9 g/cm3, the negative electrode active material particles having a characteristic of type II or type III adsorption-desorption isotherm in the IUPAC classification, as obtained by adsorption-desorption isotherm measurement with nitrogen gas. This negative electrode active material can increase the battery capacity and improve the cycle performance and battery initial efficiency. |
| US10396351B2 |
Negative electrode material for non-aqueous electrolyte secondary battery and method of producing negative electrode active material particles
A negative electrode material for a non-aqueous electrolyte secondary battery contains negative electrode active material particles containing a silicon compound expressed by SiOx, where 0.5≤x≤1.6, and a coating layer composed of an organic polymer coating the silicon compound, the silicon compound containing a lithium compound on its surface or inside. As a result, a negative electrode material for a non-aqueous electrolyte secondary battery can increase the battery capacity and improve the cycle performance and battery initial efficiency |
| US10396348B2 |
Negative electrode material for non-aqueous electrolyte secondary battery, method of producing negative electrode material for non-aqueous electrolyte secondary battery, and non-aqueous electrolyte secondary battery
The present invention is directed to a negative electrode material for a non-aqueous electrolyte secondary battery, including a conductive powder composed of silicon-based active material particles coated with a conductive carbon film, in which the conductive carbon film exhibits a d-band having a peak half width of 100 cm−1 or more as determined from a Raman spectrum of the conductive carbon film. The invention provides a negative electrode material for a non-aqueous electrolyte secondary battery that has excellent cycle performance and keeps high charge and discharge capacity due to use of a silicon-based active material, a method of producing the negative electrode material for a non-aqueous electrolyte secondary battery, and a non-aqueous electrolyte secondary battery. |
| US10396347B2 |
Positive electrode for air battery, air battery using the positive electrode, and method of manufacturing the positive electrode
A positive electrode for an air battery that can remarkably improve the battery performance is provided by uniformly dispersing fine Nb (Nb oxide) therein. An air battery using the positive electrode as well as a method of manufacturing the positive electrode is also provided.A positive electrode for an air battery includes an expanded graphite sheet containing expanded graphite and Nb dispersed within the sheet. It is desirable that the Nb be contained in a weight proportion of from 5 ppm to 50000 ppm with respect to the expanded graphite. |
| US10396346B2 |
Method of manufacturing negative electrode for nonaqueous electrolyte secondary battery
A method of manufacturing a negative electrode for a nonaqueous electrolyte secondary battery, the method includes mixing negative electrode active material particles and ferroelectric particles with each other to form first composite particles in which the ferroelectric particles are attached to the negative electrode active material particles; mixing the first composite particles and a binder with each other to form granulated particles; applying pressure to an aggregate of the granulated particles to form a sheet-shaped negative electrode mixture layer; and arranging the negative electrode mixture layer on a main surface of a negative electrode current collector foil. |
| US10396343B2 |
Sealing patch for electrolyte fill hole
A lithium-ion battery cell includes an enclosure that includes a casing and a lid. The enclosure has an electrolyte fill hole disposed on a surface of the casing opposite the lid. An electrochemical cell is disposed within the enclosure. Additionally, a sealing patch is laser welded to the surface of the casing around the electrolyte fill hole, wherein the sealing patch is configured to seal the electrolyte fill hole. |
| US10396338B2 |
Battery
A battery includes an electrode assembly, a case accommodating the electrode assembly, a cap plate sealing an upper portion of the case, a coupling pin elongated downwardly from the cap plate to the electrode assembly such that the coupling pin is concave when the cap plate is viewed from above and convex when the cap plate is viewed from below, and an electrode lead coupled to the coupling pin which electrically connects the coupling pin and the electrode assembly to one another.The battery may have a simple structure, reduced electrical resistance, an improved output performance. |
| US10396330B2 |
Porous granules containing mixture of rubber and silica powders
Granules containing mixtures of silica powder and cross-linked rubber powder are used in the manufacture of battery separators or vehicle tires. A granule contains silica and rubber powders in proportional amounts that form a silica powder carrier within which rubber powder particles are distributed. Incorporating silica-rubber granules in the manufacturing process of polyethylene separators offers a way to limit water loss in and improve the cycle life of a deep cycle lead-acid battery. Incorporating silica-rubber granules in the manufacturing process of vehicle tires affords advantages including easier material handling, reduced production of dust, and reduction in the number of ingredients measured and added to the formulation. |
| US10396326B2 |
Battery block
Battery block includes the following elements: a plurality of batteries each of which includes safety valve; positive electrode-side current collecting part for collecting current by connecting the positive electrode sides of batteries; and negative electrode-side current collecting part for collecting current by connecting the negative electrode sides of the batteries. In positive electrode-side current collecting part and negative electrode-side current collecting part, the part that includes safety valves is set to one side current collecting part. On the other side current collecting part opposite the one side current collecting part, fuse that fuses at a predetermined temperature is disposed on each of batteries. |
| US10396324B2 |
Fixing device
A fixing device has a body case therein defining a housing chamber in which an object is housed and a cover that covers the housing chamber. The body case has one of a groove and a protrusion that engage with each other. The object has an other one of the groove and the protrusion. The groove includes a receiving portion and a positioning portion. The receiving portion extends in an inserting direction in which the object is inserted into the housing chamber. The positioning portion extends in an intersecting direction intersecting with the inserting direction. The cover has a restricting portion that is in contact with the object while the cover covers the housing chamber. The protrusion engages with the positioning portion when the object is fixed in the body case. The restricting portion restricts a displacement of the object in a direction opposite to the intersecting direction. |
| US10396322B2 |
Electric storage device
An electric storage device includes first storage modules, a second storage module, an attachment part, and a holding frame. The first storage modules include one first storage module and another first storage module. The attachment part has an attachment surface on which the first storage modules are mounted. The holding frame is disposed between the one first storage module and the second storage module to hold the second storage module. The holding frame includes a first frame member and a second frame member. The first frame member has a first bottom portion connected to the attachment surface. The second frame member has a second bottom portion connected to the attachment surface such that the second bottom portion is disposed between the attachment surface and a lower part of the another first storage module. |
| US10396320B2 |
Battery retention assembly and method
An illustrative battery retaining assembly comprises a retaining plate, and a casing including mounting devices. One of the mounting devices may include a hinge device, and another of the mounting devices may include a latch device. The retaining plate includes engagement portions engageable with the mounting devices, such that the retaining plate may be mounted to the casing. One of the engagement portions may include a channel engageable with the hinge device, and another of the engagement portions may include a catch engageable with the latch device. The mounting devices and engagement portions may be configured to enable the retaining plate to slide at an oblique angle with respect to the casing, to provide a variable separation distance between the casing and the retaining plate. |
| US10396319B2 |
Battery pack for coordinate measurement machine
A Battery Pack for portable CMM technology. The battery gives the CMM a longer operating period and extends battery time. The battery pack is configured to work with different operating voltages required by measurement equipment made by various manufactures'. The battery pack also provides a common mounting platform adapted to be utilized with the standard 3½-8 threaded equipment and accessories. |
| US10396316B2 |
Cell packaging material and cell
A cell packaging material in which the substrate layer surface has excellent ink printing characteristics. Cell packaging material including a layered article provided with at least a substrate layer, a metal layer, and a heast-fusible layer in the stated order, the substrate layer being formed from a polyamide resin containing an ethylene-bis-stearic acid amide and an ethylene-bis-oleic acid amide. |
| US10396310B2 |
Display apparatus
A display apparatus includes a display device and an encapsulation layer covering the display device. The encapsulation layer includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and a hybrid encapsulation layer positioned between the first inorganic encapsulation layer and the second inorganic encapsulation layer. The hybrid encapsulation layer includes at least one of alucone, zircone, zincone, titanicone, and nickelcone. |
| US10396309B2 |
Display device and fabricating method thereof
Discussed is a display device and a fabricating method thereof according to an embodiment, in which an organic-inorganic composite film is patterned without a mask by using an anti-film layer, and a residual anti-film layer protects a pad portion. The display device comprises a lower substrate; pixels arranged on a display area of the lower substrate; pads arranged on a non-display area of the lower substrate; an encapsulation layer arranged on the pixels; and an anti-film layer arranged on the pads as a molecular layer having a thickness of a single molecule. Also, the fabricating method of the display device comprises the steps of forming pads on a non-display area of a lower substrate and forming pixels on a display area; and forming an anti-film layer on the pixels as a molecular layer having a thickness of a single molecule. |
| US10396308B2 |
Organic EL display panel
An organic electroluminescence (EL) display panel includes a multi-layered wiring laminate disposed on a substrate and including insulating layers and wiring disposed on at least one of the insulating layers and extending to a vicinity of an outer periphery of the wiring laminate; an organic EL element array disposed on the wiring laminate; a first inorganic insulating layer disposed on the array and extending outside the outer periphery of the wiring laminate in plan view; a resin sealing layer disposed on the first inorganic insulating layer, covering the array in plan view, and having an outer periphery above a resin insulating layer that is a highest layer among the insulating layers; a second inorganic insulating layer disposed on the resin sealing layer, extending outside the outer periphery of the resin sealing layer in plan view, and being in contact with the first inorganic insulating layer in a thickness direction. |
| US10396302B2 |
Organic electroluminescence display device
An electroluminescence display device includes a first pixel electrode; a second pixel electrode provided in the same layer as the first pixel electrode; a counter electrode provided on the first pixel electrode and the second pixel electrode; a first organic light emitting layer provided between the first pixel electrode and the counter electrode, the first organic light emitting layer emitting light having a first wavelength; and a second organic light emitting layer provided between the second pixel electrode and the counter electrode, the second organic light emitting layer emitting light having a second wavelength. The first light emitting layer contains a host material, a first dopant material and a first assist dopant material; and the second light emitting layer contains the host material, a second dopant material and a second assist dopant material. |
| US10396301B2 |
Organic solar cell with vertical active layers
A photovoltaic device includes a substrate, an active layer with at least one organic material, and a pair of electrodes supported by the substrate. The active layer includes a first surface that receives light and a second surface that is supported by the substrate. The second surface is opposite to the first surface. Surfaces of the electrodes that contact surfaces of the active layer are perpendicular to the substrate. |
| US10396296B2 |
Organic light-emitting device
An organic light-emitting device includes electrodes and light-emitting units that each include an emission layer; and a charge generation layer, including n- and p-type charge generation layers, disposed between each adjacent pair of light-emitting units. A wavelength of maximum intensity of light emitted from one of the light-emitting units may be different from another, an n-type charge generation layer may have a metal-containing material having a work function of about 2.0 eV to about 4.5 eV, and a p-type charge generation layer may be formed of a hole transport material, an absolute value of a HOMO energy level of the hole transport material being greater than about 5.5 eV, and an absolute value of a LUMO energy level of the hole transport material being less than that of a LUMO energy level of a hole transport layer of a light-emitting unit adjacent to the p-type charge generation layer. |
| US10396294B2 |
Carbazole compound and organic light-emitting device including the same
A carbazole compound represented by Formulae 1A or 1B: wherein in Formulae 1A and 1B, A, R1 to R4, and c1 to c3 are described in the specification. |
| US10396289B2 |
Spiro organic compounds, material comprising the same for organic electroluminescence devices, and organic electroluminescence device comprising the material
The present invention provides a novel organic compound of General Formula 1, a material comprising the same for organic electroluminescence devices, and an organic electroluminescence device comprising the material. The organic compound of the present invention is useful in organic electroluminescence devices as a hole injection layer substance, a hole transport layer substance, an electron blocking layer substance, and an emission layer substance such as green and red phosphorescent host substance, and when used in the organic electroluminescence devices, can reduce the drive voltage, and increase the luminous efficiency, luminance, thermal stability, color purity and service life of the devices. |
| US10396288B2 |
Organic electroluminescent element and electronic device
An organic EL device with high emission efficiency, an electronic equipment including the organic EL device, and a compound providing the organic EL device are provided. The compound is represented by formula (1): wherein Ar1 represents a substituted or unsubstituted naphthalene ring; the substituent on the naphthalene ring is at least one selected from a fluorine atom, a cyano group, an alkyl group, a cycloalkyl group, an alkoxy group, an aryloxy group, an alkylthio group, an arylthio group, a group represented by —Si(R101)(R102)(R103), and a group represented by —Z—Ra; R1 and R2 each independently represent a hydrogen atom, an alkyl group, a cycloalkyl group, a group represented by —Si(R101)(R102)(R103), an aryl group, or a heteroaryl group; R11 to R18 each independently represent a hydrogen atom, a fluorine atom, a cyano group, an alkyl group, a cycloalkyl group, an alkoxy group, an aryloxy group, an alkylthio group, an arylthio group, a group represented by —Si(R101)(R102)(R103), or a group represented by —Z—Ra; each Z represents a single bond, an arylene group, a heteroarylene group, or a divalent linking group in which 2 to 4 groups selected from the above groups are linked together; Ra represents a group represented by —N(R104)(R105), an aryl group, or a heteroaryl group; and R101 to R105 each represent a hydrogen atom, an alkyl group, a cycloalkyl group, aryl group, or a heteroaryl group; provided that at least one selected from the substituent on the naphthalene ring and R11 to R18 represents a group represented by —Z—Ra. |
| US10396287B2 |
Amino fluorene monomers, polymers, and organic electronic devices
An organic electronic device comprising an anode, a cathode, a semiconducting layer between the anode and the cathode and a hole transporting layer between the anode and the semiconducting layer, the hole-transporting layer comprising a co-polymer comprising repeat units of formula (I) and one or more co-repeat units: (I) wherein: Ar1 independently in each occurrence represents a fused aryl or fused heteroaryl group that may be unsubstituted or substituted with one or more substituents; Ar2 represents an aryl or heteroaryl group that may be unsubstituted or substituted with one or more substituents; R independently in each occurrence represents a substituent; and m is 1 or 2, preferably 1; and each Ar1 is directly bound to an aromatic or heteroaromatic group of a co-repeat unit. |
| US10396285B2 |
Apparatus and method for detecting presence of attenuation in OLED device
An apparatus and a method for detecting presence of attenuation in the OLED device are provided. The apparatus for detecting presence of attenuation in the OLED device includes: a difference function construction circuit, an integrating circuit, a comparing circuit and a determining circuit. The method for detecting presence of attenuation in the OLED device includes: constructing a first light brightness difference function and a second light brightness difference function before and after aging, integrating the first function and the second function, comparing two integrals, and determining whether or not intrinsic attenuation is present in a light emitting material of a light emitting layer in the OLED device. The apparatus for detecting presence of attenuation in the OLED device is configured for executing the method for detecting presence of attenuation in the OLED device. |
| US10396270B2 |
Vibration actuator that is easy in conduction inspection
The vibration actuator enables easy inspection of conductivity of a conduction path for connecting an electrode of an electromechanical energy conversion element to a GND potential. In the vibration actuator, a vibration element includes an elastic body formed of a material which is insulating, dielectric, or semi-conductive, and a piezoelectric element joined to the elastic body. The piezoelectric element includes a first electrode formed on a surface of a piezoelectric body by which surface the piezoelectric body is joined to the elastic body, a second electrode provided in a manner opposed to the first electrode via the piezoelectric body, and at least two conduction paths each having a conductor in a through-hole formed in the piezoelectric body. One of the at least two conduction paths electrically connects the first electrode and the second electrode. |
| US10396269B2 |
Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits
A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material. |
| US10396260B2 |
Method of producing an optoelectronic component and optoelectronic component
A method of producing an optoelectronic component includes providing a wafer substrate that includes a light-emitting layer sequence, singulating the wafer substrate having the layer sequence into semiconductor components, applying the semiconductor components to an intermediate carrier, arranging a potting material on the intermediate carrier such that the potting material laterally surrounds the semiconductor components and is in direct contact, at least in places, with side surfaces of the semiconductor components, arranging one contact on one semiconductor component and the potting material, wherein one contact is arranged on a side of the semiconductor component and the potting material remote from the intermediate carrier, connecting the component to a carrier element, on a side of the semiconductor components remote from the intermediate carrier, removing the intermediate carrier and the wafer substrate of the semiconductor components, and bringing the semiconductor components into electrical contact by the contacts and the potting material. |
| US10396253B2 |
Method for manufacturing light-emitting device
A method for manufacturing a light-emitting device includes: scraping at least one lateral surface of a light-transmissive member disposed on a light-emitting element mounted on a substrate to shape the light-transmissive member; and spraying sublimating particles toward at least one of the substrate, the light-emitting element, or the light-transmissive member. |
| US10396250B2 |
Light emitting element including ZnO transparent electrode
An exemplary light emitting diode is provided to comprise: a first semiconductor layer; a mesa disposed on the first semiconductor layer and including an active layer and a second semiconductor layer disposed on the active layer; a ZnO transparent electrode disposed on the mesa; a first electrode disposed on the first semiconductor layer; and a second electrode disposed on the ZnO transparent electrode, and including a second electrode pad and at least one second electrode extending portion extending from the second electrode pad. The second electrode extending portion contacts the ZnO transparent electrode. The ZnO transparent electrode includes a first region and a second region. The first region protrudes from the top surface of the ZnO transparent electrode, includes a plurality of projecting portions arranged in a predetermined pattern, the thickness of the first region greater than the thickness of the second region. |
| US10396247B2 |
Light-emitting device package
A light-emitting device package of the embodiments includes a package body; at least one light emitting device above the package body; an adhesive layer between the at least one light emitting device and the package body; and an adhesive-layer-accommodating portion disposed in the package body for accommodating the adhesive layer therein, wherein the adhesive-layer-accommodating portion has a side surface disposed to be inclined at a predetermined angle relative to an imaginary vertical plane that extends in a thickness direction of the package body. |
| US10396246B2 |
Optoelectronic device and method for manufacturing the same
An optoelectronic device includes a semiconductor stack, including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer; a first metal layer formed on a top surface of the second semiconductor layer; a second metal layer formed on a top surface of the first semiconductor layer; an insulative layer formed on the top surface of the first semiconductor layer and the top surface of the second semiconductor layer; wherein a space between a sidewall of the first metal layer and a sidewall of the semiconductor stack is less than 3 μm. |
| US10396245B2 |
Light emitting element having a conductive pattern and fabrication method thereof
The present invention discloses a light emitting element and a fabrication method thereof. The light emitting element includes: an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer and a cathode electrode, all of the light emitting units are divided into a plurality of light emitting sets, each light emitting set includes at least two light emitting units and the light emitting units in a same light emitting set share a same electron transport layer and a same cathode electrode. In the technical solutions of the present invention, all of the light emitting units in a same light emitting set share a same electron transport layer and a same cathode electrode, thus effectively reducing the number of the cathode electrodes. |
| US10396240B2 |
III-nitride semiconductor light emitting device having amber-to-red light emission (>600 nm) and a method for making same
A III-nitride semiconductor light emitting device incorporating n-type III-nitride cladding layers, indium containing III-nitride light emitting region, and p-type III-nitride cladding layers. The light emitting region is sandwiched between n- and p-type III-nitride cladding layers and includes multiple sets of multi-quantum-wells (MQWs). The first MQW set formed on the n-type cladding layer comprises relatively lower indium concentration. The second MQW set comprising relatively moderate indium concentration. The third MQW set adjacent to the p-type cladding layer incorporating relatively highest indium concentration of the three MQW sets and is capable of emitting amber-to-red light. The first two MQW sets are utilized as pre-strain layers. Between the MQW sets, intermediate strain compensation layers (ISCLs) are added. The combination of the first two MQW sets and ISCLs prevent phase separation and enhance indium uptake in the third MQW set. The third MQW set, as a result, retains sufficiently high indium concentration to emit amber-to-red light of high output power without any phase separation associated problems. |
| US10396237B2 |
Light-emitting diode substrate and manufacturing method thereof, and display device
A light-emitting diode substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of a light-emitting diode (LED) substrate, including: disposing a supporting substrate supporting a plurality of LED units to be opposed to a receiving substrate so that a side of the supporting substrate facing the receiving substrate supports the plurality of LED units; and irradiating a side of the supporting substrate away from the receiving substrate with laser, stripping the LED units from the supporting substrate, and transferring the LED units onto the receiving substrate. The manufacturing method of the LED substrate can better transfer LED units from the supporting substrate onto the receiving substrate. |
| US10396231B2 |
Photovoltaic material and use of it in a photovoltaic device
The present invention relates to a photovoltaic material and a photovoltaic device comprising the photoactive material arranged between a hole transport layer and an electron acceptor layer. The present invention also relates to the use of the photovoltaic material. |
| US10396228B2 |
Quantum dot and luminescent material made therefrom
A solar concentrator module (80) employs a luminescent concentrator material (82) between photovoltaic cells (86) having their charge-carrier separation junctions (90) parallel to front surfaces (88) of photovoltaic material 84 of the photovoltaic cells (86). Intercell areas (78) covered by the luminescent concentrator material (82) occupy from 2 to 50% of the total surface area of the solar concentrator modules (80). The luminescent concentrator material (82) preferably employs quantum dot heterostructures, and the photovoltaic cells (86) preferably employ low-cost high-efficiency photovoltaic materials (84), such as silicon-based photovoltaic materials. |
| US10396226B2 |
Masterbatch for solar battery sealing sheet and process for producing solar battery sealing sheet
A masterbatch for a solar battery sealing sheet containing: at least one ethylene resin selected from the group consisting of an ethylene-α-olefin copolymer, an ethylene homopolymer and an ethylene-unsaturated ester copolymer; and at least one compound selected from the group consisting of silicon dioxide and zeolite, wherein a degree of aggregation of silicon is 0 or more and 0.350 or less and the ignition loss of the compound is more than 1.7% to 15% or less. |
| US10396225B2 |
Photovoltaic module with improved moisture protection layer
A photovoltaic module includes front and back sealing layers and at least one photovoltaic cell positioned located therebetween. A moisture resistant layer provided between the first and second sealing layers extends around a portion of a perimeter of the at least one photovoltaic cell. A moisture barrier structure including moisture barrier particles is operatively connected to the sealing layers. The moisture barrier structure improves the moisture resistance of the sealing layer and decreases the water vapor transmission rate into the photovoltaic module. |
| US10396223B2 |
Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk
A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type. |
| US10396221B2 |
Solution process for silver-containing chalcogenide layer deposition
A method of preparing a Ag2ZnSn(S,Se)4 compound, including dissolving selenourea (SeC(NH2)2) in an aprotic solvent, and dissolving a silver salt, a zinc salt, and a tin salt in the aprotic solvent with the selenourea to form a metal solution; and coating the metal solution onto a substrate to form an Ag2ZnSn(S,Se)4 compound layer on the substrate. |
| US10396219B2 |
Transparent conductive oxide in silicon heterojunction solar cells
Devices and methods for reducing optical losses in transparent conductive oxides (TCOs) used in silicon heterojunction (SHJ) solar cells while enhancing series resistance are disclosed herein. In particular, the methods include reducing the thickness of TCO layers by about 200% to 300% and depositing hydrogenated dielectric layers on top to form double layers of antireflection coating. It has been discovered that the conductivity of a thin TCO layer can be increased through a hydrogen treatment supplied from the capping dielectric during the post deposition annealing. The optimized cells with ITO/SiOx:H stacks achieved more than 41 mA/cm2 generation current on 120-micron-thick wafers while having approximately 100 Ohm/square sheet resistance. Further, solar cells and methods may include integration of ITO/SiOx:H stacks with Cu plating and use ITO/SiNx/SiOx triple layer antireflection coatings. The experimental data details the improved optics and resistance in cell stacks with varying materials and thicknesses. |
| US10396217B2 |
Decoupling finFET capacitors
A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material. |
| US10396216B2 |
Device including a sidewall Schottky interface
In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface. |
| US10396214B2 |
Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors
Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate. |
| US10396209B2 |
Thin film transistor comprising light shielding layers, array substrate and manufacturing processes of them
A thin film transistor and a manufacturing method thereof, and an array substrate are disclosed. The thin film transistor includes a gate electrode, an insulating layer, an active layer and a source/drain electrode layer, and further includes a light shielding layer, and the light shielding layer is configured to block light from entering the active layer via the insulating layer, and the light shielding layer and the gate electrode are arranged in a same layer and electrically unconnected with each other. The thin film transistor can reduce the light irradiated to the active layer and thus reduce the adverse impact thus incurred. |
| US10396207B2 |
Method for manufacturing thin film transistor substrate
There is provided a manufacturing method for a thin-film transistor substrate, which enables to excellently perform alignment between an annealed region of a semiconductor film and a mask pattern of a conductive film. The method comprises annealing a semiconductor film being formed on a gate insulation film covering a gate electrode with a laser beam by using a mask, the gate electrode being formed within a thin-film transistor substrate region on a substrate; forming a first alignment mark outside the thin-film transistor substrate region on the substrate, by irradiating the substrate through the mask with the laser beam; patterning the semiconductor film; forming a conductive film on the semiconductor film; positioning a photomask on the basis of the first alignment mark; and forming a source electrode and a drain electrode by patterning the conductive film through the photomask; wherein the first alignment mark is formed while annealing the semiconductor film. |
| US10396205B2 |
Integrated circuit device
An integrated circuit device includes a base burying insulating film covering a lower side wall of a fin-type active region on a substrate, an isolation pattern having a top surface higher than a top surface of the base burying insulating film, and a gate line covering a channel section of the fin-type active region. The gate line has an upper gate covering an upper portion of the channel section and a lower gate protruding from the upper gate toward the substrate and filling a space between a lower side wall of the channel section and an upper side wall of the isolation pattern. |
| US10396203B2 |
Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material. |
| US10396202B2 |
Method and structure for incorporating strain in nanosheet devices
A semiconductor structure includes a plurality of stacked and suspended semiconductor nanosheets located above a semiconductor substrate. Each semiconductor nanosheet has a pair of end sidewalls that have a V-shaped undercut surface. A functional gate structure is located around the plurality of stacked and suspended semiconductor nanosheets, and a source/drain (S/D) semiconductor material structure is located on each side of the functional gate structure. In accordance with the present application, sidewall portions of each S/D semiconductor material structure are in direct contact with the V-shaped undercut surface of the end sidewalls of each of the semiconductor nanosheets. |
| US10396200B2 |
Method and structure of improving contact resistance for passive and long channel devices
A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate. |
| US10396198B2 |
Vertical transistor pass gate device
A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device. |
| US10396197B2 |
Semiconductor device and method for producing semiconductor device
A semiconductor device includes a planar semiconductor layer formed on a substrate; a pillar-shaped semiconductor layer formed on the planar semiconductor layer; a gate insulating film surrounding the pillar-shaped semiconductor layer; a first metal surrounding the gate insulating film, the first metal being in contact with an upper portion of the planar semiconductor layer; a gate formed above the first metal so as to surround the gate insulating film, the gate being electrically insulated from the first metal; and a second metal formed above the gate so as to surround the gate insulating film, the second metal being electrically insulated from the gate, the second metal having an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer. |
| US10396194B2 |
Semiconductor device and method of manufacturing thereof
A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a trench, a first electrode, and a Schottky electrode. Between trenches where the Schottky electrode is provided, a sidewall of each of the trenches is in contact with first semiconductor layer; and between trenches where the first electrode is provided, a sidewall of each of the trenches is in contact with the second semiconductor region and the third semiconductor region. A region of a part of the Schottky electrode faces toward the first semiconductor region in a depth direction and the trench faces the first semiconductor region in the depth direction. |
| US10396193B2 |
III-nitride high electron mobility transistor
An III-nitride HEMT, including a substrate; a semiconductor epitaxial stack, formed on the substrate, including a buffer structure, a channel layer formed on the buffer structure and a barrier layer formed on the channel layer, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer; and a first electrode, a third electrode and a second electrode located in between, respectively formed on the barrier layer, wherein the semiconductor epitaxial stack includes a sheet resistance greater than 500 Ω/sq, wherein there is a first minimum space between the first electrode and the second electrode, a second minimum space between the second electrode and the third electrode, and the ratio of the first minimum space to the sum of first minimum space and the second minimum space is between 0.77 and 1, wherein the second electrode includes a length greater than or equal to 9 μm. |
| US10396191B2 |
Semiconductor device
A semiconductor device, including: a channel layer formed on a substrate; a top barrier layer formed on the channel layer, wherein a first heterojunction is formed between the channel layer and the top barrier layer so that a first two-dimensional electron gas is generated in the channel layer; a buffer structure formed between the substrate and the channel layer; a back barrier layer formed between the buffer structure and the channel layer, wherein a second heterojunction is formed between the buffer structure and the back barrier layer so that a second two-dimensional electron gas is generated in the buffer structure; and a source electrode, a drain electrode, and a gate electrode formed on the top barrier layer, respectively; wherein a sheet carrier density of the second two-dimensional electron gas is less than 8E+10 cm−2. |
| US10396188B1 |
Heterojunction bipolar transistors and method of fabricating the same
A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter may be smaller than 100 nanometers, which is suitable for high speed applications. |
| US10396181B2 |
Forming stacked nanowire semiconductor device
A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire. |
| US10396180B2 |
Method for forming apparatus comprising two dimensional material
A method and apparatus, the method comprising: forming at least two electrodes (23) on a release layer wherein the at least two electrodes are configured to enable a layer of two dimensional material (25) to be provided between the at least two electrodes; providing moldable polymer (27) overlaying the at least two electrodes; wherein the at least two electrodes and the moldable polymer form at least part of a planar surface (29). |
| US10396179B2 |
Forming vertical transport field effect transistors with uniform bottom spacer thickness
A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin. |
| US10396170B2 |
Semiconductor devices and methods for forming semiconductor devices
A semiconductor device includes a transistor doping region of a vertical transistor structure arranged in a semiconductor substrate. Additionally, the semiconductor device includes a graphene layer portion located adjacent to at least a portion of the transistor doping region at a surface of the semiconductor substrate. The semiconductor device further includes a transistor wiring structure located adjacent to the graphene layer portion. |
| US10396169B2 |
Nanosheet transistors having different gate dielectric thicknesses on the same chip
Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack. |
| US10396166B2 |
Semiconductor device capable of high-voltage operation
A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure. |
| US10396165B2 |
Thin low defect relaxed silicon germanium layers on bulk silicon substrates
A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary. |
| US10396160B2 |
Semiconductor structure having a single or multiple layer porous graphene film and the fabrication method thereof
A semiconductor structure having a multiple-porous graphene layer includes a sapphire substrate, a single or multiple layer porous graphene film, and a gallium nitride layer. A fabrication method for forming the semiconductor structure having a single or multiple layer porous graphene film, includes: firstly, growing up the graphene on the copper foil; then, using the acetone and isopropyl alcohol to wash the sapphire substrate, and then using the nitrogen flow to dry up; transferring the graphene onto the semiconductor substrate, using the Poly(methyl methacrylate) to fix the single or multiple layer porous graphene film, and using the acetone to wash up; using the photolithography process to etch the whole surface of the multiple-porous graphene layer; and, using the metalorganic chemical vapor deposition to deposit gallium nitride on the single or multiple layer porous graphene film and the sapphire substrate. |
| US10396156B2 |
Method for FinFET LDD doping
A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench. |
| US10396148B2 |
Semiconductor device
A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes. |
| US10396147B2 |
Grated MIM capacitor to improve capacitance
An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor. |
| US10396145B2 |
Memory cells comprising ferroelectric material and including current leakage paths having different total resistances
A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed. |
| US10396142B2 |
Array substrate and AMOLED display device
This disclosure discloses an array substrate comprising: a substrate; a driver chip, located on the substrate; a plurality of data lines, arranged in turn on the substrate, extended longitudinally and electrically connected to the driver chip; a plurality of high level lines; a metal block, located on the substrate and electrically connected to the high level lines, so that the high level lines at the same high level; wherein the data lines are electrically connected to driver chip through the area which the metal block is located in, and an insulating layer exists between the metal block and the data lines, a hollow area located in the metal block overlaps the data lines to reduce parasitic capacitance formed by the metal block and the data lines. This disclosure also discloses an AMOLED display device. Impact of resistor-capacitor delay and damage to components can be reduced by using this disclosure. |
| US10396140B2 |
Thin film transistor including a vertical channel and display apparatus using the same
A thin film transistor includes a substrate and a gate electrode disposed over the substrate. The gate electrode includes a center part and a peripheral part configured to at least partially surround the center part. The thin film transistor further includes a gate insulating layer disposed below the gate electrode and a first electrode insulated from the gate electrode by the gate insulating layer. The first electrode has at least a portion thereof overlapping the center part. The thin film transistor additionally includes a spacer disposed below the first electrode and a second electrode insulated from the first electrode by the spacer. The second electrode has at least a portion thereof overlapping the peripheral part. The thin film transistor further includes a semiconductor layer connected to the first and second electrodes, and insulated from the gate electrode by the gate insulating layer. |
| US10396136B2 |
Organic light-emitting display device
An organic light-emitting display device, including a substrate that includes a plurality of first emission portions that realize a first color and a plurality of second emission portions that realize a second color; a pixel-defining film that defines the plurality of first emission portions and the plurality of second emission portions; a plurality of pixel electrodes that are separate from each other and respectively correspond to the plurality of first emission portions; and a first stacked structure that includes an intermediate layer and a counter electrode on the intermediate layer, the intermediate layer including an organic emission layer emitting light of the first color, the first stacked structure further including first emission pattern portions respectively corresponding to the plurality of first emission portions, and first connection pattern portions on the pixel-defining film, the first connection pattern portions connecting the first emission pattern portions. |
| US10396134B2 |
Flexible color filter integrated with touch sensor, organic light-emitting display including the same, and manufacturing method thereof
The present invention relates to a flexible color filter integrated with a touch sensor, an organic light-emitting display including the same, and a manufacturing method thereof. The flexible color filter integrated with the touch sensor according to the present invention includes a color filter array formed on one surface of a separation layer, an overcoating layer formed on the color filter array, a touch sensor array formed on the overcoating layer, and a base film formed on the other surface of the separation layer. According to the present invention, a functional film, which is very thin, has high optical and flexible properties, and is formed by integrating a color filter with a touch sensor, and an organic light-emitting display to which the functional film is bonded may be implemented. |
| US10396132B2 |
Display device
A display device includes: a display element; a wavelength conversion element disposed on the display element and comprising a plurality of first wavelength conversion layers and a plurality of second wavelength conversion layers arranged in a first predetermined pattern; a transparent frame disposed on the wavelength conversion element and having a plurality of air gaps defined on a surface facing the wavelength conversion element, wherein the air gaps are recessed in a thickness direction; and a color filter element disposed on the transparent frame and comprising a plurality of first wavelength filter layers, a plurality of second wavelength filter layers and a plurality of third wavelength filter layers arranged in a second predetermined pattern, wherein the first and second wavelength filter layers are arranged to overlap the first and second wavelength conversion layers, respectively, and wherein the air gaps are arranged to overlap the first and second wavelength conversion layers. |
| US10396129B2 |
Organic light emitting display device
An organic light-emitting display device. A substrate is divided into a plurality of subpixels generating different colors of light. A light leakage prevention layer is disposed on a portion of the substrate corresponding to a light-emitting area of at least one subpixel of the plurality of subpixels. An overcoat layer is disposed on a portion of the substrate corresponding to at least one subpixel of the plurality of subpixels, and includes microlenses having a plurality of concave portions or a plurality of convex portions. An organic electroluminescent device is disposed on the overcoat layer. |
| US10396127B2 |
Constructions comprising stacked memory arrays
Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck. |
| US10396126B1 |
Resistive memory device with electrical gate control
Semiconductor devices and methods for forming the semiconductor devices include a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode. A bottom dielectric layer is disposed on the first side of the bottom electrode around the gate structure. A top dielectric layer is disposed on the first side of the top electrode around the gate structure. A gate electrode is disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode. |
| US10396123B2 |
Templating layers for perpendicularly magnetized Heusler films
Devices are described that include a multi-layered structure that is non-magnetic at room temperature, and which comprises alternating layers of Co and at least one other element E (that is preferably Al; or Al alloyed with Ga, Ge, Sn or combinations thereof). The composition of this structure is represented by Co1-xEx, with x being in the range from 0.45 to 0.55. The structure is in contact with a first magnetic layer that includes a Heusler compound. An MRAM element may be formed by overlying, in turn, the first magnetic layer with a tunnel barrier, and the tunnel barrier with a second magnetic layer (whose magnetic moment is switchable). Improved performance of the MRAM element may be obtained by placing an optional pinning layer between the first magnetic layer and the tunnel barrier. |
| US10396121B2 |
FinFETs for light emitting diode displays
The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped. |
| US10396118B2 |
Semiconductor integrated circuit, electronic device, solid-state imaging apparatus, and imaging apparatus
A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate. |
| US10396116B2 |
Solid-state image-capturing element and electronic device
The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode. |
| US10396114B2 |
Method of fabricating low CTE interposer without TSV structure
A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element. |
| US10396112B2 |
Imaging apparatus and electronic apparatus
An imaging apparatus includes: an interposer on which an image sensor including a light reception section is disposed; a translucent member that is provided on the light reception section; and a mold that is formed in sides of the interposer having a rectangular shape and bonded to the translucent member to support the translucent member, the mold including a seal surface that is bonded to the translucent member, the seal surface being provided with a protrusion. |
| US10396107B2 |
Photodiode array
A photodiode array 1 has a plurality of photodetector channels 10 which are formed on an n-type substrate 2 having an n-type semiconductor layer 12, with a light to be detected being incident to the plurality of photodetector channels 10. The photodiode array 1 comprises: a p−-type semiconductor layer 13 formed on the n-type semiconductor layer 12 of the substrate 2; resistors 4 each of which is provided to each of the photodetector channels 10 and is connected to a signal conductor 3 at one end thereof; and an n-type separating part 20 formed between the plurality of photodetector channels 10. The p−-type semiconductor layer 13 forms a pn junction at the interface between the substrate 2, and comprises a plurality of multiplication regions AM for avalanche multiplication of carriers produced by the incidence of the light to be detected so that each of the multiplication regions corresponds to each of the photodetector channels. The separating part 20 is formed so that each of the multiplication regions AM of the p−-type semiconductor layer 13 corresponds to each of the photodetector channels 10. |
| US10396106B2 |
Method for producing a semiconductor chip and semiconductor chip
A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided. |
| US10396101B2 |
Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region. |
| US10396100B2 |
Array substrate, display panel and pixel patching method
The present application provides an array substrate, which comprises a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, a plurality of pixel electrodes, and a plurality of conductive members. In each of the pixel regions, a control terminal of the TFT is electrically connected with the gate line, an input terminal of the TFT is electrically connected with the data line, and an output terminal of the TFT is electrically connected with the pixel electrode. The output terminal comprises a body, and a first contact and a second contact which are connected with the body. The first contact and one of the conductive members extending into the pixel region are overlapping-disposed and insulated from each other. The second contact and another of the conductive members extending into the pixel region are overlapping-disposed and insulated from each other. |
| US10396096B2 |
Transistor array panel and manufacturing method thereof
A transistor array panel includes a transistor which includes a gate electrode, a semiconductor layer on the gate electrode, and a source electrode and a drain electrode on the semiconductor layer. The semiconductor layer includes a first portion overlapping the source electrode, a second portion overlapping the drain electrode, and a third portion between the first portion and the second portion. The first portion, the second portion, and the third portion have different minimum thicknesses. |
| US10396092B2 |
Vertical memory device and method of manufacturing the same
Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction. |
| US10396090B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, a cell stack structure, a channel layer, a peripheral contact plug, and first dummy conductive rings. The substrate may include a first region and a second region. The cell stack structure may include interlayer insulating layers and conductive patterns, which are alternately stacked over the first region of the substrate. The channel layer may penetrate the cell stack structure. The peripheral contact plug may extend in parallel to the channel layer over the second region of the substrate. The first dummy conductive rings may be disposed at the same levels as the conductive patterns, are spaced apart from the peripheral contact plug, and surround the peripheral contact plug. |
| US10396079B2 |
Non-planar semiconductor device having doped sub-fin region and method to fabricate same
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins. |
| US10396073B2 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure. |
| US10396072B2 |
Semiconductor device
A semiconductor device is provided having a first region and a second region surrounding the first region includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type between the first electrode and the second electrode, a second semiconductor layer of the first conductivity type located over the first semiconductor layer, a third semiconductor layer of the second conductivity type on the second semiconductor layer in the first region, a fourth semiconductor layer of the first conductivity type between the third semiconductor layer and the second semiconductor layer, a fifth semiconductor layer of the second conductivity type on the second semiconductor layer in the second region, and a sixth semiconductor layer of the first conductivity type located between the fifth semiconductor layer and the second semiconductor layer, wherein the width of the fourth semiconductor layer is less than the width of the sixth semiconductor layer. |
| US10396064B2 |
Layout pattern for SRAM and manufacturing methods thereof
The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit. |
| US10396061B1 |
Transparent electronics for invisible smart dust applications
Dust-sized and light transparent semiconductor chips are provided and are used in a transparent electronic system. The dust-sized and light transparent semiconductor chips are composed entirely of materials that are transparent to visible light. The dust-sized and light transparent semiconductor chips are used as a component of a transparent electronic system. |
| US10396060B2 |
Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface. |
| US10396052B2 |
Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars. |
| US10396049B2 |
Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer. |
| US10396048B2 |
Contact hole structure and fabricating method of contact hole and fuse hole
A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole. |
| US10396047B2 |
Semiconductor package with package components disposed on a package substrate within a footprint of a die
Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed. |
| US10396045B2 |
Metal on both sides of the transistor integrated with magnetic inductors
An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side and an opposite second side; an inductor disposed on the second side of the structure; and a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum including a first side and an opposite second side, wherein the second side is coupled to the substrate; removing a portion of the substrate; forming at least one inductor on the second side of the device stratum; and coupling the at least one inductor to at least one of the plurality of transistor devices. |
| US10396041B2 |
High yield substrate assembly
High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates. |
| US10396036B2 |
Rlink-ground shielding attachment structures and shadow voiding for data signal contacts of package devices; vertical ground shielding structures and shield fencing of vertical data signal interconnects of package devices; and ground shielding for electro optical module connector data signal contacts and contact pins of package devices
A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts. |
| US10396034B2 |
Semiconductor devices and methods of manufacturing semiconductor devices
A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less. |
| US10396032B2 |
Semiconductor structures
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings. |
| US10396031B2 |
Electronic device with delamination resistant wiring board
This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at the back surface of the board. The back-surface ground pattern is provided with a notch overlapping a region of an upper wiring layer at which a board member is exposed and which is encircled by a wide pattern, the notch permitting the release of water vapor from the region. |
| US10396023B2 |
Semiconductor device
The semiconductor device includes a multi-layered substrate having an insulating plate and a circuit plate, a semiconductor chip having a front surface attached with a main electrode and a control electrode formed thereon, and a back surface fixed to the circuit plate, a first wiring substrate which includes a first conductive member and is placed so as to face the main electrode connected electrically to first conductive member, a second wiring substrate which includes a second conductive member, is placed so as to face the control electrode, and has an opening, and a conductive post having one end and another end, the one end being connected electrically and mechanically to the control electrode, and the other end being connected electrically and mechanically to the second conductive member. The first conductive member is thicker than the second conductive member, and the first wiring substrate is disposed within the opening. |
| US10396021B2 |
Fabrication method of layer structure for mounting semiconductor device
A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield. |
| US10396013B2 |
Advanced through substrate via metallization in three dimensional semiconductor integration
An advanced through silicon via structure for is described. The device includes a substrate including integrated circuit devices. A high aspect ratio through substrate via is disposed in the substrate. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is disposed on the sidewalls of the through substrate via. A surface portion of the metallic barrier layer has been converted to a nitride surface layer by a nitridation process. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer fills the through substrate via and has a recess in an upper portion. A second barrier layer is disposed over the recess. A second metal layer is disposed over the second barrier layer and creates a contact. |
| US10396012B2 |
Advanced through substrate via metallization in three dimensional semiconductor integration
A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A first metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill the through substrate via. A selective etch creates a recess in the first metal layer in the through substrate via. A second barrier layer is deposited over the recess. A second metal layer is patterned over the second barrier layer filling the recess and creating a contact. Another aspect of the invention is a device produced by the method. |
| US10396011B2 |
Thermally enhanced semiconductor package and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity. |
| US10396010B2 |
Onboard control device
Provided is an inexpensive and highly reliable resin sealed-type onboard electronic control device is mounted in a vehicle such as an engine control unit and a control unit for automatic transmission, which have a heat dissipation structure for dissipating heat generated from an electronic component such as a semiconductor element. The onboard control device includes a circuit board, a member provided to face the circuit board, a heat generating electronic component mounted between the circuit board and the member, a heat dissipating material provided between the heat generating electronic component and the member, and a sealing resin to seal the circuit board and the heat generating electronic component. And a space between the member and the circuit board is at least a part of a range where the heat dissipating material is not provided, and is narrower than a range where the heat dissipating material is provided. |
| US10396009B2 |
Heat dissipation material and method of manufacturing thereof, and electronic device and method of manufacturing thereof
A heat dissipation material includes a plurality of linearly-structured objects of carbon atoms configured to include a first terminal part and a second terminal part; a first diamond-like carbon layer configured to cover the first terminal part of each of the plurality of linearly-structured objects; and a filler layer configured to be permeated between the plurality of linearly-structured objects. |
| US10396008B2 |
Semiconductor device
A semiconductor device includes a first metal plate and a second metal plate which interpose a first semiconductor element therebetween, the first metal plate and the second metal plate being bonded to the first semiconductor element with first soldered portions; and includes a third metal plate and a fourth metal plate which interpose a second semiconductor element therebetween, the third metal plate and the fourth metal plate being bonded to the second semiconductor element with second soldered portions. A first joint provided at an edge of the first metal plate and a second joint provided at an edge of the fourth metal plate are bonded with a third soldered portion. A total sum of thicknesses of the first soldered portions is different from a thickness of the third soldered portion, a solidifying point of the thinner one is higher than a solidifying point of the thicker one. |
| US10396007B2 |
Semiconductor package with plateable encapsulant and a method for manufacturing the same
A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon. |
| US10396006B2 |
Molded air cavity packages and methods for the production thereof
Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package. |
| US10396002B2 |
Electronic component storage substrate and housing package
The present invention includes: a substrate 3, a rectangular frame-shaped substrate bank section 5 provided on the substrate 3 and including four corner portions 5A, and a metal layer 9 provided on a top surface 5Aa of the substrate bank section 5. A top surface 5Aa of the corner portions 5A of the substrate bank section 5 may have an inclined portion S slanted downward. An electronic component housing package may have a lid welded onto the metal layer 9 provided on the substrate bank section 5 of the electronic component storage substrate. |
| US10396000B2 |
Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension. |
| US10395999B1 |
Method for monitoring fin removal
A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features. |
| US10395997B2 |
Semiconductor process
The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units. |
| US10395996B2 |
Method for forming a semiconductor structure containing high mobility semiconductor channel materials
A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer. |
| US10395993B2 |
Methods and structure to form high K metal gate stack with single work-function metal
A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate. |
| US10395990B2 |
Semiconductor device and method for fabricating the same
A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction. |
| US10395986B1 |
Fully aligned via employing selective metal deposition
A method is presented for creating a fully-aligned via (FAV) by employing selective metal deposition. The method includes forming metal lines within a first inter-layer dielectric (ILD) layer, forming a second ILD layer over the first ILD layer, forming a lithographic stack over the second ILD layer to define areas where via growth is prevented, recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack, and performing metal growth over the exposed top surface of the metal lines where via growth is permitted. |
| US10395981B2 |
Semiconductor device including a leveling dielectric fill material
The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions. |
| US10395980B1 |
Dual airgap structure
The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines. |
| US10395979B2 |
Semiconductor devices
A semiconductor device includes a first lower insulating interlayer, a protection insulating layer, and a first upper insulating interlayer that are sequentially stacked on a substrate, and a conductive pattern penetrating the first upper insulating interlayer, the protection insulating layer; and the first lower insulating interlayer. The conductive pattern includes a line part extending in a direction parallel to an upper surface of the substrate and contact parts extending from the line part toward the substrate. The contact parts are separated from each other with an insulating pattern therebetween. The insulating pattern includes a portion of each of the first upper insulating interlayer, the protection insulating layer, and the first lower insulating interlayer. At least a portion of the insulating pattern has a stepped profile. |
| US10395970B2 |
Dual trench structure
A method for fabricating a dual trench structure. The method includes providing a wafer comprising a semiconductor layer including a top surface. The method includes providing charge compensation trenches and termination trenches open to the top surface that are formed in a single etch step but with different final shield oxide thicknesses. A first shield oxide layer of a first thickness is formed on the plurality of charge compensation surfaces and the termination trench surface, wherein the first thickness of the first shield oxide layer is sufficient to allow formation of voids through the charge compensation trenches. Poly-silicon is deposited to form the electrodes in the charge compensation trenches. An isolated poly-silicon etch and clean etch is performed in the termination trenches to expose the first shield oxide layer. A second shield oxide layer is deposited on the first shield oxide layer in the termination trenches. |
| US10395968B2 |
Substrate transport device, detection position calibration method and substrate processing apparatus
During a detection position calibrating operation and a substrate transport operation, a detection coordinate calculator calculates detection coordinates of an outer periphery of a reference substrate or a substrate placed at a reference position on a hand. During the detection position calibrating operation, an offset calculator calculates offsets of a plurality of detectors based on detection coordinates and design coordinates. During the substrate transport operation, a detection coordinate corrector corrects the detection coordinates based on the offsets of the plurality of detectors, and a coordinate information corrector corrects coordinate information based on the corrected detection coordinates. A movement controller controls an up-and-down direction driving motor, a horizontal direction driving motor and a rotation direction driving motor and controls an upper hand advancing retreating driving motor and a lower hand advancing retreating driving motor, such that the substrate is transported from a reception position to a placement position based on the corrected coordinate information. |
| US10395964B2 |
Apparatus and method for measurement of the thermal performance of an electrostatic wafer chuck
An apparatus and method are described for measuring the thermal performance of a wafer chuck, such as an electrostatic chuck. In one example, the apparatus ha a chamber, a base to support a wafer chuck in the chamber, a heater to heat the chuck, a window through the exterior of the chamber, and an infrared imaging system to measure the temperature of the chuck while the chuck is heated. |
| US10395962B2 |
Substrate arrangement apparatus and substrate arrangement method
In a substrate arrangement apparatus, a holder elevating mechanism disposes each first substrate between each pair of second substrates, with the first and second substrates being alternately arranged front-to-front and back-to-back. Each substrate is curved in a first radial direction to one side in a thickness direction with a minimum curvature, and curved in a second radial direction orthogonal to the first radial direction to the one side in the thickness direction with a maximum curvature. The first radial direction of the first substrates, each arranged between each pair of the second substrates, is approximately orthogonal to the first radial direction of the second substrates. This improves uniformity in the up-down direction of the distance in the direction of arrangement between the first and second substrates that are alternately arranged adjacent to each other in the direction of arrangement. |
| US10395957B2 |
Substrate processing apparatus, substrate processing method and storage medium
A substrate processing unit 14 includes processing modules 2 each performing a process on a substrate, and a substrate transfer device 121 is provided between a mounting unit 11 and the processing modules. A parameter storage unit 3 stores sets of transfer parameter 33 where an operating speed of the substrate transfer device corresponds to a processing number of substrates per a unit time. A parameter selecting unit 4 compares a processing number of substrates per a unit time determined based on a recipe 31 corresponding to the process, with those corresponding to the transfer parameters and selects a transfer parameter corresponding to the minimum processing number of substrates among the processing numbers of substrates equal to or larger than that determined based on the recipe. A transfer control units 151 to 153 control the substrate transfer device based on a set value of the selected transfer parameter. |
| US10395954B2 |
Method and device for coating a product substrate
A method and device for coating projecting surfaces of discrete projections of a product substrate that has functional units arranged at least partially in recesses. The method includes the steps of: bringing the projecting surfaces into contact with a coating material that is applied on a carrier substrate, and separating the carrier substrate from the projecting surfaces in such a way that the coating material remains partially on the product substrate. In addition, this invention relates to a corresponding device. |
| US10395951B2 |
Method of cleaning a substrate and apparatus for performing the same
In a method of cleaning a substrate, a protecting liquid may be sprayed to a surface of the substrate from a first position in a first spray direction. Cleaning droplets may be injected on to the surface of the substrate. The protecting liquid may be sprayed to the surface of the substrate from a second position different from the first position in a second spray direction. For example, the protecting liquid may be always sprayed from the central portion toward the edge portions in the substrate so that the protecting liquid on the substrate may have a uniform thickness. |
| US10395949B2 |
Substrate drying apparatus, storage medium, and substrate drying method
The substrate drying apparatus includes a rinse agent nozzle configured to eject a rinse agent to the substrate while moving away from a center of the substrate relative to the substrate, a drying gas nozzle configured to spout a drying gas to the substrate while moving away from the center of substrate relative to the substrate with movement of the rinse agent nozzle, a liquid area sensor and a dried area sensor configured to sense a surface of the substrate around an interface of the rinse agent by moving away from the center of the substrate with movement of the rinse agent nozzle and the drying gas nozzle, and a control unit configured to control a drying condition based on the sensing results of the liquid area sensor and the dried area sensor. |
| US10395948B2 |
Purge module jig and purge module having the same
A purge module jig and a purge module including the purge module jig are provided. The purge module jig and the purge module include a plate having a recessed groove and an opening formed therein, a gas transfer pipe having an elliptical cross section, and a fixing part fixing the plate and the gas transfer pipe with each other, so that leakage of cleaning gas is prevented, thickness thereof is reduced, the interference between the jig and a wafer cassette is reduced, the purge module jig and the purge module can be applied to various load ports of various manufactures, and performance thereof can be improved. |
| US10395946B2 |
Electronic package and manufacturing method thereof
A method for manufacturing an electronic package includes: forming a middle patterned conductive layer having a first surface, a second surface opposite to the first surface, and a plurality of middle conductive pads; forming a first redistribution circuitry on the first surface, wherein the first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements, each first conductive element has a first conductive via and pad that form a T-shaped section, and each first conductive via connects the corresponding middle conductive pad and is tapering; and forming a second redistribution circuitry on the second surface, wherein the second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements, each second conductive element has a second conductive via and pad that form an inversed T-shaped section, and each second conductive via connects the corresponding middle conductive pad and is tapering. |
| US10395944B2 |
Pulsing RF power in etch process to enhance tungsten gapfill performance
Methods and apparatuses for filling features with metal materials such as tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a metal such as a tungsten-containing material followed by removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ratio feature. The portion may be removed by exposing the tungsten-containing material to a plasma generated from a fluorine-containing nitrogen-containing gas and pulsing and/or ramping the plasma during the exposure. |
| US10395943B2 |
Patterning method, method for producing processed substrate, method for producing optical component, method for producing circuit board, and method for producing electronic component
To provide a patterning method for forming a desired pattern in a reverse process.A patterning method includes a reverse process.A photocurable composition contains at least a polymerizable compound (A) component and a photopolymerization initiator (B) component.The (A) component has a mole fraction weighted average molecular weight of 200 or more and 1000 or less.The (A) component has an Ohnishi parameter (OP) of 3.80 or more.The Ohnishi parameter (OP) of the (A) component is a mole fraction weighted average of N/(NC−NO), wherein N denotes a total number of atoms in a molecule, NC denotes a number of carbon atoms in the molecule, and NO denotes a number of oxygen atoms in the molecule. |
| US10395937B2 |
Fin patterning for semiconductor devices
A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask. |
| US10395935B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency power for generating the plasma, a sample stage including an electrode electrostatically chucking the sample, mounting the sample thereon, a DC power supply applying DC voltage to the electrode, and a control device shifting the DC voltage previously set, in a negative direction by a first shift amount during discharge of the plasma, shifting the DC voltage having been shifted in the negative direction by the first shift amount, in a positive direction by a second shift amount after the discharge of the plasma. The first shift amount has a value changing potential over a surface of the sample to 0 V, upon shifting the DC voltage in the positive direction. The second shift amount has a value obtained based on a floating potential of the plasma. |
| US10395933B2 |
Method for manufacturing semiconductor wafer
A method for manufacturing a semiconductor wafer including: slicing off a plurality of wafers from an ingot; chamfering outer peripheral portions of the plurality of sliced wafers; and performing double-side polishing to polish both surfaces of each wafer whose outer peripheral portion is held by a carrier, wherein includes performing warp direction adjustment to uniform directions of warps of the plurality of wafers in one direction after the slicing and before the chamfering, and the chamfering and the double-side polishing are performed in a state where the directions of the warps of the plurality of wafers are uniformed in one direction after the warp direction adjustment. Consequently, it is possible to provide the method for manufacturing a semiconductor wafer which can suppress degradation of flatness of the double-side polished wafers even in case of uniforming the directions of the warps of the wafers in one direction before the double-side polishing. |
| US10395928B2 |
Depositing a passivation layer on a graphene sheet
Embodiments of the disclosed technology include depositing a passivation layer onto a surface of a wafer that may include a graphene layer. The passivation layer may protect and isolate the graphene layer from electrical and chemical conditions that may damage the graphene layer. As such, the passivation layer may further protect the graphene sensor from being damaged and impaired for its intended use. Additionally, the passivation layer may be patterned to expose select areas of the graphene layer below the passivation layer, thus creating graphene wells and exposing the graphene layer to the appropriate chemicals and solutions. |
| US10395924B2 |
Semiconductor stack
A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is famed. Density of a second recessed portion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm−2 in the epi principal surface. |
| US10395923B2 |
Localized electron beam induced deposition of silicon carbide
A method for produce a silicon-carbide film by admitting a gaseous silicon-carbide precursor into a vacuum chamber containing a substrate and directing an electron beam into the vacuum chamber onto to the surface of the substrate. The electron beam dissociates the gaseous silicon-carbide precursor at the surface of the substrate creating non-volatile fragments that bind to the substrate surface forming a silicon-carbide film. |
| US10395922B2 |
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam. |
| US10395921B2 |
Method of forming thin film
Provided is a method of forming a thin film having a target thickness T on a substrate by an atomic layer deposition (ALD) method. The method includes n processing conditions each having a film growth rate that is different from the others, and determining a1 to an that are cycles of a first processing condition to an n-th processing condition so that a value of |T−(a1×G1+a2×G2+ . . . +an×Gn)| is less than a minimum value among G1, G2, . . . , and Gn, where n is 2 or greater integer, G1, . . . , and Gn respectively denote a first film growth rate that is a film growth rate of the first processing condition, . . . and an n-th film growth rate that is a film growth rate of the n-th processing condition, and the film growth rate denotes a thickness of a film formed per a unit cycle in each of the processing conditions. The film forming method may precisely and uniformly control a thickness of the thin film when an ALD is performed. |
| US10395915B2 |
Nozzle assembly, substrate treatment apparatus including the nozzle assembly, and method of treating substrate using the assembly
Provided is a substrate treatment apparatus. The apparatus includes a chuck supporting a substrate and being rotatable, a container surrounding the chuck and collecting chemicals scattered due to rotations of the substrate, and a first spray nozzle spraying the chemicals to the substrate. |
| US10395912B2 |
Spray chambers and methods of using them
Devices, systems and methods including a spray chamber are described. In certain examples, the spray chamber may be configured with an outer chamber configured to provide tangential gas flows. In other instances, an inner tube can be positioned within the outer chamber and may comprise a plurality of microchannels. In some examples, the outer chamber may comprise dual gas inlet ports. In some instances, the spray chamber may be configured to provide tangential gas flow and laminar gas flows to prevent droplet formation on surfaces of the spray chamber. Optical emission devices, optical absorption devices and mass spectrometers using the spray chamber are also described. |
| US10395909B2 |
Mass spectrometer
The objective of the present invention is to obtain an MS2 spectrum for each of a plurality of different ion species even when their m/z values are extremely close to each other and prevent separate setting of each ion species as the precursor ion. In the vicinity of the target m/z, a precursor-ion selection window covering a predetermined m/z range (2×ΔM) is gradually shifted in predetermined steps (Δm) to define a plurality of windows as the condition of the precursor-ion selection. When an MS2 analysis is performed on the same sample for each window, the intensities of the product-ion peaks which appear on the MS2 spectrum change with the change in the central m/z value of the window. From this intensity change, which of the plurality of ion species selected as the precursor ion is the origin of each product ion is determined. Based on the result of this determination, the product ions are sorted out and an MS2 spectrum is reconstructed for each ion species. |
| US10395898B2 |
Substrate treating apparatus, substrate treating method, and plasma generating unit
Disclosed are a substrate treating apparatus, a substrate treating method, and a plasma generating unit. The substrate treating apparatus includes a housing configured to provide a treatment space, in which a substrate is treated, a support unit configured to support a substrate in the treatment space, a plasma generating unit disposed outside the housing and configured to excite plasma from a gas and supply the excited plasma to the treatment space, and a controller, wherein the plasma generating unit includes a plasma generating chamber having a space, into which a gas is introduced, a first antenna wound to surround the plasma generating chamber and connected to a power source through an electric wire, a second antenna wound around the plasma generating chamber and connected to the power source through an auxiliary electric wire, and a switch configured to switch on and off the auxiliary electric wire. |
| US10395896B2 |
Method and apparatus for ion energy distribution manipulation for plasma processing chambers that allows ion energy boosting through amplitude modulation
Methods and apparatus for boosting ion energies are contemplated herein. In one embodiment, the methods and apparatus comprises a controller, a process chamber with a symmetrical plasma source configured to process a wafer, one or more very high frequency (VHF) sources, coupled to the process chamber, to generate plasma density and two or more frequency generators that generate low frequencies relative to the one or more VHF sources, coupled to a bottom electrode of the process chamber, the two or more low frequency generators configured to dissipate energy in the plasma sheath, wherein the controller controls the one or more VHF sources to generate a VHF signal and the two or more low frequency sources to generate two or more low frequency signals. |
| US10395894B2 |
Systems and methods for achieving peak ion energy enhancement with a low angular spread
Systems and methods for increasing peak ion energy with a low angular spread of ions are described. In one of the systems, multiple radio frequency (RF) generators that are coupled to an upper electrode associated with a plasma chamber are operated in two different states, such as two different frequency levels, for pulsing of the RF generators. The pulsing of the RF generators facilitates a transfer of ion energy during one of the states to another one of the states for increasing ion energy during the other state to further increase a rate of processing a substrate. |
| US10395890B2 |
Ion implantation method and ion implantation apparatus
An ion implantation apparatus includes: a multistage linear acceleration unit including a plurality of stages of high-frequency resonators and a plurality of stages of focusing lenses; a first beam measuring unit disposed in the middle of the multistage linear acceleration unit and configured to allow passage of a beam portion adjacent to a center of a beam trajectory and measure a current intensity of another beam portion blocked by an electrode body outside a vicinity of the center of the beam trajectory; a second beam measuring unit disposed downstream of the multistage linear acceleration unit and configured to measure a current intensity of an ion beam exiting from the multistage linear acceleration unit; and a control device configured to adjust a control parameter of the plurality of stages of focusing lenses based on measurement results of the first and second beam measuring units. |
| US10395885B2 |
Charged particle device, charged particle irradiation method, and analysis device
Provided is an optical system which can adjust, including increase, a spin polarization degree of an electron beam. Disclosed is a charged particle device having a charged particle source which generates charged particles, a sample table on which a sample is placed, and a transport optical system which is disposed between the charged particle source and the sample table and transports the charged particles as charged particle flux toward the sample table. In this device, the transport optical system includes a magnetic field generating section which generates a magnetic field having a vertical component to a course of the charged particle flux, an electric field generating section which generates an electric field having a vertical component to the course of the charged particle flux, and a shielding section which shields at least a part of the charged particle flux passed through the magnetic field generating section and the electric field generating section. Moreover, the vertical component of the magnetic field has a magnetic field gradient, and the vertical component of the electric field gives an electrostatic force in a direction opposite to a Lorentz force received by the charged particle flux. |
| US10395884B2 |
Ruthenium encapsulated photocathode electron emitter
A photocathode structure, which can include an alkali halide, has a protective film on an exterior surface of the photocathode structure. The protective film includes ruthenium. This protective film can be, for example, ruthenium or an alloy of ruthenium and platinum. The protective film can have a thickness from 1 nm to 20 nm. The photocathode structure can be used in an electron beam tool like a scanning electron microscope. |
| US10395882B1 |
Tunable quantum confinement and quantum dot photocathode
A tunable photocathode for use in vacuum electronic devices includes a nanostructured photoemission layer including quantum confined nanostructures, such as quantum dots. The quantum confined nanostructures can be tuned (e.g., prepared to have various characteristics or parameters) in order to independently optimize various characteristics of the electron beam emitted by the photocathode. For example, by changing the material composition, size and geometry of the quantum confined nanostructures, the energy levels of the quantum confined nanostructures in the photoemission layer can be tuned to provide a photocathode having a high quantum efficiency, low emittance, fast response time to incident light pulses, long operational lifetime, and increased environmental stability compared with conventional photocathodes and cathodes in vacuum electronic devices. |
| US10395880B2 |
Electron gun adjustment in a vacuum
Embodiments include a vacuum device, comprising: an enclosure configured to enclose a vacuum, the enclosure including an external base including an opening; an internal base within the enclosure; and an adjustable support assembly adjustably coupling the internal base to the external base and extending through the opening, the adjustable support assembly comprising: a threaded shaft extending along a longitudinal axis and coupled to the internal base; a threaded hole component threadedly engaged with the threaded shaft and coupled to the external base such that the threaded hole component is axially constrained in a direction along the longitudinal axis relative to the external base independent of the threaded shaft; and a flexible component coupled to the external base and the threaded shaft and sealing the opening. |
| US10395878B2 |
Modular fuse holder and arrangement and connection thereof
A fuse holder includes a holder base comprising a plurality of protrusions each having a mounting hole formed therein to provide for mounting of the holder base to an external component and one or more mating protrusions and one or more mating slots formed on each of opposing side surfaces. The fuse holder also includes an input stud coupled to or formed on the holder base and a cover configured to attach to the holder base to at least partially enclose one or more fuses positionable on the fuse holder. The one or more mating protrusions and the one or more mating slots formed on each of the opposing side surfaces of the holder base comprise dovetailed protrusions and slots of a matching profile capable of receiving such a dovetailed protrusion, so as to enable a side-by-side stacking and interlocking of fuse holders with such mating protrusions and mating slots. |
| US10395876B1 |
Protection device
A protection device comprises a first planar substrate, a second planar substrate, a heater and a fusible element. The first planar substrate comprises a first surface, and the second planar substrate comprises a second surface facing the first surface. The heater comprises a first heating element and a second heating element in parallel connection, and the first heating element is disposed on the first surface. The fusible element is disposed on the first surface and adjacent to the first and second heating elements, thereby the fusible element is melted by absorbing the heat generated by the first heating element and/or second heating element. The second heating element has a resistance at least twice that of the first heating element. |
| US10395875B2 |
Circuit breaker panel including remotely operated circuit breaker
A circuit breaker panel includes a control unit structured to generate a control signal and a number of circuit breakers. At least one of the circuit breakers includes a number of sets of separable contacts and is structured to open or close one set of separable contacts based on the control signal. At least one of the circuit breakers is structured to electrically connect between a line and load and includes a power supply structured to convert power from the line and to use the converted power to open or close the set of separable contacts. |
| US10395872B2 |
Movable contact assembly for circuit breaker
According to an aspect of the present invention, there is provided a movable contact assembly for a circuit breaker, which includes a fixed contact, a connector formed to protrude from one side of a terminal connected to a load or a power source, a plurality of movable contacts pivotably installed at the connector through a connector pin and configured to be contactable to or separable from the fixed contact, a side holder pivotably installed at the connector through the connector pin, a catch pivotably installed at the connector, supported on the side holder, and configured to restrict a rebound phenomenon of the plurality of movable contacts when current limiting interruption occurs, and a pressurizing protrusion formed at a lower portion of each of the plurality of movable contacts and configured to push the catch when the current limiting interruption occurs. |
| US10395871B1 |
Electrical switching apparatus and method of manufacturing same
An electrical switching apparatus includes a housing member, a printed circuit board assembly having a board including a first side and a second side facing away from the first side, and a barrier member coupled to each of the housing member and the first side of the board. The barrier member substantially encapsulates the first side of the board. |
| US10395867B2 |
Self regulating mechanism for storage water heater
A self regulating mechanism for a storage water heater for preventing the operation of heating elements while the heating elements are not submerged comprises a liquid level switch and an electrical contactor which are each integrated with a storage water heater having at least a water tank, at least one heating element and thermostat pair, and an input voltage line. In operation, the electrical contactor is wired to selectively control the flow of electricity from the input voltage line to the thermostats and heating elements and the liquid level switch is operative to determine the water level and operate the switching of the electrical contactor based on whether the level of water in the water tank meets a predetermined threshold. As such, the electrical contactor will only permit electricity to flow to the heating element when the liquid level switch indicates that the water tank is substantially full. |
| US10395863B2 |
Magnetic rotary dial
The present disclosure includes a rotary dial assembly having a holder and a dial portion rotatably coupled to the holder. A plurality of dial magnets are fixed to the dial portion. A holder magnet is on a side of the holder opposite to the dial portion. The holder magnet is configured to attract or repel the plurality of dial magnets as the dial portion is rotated to resist rotation of the dial portion. |
| US10395857B2 |
POW switching device with enhanced programming
A PCB motor controller comprises relays mounted on a PCB and interconnected to power traces in or on the PCB to receive incoming three-phase power and to output three-phase power to a motor. Control power traces in or on the PCB connect the relays to control circuitry, also mounted on the PCB. A power supply is mounted on the PCB and connected to the control circuitry to provide power for its operation and for switching of the relays. The relays are switched in accordance with a point-on-wave (POW) switching scheme, allowing for the use or relays and the PCB, which may not otherwise be suitable for motor control applications. |
| US10395853B2 |
Electrode and process for preparing the electrode and devices thereof
An electrode, process for preparing the electrode and devices thereof. An electrode comprising at least one metal deposited on a substrate; and at least one electrically conducting polymer. The devices comprising the electrode for energy storage and molecular separation. |
| US10395845B2 |
Flexible Ti—In—Zn—O transparent electrode for dye-sensitized solar cell, and metal-inserted three-layer transparent electrode with high conductivity using same and manufacturing method therefor
A flexible Ti—In—Zn—O transparent electrode for a dye-sensitized solar cell includes a flexible transparent substrate, and a Ti—In—Zn—O thin-film on the flexible transparent substrate. The Ti—In—Zn—O thin-film has an amorphous structure. The flexible transparent electrode, despite being deposited at room or low temperature, has low surface resistance, high conductivity and transmittance, superior resistance against external bending, improved surface characteristics and better surface roughness performance. |
| US10395842B2 |
Thin film capacitor and manufacturing method thereof
A thin film capacitor includes a capacitor body formed by alternately stacking first and second electrode layers and a dielectric layer on a substrate, and having the second electrode layer disposed in an uppermost portion thereof, and a stress alleviation layer formed on the uppermost second electrode layer. The stress alleviation layer is formed of a material having a coefficient of thermal expansion higher than those of the substrate and the dielectric layer. |
| US10395839B1 |
Multilayer ceramic electronic component
A multilayer ceramic electronic component includes a ceramic body including dielectric layers and first and second internal electrodes, first and second external electrodes disposed on first and second external surfaces of the ceramic body, respectively, the first and second external electrodes each including first and second base electrode layers having at least a portion in contact with first and second external surfaces of the ceramic body, respectively, and first and second plating layers, and a water repellent layer including a portion disposed to cover a gap between the ceramic body and the first and second plating layers, having a first thickness and a portion disposed to cover a surface of the ceramic body, to having a second thickness, smaller than the first thickness. |
| US10395838B2 |
Multilayer ceramic electronic component including an organic layer
In a multilayer ceramic capacitor, A>B is satisfied by an atomic concentration ratio B of Si to Cu in a first organic layer disposed on a first base electrode layer located on a first end surface, an atomic concentration ratio A of Si to Cu in the first organic layer disposed on the first base electrode layer located on a first principal surface and a second principal surface, and an atomic concentration ratio A of Si to Cu in the first organic layer located directly on the first principal surface and the second principal surface. |
| US10395836B2 |
Multilayer ceramic electronic component
A multilayer ceramic electronic component includes a laminated body, a first external electrode, a pair of second external electrodes, and a pair of insulating coating portions. The pair of insulating coating portions extends in a laminating direction between each of the pair of second external electrodes and the first external electrode on a second principal surface, from the second principal surface to respective portions of a first side surface and a second side surface. As viewed from at least one direction in the laminating direction, an end of the pair of insulating coating portions, which is located closest to a first principal surface, is located closer to the first principal surface than an end of the first external electrode and pair of second external electrodes, which is located closest to the first principal surface. |
| US10395834B2 |
Multilayer capacitor and board having the same
A multilayer capacitor includes a ceramic body including a plurality of dielectric layers stacked to be disposed perpendicularly to a mounting surface of the ceramic body, and first and second internal electrodes alternately disposed, with respective dielectric layers interposed therebetween, the first and second internal electrodes being exposed to the mounting surface of the ceramic body and first and second end surfaces of the ceramic body opposing each other, respectively; first and second external electrodes disposed on the ceramic body to be connected to the first and second internal electrodes, respectively; and an insulating layer disposed on the mounting surface of the ceramic body and covering portions of the first and second internal electrodes exposed to the mounting surface but not in contact with the first and second external electrodes. |
| US10395827B2 |
Electronic component
An electronic component includes a laminated body including first and second end surfaces, first and second side surfaces, and first and second principal surfaces, a first external electrode, and a second external electrode, in which the first external electrode includes a first fired electrode layer and a first resin layer, the second external electrode includes a second fired electrode layer and a second resin layer, each of the first fired electrode layer and the second fired electrode layer is provided on the laminated body and includes a region including voids and glass, each of the first resin layer and the second resin layer includes metal particles, and a surface layer of each of the first resin layer and the second resin layer has a portion of the metal particles exposed in a ratio of about 72.6% or more and about 90.9% or less. |
| US10395826B2 |
Method of supporting a capacitor, capacitor assembly and subsea adjustable speed drive comprising the assembly
A method is disclosed for supporting a capacitor. In an embodiment, the method includes applying a pressure on a first side of the capacitor parallel to a first electrode of the capacitor in a first direction of a normal of the first electrode; applying a pressure on a second side of the capacitor parallel to a second electrode of the capacitor in a second direction of a normal of the second electrode, the first direction being opposite to the second direction; and afterwards pressurizing a non-conductive fluid surrounding the capacitor to a target pressure. |
| US10395825B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween, and first and second external electrodes disposed on one surface of the body and respectively connected to the first and second internal electrodes. The first internal electrode includes a first main portion and a first lead out portion connecting the first main portion and the first external electrode, the second internal electrode includes a second main portion and a second lead out portion connecting the second main portion and the second external electrode, and the second main portion has a greater area than the first main portion and includes a corner portion defining an open space to compensate for a capacitance formed by an area in which the first lead out portion and the second main portion overlap each other. |
| US10395819B2 |
Multiple phase power converters having integrated magnetic cores for transformer and inductor windings
A multiphase DC/DC power converter includes a magnetic core having a plurality of core sections and defining a plurality of magnetic flux paths, and a plurality of winding including a plurality of transformer winding sets and a plurality of inductor windings. Each transformer winding set includes a primary winding and a secondary winding wound about at least one core section of the plurality of core sections. Each inductor winding is wound about another core section of the plurality of core sections. Magnetic flux generated by one transformer winding set of the plurality of transformer winding sets substantially cancels magnetic flux generated by at least one adjacent transformer winding set of the plurality of transformer winding sets. Magnetic flux generated by one inductor winding of the plurality of inductor windings substantially cancels magnetic flux generated by at least one adjacent inductor winding of the plurality of inductor windings. |
| US10395815B2 |
Magnetic device
A magnetic device includes a housing, a bobbin, at least one coil, and a first magnetic core and a second magnetic core. The housing has at least one side plate and a bottom plate. The side plate stands on the bottom plate and forms a space with the bottom plate. The bobbin is at least partially located in the space. The bobbin has a cylinder. The at least one coil is wound around the cylinder. Each of the first and second magnetic cores includes a center column, a side column, a connecting portion, and a metal clip. The center column is located in the cylinder. The side column is located outside the coil and away from the bottom plate, such that the coil is located between the side column and the bottom plate. The connecting portion connects the center column and the side column. |
| US10395812B1 |
Adjustable inductor
An adjustable inductor, according to embodiments of the invention, includes a wire coil configured to mount on a first side of a conductive plate. The wire coil is conductive and is a plurality of windings. A core has a first portion and a second portion. The first and second portions are configured with a plurality of grooves for threading engagement with the plurality of windings of the wire coil. The threading engagement attaches the core to the plurality of windings of the wire coil, which results in varied inductance. |
| US10395810B2 |
Inductor
An inductor includes a stacked body with a plurality of structural bodies that are stacked. Each of the plurality of structural bodies includes a wiring and an insulation layer formed on the wiring. The wirings of the plurality of structural bodies are connected in series to form a helical coil. The inductor further includes a through hole, which extends through the stacked body in a thickness direction of the stacked body, and a plurality of discrete insulation films, which are spaced apart from each other and cover surfaces of the wires of the plurality of structural bodies exposed from a surface of the stacked body. |
| US10395802B2 |
Wire harness manufacturing method
A wire harness manufacturing method includes a conduction path inserting step of inserting one or a plurality of conduction paths from one end of a resin-made tubular exterior member to the other end thereof, and an exterior member working step of performing post-working on one or a plurality of parts of the exterior member, after the conduction path inserting step. The exterior member working step includes forming a convex-shaped part when viewed from an inner surface side of the exterior member by performing the post-working using heat on an outer surface side of the exterior member. The convex-shaped part is a vibration suppressing part to reduce a play rate of the conduction path in the exterior member and suppress a vibration of the conduction path. |
| US10395800B2 |
Method of manufacturing an electrical cable using 3-D printing
Embodiments are directed to a method for manufacturing a product comprising: establishing, by a computing device comprising a processor, at least one parameter of a particular instance of a component to be used in the product, adapting, by the computing device, a baseline model of the component based on the at least one parameter to accommodate use of the particular instance of the component, growing a structure based on the adapted model to accommodate the particular instance of the component using an additive manufacturing technique, coupling the structure to the particular instance of the component, growing an electrical harness by using additive printing to establish an electrical cable, and assembling the product by coupling the electrical harness to the particular instance of the component. |
| US10395796B2 |
Flat cable and waterproof cable
A flat cable that includes a plurality of cores each including one insulated wire and/or a plurality of insulated wires that are twisted together, the cores being lined up in a cable width direction, which is orthogonal to a longitudinal direction of the insulated wires; a sheath that collectively covers the plurality of cores; and a space that is surrounded by an outer surface of one of the plurality of cores, an outer surface of another one of the plurality of cores that is adjacent to the one of the plurality of cores, and an inner surface of the sheath. |
| US10395795B2 |
Data transmission cable
A data transmission cable includes a first wire and a second wire adjacent to each other, each of the first wire and the second wire has a central conductor and a cover layer enclosing the conductor, and the conductor of the first wire has an outer diameter same as the conductor of the second wire. The ratio of the center distance between the first wire and the second wire to the outer diameter of the conductor is in the range of 1.7 to 2.35. |
| US10395788B2 |
X-ray collimator
An x-ray collimator that may include a substrate containing a plurality of holes, each hole being frustoconical at one end and tubular at the other end for use in an x-ray imaging system, whereby the x-ray collimator may be aligned with a two-dimensional array of x-ray sources and a two-dimensional x-ray sensor, and whereby x-ray photons from the x-ray sources may pass through the collimator holes and emerge as a beam of x-ray photons in a narrow angle cone which may pass through a subject being imaged, positioned between the output holes of the collimator and the x-ray sensor. |
| US10395783B2 |
Steam generator for nuclear steam supply system
A nuclear steam supply system utilizing gravity-driven natural circulation for primary coolant flow through a fluidly interconnected reactor vessel and a steam generating vessel. In one embodiment, the steam generating vessel includes a plurality of vertically stacked heat exchangers operable to convert a secondary coolant from a saturated liquid to superheated steam by utilizing heat gained by the primary coolant from a nuclear fuel core in the reactor vessel. The secondary coolant, may be working fluid associated with a Rankine power cycle turbine-generator set in some embodiments. The steam generating vessel and reactor vessel may each be comprised of vertically elongated shells, which in one embodiment are arranged in lateral adjacent relationship. In one embodiment, the reactor vessel and steam generating vessel are physically discrete self-supporting structures which may be physically located in the same containment vessel. |
| US10395781B2 |
In-situ determination of rod control system coil and cable impedances for nuclear power plants
Systems and methods of monitoring a rod control system of a nuclear power plant, including calculating impedance of at least one coil of a rod movement mechanism non-intrusively while the system is operating, comparing a measured impedance to a reference impedance, and determining if the measured impedance deviates from the reference impedance value by a predetermined amount to indicate degradation of the rod control system. |
| US10395780B2 |
Fuel assembly for a nuclear boiling water reactor
A fuel assembly for a nuclear power boiling water reactor, including: a fuel channel defining a central fuel channel axis, fuel rods, each having a central fuel rod axis, at least 3 water channels for non-boiling water, each water channel having a central water channel axis and each water channel having a larger cross-sectional area than the cross-sectional area of (the average) fuel rod. The fuel rods comprise a first group of full length fuel rods and a second group of shorter fuel rods. The fuel assembly comprises at least 5 fuel rods which belong to said second group and which are positioned such that the central fuel rod axis of each of these at least 5 fuel rods is closer to the central fuel channel axis than any of the water channel axes of the water channels. |
| US10395777B2 |
Method and system for characterizing microorganism-associated sleep-related conditions
Embodiments of a method and/or system for characterizing one or more sleep-related conditions can include determining a microorganism dataset associated with a set of subjects; and/or performing a characterization process associated with the one or more sleep-related conditions, based on the microorganism dataset, where performing the characterization process can additionally or alternatively include performing a sleep-related characterization process for the one or more sleep-related conditions, and/or determining one or more therapies S140. |
| US10395774B2 |
Vascular flow assessment
A vascular assessment apparatus is disclosed. The apparatus is configured to receive medical images of a coronary vessel tree of a subject from a medical imaging device and analyze the medical images to identify vessel segments within the coronary vessel tree. For each identified vessel segment, the apparatus is configured to analyze portions of the segment to determine at least one of a radius, diameter, or cross-sectional area of the vessel segment at the analyzed portions, determine resistances for the analyzed portions of the vessel segment based the radius, diameter, or the cross-sectional area at the analyzed portions, and combine the determined resistances for the analyzed portions of the vessel segment to determine a total resistance of the identified vessel segment. The example apparatus is also configured to determine flow rates at each identified vessel segment and calculate an index indicative of vascular function based on the determined flow rates. |
| US10395771B2 |
Computer-aided telemedical evaluation
Computer-aided telemedical evaluation is described. A computing environment can receive a video comprising frames of a subject in motion. The computing environment can identify one or more anatomical features of the subject and determine one or more gait cycle patterns for the anatomical features by tracking motion of the anatomical features over a number of frames of the video. The computing environment can also examine the gait cycle patterns to identify symmetry, asymmetry, and other characteristics in the gait cycle patterns with respect to each other, the anatomical features of the subject, and/or inanimate features of the surroundings. Based on the examination, the computing environment can also provide an evaluation of the subject in the video. The evaluation can include the identification of one or more limbs associated with lameness in the subject. Care can then be administered to the subject, in part, based on the evaluation. |
| US10395769B2 |
Patient care devices with local indication of correspondence and power line interconnectivity
According to the present disclosure, a system includes a patient support device and a power line network for communicating data, such as patient identifying information. The patient support device locally indicates information about an assigned patient. A patient care apparatus is communicatively connected to the power line network to receive data and to provide a local indication of the data received. The local indication of the device and the apparatus includes respective lights that flash substantially synchronously. |
| US10395766B2 |
Diagnostic process analysis system
Upon evaluation of a value of a diagnostic process, the value of a diagnostic process is evaluated not based on a simple cost but on a cost required for all processes of a patient who was in the diagnostic process through a follow-up survey. Diagnostic processes that are not relevant to a target diagnostic process are eliminated, clustering is performed on patients to divide the patients into clinically meaningful homogeneous groups, and the target diagnostic process is evaluated for each of the homogeneous groups. For the purpose, importance scores of data pieces of the clinical data are calculated and the relevant data is output using the output result of the medical knowledge extraction unit, clustering is performed on patients in the clinical data, and a clinical index and a cost are output for each of the clusters. |
| US10395757B2 |
Parental genome assembly method
Provided is a parental genome assembly method, comprising: using the sequencing data of parental selfing line progeny population to assemble and perfect the parental genome data. Also provided is a device for implementing the method. |
| US10395756B2 |
Genetic, metabolic and biochemical pathway analysis system and methods
Identifying pathways that are significantly impacted in a given condition is a crucial step in the understanding of the underlying biological phenomena. All approaches currently available for this purpose calculate a p-value that aims to quantify the significance of the involvement of each pathway in the given phenotype. These p-values were previously thought to be independent. Here, we show that this is not the case, and that pathways can affect each other's p-values through a “crosstalk” phenomenon that affects all major categories of existing methods. We describe a novel technique able to detect, quantify, and correct crosstalk effects, as well as identify novel independent functional modules. We assessed this technique on data from four real experiments coming from three phenotypes involving two species. |
| US10395752B2 |
Margin test for multiple-time programmable memory (MTPM) with split wordlines
The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline. |
| US10395748B2 |
Shared error detection and correction memory
Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells. |
| US10395747B1 |
Register-transfer level design engineering change order strategy
An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s). |
| US10395744B2 |
CMOS anti-fuse cell
A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a drain P+ diffusion deposited in the N-well, a source P+ diffusion deposited in the N-well, and an oxide layer deposited on the N-well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region. |
| US10395742B2 |
Semiconductor device
A memory cell of a split gate type MONOS memory is formed over a plate-shaped fin being a part of a semiconductor substrate. In a data erase operation, in a selected memory cell on which erasing is performed, a drain region is applied with 0 V, a memory gate electrode is applied with a positive voltage, and accordingly, erasing is performed by the FN mechanism. Also, in the data erase operation, in an unselected memory cell on which the erasing is not performed, connected to the same memory gate line as the above-described selected memory cell, the drain region is in an open state, and the memory gate electrode is applied with the positive voltage, whereby an induced voltage region is generated in a channel region. Thus, a potential difference between the channel region and the memory gate electrode is small, and accordingly, the erasing is not performed. |
| US10395737B2 |
Three-dimensional vertical NOR flash thin-film transistor strings
A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings. |
| US10395734B2 |
Method and apparatus for determining a cell state of a resistive memory cell
A sensing circuit senses a sensing voltage of a resistive memory cell and outputs a resultant value in response to the sensing voltage which is indicative for the actual cell state. A settling circuit includes a plurality of current mirrors for settling the sensing voltage to a certain target voltage representing one of M programmable cell states. A prebiasing circuit is provided for prebiasing a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage. A resistance circuit includes a plurality of resistors connected in series and coupled in parallel to the resistive memory cell. The resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit. The settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs switchable to define a linear range detection currents corresponding to the certain target voltages. |
| US10395733B2 |
Forming structure and method for integrated circuit memory
An integrated circuit and its manufacturing method are disclosed. The integrated circuit includes a forming voltage pad, a memory array including a plurality of memory cells, and a plurality of access lines connected to the memory cells. A forming voltage rail is coupled to the forming voltage pad. A diode is disposed in current flow communication with the forming voltage rail and an access line in the plurality of access lines. The diode is configured to be forward biased during application of a forming voltage to the forming voltage pad to induce a forming current in memory cells in the plurality of memory cells, and to be reverse biased during application of a reference voltage to the forming voltage pad during utilization of the memory array for memory operations. |
| US10395732B2 |
Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions
Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region. |
| US10395731B2 |
Memory cells, memory systems, and memory programming methods
Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes. |
| US10395729B2 |
Method of operating a memory unit sector
Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit. |
| US10395727B2 |
Nonvolatile method device and sensing method of the same
A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node. |
| US10395726B2 |
Fuse array and memory device
A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series. |
| US10395725B2 |
Semiconductor device including memory cells
A semiconductor device including: first to m-th memory cells (m is an integer of 2 or more), wherein the i-th memory cell (i is an integer greater than or equal to 1 and less than or equal to m) includes a capacitor and a first transistor; first to m-th lines, wherein the i-th line is electrically connected to a first terminal of the capacitor of the i-th memory cell; and a circuit electrically connected to the first to m-th memory cells through a wiring, wherein the circuit is configured to output data depending on summation of products of the i-th retained data and the i-th supplied data, is provided. |
| US10395724B1 |
Unregulated voltage stacked memory
Methods, systems, and devices supporting unregulated voltage stacked memory are described. A memory device may include one or more memory cells used to store information (e.g., in the form of a logic state) and configured into a number of memory banks. In some embodiments, the memory cells may be stacked. The memory device may also include multiple power supplies, which may be arranged in a series configuration between the memory banks. A memory control logic may be coupled in series with the power supplies and configured to equalize power across stacked memory cells when performing a read operation or a write operation to any of the plurality of stacked memory cells. |
| US10395722B2 |
Reading from a mode register having different read and write timing
A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register. |
| US10395721B1 |
Memory devices configured to provide external regulated voltages
Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices. |
| US10395718B2 |
Charge mirror-based sensing for ferroelectric memory
Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell. |
| US10395713B2 |
One-transistor synapse cell with weight adjustment
Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference. |
| US10395711B2 |
Perpendicular source and bit lines for an MRAM array
A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells. |
| US10395710B1 |
Magnetic memory emulating dynamic random access memory (DRAM)
The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier. |
| US10395709B2 |
Magnetic memory device
According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation. |
| US10395707B2 |
Amorphous seed layer for improved stability in perpendicular STTM stack
A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer. |
| US10395705B2 |
Integrated circuit copy prevention device powered by a photoelectric cell
An integrated circuit includes a substrate, a first circuit disposed on the substrate, a photoelectric cell disposed on the substrate and coupled to the first circuit, the photoelectric cell to provide power to the first circuit when the photoelectric cell is exposed to light, and the first circuit to allow disabling at least a portion of the integrated circuit when powered by the photoelectric cell. |
| US10395703B2 |
Column decoder of memory device
A column decoder of a memory device includes a first selection circuit, a second selection circuit and a decoding circuit. The first selection circuit and the second selection circuit are electrically connected in cascade with a memory array of the memory device. The decoding circuit receives a column address including a first sub-address and a second sub-address. The decoding circuit generates first decoded data and second decoded data for controlling the first selection circuit and the second selection circuit based on the first sub-address and the second sub-address. A first decoder in the decoding circuit decodes the first sub-address into the first decoded data, and the first decoded data is reversed in response to change of a first predetermined bit of the second sub-address. |
| US10395701B1 |
Memory device with a latching mechanism
A memory device includes a timing circuit configured to: receive an input signal, wherein the input signal is one signal within a group of input signals (e.g., multiple bits or nibbles) that are communicated according to a sequence with each of the input signals individually in serial to parallel operations, and generate a grouped latching timing signal based on the received input signal, wherein the timing signal corresponds to nibbles of the data. |
| US10395698B2 |
Address/command chip controlled data chip address sequencing for a distributed memory buffer system
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits. |
| US10395695B2 |
Data storage library with media acclimation device and methods of acclimating data storage media
A system, method and apparatus to acclimate a data storage component from a first environmental setting to a second environmental setting is disclosed. In one embodiment a system having a data storage library with a plurality of data storage cartridges and at least one media acclimation device having one or more storage locations which are sized to accept one or more data storage cartridges therein is disclosed. The at least one media acclimation device is configured to gradually acclimate the one or more storage locations from an external environmental condition to an internal environmental condition. In another embodiment, a method of acclimating a data storage library component is disclosed. The system, method and apparatus may optionally further include at least one environmental conditioning unit for conditioning the internal environment within the library. |
| US10395691B1 |
Device configured to switch a test system channel between multiple drive controllers
A data storage drive has two controllers with respective digital control outputs and serial channels. The drive has a serial test channel operable to communicate with a testing system. A switching circuit is coupled to the digital control outputs, the serial channels, and the serial test channel. The switching circuit is configured to, in response to respective combinations of binary values set via the digital control outputs, switch lines of the serial test channel between the respective serial channels of the controllers. The controllers are configured to set the combinations of binary values in response to one or more command received via a receive line of the serial test channel. |
| US10395688B2 |
Storage library system
Implementations generally relate to storage systems. In one implementation, a system includes a plurality of storage libraries that store a plurality of removable media units. The system also includes a plurality of head units for reading and writing to one or more of the removable media units. The system also includes a plurality of robots that transfer one or more of the removable media units between one or more of the storage libraries and one or more of the head units. The system also includes enabling one or more of the robots to recover a set of data from two or more of the removable media units if a failure occurs in association with at least one of the other removable media units. |
| US10395687B1 |
Tape drive bearing temperature control
A determination is made whether read/write is enabled within the tape drive storage unit. In response to determining that read/write is enabled, a determination is made whether a temperature within the tape drive storage unit exceeds a threshold value. In response to determining that the temperature within the tape drive storage unit exceeds the threshold value, a determination is made of a direction of travel of a tape media within the tape drive storage unit. In response to determining that the direction of travel is a forward direction, a first cooling device is powered on. The first cooling device lowers the temperature of a first guide roller and the tape media coming off a first tape storage reel prior to the tape media passing by a read/write head within the tape drive storage unit. |
| US10395686B2 |
Optical medium having a linear track
Various devices and systems may benefit from enhanced reading of optical media. For example, certain computer systems may benefit from array reading of optical media. An apparatus may include, for example, an array of optical sensors. The array of optical sensors may be configured to read a plurality of parallel linear strips of data from an optical medium. |
| US10395683B2 |
Procedure for setting laser and heater power in HAMR device
A heater power of a heat-assisted magnetic recording head is set based on an initial head-medium clearance estimate in response to the heater power. For a plurality of iterations, an optimum laser power of the recording head is determined and a heater power is set for a next iteration that results in an optimum heater power for the optimum laser power. If differences in the heater and laser powers between two subsequent iterations are below thresholds, the iterations are stopped and the optimum heater power and the optimum laser power for one of the subsequent iterations are used as an operational heater power and an operational laser power. |
| US10395680B1 |
Leading edge thermal sensor for a heat-assisted magnetic recording head
An apparatus includes a slider having an air bearing surface (ABS). A near-field transducer (NFT) is disposed at or near the ABS. The slider has an optical waveguide configured to couple light from a laser source to the NFT. A thermal sensor is disposed at a leading edge of the NFT, the thermal sensor has an ABS section situated at or proximate the ABS and a distal section extending away from the ABS. The thermal sensor is configured to detect changes in output optical power of the laser source and contact between the slider and a magnetic recording medium. |
| US10395679B2 |
Transducing head suspension with resonance system
A data storage system can employ at least one transducing head that is suspended above a data storage medium to access data. The transducing head suspension can be configured with a resonance system where a gimbal flexure is mounted to a load beam via a physical connection. The gimbal flexure may support a transducing head and contact the load beam via the physical connection, a dimple, and a first contact feature concurrently while the physical connection, dimple, and first contact feature are each separate and different points of physical contact. |
| US10395677B2 |
Distributing tape drive abrasion
Some embodiments are directed to computer program products for use with tape drives that oscillate the relative transverse position of a tape and magnetic head during seek operations (for example, by moving the magnetic head in the transverse direction). Some embodiments are directed to methods and computer program products for use with tape drives that select relative transverse position of the tape and magnetic head to counter uneven wear (for example, observed uneven wear, uneven wear predicted based on historical tape and drive usage data). |
| US10395675B1 |
Stress-free tape head module
An apparatus according to one embodiment includes a die comprising an array of transducers in a transducer region of the die, a first region extending from the transducer region to a first end of the die and a second region extending from the transducer region to a second end of the die. The apparatus also includes a beam. The first region of the die is fixedly attached to the beam. The transducer region and the second region are not fixedly attached to the beam. An apparatus according to another embodiment includes a die and a beam. The transducer region of the die is fixedly attached to the beam. |
| US10395674B2 |
Tape head and system having asymmetrical construction
According to one embodiment, a method includes determining a first distance from a sensor to a first edge closest thereto, where the sensor is positioned between a lower shield and the first edge, selecting a first wrap angle based on the first distance for inducing tenting of a moving magnetic recording tape in a region above the sensor, determining a second distance from a second edge to the sensor, and selecting a second wrap angle based on the determined second distance for affecting or not affecting the tenting of a moving magnetic recording tape in the region above the sensor. |
| US10395673B1 |
In-field laser calibration for heat-assisted magnetic recording head using temperature compensation equation
A temperature compensation equation is generated during manufacture of a heat-assisted magnetic recording (HAMR) disk drive using initial total currents supplied to a laser diode of the disk drive at different initial operating temperatures. The total currents represent currents for recording data to or erasing data from the medium. The temperature compensation equation is stored in the disk drive, and updated, during field operation, using a subsequent total current associated with an operating temperature differing from the initial operating temperatures. The total current supplied to the laser diode for a subsequent write operation is adjusted using the updated temperature compensation equation in response to the operating temperature at the time of the subsequent write operation. |
| US10395670B1 |
Diagnosis method, diagnosis device, and computer-readable recording medium which records diagnosis program
A diagnosis method includes giving an instruction to present at least two sound collection positions of an abnormal sound of an electric apparatus to an outside; comparing a current position of the diagnosis device and one sound collection position of the at least two sound collection positions; obtaining sound data indicative of an abnormal sound of the electric apparatus collected by a microphone, based on a comparison result and storing the sound data in a sound data storage portion so as be correlated with log data and the one sound collection position; and diagnosing an abnormal sound of the electric apparatus by using at least two items of sound data and at least two sound collection positions, based on a determination result whether sound collection is completed and a determination result whether diagnosis of an abnormal sound is possible. |
| US10395668B2 |
System and a method for determining an interference or distraction
A method and a system for determining an interference value. The method receives a sound signal and an interferer signal and forms a pair of a portion of the sound signal and the interferer signal. The portions have a predetermined time duration but the method is capable of determining the interference value swifter, so that the interference value may be output in real time. |
| US10395666B2 |
Coordinating and mixing vocals captured from geographically distributed performers
Despite many practical limitations imposed by mobile device platforms and application execution environments, vocal musical performances may be captured and continuously pitch-corrected for mixing and rendering with backing tracks in ways that create compelling user experiences. Based on the techniques described herein, even mere amateurs are encouraged to share with friends and family or to collaborate and contribute vocal performances as part of virtual “glee clubs.” In some implementations, these interactions are facilitated through social network- and/or eMail-mediated sharing of performances and invitations to join in a group performance. Using uploaded vocals captured at clients such as a mobile device, a content server (or service) can mediate such virtual glee clubs by manipulating and mixing the uploaded vocal performances of multiple contributing vocalists. |
| US10395661B2 |
Audio encoder for encoding a multichannel signal and audio decoder for decoding an encoded audio signal
A schematic block diagram of an audio encoder for encoding a multichannel audio signal is shown. The audio encoder includes a linear prediction domain encoder, a frequency domain encoder, and a controller for switching between the linear prediction domain encoder and the frequency domain encoder. The controller is configured such that a portion of the multichannel signal is represented either by an encoded frame of the linear prediction domain encoder or by an encoded frame of the frequency domain encoder. The linear prediction domain encoder includes a downmixer for downmixing the multichannel signal to obtain a downmixed signal. The linear prediction domain encoder further includes a linear prediction domain core encoder for encoding the downmix signal and furthermore, the linear prediction domain encoder includes a first joint multichannel encoder for generating first multichannel information from the multichannel signal. |
| US10395660B2 |
Apparatus and method for multichannel direct-ambient decompostion for audio signal processing
An apparatus for generating one or more audio output channel signals depending on two or more audio input channel signals is provided. Each of the two or more audio input channel signals comprises direct signal portions and ambient signal portions. The apparatus comprises a filter determination unit for determining a filter by estimating first power spectral density information and by estimating second power spectral density information. Moreover, the apparatus comprises a signal processor for generating the one or more audio output channel signals by applying the filter on the two or more audio input channel signals. The first power spectral density information indicates power spectral density information on the two or more audio input channel signals, and the second power spectral density information indicates power spectral density information on the ambient signal portions of the two or more audio input channel signals. |
| US10395657B2 |
Display apparatus capable of releasing a voice input mode by sensing a speech finish and voice control method thereof
A voice control method and display apparatus are provided. The voice control method includes converting a voice of a user into text in response to the voice being input during a voice input mode; performing a control operation corresponding to the text; determining whether speech of the user has finished based on a result of the performing the control operation; awaiting input of a subsequent voice of the user during a predetermined standby time in response to determining that the speech of the user has not finished; and releasing the voice input mode in response to determining that the speech of the user has finished. |
| US10395655B1 |
Proactive command framework
Techniques for determining a command or intent likely to be subsequently invoked by a user of a system are described. A user inputs a command (either via a spoken utterance or textual input) to a system. The system determines content responsive to the command. The system also determines a second command or corresponding intent likely to be invoked by the user subsequent to the previous command. Such determination may involve analyzing pairs of intents, with each pair being associated with a probability that one intent of the pair will be invoked by a user subsequent to a second intent of the pair. The system then outputs first content responsive to the first command and second content soliciting the user as to whether the system to execute the second command. |
| US10395654B2 |
Text normalization based on a data-driven learning network
Systems and processes for operating an intelligent automated assistant to perform text-to-speech conversion are provided. An example method includes, at an electronic device having one or more processors, receiving a text corpus comprising unstructured natural language text. The method further includes generating a sequence of normalized text based on the received text corpus; and generating a pronunciation sequence representing the sequence of the normalized text. The method further includes causing an audio output to be provided to the user based on the pronunciation sequence. At least one of the sequence of normalized text and the pronunciation sequence is generated based on a data-driven learning network. |
| US10395647B2 |
System and method for natural language processing
A system and method for improving accuracy of natural language processing using a plurality of speech recognition engines, a data fusion model to identify a correct result from the plurality of speech recognition engines and a semantic understanding model, separate and distinct from the speech recognition model, to process the correct results. A corpus is developed using the correct results and the corpus is used to train the data fusion model and the semantic understanding model. |
| US10395645B2 |
Method, apparatus, and computer-readable recording medium for improving at least one semantic unit set
A method, system, and a computer-readable recording medium for improving a set of at least one semantic unit are provided. According to the present invention, a set of at least one semantic unit may be improved by using a phonetic sound or text. |
| US10395644B2 |
Speech recognition method, speech recognition apparatus, and non-transitory computer-readable recording medium storing a program
A speech recognition method acquires sound information via multiple microphones, detects a sound source interval including sound from the sound information, acquires an estimated direction of speech by conducting direction estimation on a speech interval from among the sound source interval, conducts an adaptation process of using the sound information to estimate filter coefficients, decides a buffer size of the sound information to hold in a buffer, based on sound source interval information, estimated direction information, and adaptation process convergence state information, holds the sound information in the buffer according to the buffer size, conducts a beamforming process using the sound information held in the buffer and the filter coefficients to acquire speech information, and conducts speech recognition on the speech information acquired by the beamforming process. The method decides the buffer size to be a size sufficient for convergence of the adaptation process immediately after sound information processing starts. |
| US10395641B2 |
Modifying a language conversation model
Provided herein is a system, method, and computer program product for modifying a language conversation model of the language learning system. Modifying the language conversation model includes receiving, using a conversational sub-system, voice inputs. The conversational sub-system converts the voice inputs to voice input data and processes the voice input data. The conversational sub-system detects an error in processing the voice input data and, based at least in part on the error, stores additional data comprising additional voice input data in a memory. The conversational sub-system applies machine learning to the additional data to derive a function that is not enabled within the language conversation model. The conversational sub-system develops an update that enables the language conversation model to implement the function. The update is applied to the language conversation model. |
| US10395639B2 |
Method and user device for providing context awareness service using speech recognition
A method for providing a context awareness service is provided. The method includes defining a control command for the context awareness service depending on a user input, triggering a playback mode and the context awareness service in response to a user selection, receiving external audio through a microphone in the playback mode, determining whether the received audio corresponds to the control command, and executing a particular action assigned to the control command when the received audio corresponds to the control command. |
| US10395638B2 |
Natural language processing to merge related alert messages for accessibility
An apparatus and a computer program product for merging incoming alerts for accessibility are described. Two input alerts intended for presentation by a screen reader are received. If the two input alerts have arrived with a specified time interval, the two input alerts are combined into an output alert. The output alert is sent to a screen reader for presentation. |
| US10395636B2 |
Electronic device and method of controlling the same
An electronic device is provided. The electronic device includes an audio module including a plurality of audio reception units and a plurality of audio output units and a processor electrically connected to the audio module and configured to receive sound via the plurality of audio reception units, generate antiphase signals based on waveforms of the received sound, determine directions in which to emit the antiphase signals, based on locations of the plurality of audio reception units, and emit the antiphase signals via the plurality of audio output units. |
| US10395634B2 |
Speech reproduction device configured for masking reproduced speech in a masked speech zone
A speech reproduction device for reproducing speech based on a received speech signal so that the reproduced speech is intelligible in a clear speech zone and unintelligible in a masked speech zone includes an audio processing module configured for receiving the speech signal; a set of speech loudspeakers configured for reproducing the speech based on one or more speech loudspeaker signals; and a set of masking sound loudspeakers configured for producing a masking sound based on one or more masking sound loudspeaker signals, wherein the masking sound masks the speech in the masked speech zone; wherein the audio processing module includes a speech signal analysis module configured for producing one or more analysis signals based on spectral and/or temporal characteristics of the speech signal; wherein the audio processing module includes a masking sound generator configured for producing one or more masking sound signals based on the one or more analysis signals. |
| US10395633B2 |
Sound insulating sheet material with a cellular structure including gelatine and/or a process for producing the same
A composition for producing a sheet material with a cellular structure, the composition including the following components: (a) about 5 to about 25 weight % gelatine, (b) about 25 to 60 weight % filler material, (c) about 15 to about 40 weight % water, and (d) a cellular structure promoting agent. |
| US10395632B2 |
Electronic system combinable with a musical wind instrument in order to produce electronic sounds and instrument comprising such a system
An electronic system that can be combined with a wind musical instrument with lateral holes comprising a tubular body defining, on the inside, an air column, comprises at least one device for emitting elastic mechanical waves in the body of the instrument, at least one device for receiving elastic mechanical waves positioned to receive the waves emitted by at least one emission device after their propagation in the material of the body of the instrument and designed to provide at least one reception signal characteristic of the waves received and a device for detecting and locating the disturbance induced by an action of closing at least one lateral hole of the instrument, configured to detect and identify a configuration of closing of the lateral holes of the instrument from the analysis of at least one reception signal, the detection and location device positioned removably inside the air column of the instrument. |
| US10395631B1 |
Magnetic pedalboard system to generate sound effects for musical instruments
A magnetic pedalboard system to supply power to effects pedals for use with a musical instrument is provided. The magnetic pedalboard system includes a base member, a pair of conductive strips coupled to the top surface of the base member and electrically coupled to a power supply, and at least one pedal coupled to the pair of conductive strips, the at least one pedal having a first portion of magnetic electrical contacts electrically coupled to a second portion of magnetic electrical contacts. The at least one pedal is designed to slide along any portion of the conductive strips with the first portion of magnetic electrical contacts directly coupled to the first conductive strip and the second portion of magnetic electrical contacts directly coupled to the second conductive strip, thereby permitting the power supply to transmit electricity through the conductive strips to the at least one pedal. |
| US10395629B2 |
Musical instrument restringing device
A guitar restringing device includes one or more mandrils that rotate about one or more mandril guide axles. The one or more mandril guide axles are configured to constrain motion of the one or more mandrils keeping constant tension on a replacement guitar string during a string winding process. |
| US10395628B2 |
Flanged tone chamber window for woodwind mouthpieces
A woodwind mouthpiece has a tone chamber in communication with a central bore running through the mouthpiece and a window exposing the tone chamber. A table is located at a first end of the window, and a tip rail is located at a second end of the window opposite the first end. A pair of side rails run along opposite sides of the window from the table to the tip rail. Each side rail includes a side rail top surface. A pair of flanges are provided in the mouthpiece such that each flange extending out from one of the side rail top surfaces in a direction opposite the window. This arrangement reduces the intensity of the shock fronts at the aperture into the tone chamber. |
| US10395625B2 |
Support assembly and keyboard apparatus
A support assembly includes a support rotatable with respect to a frame, a repetition lever rotatable with respect to the support, and a first extension portion disposed to the repetition lever on a jack side with respect to the center of rotation of the repetition lever, the first extension portion being in contact with a stopper from below the stopper. |
| US10395624B2 |
Adjusting an angular sampling rate during rendering utilizing gaze information
A method, computer readable medium, and system are disclosed for adjusting an angular sampling rate during rendering. The method includes the steps of determining a location of a gaze within a displayed scene, and adjusting, during a rendering of the scene, an angular sampling rate used to render at least a portion of the scene, based on the location of the gaze within the displayed scene. |
| US10395618B2 |
Display apparatus having signal delay compensation
A display apparatus includes a controller which generates control signals and outputs image data, a compensating circuit which receives a portion of the control signals from the controller and generates a compensation signal, a voltage generating circuit which converts an input voltage to a driving voltage and increases or decreases a voltage level of the driving voltage in a frame period in response to the compensation signal, a driving part which receives the control signals and the image data from the controller and receives the driving voltage from the voltage generating circuit to generate a panel driving signal, and a display panel which receives the panel driving signal from the driving part to display an image. |
| US10395616B2 |
Display device with clock signal modification during vertical blanking period
A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle. |
| US10395613B2 |
Drive control circuit and liquid crystal display device
Disclosed is a drive control circuit, comprising a sub pixel set, a thin film transistor set, a switching unit and a driver, the driver comprises a control end, a row drive end and a column drive end, the sub pixel set comprises a plurality of sub pixels arranged in array, and the thin film transistor set comprises thin film transistors arranged in array, and one thin film transistor corresponds to one sub pixel, and the sub pixel set comprises at least one mixed sub pixel column, having at least two different sub pixels, connected to the switching unit via corresponding thin film transistors, and the control ends of the thin film transistors corresponding to the at least one mixed sub pixel column are connected to the row drive end, and the switching unit is also connected to the column drive end and the control end. |
| US10395603B2 |
Display device and electronic device having the same
A display device includes a display panel including pixels, a data driver configured to provide a data signal and an emission voltage to the pixels through the data lines, a scan driver configured to provide a scan signal to the pixels through the scan lines, a power voltage provider configured to provide a high power voltage to the pixels through a high power voltage line and to provide a low power voltage to the pixels through a low power voltage line, and a timing controller configured to generate control signals that control the data driver and the scan driver. The display panel includes a power controller that determines whether the data line is coupled to the high power voltage line or to the low power voltage line. |
| US10395601B2 |
Organic light emitting display device
An organic light emitting display device is discussed. The organic light emitting display device includes a first substrate including an active area that includes a plurality of pixels, and including upper, lower, left, and right inactive areas. The first substrate includes a plurality of data lines and a plurality of gate lines; a plurality of driving power lines; a cathode electrode layer; a plurality of driving power pads; a plurality of cathode connection parts provided in each of the left and right inactive areas; a first common driving power line; a second common driving power line; and a plurality of cathode power pads. Each of the first and second common driving power lines includes a plurality of divided common division lines. The plurality of driving power lines are grouped into a plurality of driving power line groups to be connected to a corresponding common division line. |
| US10395598B2 |
Pixel driving circuit and display apparatus thereof
A pixel driving circuit for driving a pixel unit comprises a light emitting element, a first initiating transistor, a drive transistor with a first gate electrode and a second gate electrode, a controlling transistor, a resetting transistor, a second initiating transistor, a first storage capacitor, and a second storage capacitor. A gate electrode of the second initiating transistor receives the second control signal, a source electrode of the second initiating transistor is electrically connected to an anode of the light emitting element, and a drain electrode of the second initiating transistor is electrically connected to a source electrode of the second initiating transistor. The second initiating transistor controls the second storage capacitor to discharge through the light emitting element and resets the anode of the light emitting element. |
| US10395596B2 |
Organic light emitting display device, data driver, and method for driving data driver
An organic light emitting display device which improves expression capability in a low luminance level region, wherein, when receiving a pulse width modulation value indicating a low luminance level region, the device changes the received pulse width modulation value into a pulse width modulation dimming value indicating a high luminance level region, and expresses a low luminance level region through a luminance level indicated by the pulse width modulation dimming value and a pulse width modulation dimming operation. Luminance in a low luminance level region is controlled through a pulse width modulation dimming value indicating a high luminance level region and a pulse width modulation dimming operation, so that it is possible to minutely control luminance in a low luminance level region and improve expression capability in a low luminance level region. |
| US10395595B2 |
Display device
Pixel circuits each include a write transistor having a gate electrode connected to a write control line, one of a drain electrode and a source electrode connected to a data line for transmitting data voltage corresponding to luminance of the pixel circuit, and the other of the drain electrode and the source electrode connected to a gate electrode of a drive transistor. A compensation circuit includes a compensation transistor connected to a compensation signal line and the write control line. A compensation voltage generation circuit outputs compensation control voltage in accordance with a representative value of data voltage for the pixel circuits. A capacitance of the write control line caused by the compensation transistor and a capacitance of the write control line caused by the write transistors of the pixel circuits have mutually opposite voltage dependence with respect to the representative value of the data voltage for the pixel circuits. |
| US10395589B1 |
Hybrid microdriver architectures having relaxed comparator requirements
Methods, systems, and apparatuses for controlling an emission of the light emitting devices are described herein. The light emitting devices may be light emitting diode (LED) devices including μLED devices or organic LED (OLED) devices. Emission control of the LED may be performed using a micro-scale driving circuit (e.g., μDriver) containing drive transistors for constant current driving of the light emitting devices. One embodiment provides for a display driver hardware circuit comprising a thin film transistor (TFT) backplane and an integrated circuit to switch and drive a plurality of LED devices, the integrated circuit including emission logic to generate an emission pulse to an LED device, the emission logic including comparator logic having a relaxed comparator offset, the comparator logic to compare a voltage from a storage capacitor on the TFT backplane to a reference voltage to control a length of the emission pulse provided by the emission logic. |
| US10395588B2 |
Micro LED display pixel architecture
A Light Emitting Diode (LED) display is described. The LED display includes a plurality of pixel circuits, each including an LED and a non-volatile memory cell to adjust current to the LED. |
| US10395584B2 |
Intensity scaled dithering pulse width modulation
A circuit for driving at least one light emitting diode (LED) of a display based on a greyscale vector. The circuit includes brightness scale detection circuitry to determine a brightness value based on the greyscale vector and refresh cycle selection circuitry to output an indication of a subset of refresh cycles, referred to as dithered refresh cycles. The circuit also includes pulse width determination circuitry to define a pulse width based on the greyscale vector. Pulse adjustment control circuitry, for each dithered refresh cycle, determines a dithered pulse width by adjusting the pulse width by a width adjustment amount, and outputs a dithered pulse width modulation signal including a series of pulses including a pulse having the pulse width determined by the pulse width determination circuitry non-dithered refresh cycles and a pulse having the dithered pulse width for the dithered refresh cycles. |
| US10395579B2 |
Display panel, display apparatus and sub-pixel rendering method
A display panel, a display apparatus and a sub-pixel rendering method. The display panel is constituted by repeating pixel groups. Each pixel group is composed of a pre-determined number of pixels arranged in a row, and each pixel is constituted by arraying sub-pixels of at least two different primary colors in different orders, wherein adjacent sub-pixels between adjacent pixels in each pixel group or adjacent sub-pixels between adjacent pixel pairs in each pixel group have an identical color. The adjacent sub-pixels having the identical color increase the saturation of a displayed color, so that a colored display screen has a higher color saturation, the displayed color is brighter, and levels are richer. One or more pairs among pairs constituted by the adjacent sub-pixels, having the identical color, of the adjacent pixels in each pixel group and pairs constituted by the adjacent sub-pixels, having the identical color, of the adjacent pixels between the pixel groups can be combined into a super sub-pixel, there is no black gap in the super sub-pixel, and the brightness of the super sub-pixel is greater than that of any one of the combined original sub-pixels having the identical color. The configuration of the super sub-pixel improves the utilization rate of a light source, reduces power consumption and also takes high pixel density into account. |
| US10395578B2 |
Flat panel display device having display areas with the appearance of rounded corners
A display device may include: a display unit including: a display area having a plurality of pixels to display an image; and a non-display area surrounding the display area; and a frame covering at least a portion of the non-display area, the frame having a rounded outer corner and an inner corner, wherein the plurality of pixels includes a first pixel disposed between the inner corner and a curved line or under the curved line, and wherein the display device is configured to operate the first pixel to constantly generate a first color while the image is displayed. |
| US10395577B2 |
Organic light emitting display device and method of driving the same
A method of driving an OLED display device includes receiving image data. A load value is determined for each sub-pixel. A first load value is set to a largest load value determined for each sub-pixel. A first correction factor is calculated that decreases as the first load value increases, when the first load value is greater than a first threshold. A second load value is calculated based on the image data and current contribution weights for the sub-pixels. A second correction factor is calculated that decreases as the second load value increases, when the second load value is greater than a second threshold. Either the first correction factor or the second correction factor is selected. The image data is converted into output image data based on the correction factor. An image corresponding to the output image data is displayed. |
| US10395574B2 |
System and methods for extracting correlation curves for an organic light emitting device
A system and method for determining and applying characterization correlation curves for aging effects on an organic light organic light emitting device (OLED) based pixel is disclosed. A first stress condition is applied to a reference pixel having a drive transistor and an OLED. An output voltage based on a reference current is measured periodically to determine an electrical characteristic of the reference pixel under the first predetermined stress condition. The luminance of the reference pixel is measured periodically to determine an optical characteristic of the reference pixel. A characterization correlation curve corresponding to the first stress condition including the determined electrical and optical characteristic of the reference pixel is stored. Characterization correlation curves for other predetermined stress conditions are also stored based on application of the predetermined stress conditions on other reference pixels. The stress condition of an active pixel is determined and a compensation voltage is determined by correlating the stress condition of the active pixel with the curves of the predetermined stress conditions. |
| US10395573B2 |
Display apparatus
According to an aspect, a display apparatus includes: a signal line or a scanning line coupled to a plurality of pixels arranged in a display region; a driver that supplies a drive signal via a resistor to the signal line or the scanning line; and an anomaly detector that monitors a response characteristic of a node between the resistor and the signal line or a node between the resistor and the scanning line. |
| US10395572B2 |
Display device and method of testing a display device
A display device includes a display panel including a display panel including pixels, a timing controller configured to calculate an on-pixel ratio of input image data provided from an external component, and a data driver configured to select a first gamma correction value from among a plurality of gamma correction values based on the on-pixel ratio, and configured to generate a data signal based on the input image data and the first gamma correction value. |
| US10395570B2 |
Mark and sign lighting device, method and system
A mark and sign illuminating device and system. The device is a device in which a transparent light guide layer (1203), a light reflecting layer (1204) and border rims (1251, 1252) are formed integrally. An LED illuminating light source LED1 and an LED illuminating light source LED2 are provided in the transparent light guide layer (1203). The reflective layer (1204) is provided with overlapping incidence of effective incident angles within the range of 360 degrees in the transverse direction and within the range of about 1 degree to about 179 degrees in the longitudinal direction, so that wide effective reflection angles and observation angles are formed. The advantage is that marks, signs and warning marks can be identified, seen and read more easily. |
| US10395569B2 |
Light fixture sign
A concealed light fixture sign includes a flange having stencil openings formed therein that define a message. A container extends from a rear surface of the flange and provides light through the stencil openings. The container is configured to be installed completely within a recess behind a mounting surface with the flange positioned substantially flush with the mounting surface. Translucent inserts positioned within the stencil openings are removable to provide access to an interior of the container after installation of the light fixture sign. |
| US10395566B2 |
Offset display holder with C-channel
A display holder includes an extruded member having a top surface from which extends a T-shaped grip portion for engagement by a gripper at the end of a pole. Spaced from the grip portion is a brace on the end of which is a web connected to a C-channel. The C-channel receives a display or sign such as a dowel in a sleeve of the display which allows the user to maximize sign size, head space or lines of sight. The C-channel also can be used to receive a block end hook, a cord suspender, or a clip. A ring may be provided through a hole in the web. The display holder is mounted or un-mounted safely from floor level in one single motion to a ceiling by magnets on the top surface or to a wall by magnets on the brace. |
| US10395565B2 |
Hardcase luggage with built-in name tag compartment
A luggage container with built-in external compartment, which includes a case having an outer side and an inner side and a drawer configured to be slid in and out of the case. The case includes a coupling portion formed on the inner side, the coupling portion protruding from the inner side, and the coupling portion is shaped to receive a fastening element. The case is shaped to form a space between a surface of an object onto which the case is coupled and a surface of the inner side to receive the drawer. The drawer is shaped to remain within the case when the drawer is pulled out of the case such that the case and the drawer are not separated even when the drawer is pulled out maximally. |
| US10395563B2 |
Method and apparatus for editing a digital map of a transport vehicle for transporting vehicles
A digital map of a transport vehicle for transporting vehicles includes one or more digital reference locations that are respectively associated with real reference locations of the transport vehicle. A method includes: ascertaining respective reference coordinates of the real reference locations relative to a reference coordinate system, so that the ascertained reference coordinates are associated with the corresponding digital reference locations; deriving respective coordinates of further digital locations of the digital map from the reference coordinates of the reference locations based on a derivation protocol, so that coordinates relative to the reference coordinate system are respectively associated with the further digital locations, so that an edited digital map of the transport vehicle is created, in which map coordinates relative to the reference coordinate system are associated with the digital locations. |
| US10395562B2 |
Combat medical simulators and associated systems and methods
Devices, systems, and methods appropriate for use in combat medical training are provided. In some instances, the combat medical simulators facilitate training of common field medical techniques including tracheostomy, wound care, tourniquet use, pneumothorax, cardiopulmonary resuscitation, and/or other medical treatments. Further, the combat medical simulators have joints that provide realistic ranges of motions to enhance the realism of the training experience. |
| US10395542B2 |
Drone traffic engineering
In one embodiment, a method includes receiving a request for a flight path for a drone, the request including information indicative of a source location within a geographical area and a destination location within the geographical area, modeling the geographical area including a plurality of geographical regions as a data network including a plurality of nodes, determining a network data path from a source node of the plurality of nodes corresponding to the source location to a destination node of the plurality of nodes corresponding to the destination location, determining a flight path for the drone based on the network data path, and transmitting data indicative of the flight path for the drone. |
| US10395539B2 |
Non-line of sight obstacle detection and localization
A non-line of sight obstacle detection and localization system and method of detecting and localizing a non-line of sight object include receiving reflections at a detection system of a moveable platform, the reflections including direct and multipath reflections, identifying the reflections associated with static targets to retain the reflections associated with moving targets, and distinguishing between line of sight objects and non-line of sight objects among the moving targets. The method also includes localizing the non-line of sight objects relative to the platform and indicating approaching non-line of sight objects among the non-line of sight objects, the approaching non-line of sight objects moving toward the platform on a path that intersects the platform. |
| US10395526B1 |
Road segment rating based on roadway communication
Methods, computer-readable media, systems and apparatuses for rating a road segment based on data received from one or more sensors distributed along the road segment. In some arrangements, a number of sensors along a road segment may be determined based on characteristics or features of the road segment. In at least some arrangements, the data received and/or processed from road segment sensors may be controlled based on current road segment conditions. For instance, in fair weather data from fewer than all sensors along a road segment may be received and/or processed because the likelihood of a dangerous condition is reduced. However, when current conditions indicate the potential for hazardous conditions (e.g., temperature near or below freezing, presence of moisture, untreated road segment, etc.) data from all sensors may be received and/or processed to ensure the most accurate information for an entire length of the road segment is obtained. |
| US10395525B1 |
Vehicle identification system
A vehicle identification system includes one or more displays associated with a vehicle, a transceiver, and a controller communicatively coupled to the transceiver. The one or more displays are located to be visible from an exterior of the vehicle. The controller is adapted to generate a first signal to be transmitted by the transceiver to a mobile communication device associated with a driver of the vehicle when it is determined that the vehicle is within a predetermined distance of a specific location. The mobile communication device associated with the driver is adapted to generate a second signal to be transmitted to the one or more displays. The second signal represents an indicator. |
| US10395521B2 |
Traffic management based on basic safety message data
The disclosure includes a system and method for managing traffic in a roadway system based on Basic Safety Message data (“BSM data”) included in a set of Basic Safety Messages (“BSMs”). The method may include wirelessly receiving a set of BSMs describing a set of vehicles traveling along the roadway system. Each BSM included in the set of BSMs may describe a specific vehicle included in the set of vehicles, including that vehicle's lane, speed and heading of travel. The method may include analyzing the BSM data to determine whether there is an imbalance of traffic flow among a first set of vehicles traveling towards a first heading and a second set of vehicles traveling towards a second heading. The method may include determining that the bidirectional lane will be reconfigured so that traffic in the bidirectional lane flows towards the second heading based on the imbalance of traffic flow. |
| US10395515B2 |
Sensor aggregation and virtual sensors
A sensor aggregator is disclosed that may instantiate virtual sensors providing virtual sensor data. Virtual sensor data may be based at least in part on data shared by transitory sensors that come into an environment associated with the aggregator. An aggregator may have local sensors, e.g., non-transitory sensors associated therewith or disposed therein, or mobile sensors operating in conjunction with or for the aggregator, that may be used to provide sensor data to the aggregator that may also be provided as sensor output from the aggregator. An aggregator may combine different sensor inputs to derive virtual sensors based on received sensor data. In an emergency, an aggregator may assist with exit strategies based conditions sensed in various locations to help route people away from problems. Multiple aggregators may share data and trust mechanisms employed to determine if received sensor data may be trusted/used by an aggregator. And, aggregators may operate to store and forward data, such as to a cloud service, on behalf of a sensor. Accounting/payment systems may be used. |
| US10395514B2 |
Alarm pull station having a removable actuator cover
An alarm pull station having a removable actuator cover and an actuator switch operatively coupled to the actuator cover to signal when the pull station is a normal mode, an alarm mode, or a maintenance mode corresponding to when the cover has been removed. |
| US10395512B2 |
Mobile signal unit, mobile operating unit and mobile defense system
A mobile signal unit is responsive to a mobile operating unit yet sufficiently compact and lightweight for unobtrusive connection to an item of clothing, a purse, and/or a backpack. It has a siren powered by gas or electricity. It has a wireless first interface, through which the siren can be remotely activated and/or deactivated by the mobile operating unit. The siren can be activated manually by an activation command that matches an activation code stored in a memory unit of the signal unit and/or the operating unit. The siren is automatically activated after the wireless connection to the operating unit if a connection signal strength of the operating unit falls below a threshold and/or the wireless connection to the operating unit is interrupted. |
| US10395506B2 |
Remote cooking systems and methods
A remote temperature monitoring system includes a first unit operatively connected to one or more temperature sensors for sensing the temperature of one or more materials or food items being cooked or heated. The first unit transmits the sensed temperature to a second unit that is located remotely from the first unit during heating. The second unit is programmable with the desired temperature and/or heating parameters of the item. By monitoring the temperature status of the item over time, the system determines when the food has reached the desired temperature or degree of cooking, and notifies the user. |
| US10395501B2 |
Mobile monitoring device
A mobile monitoring device, comprising a gas measurement device designed to read a value of a measured gas property of a gas and to provide a gas measurement signal dependent on the read value of the measured gas property; a body measurement device designed to read a value of a measured physical body property of a body of a person wearing the mobile monitoring device and to provide a body measurement signal dependent on the read value of the measured body property; and a control unit designed to receive the gas measurement signal and the body measurement signal and to control the mobile monitoring device dependent on a degree of correlation between a gas signal derived from the gas measurement signal and a body signal derived from the body measurement signal. |
| US10395498B2 |
Fire detection apparatus utilizing a camera
A fire detection device is provided that has a camera that captures a reference image and a measured image. A processor compares intensity of the measured image to intensity of the reference image and uses this comparison to determine if an alarm is generated to indicate the presence of fire. The intensity of the measured image may be the total number of photons of the measured image, and the intensity of the reference image may be the total number of photons of the reference image. In other arrangements, the intensity may be measured between individual corresponding pixels of the reference and measured images. |
| US10395491B2 |
Apparatus, systems, and methods for signal localization and differentiation
Apparatus, systems, and methods for providing transmission and localized reception of audio, visual, and tactile signaling are taught for a myriad of useful purposes, including embodiments that permit differentiation between selected groups of intended recipients to permit simultaneous use of multiple instances of this technology in close proximity, if desired. |
| US10395488B2 |
Systems and methods for generating haptic effects associated with an envelope in audio signals
Systems and methods for generating haptic effects associated with envelopes in audio signals are disclosed. One disclosed system for outputting haptic effects includes a processor configured to: receive an audio signal; determine an envelope associated with the audio signal; determine a haptic effect based in part on the envelope; and output a haptic signal associated with the haptic effect. |
| US10395483B2 |
Method, system, and computer program product for sports game
A computer implemented game involving analytics and real time data analysis. The game can allow players to predict and wager on the types of plays that have yet to occur, for example, in a football game. The game may utilize an algorithm that compares situational data in a game to stored data regarding similar situations in past games. The game can then provide a likelihood that a certain type of play can be performed, which may be interpreted as odds of a certain type of play. Users can then utilize this information to predict and wager on the upcoming play. Depending on the results of the play, users may win or lose their wager. |
| US10395482B2 |
Systems and methods for modifying selections available in a bonus game
In at least one embodiment, systems, methods and articles of manufacture provide for a game comprising a primary game and a bonus round comprising a plurality of player selectable elements, in which game an outcome of the primary game may include an eliminator symbol which functions to render unavailable for selection at least one of the player selectable elements. In one embodiment, the lowest value player selectable element is removed or rendered unavailable, thus effectively increasing the player's chances of selecting a higher value player selectable element. |
| US10395481B2 |
Gaming system, gaming device and method having secondary symbols associated with primary symbols
A gaming system including a plurality of generated primary symbols and at least one generated secondary symbol. If any generated primary symbol is associated with any generated secondary symbol, the gaming system provides an award based on the generated primary symbol being associated with the generated secondary symbol. |
| US10395480B2 |
Gaming machine with symbol accumulation
An embodiment may involve selecting a first bonus set of symbols associated with respective positions of each of a plurality of reels as a first bonus outcome event of the bonus game. The embodiment may further involve incrementing a bonus counter by a number of instances of a predetermined symbol, in the bonus symbol set, that do not contribute to any winning combination. The embodiment may also involve determining that the bonus counter is at least equal to a threshold number. The embodiment may additionally involve selecting a second bonus set of symbols associated with respective positions of each of the reels as a second bonus outcome event of the bonus game, where the second bonus set of symbols includes at least the threshold number of instances of the predetermined symbol, and where the second bonus set of symbols includes a winning combination. |
| US10395477B2 |
Systems and methods for tracking of non-wagering account associated with gaming environment
Systems and methods are disclosed for associating a player identifier with a financial account. The financial account can holds funds that are accessible through the player's use of a payment vehicle. Information associated with transactions using the payment vehicle can be used for player relationship purposes. |
| US10395476B2 |
Integrated gambling process for games with explicit random events
A gambling integrated game that includes an entertainment system engine that provides an entertainment game to a user, a real world engine that provides gambling games to one or more users, and a game world engine that monitors the entertainment game and provides gambling games when appropriate. The entertainment system engine provides an entertainment game that includes random events. When a random event occurs in the entertainment game, the entertainment system engine resolves the random event and provides the results of the random event to the game world engine. The game world engine receives the results of the random event and determines gambling results based upon the results of the random event. |
| US10395475B2 |
Gaming machine and a method of gaming thereon
Described herein is a gaming machine and, a method of gaming thereon, comprising: a symbol selector for selecting a plurality of symbols from a set of symbols during play of a game, the set of symbols including a plurality of function symbols; a display having at least a game area, the selected symbols being displayed in said game area; an outcome evaluator for determining that at least one predefined triggering criterion is satisfied; and a game area expander for expanding said game area in response to said at least one predefined triggering criterion being satisfied, such that at least one additional symbol of the set of symbols is displayed in an expanded game area. |
| US10395471B2 |
Apparatus, system and method for electronic gaming
A system for electronic gaming is described which includes a plurality of individual game stations each of which is constructed and arranged with a user interface. Upstream from each game station is a third party subsystem which includes a corresponding database. This third party subsystem is in data communication with each game station. Also upstream from the plurality of game stations is a gaming server subsystem which includes a database. A central determinate translator system is constructed and arranged in communication either directly or indirectly with each game station and provides a communication link and interface between the gaming server subsystem and each game station. |
| US10395470B2 |
Method and device for implementing wagering games requiring player input
A gaming table includes input sensors which are configured to receive multiple inputs from a player. The sensors are linked to a gaming table controller and are configured to receive different types of inputs from players at different times. One input may comprise a wager input in the form of one or more chips which are associated with the sensor. Another input may comprise a game play input, such as a spin input for a bonus game, received by a player placing their hand proximate to the sensor. |
| US10395469B2 |
Gaming machine
A gaming machine including a display that has a first display area and a second display area. The first display area displays a first prize and a second prize. The first prize has a first prize threshold and the second prize has a second prize threshold. The second display area displays an overflow prize, while the game controller contributes to the first prize at least a portion of the credit balance with respect to a wagering activity, and causes the display to display an increment of the overflow prize in response to the first prize having reached the first threshold. A payout mechanism configured to, in response to determining one of the first prize and the second prize is to be awarded, cause a payout associated with the one of the first prize and the second prize to be awarded and the incremented overflow prize. |
| US10395468B2 |
Gaming machine
A gaming machine having a game controller and a display. The game controller causes the display to display a feature wheel including a plurality of display slices. A first display slice is associated with a first prize of a plurality of prizes and has a respective variable size being dependent on the first prize and visually identifies the first prize relative to a second prize associated with a second display slice. |
| US10395466B2 |
Gaming machine
To facilitate and shorten the work of changing displayed content on the topper display device 211, a slot machine 1 includes: a gaming machine main body 5 configured to run a game; a topper display device 211 accommodating a display plate module 2117 for displaying a game related information, in such a manner that the display plate module 2117 is detachable from a side; a topper support mechanism 215 rotatably supports the topper display device 211 so that the topper display device 211 is capable of rotating in a horizontal direction on the gaming machine main body 5. |
| US10395465B2 |
Persistent device relationships in wagering game systems
In some embodiments a wagering game system comprises a personal area network device configured to render media content including results of a wagering game. The system can include a wagering game machine configured to determine and provide the wagering game results to the personal area network device. The wagering game machine can include a personal area network device transceiver configured to exchange data with the personal area network device, the data including the wagering game results, and a personal area network controller configured to detect the personal area network device, to procure an identification code for the personal area network device without player input, and to authenticate the personal area network device by use of the identification code. The system can also include a repository configured to store the identification code in association with a player identifier and to provide the identification code to the wagering game machine upon request. |
| US10395462B2 |
Authentication arrangement and method for use with financial transactions
An authentication arrangement for use in a network payment system for transacting a sale of merchandise over a network using an integrated circuit card is described, the arrangement comprising: a merchant server in communication with said network, said merchant server having at least a first item of merchandise for sale; a client terminal in communication with said network, said client terminal having an output device for reviewing said first item for sale, and an input device for initiating a purchase transaction to purchase said first item for sale, said client terminal being arranged to build a purchase message using information relating to a merchant identifier and financial transaction information obtained from said merchant server; a card reader for communicating with said integrated circuit card, said client terminal having means to generate a challenge message, said challenge message being generated from the information relating to the merchant identifier and an account number, means for receiving the challenge message at the card reader and for generating a value from the challenge message; said integrated circuit card having means for generating a cryptographic message from at least a part of said value, the card reader having means to generate an authentication token from at least a part of the cryptographic message, and said client terminal having means for transmitting at least part of the authentication token in a message for transmission via the network. |
| US10395461B2 |
Anti-counterfeiting features and methods of fabrication and detection
Aspects of the present disclosure include an anti-counterfeiting pattern that is identifiable by sheet resistance mapping metrology, a method of fabricating such an anti-counterfeiting device, and a method of detecting such an anti-counterfeiting device by imaging the pattern with sheet resistance mapping metrology. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US10395456B2 |
Noise-tolerant security system
A security system and method includes a tag that continues to function in the presence of LF noise by (i) detecting the LF noise, and (ii) generating an RF signal comprising information that causes a controller to issue a lock command. |
| US10395445B2 |
System and method for monitoring payload distribution and machine including same
A machine includes a frame, a suspension system mounted to the frame and including a plurality of struts, and a payload distribution monitoring system supported by the frame. The payload distribution monitoring system includes pressure sensors respectively arranged with the struts, a computer-readable medium bearing a payload distribution monitoring program, a controller, and an interface device. The controller is in operable communication with the pressure sensors to receive their signals and configured to execute the payload distribution monitoring program. The interface device is in operable communication with the controller and configured to display the payload distribution monitoring program's graphical user interface. The payload distribution monitoring program is configured to monitor the strut pressure signals for an unbalanced loading condition that occurs when a relative strut pressure differential, which is computed using the strut pressure signals from the pressure sensors, exceeds a differential limit. |
| US10395442B2 |
System and method for performing diagnostics on a DC-DC converter
In an example, a vehicle diagnostic system is disclosed. The vehicle diagnostic system includes a first DC-DC converter having an input and an output and a second DC-DC converter having an input and an output. The output of the first DC-DC converter is connected to the input of the second DC-DC converter at a first node, and the output of the second DC-DC converter is connected to the input of the first DC-DC converter at a second node. The vehicle diagnostic system includes a battery connected to a vehicle load and the first node and a redundant power source connected to the second node. The vehicle diagnostic system includes a control module that is configured to initiate operation of the first DC-DC converter and the second DC-DC converter to cause current re-circulation between the first DC-DC converter and the second DC-DC converter. |
| US10395439B2 |
Methods and apparatus for assisting in the maintenance of aircraft and other mobile platforms using occurrence probabilities of potential causes of a detected event
The present disclosure relates to health monitoring and maintenance of mobile platforms such as aircraft. In particular, onboard apparatus and methods and also ground-based apparatus and methods that cooperate in assisting with the maintenance of mobile platforms by facilitating diagnosis of events detected onboard mobile platforms while such mobile platforms are in operation (e.g., transit, flight) are disclosed. In various aspects, the present disclosure discloses apparatus and methods for handling and reporting the detection of events onboard mobile platforms, reporting predefined additional information associated with the event upon request from a ground facility, identifying one or more potential causes for the detected event and determining the occurrence probability for each potential cause identified. |
| US10395437B2 |
Adjusting components of cargo transportation units
In some examples, a controller detects a compromised condition of a component of a cargo transportation unit (CTU), determines a time of performing a next maintenance of the CTU, and controls adjustment of the component in response to detecting the compromised condition and based on the time of performing the next maintenance of the CTU. |
| US10395431B2 |
Overlay for camera field of vision
One or more computer processors generate an augmented reality overlay for camera field of vision based on a perspective of a display device. The one or more processors generate an overlay image that represents a field of view of an imaging device based at least on an orientation of the imaging device at a first location. The one or more processors generate a modified overlay image by modification of one or both of a size and an orientation of the overlay image based, at least in part, on differences between (i) a second location and an orientation of an image display device relative to (ii) the first location and the orientation of the imaging device. The one or more processors the modified overlay image using the image display device. |
| US10395429B2 |
Image processing apparatus and display control method
Aspects of the present invention include an apparatus comprising a recognition unit configured to recognize real object in an image. The apparatus may further comprise a determining unit configured to determine a stability indicator indicating a stability of the recognition, and a display control unit configured to modify a display of a virtual object according to the stability indicator. |
| US10395426B2 |
Augmented reality system and method
A computer-implemented method, computer program product, and computing system for receiving a unique identifier on a client electronic device. The unique identifier is associated with at least one IT component. Status information is obtained concerning the at least one IT component. A visual representation of the at least one IT component is generated on a display screen of the client electronic device. A graphical representation of the status information is superimposed onto the visual representation of the at least one IT component. |
| US10395423B2 |
Apparatus and method for rendering adaptive mesh refinement (AMR) data
An apparatus and method are described for rendering adaptive mesh refinement data. For example, one embodiment of a graphics processing apparatus comprises: a tree data structure generator to transform adaptive mesh refinement (AMR) data into a multi-octree or kd-tree data structure, respectively; an interpolator to implement an interpolation scheme based on the multi-octree or kd-tree data structure to generate interpolated results, the interpolation scheme using repeated linear interpolation; and a ray tracing-based renderer to use the interpolated results to render image frames using ray tracing techniques. |
| US10395422B2 |
Participating media baking
According to one embodiment, a method includes identifying a scene to be rendered, pre-computing one or more lighting elements within the scene, including creating a plurality of light scattering tables, performing, during the pre-computing, a computation of light extinction and light in-scattering within participating media of the scene, utilizing the plurality of light scattering tables, and during a ray tracing of the scene, approximating spatially heterogeneous media of the scene as spatially homogeneous media of the scene by performing a volume intersection for each light ray associated with the spatially heterogeneous media of the scene to determine a homogeneous scattering coefficient for the light ray, and applying to the spatially heterogeneous media of the scene one of the plurality of light scattering tables, where each of the plurality of light scattering tables corresponds to a single homogeneous scattering coefficient, and a table lookup is adjusted for the one of the plurality of light scattering tables utilizing an analytic correction factor in order to apply the one of the plurality of light scattering tables with a different homogeneous scattering coefficient. |
| US10395419B1 |
Non-destructive multi-resolution surface clipping
In an example embodiment, a technique is provided for surface mesh clipping. A surface mesh file and clip objects are received, and a unique identifier of a clip object is added to each node of a spatial index of the surface mesh that intersects the respective clip object. For any currently visible nodes, clip geometries and a series of meshes that partition the node into clipped regions are computed and stored in a clip file separate from the surface mesh file. Any non-currently visible nodes are computed and the clip file updated in response to display of the respective node. A clipped surface mesh is rendered by assembling regions of the surface mesh that are not affected by clip objects and clipped regions from the clip file, and the rendered clipped surface mesh is displayed. |
| US10395417B2 |
Data plot processing
A method, system, and/or computer program product processes a data plot comprising a plurality of data points for inclusion of additional information content. A space of the data plot is divided into subspaces, where each subspace contains at least one data point of the data plot. An available area on a display for each subspace is computed, and then a compressed information representation for each subspace is computed based on information about at least one data point contained in each subspace and a computed available area for each subspace. An available area of each subspace is computed based on a maximum size of a shape that can fit within each subspace. The data plot is displayed, where each unit of compressed information is displayed adjacent to a corresponding group of data points from the data plot. |
| US10395415B2 |
Method of fast intersections in ray tracing utilizing hardware graphics pipeline
Fast intersection in ray tracing between secondary rays and geometric objects. An ordinary GPU hardware is utilized as a means for intersecting scene geometry with a large group of rays. A reduction of computational complexity, reduction of power consumption and performance improvement are gained, making this ray tracing method suitable for battery powered devices. |
| US10395413B2 |
Dynamic user interfaces
A method for displaying and controlling an animation in a user interface on multiple electronic devices comprising: providing a first computer system comprising a first computer processor and a first electronic display coupled to the first computer processor, wherein the first computer processor is programmed to send animation instructions comprising a plurality of animation pathways, the animation pathways executed independently of one another with percentage completion to generate and display on the first electronic display of the first computer system a user interface (UI), wherein the animation pathways have different relative velocities as a function of percentage completion regardless of the duration(s) of the animation pathways; and sending the animation instructions to a second computing device comprising a second computer processor and a second electronic display coupled to the second computer processor, wherein the second computer processor is programmed to send the animation instructions comprising a plurality of animation pathways, the animation pathways executed independently of one another with percentage completion to generate and display on the second electronic display of the second computer system a user interface (UI), wherein the animation pathways have different relative velocities as a function of percentage completion regardless of the duration(s) of the animation pathways. |
| US10395410B2 |
System and method for real-time pose-based deformation of character models
Systems and methods for animating a character model by deforming the character model based on poses. Embodiments may contain a modeling component in which a user may create a character model that contains a rig representing animation controls applied to the model, and geometric/graphic parameters for graphically rendering the model. The user also may create directed graphs that contain nodes representing operations that act on the character model and directional connections representing data flow between nodes. The embodiments may contain a compiling component that convert a directed graph into a sequence of instructions that perform the operations denoted at the nodes. The embodiments provide tools and methods to reduce redundancies in the sequence of instructions producing an optimized version of instruction sequence. The resulting instructions are then convertible into machine code for running on a video game device or loaded into a plug-in of a graphic rendering engine. |
| US10395409B2 |
Method and system for real-time virtual 3D reconstruction of a live scene, and computer-readable media
A method, system and computer-program product for real-time virtual 3D reconstruction of a live scene in an animation system. The method comprises receiving 3D positional tracking data for a detected live scene by the processor, determining an event by analyzing the 3D positional tracking data by the processor, comprising steps of determining event characteristics from the 3D positional tracking data, receiving pre-defined event characteristics, determining an event probability by comparing the event characteristics to the pre-defined event characteristics, and selecting an event assigned to the event probability, determining a 3D animation data set from a plurality of 3D animation data sets assigned to the selected event and stored in the data base by the processor, and providing the 3D animation data set to the output device. |
| US10395408B1 |
Systems and methods for rendering vector shapes
A vector shape may have a first edge and a second edge that defines an intersection feature. A distance map may be divided into texels. The distance map may characterize the vector shape with a flag field, a first distance field, and a second distance field. The flag field may indicate the use of one-distance field rendering or two-distance field rendering for a given texel. The use of two-distance field rendering for the given texel may include use of the first distance field characterizing a first distance between the given texel and the first edge and the second distance field characterizing a second distance between given the texel and the second edge. Based on the use of two-distance field rendering for the given texel, the vector shape corresponding to the given texel may be rendered based on the first distance field and the second distance field. |
| US10395404B2 |
Image processing device for composite images, image processing system and storage medium
According to one embodiment, an image processing device includes a subject image acquisition module, a first clothing image acquisition module and a second clothing image generator. The subject image acquisition module is configured to acquire subject images which are images of a subject successively picked up by an image pickup module. The first clothing image acquisition module is configured to acquire a first clothing image which is an image of clothes worn by the subject included in the subject images. The second clothing image generator is configured to adjust transparency of a pixel at a predetermined place of pixels constituting the first clothing image, and generate a second clothing image different from the first clothing image. |
| US10395402B2 |
Apparatus, system and method for embedding data in an image file
An image processing device is provided to generate electronic document data representative of at least one physical document having at least one page. A unique document identifier value is determined to identify the at least one page, the unique document identifier being determined based on an end document identifier value associated with an electronic document project managed by a document management system. An annotated electronic document is generated by embedding data representing the unique document identifier within the at least one page of the electronic document data. An information file is generated and includes at least one characteristic associated with the annotated electronic document. The information file and annotated electronic document are communicated to the document management system for incorporation into an associated electronic document project stored therein. |
| US10395401B2 |
Method for efficient parallel visualizing vector graphic
A method for efficiently visualizing parallel vector data rapidly renders high-quality complex vector graphics. The present invention provides a scanline algorithm for calculating and rendering on contour lines, which parallel-rasterizing on the contour lines. The algorithm firstly rasterizes the contour lines into segments corresponding to output image pixels. On each segment, color values are analytically calculated, or approximately obtained by a sampling algorithm. Contour rasterizing is efficiently completed in parallel. By analytical calculation or 32-bit sampling, high quality results are obtained. The present invention adapts parallel prefixes and algorithms in a scanline direction to obtain covering information for each pixel and generate filled areas. Finally, the contour line segments and the filled areas of the vector graphics are rendered in the output image. The present invention is entirely based on parallel many-core computing devices for real-time high-quality vector graphic rendering with hardware acceleration. |
| US10395399B2 |
Method for improving the print quality of graphic elements
A method for improving the print quality of graphic elements, in particular vectorized letter graphics, in PDF documents in the prepress stage of a printing process by using a computer, includes analyzing the page content of the PDF document by using the computer and saving the page content in a suitable data structure, searching the data structure for graphic elements, in particular letter graphics, that fulfill specific predefined criteria relating to an evaluation of the height and width of the graphic paths of graphic elements that are present in the PDF document, by using the computer, converting the selected graphic elements into image masks by rendering the selected graphic elements on the computer and substituting the generated image masks for the originally selected graphic elements in the PDF document by using the computer. The PDF document with the generated image masks are printed on a printing machine. |
| US10395397B2 |
Metal artifacts reduction for cone beam CT
A method for processing volume image data obtains two-dimensional projection images of a subject on an image detector, wherein each of the images has the detector and a radiation source at a different scan angles. The image data is arranged as an image stack with corresponding pixel data from the detector in register for each of the images in the stack. A partial subset of projection images showing a metal object is identified. Information relative to the metal object propagates from the partial subject of projection images to the remaining images of the stack. For each of one or more stacked projection images, region growing defines a metal mask and adjusts image data values defined by the mask. The volume image data is reconstructed using region growing results. A 2D image is rendered and displayed from the reconstructed volume image data. |
| US10395395B2 |
Virtual projection images for tomosynthesis artifact reduction
A method for tomosynthesis volume reconstruction acquires at least a prior projection image of the subject at a first angle and a subsequent projection image of the subject at a second angle. A synthetic image corresponding to an intermediate angle between the first and second angle is generated by a repeated process of relating an area of the synthetic image to a prior patch on the prior projection image and to a subsequent patch on the subsequent projection image according to a bidirectional spatial similarity metric, wherein the prior patch and subsequent patch have n×m pixels; and combining image data from the prior patch and the subsequent patch to form a portion of the synthetic image. The generated synthetic image is displayed, stored, processed, or transmitted. |
| US10395392B1 |
Learning method and learning device for strategic transforming RGB training image sets into non-RGB training image sets, to be used for learning object detection on objects of images in non-RGB format, by using cycle GAN, resulting in significantly reducing computational load and reusing data
A method for learning transformation of an annotated RGB image into an annotated Non-RGB image, in target color space, by using a cycle GAN and for domain adaptation capable of reducing annotation cost and optimizing customer requirements is provided. The method includes steps of: a learning device transforming a first image in an RGB format to a second image in a non-RGB format, determining whether the second image has a primary or a secondary non-RGB format, and transforming the second image to a third image in the RGB format; transforming a fourth image in the non-RGB format to a fifth image in the RGB format, determining whether the fifth image has a primary RGB format or a secondary RGB format, and transforming the fifth image to a sixth image in the non-RGB format. Further, by the method, training data can be generated even with virtual driving environments. |
| US10395388B2 |
Broad area geospatial object detection using autogenerated deep learning models
A system for automated geospatial image analysis comprising a deep learning model that receives orthorectified geospatial images, pre-labeled to demarcate objects of interest. The module presents marked geospatial images and a second set of unmarked, optimized, training geospatial images to a convolutional neural network. This process may be repeated so that an image analysis software module can detect multiple object types or categories. The image analysis software module receives orthorectified geospatial images from one or more geospatial image caches. Using a multi-scale sliding window submodule, image analysis software scans geospatial images, detects objects present and geospatially locates them. |
| US10395387B2 |
Method and apparatus for detecting a utilization of an electronic device by a driver, for a vehicle
A method includes a reading-in step in which at least one sensor signal is read in via an interface to a sensor disposed in the vehicle, the sensor signal representing at least one current parameter of the electronic device and/or of the driver in the vehicle. The method furthermore includes a comparing step in which the sensor signal is compared with at least one stored utilization signal that represents a utilization of the electronic device by the driver while driving the vehicle. The method further includes an outputting step in which a detection signal is outputted if a predetermined correlation exists between the sensor signal and the utilization signal, in order to indicate the detected utilization of the electronic device. |
| US10395379B2 |
Image object tracking method and apparatus
An image object tracking method and apparatus are provided. The image object tracking method includes the steps of: determining a feature point of a target object in a first frame, determining a prediction point of the feature point in a second frame, calculating an estimated rotation angle of an image capturing device according to a distance between the coordinate of the prediction point and the coordinate of the feature point and a distance between the image capturing device and the target object, calculating a lens rotation angle of the image capturing device rotated from a time point that the first frame is captured to a time point that the second frame is captured according to a piece of inertial measurement information provided by an inertial measurement unit, and determining whether the prediction point corresponds to the feature point by comparing the estimated rotation angle and the lens rotation angle. |
| US10395371B2 |
Systems and methods for adaptive histopathology image unmixing
The present invention relates to systems and methods for adaptively optimizing broadband reference spectra for a multi-spectral image or adaptively optimizing reference colors for a bright-field image. The methods and systems of the present invention involve optimization techniques that are based on structures detected in an unmixed channel of the image, and involves detecting and segmenting structures from a channel, updating a reference matrix with signals estimated from the structures, subsequently unmixing the image using the updated reference matrix, and iteratively repeating the process until an optimized reference matrix is achieved. |
| US10395368B2 |
Methods and systems for assessing histological stains
The present disclosure includes methods of assessing a histologically stained specimen based on a determined color signature of a region of interest of the specimen. Such assessments may be performed for a variety of purposes including but not limited to assessing the quality of the histological stain, as part of identifying one or more biologically relevant features of the image, as part of differentiating one feature of the image from other features of the image, identifying an anomalous area of the stained specimen, classifying cells of the specimen, etc. Also provided are systems configured for performing the disclosed methods and computer readable medium storing instructions for performing steps of the disclosed methods. |
| US10395367B2 |
Magnetic resonance imaging apparatus
A magnetic resonance imaging apparatus according to embodiments includes processing circuitry. The processing circuitry is configured to detect, defining at least either intervertebral discs or vertebral bodies as target regions, target region information indicative of a position and a direction of each target region for each of a plurality of target regions included in a spine of a subject based on an image in which the spine is imaged; select target regions of imaging subjects out of the target regions based on the target region information; and cause a display to display, regarding the target regions, information representing imaging areas that concern the target regions of imaging subjects and information representing imaging areas that concern other target regions in different display forms. |
| US10395365B2 |
Method, computer and imaging apparatus for determining an imaging parameter for an imaging procedure
In a method and computer for determining an imaging parameter for an imaging procedure, a patient-specific imaging value for imaging an image data set is provided to a computer. An imaging parameter is determined in the computer by applying a trained imaging rule to the patient-specific imaging value. The trained imaging rule is based on a number of training data sets, wherein the training data sets each includes at least one patient-specific training imaging value and at least one training imaging parameter and at least one training quality evaluation. The complex influences of the patient-specific imaging values and the imaging parameters on the result of imaging can be quantified thereby. Allocation of the training quality evaluation by individual operators or specific groups of operators makes it possible to adjust the image recording parameters flexibly and individually. The imaging parameter can be determined such that the result of imaging is individually adjusted to an operator. |
| US10395363B2 |
Image processing device
According to the image processing device of the present invention, the binarization image having increasing assuredness can be generated by extracting the metal piece from the original image with the graph cut processing. The image processing device of the present invention is the system that executes an image trimming from near the center of the intermediate region after the metal piece is divided relative to the image of the roughly extracted binarization image near the center of the intermediate region in that it is difficult to decide whether it belongs to the metal piece or not. Following such steps, the intermediate region can be assuredly trimmed while executing the image trimming in the region as small as possible. |
| US10395359B2 |
Adaptive local threshold and color filtering
Methods and systems for detecting defects on a wafer using adaptive local thresholding and color filtering are provided. One method includes determining local statistics of pixels in output for a wafer generated using an inspection system, determining which of the pixels are outliers based on the local statistics, and comparing the outliers to the pixels surrounding the outliers to identify the outliers that do not belong to a cluster of outliers as defect candidates. The method also includes determining a value for a difference in color between the pixels of the defect candidates and the pixels surrounding the defect candidates. The method further includes identifying the defect candidates that have a value for the difference in color greater than or equal to a predetermined value as nuisance defects and the defect candidates that have a value for the difference in color less than the predetermined value as real defects. |
| US10395356B2 |
Generating simulated images from input images for semiconductor applications
Methods and systems for generating a simulated image from an input image are provided. One system includes one or more computer subsystems and one or more components executed by the one or more computer subsystems. The one or more components include a neural network that includes two or more encoder layers configured for determining features of an image for a specimen. The neural network also includes two or more decoder layers configured for generating one or more simulated images from the determined features. The neural network does not include a fully connected layer thereby eliminating constraints on size of the image input to the two or more encoder layers. |
| US10395355B2 |
Computer-implemented methods, computer readable medium and systems for a precision agriculture platform
A computer platform implements a precision agriculture system that predicts output conditions, such as diseases, salt damage, soil problems, water leaks and generic anomalies, for orchards under analysis. The computer platform stores site and crop datasets and processed satellite image for the orchards. An orchard data learned model predicts a propensity for existence of output conditions associated with the permanent crops based on the data values for the variables of the site and crop datasets. Also, a satellite model predicts a propensity for existence of the output conditions at the orchard based on processed satellite images. A precision agriculture management model is disclosed that integrates the orchard data learned model with the satellite model to accurately predict the output conditions. |
| US10395354B2 |
Conductive film, display device having the same, and method of evaluating conductive film
In a conductive film, a method of evaluating a pattern in the conductive film, and a display device, thin metal lines of a wiring portion is formed in a wiring pattern having quadrilateral shapes of which angles are maintained and pitches are made to be irregular. From at least one point of view, in frequencies of the moirés that are equal to or less than a frequency threshold value and are calculated for each color from two peak frequencies and two peak intensities of 2DFFT spectra of transmittance image data of rhomboid wiring patterns which are not made to be irregular and luminance image data of pixel array patterns of the respective colors at the time of lighting up for each single color, the thin metal lines has a quadrilateral wiring pattern in which angles of rhomboid shapes of rhomboid wiring patterns, each of which allows the indicator of evaluation of moirés to be equal to or less than the evaluation threshold value, are made to be irregular in a predetermined range. The indicator of evaluation is calculated from evaluation values of the moirés of the respective colors obtained by applying human visual response characteristics in accordance with an observation distance to intensities of the moirés equal to or greater than an intensity threshold value. |
| US10395353B2 |
Model-based scatter in multi-modality multi-energy SPECT reconstruction
In SPECT reconstruction, multi-modal reconstruction is combined with model-based multi-energy image formation. The scatter modeling of the model-based image formation uses resampling to facilitate convolution with the scatter kernels while maintaining resolution for the multi-energy projection. This combination of multi-modal and model-based multi-energy image formation simultaneously addresses the inaccuracy of the image formation process for complicated energy spectra and image blurring due to degradation of resolution. Varying the reconstruction by iteration may provide some of the benefits while reducing computational burden. |
| US10395352B2 |
Automatic compensation for the light attenuation due to epidermal melanin in skin images
Melanin is an effective absorber of light and is able to dissipate the majority of light absorbed by the pigment. This can mask the absorbance of biomolecules of interest such as hemoglobin when imaging skin tissue. Melanin is the primary determinant of skin color which can vary between individuals as well as within individuals (due to the presence of portions of skin with more or less pigment as well as features such as freckles and moles). Described herein are methods for compensating for melanin absorption at the pixel level of an image, thereby allowing for more accurate imaging of concentration and distribution of biomolecules of interest in a tissue portion. |
| US10395348B2 |
Image pickup apparatus, image processing apparatus, and control method of image pickup apparatus
An image pickup apparatus includes an image capturing unit, an optical system, and a control unit. The control unit causes the image capturing unit to capture images while moving an in-focus position of the optical system to a plurality of positions to form a plurality of images with different in-focus positions, and causes the image capturing unit to capture images with an aperture set to a depth of field deeper than depths of field for the plurality of images with the different in-focus positions to form a reference image. A combining unit compares the reference image to the plurality of images with the different in-focus positions, and combines images using the plurality of images with the different in-focus positions and the reference image based on a result of the comparison. |
| US10395347B2 |
Image processing device, imaging device, image processing method, and image processing program
In a case where IR data of a near-infrared light image is data in which a visible light component and a near-infrared light component coexist, a point image restoration process is performed on the IR data using a first point image restoration filter based on a first point spread function for visible light of the optical system and a second point image restoration filter based on a second point spread function for near-infrared light of the optical system. An appropriate point image restoration process is performed on the IR data that is captured in a time zone of twilight or dawn by performing weighted averaging on a point image restoration process using the first point image restoration filter and a point image restoration process using the second point image restoration filter using a first gain α and a second gain β according to a light amount ratio between visible light and near-infrared light at the time of capturing the IR data. |
| US10395345B2 |
Applying different motion blur parameters to spatial frame regions within a sequence of image frames
First and second spatial frame regions are identified in a sequence of motion picture image frames captured at a high frame rate. Different motion blur parameters are determined for each of the first and second spatial frame regions. First and second intermediate frame sequences having frame rates less than the capture frame rate are generated from the original frame sequence. The first motion blur parameter is applied to the first intermediate frame sequence and the second motion blur parameter is applied to the second intermediate frame sequence. The first and second spatial frame regions in the corresponding first and second intermediate frame sequences are composited to produce an output frame sequence having different motion blur in different regions of the scene. |
| US10395344B2 |
Image processing method
A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image. |
| US10395343B2 |
Method and device for the real-time adaptive filtering of noisy depth or disparity images
A method and a device for filtering the aberrations of disparity or depth images using an adaptive approach are described. The method allows the local filtering of those points which are not spatially coherent in their 3D neighborhood, according to a criterion derived from a geometrical reality of the transformations carried out on the light signals. Advantageously, the noise filtering method may be applied to a dense depth image or to a dense disparity image. |
| US10395339B2 |
Data processing systems
In a data processing system, an input data array to be downscaled is split into plural parts along its horizontal extent and the different parts of the input data array are then provided to respective scalers of the data processing system and are respectively downscaled by those scalers to provide a plurality of downscaled output parts. The plural downscaled output parts are then combined (merged) to provide the desired downscaled output data array. |
| US10395338B2 |
Virtual lens simulation for video and photo cropping
In a video capture system, a virtual lens is simulated when applying a crop or zoom effect to an input video. An input video frame is received from the input video that has a first field of view and an input lens distortion caused by a lens used to capture the input video frame. A selection of a sub-frame representing a portion of the input video frame is obtained that has a second field of view smaller than the first field of view. The sub-frame is processed to remap the input lens distortion to a desired lens distortion in the sub-frame. The processed sub-frame is the outputted. |
| US10395334B2 |
Three-dimensional deposition device and three-dimensional deposition method
Provided is a signal processing device including: a determination unit configured to determine a state of software associated with image processing on an input image signal indicating an image captured by a medical apparatus; and an output control unit configured to have a first processed image signal that is the input image signal on which image processing has been performed by the software selectively outputted, on the basis of a result of determination of the state of the software. |
| US10395329B2 |
Method for developing individualized athletic training program
The ability to use data from tests of maximum aerobic capacity to determine the ventilatory threshold and point of respiratory compensation (RCP) is useful for coaches, athletes, and other disciplines in the development of training schemes. Current methods for determining the RCP generally involve identifying deflections in respiratory variables when examined along minute ventilation. The present disclosure describes a novel method for crafting training programs by determining the RCP using standard scores (Z scores) for minute ventilation and oxygen consumption. This method offers further benefits as it is not reliant on visual determination of changes in slope of variables of interest, which can often lead to inaccuracy due to human error. |
| US10395325B2 |
Legal document search based on legal similarity
A method and system are provided for performing a legal document search. The method includes finding, by a processor, for each of a plurality of documents, a respective law clause related thereto, to obtain a plurality of related law clauses. The method further includes constructing, by the processor, a graph having nodes defined by the plurality of documents and the plurality of related law clauses and having edges defined by (1) relations between the plurality of documents and the plurality of related law clauses and (2) relations between the plurality of documents. The method further includes identifying, by the processor, from the plurality of documents, one or more candidate documents that are similar to an input query document by mining the graph using similarity criteria. |
| US10395322B2 |
Correlating resource usage data to a waste scoring system
A method for correlating energy usage data and water usage data to a waste scoring system is described. In one embodiment, the method includes receiving energy usage data and water usage data from a plurality of users, identifying at least one user group from the plurality of users based on predetermined parameters, and calculating average energy usage and average water usage for each of the user groups. The energy usage data and water usage data received for an individual user may then be compared to the calculated average energy usage and calculated average water usage for at least one of the user groups, and a general waste score may be calculated for the individual user. In some cases, a plurality of sub-waste scores may be calculated indicating factors of energy usage and factors of water usage for the individual user. |
| US10395318B2 |
System and method for administering insurance discounts for mobile device disabling technology
A system and method for processing and administering insurance policy premium discounts for mobile device disabling technology to promote safer driver is disclosed. An insurance policy premium discount is determined based on the level of disabling technology implemented by a user on a user's mobile device. |
| US10395315B2 |
System and method for processing and displaying quantity information during user-configurable time periods
A system and method for displaying quantity related information determined for a plurality of time periods are described. According to one method, a trader may define one or more time periods for which a trading application may determine traded quantities, traded buys, traded sells, or other quantity related information at a plurality of price levels during the defined time periods. The trading application may then graphically display the quantities for each time period in relation to the static axis of prices. The method further includes periodically updating the displayed traded quantity to reflect the quantity during the defined time period, where the quantity is updated based on subsequent market updates that are received from the exchange for the tradable object. |
| US10395312B2 |
System and method for proactively offering financing offers to customers of E-commerce websites
A method and system for proactively offering financing offers to customers of e-commerce websites are provided. The method includes collecting data related to a customer associated with a customer node, upon identification that a customer logs on to an e-commerce website; generating at least one customer characteristic of the customer based on the collected data; computing an adaptive credit standing of the customer based on the at least one customer characteristic; determining whether the adaptive credit standing meets a credit standing threshold associated with at least one product of interest; and upon determining that the adaptive credit standing meets the credit standing threshold, providing at least one financing offer to the customer associated with the customer node. |
| US10395305B2 |
Distribution channel using audio/visual recognition
Systems and methods are provided for providing a platform to provide virtual storefronts to consumers. Environmental elements are associated with specific consumer services on computer server. A user in the environment takes audio or visual recordings of an environmental element and uploads the recordings to the server. The server determines the appropriate consumer service associated with the recorded environmental element and provides the user with a reference to the service. Accordingly, any space, such as a bus stop, subway or train terminal, movie theater, or airport, may be turned into a virtual store. |
| US10395302B2 |
Matching techniques for data transaction requests with private attributes
A computer system is provided that includes a paired list of data transaction requests on which a matching process is performed. There are multiple different types of data transaction requests that are stored in the paired list including data transaction requests with midpoint attributes and data transaction requests with discretion attributes. The computer system may determine how the multiple different types of data transaction requests may be match against each other. Two matching processes can be used to determine if a match exists between the first and second sides of the paired list. Matches that are determined at private values are not disseminated to third-parties via public market data feeds. |
| US10395301B2 |
Method, medium, and system for using a combination of batch-processing and on-demand processing to provide recommendations
Systems and methods described herein, which utilize a combination of batch-processing and on-demand processing to provide recommendations, can include database(s) that store client data, item data, and executable code for composable algorithms that utilize the client data and/or the item data to provide recommendations. The system also includes a batch-process resultsP data store that stores results of composable algorithms executed using batch-processing. Additionally, the system includes an algorithm engine that accepts calls to composable algorithms and output results thereof. The algorithm engine determines which called composable algorithms are designated as being executable using batch-processing, and which are designated as being executable using on-demand processing. The algorithm engine returns results of called composable algorithms designated as being executable using on-demand processing by executing the executable code thereof, and returns results of called composable algorithms designated as being executable using batch-demand-processing by obtaining the results from the batch-process results data store. |
| US10395290B1 |
Location-based remote customer service
Provided are, among other things, systems, methods and techniques for providing remote location-based customer service for in-store customers. One such system includes: (a) a central server; (b) wireless transceivers coupled to the central server at different locations within each of multiple different retail shopping sites; and (c) handheld wireless devices, carried by customers at such retail shopping sites and in wireless communication with such wireless transceivers. Each of the handheld wireless devices is configured with a user interface that allows a customer to designate a user-interface element to request a customer-service session. Upon designation of the user-interface element on one of such handheld wireless devices, the request is forwarded to the central server. The central server establishes a two-way real-time communication link between the handheld wireless device and a customer-service representative. |
| US10395282B2 |
Coupon placement within an advertisement
A computer-implemented method for generating coupons is provided. The method comprises receiving a query for a coupon from a publisher for an ad unit; wherein said ad unit is designed by a third party designer and comprises certain visually perceptible elements; responsive to receiving the query determining if a coupon should be generated for the ad unit; if it is determined that a coupon should be generated for the ad unit, then: (A) retrieving stored data to corresponding to the ad unit; (B) using the stored data, to automatically generate a coupon for displaying together with the ad unit; wherein said coupon includes elements that visually correspond to the visually perceptible elements of the ad unit; and (C) transmitting said coupon to the publisher for displaying with the ad unit. |
| US10395278B2 |
Mobile device detection and engaging
Mobile device detecting and engaging are described. A server can determine that a mobile device has connected with a wireless network at a physical location. The server can provide a captive portal of the wireless network to the mobile device to receive contact information for the mobile device. The server can then provide a message including information related to the physical location to the mobile device using the contact information. |