| Document | Document Title |
|---|---|
| US09866429B2 |
Transparent PSTN failover
Novel tools and techniques for implementing Transparent PSTN Failover. In some embodiments, a VoIP switch might receive a call request for connection between a calling party at a calling telephone number (“TN”) and a called party at a called TN. Based on a determination that connection via a session border controller (“SBC”) between the VoIP switch and an Internet Protocol (“IP”) gateway has been lost, the VoIP switch might route the call request to a PSTN redirect TN through the PSTN. One of the Class 5 switch of the PSTN or the IP gateway might replace the redirect TN with the called TN, based on a determination that the redirect TN represents a PSTN failover. The IP gateway may then route the call request to an IP PBX for terminating (establishing) the call connection between calling party and called party, without interception by an operator, receptionist, or auto attendant. |
| US09866427B2 |
Multi-stage switch fabric fault detection and handling
In some examples, a switching system includes a plurality of fabric endpoints and a multi-stage switching fabric having a plurality of fabric planes each having a plurality of stages to switch data units between any of the plurality of fabric endpoints. A fabric endpoint of the fabric endpoints is configured to send, to a switch of a first one of the stages and within a first fabric plane of the plurality of fabric planes, a self-ping message destined for the fabric endpoint. The fabric endpoint is configured to send, in response to determining the fabric endpoint has not received the self-ping message after a predetermined time, an indication of a connectivity fault for the first fabric plane. |
| US09866425B1 |
Systems and methods for operations, administration and maintenance (OAM) in the physical coding sublayer (PCS)
Systems and methods described herein provide a method for operation, administration and maintenance (OAM) of data message transmission. The method comprises reading a transmit register of a transmitter associate with a first management entity to determine a transmit status of the transmit register. The method further comprises loading a data message into the transmit register when the transmit status of the transmit register indicates availability. The method further comprises embedding the data message as an out-of-band message with physical code sublayer modulation, and transmitting the out-of-band message on the physical code sublayer to a receiver associated with a second management entity. A transmit state machine of the transmitter and a receive state machine of the receiver establish a handshake to allow the out-of-band message to be passed asynchronously. |
| US09866424B2 |
Business services dashboard
Novel tools and techniques are provided for implementing a business services dashboard. In some embodiments, a method might comprise defining relationship(s) between at least one technology service and at least one business service provided by an enterprise, and receiving data associated with real-time technical events corresponding to changed conditions in one or more technology services utilizing at least one technology asset. Each defined relationship might indicate a dependence on the one or more technology services by one or more business services. The method might further comprise identifying, based on the defined relationship(s), one or more business events that impact the one or more business services of the enterprise, as a result of the changed condition. Business user views and technical user views might be generated and sent to user devices associated with respective business and technical group users. Corresponding system and apparatus may be provided. |
| US09866423B2 |
Non-uniform constellations
A method for generating a non-uniform constellation is provided. The method comprises the step of performing a first process, the first process comprising the steps of: obtaining a first constellation defined by one or more parameter values; and generating a second constellation based on the first constellation using a second process. The second process comprises the steps of: obtaining a set of candidate constellations, wherein the set of candidate constellation comprises the first constellation and one or more modified constellations, wherein each modified constellation is obtained by modifying the parameter values defining the first constellation; determining the performance of each candidate constellation according to a predetermined performance measure; selecting the candidate constellation having the best performance as the second constellation. |
| US09866420B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
A method is presented for receiving broadcast signals. The broadcast signals are received. The received broadcast signals are demodulated by an Orthogonal Frequency Division Multiplex (OFDM) scheme. A signal frame is parsed from the demodulated broadcast signals. Data in the parsed signal frame is bit interleaved. The bit deinterleaving includes block deinterleaving the data with each set of a number of bit groups. The number of bit groups is based on modulation type. When the modulation type is 16 Quadrature Amplitude Modulation (QAM), the number of bit groups is 4. The block deinterleaved data is group-wise deinterleaved by a unit of the bit group and parity deinterleaving parity bits of data in the group-wise deinterleaved data. The bit deinterleaved data is decoded. |
| US09866419B2 |
Transmission apparatus, reception apparatus, and communication system
A transmission apparatus that transmits a block signal including a plurality of data symbols, includes a data-symbol generation unit that generates data symbols; a fixed-symbol arrangement unit that arranges a data symbol and a fixed symbol such that the fixed symbol is inserted at a predetermined position in the block signal to generate a block symbol; an interpolation unit that performs interpolation processing on the block symbol; and a CP insertion unit that inserts a Cyclic Prefix into a signal on which the interpolation processing has been performed to generate the block signal. |
| US09866416B2 |
System and method for simultaneous communication with multiple wireless communication devices
Embodiments of the present invention relate to methods and systems for simultaneous communication with multiple wireless communication devices. In some embodiments, a method for simultaneous communication with multiple wireless communication devices includes receiving, using a plurality of antennas at a first wireless station, a plurality of packets, comprised of orthogonal frequency division multiplexing (OFDM) wireless signals, transmitted simultaneously from a plurality of other wireless stations wherein each of the simultaneously transmitted packets includes a plurality of frequency tones, frequency domain transform the received packets, grouping frequency domain transform outputs for each subcarrier, determining a difference between subcarrier groups formed over different sample sets, and determining a set of weights for each subcarrier, wherein the weights are selected such that the first wireless station can at least one of detect or demodulate the received plurality of packets. |
| US09866409B2 |
Method and system for VXLAN encapsulation offload
A method for virtual extensible local area network (VXLAN) encapsulation. The method includes receiving a first augmented MAC frame on a first ingress port of a first network device, where the first augmented MAC frame includes a first egress port ID (EPID), a first ingress port ID (IPID), and a first MAC frame. The method further includes identifying a first destination VXLAN tunnel endpoint (VTEP) internet protocol (IP) address based on the first EPID, where the first destination VTEP IP address is associated with a first destination VTEP. The method further includes identifying a source VTEP IP address based on the first IPID, performing VXLAN encapsulation of the first MAC frame to obtain a VXLAN frame, and sending the VXLAN frame to the first destination VTEP via a first egress port of the first network device. |
| US09866404B2 |
Router and method for establishing a network connection using the router
A method for establishing a new network connection using a router includes receiving notification of switching network modes of the router, and detecting whether a new network connection is established by the router. When the new network connection is disabled, the clients are disconnect from a LAN port of the router, a recertification request from the clients is refused, and the recertification request after a first predetermined time duration is received. Thus, a network connection is established. |
| US09866402B2 |
Remote care system for apartment building and remote monitoring apparatus used therein
A remote care system for an apartment building includes: a home electric appliance installed in a housing unit structuring an apartment building; a sensor that is provided in the home electric appliance and senses the behavior of a resident in the housing unit; and a remote monitoring apparatus that remotely controls the home electric appliance installed in each of a plurality of housing units based on sensing information transmitted from the sensor. This realizes implementation and operation of a remote care system for an apartment building using a major appliance used in ordinary households. |
| US09866401B2 |
Dynamic protection of shared memory and packet descriptors used by output queues in a network device
A network switch includes a buffer to store network packets and packet descriptors (PDs) used to link the packets into queues for output ports. The buffer and PDs are shared among the multiple traffic pools. The switch receives a multicast packet for queues in a given pool. The switch determines if there is unused buffer space available for packets in the given pool based on a pool dynamic threshold, if there is unused buffer space available for packets in each queue based on a queue dynamic threshold for the queue, if there are unused PDs available to the given pool based on a pool dynamic threshold for PDs, and if there are unused PDs available for each queue based on a queue dynamic threshold for PDs for the queue. The network switch admits the packet only into the queues for which all of the determining operations pass. |
| US09866396B2 |
Method for validating messages
There is provided a method for secure communications. The method includes a computing device receiving a notification comprising a message, a counter value, a signature signed by a signer and based on the message and the counter value, and an indication of the signer. The device obtains a current counter value based on an identity of the signer, checks the signature and compares the counter value with the current counter value; and, if the counter comparison and the signature checking is successful, accepting the message. |
| US09866392B1 |
Distributed system web of trust provisioning
A web of trust in a distributed system is established. A root of trust for at least two components in the distributed system validates information for the distributed system. The validated information is then used to create additional information for the distributed system. Versions of the information are usable to validate subsequent versions of the information such that validation of a version of the information can be performed by using one or more previous versions to verify that the version is a valid successor of a previously validated previous version. |
| US09866389B2 |
Multi-broadcast beacon signals
Disclosed herein are techniques and systems for transmitting a multi-broadcast signal from a wireless broadcasting device (or beacon) as part of a beacon recognition process. Specifically, the multi-broadcast signal may be in the form of multiple packets that are broadcast from the beacon within a recognition time period. A process may include creating a first packet having a first identifier (ID) and a randomly generated value, broadcasting the first packet from the beacon, generating a second ID based at least in part on the randomly generated value included in the first packet, and broadcasting, within a period of time from the broadcast of the first packet, a second packet having the second ID and a device ID that uniquely identifies the beacon. A mobile device in proximity to the beacon may include logic to detect and interpret a multi-broadcast signal from the beacon. |
| US09866375B2 |
Multi-level key management
A key manager provides a way to separate out the management of encryption keys and policies from application domains. The key manager may create cipher objects that may be used by the domains to perform encryption or decryption, without exposing the keys or encryption/decryption algorithms to the domains. A master key managed by the key manager may be used to encrypt and decrypt the domain keys that are stored under the control of the key manager. The key manager supports the rekeying of both the master key and the domain keys based on policy. Multiple versions of domain keys may be supported, allowing domains to access data encrypted with a previous version of a domain key after a rekeying. |
| US09866371B2 |
Cryptography on a simplified elliptical curve
A cryptographic calculation includes obtaining a point P(X,Y) from a parameter t on an elliptical curve Y2=f(X) and from polynomials satisfying: −f(X1(t))·f(X2(t))=U(t)2 in the finite body Fq, irrespective of the parameter t, q=3 mod 4. A value of the parameter t is obtained and the point P is determined by: (i) calculating X1=X1 (t), X2=X2(t) and U=U(t); (ii) testing whether the term f(X−1) is a squared term in the finite body Fq and, if so, calculating the square root of the term f(X1), the point P having X1 as abscissa and Y1, the square root of the term f(X1), as ordinate; (iii) otherwise, calculating the square root of the term f(X2), the point P having X2, as abscissa and Y2, the square root of the term f(X2), as ordinate. The point P is useful in encryption, scrambling, signature, authentication or identification cryptographic applications. |
| US09866370B2 |
Configurable ASIC-embedded cryptographic processing engine
Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic. |
| US09866365B2 |
RF structure of user terminal for supporting multi-carrier aggregation and various communication radio access technologies
According to one embodiment of the present specification, a user terminal is provided. The user terminal can comprise: a tunable antenna capable of adjusting a band; a diplexer connected to the tunable antenna to synthesize and separate sub-carriers; one or more antenna switches connected to the diplexer to synthesize and separate low-band sub-carriers and middle-band and high-band sub-carriers; and a sub-carrier processing unit connected to the one or more antenna switches to synthesize and separate a plurality of low-band sub-carriers, a plurality of middle-band sub-carriers and a plurality of high-band sub-carriers. A low-noise amplifier can be connected to the sub-carrier processing unit in order to prevent an increase in a reception sensitivity loss and a noise index occurring on a reception path of the diplexer, the one or more antenna switches and the sub-carrier processing unit. |
| US09866363B2 |
System and method for coordinated management of network access points
A method for coordinated wireless network management applicable to overlay network access points. The method includes sending, from an overlay access point of a plurality of overlay access points to a coordinator device, wireless operational parameters characterizing operation of the one of the plurality of overlay access points. The overlay access point receives suggested operational information provided by the coordinator device. The suggested operational information causes modification of a perceived value of at least one operational parameter of the one of the plurality of overlay access points wherein the perceived value is different from an actual value of the operational parameter. The method further includes adjusting an operational mode of the overlay access point based upon the perceived value. The adjusting may be further based at least in part upon a negotiation of wireless access parameters between the overlay access point and one or more local wireless devices. |
| US09866362B2 |
Method and system for searching network in long term evolution slave mode
Method and system for searching network in a Long Term Evolution (LTE) slave mode are provided. The method includes: determining whether the number of frequency points to be measured is greater than N, wherein N is a positive integer; if the number is greater than N, ordering the frequency points to be measured according to their signal strength; selecting, from the ordered frequency points to be measured, N frequency points whose signal strength is greater than other ordered frequency points as optimally selected frequency points; and performing cell search based on the optimally selected frequency points. Based on the above method, the cell search is performed by measuring the N optimally selected frequency points. In this way, the number of measured frequency points is reduced, and a time period for measuring each optimally selected frequency point is prolonged. Therefore, the possibility of finding a cell may be increased. |
| US09866359B2 |
Downlink acknowledgment in response to uplink multiple user transmission
The present invention provides a method and apparatus for transmitting a downlink ACK in response to an uplink multi-user transmission in a HE WLAN. In an aspect of the present invention, a method for transmitting an ACK in response to uplink data received from a plurality of STAs by an AP in a WLAN may be provided. The method may include transmitting a frame triggering transmission of a plurality of uplink data units from the plurality of STAs to the plurality of STAs, receiving a PPDU frame including a plurality of uplink data units from the plurality of STAs a predetermined IFS after transmitting the trigger frame, and transmitting an ACK frame including ACKs for the plurality of data units from the plurality of STAs. |
| US09866355B2 |
Service aware interference management
Methods, arrangement and network nodes for supporting inter-cell coordination of scheduling of radio resources subjected to inter cell interference. The methods involve identifying one or more radio resources which are subjected to inter-cell interference between a first cell and a second cell. The methods further involve deriving a respective service value related to service that could be provided in the respective first and second cell by use of the one or more radio resources. Further, transmissions in the one or more radio resources are controlled based on comparison of the service values, thus enabling inter-cell service value-based scheduling of the one or more radio resources, prioritizing services having the highest value per radio resource. |
| US09866354B2 |
Fragmentation of service data units in a high-efficiency wireless local-area network
Apparatuses, methods, and computer readable media are disclosed for fragmentation of media access control service data units (MSDU) in a high-efficiency wireless local-area network. An apparatus of a access point or station comprising memory and processing circuitry coupled to the memory is disclosed. The processing circuitry is configured to fragment a media access control (MAC) service data unit (MSDU) into two or more MSDU fragments, and encapsulate the two or more MSDU fragments into two or more aggregated MSDUs (A-MSDUs); one or more A-MSDUs and one or more MAC protocol data units (MPDUs); or, two or more MPDUs. The processing circuitry may be further configured to encode a delimiter in front of a first fragment of the two or more MSDU fragments, where the delimiter indicates a length of the two or more MSDU fragments, and to encode each MPDU to comprise a sequence number. |
| US09866352B2 |
Method, device and storage medium for improving distance measure equipment interference resisting capability of LTE system
A method for improving a Distance Measure Equipment (DME) interference resisting capability of a Long Term Evolution (LTE) system are described in the present disclosure; at an LTE User Equipment (UE) side, the method includes that: a symbol level DME interference result is obtained, and a scheduling message is sent according to the obtained symbol level DME interference result or according to the obtained symbol level DME interference result and a Physical Downlink Shared Channel (PDSCH) scheduling situation of a current subframe; at an LTE evolved Node B (eNB) side, the method includes that: the received scheduling message is detected, and a subframe is scheduled according to the received scheduling message. The present disclosure also discloses a UE, an eNB and two computer storage media for improving the DME interference resisting capability of the LTE system. |
| US09866350B2 |
Streaming media packet processing method, WiFi chip, and mobile terminal
A streaming media packet processing method and a mobile terminal are provided. The method includes receiving a streaming media packet and determining whether the streaming media packet is an error streaming media packet according to a first cyclic redundancy check (CRC) code of the streaming media packet. If the streaming media packet is an error streaming media packet, the method includes determining whether a transmission control protocol (TCP)/internet protocol (IP) header of the streaming media packet is correct. If the TCP/IP header of the streaming media packet is correct, the method further includes determining whether the streaming media packet is preset streaming media. If the streaming media packet is preset streaming media, the method further includes calculating a second CRC of the streaming media packet, combining the second CRC with the streaming media packet, and transmitting the streaming media packet combined with the second CRC to a processor such that the processor processes the streaming media packet according to the second CRC. Hence, an anti-interference capability of the WiFi chip during streaming media transmission and a transmission stability of a multimedia service packet are improved. |
| US09866346B2 |
Redundancy protection for reconfigurable optical add/drop multiplexing (ROADM) branching unit
Aspects of the present disclosure describe systems, structures and methods providing fully reconfigurable optical add-drop multiplexing (ROADM) that provide redundancy protection against any two (2) simultaneous wavelength selective switch (WSS) failures with only four 2×1 WSS structures for both Eastbound and Westbound traffic, while not requiring bidirectional operation of the WSS structures. |
| US09866345B2 |
Device, system and method for transmitting wavelength division multiplexed optical signal
A transmission device for which a work path is established in a first degree and a protection path is established in a second degree includes: a switch equipped with a plurality of optical ports; an optical signal generator, optically connected to a first optical port, and configured to generate an optical signal that is transmitted through the work path; and a monitor light generator, optically connected to a second optical port, and configured to generate monitor light by using a wavelength tunable light source. The monitor light generator controls a wavelength of the monitor light to be substantially the same as a wavelength of the optical signal. The switch guides the optical signal that arrives at the first optical port toward the first degree and guides the monitor light that arrives at the second optical port toward the second degree. |
| US09866344B2 |
Frequency conversion device, wavelength multiplex device and frequency conversion method
A frequency conversion device includes: an optical convertor configured to convert a source modulated light into an unmodulated light; and a frequency convertor configured to use the unmodulated light converted by the optical convertor as a reference light and convert the source modulated light into a modulated light that has a desirable frequency. |
| US09866343B1 |
Orthogonal frequency division multiplex (OFDM) sub-band allocation to enhance wireless data communications
An Orthogonal Frequency Division Multiplex (OFDM) base station transfers a wideband measurement request for a wideband OFDM spectrum to User Equipment (UE). The base station receives a wideband signal metric from the UE, and if the wideband signal metric is below a threshold, the base station transfers a sub-band null request to shield a sub-band of the wideband spectrum to an adjacent base station. The base station also transfers a sub-band measurement request to the UE. The base station receives a sub-band signal metric for the shielded sub-band from the UE, and if the sub-band signal metric is above a threshold, then the base station authorizes use of the shielded sub-band for the UE. The base station receives a communication request for the UE, and in response, transfers another sub-band null request to the adjacent base station and exchanges wireless data over the shielded sub-band with the UE. |
| US09866339B1 |
Method and apparatus for securing clock synchronization in a network
Aspects of the disclosure provide a method. The method includes generating a first message having a plurality of fields according to a precision time protocol, encapsulating one or more fields of the first message into a first encapsulation, preparing a first packet that includes the first message and the first encapsulation, and transmitting the first packet through a network. |
| US09866326B1 |
Method for self-calibration of an electrical and/or optical channel
An auto-equalization network device for optical transmitting and receiving is provided. The device includes a network device having an optical transmitter and an optical receiver. The network device is configured to determine a frequency domain forward transmission loss characterization for a signal transmitted by the optical transmitter, looped back and received by the optical receiver. The device is configured to generate a model in the frequency domain having control points based on the characterization, generate and load finite impulse response (FIR) filter taps into a finite impulse response filter based on the model in the frequency domain. The device is configured to iterate transmission of a signal with frequency-dependent preemphasis by the finite impulse response filter, characterization for the frequency-dependent preemphasized signal as looped back and received by the optical receiver, comparison to previous characterization, adjustment of the control points, and reloading the finite impulse response filter taps, until the comparison meets an optimum, so that the network device is auto-equalized for optical transmitting. |
| US09866318B2 |
Method, apparatus, and system for adjusting emission parameter of laser in WDM-PON
A method includes monitoring a power value of output light of the laser and a power value of reflected light, obtaining an insertion loss value according to the power value of the output light, the power value of the reflected light, and a parameter of a Faraday rotation reflector, obtaining a bias current value according to the insertion loss value, and adjusting the power value of the output light of the laser using the bias current value. The insertion loss value is obtained by detecting the power value of the reflected light obtained after the output light of the laser is reflected. Because the insertion loss value is a power loss value, of the output light of the laser, on a one-way link between the laser and the Faraday rotation mirror. |
| US09866315B2 |
Super-channel multiplexing and de-multiplexing using a phased array switching engine
A method may include receiving, by a switching engine, an optical signal. The optical signal may carry a super-channel that includes a plurality of sub-carriers to be directed toward respective output ports. The switching engine may have a plurality of regions of pixels on which respective sub-carriers, of the plurality of sub-carriers, are incident. The method may include applying, by the switching engine, respective single beam steering gratings to first, overlapping, areas of the plurality of regions of pixels. The method may include applying, by the switching engine, one or more respective pluralities of beam steering gratings to second, overlapping areas of the plurality of regions of pixels. The method may include directing, based on the single beam steering gratings and the one or more pluralities of beam steering gratings, parts of the optical signal toward the respective output ports. |
| US09866311B2 |
System comprised of an electrical kitchen appliance and an add-on module
A system comprising an electric kitchen appliance and an additional module that can be connected to the electric kitchen appliance for the exchange of data, wherein the additional module has a kitchen appliance interface, via which the data can be transmitted from the additional module to the electric kitchen appliance. The additional module has a radio interface and a repeater, wherein a data connection to a radio network can be established by way of the radio interface such that via the radio network, data signals can be transmitted to the additional module. By way of the repeater, the intensity of received data signals from the radio network can be amplified, and the amplified data signals can be re-transmitted. In this way, an additional benefit is made available to the user of the system. |
| US09866309B2 |
Host node device and methods for use therewith
Aspects of the subject disclosure may include, for example, a host node device having a terminal interface that receives downstream channel signals from a communication network and send upstream channel signals to the communication network. An access point repeater launches the downstream channel signals as guided electromagnetic waves on a guided wave communication system and to extract a first subset of the upstream channel signals from the guided wave communication system. A radio wirelessly transmits the downstream channel signals to at least one client node device and to wirelessly receive a second subset of the upstream channel signals from the at least one client node device. Other embodiments are disclosed. |
| US09866307B2 |
Method for transceiving data symbol using antenna correlation in wireless access system which supports massive antenna
A method and device for transmitting data symbols using an antenna correlation in a wireless access system supporting multiple input/multiple output (MIMO) operations. The method includes: receiving, from a receiving end, grouping information of a plurality of antennas for supporting the MIMO operations, where the grouping information includes information on the two selected antenna subgroups; selecting two antennas of which a correlation is highest from the two selected antenna subgroups respectively for transmitting the data symbols; and transmitting different data symbols through each of the two selected antennas of the two selected antenna subgroups on an identical time frequency resource. Here, antennas with a highest correlation are grouped into two or more antenna subgroups. Also, two antenna subgroups, of which a correlation is lowest from the two or more antenna subgroups, are selected among the two or more antenna subgroups by the receiving end. |
| US09866301B2 |
Channel estimation techniques for LSAS backhaul and the like
In certain embodiments, a macrocell base station (BS), such as an LSAS BS, estimates its backhaul channels with a small-cell BS (e.g., a relay or repeater) by averaging multiple instances of a received pilot signal repeatedly transmitted by the small-cell BS. Since the macrocell and small-cell BSs are stationary, averaging the received pilot signal transmissions over time results in the zero-temporal-mean time-dependent component of each backhaul channel as well as zero-temporal-mean noise and interference signals from other wireless nodes to substantially cancel out, enabling the macrocell BS to relatively infrequently estimate a relatively time-invariant, dominant component for each backhaul channel. The macrocell BS uses the estimated dominant components to generate user-data-based downlink transmissions to the small-cell BS. In this way, the processing to estimate channel state information (CSI) data for the backhaul channels is greatly reduced compared to conventional techniques. |
| US09866297B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
The present invention provides a method of transmitting broadcast signals. The method includes, encoding Data Pipe, DP, data according to a code rate, wherein the encoding further includes Low-Density Parity-Check, LDPC, encoding the DP data, Bit interleaving the LDPC encoded DP data, and mapping the bit interleaved DP data onto constellations; building at least one signal frame by mapping the encoded DP data; and modulating data in the built signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, method and transmitting the broadcast signals having the modulated data. |
| US09866290B2 |
Apparatus and methods for multi-user simultaneous transmission
The embodiments provide a method implemented by a first station (STA) for transmitting a frame to an Access Point (AP) as part of an uplink multi-user simultaneous transmission. The method avoids unintentional beamforming at the AP. The method includes receiving a first frame from the AP, where the first frame includes scheduling information for scheduling a simultaneous uplink transmission for the first STA and one or more other STAs, generating a second frame having a common part and a user-specific part, where the second frame is to be transmitted simultaneously with other frames according to the scheduling information, determining a cyclic shift value to be applied to the common part, where the cyclic shift value is determined to be different from one or more cyclic shift values to be applied by each of the other STAs, applying the cyclic shift value to the common part and transmitting the second frame to the AP. |
| US09866288B2 |
Method for operating a base station comprising a plurality of antennas in a wireless radio network
The present invention relates to a method for operating a base station (11) in a wireless radio network (10). The base station (11) comprises a plurality of antennas for transmitting radio frequency signals between the base station (11) and a user equipment (UE1, UE2). According to the method, at each antenna (12) a training signal sent from the user equipment (UE1, UE2) is received and for each antenna (12) a corresponding configuration parameter is determined based on the training signal. A plurality of payload information blocks (33) is transmitted between the base station (11) and the user equipment (UE1, UE2) using the determined configuration parameters and a predetermined transmission scheme. For at least one payload information block (33) a transmission quality parameter is determined and an adapted transmission scheme is determined based on the determined quality parameter. |
| US09866279B2 |
Systems and methods for selecting which power transmitter should deliver wireless power to a receiving device in a wireless power delivery network
The embodiments described herein include a transmitter that transmits a power transmission signal (e.g., radio frequency (RF) signal waves) to create a three-dimensional pocket of energy. At least one receiver can be connected to or integrated into electronic devices and receive power from the pocket of energy. A wireless power network may include a plurality of wireless power transmitters each with an embedded wireless power transmitter manager, including a wireless power manager application. The wireless power network may include a plurality of client devices with wireless power receivers. Wireless power receivers may include a power receiver application configured to communicate with the wireless power manager application. The wireless power manager application may include a device database where information about the wireless power network may be stored. |
| US09866272B2 |
Communication system comprising a connector having first and second waveguides disposed in proximity to each other for coupling millimeter-wave data signals
Provided is a connector system including a first waveguide having a first opening terminal and a second waveguide having a second opening terminal. The first and second waveguides transmit a high-frequency signal when the first opening terminal is in contact with or in the vicinity of the second opening terminal. A dielectric plate is provided on an opening terminal surface of at least one of the first and second opening terminals. |
| US09866262B2 |
Wireless transceiving device
A wireless transceiving device is proposed. The wireless transceiving device includes a transmitting circuit, a receiving circuit and an auxiliary receiving circuit. The transmitting circuit includes a signal transceiving circuit. The receiving circuit includes the signal transceiving circuit. The auxiliary receiving circuit is coupled to the receiving circuit and includes an auxiliary antenna. When the receiving circuit receives a signal via the signal transceiving circuit, the auxiliary receiving circuit assists the receiving circuit to receive the signal via the auxiliary antenna. |
| US09866256B2 |
Electronic apparatus
Electronic apparatus is provided with main body, and inner battery cover and additional module which are attachable and detachable in relation to main body. Battery is stored in opening portion of housing, recessed portion is formed in vertical surface which stands substantially vertically from main surface, and first terminal is formed on inner portion of recessed portion. Connecting surface which comes into contact with vertical surface is formed on additional module, and second terminal which is electrically connected to first terminal is formed on connecting surface. In a state in which additional module is attached to main body, second terminal is positioned on an inner portion of recessed portion and is connected to first terminal, and thus, reliable and firm attachment is performed. |
| US09866254B2 |
Mobile device protection jacket
A mobile device protection jacket includes a covering jacket body and a back cover, wherein a front piece is provided on the covering jacket body and a side protection piece is formed on a periphery of the front protection piece in an extending and penetrating manner, so a holding space for holding a mobile device is formed between the front protection piece and side protection piece and embedment catching portions are formed on an outer edge of the side protection piece; and wherein embedment fixing portions are formed on an outer edge of the back cover at positions corresponding to the embedment catching portions on the outer edge of the side protection piece of the covering jacket body, such that the back cover can be jointed and fixed through mutual embedment and catching of the embedment fixing portions and the embedment catching portions of the side protection piece. |
| US09866253B2 |
Bendable device having rigid receiving space and electronic apparatus
Embodiments of the present disclosure provide a bendable device having rigid receiving space that include a bendable housing having a receiving space therein, and in the process of the bendable housing being bent, at least a part of the volume of the receiving space is free from bending influence, thus the at least partial volume of the receiving space free from the bending influence constitutes a rigid receiving space. |
| US09866248B2 |
Method for verifying location information of a terminal connected to a cellular telecommunications network
A method for verifying location information of a terminal equipped with a UICC card, connected to a cellular telecommunications network and located in a current cell, said terminal storing in the UICC card an identifier of the current cell and at least one identifier of a previous cell in which the terminal was previously located. This method comprises the following steps, implemented by a processing server connected to the network: receiving said identifiers coming from the terminal via the communication network; determining first location information using the identifier of the current cell; estimating second location information using the identifier of at least one previous cell; detecting a location error if the two items of location information correspond to different geographical positions according to a defined criterion. |
| US09866246B1 |
Digital Transmitter channel optimization device
A digital transmitter channel optimization device can be employed within or in conjunction with a transmitter to perform a number of techniques in the digital domain to account for distortion introduced in the transmitter. The optimization device can be configured to perform such techniques on an arbitrary signal to thereby allow the optimization device to be used with virtually any transmitter. The optimization device may be particularly beneficial in wideband systems where accounting for distortion can be difficult to accomplish using existing techniques. |
| US09866241B2 |
Techniques for adaptive LDPC decoding
Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits. |
| US09866237B1 |
Low power switched capacitor integrator, analog-to-digital converter and switched capacitor amplifier
Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit. |
| US09866235B2 |
Digital to analog converter
Digital to analog converters have first and second to analog arrays. The first digital to analog array has a reference input, a reference output, a first digital input that is connectable to a digital signal, and an analog output. The second digital to analog array includes a reference input, a reference output that is coupled to the reference input of the first digital to analog array, a plurality of switches coupled to the reference input, and a plurality of resistors coupled between the switches and the reference output. |
| US09866234B1 |
Digital-to-analog converter
Certain aspects of the present disclosure provide digital-to-analog converters (DACs). One example DAC generally includes a first transistor configured to selectively couple a power source to a load. In a first mode of operation of the DAC, the first transistor is closed and couples the load to the power source. In a second mode of operation of the DAC, the first transistor is open and decouples the load from the power source. The DAC further includes a current limiting circuit selectively coupled between the first transistor and a reference voltage. In the first mode, the current limiting circuit is decoupled from the reference voltage. In the second mode, the current limiting circuit is coupled to the reference voltage. |
| US09866232B2 |
Analog-to-digital converter, radiation detector and wireless receiver
According to an embodiment, an analog-to-digital converter includes a detection circuit, a first conversion circuit, a second comparator, a delay control circuit, a control circuit. A detection circuit detects a differential time signal corresponding to a delay time by using a comparison signal and a delay comparison signal. A first conversion circuit generates a differential voltage by performing time-to-voltage conversion on the differential time signal. A second comparator generates a digital delay determination signal by comparing the differential voltage and an adjustment target voltage. A delay control circuit generates a delay control signal controlling the delay time in accordance with a delay determination signal. A control circuit generates a control signal by using the delay comparison signal in an analog-to-digital conversion period. |
| US09866230B2 |
Method and apparatus for calibration of a time interleaved ADC
Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module. |
| US09866229B2 |
Power adapter and control method thereof
A power adapter includes a power converting circuit, a connecting terminal and a controller. The power converting circuit is used to convert an input voltage to an output voltage according to a control signal. The connecting terminal is connected to an electronic device to allow the output voltage outputted by the power converting circuit to charge the electronic device. The controller receives an identifying command from the electronic device when the electronic device is connected to the connecting terminal, and outputs the control signal according to the identifying command. |
| US09866227B1 |
Sigma-delta analog-to-digital converter including loop filter having components for feedback digital-to-analog converter correction
Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC. |
| US09866224B2 |
Oscillator, radio communication device, and radio communication method
An oscillator has an oscillator which comprises a first variable capacitor to adjust capacitance based on a first signal and a second variable capacitor to adjust capacitance, generates an oscillation signal having a frequency in accordance with the capacitance of the first variable capacitor and the second variable capacitor, an integer phase detector to detect an integer phase of the oscillation signal, a fractional phase detector to detect a fractional phase of the oscillation signal, a phase error generator to generate a fourth signal indicating a phase error of the oscillation signal, a first filter to extract the first signal in a predetermined frequency band, included in the fourth signal, and to output the first signal, and a second filter to extract the second signal in a predetermined frequency band, included in the fourth signal, and to output the second signal. |
| US09866219B2 |
Device for logic operation
An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale. |
| US09866216B1 |
Biasing circuit for level shifter with isolation
A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter. |
| US09866214B2 |
Composite device and switching power supply
This invention provides a composite device and a switching power supply. The composite device integrates therein a first enhancement-mode MOS device and a depletion-mode MOS device, and comprises: an epitaxial region of a first doping type; a first well region and a second well region formed in parallel on the front side of the epitaxial region; a first doped region of the first doping type formed within the first well region; a gate of the first enhancement-mode MOS device; a second doped region of the first doping type formed within the second well region; a channel region of the first doping type, wherein the channel region extends from a boundary of the second well region to a boundary of the second doped region; and a gate of the depletion-mode MOS device. The switching power supply includes the composite device above. This invention can decrease the process complexity, reduce the chip area and cost, and may be applicable to high power scenarios. |
| US09866211B2 |
Protection device for a semiconductor switch, and method for operating a protection device for a semiconductor switch
The invention relates to a surge protection device for a semiconductor switch with an improved response behavior. The protection device comprises a dynamic component together with a static component and a capability to analyze switch operations on the semiconductor switch. The dynamic component of the surge protection device activates in the event of a low surge, but is time-limited, however, with respect to the response behavior. Furthermore, the response of the dynamic component of the surge protection device can also be limited such that a response occurs only after switch operations on the semiconductor switch. |
| US09866208B2 |
Precision measurements and calibrations for timing generators
Described herein are methods and subsystems for use with a timing generator having an output driver at which a timing signal having timing pulses is output. A method includes controlling the timing generator to cause the output driver to output a timing signal having an expected duty cycle, and filtering the timing signal to produce a DC voltage having a magnitude indicative of an actual duty cycle of the timing signal. The method also includes converting the DC voltage to a digital value indicative of the actual duty cycle of the timing signal. The method can also include comparing the digital value to an expected value corresponding to the expected duty cycle, and using results of the comparing to determine an error associated with the timing generator and/or produce a calibration table that can be used to calibrate the timing generator and/or calibrate a measurement made using the timing generator. |
| US09866207B2 |
Semiconductor device, power control device and electronic system
A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor. |
| US09866206B2 |
Driver circuit for memory devices
There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit. |
| US09866203B1 |
High reliability power tuners
High reliability impedance tuners used in high power measurements suffer fast heating and consequently thermal expansion of the central conductor, which has a very small mass and is thermally isolated from the tuner housing. This leads to false measurements or catastrophic tuner failure (short) of either the DUT or the tuner. A method is introduced for allowing the center conductor to expand linearly without deforming and risking loss of accuracy first and catastrophic failure later. Practical tests have shown significant thermal behavior improvement. |
| US09866200B2 |
Multiple coil spring MEMS resonator
A multiple coil spring MEMS resonator includes a center anchor and a resonator body including two or more coil springs extending in a spiral pattern from the center anchor to an outer closed ring. Each pair of coil springs originates from opposing points on the center anchor and extends in the spiral pattern to opposing points on the outer ring. The number of coil springs, the length and the width of the coil springs and the weight of the outer ring are selected to realize a desired resonant frequency. |
| US09866199B2 |
Vibrating device
A vibrating device having tuning fork arms extending in a first direction that are joined to a base portion and are arranged side by side in an second direction. Each of the tuning fork arms has a structure that a silicon oxide layer is laminated on a Si layer made of a degenerate semiconductor, and that an excitation portion is provided on the silicon oxide layer. When a total thickness of the Si layer is denoted by T1, a total thickness of the silicon oxide layer is denoted by T2, and the temperature coefficient of resonant frequency (TCF) when the silicon oxide layer is not provided on the Si layer is denoted by x, a thickness ratio T2/(T1+T2) is within a range of (−0.0002x2−0.0136x+0.0014)±0.05. |
| US09866198B2 |
Resonator element, resonator, electronic device, electronic apparatus, and moving object
A resonator element includes a substrate that vibrates in a thickness shear vibration, a first excitation electrode that is provided on one main surface of the substrate and has a shape in which at least three corners of a virtual quadrangle are cut out, and a second excitation electrode that is provided on the other main surface of the substrate, and a ratio (S2/S1) of an area S1 of the virtual quadrangle and an area S2 of the first excitation electrode satisfies a relationship of 69.2%≦(S2/S1)≦80.1%. |
| US09866197B2 |
Tunable RF filter based RF communications system
RF communications circuitry, which includes a first RF filter structure, is disclosed. The first RF filter structure includes a first tunable RF filter path and a second tunable RF filter path. The first tunable RF filter path includes a pair of weakly coupled resonators. Additionally, a first filter parameter of the first tunable RF filter path is tuned based on a first filter control signal. A first filter parameter of the second tunable RF filter path is tuned based on a second filter control signal. |
| US09866193B2 |
Parallel RC circuit equalizers
Disclosed are apparatus and methodology for increasing the resonance frequency and useful frequency range of surface mount RC equalizer devices. The presently disclosed subject matter provides improved operational characteristics of generally known such RC equalizer devices by implementing a reverse geometry that relocates the internal termination points, as well as external termination points for such devices, along lateral portions of the assembled device. Such reverse geometry achieves improvements by providing a reduction of the equivalent series inductance (ESL) to provide the increased resonance frequency and useful frequency range. |
| US09866192B2 |
Filter component with windingless magnetic toroidal core
Filter component having a windingless magnetic toroidal core with an opening, a toroidal core housing in which the toroidal core is fastened using a snap-on mechanism, wherein the filter component is designed such that a conductor can be run windinglessly through the opening of the toroidal core fastened in the toroidal core housing. |
| US09866189B2 |
Analog amplifier for recovering abnormal operation of common mode feedback
An analog amplifier for recovering an abnormal operation of a common-mode feedback is provided. An analog variable amplifier includes a first input transistor and a second input transistor, a first output transistor and a second output transistor, a third transistor and a fourth transistor, a first current source, a fifth transistor and a sixth transistor, and a second current source. The first input transistor and the second input transistor amplify a bias current depending on a magnitude of a first input voltage and a second input voltage. The first output transistor and the second output transistor output the amplified bias current. The third transistor and the fourth transistor receive an output voltage of the first output transistor as an input and amplifying the received output voltage. The first current source provides a predetermined current between the first output transistor and the third transistor. |
| US09866183B2 |
Devices and methods for adaptive crest factor reduction in dynamic predistortion
A non-linear pre-distortion engine maintaining constant peak power at its output is disclosed. The engine includes a compression estimator, a crest factor reduction processor, a digital pre-distorter and a power amplifier. The compression estimator is configured to generate a compression estimate based on an input signal and a feedback signal. The feedback signal is based on an RF output signal. The crest factor reduction processor is configured to reduce a crest factor of the input signal to generate a crest factor reduced signal based on the compression estimate. The digital pre-distorter is configured to apply a pre-distortion to the crest factor reduced signal after an initial phase and generate a pre-distorted signal based on pre-distortion parameters. The power amplifier is configured to amplify the pre-distorted signal to generate the RF output signal. The operation of the chain consisting of pre-distorter and power amplifier is substantially linear and the pre-distorter maintains constant peak power at its output, which eliminates unwanted avalanche or pre-distorter blow-up issues. |
| US09866181B2 |
Power amplification circuit and transmitter
Embodiments for a power amplifier that can increase a low-frequency resonance frequency are provided. The power amplifier includes a power amplifying transistor die, a first metal oxide semiconductor capacitor, a direct current decoupling capacitor, and an output matching network, where: a drain of the power amplifying transistor die is connected to a first end of the first metal oxide semiconductor capacitor by using a bonding wire, and a second end of the first metal oxide semiconductor capacitor is grounded; the drain of the power amplifying transistor die is directly connected to the output matching network by using a bonding wire; a source of the power amplifying transistor die is grounded; the first end of the first metal oxide semiconductor capacitor is connected to one end of the direct current decoupling capacitor by using a bonding wire; and the other end of the direct current decoupling capacitor is grounded. |
| US09866179B1 |
Multipath linear low noise amplifier
The present disclosure relates to methods and systems for LNAs with high linearity and low noise for wideband receivers that receive high dynamic range signals. A multi-stage multipath LNA is disclosed in which outputs from various stages are amplified with variable gains and combined in parallel. A smart gain control unit evaluates the noise and non-linearity characteristics associated with each gain stage to configure the variable gains for the various stages to generate an overall LNA gain that minimizes the overall noise and/or non-linearity characteristics of the LNA while ensuring that the overall gain for the LNA satisfies the desired gain. The variable gains may be configured to change smoothly over the dynamic range of the input signal. Noise is minimized by reducing additional gain stages and by the smooth change in gain when switching between stages. High linearity performance is maintained by minimizing the number of gain stages combined. |
| US09866174B2 |
Resonant frequency divider design methodology for dynamic frequency scaling
A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio. |
| US09866171B2 |
Measuring device for property of photovoltaic device and measuring method using the same
A measuring device for the property of a photovoltaic device and a measuring method using the same are provided. The measuring device includes several light sources and a feedback control module. The light color of each light source is different and includes several light-emitting elements symmetrically configured. The feedback control module is used for controlling illuminations of the light-emitting elements for measuring the property of a photovoltaic device. |
| US09866168B2 |
Flexible photovoltaic modules having junction box supporting flaps
Provided are flexible photovoltaic modules having flaps for supporting junction boxes. Junction boxes are used for making electrical connections to photovoltaic cells sealed inside the modules. A flap may be formed by one or two flexible sealing sheets extending beyond the boundary of the photovoltaic cells. A junction box is attached to the front surface of the flap. In certain embodiments, a flap is formed by one sealing sheet, such as a back side sheet. Materials of the back side sheet may be different from materials of the front side sheet and be selected to ensure support to the junction box. Additional support to the junction box may be provided by extending one of its edges in between the two sealing sheets. This edge extension or other features may be used for mechanical protection of electrical leads extending between the junction box and photovoltaic cells. |
| US09866162B2 |
Excitation circuit of a motor vehicle alternator, voltage regulator, and alternator which incorporates it
The excitation circuit according to the invention controls an excitation current (lexc) in an excitation winding (2) of an alternator by means of an on-board network voltage control loop (Vbat+, 3) of the vehicle, and comprises a first MOS power transistor (9) which is connected between a first positive supply terminal Vbat+ (6), and a first excitation terminal (7), and is controlled by the control loop by means of a first control circuit (10), a second MOS power transistor (11), which is connected between the first excitation terminal and a second excitation terminal (8) which is connected to a ground terminal (5) and acts as a free wheel diode, whilst being controlled by means of a second control circuit (12). According to the invention, the circuit additionally comprises a control loop (15) of a drain-source voltage (Vds) of the second transistor. |
| US09866160B2 |
Power conversion system and controlling method thereof and wind turbine power generation system
A system includes a source side converter for being electrically coupled to a generator of a power source, a line side converter for being electrically coupled to a power network, a DC link coupled between the source side converter and the line side converter, and a controller for generating source side switching signals based on a current or torque of the generator and a virtual impedance signal for system damping or reactive power compensation when at least one detected signal of the system is not normal. A method for controlling the system is also included. |
| US09866159B1 |
Rotor control method and device
Electric motors may include one or more sensors usable to determine rotor alignment and/or speed. A method and apparatus for rotor alignment and/or speed error detection and/or correction are proposed, such as using signals from one or more sensors. A method and apparatus for controlling stator tooth activation based, at least in part, on corrections and offsets is also disclosed. |
| US09866149B2 |
Method and apparatus for enabling floating touch screen haptics assemblies
A system that includes an actuator amplification apparatus and a push pull actuator disposed on or within the actuator amplification apparatus. The actuator amplification apparatus is configured to receive a push pull actuator. The actuator amplification apparatus includes a body fixture configured to attach the actuator amplification apparatus to a fixed mass, an output interface to attach the actuator amplification apparatus to a moving mass, and an integral amplification mechanism. The integral amplification mechanism of the actuator amplification apparatus amplifies a force output by the push pull actuator to the moving mass. The integral amplification mechanism includes a plurality of linkages or an integral lever arm. The actuator amplification apparatus may include stabilizers configured to limit movement of the push pull actuator. In an embodiment, the fixed mass is a dashboard frame of an automobile and the moving mass is a floating haptic touch screen assembly. |
| US09866147B2 |
Power-converting device and power conditioner using the same
A first bidirectional switch is electrically connected between a first connection point which is a connection point of a first switching element and a second switching element and a second connection point which is a connection point of a seventh switching element and an eighth switching element. A second bidirectional switch is electrically connected between a third connection point which is a connection point of a third switching element and a fourth switching element and a fourth connection point which is a connection point of a fifth switching element and a sixth switching element. A power-converting device is configured to generate an output voltage between a first output point and a second output point. |
| US09866146B2 |
Enhanced flyback converter
A DC/DC flyback converter that exhibits reduced switch and transformer voltage stresses in comparison to known flyback converters. The flyback converter also employs soft switching. Embodiments of such flyback converters may be used, without limitation, in electric vehicles and hybrid electric vehicles. A front-stage of the flyback converter comprises a DC/AC step-down circuit that may be separately used for various purposes. |
| US09866139B2 |
Inductive power transfer converter
A bidirectional inductive power transfer (IPT) power converter comprising a cycloconverter, coupled to an AC port, and a resonant circuit, coupled to the cycloconverter, for storing energy and coupling energy to an IPT port. |
| US09866137B2 |
Deviation compensation method of potential transformer
A deviation compensation method of a potential transformer is provided. The deviation compensation method includes: providing first to Nth potential transformers to be installed at different locations in a high voltage direct current (HVDC) transmission system; supplying a first voltage to the first to Nth potential transformers provided; measuring voltage values output through the first to Nth transformers by the first voltage supplied; determining whether there is a deviation between the measured voltage values; and determining compensation values for correcting the measured voltage values to the same voltage value when there is the deviation. |
| US09866136B2 |
Isolated power supply with input voltage monitor
A power converter can include an electrical isolation circuit between input and output nodes. An input signal monitor node can be provided, such as on a converter output side of the isolation circuit. In an example, a peak detection circuit can be coupled to the input signal monitor node. The output node of the power converter can be configured to supply an output power signal that is a function of an input signal at the input node. The power converter can include multiple, independently-switchable switches at one or more of the input and output sides of the isolation circuit. In an example, the power converter with the input signal monitor node can be configured as a bias supply to provide power, at the output node, to a controller circuit for a main stage power converter circuit. |
| US09866132B2 |
DC-DC power conversion and balancing circuit
A system includes DC-DC power conversion circuitry having a first switch and a second switch on either side of a first transformer with a first pair of capacitors and a second pair of capacitors cross-connected across the transformer. Balancing circuitry includes a primary side of a second transformer connected between the first pair of capacitors and the second pair of capacitors of the DC-DC power conversion circuitry. Control circuitry is configured to determine a direction of power transfer through the DC-DC power conversion circuitry, align a primary side and a secondary side of the DC-DC power conversion circuitry based on the determined direction of power transfer, align the balancing circuitry to perform balanced or unbalanced operations, and control switching of the first switch and the second switch. |
| US09866126B2 |
Galvanic isolator and circuit using galvanic isolation
A method and apparatus for isolating voltages while transmitting data signals. In one embodiment of the method, a modulation circuit modulates a carrier signal using an input data signal. A demodulation circuit receives the modulated carrier signal via a first capacitor coupled in series between the modulation circuit and the demodulation circuit. The demodulation circuit also receives the carrier signal via a second capacitor coupled in series between the demodulation circuit and the circuit that generates the carrier signal. The demodulation circuit demodulates the modulated carrier signal using the carrier signal. |
| US09866125B2 |
Input voltage sensor responsive to load conditions
An ac-dc power converter controller includes a switch driver circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter. An input sense circuit is coupled to receive an input sense signal representative of the input of a power converter. A sense enable circuit is coupled to generate a sense enable signal in response to the drive signal. The sense enable signal is coupled to control the input sense circuit to sense the input sense signal for an extended duration of time after the power switch turns OFF. |
| US09866124B2 |
High power factor primary regulated offline LED driver
A fly-back type switched current regulator includes a primary transformer winding coupled to receive a rectified DC signal derived from an AC signal. The drain of a power transistor is coupled to the primary winding, with the source of the power transistor coupled to an input of a comparison circuit and a primary transformer winding sense resistor. A control terminal of the power transistor is coupled to an output of the comparison circuit. A capacitor stores a variable reference signal for application at a first capacitor terminal to another input of the differential circuit. The variable reference signal is compared to a winding current signal generated by the sense resistor by the comparison circuit. An injection circuit applies an AC signal derived from the rectified DC signal to a second terminal of the capacitor so as to modulate the stored variable reference signal. The regulator is coupled to drive LEDs. |
| US09866122B2 |
Hybrid boost-bypass function in two-stage converter
A boost-bypass converter includes a boost inductor coupled between an input and an output of the boost-bypass converter. A bypass diode is coupled between the input the output of the boost-bypass converter. A boost switching element is coupled to the boost inductor, and is coupled to be activated during a first interval in each line half cycle of an input voltage to boost an output voltage at the output of the boost-bypass converter. The boost switching element is coupled to be deactivated during a second interval in said each line half cycle such that the output voltage drops towards the input voltage. The output voltage is coupled to follow the input voltage during a third interval in said each line half cycle of the input voltage. Energy is transferred between the input and the output of the boost-bypass converter through the bypass diode during the third interval. |
| US09866119B2 |
DC-DC converter with pull-up and pull-down currents based on inductor current
A DC-DC converter includes an inductor, a switch module, a pull-up circuit and a pull-down circuit. The inductor has a first node and a second node, and the second node is coupled to an output node of the DC-DC converter. The switch module is arranged for selectively connecting an input voltage or a ground voltage to the first node of the inductor according to a driving signal. The pull-up circuit is arranged for selectively providing a first current to the output node of the DC-DC converter. The pull-down circuit is arranged for selectively sinking a second current from the output node of the DC-DC converter. In addition, at least one of the first current provided by the pull-up circuit and the second current sunk by the pull-down circuit is determined based on an inductor current flowing through the inductor. |
| US09866116B2 |
Digitally variable slope compensation circuit
A digitally compensated circuit for a power supply having a plurality of integrated circuits. The plurality of integrated circuits has a digitally variable slope controller to adjust charge time of an inductor and voltage distortion and an adjustable voltage generator, which generates a modified voltage set point. The digitally compensated circuit has a comparator, which compares the modified voltage set point to a first feedback and turns off a comparator output signal when first feedback approaches or exceeds the modified voltage set point. An adjustable pulse width modulator generator produces an output voltage. A current monitor receives output voltage and provides a second feedback, which is transferred to the plurality of integrated circuits. An inductor receives output voltage and generates variable output power for a load, utilizing the digitally variable slope controller to reduce oscillation, system disturbances, and subharmonic oscillations over a dynamic voltage input range. |
| US09866115B2 |
Reduction of frequency variation for ripple based, constant-on-time DC-DC converters
Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed. |
| US09866112B1 |
Ultra-low power bandgap reference using a clocked amplifier
Methods and apparatus providing an ultra-low power bandgap reference using a clocked amplifier are disclosed. An example apparatus includes a clocked comparator to compare a first voltage to a second voltage when a clock signal pulses and output a comparison signal based on the comparison, the comparison signal being (A) a first signal when the first voltage is higher than the second voltage and (B) a second signal when the first voltage is lower than the second voltage; a monoshot to when the comparison signal is a first signal, output a first pulse; and when the comparison signal is a second signal, output a second pulse; and a charge pump to increase an output voltage when the monoshot outputs the first pulse; decrease the output voltage when the monoshot outputs the second pulse; and hold the output voltage when the monoshot is not outputting a pulse. |
| US09866103B2 |
Magnetic capacitive current limit circuit for transformers
Circuit and apparatus for improving operating features characteristics of DC power supplies implementing three Phase transformer devices of the type such as 12-step and 24-step transformers. The circuit and apparatus reduces harmonic AC input current while providing almost unity power factor for DC power supply outputs intended for aircraft or marine applications where size and weight are concerns. The circuit includes a passive series connected nonlinear resonant LC circuit connected at each phase of the input to the three phase transformer With the three phase transformer having the added series nonlinear resonant LC circuit, the power supply is enhanced with current limiting for the entire transformer, rectifier and load, due to load shorting, input voltage transients, transformer winding short circuit or rectifier failure. Further, such apparatus provides limiting of power inrush currents during voltage application or turn on, while also providing EMI filtering. |
| US09866102B2 |
Power conversion device
A power conversion device is mounted with a control circuit, a plurality of drive circuits for driving switching elements in response to control signals from the control circuit, and a plurality of power supply circuits for supplying power to the drive circuits on a substrate. The power conversion device has a drive-circuit/power supply-circuit placement and wiring regions of a high current system in which the drive circuits and the power supply circuits are disposed on the substrate are provided for the respective switching elements with isolating regions interposed between the drive-circuit/power supply-circuit placement and wiring regions and the control circuit of a low current system. A gap is formed between the pairs of the drive-circuit/power supply-circuit regions. Power supply transformers are provided for transforming a voltage supplied from the control circuit for the respective power supply circuits in-between the isolating regions. |
| US09866099B1 |
Adaptive high-side gate drive for ringing mitigation in switching power converters
A power converter includes a high side device, a low side device connected to the high side device at a switch node, an inductor connected to the high side device and the low side device at the switch node, and a high side driver. The high side driver is configured to drive a gate of the high side device at a first current for a first period of time. In response to the first period of time ending, the high side driver is configured to step down the first current for a second period of time. In response to the second period of time ending, the high side driver is configured to drive the gate of the high side device at the first current. |
| US09866098B2 |
Serially connected inverters
A photovoltaic power generation system, having a photovoltaic panel, which has a direct current (DC) output and a micro-inverter with input terminals and output terminals. The input terminals are adapted for connection to the DC output. The micro-inverter is configured for converting an input DC power received at the input terminals to an output alternating current (AC) power at the output terminals. A bypass current path between the output terminals may be adapted for passing current produced externally to the micro-inverter. The micro-inverter is configured to output an alternating current voltage significantly less than a grid voltage. |
| US09866096B2 |
Linear drive
The present invention relates to a linear drive (1), comprising a running track (2), at least one movement unit (4) with at least one magnetic element (5), which is linearly movable on the running track (2), a plurality of electrical primary magnets (3) which are stationarily arranged on the running track (2) and act magnetically upon the at least one magnetic element (5), wherein the primary magnets (3) can be activated individually or in groups for driving the movement unit (4), a magnetically activatable element (7) on the movement unit (4), wherein the magnetically activatable element (7) can be activated by at least one primary magnet (3) independently of the drive of the movement unit (4), and an actuator (9) and/or a load on the movement unit (4), the magnetically activatable element (7) being in operative connection with the actuator (4) and/or the load. |
| US09866095B2 |
End-ring for induction motor, rotor having the same
A rotor comprises a rotor core comprising a rotational axis and a plurality of slots, a plurality of rotor bars inserted in the plurality of slots, and a plurality of holders arranged around a rotational axis of the rotor. Each holder comprises an insertion groove configured to receive and engage with an end of one of the plurality of rotor bars. An end of another rotor bar among the plurality of rotor bars is interposed between and coupled to two immediately neighboring holders among the plurality of holders. |
| US09866084B2 |
Insulated stator of a motor having holding grooves to hold end parts of a coil winding
A core segment sub-assembly has a first holding groove, which holds a start part of a coil wire of a three-phase winding, and a second holding groove, which holds an end part of the coil wire of the three-phase winding, at positions on an axial end surface of an annular covering part and shifted in a circumferential direction relative to a tooth covering part, on which the winding is provided. The first holding groove and the second holding groove sandwiches the tooth covering part and are separated more from each other as extending in a radially outward direction. The positions and the directions of the first holding groove and the second holding grooves are matched to the paths of the coil wire wound by a flyer type winding machine. The stator can thus be made suited to a winding process by the flyer type winding machine. |
| US09866079B2 |
Electric motor
An electric motor includes a rotor and a wound stator structure. The stator structure includes a housing, a laminated stator core and windings wound around the stator core. The laminations of the stator core have an annular body and a plurality of teeth extending radially inwardly from the annular body. Projections and recesses are formed at the outer edge of the annular body. When assembled, the recesses of one lamination are aligned with the projections of an adjacent lamination such that when fitting the stator into the housing the projections may be deformed into an axially adjacent recess by contact with the housing. Thus the stator core contacts the housing at discrete locations. |
| US09866078B2 |
Brush assembly mount
An electric motor is provided including a stator assembly having a stator body and magnets attached to an inner surface of the stator body via an adhesive, and an armature rotatably received within the stator assembly and having an armature shaft on which a commutator is mounted. A brush assembly is provided including a brush card mount disposed around the commutator and a mating housing longitudinally extending from the brush card mount. The mating housing includes a cylindrical wall and a mating surface formed substantially perpendicularly to an inner surface of the cylindrical wall and arranged to mate with an end surface of the stator body. The mating surface of the mating housing includes posts longitudinally extending along the inner surface of the cylindrical wall and recessed surfaces formed therebetween, the posts being mounted on the end surface of the stator body. |
| US09866077B2 |
Rotor and reluctance motor
A rotor for an electrical machine, in particular synchronous reluctance machine, is provided. The rotor is formed as a cylindrical structure having a magnetically soft element formed with an even number of salient magnetic poles openings for forming magnetic flux barriers. The openings are at least partially filled with a diamagnetic and/or paramagnetic medium and the diamagnetic and/or paramagnetic medium may axially and tangentially fix the magnetically soft element relative to the rotor. A method for producing such a rotor and apparatus using the rotor, including a reluctance motor, in particular a synchronous reluctance motor, that uses the rotor are provided. |
| US09866074B2 |
Integrated circuits for transmitting wireless power, receiving wireless power, and/or communicating wirelessly
The disclosed technology relates to wireless communication and wireless power transmission. In some implementations, the disclosed technology is directed to an integrated circuit having a transmitter that transmits radio frequency (RF) based wireless power and receives signals for detecting the location of a client device. The disclosed technology is also directed to an integrated circuit for a client device that receives power from the transmitter and transmits beacon signals, which the transmitter can use to locate the client device. |
| US09866071B2 |
Wireless power transmission device for closed space
A wireless power transmission device includes an inner retainer fixed to an inner surface of a wall and supporting a power-receiving coil in proximity to a power transmission wall, and an outer retainer fixed to an outer surface of the wall and supporting a power-supplying coil in proximity to the power transmission wall, wherein the electric power is wirelessly transmitted between the power-supplying coil and the power-receiving coil. |
| US09866069B2 |
Manually beam steered phased array
A beam steered phased array antenna and system for including the same are described. In one embodiment, the antenna apparatus comprises an array of a plurality of antenna elements, the array having a single moveable feeding point coupled to the antenna elements, where the moveable feeding point is movable with respect to the antenna elements in the array. |
| US09866066B2 |
Wireless power transfer via electrodynamic coupling
Wireless power transmission (WPT) systems are provided. According to an embodiment, the WPT system uses one or more power transmitting coils and a receiver for electromagnetically coupled wireless power transfer. The electrodynamic receiver can be in the form of an electrodynamic transducer where a magnet is allowed to oscillate near a receiving coil to induce a voltage in the receiving coil, a piezoelectric transducer where the magnet causes a vibrating structure with a piezoelectric layer to move, an electrostatic transducer where movement of the magnet causes a capacitor plate to move, or a combination thereof. An alternating magnetic field from the transmitting coil(s) excites the magnet in the receiver into mechanical resonance. The vibrating magnet then functions similar to an energy harvester to induce voltage/current on an internal coil, piezoelectric material, or variable capacitor. Embodiments utilize magnetic coupling and electromechanical resonance for safe, spatially distributed, low-frequency power delivery to portable devices. |
| US09866062B2 |
Electrical device
There is provided an electrical device (10) comprising electrical elements communicating with an integral power supply (12), wherein a power connection means (22) associated with the electrical elements (13, 13′ and 14) is adapted to receive a temporary external source of electrical power such as a battery (24) to allow removal and replacement of the integral power supply without interrupting power to the electrical elements. The integral power supply (12) is adapted to receive an enduring external power source, with a second switch (32) provided to disable connection of the integral power supply (12) to the enduring power source while the battery (24) is connected. |
| US09866058B2 |
Power feeding device, power receiving device, and wireless power transmission device
A power receiving device, a power feeding device, and a wireless power transmission device are provided. The power receiving device receives power wirelessly transmitted from the power feeding device and includes one or more power receiving units. At least one of the power receiving units in the power receiving device is disposed along two or more surfaces which form the outer shape of the power receiving device and are not parallel to each other. |
| US09866053B2 |
Method for compensating alternator regulation to control remote battery voltage utilizing adaptive variable
A method for compensating for alternator to battery voltage drop in charging systems lacking external remote sensing capabilities and utilizing serial communications. A controller utilizes an adaptive variable for determining an alternator output voltage setpoint that compensates for battery cable voltage losses, and adjusting the setpoint to achieve substantially constant battery voltage of the entire range of alternator loads. |
| US09866052B2 |
Secondary battery charging system and method, and battery pack
Even after the battery reaches the last stage of the end of life, the use can be continued. A charging system includes battery pack and charger. During the charge of lithium-ion secondary battery, charge control unit calculates the full charge capacity maintaining rate, sets a first charge current value on the basis of the full charge capacity maintaining rate, and charges the battery. When lithium-ion secondary battery reaches the last stage of the end of life, charge control unit sets a second charge current value lower than the first charge current value set based on the full charge capacity maintaining rate, and charges the battery. |
| US09866047B2 |
Multi-battery and multi-device connection system
An electrical connection system that connects and disconnects a plurality of supply circuits. More specifically, a connection system that can quickly connect two or more batteries in series or in parallel by connecting a wire bridge system to two or more mated battery side connectors. Alternatively, the connection system can quickly connect a plurality of devices to one battery connection point by connecting a multi-device connector to a mated battery side connector. |
| US09866040B2 |
Power transmission device and wireless power transmission system
A power transmission device applies a alternating-current voltage to an active electrode OPPOSING an active electrode of a power reception device with a gap therebetween, and to a passive electrode OPPOSING a passive electrode of the power reception device with a gap therebetween and transmits power via electric field coupling. The power transmission device includes a controller that monitors a voltage applied to the passive electrode. If a change in the voltage per unit time exceeds a threshold, the controller determines that a metal foreign object has become interposed between the active electrodes and a user has touched the metal foreign object, and stops the transmission of power to the power reception device. Thus, a power transmission device and a wireless power transmission system are provided that are capable of preventing with certainty a malfunction due to a foreign object when a foreign object has become interposed between electrodes. |
| US09866038B2 |
Wireless power transmission system
A power transmission apparatus includes capacitors connected in series between an active electrode and a passive electrode. A power reception apparatus includes capacitors connected in series between an active electrode and a passive electrode. When a capacitance between the active electrodes is represented by Caa, a capacitance between the passive electrodes is represented by Cpp, and reactances of the capacitors are represented by X1, X2, X3, and X4; the active electrodes, the passive electrodes and the capacitors are configured such that Cpp/Caa=X1/X2=X3/X4 and Cpp≧Caa are satisfied. Thus, a wireless power transmission system capable of stabilizing an operation of a load circuit in the power reception apparatus is provided. |
| US09866036B2 |
Electricity supply device and electricity reception device
The electricity supply device (100) supplies electricity using electromagnetic force and opposes an external electricity reception coil (153a). An electricity supply coil (102a) has a hollow section (102b), and has a spiral shape. A reader (103) has an antenna disposed in the projected space resulting from projecting the hollow section (102b) in the central axial direction of the electricity supply coil (102a) and at a position more separated from the electricity reception coil (153a) than the opposing surface that opposes the electricity reception coil (153a) and is of the electricity supply coil (102a), and ID data transmitted by an RF tag (154) installed proximally to the electricity reception coil (153a) is received and detected by the antenna. An electricity-supply-side control unit (104) determines the presence/absence of an electricity reception coil (153a) on the basis of the ID data detected by the reader (103). |
| US09866035B2 |
Rotatable coupling
A rotatable coupling includes an input housing rotatably coupled to an output housing by a tube fixed to the output housing and on which tube the input housing rotates. The coupling includes two magnetic flux concentrators disposed about the tube and defining therebetween an annular cavity, a first concentrator fixed to the input housing and a second concentrator fixed to the output housing, such that relative rotation of the housings causes relative rotation of the concentrators on either side of the annular cavity. The coupling includes concentric coils disposed within the annular cavity that permit power transfer across the coupling, a first coil fixed to the input housing and a second coil fixed to the output housing; an emitter fixed to the input housing; and a receiver fixed to the output housing and positioned to receive the signals from the emitter during the relative rotation of the housings. |
| US09866031B2 |
Method and apparatus for power control
According to one embodiment, a power control apparatus includes a receiving unit, an environment-data acquiring unit, and a calculation unit. The receiving unit receives, from a power supplying side, a power-consumption reduction request for reducing power consumption at a power demanding side. The environmental data acquiring unit acquires, from the power demanding side, environmental data representing environmental state of the power demanding side. The calculating unit calculates a power-reduction value based on the environmental data, in response to the power-consumption reduction request. |
| US09866027B2 |
Device and method for controlling high voltage direct current transmission system
A device for controlling a high voltage direct current (HVDC) transmission system is provided. The device includes: a communication unit communicating with a control device; a control unit obtaining a databack signal received through the communication unit, checking a data line error and a line connection error based on an obtained databack signal, and outputting a valve control signal based on the databack signal; and an output unit outputting the valve control signal to a valve control device based on control of the control unit. |
| US09866023B2 |
Security concept for integrating a battery into an inverter
An inverter apparatus includes an input stage receiving DC electric power from a DC power generator for loading a DC voltage link, a DC/AC converter connected to the DC voltage link and feeding AC electric power into a power grid. The apparatus further includes a bidirectional connection for loading a battery out of the DC voltage link and for loading the DC voltage link out of the battery, and a controller operating the DC/AC converter and the bidirectional connection. The controller receives present values of relevant parameters of the battery including working data at least related to a state of charge and safety data indicating a safety state of the battery from a battery monitoring unit. The controller, in operating the bidirectional connection, considers the working data and is commanded by the safety data. |
| US09866022B2 |
Power supply system
When an AC line of one local system and a power system are in a parallel-off state, a control device included in a power supply system causes local inverter devices of the local systems to operate in a parallel-off operation mode in which control is performed such that the voltage and frequency of power on the AC line is at a target voltage and a target frequency determined according to the state of charge of a power storage device. When a condition for switching to the connected state has been satisfied, the control device stops operation of the local inverter device in the parallel-off operation mode and causes a switch to the connected state by operating the interrupting device, and thereafter causes the local inverter device to operate in a charging operation mode used in charging the power storage device with supplementary power received from the power system. |
| US09866017B2 |
DC power generation system and protection method for DC power generation system
A DC power generation system in which an arc detector, comprising an arc noise analysis unit which detects an arc which occurs in a DC power generation system based on noise of signal of a voltage-current sensor, a voltage-current variation analysis unit for specifying an arc occurrence point in a case where an arc is detected in the arc noise analysis unit, a voltage-current operation point of output of each string is analyzed based on a signal from a voltage-current sensor and based on variation of voltage-current operation point before and after when an arc is detected and a switch control unit for controlling of opening or closing of a switch based on an arc specified result in a voltage-current variation analysis unit, is provided. |
| US09866014B2 |
Electronic device with shared EOS protection and power interruption mitigation
In an embodiment, an electronic device comprises a shared electrical over-stress (EOS) protection circuit. The shared EOS protection circuit may be coupled between a power input terminal and ground terminal to provide an EOS current path from the power input terminal to the ground terminal, and coupled between the output terminal and the ground terminal to provide an EOS current path from the output terminal to the ground terminal. The electronic device may also include a power interruption mitigation circuit to provide power to the electronic device during interruptions or fluctuations in external power. |
| US09866007B2 |
Electrical cord connection covering techniques
According to techniques of the present application, an apparatus for covering at least a portion of a cord includes a lower portion and an upper portion. The lower portion may include a bowl region having an upper rim. The lower portion may also include flexible tabs that substantially surround or completely surround the upper rim. Each of the flexible tabs may extend outwardly or downwardly from the upper rim. The upper portion may have a lower rim that extends below the outer edges of each of the flexible tabs when the upper portion is engaged to the lower portion. The upper portion may contact each of the flexible tabs when the upper portion is engaged to the lower portion. The apparatus may include a securing member extending downwardly from the lower portion to secure the apparatus to a resting surface. |
| US09866004B2 |
Hanger for mounting cables
A cable hanger includes: a base panel having opposed ends; a pair of arms, each of the arms attached to a respective end of the base panel and having a free end; a pair of locking projections, each of the locking projections attached to a respective free end of the arms; and a pair of gripping members, each gripping member attached to a respective arm, each gripping member having opposed ends, wherein one of the ends of each gripping member is fixed to the arms and the other of the ends of each gripping member is fixed to the arm or to the base panel. The arms and locking projections are configured to spread apart to enable insertion of a cable between the arms, wherein the gripping projections engage and grip the cable, and wherein the locking projections are configured to be inserted into the aperture of the supporting structure. |
| US09865996B2 |
Polarized resin film and process for producing same
An object of the present invention is to provide a polarized vinylidene fluoride/tetrafluoroethylene copolymer resin film that can significantly reduce, when used as an optical film, the deterioration of the quality of video or still images formed by display elements.The present invention provides a polarized vinylidene fluoride/tetrafluoroethylene copolymer resin film having 2,000 or fewer spot defects per m2, the number of spot defects being measured by a defect measurement method;the method using an surface inspection system in which a CCD camera is placed so as to detect defects at an angle of 45 degrees relative to an LED source, defects of the film are read within a rectangular range of 300 mm in a width direction (the direction perpendicular to the scanning direction), and 150 mm in a machine direction (the scanning direction), while the film is scanned under the camera at a rate of 20 m/min;wherein first, defects having a bright area of 1.5 mm2 or less and a dark area of 1.4 mm2 or less are selected; andnext, in order to remove defects resulting from causes other than a corona treatment contained in these defects, a circumscribed rectangle of defect is set so as to have two sides along the scanning direction, and the number of only defects that have a circumscribed width of 2.88 mm or less, a circumscribed length of 2.3 mm or less, an aspect ratio of −39 to +27, an occupancy area ratio in the circumscribing rectangle of 4,000 to 6,950, and an area ratio of −3,100 to +5,200, is automatically counted as spot defects by the surface inspection system. |
| US09865990B2 |
Monolithic wide wavelength tunable mid-IR laser sources
A method of characterizing a monolithic tunable mid-infrared laser including a heterogeneous quantum cascade active region together with a least first and a second tunable integrated distributed feedback gratings, the method including operating the laser while tuning the first grating through its full tuning range, while holding the reflectivity function of the second grating constant, then operating the laser while tuning the second grating through its full tuning range, while holding the reflectivity function of the first grating constant. |
| US09865988B2 |
High-power planar waveguide (PWG) pumphead with modular components for high-power laser system
A system includes a laser system having a master oscillator and a planar waveguide (PWG) amplifier having one or more laser diode pump arrays, a PWG pumphead, input optics, and output optics. The PWG pumphead is configured to receive a low-power optical beam from the master oscillator and generate a high-power optical beam. The PWG pumphead includes a laser gain medium, a cartridge, and a pumphead housing. The cartridge is configured to receive and retain the laser gain medium, and the cartridge includes one or more cooling channels configured to transport coolant in order to cool the laser gain medium. The pumphead housing is configured to receive and retain the cartridge, where the cartridge is removable from the housing. |
| US09865986B2 |
Coherent combining pulse bursts in time domain
A beam combining and pulse stacking technique is provided that enhances laser pulse energy by coherent stacking pulse bursts (i.e. non-periodic pulsed signals) in time domain. This energy enhancement is achieved by using various configurations of Fabry-Perot, Gires-Tournois and other types of resonant cavities, so that a multiple-pulse burst incident at either a single input or multiple inputs of the system produces an output with a solitary pulse, which contains the summed energy of the incident multiple pulses from all beams. This disclosure provides a substantial improvement over conventional coherent-combining methods in that it achieves very high pulse energies using a relatively small number of combined laser systems, thus providing with orders of magnitude reduction in system size, complexity, and cost compared to current combining approaches. |
| US09865985B1 |
Widely tunable infrared source system and method
A system and method for tuning and infrared source laser in the Mid-IR wavelength range. The system and method comprising, at least, a plurality of individually tunable emitters, each emitter emitting a beam having a unique wavelength, a grating, a mirror positioned after the grating to receive at least one refracted order of light of at least one beam and to redirect the beam back towards the grating, and a micro-electro-mechanical systems device containing a plurality of adjustable micro-mirrors. |
| US09865982B1 |
Environmentally robust and compact mode-locked laser
A mode-locked laser has optical components integrated into a single apparatus and interrelated via optical free-space coupling. The laser optical cavity path is reduced to less than ten meters, primarily composed of optical gain fiber. A Fabry-Perot filter is matched to the laser pulse repetition frequency. Utilizing a Fabry-Perot filter within the laser optical cavity suppresses supermode spurs in the phase noise spectrum; thereby reducing total timing jitter. |
| US09865979B2 |
Brush holder assemblies and methods for mounting and replacing brushes
An assembly has a handle, a brush holder, and a support that connect and disconnect to each other using a locking mechanism. The handle reversibly connects and disconnects from the brush holder. The locking mechanism includes a connecting member on the brush holder that attaches to the handle by interaction of a locking flange on the connecting member with a pair of teeth inside of the handle. Insertion of the support within the brush holder extends a post on the support through the connecting member to interact with the handle and enable disconnection of the handle from the brush holder when the support is fully engaged by the brush holder. The locking mechanism prevents the handle from releasing from the brush holder before the brush holder is completely seated on the support. |
| US09865976B2 |
High-density data communications cable
Disclosed is a system for operating a network incorporating high-density connections for increased efficiency, network operation and management. The high-density connections are incorporated into the patch panel, network switch, and cables that connects them, as well as into cable analyzers and printed circuit boards (PCBs) which allow for a complete network within a single computer running virtualization software. |
| US09865975B2 |
Hinged connector door assembly
A door assembly for attachment to a connector housing is shown. The door assembly comprises a pair of opposed doors mounted on either side of an opening by a hinge, which when in a closed position define a cable receiving opening there between. Supports are provided on either door which grip the of cable therebetween when the doors are in the closed position. In a particular embodiment a locking mechanism is provided to retain the doors in a closed. |
| US09865972B2 |
Electrical connector with spring clip
A connector assembly including a connector body with a spring clip including a first free end for engaging a side wall of an electrical box upon installation. During insertion of the connector body the first free end is deformed so as to permit further insertion. Once the connector body is fully inserted, the spring clip cooperates with a lug on the connector body to hold the connector assembly onto the electrical box. |
| US09865969B2 |
Connector assembly which is configured to be mounted on a structural member via a fixing member
A connector assembly having first and second connectors. The first connector includes a first housing which is configured to receive an installed fixing member. The second connector includes a second housing which is mated with the first connector. The first housing includes a fixing member installation portion having a deformable flexible locking member for locking the fixing member. The second housing includes a stopping member for preventing deformation of the flexible locking member when mating of the first connector and the second connector has been completed. |
| US09865965B2 |
Waterproof structure for terminal of wire with terminal fitting
The present invention provides a waterproof structure for a terminal of a wire with a terminal fitting provided with a waterproof block made of resin, the waterproof block covering an end portion of an insulation coated wire which is coupled to a terminal fitting. The waterproof block includes a waterproof portion covering a coupling portion coupling the end portion of the wire and the terminal fitting, the waterproof portion adhering to an outer circumferential surface of an end of an outer skin of the wire, and a cylindrical portion projecting cylindrically from the waterproof portion along the outer skin of the wire. The cylindrical portion has a smaller cross sectional area than the waterproof portion and has rigidity more similar to the outer skin than the waterproof portion in desired bending and torsional directions of the wire and is adhered to an end-adjacent outer circumferential surface of the outer skin. |
| US09865962B2 |
Electrical connector assembly having waterproof function and method of manufacturing the same
The present invention relates to an electrical connector assembly comprising: an insulative housing; a plurality of terminals received into the insulative housing; metallic shell enclosing the insulative housing; and waterproof material sandwiched between the insulative housing and the metallic shell. |
| US09865959B2 |
Modular plug-in connector
The invention relates to a plug-in connector comprising a frame (10) for detachably latching a plurality of contact support modules (20, 21) of the width 0.5×B, 1×B, 1.5×B or 2×B, the frame being formed by two mutually opposed longitudinal lateral walls (11) and by two mutually opposed transversal lateral walls (12), wherein at least two contact support modules (20, 21) of different width can be received in and latched to the frame, the contact support modules having at least one latching element (23) that interacts with a corresponding counter-latching element (13) arranged on the frame in order to detachably secure the contact support modules in the frame, a rigid grid of latching elements being arranged externally on the longitudinal lateral walls (11) of the frame (10) at a uniform grid spacing of the counter-latching elements (13) of 0.5×B. |
| US09865957B2 |
Electrical pop out device with electrical outlets and/or USB ports
An electrical pop out device has a shroud and an outlet housing. The outlet housing is sized to be placed inside the shroud. A guidance mechanism connects the outlet housing with the shroud. The guidance mechanism includes multiple rack gears and multiple pinion gears. The outlet housing is moveable with respect to the shroud along a direction defined by the rack gear. A spring connector electrically couples the shroud to the outlet housing. |
| US09865953B2 |
Electrical contact assembly for printed circuit boards
A socket housing and contact assembly process includes forming the solder ball contact region after initial installation of a set of contacts into the housing. The contact regions of the set of contacts pass through corresponding contact cavities to extend beyond the housing and the contact regions are formed over at equal angles for solder ball placement. |
| US09865944B2 |
Output terminal, insulator sleeve, cover for AC generator and assembly thereof
An output terminal for a vehicle AC generator is provided. The output terminal comprises: a bolt and a cylinder nut. The bolt has outer threads and is inserted through a through hole of a rectifier unit. The cylinder nut has inner threads, which engage with the outer threads of the bolt so that the cylinder nut surrounds the outer circumference of the bolt and fixes the bolt to the rectifier unit. The cylinder nut has a recess in its outer circumference. An insulating sleeve may be provided on the output terminal. The insulating sleeve has at least an internal protrusion for being received in and engaged with the recess of the cylinder nut. |
| US09865941B1 |
Electrical connectors for high density attach to stretchable boards
A system can include a first portion of a fabric fastener, a second portion of the fabric fastener, wherein the first portion and the second portion are configured to mechanically connect with each other and to resist separation from each other once connected, and wherein the first and second portions include a plurality of corresponding electrical contacts configured to form a plurality of individual electrical connections when the first portion is mechanically connected with the second portion. |
| US09865940B2 |
Direct plug-in compression spring terminal with retaining spring
A direct plug-in compression spring terminal includes a bus bar for contacting an electrical conductor, and a clamping spring for fastening the electrical conductor in the direct plug-in compression spring terminal, wherein the clamping spring has a clamping arm that can be pivoted in a clamping direction about a clamping axis, and an actuating device for pivoting the clamping bar. In an open state, in which the electrical conductor can be inserted into the direct plug-in compression spring terminal, the clamping arm is pivoted against the clamping direction against a restoring force of the clamping spring. In a clamping state, in which the electrical conductor is clamping in the direct plug-in compression spring terminal, the clamping arm is pivoted in the clamping direction by the restoring force of the clamping spring. In the open state, the actuating device is locked in the direct plug-in compression spring terminal and additionally clamped to the clamping arm. |
| US09865938B2 |
Apparatus for electrically bonding a solar array
In various representative aspects, an apparatus for securing solar panels to a rail support guide, while facilitating grounding by a common grounding wire. The apparatus is an electrically conductive lay-in-lug fastener, which facilitates multiple rows of solar panels to be electrically bonded to each other. The apparatus includes a lug member for securing the grounding wire. In doing so, the structure for securing the grounding wire is at an acute angle to the frame, enabling a wrench to be used even in space-challenged locations. |
| US09865937B1 |
Method for fabricating radiating element containment and ground plane structure
A method for fabricating a radiating element containment and ground plane structure. The method includes positioning post components, wherein each of the post components has at least one channel. The method further includes positioning a ground plane component including insertion slots and post attachment points. The method also includes attaching the post components to the ground plane component such that each post component is electrically grounded to the ground plane component. |
| US09865936B2 |
Array antenna feed structures
An array antenna has rectangular conductor sections, located successively side by side in a first plane, mutually separated by slots of constant width. A backing reflector is transverse to the first plane. Feed structures extend through the backing reflector, the feed structures comprising pairs of parallel feed conductors, each pair comprising conductors coupled to the rectangular conductor sections on opposite sides of a respective one of the slots. |
| US09865935B2 |
Printed circuit board for antenna system
A Printed Circuit Board (PCB) comprising various integral components and method of manufacture are provided. The PCB includes a Substrate Integrated Waveguide (SIW), integrated waveguide antennas disposed above the SIW, apertures formed in SIW for coupling with the waveguide antennas, a transmission line routed above the SIW and using the SIW as a ground plane thereof, and further antennas, integrated into the PCB and disposed above and coupled to the transmission line. The SIW and the transmission line may be branched structures for feeding corresponding arrays of waveguide antennas and further antennas. Coplanar waveguides may also be integrated into the PCB and coupled to the SIW and the transmission line via integral impedance matching structures. PCB feature re-use and component interleaving may provide for a desirable and manufacturable PCB structure. |
| US09865934B2 |
Ultra-wideband extremely low profile wide angle scanning phased array with compact balun and feed structure
A phased array antenna comprising a dielectric superstrate material, a ground plane material, a plurality of dipole structures located between the superstrate and ground plane materials, and a plurality of balun and matching networks in electrical communication with the plurality of dipole structures, wherein the phased array antenna is adapted to achieve a bandwidth of at least about 7:1. |
| US09865933B2 |
Method for calibrating a radar sensor, and radar system
A method, and corresponding radar system, for calibrating a radar sensor, including: placing at least one reference object at a predetermined position in the field of view of the radar sensor; sensing an estimated position of the at least one reference object by way of the radar sensor; calculating a correction value for the position of the at least one reference object based on the predetermined position of the at least one reference object and on the estimated position, sensed by the radar sensor, of the at least one reference object; and applying the calculated correction value to estimated positions, sensed by the radar sensor, of further objects in the field of view of the radar sensor. |
| US09865928B2 |
Dual-polarized antenna
In a multilayer substrate (2), an internal ground layer (11) is provided at a position between insulating layers (4) and (5) and a radiating element (13) is provided at a position between insulating layers (3) and (4). A first coplanar line (7) is connected to an intermediate position of the radiating element (13) in an X-axis direction, and a second coplanar line (9) is connected to an intermediate position of the radiating element (13) in a Y-axis direction. A passive element (16) is laminated on the upper surface of the radiating element (13) through the insulating layer (3). The passive element (16) is formed in a cross shape in which a first patch (16A) extending in the X-axis direction and a second patch (16B) extending in the Y-axis direction are orthogonal to each other. |
| US09865923B2 |
Antenna
An antenna includes antenna coil having a magnetic-material core and a coil conductor. The antenna coil is arranged toward a side of a planar conductor, such as a circuit board. Of the coil conductor, a first conductor part close to a first main face of the magnetic-material core and a second conductor part close to a second main face of the magnetic-material core are provided such that the first conductor part is not over the second conductor part in view from a line in a direction normal to the first main face or the second main face of the magnetic-material core. In addition, a coil axis of the coil conductor is orthogonal to the side of the planar conductor. |
| US09865918B2 |
Sliding radome with support structure
A radome includes a shell defining an internal volume. A track is coupled to the shell, and the track allows the shell to move axially between an open position and a closed position. A support structure is coupled to the shell, and the support structure moves from a collapsed position to an expanded position. |
| US09865912B2 |
Universal ceiling antenna mount
A universal ceiling antenna mount may include a plate having a first side and a second side. The plate may include at least one antenna adapter hole, at least one mounting post attached to the second side of the plate, and at least one stem having a top open end and a bottom open end. The bottom open end of the stems may attach to the second side of the plate over the antenna adapter holes. A top plate having at least one hole and at least one mounting hole may sandwich a ceiling tile with the second side of the plate and be secured. At least one coaxial antenna cable may be connected to a top side of mount. At least one antenna may be connected to a bottom side of the mount. |
| US09865911B2 |
Waveguide system for slot radiating first electromagnetic waves that are combined into a non-fundamental wave mode second electromagnetic wave on a transmission medium
Aspects of the subject disclosure may include, for example, a system for generating first electromagnetic waves and directing instances of the first electromagnetic waves to an interface of a transmission medium to induce propagation of second electromagnetic waves substantially having a non-fundamental wave mode. Other embodiments are disclosed. |
| US09865910B2 |
Optimized coaxial transmission line and method for overcoming flange reflections
An optimized coaxial transmission line having joined segments of coaxial transmission lines is provided. First insulating supports positioned at flange joints within the joined segments are provided. Second insulating supports are positioned a distance x, where x = 1 4 λ + n · 1 2 λ , from the first insulating supports to cancel reflections created by the insulating supports. Preferably, x=¼λ, and the second insulating supports are positioned for one quarter of a wavelength at either FM frequencies, VHF frequencies, UHF frequencies, or IBOC frequencies. A method for optimizing a transmission line by frequency is also provided. First, segments of coaxial transmission lines are joined together, each segment having a first insulating support positioned at a flange joints within the joined segment. Next, a second insulating support is positioned along the length of each segment of coaxial transmission line a distance x from said first insulating support, where x = 1 4 λ + n · 1 2 λ . |
| US09865904B2 |
Battery cell of improved cooling efficiency
Disclosed herein is a battery cell configured such that at least one electrode assembly of a structure having a cathode, an anode, and a separator interposed between the cathode and the anode is mounted in a battery case, at least one heat dissipation member to dissipate heat generated in the electrode assembly during charge and discharge of the battery cell or upon occurrence of a short circuit is disposed in the electrode assembly and/or is in contact with an outer surface of the electrode assembly, and a portion of the heat dissipation member is exposed outward from the electrode assembly. |
| US09865903B1 |
Portable renewable energy power system
A portable renewable energy power system, the system having a first solar panel attached to an enclosure; a second solar panel hingeably attached to the enclosure; in an open position wherein the second solar panel is exposed and extends out from the enclosure; in a closed position; a battery module; a user interface comprising at least one input device and at least one display; an alternating current/direct current (AC/DC) converter; a direct current/alternating current (DC/AC) converter; and, a control module configure to provide: a solar charge configuration; a battery only configuration; a solar only configuration; and a solar and battery configuration, and a handle attached to the enclosure for carrying the system. |
| US09865902B2 |
Device for monitoring an electrical accumulation battery and associated method
A device is provided for monitoring an electrical accumulation battery that includes a set of cells connected in series. The device includes means for measuring a current intensity delivered by the battery; means for measuring an electrical voltage between an upstream connection point and a downstream connection point of each cell of the battery; a recorder that records a zero-current electrical voltage between the upstream connection point and the downstream connection point of each cell of the battery; and an electrical resistance estimator configured to periodically estimate an electrical resistance of each cell in the battery, between the upstream connection point and the downstream connection point. |
| US09865900B2 |
Solid electrolyte interphase film-suppression additives
An energy storage device comprising: (A) an anode comprising graphite; and (B) an electrolyte composition comprising: (i) at least one carbonate solvent; (ii) an additive selected from CsPF6, RbPF6, Sr(PF6)2, Ba(PF6)2, or a mixture thereof; and (iii) a lithium salt. |
| US09865898B2 |
Power storage module and fixing structure of power storage module
A power storage module is formed by superimposing a pair of end plates at opposite ends in the stacking direction of a plurality of power storage cells that are stacked in the stacking direction. The pair of end plates are connected by a frame holding an insulator between itself and the power storage cells. Condensed water occurring on the surface of the power storage cells could contact the end plate. There is thus a possibility that a liquid junction will be formed; when the power storage module is in a mounted state the insulator includes a first rib extending in a direction, condensed water attached to the insulator cannot flow toward the end plate due to it being blocked by the first rib, thus preventing the power storage cell from forming a liquid junction with the end plate via the condensed water. |
| US09865897B2 |
Stacked electrochemical cell with increased energy density
An electrochemical cell assembly (500) includes a first cell and a second cell. The first cell can include a first anode (503) and a first cathode (504), wound in a first jellyroll assembly (501) with a first jellyroll assembly exterior defined by the first cathode. The second cell can include a second anode (512) and a second cathode (513), wound in a second jellyroll assembly (502) with a second jellyroll assembly exterior defined by the second anode. The first cell and the second cell can be arranged in a housing with the first jellyroll assembly exterior adjacent to the second jellyroll assembly exterior to improve energy density. The first cell assembly and the second cell assembly can have different widths to create differently shaped cell assemblies. |
| US09865896B2 |
Stack assembly comprising flexible compression force mat
A solid oxide fuel or solid oxide electrolysis cell Stack assembly (203) has an improved, simple, cost reducing and robust compression System, housing and Single sided System interface with a flexible-interface-fixture (204) which is rigid enough to fix the at least one cell Stack in the housing when not in Operation, but flexible enough to allow for transfer of the compression force from the flexible compression mat (211) in the top closed end of the housing (201), through the at least one cell Stack and further towards the interface counterpart of the System when in Operation. |
| US09865895B2 |
Methods to prepare stable electrolytes for iron redox flow batteries
An iron redox flow battery system, comprising a redox electrode, a plating electrolyte tank, a plating electrode, a redox electrolyte tank with additional acid additives that may be introduced into the electrolytes in response to electrolyte pH. The acid additives may act to suppress undesired chemical reactions that create losses within the battery and may be added in response to sensor indications of these reactions. |
| US09865891B2 |
System and method for diagnosing state of cooling water
A system for diagnosing a cooling water state applied to a cooling water pump control system is provided. The cooling water pump control system includes a speed controller that generates an output current instruction value of an inverter to provide power to a cooling water pump based on a difference between a speed instruction value of the cooling water pump and an actual speed measurement value of the cooling water pump. The system for diagnosing a cooling water state includes a pump speed prediction model unit that generates a speed estimation value to predict a speed of the cooling water pump based on the output current instruction value, and a pump state diagnosing unit that compares the speed estimation value and the actual speed measurement value to diagnose a circulation state of the cooling water. |
| US09865889B2 |
Solid electrolyte fuel battery having anode and cathode gas supply channels with different cross-section areas
A solid electrolyte fuel battery having a fuel gas supply channel that is composed of a first anode gas supply channel part, at least a part of an inner wall surface of which is a fuel electrode layer, and a second anode gas supply channel part; and an air supply channel that is composed of a first cathode gas supply channel part, at least a part of an inner wall surface of which is an air electrode layer, and a second cathode gas supply channel part. The cross-section area of the first anode gas supply channel part is larger than the cross-section area of at least a portion of the second anode gas supply channel part. The cross-section area of the first cathode gas supply channel part is larger than the cross-section area of at least a portion of the second cathode gas supply channel part. |
| US09865887B2 |
Scalable, massively parallel process for making micro-scale particles
A method of fabrication produces one or more functional microparticles using a parallel pore working piece. In one embodiment, the method forms a particle that includes a segment for the oxidation of a biofuel (such as glucose) and the reduction of oxygen. The particle may be synthesized in a structure with defined and parallel, uniform, thin pores that completely penetrate the structure. Further, the functional microparticle may be configured to reside in a human or animal body or cell such that i t may be self-contained fuel cell having an anode, a cathode, a separator membrane, and a magnetic component. In other embodiments, the functional microparticles may deliver energy or therapeutic materials in the body. |
| US09865886B2 |
Coolable battery system, method for cooling a battery and automobile comprising a coolable battery system
A battery includes at least one integrated first heat exchanger element that forms an integral part of the battery and is formed in one piece with the battery. The heat exchanger element can end flush with the surface of the battery, but it can also protrude from or be recessed into the surface of the battery. A coolable battery system includes at least one such battery and a second heat exchanger element for each battery that can be reversibly brought into thermal operative contact with the first heat exchanger element. A method for cooling such a battery in the coolable battery system, in which the first heat exchanger element of the at least one battery is brought in thermal operative connection with the second heat exchanger element, includes maintaining the second heat exchanger element at a lower temperature level than the first heat exchanger element. |
| US09865885B2 |
Manufacturing method of catalyst ink, manufacturing method of fuel cell, and fuel cell
A catalyst ink for improving the performance of catalyst electrodes in a fuel cell is produced by the following procedure. A catalyst dispersion is prepared by dispersing catalyst-supported particles as conductive particles with a catalyst supported thereon in a solvent. A gel material having viscoelasticity is prepared by mixing an ionomer with a volatile solvent. A catalyst ink having a desired viscosity is produced by stirring and mixing the catalyst dispersion with the gel material. |
| US09865880B2 |
Component including a rechargeable battery
According to the invention there is provided a component including a rechargeable battery and a method of producing same. The component uses one of an acid and an alkaline chemistry and the battery has an anode structure, a cathode structure, and a separator structure which separates the anode from the cathode and contains an electrolyte. The anode structure and the cathode structure are each formed from a composite material which includes electrically conductive fibres and electrochemically active material in a binder matrix including less than 50% w/w of an elastomer binder and the battery is formed to be structurally inseparable from the rest of the component. |
| US09865875B2 |
Method for preparing lithium iron phosphate nanopowder
The present invention relates to a method for preparing a lithium iron phosphate nanopowder, including the steps of (a) preparing a mixture solution by adding a lithium precursor, an iron precursor and a phosphorus precursor in a glycerol solvent, and (b) putting the mixture solution into a reactor and heating to prepare the lithium iron phosphate nanopowder under pressure conditions of 1 bar to 10 bar, and a lithium iron phosphate nanopowder prepared by the method. When compared to a common hydrothermal synthesis method, a supercritical hydrothermal synthesis method and a glycothermal synthesis method, a reaction may be performed under a relatively lower pressure. Thus, a high temperature/high pressure reactor is not necessary and process safety and economic feasibility may be secured. In addition, a lithium iron phosphate nanopowder having uniform particle size and effectively controlled particle size distribution may be easily prepared. |
| US09865870B2 |
Batteries with nanostructured electrodes and associated methods
Several embodiments related to batteries having electrodes with nanostructures, compositions of such nanostructures, and associated methods of making such electrodes are disclosed herein. In one embodiment, a method for producing an anode suitable for a lithium-ion battery comprising preparing a surface of a substrate material and forming a plurality of conductive nanostructures on the surface of the substrate material via electrodeposition without using a template. |
| US09865865B2 |
Method for producing cathodes
Process for producing cathodesProcess for producing cathodes comprising a cathode material comprising (A) at least one lithiated transition metal mixed oxide, (B) carbon in an electrically conductive modification, (C) at least one binder, and also (D) at least one film, wherein (a) a mixture comprising lithiated transition metal mixed oxide (A), carbon (B) and binder (C) is applied to film (D), (b) dried, (c) compacted to such an extent that the cathode material has a density of at least 1.8 g/cm3 to obtain a compacted blank and (d) after compaction as per (c) thermally treated at a temperature in the range from 35° C. below the melting point or the softening point of binder (C) to a maximum of 5° C. below the melting point or the softening point of binder (C). |
| US09865864B2 |
Rechargeable battery
A rechargeable battery that simplifies a structure that implements an external short circuit and that reduces a production cost is provided. The rechargeable battery includes: an electrode assembly that is formed by spiral-winding a first electrode and a second electrode that are disposed at respective surfaces of a separator interposed therebetween; a case that houses the electrode assembly; a cap plate that closes and seals an opening of the case; a first electrode terminal that is connected to the first electrode and that is installed in an insulation state in the cap plate; a second electrode terminal that is connected to the second electrode and that is electrically connected to the cap plate; and a vent plate that is installed in a vent hole of the cap plate and that is short-circuited with the first electrode terminal when the vent hole is opened. |
| US09865863B2 |
Safety apparatus and protection method of secondary battery for electric vehicle using switch
The present invention relates to a safety apparatus and a protection method of a secondary battery, which can prevent explosion and fire of the secondary battery using a switch or a rupture switch attached on the outside of the secondary battery if a swelling degree of the secondary battery reaches a predetermined value when the secondary battery is swelled due to abnormal usage such as overcharge, short-circuit, reverse-connection and heat-exposure of large-capacity lithium polymer battery. |
| US09865862B2 |
Safety material and system
Compositions and methods for deterring and/or visually identifying oral contact with objects that are hazardous upon oral contact or ingestion are disclosed. The compositions generally comprise a colorant and a carrier and may further comprise an aversive agent, a salivating agent, and/or an emetic. The compositions may be particularly useful for application to batteries, including button cells. |
| US09865859B2 |
Stacked-type secondary battery
A structure with suppressed thickness and high-density when battery cells of a thin-film-solid secondary battery are stacked. Adjacent battery cells are stacked such that negative electrodes are in contact with each other and positive electrodes are in contact with each other, and arranged such that a taking-out lead electrode smaller than negative or positive electrode surfaces are sandwiched between two negative electrodes in contact with each other or two positive electrodes in contact with each other, and the lead electrodes sandwiched between electrodes of different layers are arranged such that there is no region where all of the lead electrodes simultaneously overlap one another as viewed in a planar arrangement. There are a strip-shaped lead electrode and a linear lead electrode. Further, a conductive sheet forming the electrode is extended to also serve as the taking-out electrode, thereby making it possible to reduce the number of lead electrodes. |
| US09865855B2 |
Energy storage device
An energy storage device includes a positive electrode, a negative electrode, and an insulating layer arranged between these electrodes to electrically insulate these electrodes. The negative electrode includes a composite layer containing active material particles. The composite layer of the negative electrode, and the positive electrode are arranged to face each other across the insulating layer. The insulating layer contains electrically insulating particles, and is made porous by a gap between these particles. The composite layer of the negative electrode is made porous by a gap between the active material particles, and “−0.8≦Log B−Log A≦1.0” is satisfied in which in a pore distribution of the composite layer, a pore peak diameter is represented by A (μm), and in a pore distribution of the insulating layer, a peak diameter is represented by B (μm). |
| US09865854B2 |
Lithium ion battery separators and electrodes
A lithium ion battery separator includes a porous film of a polymeric chelating agent. The polymeric chelating agent includes a poly(undecylenyl-macrocycle), where the macrocycle is a chelating agent. A positive electrode includes a structure and a coating formed on a surface of the structure. The structure includes a lithium transition metal based active material, a binder, and a conductive carbon; and the coating includes a poly(undecylenyl-macrocycle), where the macrocycle is a chelating agent. The separator and/or positive electrode are suitable for use in a lithium ion battery. |
| US09865852B2 |
Energy storage container with vortex separator
A vortex separator includes: a housing having a cylindrical chamber therein; an inlet through a mantle of the cylindrical chamber, the inlet positioned at a proximal end of the housing; a pipe that enters the housing at the proximal end and extends axially through the cylindrical chamber toward a distal end of the housing which is closed; an outlet through the mantle, the outlet positioned at the distal end; and a catch basin at the outlet. |
| US09865849B2 |
Assembled battery and method for manufacturing assembled battery
A battery pack includes: cells, and electrode tabs including a positive electrode tab and a negative electrode tab which are connected with the power generation element, and which are provided to protrude from end portions of the outer member; frame members each including a front surface and a back surface on which the pair of the cells are mounted; conductive members each of which is disposed on the frame member, and each of which electrically connects the electrode tabs of the pair of the cells; and bus bars each of which electrically connects the conductive members disposed on the frame members of the plurality of the stacked frame members, and which are adjacent in a stacking direction. |
| US09865847B2 |
Outer package material for lithium-ion battery and method for producing lithium-ion battery using the outer package material
A lithium-ion battery outer package material, provided with: a base layer, and a first adhesive layer, a metallic foil layer, a corrosion prevention treatment layer, a second adhesive layer, and a sealant layer sequentially layered on one of the surfaces of the base layer. When a tensile test (a sample of the substrate layer is stored for 24 hours in a 23° C. and 40% RH environment; a tensile test is subsequently performed in a 23° C. and 40% RH environment with the specimen width being 15 mm, the distance between gauge points being 50 mm, and the tensile speed being 100 mm/min; and the tensile elongation and tensile stress of the specimen are measured) is performed, the tensile elongation in a first direction, which is either the TD direction or the MD direction of the sample, relative to the length of the sample is from about not less than 50% to less than 80%, and the tensile stress in a second direction, which is perpendicular to the first direction, is from about not less than 150 to 230 MPa. |
| US09865845B2 |
Case for vehicle's battery pack
Disclosed is a case for a vehicle's battery pack. In an aspect of the present disclosure, it is possible to provide a stable and economic case for a battery pack including a plurality of secondary battery cells. |
| US09865839B2 |
Display unit with moisture proof film outside of seal section and electronic apparatus with said display unit
A display unit including a first substrate and a second substrate that are disposed to face each other, a first organic insulating layer on the first substrate, a plurality of light-emitting elements arrayed in a display region, the display region on the first organic insulating layer and facing the second substrate and a first moisture-proof film covering the first organic insulating layer in a peripheral region, in which the peripheral region is provided on the first substrate and surrounds the display region. |
| US09865838B2 |
Display device having a bent portion
A display device includes: a TFT substrate; a counter substrate; a flat bonding member bonding the TFT substrate and the counter substrate at a display area and an additional function area; and a bent bonding member bonding the TFT substrate and the counter substrate at a peripheral area outside the display area and a peripheral area outside the additional function area, the bent bonding member including a bonding interface at which a shear stress occurs due to the bending of the TFT substrate and the counter substrate. The bent bonding member has a deformation allowance in a direction of the shear stress greater than that of the flat bonding member. |
| US09865837B2 |
Light-emitting device, electronic device, and lighting device
A lightweight flexible light-emitting device that is less likely to be broken is provided. The light-emitting device includes a first flexible substrate, a second flexible substrate, an element layer, a first bonding layer, and a second bonding layer. The element layer includes a light-emitting element. The element layer is provided between the first flexible substrate and the second flexible substrate. The first bonding layer is provided between the first flexible substrate and the element layer. The second bonding layer is provided between the second flexible substrate and the element layer. The first and second bonding layers are in contact with each other on the outer side of an end portion of the element layer. The first and second flexible substrates are in contact with each other on the outer side of the end portions of the element layer, the first bonding layer, and the second bonding layer. |
| US09865835B2 |
Organic electroluminescent device, illumination apparatus, and illumination system
An organic electroluminescent device includes first and second substrates, first and second electrodes, an insulating layer, an organic light emitting layer, and an intermediate layer. The first electrode is provided on the first substrate. The insulating layer is provided on the first electrode. The insulating layer includes first and second openings. The second electrode includes first and second conductive parts. The first conductive part covers the first opening. The second conductive part covers the second opening. The organic light emitting layer includes first and second light emitting parts. The first light emitting part is provided between the first electrode and the first conductive part. The second light emitting part is provided between the first electrode and the second conductive part. The second substrate is provided on a stacked body including above. The intermediate layer is provided between the stacked body and the second substrate. |
| US09865834B2 |
Method of manufacturing an organic EL display device, and organic EL display device
A method of manufacturing a display device includes forming a three-layer laminate by laminating a first transparent conductive film, a metal film, and a second transparent conductive film in order from a substrate side. The three-layer laminate forms a plurality of anode electrodes arranged in a pixel region and a plurality of dummy electrodes arranged on an outer side of the pixel region. The method of manufacturing a display device also includes subjecting the second transparent conductive film and the metal film to etching and subjecting the first transparent conductive film to etching. A density of a pattern of the plurality of dummy electrodes is reduced as a distance from the pixel region is increased. |
| US09865833B2 |
Organic light-emitting device
An organic light-emitting device having a resonance structure includes a substrate; a first electrode and a second electrode on the substrate and facing each other; an emission layer between the first electrode and the second electrode; a first hole transport layer between the first electrode and the emission layer; and a second hole transport layer between the first hole transport layer and the emission layer. An electron mobility of the second hole transport layer is 5 times to 100 times greater than an electron mobility of the first hole transport layer, and a thickness of the second hole transport layer corresponds to a resonance distance of a wavelength of emission light of the emission layer. |
| US09865832B2 |
Light emitting diode display with redundancy scheme
A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. |
| US09865829B2 |
Organic electroluminescent element material and organic electroluminescent element using same
Provided is an organic electroluminescent device (organic EL device) with improved luminous efficiency, sufficiently ensured driving stability, and a simple construction. The organic electroluminescent device includes an anode, an organic layer, and a cathode laminated on a substrate, in which at least one organic layer selected from the group consisting of a light-emitting layer, a hole-transporting layer, an electron-transporting layer, an electron-blocking layer, and a hole-blocking layer contains a carborane compound that has at least one carborane ring with a silyl group on the carbon thereof. |
| US09865828B2 |
Organic light emitting device
An organic light-emitting device is disclosed, the organic light-emitting device comprising a first electrode, a second electrode disposed opposite to the first electrode, and an emission layer comprising organic materials and disposed between the two electrodes. The emission layer may include a host and a dopant. The host may be a silane derivative of anthracene having at least one silicon substituent that is an aryl group having at least two rings that are fused to each other. The dopant may be a 7H-benzo[c]fluorene having diarylamino substituents at the 5- and 9-positions. This scheme provides organic light-emitting devices having low driving voltages, high light-emitting efficiencies and long lifetimes. |
| US09865819B2 |
Nitrogen annulated perylene diimides for use as electron transport materials in organic electronic devices
PDI derivatives useful as opto-electronically active materials or for the synthesis of such materials. Certain compounds herein function as efficient electron acceptors and are useful as electron active components of electronic devices. |
| US09865814B2 |
Resistive memory cell having a single bottom electrode and two top electrodes
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region. |
| US09865812B2 |
Methods of forming conductive elements of semiconductor devices and of forming memory cells
Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed. |
| US09865810B2 |
Electronic device and method for fabricating the same
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer. |
| US09865808B2 |
Threshold switching device and electronic device including the same
A threshold switching device includes a first electrode layer, a second electrode layer, and an insulating layer interposed between the first and second electrode layers and including a plurality of neutral defects. The threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects. |
| US09865807B2 |
Packaging for an electronic device
In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component. |
| US09865805B2 |
Method for manufacturing magnetoresistive element
Provided is a method for manufacturing a magnetoresistive element, including a step of forming a tunnel barrier layer, wherein the step of forming the tunnel barrier layer includes a deposition step of depositing a metal film on top of a substrate, and an oxidation step of subjecting the metal film to an oxidation process. The oxidation step includes holding the substrate having Mg formed thereon, on a substrate holder in a processing container in which the oxidation process is performed, supplying an oxygen gas to the substrate by introducing the oxygen gas into the processing container, at a temperature at which Mg does not sublime, and heating the substrate after the introduction of the oxygen gas. |
| US09865803B2 |
Electronic device and method for fabricating the same
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a free layer comprising CoFeGeB alloy, and having a changeable magnetization direction that is perpendicular to the free layer; a tunnel barrier layer positioned over the free layer, and configured for enabling electron tunneling; a pinned layer positioned over the tunnel barrier layer, and having a pinned magnetization direction that is perpendicular to the pinned layer; and a bottom layer positioned under the free layer, and having a B2 structure to improve a perpendicular magnetic crystalline anisotropy of the free layer. |
| US09865801B1 |
Integrated circuits with magnetic tunnel junctions and methods for producing the same
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a fixed layer that includes a magnetic material overlying a substrate. A non-magnetic first tunnel barrier layer is formed overlying the fixed layer. A total free layer is formed overlying the first tunnel barrier layer, where the total free layer includes a first spacer layer between first and second free layers. The first free layer includes one or more of cobalt, iron, and boron. The first spacer layer is non-magnetic and includes a first spacer layer boron sink material that has a boride formation enthalpy lower than the boride formation enthalpy of cobalt. |
| US09865800B2 |
Magnetic memory devices
Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure. |
| US09865797B2 |
Resonant transducer, manufacturing method therefor, and multi-layer structure for resonant transducer
A resonant transducer includes a silicon single crystal substrate, a silicon single crystal resonator disposed over the silicon single crystal substrate, a shell made of silicon, surrounding the resonator with a gap, and forming a chamber together with the silicon single crystal substrate, an exciting module configured to excite the resonator, a vibration detecting module configured to detect vibration of the resonator, a first layer disposed over the chamber, the first layer having a through-hole over the resonator, a second layer disposed over the first layer, the second layer covering a gap being positioned above the through-hole and being communicated with the through-hole, and a third layer covering the first layer and the second layer, and the third layer sealing the gap. |
| US09865795B1 |
Process for fabrication of superconducting vias for electrical connection to groundplane in cryogenic detectors
Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via. |
| US09865791B2 |
Nanostructured copper-selenide with high thermoelectric figure-of-merit and process for the preparation thereof
Disclosed is a nanostructured p-type copper-selenide as a cost-effective thermoelectric material with a high thermoelectric figure-of-merit. The nanostructured copper-selenide is a cost-effective p-type thermoelectric material having a high figure-of-merit of 2 at 973 K and is synthesized employing high energy ball milling process followed by reaction sintering under pressure at high heating rates using spark plasma sintering of the resulting nanopowders. The sintered copper-selenide shows a density of 99.9% of theoretical density and retains the nanoscale features introduced during ball milling leading to a thermoelectric figure of merit of 2 at 973 K. |
| US09865788B2 |
Thermoelectric device, in particular thermoelectric generator or heat pump
A thermoelectric device may include a housing that may have a first housing element and a second housing element. The first housing element and the second housing element may each be composed of an electrically conductive material. At least two thermoelectric elements may be arranged between the first housing element and the second housing element. The at least two thermoelectric elements may be arranged at a distance from each other and may be electrically connected via at least one conductor bridge. A first electrical insulator may be arranged between the at least two thermoelectric elements and the first housing element. A second electrical insulator may be arranged between the at least two thermoelectric elements and the second housing element. |
| US09865786B2 |
Method of manufacturing structures of LEDs or solar cells
The disclosure relates to a manufacturing method comprising the formation of elemental LED or photovoltaic structures on a first substrate, each comprising at least one p-type layer, an active zone and an n-type layer, formation of a first planar metal layer on the elemental structures, provision of a transfer substrate comprising a second planar metal layer, assembly of the elemental structures with the transfer substrate by bonding of the first and second metal layers by molecular adhesion at room temperature, and removal of the first substrate. |
| US09865785B2 |
Optoelectronic component and method of production thereof
A method of producing an optoelectronic component includes providing a lead frame subdivided by a separating region into first and second lead frame parts, carrying out etching in which at least one trench structure is produced on the upper side of the first lead frame, producing a molded body by molding a molding material around the lead frame such that 1) a cavity is formed and exposes a region of the upper side of the first lead frame part and a region of the upper side of the second lead frame part, and 2) the trench structure is provided on the upper side of the exposed region of the first lead frame part, and arranging the optoelectronic semiconductor chip on the upper side of the exposed region of the first lead frame part such that the trench structure is used as an alignment mark. |
| US09865781B2 |
Method for manufacturing light emitting device comprising lens with tapered profile
A manufacturing method for a light emitting device can include providing a bonding layer over a base, and disposing a shim plate with an opening over the bonding layer. A light emitting body is disposed over the bonding layer exposed from the opening of the shim plate. A lens is formed by approaching a die having a concave portion at its surface, to the shim plate, covering an upper surface of the light emitting body and an upper surface of the shim plate with a lens formation material within the concave portion, and then hardening the lens formation material. |
| US09865779B2 |
Methods of manufacturing the package and light-emitting device
A method of manufacturing a package, the method comprising the steps of: preparing a resin compact having a recess, and including a pair of leads arranged at a bottom surface of the recess, a first resin body forming a lateral wall of the recess, and a second resin body arranged between the pair of leads; forming a reflective film entirely on at least the bottom surface of the recess and an inner surface of the lateral wall of the recess; and removing the reflective film formed on the pair of leads in the recess in the resin compact on which the reflective film has been formed. |
| US09865776B2 |
Method for separating regions of a semiconductor layer
The invention relates to a method for separating regions of a semiconductor layer and for introducing an outcoupling structure into an upper side of the semiconductor layer, the outcoupling structure being provided to couple light out of the semiconductor layer. The upper side of the semiconductor layer is covered by a mask having first openings for introducing the outcoupling structure and at least a second opening, which is provided to introduce a separating trench into the semiconductor layer. With the aid of an etching method, the outcoupling structure is introduced into the upper side of the semiconductor layer in the region of the first openings and simultaneously a separating trench passing through the semiconductor layer is introduced into the semiconductor layer via the second opening, and a region of the semiconductor layer is separated. |
| US09865775B2 |
Light emitting element
The light emitting element is provided to comprise: a first conductive type semiconductor layer; a mesa; a current blocking layer; a transparent electrode; a first electrode pad and a first electrode extension; a second electrode pad and a second electrode extension; and an insulation layer partially located on the lower portion of the first electrode, wherein the mesa includes at least one groove formed on a side thereof, the first conductive type semiconductor layer is partially exposed through the groove, the insulation layer includes an opening through which the exposed first conductive type semiconductor layer is at least partially exposed, the first electrode extension includes extension contact portions in contact with the first conductive type semiconductor layer through an opening, and the second electrode extension includes an end with a width different from the average width of the second electrode extension. |
| US09865768B2 |
Ultrafast light emitting diodes for optical wireless communications
In one aspect, there is provided an apparatus including a light emitting diode. The apparatus may include a plurality of layers including a substrate layer, a buffer layer disposed on the substrate layer, a charge transport layer, a light emission layer, another charge transport layer, and/or a metamaterial layer. The other charge transport layer may have at least one channel etched into the other charge transport layer leaving a residual thickness of the other charge transport layer between a bottom of the etched channel and the light emission layer. A metamaterial layer may be contained in the at least one channel that is proximate to the residual thickness of the charge transport layer. The metamaterial may include a structure including at least one of a dielectric or a metal. The metamaterial may cause the light emitting diode to operate at higher frequencies and with higher efficiency. |
| US09865767B2 |
Light emitting, photovoltaic or other electronic apparatus and system
The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of lenses suspended in a polymer deposited or attached over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes are substantially spherical, and have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap. |
| US09865761B1 |
Emitter-less, back-surface alternating-contact solar cell
The disclosure provides an emitter-less solar cell design featuring p-or-n type GaAs with alternating p-n junction regions on the back-surface of the cell, opposite incident solar irradiance. Various layers of p-or-n type GaAs are interfaced together to collect charge carriers, and a thin layer of AlGaAs is applied to the front and back surfaces to prevent recombination of charge carriers. In some embodiments, the layered and doped structure generally provides an AlGaAs window layer of about 20 nm doped to about 3×(1018) cm−3, a GaAs absorption layer of about 1200 nm doped to about 2×(1017) cm−3, an AlGaAs heterojunction layer of about 20 nm doped to about 3×(1018) cm−3, and a GaAs contact layer of about 20 nm doped to about 1×(1019) cm−3. Additionally, AlGaAs BSF-heterojunction layer and GaAs BSF-contact layers each have a depth of about 20 nm and are doped to about 3×(1018) cm−3 and 1×(1019) cm−3 respectively. The heterojunction layer, and contact layer are doped to a conductivity type opposite the absorption layer. |
| US09865759B2 |
Solar cell interconnection
A solar cell can include a conductive foil having a first portion with a first yield strength coupled to a semiconductor region of the solar cell. The solar cell can be interconnected with another solar cell via an interconnect structure that includes a second portion of the conductive foil, with the interconnect structure having a second yield strength greater than the first yield strength. |
| US09865756B2 |
Method for manufacturing a thin-layer photovoltaic device, in particular for solar glazing
A method for producing a thin-film photovoltaic device (1), comprising the following steps: providing a substrate (2); placing a photovoltaic film (3) on said substrate by stacking layers comprising at least a first conductive layer (4) forming a rear electrical contact, a second photoactive layer (5) that is absorbent in the solar spectrum and is made from an inorganic material, and a third layer (6) made from a transparent conductive material forming a front electrical contact; —dividing the photovoltaic film into a plurality of individual and interconnected photovoltaic cells (30), —forming a plurality of individual holes (31) passing at least through the first and second layers of photovoltaic film in each cell, by applying a mask (8) according to a printing method, in particular material-jet digital printing, flexography, screen printing, or pad printing, said mask having main areas defining a positive or negative stencil for said holes. The present invention is applicable in the field of solar glazing. |
| US09865752B2 |
Encapsulating material for solar cell and solar cell module
An encapsulating material for solar cell of the invention contains an ethylene/α-olefin copolymer, and a content of a fluorine element in the ethylene/α-olefin copolymer, which is determined using a combustion method and an ion chromatograph method, is equal to or less than 30 ppm. |
| US09865743B2 |
Semiconductor device including oxide layer surrounding oxide semiconductor layer
Oxygen is likely to be released or an oxygen vacancy is likely to occur during a manufacturing process particularly at a side surface of an oxide semiconductor layer. When an oxygen vacancy occurs at the side surface of the oxide semiconductor layer, a problem arises in that the resistance of the side surface is reduced, the apparent threshold voltage of a transistor varies, and variation in the threshold voltage is increased. Further, the variation in the threshold voltage may cause unintentional current to flow between a source and a drain, which might lead to an increase in the off-state current of the transistor and deterioration in the electric characteristics of the transistor. A semiconductor device in which a multilayer film including an oxide semiconductor layer and an oxide layer surrounding the oxide semiconductor layer is used for a channel formation region is provided. |
| US09865742B2 |
Semiconductor device
It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed. |
| US09865736B2 |
Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure. |
| US09865734B2 |
Semiconductor device and fabrication method thereof
A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. |
| US09865733B2 |
Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences. |
| US09865730B1 |
VTFET devices utilizing low temperature selective epitaxy
Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface. |
| US09865728B2 |
Switching device
A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided. |
| US09865727B2 |
Device architecture and method for improved packing of vertical field effect devices
A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill. |
| US09865726B2 |
Method of manufacturing a semiconductor device with trench gate by using a screen oxide layer
A screen oxide layer is formed on a main surface of a semiconductor layer and a passivation layer is formed on the screen oxide layer. A gate trench is formed in a portion of the semiconductor layer exposed by a mask opening in a trench mask that comprises the passivation layer. A gate dielectric is formed at least along sidewalls of the gate trench. After removing the passivation layer, dopants are implanted through the screen oxide layer to form at least one of a source zone and a body zone in the semiconductor layer. |
| US09865725B2 |
III-nitride transistor with trench gate
A transistor includes a stack of III-nitride semiconductor layers, the stack having a frontside and a backside, a source electrode in contact with the frontside of the stack, a drain electrode in contact with the backside of the stack, a trench extending through a portion of the stack, the trench having a sidewall, and a gate structure formed in the trench, including an AlN layer formed on the sidewall of the trench, an insulating cap layer formed on the AlN layer, and a gate electrode formed on the insulator cap layer and covering the sidewall of the trench. |
| US09865723B2 |
Switching device
A switching device includes first-third semiconductor layers, a gate insulating film, and a gate electrode. The first semiconductor layer is of a first conductivity type. The second semiconductor layer is of a second conductivity type and in contact with the first semiconductor layer. The third semiconductor layer is of the first conductivity type, in contact with the second semiconductor layer. The gate insulating film covers a surface of the second semiconductor layer in a range in which the second semiconductor layer separates the first semiconductor layer from the third semiconductor layer. The gate electrode faces the second semiconductor layer via the gate insulating film. The gate electrode includes a fourth semiconductor layer covering a surface of the gate insulating film; and a fifth semiconductor layer having a bandgap different from a bandgap of the fourth semiconductor layer and covering a surface of the fourth semiconductor layer. |
| US09865721B1 |
High electron mobility transistor (HEMT) device and method of making the same
A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer co-doped with silicon (Si) and germanium Ge and a method of making the same is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate. An n-type gallium nitride (GaN) layer is disposed on an interface surface of the epitaxial layers, wherein the n-type GaN layer is co-doped with silicon (Si) and germanium (Ge) that provide a carrier concentration of at least 1×1020 cm−3 and a root mean square (RMS) surface roughness that is no greater than 2 nm for a contact surface of the n-type GaN layer that is interfaced with the interface surface of the epitaxial layers. |
| US09865720B2 |
High electron-mobility transistor
A nitride semiconductor device is disclosed. The semiconductor device provides the GaN channel layer, the InAlN barrier layer on the GaN channel layer, and the n-type AlGaN layer on the InAlN barrier layer. The source and drain electrodes are formed on the n-type AlGaN layer, while, the gate electrode is formed directly on the InAlN barrier layer. The n-type AlGaN layer has the aluminum (Al) composition greater than 20% at the interface against the InAlN barrier layer, which is greater than the aluminum (Al) composition at the interface against the source electrode. |
| US09865719B2 |
Carbon doping semiconductor devices
A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×1018 cm−3 and the dislocation density in the III-N semiconductor layer is less than 2×109 cm−2. |
| US09865714B2 |
III-V lateral bipolar junction transistor
A lateral bipolar junction transistor (LBJT) device that includes an intrinsic III-V semiconductor material having a first band gap; and a base region present on the intrinsic III-V semiconductor material. The base region is composed of an III-V semiconductor material having a second band gap that is less than the first band gap. Emitter and collector regions present on opposing sides of the base region. The emitter and collector regions are composed of epitaxial III-V semiconductor material that is present on the intrinsic III-V semiconductor material. |
| US09865712B2 |
Semiconductor device and manufacturing method thereof
A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor. |
| US09865706B2 |
Integrated process and structure to form III-V channel for sub-7nm CMOS devices
Embodiments described herein generally relate to methods and structures for forming precise fins comprising Group III-V elements on a silicon substrate. A buffer layer is deposited in a trench formed in the dielectric material on a substrate. An isolation layer is then deposited over the buffer layer. A portion of the isolation layer is removed allowing for a precisely sized Group III-V channel layer to be deposited on the isolation layer. |
| US09865700B2 |
MOS P-N junction diode with enhanced response speed and manufacturing method thereof
A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed. |
| US09865699B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (2) is formed over a substrate (1), a graphene layer (3) is grown originating from the catalyst film (2), an electrode (4) in contact with the graphene layer (3) is formed, and the catalyst film (2) is removed. |
| US09865698B2 |
Semiconductor device blocking leakage current and method of forming the same
A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer. |
| US09865696B2 |
Sputtering target, method for manufacturing the same, and method for manufacturing semiconductor device
A deposition technique for forming an oxynitride film is provided. A highly reliable semiconductor element is manufactured with the use of the oxynitride film. The oxynitride film is formed with the use of a sputtering target including an oxynitride containing indium, gallium, and zinc, which is obtained by sintering a mixture of at least one of indium nitride, gallium nitride, and zinc nitride as a raw material and at least one of indium oxide, gallium oxide, and zinc oxide in a nitrogen atmosphere. In this manner, the oxynitride film can contain nitrogen at a necessary concentration. The oxynitride film can be used for a gate, a source electrode, a drain electrode, or the like of a transistor. |
| US09865695B2 |
High-voltage transistor architectures, processes of forming same, and systems containing same
An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device. |
| US09865690B2 |
Methods for fabricating a metal structure for a semiconductor device
A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature. |
| US09865689B2 |
Monolithic integrated semiconductor structure
A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition BxAlyGazNtPv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1 and v=0.9-1, C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1 and w=0-1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1−w and/or y=1−u−x−z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one. |
| US09865683B2 |
Electronic device having a transistor with increased contact area and method for fabricating the same
An electronic device includes a semiconductor memory unit that includes: a gate including at least a portion buried in a substrate; a junction portion formed in the substrate on both sides of the gate; and a memory element coupled with the junction portion on one side of the gate, wherein the junction portion includes: a recess having a bottom surface protruded in a pyramid shape; an impurity region formed in the substrate and under the recess; and a contact pad formed in the recess. |
| US09865678B2 |
High voltage field balance metal oxide field effect transistor (FBM)
A semiconductor device includes a semiconductor substrate and epitaxial layer of a first conductivity type with the epitaxial layer on a top surface of the substrate. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the epitaxial layer. A first conductivity type source region is inside the body region and a drain is at a bottom surface of the substrate. An inslated gate overlaps the source and body regions. First and second trenches in the epitaxial layer are lined with insulation material and filled with electrically conductive material. Second conductivity type buried regions are positioned below the trenches. Second conductivity type charge linking paths along one or more walls of the first trench electrically connect a first buried region to the body region. A second buried region is separated from the body region by portions of the expitaxial layer. |
| US09865677B2 |
Super junction semiconductor device
Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short. |
| US09865675B2 |
Making multilayer 3D capacitors using arrays of upstanding rods or ridges
In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires. |
| US09865672B2 |
Macro-image OLED lighting system
Techniques to fabricate and assemble a lighting system including multiple patterned OLED lighting panels to form a high-resolution macro image are provided. An image to be displayed is determined and divided into multiple portions. Patterned static OLED lighting panels that display each portion of the image are fabricated and assembled into a fixture to form a macro-image lighting system. The fixture may removably receive and hold individual panels, such that each panel may be replaced if any malfunction occurs. Each of the patterned OLED panels may be individually driven through an electrical connection within the fixture so as to be operated at substantially the same brightness and/or same chromaticity. |
| US09865670B2 |
Flexible display device and manufacturing method thereof
A flexible display device includes: a flexible substrate including a bending area; an insulating layer formed on the flexible substrate and including at least one cutout formed to correspond to the bending area; and a plurality of wires formed along a surface shape of the insulating layer in the bending area. The at least one cutout may include an inclined lateral wall, and a width of the inclined lateral wall may be equal to or greater than a depth of the cutout. |
| US09865667B2 |
Organic light-emitting diode display and manufacturing method thereof
An organic light-emitting diode (OLED) display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to provide a scan signal. An initialization voltage line has substantially the same pattern as the scan line and is insulated from the scan line. A data line crosses the scan line and is configured to provide a data voltage. A switching transistor is electrically connected to the scan line and the data line, and a driving transistor is electrically connected to the switching transistor and includes a driving gate electrode. A storage capacitor includes a first storage electrode and a second storage electrode overlapping the first storage electrode, wherein the first storage electrode and the driving gate electrode are integrally formed. |
| US09865665B2 |
Semiconductor device, input/output device, and electronic appliance
A flexible input/output device and an input/output device having high resistance to repeated bending are provided. The input/output device includes a first flexible substrate, a first insulating layer over the first substrate, a first transistor over the first insulating layer, a light-emitting element over and electrically connected to the first transistor and including an EL layer between first and second electrodes, a first bonding layer over the light-emitting element, a sensing element and a second transistor over the first bonding layer and electrically connected to each other, a second insulating layer over the sensing element and the second transistor, and a second flexible substrate over the second insulating layer. In the input/output device, B/A is greater than or equal to 0.7 and less than or equal to 1.7, where A is a thickness between the EL layer and the first insulating layer and B is a thickness between the EL layer and the second insulating layer. |
| US09865663B2 |
Organic light-emitting device
An organic light-emitting device including a substrate, first electrodes, first banks extending in a first direction, second banks extending in a second direction, organic functional layers each including an organic light-emitting layer, and a second electrode. The second banks include an organic fluorine compound, and have portions intersecting with and disposed above the first banks. Each of the first banks includes an organic bank layer including an organic material and an inorganic bank layer disposed on the organic bank layer. For each of the first banks, an uppermost surface thereof is a surface of the inorganic bank layer included therein. |
| US09865659B2 |
Light emitting device including tandem structure
A light emitting device comprising: a pair of electrodes; two or more light emitting elements disposed between the electrodes in a stacked arrangement, wherein a light emitting element comprises a layer comprising an emissive material; and a charge generation element disposed between adjacent light emitting elements in the stacked arrangement, the charge generation element comprising a first layer comprising an inorganic n-type semiconductor material, and a second layer comprising a hole injection material. A charge generation element is also disclosed. |
| US09865658B2 |
Organic light-emitting display apparatus
An organic light-emitting display apparatus includes an organic light-emitting display panel having a display area including a plurality of pixel areas and a non-display area adjacent the display area; and a light sensing unit. The organic light-emitting display panel includes a first substrate including an organic light-emitting device on a first base substrate and a second substrate including a black matrix between the plurality of pixel areas on a surface of a second base substrate facing the first substrate and a reflective pattern formed on the black matrix. The light sensing unit is at one side of the organic light-emitting display panel. |
| US09865656B2 |
Semiconductor memory device
A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells. The memory cell array comprises: a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction; a second conductive layer extending in the first direction; a variable resistance film provided at intersections of the plurality of first conductive layers and the second conductive layer; a first select transistor disposed closer to a side of the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the second conductive layer; a third conductive layer that extends in a third direction intersecting the second direction and is connected to a lower end of the second conductive layer via the first select transistor; and a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the second conductive layer. |
| US09865655B2 |
Memory cell structure with resistance-change material and method for forming the same
Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a memory cell structure formed over the substrate. In addition, the memory cell structure includes a first electrode layer formed over the substrate and a resistance-change material layer formed over the first electrode layer. The memory cell structure further includes a second electrode layer formed over the resistance-change material layer. In addition, the resistance-change material layer includes a semimetal or a semimetal alloy. |
| US09865648B2 |
Systems and methods for testing and packaging a superconducting chip
Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously. |
| US09865644B2 |
Image sensor
With an image sensor in which the amplifier circuit is disposed at each pixel, there is such an issue that the threshold voltage of the transistor fluctuates so that the signal voltage fluctuates because a voltage is continuously applied between the source and the gate of the transistor at all times when using the amorphous thin film semiconductor as the transistor that constitutes an amplifier circuit. The gate-source potential of the TFT that constitutes the amplifier circuit is controlled so that the gate terminal voltage becomes smaller than the source terminal voltage in an integrating period where the pixels accumulate the signals, and controlled so that the gate terminal voltage becomes larger than the source terminal voltage in a readout period where the pixels output the signals. |
| US09865643B2 |
Solid-state image sensor, imaging device, and electronic equipment
The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency.In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor. |
| US09865641B2 |
Solid-state imaging device, manufacturing method therefor, and imaging apparatus
A solid-state imaging device includes: a first chip including a pixel array in which a plurality of photoelectric conversion portions converting incident light into an electric signal are disposed; a second chip having an area in a plan view less than an area of the first chip in the plan view and electrically and physically connected to the first chip; and a support portion provided to cover an entire region which is not covered with the second chip in a surface of the first chip connected to the second chip and configured to support the first chip so that flatness of the first chip may be maintained. |
| US09865640B2 |
Backside illuminated (BSI) CMOS image sensor (CIS) with a resonant cavity and a method for manufacturing the BSI CIS
A backside illuminated semiconductor image sensor that includes a Fabry-Perot resonator tuned to absorb near infrared (NIR) radiation; wherein the Fabry-Perot resonator comprises a front reflector, a back reflector and an active Silicon layer between the front reflector and the back reflector. |
| US09865639B2 |
Semiconductor device and semiconductor-device manufacturing method
It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device. |
| US09865637B2 |
Photoelectric conversion device and manufacturing method of the photoelectric conversion device
A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member. |
| US09865635B2 |
Image sensor
An image sensor and a method of fabricating the same are disclosed. The image sensor may include a substrate including an active region defined by a device isolation layer, a photoelectric conversion layer, a well impurity layer, a floating diffusion region, and a transfer gate. When viewed in a plan view, a lower portion of the transfer gate may include a first surface in contact with the device isolation layer, a second surface substantially perpendicular to the first surface, and a third surface connected to the first and second surfaces. The third surface may face the floating diffusion region. A first portion of a gate insulating layer may be adjacent to the third surface and thinner than a portion adjacent to the first surface or the second surface, and this may facilitate more efficient transfer of an electron from the photoelectric conversion layer to the floating diffusion region. |
| US09865633B2 |
Solid-state imaging device and driving method therefor
A solid-state imaging device in which the potential of a signal line, which is obtained before a pixel has an operating period, is fixed to an intermediate potential between a first power-supply potential and a second power-supply potential. |
| US09865631B2 |
Solid-state image pickup apparatus
Provided is a back-illuminated solid-state image pickup apparatus having an improved color separation characteristic. A photo detector includes a first photo detector unit and a second photo detector unit disposed deeper than the first photo detector unit with respect to a back surface of a semiconductor substrate, wherein the first photo detector unit includes a first-conductivity-type first semiconductor region where carriers generated through photo-electric conversion are collected as signal carriers. A readout portion includes a first-conductivity-type second semiconductor region extending in a depth direction such that the carriers collected in the first semiconductor region are read out to a front surface of the semiconductor substrate. A unit that reduces the amount of light incident on the second semiconductor region is provided. |
| US09865629B2 |
Method of manufacturing array substrate, display substrate, and display device
A method of manufacturing an array substrate, a display substrate and a display device are disclosed. The method of manufacturing an array substrate comprises: forming a pattern of an active layer and a pattern of source and drain electrodes on a substrate; forming a pattern of a first transparent electrode and a pattern of a passivation layer through one single patterning process; and processing the substrate on which the pattern of the passivation layer having been formed, such that a material of the passivation layer fills at least partially in a gap in the pattern of the first transparent electrode. Through forming the pattern of the first transparent electrode and the passivation layer by one single patterning process, number of masks used in the manufacturing process of the array substrate is reduced. |
| US09865621B2 |
Display device
A display device includes: a pixel electrode; a switching element that is connected to the pixel electrode and charges the pixel electrode; a reference potential terminal set at a reference potential; and a resistive element that is connected to the pixel electrode and the reference potential terminal so as to be interposed therebetween, the resistive element forming a resistance component against electric charges moving between the pixel electrode and the reference potential terminal. |
| US09865619B2 |
Array substrate and manufacturing method thereof
An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer. |
| US09865618B2 |
Semiconductor memory device and method for manufacturing same
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers. |
| US09865617B2 |
Semiconductor device
A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations. |
| US09865614B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a stacked body and a columnar portion. The stacked body includes a plurality of electrode layers stacked with an insulator between the electrode layers. The columnar portion includes a semiconductor body extending in the stacked body in a stacking direction of the stacked body, and a charge storage film provided between the semiconductor body and the electrode layers. The columnar portion includes a first portion with a first diameter, and a second portion with a second diameter smaller than the first diameter. The first portion has a higher concentration of an impurity than a concentration of the impurity of the second portion. The impurity contains at least one of boron, arsenic, and phosphorus. |
| US09865612B2 |
Semiconductor memory device and method of manufacturing the same
A semiconductr memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion. |
| US09865610B2 |
Si recess method in HKMG replacement gate technology
The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar. |
| US09865607B1 |
Method of making a fully depleted semiconductor-on-insulator programmable cell and structure thereof
A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region. |
| US09865600B2 |
Printed capacitors
A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capacitor of the plurality of printed capacitors can be a horizontal or a vertical capacitor. Each printed capacitor can include a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors. |
| US09865594B2 |
Semiconductor devices
A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the wiring structures, a spacer on a sidewall of the protection pattern, and an insulating interlayer structure containing the wiring structures and having an air gap between the wiring structures. |
| US09865592B2 |
Method for FinFET integrated with capacitor
A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (STI) feature over the substrate. The STI feature includes first and second portions. A top surface of the first portion is lower than a top surface of the second portion. The semiconductor structure further comprises fin active regions; conductive features on the fin active regions and the STI feature; and dielectric features separating the conductive features from the fin active regions. The semiconductor structure further comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features. |
| US09865585B2 |
LED module and method of manufacturing the same
A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead, a first-pole third lead, a second-pole first lead, a second-pole second lead, a second-pole third lead, a first LED chip, a second LED chip, a third LED chip, and a housing. A distal end of the first-pole first lead is offset toward a second-pole side in a first direction with respect to both a distal end of the second-pole second lead and a distal end of the second-pole third lead. |
| US09865576B1 |
Solar cell hollow circuit and solar cell display device
A solar cell hollow circuit is provided. The solar cell hollow circuit includes a substrate, a first conductive layer, a photoelectric conversion layer and a second conductive layer. The first conductive layer is formed on the substrate. The photoelectric conversion layer is formed on the first conductive layer. The second conductive layer is formed on the photoelectric conversion layer. A hollow surround area is formed on the substrate by the first conductive layer, the photoelectric conversion layer and the second conductive layer. The hollow surround area defines an opening and a positive contact or a negative contact corresponding to the opening. |
| US09865574B2 |
Alignment in the packaging of integrated circuits
A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package. |
| US09865569B2 |
Planarity-tolerant reworkable interconnect with integrated testing
A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint. |
| US09865567B1 |
Heterogeneous integration of integrated circuit device and companion device
An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies; attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites; processing a backside and the top side of the interposer wafer; removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and attaching the second IC dies to the interposer wafer at the exposed second mounting sites. |
| US09865566B1 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of conductive members surrounded by the dielectric layer, a first conductive pillar disposed over and electrically connected with one of the plurality of conductive members, a second conductive pillar disposed over and electrically connected with one of the plurality of conductive member, a first die disposed over the RDL and electrically connected with the first conductive pillar, and a second die disposed over the RDL and electrically connected with the second conductive pillar, wherein a height of the second conductive pillar is substantially greater than a height of the first conductive pillar, and a thickness of the first die is substantially greater than a thickness of the second die. |
| US09865558B2 |
Semiconductor device connected by anisotropic conductive film
A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film having a differential scanning calorimeter onset temperature of 60° C. to 85° C., and a elastic modulus change of 30% or less, as calculated by Equation 1, below, Elastic modulus change(%)={(M1−M0)/M0}×100 [Equation 1] wherein M0 is an initial elastic modulus in kgf/cm2 of the anisotropic conductive film as measured at 25° C., and M1 is a elastic modulus in kgf/cm2 of the anisotropic conductive film as measured at 25° C. after the film is left at 25° C. for 170 hours. |
| US09865557B1 |
Reduction of solder interconnect stress
An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto. |
| US09865554B2 |
Integrated circuit packaging system with under bump metallization and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads. |
| US09865550B2 |
Pattern generator having stacked chips
A pattern generator includes and upper chip and one or more lower chips. The upper chip includes an upper substrate and a plurality of conductive plates on the upper substrate. The plurality of conductive plates is arranged as an array. The one or more lower chips include one or more lower substrates and a plurality of driving circuits each on one of the one or more lower substrates and electrically coupled with a corresponding one of the plurality of conductive plates. The upper chip and the one or more lower chips are stacked one over another. |
| US09865547B2 |
Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a second region. The second region has a resistance higher than a resistance of the first region. The second region includes a side surface of an end of the graphene layer. The device further includes a first plug being in contact with the first region. |
| US09865540B2 |
Vertical memory devices and methods of manufacturing the same
A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines. |
| US09865539B2 |
Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes forming an opening in the dielectric layer. A dielectric constant of a first portion of the dielectric layer is less than that of a second portion of the dielectric layer surrounding the opening. The method further includes forming a conductive feature in the opening. The second portion is between the first portion and the conductive feature. In addition, the method includes modifying an upper portion of the first portion to increase the dielectric constant of the upper portion of the first portion. The method also includes removing the upper portion of the first portion and the second portion. |
| US09865522B2 |
Composite heat sink structures
Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a main heat transfer surface to couple to, for instance, at least one electronic component to be cooled; a compressible, continuous sealing member; and a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base; and an in situ molded member. The in situ molded member is molded over and affixed to the thermally conductive base, and is molded over and secures in place the sealing member retainer. A coolant-carrying compartment resides between the thermally conductive base and the in situ molded member, and a coolant inlet and outlet are provided in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow through the compartment. |
| US09865519B2 |
Use of an external getter to reduce package pressure
A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer. |
| US09865515B2 |
Ion implantation methods and structures thereof
A semiconductor device fabricated using a high-temperature ion implantation process is provided. The high-temperature ion implantation process includes providing a substrate having a plurality of fins. A mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. A first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. An interstitial cluster is formed within the group of fins and within the test structure. Thereafter, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure. |
| US09865511B2 |
Formation of strained fins in a finFET device
In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material. |
| US09865510B2 |
Device and methods for high-K and metal gate slacks
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. |
| US09865506B2 |
Stack type semiconductor memory device
A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. The gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer. |
| US09865504B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer. |
| US09865501B2 |
Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer
Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. By exposing a metal oxide surface to a remote plasma, the metal oxide surface on a substrate can be reduced to pure metal and the metal reflowed. A remote plasma apparatus can treat the metal oxide surface as well as cool, load/unload, and move the substrate within a single standalone apparatus. The remote plasma apparatus includes a processing chamber and a controller configured to provide a substrate having a metal seed layer in a processing chamber, form a remote plasma of a reducing gas species where the remote plasma includes radicals, ions, and/or ultraviolet (UV) radiation from the reducing gas species, and expose a metal seed layer of the substrate to the remote plasma to reduce oxide of the metal seed layer to metal and to reflow the metal. |
| US09865499B2 |
Method and apparatus for gap fill using deposition and etch processes
A method for depositing a silicon-containing film is performed by causing a silicon-containing gas to adsorb on a first surface of a depression formed in a second surface of a substrate by supplying the silicon-containing gas to the substrate. A silicon component contained in the silicon-containing gas adsorbed on the first surface of the depression is partially etched by supplying an etching gas to the substrate. A silicon-containing film is deposited in the depression by supplying a reaction gas reactable with the silicon component to the substrate so as to produce a reaction product by causing the reaction gas to react with the silicon component left in the depression without being etched. |
| US09865495B2 |
Semiconductor device and method for fabricating the same
A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a substrate, removing the dummy mask pattern and etching the substrate using the real mask pattern as a mask to form a first trench, a second trench, and a fin-type pattern defined by the first trench and the second trench. The second trench contacting the fin-type pattern comprises a smooth pattern which is convex and positioned between a bottom surface and a side surface of the second trench, a first concave portion which is positioned between the side surface of the second trench and the smooth pattern, and a second concave portion which is positioned between the convex portion and the bottom surface of the second trench. |
| US09865491B2 |
Devices for methodologies related to wafer carriers
Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed. |
| US09865489B2 |
Substrate support chuck cooling for deposition chamber
A substrate support chuck for use in a substrate processing system is provided herein. In some embodiments, a substrate support for use in a substrate processing chamber may include an electrostatic chuck having a top substrate support surface and a bottom surface, and a cooling ring assembly having a central opening disposed proximate the bottom surface of the electrostatic chuck, the cooling ring assembly including, a cooling section having a top surface thermally coupled to the bottom surface of the electrostatic chuck, the cooling section having a cooling channel formed in a bottom surface of the cooling section, and a cap coupled to a bottom surface of the cooling section and fluidly sealing the cooling channel formed in the cooling section. |
| US09865488B2 |
Processing method and processing apparatus
A method of processing an object to by using a processing apparatus is provided. The apparatus includes a plurality of containers to contain the object, a plurality of process chambers to perform a desired process on the object, a temporary storage chamber to temporarily store the object, and a transfer device to transfer the object. The method includes a first step of transferring an unprocessed object from the containers to the process chambers, and a second step of transferring a processed object from the process chambers to the temporary storage chamber. The method further includes a third step of collecting the processed object into one of the containers starting a collection of the processed object from the temporary storage chamber depending on a timing of processing a last object of the one of the containers prior to collecting the processed object into the other containers from the temporary storage chamber. |
| US09865486B2 |
Timing/power risk optimized selective voltage binning using non-linear voltage slope
Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax. The chips are sorted into different process windows, based on the voltage identified. |
| US09865483B2 |
Substrate liquid processing method, substrate liquid processing apparatus, and recording medium
Disclosed is a substrate liquid processing method. The method includes: supplying a first processing liquid to a central portion of a substrate at a first flow rate by a first nozzle while rotating the substrate using a substrate holding unit; supplying a second processing liquid to a location between the central portion and an outer circumferential end of the substrate by a second nozzle while supplying the first processing liquid to the central portion of the substrate at the first flow rate; and changing the flow rate of the first processing liquid supplied from the first nozzle to a second flow rate lower than the first flow rate, so as to continue forming of the liquid film on the overall surface of the substrate while supplying the second processing liquid by the second nozzle to the substrate that is formed with a liquid film on the overall surface thereof. |
| US09865476B2 |
Method and apparatus for pulse electrochemical polishing
A method and apparatus for pulse electrochemical polishing a wafer are disclosed. The method comprises steps of: establishing a duty cycle table showing all points on the wafer, a removal thickness corresponding to every point and a duty cycle corresponding to the removal thickness; driving a wafer chuck holding and positioning the wafer to move at a preset speed so that a special point on the wafer is right above a nozzle ejecting charged electrolyte onto the wafer; looking up the duty cycle table and obtaining the removal thickness and the duty cycle corresponding to the special point; and applying a preset pulse power source to the wafer and the nozzle and the actual polishing power source for polishing the special point being equal to the duty cycle multiplying by the preset power source. |
| US09865474B2 |
Etching method using plasma, and method of fabricating semiconductor device including the etching method
An etching method using plasma includes generating plasma by supplying process gases to at least one remote plasma source (RPS) and applying power to the at least one RPS, and etching an etching object by supplying water (H2O) and the plasma to a process chamber. |
| US09865473B1 |
Methods of forming semiconductor devices using semi-bidirectional patterning and islands
Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first hardmask layer, a second hardmask layer, a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a set of islands; etching to define the set of islands, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks. |
| US09865469B2 |
Epitaxial lift-off process with guided etching
A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput. |
| US09865467B2 |
Recess filling method and processing apparatus
There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess. |
| US09865465B2 |
Nanocrystal thin film fabrication methods and apparatus
Nanocrystal thin film devices and methods for fabricating nanocrystal thin film devices are disclosed. The nanocrystal thin films are diffused with a dopant such as Indium, Potassium, Tin, etc. to reduce surface states. The thin film devices may be exposed to air during a portion of the fabrication. This enables fabrication of nanocrystal-based devices using a wider range of techniques such as photolithography and photolithographic patterning in an air environment. |
| US09865463B2 |
Method of manufacturing a semiconductor device
In a method of manufacturing a semiconductor device, a first photoresist layer is applied on a polycrystalline silicon layer formed on a semiconductor substrate. The first photoresist layer is then patterned and cured with UV rays. The polycrystalline silicon layer is etched, using the first photoresist layer as a mask, to form a gate electrode and a resistive film of the polycrystalline silicon layer. A second photoresist layer is applied on the cured first photoresist layer and patterned to form an opening portion exposing the first photoresist layer. Impurities are ion implanted through the opening portion in the polycrystalline silicon layer. The channeling of impurities implanted during the ion implantation is suppressed by the cured first photoresist layer. |
| US09865457B2 |
Nitride film forming method using nitrading active species
There is provided a method of forming a nitride film, including: repeating a cycle including an adsorption process of adsorbing a film forming precursor gas onto a substrate having a surface in which a fine recess is formed, the film forming precursor gas containing an element and chlorine constituting a nitride film to be formed; and a nitriding process of nitriding the adsorbed film forming precursor gas with nitriding active species, to form the nitride film in the fine recess. The nitriding process includes: generating NH* active species and N* active species as a nitriding active species; and controlling concentrations of the NH* active species and the N* active species to vary an area where the film forming precursor gas is adsorbed in the fine recess. |
| US09865446B2 |
Systems and methods for reducing the kinetic energy spread of ions radially ejected from a linear ion trap
A system for analyzing a sample includes a linear ion trap, an insert DC electrode, a voltage controller, and an RF control circuitry. The linear ion trap includes a first pair of trap electrodes and a second pair of trap electrodes spaced apart from each other and surrounding a trap interior. An electrode of the second pair of trap electrodes includes a trap exit. The insert DC electrode is positioned adjacent to the trap exit. The voltage controller applies a DC voltage to the insert DC electrode. The RF control circuitry applies a main RF voltage to the first pair of trap electrodes, applies a portion of the main RF to the second pair of trap electrodes, increases the main RF applied to the first pair of trap electrodes, and applies an auxiliary RF voltage to the second pair of trap electrodes. |
| US09865441B2 |
Mass spectrometer
The present disclosure provides a mass spectrometer for performing an analysis of sample ions, and a method for operating a mass spectrometer. The mass spectrometer comprises a first ion optical element that is supplied with a first gas; a mass analyzer, wherein the performance of the mass analyzer is dependent on the pressure of the first gas in the first ion optical element; and a controller for setting a property of the first gas, which comprises at least the pressure of the first gas, on the basis of a characteristic of the analysis to be performed by the mass spectrometer. |
| US09865439B2 |
Plasma processing apparatus
A processing apparatus and a processing method for a semiconductor wafer, which allow stable end point detection, are provided. In the plasma processing apparatus or method in which a processing-target film layer of a film structure including a plurality of film layers formed in advance on a surface of a wafer mounted on a sample stage deployed within a processing chamber inside a vacuum vessel, by using plasma formed with the processing chamber, intensities of lights of a plurality of wavelengths are detected using data composed of results of reception of lights during a plurality of different time-intervals by an optical receiver which receives lights of the plurality of wavelengths from an inside of the processing chamber while processing is going. |
| US09865438B2 |
Method and apparatus for calibrating optical path degradation useful for decoupled plasma nitridation chambers
Methods for matching semiconductor processing chambers using a calibrated spectrometer are disclosed. In one embodiment, plasma attributes are measured for a process in a reference chamber and a process in an aged chamber. Using a calibrated light source, an optical path equivalent to an optical path in a reference chamber and an optical path in an aged chamber can be compared by determining a correction factor. The correction factor is applied to adjust a measured intensity of plasma radiation through the optical path in the aged chamber. Comparing a measured intensity of plasma radiation in the reference chamber and the adjusted measured intensity in the aged chamber provide an indication of changed chamber conditions. A magnitude of change between the two intensities can be used to adjust the process parameters to yield a processed substrate from the aged chamber which matches that of the reference chamber. |
| US09865436B1 |
Powered anode for ion source for DLC and reactive processes
The present invention provides a charged particle source comprising a plasma processing chamber that has a plasma source, a gas supply and an ion extraction grid that are each operatively connected to the processing chamber. A conducting plate is located adjacent to a wall of the plasma source. The conducting plate has a surface with a plurality of grooves that face the wall of the plasma source. A substrate support is disposed within an interior portion of the processing chamber for supporting a substrate. |
| US09865431B2 |
Apparatus and method for tuning a plasma profile using a tuning electrode in a processing chamber
Embodiments of the present invention relate to apparatus for enhancing deposition rate and improving a plasma profile during plasma processing of a substrate. According to embodiments, the apparatus includes a tuning electrode disposed in a substrate support pedestal and electrically coupled to a variable capacitor. The capacitance is controlled to control the RF and resulting plasma coupling to the tuning electrode. The plasma profile and the resulting deposition rate and deposited film thickness across the substrate are correspondingly controlled by adjusting the capacitance and impedance at the tuning electrode. |
| US09865423B2 |
X-ray tube cathode with shaped emitter
An emitter for a cathode of an X-ray tube is provided that includes a shaped emitting surface. The emitting surface is shaped in a suitable process in order to enable the emitting surface to focus electron beams emitted from the emitting surface on a focal spot on a target of less than 1.0 mm without the need for any additional focusing elements in the X-ray tube. |
| US09865419B2 |
Pressure-controlled electrical relay device
An electrical relay device includes a housing, a wire coil, an actuator assembly, and a shell. The housing extends between a closed end and an open end and defines a chamber. The wire coil and the actuator assembly are within the chamber. The actuator assembly is configured to move between a first position, in which a movable contact is spaced apart from at least one stationary contact, and a second position, in which the movable contact engages the at least one stationary contact, based on a magnetic field induced by current through the wire coil. The shell seals the open end of the housing to seal the chamber. The shell has a pressure relief valve in flow communication with the chamber. The pressure relief valve is configured to open in response to a pressure within the chamber exceeding a threshold set pressure to reduce the pressure within the chamber. |
| US09865415B2 |
Two piece handle for miniature circuit breakers
A miniature circuit breaker 10 having a handle assembly 100 formed of two separate pieces, namely a handle section 110 and a link section 150 with a first end 152 and a second end 154. The link section 150 is pivotally connected at the first end 152 to the handle section 110, and at the second end 154 to a movable blade 30 carrying the movable contact 32 of the circuit breaker. The handle section 110 can be formed of a plastic, and the link section 150 can be formed of a metallic material. A metallic link section can be thinner than an equivalent plastic part, and can provide a robust metal-to-metal interface with the blade 30 carrying the movable contact 32. The handle assembly 100 can also have one or more clearance gaps 132 and 134 designed between the handle section 110 and link section 150 to provide for a range of independent motion by the handle section 110 in relation to the link section 150. |
| US09865414B2 |
Limit switch
A limit switch is provided that is returned to an original position even if a turning angle of a turning lever becomes 90 degrees. In a section perpendicular to a turning shaft, a cam is formed such that a whole contact surface of the cam with a cam receiver is located on a side of the cam receiver with respect to a shaft center of the turning shaft when the external force does not act on the turning lever. |
| US09865413B2 |
Vehicle control device
In a switching control device of a vehicle control device, when a vehicle is in a non-traveling condition, an operating method for a pressing operation, which is carried out with respect to a push switch in relation to a switching control for switching an operating state of a drive source of the vehicle or a power supply state to a vehicle mounted device of the vehicle, in a case that the operating state of the drive source of the vehicle or the power supply state to the vehicle mounted device of the vehicle is switched from off to on, differs from an operating method for a pressing operation in a case that the operating state or the power supply state is switched from on to off. |
| US09865408B2 |
Switch extension device and mounting assembly
A switch extension device comprises an elongate extension member and an actuation member. The elongate extension member has a distal end shaped to couple with an electrical switch and a proximal end for positioning remote from the electrical switch. The actuation member is coupleable to the proximal end of the elongate extension member. The actuation member is movable to move the extension member to actuate the electrical switch. Methods of operation are also described. |
| US09865407B2 |
Interlock apparatus of ring main unit
An interlock apparatus of a ring main unit is provided. The interlock apparatus of the ring main unit may change a rotational motion of the shaft included in the circuit breaker to a rectilinear motion, and thus, the insertion hole may be opened or closed according to a closed or cutoff state of the circuit breaker. Accordingly, in the closed state of the circuit breaker, the control of a state of the disconnector is prevented. |
| US09865404B2 |
High-performance supercapacitors based on metal nanowire yarns
An energy-storage device is formed from a first and a second yarn, each yarn including a plurality of nanowires including aluminum and/or a transition metal. An anode pad is in contact with the first yarn and a cathode pad is in contact with the second yarn. Alternatively, first and second metallic electrodes may be disposed substantially in parallel, with pluralities of nanowires including aluminum and/or a transition metal extending therefrom. In another embodiment, a supercapacitor may include a niobium yarn including a plurality of niobium nanowires. Each niobium nanowire may include at least (i) a first section comprising at least one of unoxidized niobium and niobium oxide; (ii) a second section comprises a niobium pentoxide layer; and (iii) a third section comprises a layer formed by coating the niobium nanowire in at least one of a conductive polymer and a liquid metal. |
| US09865399B2 |
Electronic component having multilayer structure and method of manufacturing the same
An electronic component of a multi-layered structure includes a laminate formed by stacking a plurality of ceramic bodies and an external electrode made of a conductive resin for connecting each ceramic body. |
| US09865394B2 |
Electrical component comprising a connection element having a plastic body
An electrical component is disclosed. In an embodiment the component includes a component body and at least one connection element having a plastic body, wherein the at least one connection element is connected to the component body via a metal layer. |
| US09865393B2 |
Metallized film capacitor element comprising thermally conductive films and a thermally conducting film for an electrical power component
A metallized film capacitor element includes a plurality of concentrically arranged cylindrical sub-elements, each sub-element including at least one metal coated dielectric film wound in a plurality of turns. The capacitor element further includes one or more thermally conductive sections provided between the sub-elements. Each of the thermally conductive sections includes a sheet wound at least one turn and having a higher thermal conductivity than the metal coated dielectric film of the sub-elements. A thermally conducting film is provided for improving the thermal conductivity of electrical power components. The thermally conducting film includes an electrically insulating film and thermally conductive and electrically insulating particles disposed on at least one side of the film. |
| US09865391B2 |
Wireless power repeater and method thereof
A wireless power repeater for relaying power transmission between a wireless power transmitter and a wireless power receiver according to the embodiment includes a position detector for detecting a position of the wireless power receiver, a repeater resonator unit including a plurality of repeater resonators, and a controller for operating a specific repeater resonator, which is located closest to an extension line of the wireless power transmitter and the wireless power receiver, based on position information detected by the position detector. |
| US09865390B2 |
Coil component and power supply apparatus including the same
A coil component includes a first coil part including a multilayer substrate on which a conductor pattern is formed, a second coil part formed as a wire and stacked together with the first coil part, a core coupled to the first and second coil parts while penetrating through the first and second coil parts to thereby be electromagnetically coupled to the first and second coil parts, and a pressing member interposed between the core and the second coil part to allow the first and second coil parts to closely adhere to each other. |
| US09865381B2 |
Chip with protection function and method for producing same
A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti. |
| US09865380B2 |
Material comprising reduced graphene oxide, a device comprising the material and a method of producing the material
The present invention relates to a material comprising reduced graphene oxide, wherein the degree of reduction of the graphene oxide exhibits a spatial variation so that the material exhibits a gradient in the electric conductivity and/or permittivity. The material can for example be used in an electric device for purposes of field grading and/or dissipation of charges. Examples of electric devices wherein the material is beneficial includes cable accessories, bushings, power cables, microelectronics, switchgear, etc. The invention further relates to a method of producing a material for electrical applications. The method comprises treating different parts of a graphene oxide element differently, so as to achieve a different degree of reduction of the graphene oxide within the element, resulting in a sample having a gradient in the electrical conductivity and/or permittivity. The material could for example be obtained by means of applying a thermal gradient to a graphene oxide element, or by irradiation of a graphene oxide element. |
| US09865379B2 |
Thermal sleeve with self-adjusting positioning member, assembly therewith and method protecting a temperature sensitive member therewith
A thermal sleeve and method for protecting a temperature sensitive electronic member against exposure to heat. The thermal sleeve includes a tubular wall with an inner surface bounding an inner cavity extending along a central longitudinal axis between open opposite ends and a reflective outer surface. The thermal sleeve includes a positioning member constructed of a separate piece of material from the tubular wall, with an annular portion attached to the tubular wall and at least one resilient finger extending radially inwardly from the annular portion. The at least one finger extends radially inwardly along a plane from the fixed end along an arcuate path to a free end configured for abutment with a wiring harness attached to the temperature sensitive electronic member. The free end of the finger is radially expandable along the plane toward the annular portion to automatically adjust to an outer envelop of said wiring harness. |
| US09865375B2 |
Shielded electric wire and wire harness
A shielded electric wire includes electric wires, a shielding member that covers peripheries of the electric wires, a viscoelastic body that covers the peripheries of the electric wires, a sheet member having first and second sheet member covering peripheries of the shielding member and the viscoelastic body, and a protecting member provided around the sheet member. The first and second sheet members are pasted onto the shielding member and the viscoelastic body so that a pasted portion protruding in a width direction is formed. A force of adhesion of the viscoelastic body to the plurality of electric wires and the adhesive layers of the first and second sheet member is not less than 0.59 N/10 mm. A force of adhesion of the adhesive layers of the first and second sheet members to the viscoelastic body is not less than 0.59 N/10 mm. |
| US09865369B2 |
Graphene-based material
The present invention relates to a transparent chemically functionalized graphene with high electrical conductivity and which is stable in air. It also relates to a method of manufacturing a conductive and transparent graphene-based material. |
| US09865368B1 |
Production of radiopharmaceuticals
A computer-implemented method for determining optimized amount of radiopharmaceutical to be produced at a production facility, the radiopharmaceutical being for use in nuclear imaging at customer sites, in order to meet aggregate demands of orders placed by the customer sites (e.g. medical imaging centers, hospitals, etc.), wherein the quantity of radiopharmaceutical is sufficient to meet the aggregate demand while minimizing any overproduction of the radiopharmaceutical. |
| US09865366B2 |
Shielded packaging system for radioactive waste
A packaging system for radioactive waste is robust, highly functional, and can be used for nearly all radioactive waste streams that require shielded packaging. The packaging system includes a modular container that is configured to receive modular shielding inserts. The packaging system can be used to store, transport, and dispose of radioactive waste. |
| US09865364B2 |
CRDM with separate SCRAM latch engagement and locking
A control rod drive mechanism (CRDM) configured to latch onto the lifting rod of a control rod assembly and including separate latch engagement and latch holding mechanisms. A CRDM configured to latch onto the lifting rod of a control rod assembly and including a four-bar linkage closing the latch, wherein the four-bar linkage biases the latch closed under force of gravity. |
| US09865361B2 |
Diagnostics for a memory device
A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics. |
| US09865359B2 |
Semiconductor device including fuse circuit
Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively. |
| US09865358B2 |
Flash memory device and erase method thereof capable of reducing power consumption
Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells. |
| US09865356B2 |
Circuit and method for reading a memory cell of a non-volatile memory device
A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal. |
| US09865352B2 |
Program sequencing
Apparatuses, systems, methods, and computer program products are disclosed for program sequencing. An apparatus includes a block of non-volatile storage cells having a plurality of word lines. The word lines are organized into a monotonically increasing sequence. The apparatus includes a controller for the block. The controller is configured to program a set of storage cells of a word line to one or more storage states above a predetermined threshold and to program a set of storage cells of a previous word line adjacent to and before the word line in the sequence, to one or more storage states below the predetermined threshold after programming the set or storage cells of the word line to the one or more storage states above the predetermined threshold. |
| US09865349B2 |
Memory cell
Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh. |
| US09865347B2 |
Memory driving circuit
A memory driving circuit is disclosed herein. The memory driving circuit includes a programmable current source, a reference voltage generation unit and a voltage comparator unit, The programmable current source generates a second current according to a first current. The second current flows into a memory cell, and produces a device voltage at the input of the memory cell. The reference voltage generation unit generates a crystal voltage. The voltage comparator unit compares the device voltage with the crystal voltage and sends out a control signal to control the programmable current source. The first current and the second current are adjusted by the control signal so that the shape of the current pulse of SET operation to the memory cell is well controlled. |
| US09865346B1 |
Phase change memory device and method of operation
A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal. |
| US09865342B2 |
Semiconductor memory devices having separate sensing circuits and related sensing methods
A sensing circuit of a semiconductor memory device is provided which includes a bit line having a first edge and a second edge, a sensing line, a current supply unit, and a sense amplifier. A plurality of memory cells is connected between the first edge and the second edge. The sensing line is connected to the second edge of the bit line, and the current supply unit supplies a sensing current via the first edge of the bit line. The sense amplifier senses data stored at a selected memory cell by comparing a sensing voltage of the sensing line with a reference voltage when the sensing current flows to the selected memory cell from the first edge of the bit line. |
| US09865341B2 |
Electronic device
An electronic device includes a semiconductor memory unit, which includes resistive memory cells; an access circuit to apply, during a write operation, a write voltage across a selected one of the resistive memory cells in a first or second direction; first switching units, each of which is disposed between the access circuit and a first end of a corresponding one of the resistive memory cells and turned on in response to a first voltage having a level higher than a predetermined level when the corresponding resistive memory cell is selected during the write operation; and second switching units, each of which is disposed between the access circuit and a second end of the corresponding resistive memory cell and turned on in response to a second voltage having a level equal to or lower than the predetermined level when the corresponding resistive memory cell is selected during the write operation. |
| US09865339B2 |
Memory devices with reduced operational energy in phase change material and methods of operation
Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material. |
| US09865337B1 |
Write data path to reduce charge leakage of negative boost
A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor. |
| US09865334B2 |
Efficient bitline driven one-sided power collapse write-assist design for SRAMs
A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell. |
| US09865329B2 |
Memory system topologies including a buffer device and an integrated circuit memory device
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. |
| US09865327B1 |
Semiconductor memory apparatus
A semiconductor memory apparatus performs a selection in a normal readout/write-in mode and an automatic refreshing mode and includes a sense amplifier reading out data from a memory device, a first switching device connecting a first power supply voltage acting as an overdrive voltage to a first power supply intermediate node during a first period and then connecting a second power supply voltage acting as an array voltage to the first power supply intermediate node, a second switching device connecting the fourth power supply voltage to a second power supply intermediate node of the sense amplifier when the sense amplifier is driven, a first capacitor connected to the overdrive voltage and charging it, a third switching device switched on in the automatic refreshing mode, and a voltage generator generating a third power supply voltage and applying it and the first power supply voltage in parallel through the third switching device. |
| US09865326B2 |
Row hammer refresh command
A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row. |
| US09865323B1 |
Memory device including volatile memory, nonvolatile memory and controller
According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command. |
| US09865320B2 |
Electronic device
This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include free layer having a variable magnetization direction; a tunnel barrier layer formed over the free layer; a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; an exchange coupling layer formed over the pinned layer; and a magnetic correction layer formed over the exchange coupling layer, wherein the magnetic correction layer comprises a first magnetic layer, a spacer layer and a second magnetic layer that are sequentially stacked, and the first magnetic layer has a saturation magnetization smaller than a saturation magnetization of the second magnetic layer. |
| US09865314B2 |
Operation instruction generating circuit and consumable chip
An operation instruction generating circuit and a consumable chip. The operation instruction generating circuit includes: a power-on initialization module, connected to a signal wire and used for generating an initialization signal according to a signal transmitted by the signal wire; a middle signal generating module, connected to the power-on initialization module and the signal wire and used for combining, according to the initialization signal, the signal transmitted by the signal wire to generate a middle signal; and an instruction generating module, connected to the power-on initialization module and the middle signal generating module and used for generating an operation instruction according to the initialization signal and the middle signal or according to the initialization signal, the middle signal, and the signal transmitted by the signal wire. By the operation instruction generating circuit, the consumable chip is enabled to accurately respond to actions of a printing imaging device in time. |
| US09865312B2 |
Semiconductor device and semiconductor memory device
A semiconductor device includes an output driver having a variable current driving ability, for outputting an amplified data signal to the outside through a transmission line; a nonvolatile memory having a specific area for storing output adjustment data to adjust the current driving ability of the output driver; an output adjustment data readout unit for reading out the output adjustment data from the specific area of the memory in response to powering on; and a current driving ability adjustment unit for adjusting the current driving ability of the output driver on the basis of the output adjustment data read out from the memory. |
| US09865309B2 |
Dual diffusion path filtering
An apparatus and associated method for enclosing an environment-sensitive component. An enclosure separates an interior environment inside the enclosure from an external environment outside the enclosure. The enclosure has an environmental control system that captures a contaminant from the internal environment to a filter via a first diffusion path, and captures the contaminant from the external environment to the same filter via a different second diffusion path, the diffusion paths providing substantially different flow resistances to fluids carrying the contaminants to the filter via the respective diffusion paths. |
| US09865308B2 |
Provision of video data
Individual time stamp data inputs generated by different viewers of a broadcast or other video output are used to identify parts of the video data to be used to generate a sequence of video clips or “highlights”. The individual time stamps for each event are aggregated to generate a single marker flag (93) for each event, defined for example as the median (95) (or some other point) in the distribution (90) of time stamps. |
| US09865306B2 |
System to distinguish between visually identical objects
A method to include an identifier as metadata associated with a captured image is provided. The method may include receiving, by a device, an image and a unique identifier associated with the image, wherein the received image is a frame associated with a video stream. The method may also include storing the unique identifier as metadata associated with the received image, whereby the metadata is linked to a specific frame in the video stream according to a plurality of parameters, and whereby the unique identifier is received from a unique ID reader which reads a tag attached to an object included in the image. |
| US09865294B2 |
Servo integrated BPM template
Provided herein is a method including forming a data zone guiding pattern and forming a servo zone guiding pattern. A servo pattern and a data pattern are simultaneously formed. Directed self-assembly of block copolymers is guided by the data zone guiding pattern and the servo zone guiding pattern. |
| US09865293B2 |
Magnetic-disk substrate having a small waviness, for use as a magnetic disk, and a magnetic-disk drive device for use with the magnetic disk
When waviness having a wavelength component of 10 to 500 μm in the circumferential direction of a main surface of a disk-shaped substrate is acquired and slopes are acquired from the waviness at an interval of 50 to 100 μm, the substrate being used in a magnetic disk on which recording or reading is performed using a DFH head, an average value of absolute values of the slopes is 0.45×10−4 or less. This magnetic-disk substrate is used in a magnetic disk and a magnetic-disk drive device. |
| US09865286B2 |
Tape array electrical lapping guide design for small stripe TMR sensor
A magnetic tape recording module having electrical lapping guides located within and adjacent to an array of magnetic read/write elements. Electrical leads connected with the electrical lapping guides are buried deep within the head build, close to the substrate so that they can pass beneath the electrical leads of the read/write elements without any capacitive coupling between the electrical lapping guide leads and the read/write element leads. The presence of the electrical lapping guides within and adjacent to the read/write element leads provides much more accurate control of read/write element stripe height during lapping. |
| US09865285B2 |
Wiring thin plate with a wiring part and a protrusion having the same height, flexure as the wiring thin plate and method of welding of the wiring thin plate
Provided is a wiring thin plate capable of securely hold-down the wiring thin plate around a scheduled portion to be a welded spot even if the wiring thin plate is downsized and involves widened wiring traces. The wiring thin plate includes a metal supporting layer, an insulating layer on the supporting layer, a wiring part having a plurality of wiring traces on the insulating layer, a scheduled portion defined on the supporting layer to be welded, and a protrusion formed on the supporting layer for the scheduled portion and having a height that is the same as a height of the wiring part. |
| US09865284B2 |
Fabrication process for slider with extended three-dimensional air-bearing surface
Disclosed herein are processes to manufacture sliders having extended three-dimensional air-bearing surfaces and non-transitory computer-readable storage media storing machine-executable instructions to cause at least one processor to perform the processes. A disclosed method of manufacturing a slider for use in a hard disk drive comprises removing a first portion of material from a wafer, the first portion of material comprising substrate, and, using an additive fabrication technique, forming at least a portion of a feature of the slider in a first location formerly occupied by at least some of the first portion of material. The additive fabrication technique may comprise three-dimensional printing, stereo lithography, fused deposition modeling, selective laser sintering, or multi jet modeling. Also disclosed are sliders manufactured using the disclosed methods of manufacture and disk drives comprising such sliders. |
| US09865279B2 |
Method and electronic device
According to one embodiment, a method performed by an electronic device includes: receiving an audio signal comprising voice and background sound via a microphone; receiving a user's operation to set a loudness of the voice or the background sound; setting a balance between a first gain of the voice and a second gain of the background sound according to the user's operation; separating the input audio signal into a first signal of the voice and a second signal of the background sound; amplifying the first signal according to the first gain; amplifying the second signal according to the second gain; and outputting the first signal and the second signal at least partially overlapping each other via a speaker. |
| US09865276B2 |
Voice processing method and apparatus, and recording medium therefor
A processing unit of a voice processing apparatus first generates a target voice signal in a time domain by adjusting a fundamental frequency of a target voice signal to a fundamental frequency of an initial voice signal, so as to generate a spectrum of the target voice signal after pitch is adjusted. Second, the processing unit reallocates, along a frequency axis, the spectrum of the target voice characteristics by having the spectrum correspond to each of the fundamental frequencies of the initial voice signal. The processing unit then generates a converted spectrum by adjusting component values of the spectrum of the target voice characteristics, which spectrum has been reallocated, so as to correspond to the component values of the spectrum of the initial voice signal, and by adapting the component values of the spectrum of the initial voice signal to specific frequency bands of the spectrum of the target voice characteristics, with each specific frequency band including one of the harmonic frequencies corresponding to the fundamental frequency of the initial voice signal. |
| US09865274B1 |
Ambisonic audio signal processing for bidirectional real-time communication
An input ambisonic audio signal includes multiple channels, each of which is made up of audio data representing sound captured by an ambisonic microphone. A remote audio signal made up of audio data representing sound captured by remote meeting equipment is output by a local loudspeaker. Acoustic echo cancellation is performed on the input ambisonic audio signal by removing the remote audio signal from the input ambisonic audio signal. The acoustic echo cancellation may be performed on ambisonic A-format or B-format encoded audio data, or on an output encoding generated from the B-format encoded audio data. Comfort noise may be generated based on spectral and spatial characteristics of noise in the input audio data, for insertion into the input signal during acoustic echo cancellation. Automatic gain control may be performed across the multiple channels of the input audio signal. |
| US09865270B2 |
Audio encoding and decoding
An audio encoder comprises a multi-channel receiver which receives an M-channel audio signal where M>2. A down-mix processor down-mixes the M-channel audio signal to a first stereo signal and associated parametric data and a spatial processor modifies the first stereo signal to generate a second stereo signal in response to the associated parametric data and spatial parameter data for a binaural perceptual transfer function, such as a Head Related Transfer Function (HRTF). The second stereo signal is a binaural signal and may specifically be a (3D) virtual spatial signal. An output data stream comprising the encoded data and the associated parametric data is generated by an encode processor and an output processor. The HRTF processing may allow the generation of a (3D) virtual spatial signal by conventional stereo decoders. A multi-channel decoder may reverse the process of the spatial processor to generate an improved quality multi-channel signal. |
| US09865268B1 |
User authentication for voice-input devices
Techniques for authenticating users at devices that interact with the users via voice input. For instance, the described techniques may allow a voice-input device to safely verify the identity of a user by engaging in a back-and-forth conversation. The device or another device coupled thereto may then verify the accuracy of the responses from the user during the conversation, as well as compare an audio signature associated with the user's responses to a pre-stored audio signature associated with the user. By utilizing multiple checks, the described techniques are able to accurately and safely authenticate the user based solely on an audible conversation between the user and the voice-input device. |
| US09865265B2 |
Multi-microphone speech recognition systems and related techniques
A speech recognition system for resolving impaired utterances can have a speech recognition engine configured to receive a plurality of representations of an utterance and concurrently to determine a plurality of highest-likelihood transcription candidates corresponding to each respective representation of the utterance. The recognition system can also have a selector configured to determine a most-likely accurate transcription from among the transcription candidates. As but one example, the plurality of representations of the utterance can be acquired by a microphone array, and beamforming techniques can generate independent streams of the utterance across various look directions using output from the microphone array. |
| US09865264B2 |
Selective speech recognition for chat and digital personal assistant systems
Disclosed are computer-implemented methods and systems for dynamic selection of speech recognition systems for the use in Chat Information Systems (CIS) based on multiple criteria and context of human-machine interaction. Specifically, once a first user audio input is received, it is analyzed so as to locate specific triggers, determine the context of the interaction or predict the subsequent user audio inputs. Based on at least one of these criteria, one of a free-diction recognizer, pattern-based recognizer, address book based recognizer or dynamically created recognizer is selected for recognizing the subsequent user audio input. The methods described herein increase the accuracy of automatic recognition of user voice commands, thereby enhancing overall user experience of using CIS, chat agents and similar digital personal assistant systems. |
| US09865261B2 |
Webpage navigation utilizing audio commands
As provided herein, an audio signal (e.g., a user's spoken statement “check email”) may be received from the user of a client device accessing a webpage (e.g., a webmail webpage) utilizing a browser. The webpage may be parsed, analyzed, and/or mapped to identify one or more elements on the webpage (e.g., a send/receive email user interface element). The audio signal may be evaluated relative to the one or more elements on the webpage (e.g., such as by a dictionary comprising one or more audio signals paired to one or more audio commands) to identify an audio command. The audio command may be transformed into a text command (e.g., a script corresponding to a script action that invokes the send/receive email user interface element). The text command may be utilized to invoke an event (e.g., send/receive email) corresponding to an element on the webpage. |
| US09865259B1 |
Speech-responsive portable speaker
An electronic device may operate in different modes of operations. In a first mode of operation, the electronic device may receive user speech via a microphone, generate an audio signal that represents the user speech, and then send the audio signal to one or more remote computing device for analysis. In a second mode of operation, the electronic device may receive audio data from a peripheral device and then output audible content represented by the audio data. In some instances, the electronic device may operate in the first mode of operation and/or the second mode of operation based on whether the electronic device can communicate with the one or more computing devices over a wide-area network. |
| US09865256B2 |
System and method for calibrating a speech recognition system to an operating environment
A voice controlled medical system with improved speech recognition includes a microphone in an operating environment and a medical device. The voice controlled medical system further includes a controller in communication with the microphone and the medical device that operates the medical device by executing audio commands received by the microphone. The voice controlled medical system further includes a calibration signal indicative of distortion in the operating environment which is generated by comparing an audio signal played in the operating environment with a sound signal received by the microphone. The controller uses the calibration signal to interpret audio commands received by the microphone. |
| US09865251B2 |
Text-to-speech method and multi-lingual speech synthesizer using the method
A text-to-speech method and a multi-lingual speech synthesizer using the method are disclosed. The multi-lingual speech synthesizer and the method executed by a processor are applied for processing a multi-lingual text message in a mixture of a first language and a second language into a multi-lingual voice message. The multi-lingual speech synthesizer comprises a storage device configured to store a first language model database, a second language model database, a broadcasting device configured to broadcast the multi-lingual voice message, and a processor, connected to the storage device and the broadcasting device, configured to execute the method disclosed herein. |
| US09865250B1 |
Audibly indicating secondary content with spoken text
A system and method for navigating secondary content. The system may monitor for gestures input to the system by an input device and may detect an arc gesture. The arc gesture may travel along both a horizontal axis and a vertical axis from a first point to a second point and may be delineated from a horizontal or a vertical motion. The system may identify secondary content corresponding to the arc gesture in response to the arc gesture and output data corresponding to the secondary content. The system may identify supplemental text associated with the secondary content and synthesize supplemental speech corresponding to the supplemental text. The output data may include audio including the synthesized supplemental speech. |
| US09865247B2 |
Devices and methods for use of phase information in speech synthesis systems
A device may receive a speech signal. The device may determine acoustic feature parameters for the speech signal. The acoustic feature parameters may include phase data. The device may determine circular space representations for the phase data based on an alignment of the phase data with given axes of the circular space representations. The device may map the phase data to linguistic features based on the circular space representations. The linguistic features may be associated with linguistic content that includes phonemic content or text content. The device may provide a synthetic audio pronunciation of the linguistic content based on the mapping. |
| US09865241B2 |
Method for following a musical score and associated modeling method
A method for following a musical score in real time. At least one sound emitted by a performer is recorded. At least one chromatic vector is estimated. The chromatic vector is compared with theoretical chromatic vectors of the musical score. A transition between the chromatic vector and a previous chromatic vector with theoretical transitions of the musical score is compared. A work position of the performer depending on a previous work position is estimated from the comparison of the chromatic vector and the comparison of the transition. The recording is carried out for a suitable period depending on the ratio between a period of the transition and a reference period. |
| US09865233B2 |
Hybrid graphics display power management
Some embodiments describe techniques that relate to hybrid graphics display power management. In one embodiment, data corresponding to one or more image frames of a video stream are stored in a local frame buffer. A display device (e.g., an LCD) may then be driven based on the stored data in the local frame buffer or a video stream from a graphics controller. Other embodiments are also described. |
| US09865228B2 |
Computer program product, information processing method, and information processing apparatus
A computer program product includes a non-transitory computer-usable medium having computer-readable program codes embodied in the medium. The program codes when executed cause a computer to execute: detecting a connection status of an externally connected second display different from a built-in first display; writing status information indicating the detected connection status in a storage, changing over a display destination between the first display and the second display based on the detected connection status, and controlling a display screen according to screen specifications of the first display or the second display, which corresponds to the display destination after changeover; and reading the connection status written in the storage and scaling a display image at a magnification based on the read connection status. |
| US09865225B2 |
Providing a representation for a device connected to a display device
Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing a representation to a connected device. An embodiment operates by recognizing a new device connected to a display device, collecting device fingerprint information from the new device, and requesting a device class representation information determined based on the device fingerprint information. Another embodiment operates by receiving device fingerprint information from a display device via a network connection, wherein the device fingerprint information is collected from a device connected to a display device, and providing device class representation information to the display device via the network connection, when the device class representation information corresponding to the device fingerprint information is available. |
| US09865222B2 |
Systems and methods for displaying, distributing, viewing, and controlling digital art and imaging
System and method for displaying digital content on a display device, including a display screen, a structural assembly, secured to the rear face of the display screen, and a processing controller within the structural assembly, including a memory, display processor, and power distribution and adaptation module. An external power assembly configured to connect to an external power supply, a connector cord configured to connect the power assembly and the power distribution and adaptation module, and a case for the display device, configured to couple to the display screen to provide structural rigidity during shipping, are also presented. An application is provided, configured to run on a computer with memory, processor, and user input device, and configured to communicate via the internet with the processing controller of the display device and a service cloud including a server, memory, and processor, to control the display of digital content on the display screen. |
| US09865221B2 |
Voltage regulation circuit and liquid crystal display comprising the same
A voltage regulation circuit is provided, including a reverse processing module for processing a first initial voltage of a common voltage generating module so as to obtain a reverse voltage of AC voltage; and an integration module for regulating the first initial voltage according to the reverse voltage of the AC voltage so as to make a liquid crystal drive voltage equal to a preset value. The liquid crystal drive voltage is a difference value of between a second initial voltage and the first initial voltage which is regulated. |
| US09865220B2 |
Gate driving circuit and display device
The present disclosure discloses a gate driving circuit and a display device, to avoid power consumption arising from overlapping of voltages output by the output ends of gate drivers in the case that the gate driving circuit is configured with a plurality of clock signals. The gate driving circuit includes: a plurality of gate scan lines, and N stages of gate drivers connected in cascade. Each stage of gate drivers includes a reset end and an output end, which provides a gate scan signal to a corresponding gate scan lines. The output end of a m-th stage gate driver is connected provides a reset signal to the reset end of a (m−1)-th stage of gate drivers, N and m are positive integers, and m |
| US09865219B2 |
Liquid crystal display device with an integrated touch panel and method of driving the same
Disclosed is an LCD device and a method of driving the same. The LCD device includes a liquid crystal panel configured to comprise a TFT substrate and a color filter substrate; a touch panel configured to comprise a plurality of driving electrodes and a plurality of receiving electrodes; a common voltage generator configured to generate a common voltage; a touch sensing unit configured to supply the common voltage to the driving electrodes and sequentially supply a driving voltage to scanned driving electrodes, corresponding to scanned gate lines to which a scan signal has been inputted for one frame period, to detect a touch; and a driving voltage generator configured to generate the driving voltage. |
| US09865214B2 |
Shift register, driving method thereof, gate driving circuit and display device
A shift register unit includes: a pull-up node control unit; a pull-down control node control unit connected with a first level output terminal, and configured to control an electrical potential at a pull-down control node to be a second level when an electrical potential at a pull-up node is a first level, and to control a pull-down control node to be connected with a first level output terminal when the electrical potential at the pull-up node is a third level; a pull-down node control unit; a gate driving signal output unit; and a carry signal output unit configured to control a carry signal output terminal to output a carry signal under the control of the pull-up node and the pull-down node. The carry signal output terminal provides an input signal to a shift register unit in an adjacent next stage. |
| US09865213B2 |
Scan driver circuit for driving scanning lines of liquid crystal display
A scan driver circuit for driving scanning lines is proposed. The scan driver circuit includes a pull-down control module, a pull-down module, a recovering control module, a recovering module, a downlink module, a first bootstrap capacitor, a constant low voltage supply, and a constant high voltage supply. The present inventive scan driver circuit has advantages of simple structure and low power consumption. |
| US09865211B2 |
Shift register unit, gate driving circuit and display device
There are provided a shift register unit, a gate driving circuit and a display device, which enable gate lines in non-output rows to remain in the state of no signal outputting. The shift register unit comprises an input module (10), a pull-up module (20), a pull-down control module (30), a first pull-down module (31), a second pull-down module (40) and a reset module (50). In the non-output time, the first pull-down module and the second pull-down module pull down the output voltages of the pull-up modules connected thereto to a low level alternately, thereby enabling gate lines in non-output rows to remain in the state of no signal outputting. |
| US09865203B2 |
Display apparatus and method of driving the same
A display apparatus includes pixels. A first pixel group of the pixels displays a first grayscale image on the basis of a first gamma curve during three sub-frame periods among consecutive first to fourth sub-frame periods and displays a second grayscale image based on of a second gamma curve during a remaining one sub-frame period of the first to fourth sub-frame periods. A second pixel group of the pixels displays a third grayscale image based on the first gamma curve during three sub-frame periods among the first to fourth sub-frame periods and displays a fourth grayscale image based on the second gamma curve during a remaining one sub-frame period of the first to fourth sub-frame periods. A sub-frame period in which the first pixel group displays the second grayscale image is different from a sub-frame period in which the second pixel group displays the fourth grayscale image. |
| US09865198B2 |
Display device of active matrix type
A display device of active matrix type allows reducing display brightness non-uniformity that is caused by initial variation and fluctuation over time in a driving transistor for emissive elements in pixel circuits. The display device includes pixel circuits, a measurement circuit and a gradation voltage supplying circuit. Each pixel circuit includes the driving transistor and an input circuit. The measurement circuit includes a constant current supplying circuit for generating and supplying one or more constant currents to the input circuit of the pixel circuits in a time division manner. The measurement circuit A/D-converts output voltages of the constant current supplying circuit and calculates data relating to electron mobility and threshold value of the driving transistor. The gradation voltage supplying circuit supplies to the pixel circuits a corrected gradation voltage, which is data corrected on the basis of data calculated from the measurement circuit. |
| US09865197B2 |
Method for determining a refresh frequency for a matrix of OLED active pixels and corresponding device
A device includes an OLED pixel and a control circuit controlled at a refresh rate thereof. The device includes first and second dummy control circuits having similar operating characteristics to the control circuit. A controller and logic circuit switch on the first and second dummy control circuits and apply an input voltage so the first and second dummy control circuits output first and second output voltages. At a first time, the controller and logic circuit switch off the second dummy control circuit so a leakage current flows through the second dummy control circuit to ground, causing the second output voltage to reduce. Comparison circuitry determines a second time at which, due to the reduction of the second output voltage, a difference between the first and second output voltages is greater than a threshold. Determination circuitry determines the refresh frequency based upon elapsed time between the first and second times. |
| US09865191B2 |
Image processing device, display device, electronic device and method for processing an image
An image processing device comprising: a conversion unit to receive a first input signal including first color information, a first color being reproduced at pixels on the basis of the first color information, the first input signal including first color information obtained from an input image signal corresponding to a red component, a green component and a blue component, to specify saturation of the first color, and configured to obtain luminance attenuation ratio on the basis of a relationship previously stored between saturation and luminance attenuation ratio, and the saturation of the first color, and to output a second input signal including second color information whose luminance is decreased from the first color information on the basis of the luminance attenuation ratio corresponding to the first color information; and a signal processing unit configured to output an output signal for driving the pixels on the basis of the second input signal. |
| US09865186B2 |
Apparatus, system, and method for displaying content on a vehicle
Methods, systems, and apparatuses for displaying or projecting images on a vehicle are described herein. The methods include receiving location data of a vehicle, determining content corresponding to the location, and providing images corresponding to the content to projectors for display on a side of a vehicle. The systems include a vehicle, projectors mounted on the vehicle such that an image created by the projector is cast on a surface of the vehicle, and a control module configured to provide images to the one or more projectors for display on a side of the vehicle. The apparatuses include a location module that determines a current location of a vehicle, a content selection module that determines a content corresponding to the current location, and a display module that provides images corresponding to the content to one or more projectors for display on a side of a vehicle. |
| US09865185B2 |
LED matrix lighting device
One embodiment of a light emitting diode (LED) lighting device comprises multiple LED light sources disposed on multiple elongated circuit boards, with each LED light source being electrically connected to one of the circuit boards. The elongated circuit boards are electrically coupled using electrical passageways to provide power to the circuit boards at intervals along the length of the elongated circuit boards, and the light sources disposed on the circuit boards emit light in the same direction perpendicular to the elongated circuit boards. The electrical passageways can be wires or groups of wires. |
| US09865182B2 |
Fibers with surface markings used for coding
Disclosed are fibers comprising one or more branded fibers which exhibit surface markings in a repeated pattern along the length of the branded fibers. The branded fibers can be incorporated into yarns or fiber bands to represent supply chain information of the yarns, fiber bands, and/or articles made from the yards or fiber bands. In a specific example, branded fibers can be incorporated into an acetate tow band The branded fibers can be recovered from a cigarette filter, the repeated pattern decoded, and supply chain information associated with the acetate tow used to make the cigarette filter, such as manufacturer, customer, ship to location, and even the acetate tow bale, can be obtained. |
| US09865180B2 |
Heart phantom assembly
A heart phantom assembly comprises a mechanical actuator system comprising a support operatively supporting at least two actuators and a fixing device. A phantom interface is operatively connected to the at least two actuators to be displaceable in at least one translational degree of freedom and at least one rotational degree of freedom as a function of actuation from the at least two actuators. A deformable heart phantom is connected at an end to the phantom interface, and at another end to the fixing device, to be subjected to compression/expansion in response to movements of the phantom interface in the translational degree of freedom, and to torsion in response to movements of the phantom interface in the rotational degree of freedom. |
| US09865173B2 |
Method and apparatus to encourage development of long term recollections of given episodes
These teachings are applicable for use with an individual who faces problems with respect to forming new long term memories. Generally speaking, pursuant to these various embodiments, one automatically captures (101) a record of experiential content to which the individual is exposed during a given episode and then automatically associates (102) that record of experiential content with metadata that characterizes the given episode. This record of experiential content is then automatically used (103) to re-expose the individual to at least portions of the given episode to thereby encourage development of a long term recollection of at least a portion of the given episode. These teachings will accommodate a variety of experiential content modalities including both audio content and visual content. |
| US09865168B2 |
Detecting misbehavior in vehicle-to-vehicle (V2V) comminications
A method includes: receiving, at a host vehicle, a plurality of messages transmitted using Vehicle-to-Vehicle (V2V) communications indicating a heading angle and a speed of a remote vehicle; calculating an expected change in frequency of the plurality of messages received at the host vehicle based on the heading angle and the speed of the remote vehicle; measuring an actual change in frequency of the plurality of messages received at the host vehicle due to the Doppler effect; comparing the expected change in frequency to the actual change in frequency; and determining that the plurality of messages were not transmitted from the remote vehicle when a difference between the expected change in frequency and the actual change in frequency exceeds a predefined frequency change threshold. |
| US09865164B2 |
Vehicle operation assistance information management
A vehicle may traverse a portion of a vehicle transportation network, which may include a processor of the vehicle executing instructions to identify a first vehicle operation assistance information item, and, on a condition that an immanency for the first vehicle operation assistance information item is within a maximum relevant immanence and a utility metric for the first vehicle operation assistance information item indicates high utility, present a representation of the first vehicle operation assistance information item by, on a condition that a first urgency identified based on the immanency indicates a warning urgency or an advisory urgency, controlling a primary graphical display portion to present a first portion of a graphical representation of the first vehicle operation assistance information item, and controlling a secondary graphical display portion to present a second portion of the graphical representation. |
| US09865163B2 |
Management of mobile objects
To use a high-quality driving support and automatic driving system that manages a plurality of mobile objects through communication with the mobile objects to manage mobile objects that do not communicate with this system, provided is a system including a mobile object server operable to assist with movement of a plurality of mobile objects within a geographic space, wherein the mobile object server having: a monitoring section operable to monitor movement of a first mobile object that does not receive at least a portion of movement assistance and an assisting section operable to assist with movement of a second mobile object that is an assistance target, using a result obtained by monitoring the first mobile object. Also provided is a method and program product. |
| US09865162B2 |
Control method for traveling apparatus and traveling control apparatus
A control method allows an own vehicle to proceed through a specific intersection into which vehicles are permitted to proceed in the order that the vehicles arrive. The method includes setting a determination region within a lane other than a lane in which the own vehicle travels; determining whether the own vehicle reaches a certain position at the near side of the specific intersection; allocating a priority state to the determination region when the own vehicle reaches the certain position and allocating a non-priority state to the determination region in which the vehicle does not exist when the own vehicle reaches the certain position; changing the priority state of the determination region to the non-priority state when the vehicle no longer exists in the determination region; and allowing the own vehicle to proceed into the specific intersection when the determination region of the priority state is not present. |
| US09865161B2 |
Method, remote controller and electrical applicance for releasing a binding of a remote controller
A method, a remote controller and an electrical appliance for releasing a binding of a remote controller are provided. The method includes: acquiring, by the remote controller, a trigger event for releasing a binding; broadcasting, by the remote controller, a request to release the binding based on the trigger event for releasing the binding; judging, by an electrical appliance, whether a binding relationship between the electrical appliance and the remote controller needs to be released based on the request to release the binding; and releasing the binding relationship between the electrical appliance and the remote controller upon the judgment that the binding relationship between the electrical appliance and the remote controller needs to be released. |
| US09865160B2 |
System and method for the remote control of the shared access to one or more items
A system and method for remotely controlling access of at least one user to one or more properties belonging to an owner in order to share the properties, wherein at least one electric interface device is connected to controlling and/or servoassisting elements associated with one property and configured to perform at least one electric, electromechanical and/or optical interaction with the property. Each electric interface device is remotely connected to a mainframe via a long-distance communication line. The identification data of the user, the property to be shared and the allowed interactions with each electric interface device associated with the property, are stored in the memory of the mainframe. A data communication is established between the electric interface device and the mainframe and temporarily assigned to the user which enables one or more interactions with the at least one electric interface device associated with a property. |
| US09865156B2 |
System for contextualizing and resolving alerts
Systems and methods for generating an alert resolution status based on a contextualized alert. An asset repository stores asset-specific data for interpreting an asset parameter. A diagnostic contextualization component is coupled to the asset repository and generates the contextualized alert by retrieving data in the repository. The component also generates the alert resolution status based on determinations related to the contextualized alert. |
| US09865154B2 |
Adaptive exit arm times based on real time events and historical data in a home security system
A security system includes a plurality of sensors installed at a premises to capture data from an environment in or around the premises, a memory configured to store data captured spanning at least a first period of time, and a processor configured to arm the plurality of sensors in an order determined based on a history of detected activity in the premises as indicated by the stored data. |
| US09865153B2 |
Method using a mobile computing device to improve Bluetooth anti-lost reminder in precise positioning and remindering
Systems and methods for precise location and tracking of a bag, wallet or luggage body. The system having a bag, wallet or luggage body having an anti-lost communication device attached to the bag, wallet or luggage body, the anti-lost communication device comprising a wireless communication device; and an application on a mobile computing device in communication with the wireless communication device, wherein the application issues a reminder on the mobile computing device when it determines the wireless communication device is a predetermined distance from the mobile computing device or the wireless communication device has lost communication with the mobile computing device. |
| US09865151B2 |
Observation system and method for controlling observation system
An observation system includes: a power supply unit having a battery; a sensor unit which detects a state of a structure on the basis of electricity from the power supply unit; a charging unit which charges the battery from renewable energy; and a processing unit which processes sensing information in one observation mode of a plurality of observation modes including at least a first observation mode and a second observation mode in which at least one of a sensor capability of the sensor unit and a load of computational processing using the sensing information is higher than in the first observation mode. The processing unit sets an observation mode on the basis of information for disaster occurrence estimation. |
| US09865149B1 |
Fingerprint reader child tracking system
A child tracking system includes an electronic device that may be manipulated. A pair of tracking units is provided. Each of the tracking units may be worn by an associated one of an adult and a child. Each of the tracking units may be in communication with a global positioning satellite. Thus, a physical location corresponding to each of the tracking units may be identified. Each of the tracking units is in electrical communication with the electronic device. Thus, the electronic device may display the physical location corresponding to each of the tracking units. Each of the tracking units has a fingerprint reader to read fingerprints. |
| US09865147B2 |
Collision warning system
A self-contained collision warning device warns of possible collisions between people and between people and moving objects on opposite sides of doors and other visual barriers. Motion sensors detect the presence of people or moving objects and activate indicators that warn of the presence of unseen people and moving objects. The device can be mounted to a door or wall without modification to the door or wall or access to electrical power. |
| US09865143B2 |
Status displaying device and method thereof for solid-state drive
The present invention discloses a status displaying device and method thereof for a Solid-State Drive (SSD). The status displaying device may include a non-volatile memory, an emitting unit, a firmware, and a first control unit. A first instruction is generated and transmitted by the firmware. The first instruction is received by the first control unit. The first control unit performs a first operation on the non-volatile memory and controls the emitting unit to have a first emitting behavior according to the first instruction. |
| US09865136B2 |
Computer gaming device and method for computer gaming
A system for computer gaming includes a processor configured to provide a first table of a first group of players grouped together to play a first hand and provide to each of the first group of players one or more cards for the first hand. The system includes an interface couple to the processor and configured to receive from a first player of the first group of players a request to fold the one or more cards of the first player. The processor is also configured to automatically move the first player to a second table of a second group of players grouped together to play a second hand. |
| US09865135B2 |
Methods for selling pre-printed online lottery tickets
A system and method of selling pre-printed lottery tickets for random draw lotteries through the retailers POS without the use of additional lottery hardware. Pre-printed lottery tickets allow a consumer to purchase a lottery ticket for a subsequently occurring draw by including that ticket in their shopping basket. The pre-printed lottery ticket may be purchased as any other common product through the point of sale terminal. No specialized hardware such as lottery terminal, printer or dispensing device is necessary. |
| US09865131B2 |
Gaming machine having a first display and a second display
Provided is a gaming machine that can offer various play patterns and payout patterns without giving the player distrust or uncomfortableness. Upon establishment of a bonus trigger, a main CPU conducts a jackpot challenge lottery; if a jackpot is drawn, conducts another lottery to select either one of the prizes, Credit or Jackpot+Credit; if the prize Credit is drawn, pays out a determined amount to be credited; if the prize Jackpot+Credit is drawn, conducts another lottery for a jackpot prize, and pays out the amount corresponding to the drawn prize and the amount to be credited. |
| US09865127B2 |
Regulated hybrid gaming system
Systems of detecting unauthorized operation of a hybrid game are disclosed, including a hybrid game associated with a player, the hybrid game constructed to: communicate game operating performance data (GOPD); and the a regulatory scanning and screening audit (RSSA) module connected to the hybrid game via a communication link, the RSSA module constructed to: receive GOPD comprising game world credit information for game world credit accrued by the player, and real credit information for real credit committed by the player; determine a rate of accrual of the game world credit and a rate of commitment of the real credit; determine whether the player is operating the hybrid game in an unauthorized manner; and communicate a notification causing the hybrid game to suspend operation. |
| US09865123B2 |
Wide screen gaming apparatus
A gaming apparatus includes a display unit and has a display support structure that extends substantially vertically from a horizontal support base. The display unit includes a flat-panel display screen having a width (W) and a height (H) wherein W/H is at least 16/10 The display unit is rotatable about a horizontal axis located in a plane substantially parallel to the display screen wherein, a player's angle of viewing the display unit may be adjusted by vertical translation of the display unit on the display support structure, over a vertical range of motion, and by rotation of the display unit about the horizontal axis. A front face of the display structure presents, in a region proximate to the vertical range of motion, a concave side of a curved surface. |
| US09865122B2 |
Gaming apparatus with special symbols
Systems and methods for determining a plurality of outcomes of a game of chance are provided. In a spinning reel game, for example, a first game event may be provided in which a plurality of symbols are spun up on a plurality of spinning reels to form an array of symbols, each spinning reel spinning up at least three symbols and at least one of the spinning reels being defined so that at least two feature symbols can be simultaneously spun up on that reel. A result of the spin is evaluated to assess whether two or more feature symbols have been spun up on the same reel. If so, a second game event is provided in which the two or more feature symbols and all other symbols spun up on the same reel are converted to special symbols. The special symbols have an enhanced play characteristic in comparison to the other symbols, and the outcome of the game is re-evaluated to establish whether any outcomes exist which define a winning combination. A prize or an award is awarded if one or more winning combinations exist. |
| US09865120B2 |
Gaming machine and backlit reel device thereof
A gaming machine includes: a reel having an outer circumferential surface on which symbols are lined up; a reel driving mechanism which rotates the reel to rearrange the symbols; a magnet which is provided in the reel driving mechanism to change an external magnetic field in accordance with the rotation of the reel; a magnetic force detecting mechanism which detects a magnetic force of the external magnetic field so as to output a magnetic force detection signal; a reel setting unit by which the magnetic force detection signal and arrangement positions of the symbols are associated with one another; and a reel drive control unit which controls the reel driving mechanism so that the symbols are rearranged in a predetermined arrangement based on the magnetic force detection signal and the arrangement positions of the symbols. |
| US09865111B2 |
Fob case for reduced transmission interference
A fob includes a case, an antenna, at least one input device, and a positioning element. The case has an interface portion and a handle portion. The antenna is disposed at the interface portion of the case. The input device is disposed on the interface portion of the case. The finger positioner orients a user's hand on the handle portion of the case away from the antenna. |
| US09865106B2 |
Wireless protocol message conversion device and methods of using thereof
A method of wireless forwarding of service related content in a communication session. The method comprises providing a conversion circuit fixated in proximity to a service providing system and having a client side communication unit and a system side communication unit, intercepting, using the client side communication unit, a first wireless data message having service related content encoded according to a first communication protocol, generating, using the system side communication unit, a second wireless data message having the service related content encoded according to a second communication protocol, and transmitting, using the system side communication unit, the second wireless data message to the service providing system. |
| US09865104B1 |
Gesture encrypted access system based on multidimensional code
A system and approach utilizing a multi-dimensional code on a card and a gesture applied to the card for a scan. The two-dimensional card may contain information about the card holder, other individuals, the facility or area at which access is desired, and a gesture relating to scanning the card. Appropriate information and a correct gesture applied to the card during a scan may enable a holder of the card to gain access to the facility or area. The gesture may legitimize the card holder. |
| US09865101B2 |
Methods for detecting one or more aircraft anomalies and devices thereof
Methods, devices, and non-transitory computer readable media that detect an anomaly in an aircraft include obtaining aircraft flight data from multiple aircraft sensor devices. The obtained aircraft flight data is clustered into two or more data groups. A distance between the clustered aircraft flight data in at least one of the two or more data groups associated with a part of the aircraft and stored baseline flight data for the part of the aircraft is determined. A statistical model analysis is executed on the determined distance to detect any anomaly with the part of the aircraft. |
| US09865099B2 |
Vehicle installed mobile device and server for GPS services and task assignments
Mobile device installed in a vehicle for communicating a current location and a current destination, to a coordination server, receiving a set of tasks (statically assigned or dynamically assigned) for the user (for example, from the server or from another user or adhoc tasks specified by a customer), displaying the set of tasks to the user, receiving a completion response (successful or unsuccessful) from the user, and proceeding to the next waypoint along a route/trip plan. A coordination server facilitates communication of a list of tasks dynamically and opportunistically assigned to a user to be performed at a specified location. |
| US09865098B2 |
Systems and methods for forecasting travel delays
Various embodiments of the present invention are directed to a fleet management computer system configured for forecasting travel delays within a geographic area. According to various embodiments, the fleet management computer system is configured to assess operational data, including vehicle telematics data. In various embodiments, the fleet management computer system is further configured to determine, based on the operational data, a value indicative of the average amount of travel delay time per unit of distance within the geographic area, such as the average amount of idle time second per mile of travel with the geographic area. |
| US09865097B2 |
Identifying matching properties between a group of bodies representing a geological structure and a table of properties
Systems and methods for identifying matching properties between a group of bodies representing a geological structure and a table of properties by performing property matching on the group of bodies to convert each body to a respective compartment represented by a triangulated mesh of the bounding body. |
| US09865090B2 |
Portable information processor and method of controlling head-mountable display
A system includes a head-mountable display and a portable information processor. The portable information processor includes a determination device that determines whether communication between a head-mountable display and the portable information processor is enabled. The portable information processor includes an identification device that identifies at least a portion of image data that is displayed by the portable information processor. The portable information processor includes a transmitter that transmits the identified at least a portion of the image data to the head-mountable display when the determination device determines that communication between the head-mountable display and the portable information processor is enabled. The head-mountable display includes a receiver that receives the identified at least a portion of the image data from the portable information processor. The head-mountable display includes a display that displays the identified at least a portion of the image data. |
| US09865086B2 |
Methods and systems for generating a multi-dimensional surface model of a geometric structure
The present disclosure provides systems and methods for generating a multi-dimensional surface model of a geometric structure. The system includes a device including at least one sensor configured to collect a set of location data points corresponding to respective locations on or enclosed by a surface of the geometric structure, and a computer-based model construction system coupled to the device. The computer-based model construction system is configured to generate a working volume based on the set of location data points, calculate a dilated field for the working volume, define a dilated surface based on the dilated field, calculate an eroded field for the working volume based on the dilated surface, and define an eroded surface based on the eroded field. |
| US09865085B1 |
Systems and methods for 3D modeling using skipping heuristics and fusing
Systems and methods for three dimensional modeling using skipping heuristics and fusing are disclosed herein. An example method includes obtaining a plurality of three dimensional models of a target, each of the models having a unique resolution level, assembling an aggregate three dimensional model using a hierarchical tree representation of the plurality of three dimensional models by skipping levels of detail in the hierarchical tree and rendering the levels of the hierarchical tree that were not skipped. Fusing overlapping sections of the aggregate model can be accomplished using bivariate visibility testing. |
| US09865082B2 |
Image processing system, X-ray diagnostic apparatus, and image processing method
An image processing system according to an embodiment includes an input unit, an output unit, an acquiring unit, and a display unit. The input unit receives setting of a landmark in first medical image data obtained by capturing a certain tissue of a subject. The output unit outputs data including information of the position of the landmark in the first medical image data as output data. The acquiring unit receives the output data and acquires, based on one or a plurality of pieces of second medical image data obtained by capturing the certain tissue of the subject and the position of the landmark, three-dimensional position information of the landmark in a three-dimensional capturing space of the second medical image data. The display unit displays image data obtained by superimposing the first medical image data on the second medical image data, based on the three-dimensional position information. |
| US09865080B2 |
Velocity volume rendering with sign-based termination in ultrasound
Velocities are volume rendered in ultrasound. Early ray termination is used to avoid compositing velocities of different signs together. As long as the velocities are of the same sign, compositing continues from the viewer to a back of the volume being rendered. Once the velocity changes sign, compositing is reduced or terminated to avoid compositing velocities of different directions. The velocity rendering emphasizes the velocities of one direction closest to the viewer. |
| US09865066B2 |
Computed tomography system for cargo and transported containers
An imaging system includes an x-ray or gamma ray source that emits an x-ray or gamma ray beam, a tunnel having a plurality of detectors, and a translatable platform. The detectors each receive a portion of the beam. The translatable platform supports cargo or a transported container and moves through the tunnel so that the cargo or transported container crosses the portions of the beam received by the detectors. The translatable platform may rotate and move through the tunnel at multiple angles. The imaging system may also include a computer and a graphical interface. The computer may receive information collected by the detectors and may reconstruct a three-dimensional image of the cargo or transported container. The graphical interface may display the three-dimensional image or information derived from the three-dimensional image. According to other embodiments, a system for creating a three-dimensional image may receive data from a wide vertical beam angle and generate and output a three-dimensional model. |
| US09865062B2 |
Systems and methods for determining a region in an image
A method for determining a region of an image is described. The method includes presenting an image of a scene including one or more objects. The method also includes receiving an input selecting a single point on the image corresponding to a target object. The method further includes obtaining a motion mask based on the image. The motion mask indicates a local motion section and a global motion section of the image. The method further includes determining a region in the image based on the selected point and the motion mask. |
| US09865059B2 |
Medical image processing method and apparatus for determining plane of interest
A medical image processing apparatus includes a data acquirer that scans an object with a fiducial marker attached thereto to acquire volume data, and a data processor that estimates a plane of interest, based on a position of the fiducial marker and a position of a landmark in the volume data. |
| US09865058B2 |
Three-dimensional mapping system
A survey application generates a survey of components associated with a three-dimensional model of an object. The survey application receives video feeds, location information, and orientation information from wearable devices in proximity to the object. The three-dimensional model of the object is generated based on the video feeds, sensor data, location information, and orientation information received from the wearable devices. Analytics is performed from the video feeds to identify a manipulation on the object. The three-dimensional model of the object is updated based on the manipulation on the object. A dynamic status related to the manipulation on the object is generated with respect to reference data related the object. A survey of components associated with the three-dimensional model of the object is generated. |
| US09865054B2 |
Evaluation method of spheroid and spheroid evaluation apparatus
An evaluation method of a spheroid comprises specifying a spheroid region taken up by the spheroid out of the image including the spheroid and a surrounding region thereof, obtaining an average value of an optical density of the spheroid and a magnitude of a variation of the optical density in the spheroid from an image density of the spheroid region, obtaining a circularity of the spheroid from a contour of the spheroid region, obtaining a sharpness of the spheroid from the image densities of the spheroid and the surrounding region thereof, and obtaining the collapse degree of the spheroid by substituting the average value of the optical density, the magnitude of the variation of the optical density, the circularity and the sharpness into a predetermined operational expression. |
| US09865051B2 |
Vascular territory segmentation using mutual clustering information from image space and label space
Methods, systems, computer programs, circuits and workstations are configured to generate at least one two-dimensional weighted CBF territory map of color-coded source artery locations using an automated vascular segmentation process to identify source locations using mutual connectivity in both image and label space. |
| US09865050B2 |
Measuring intramuscular fat
Dual-energy absorptiometry is used to estimate intramuscular adipose tissue metrics and display results, preferably as related to normative data. The process involves deriving x-ray measurements for respective pixel positions related to a two-dimensional projection image of a body slice containing intramuscular adipose tissue as well as subcutaneous adipose tissue, at least some of the measurements being dual-energy x-ray measurements, processing the measurements to derive estimates of metrics related to the intramuscular adipose tissue in the slice, and using the resulting estimates. Processing the measurements includes an algorithm which places boundaries of regions, e.g., a large region and a smaller region. The regions are combined in an equation that is highly correlated with intramuscular adipose tissue measured by quantitative computed tomography in order to estimate intramuscular adipose tissue. |
| US09865047B1 |
Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool
Systems and methods for providing improved wafer geometry measurements are disclosed. A wafer geometry measurement system may utilize techniques that enable the wafer geometry measurement system to identify and reduce wafer surface errors caused by structures such as patterns on the wafers being measured. The wafer geometry measurement system may also utilize techniques that enable the wafer geometry measurement system to accurately reconstruct patterned wafer surfaces. |
| US09865040B2 |
Electronic device including sub-array based deblurring of a blurred finger image and related methods
An electronic device may include a finger biometric sensor that includes an array of electric field sensing pixels and image data output circuitry coupled thereto and capable of processing the image data from each of sub-arrays of the array of electric field sensing pixels. The electronic device may also include a dielectric layer over the array of electric field sensing pixels and causing electric field diffusion so that the image data output circuitry generates image data corresponding to a blurred finger image. The electronic device also includes deblurring circuitry coupled to the image data output circuitry and capable of processing the image data from each of the plurality of sub-arrays of the array of electric field sensing pixels to produce processed image data representative of a deblurred finger image. |
| US09865036B1 |
Image super resolution via spare representation of multi-class sequential and joint dictionaries
A method of developing an image training library includes receiving, at a processor, a set of high resolution image samples at a first resolution, generating a set of low resolution image samples having a second resolution from the set of high resolution images, wherein the second resolution is lower than the first resolution, clustering the low resolution image samples using features in the low resolution images, generating a low resolution dictionary for each cluster, generating sparse coefficients for each sample, and using the sparse coefficients to generate a high resolution dictionary for each cluster. |
| US09865029B2 |
Contextual rendering of process graphics
Contextual rendering systems, methods, and computer-readable media include circuitry configured to parse a graphics file into a plurality of graphics objects, determine whether one or more dynamic behavior attributes are present for each graphics object, extract at least one tag name for each graphics object having the one or more dynamic behavior attributes, assign an attribute weight to each dynamic behavior attribute, compute a sum of the attribute weights for each tag name-graphics object combination, rank each of the tag name-graphics object combinations according to the respective computed sum, and display a portion of a graphics view of one or more graphics objects for a first-ranked tag name-graphics object combination in context with other graphics objects. |
| US09865027B2 |
System and method for embedding of a two dimensional code with an image
Disclosed are a method and apparatus for embedding a graphic image representation into a two dimensional matrix code by modifying the characteristic values of individual pixels in the image according the values of a provided two dimensional matrix code image. The modified character pixel values are determined using an optimization procedure that minimizes a visual distortion with respect to the original graphic image representation while maintaining the value of a probability of error model below a specified limit. |
| US09865025B2 |
Electronic health record system and method for patient encounter transcription and documentation
A patient encounter documentation and analytics system includes a mobile computing platform and a server-based host platform. A mobile application in tandem with a wireless microphone collects voice signals during a patient-caregiver encounter, transforms the voice signals into audio data files, and uploads the audio data files to the server. A speech recognition software module digitally transcribes the audio data file into text. A text processing module extracts and organizes relevant clinical data based on keyword, key phrase and question/answer analysis. Relevance of words and phrases may be determined in view of, e.g., their presence, frequency and context. A diagnostic decision support module enables the healthcare provider to review the determined clinical information and provide a diagnosis associated with the encounter. A documentation skeleton module extracts diagnosis-specific text components from the transcribed text file and assembles an electronic medical document based on the diagnosis and the diagnosis-specific text components. |
| US09865022B2 |
System and method for defining a drilling path based on cost
Provided is a method for selecting one of a plurality of convergence paths that may be drilled by a bottom hole assembly (BHA) comprising identifying, by a computer system, a plurality of geometric convergence paths, wherein each of the geometric convergence paths provides a convergence solution from a defined bottom hole assembly (BHA) location to a target drilling path of a well plan. An offset distance is calculated for drilling by the BHA each of the geometric convergence paths connecting the BHA location to the target drilling path. A drill path curvature associated with drilling each of the geometric convergence paths by the BHA is determined by the computer system. A time required for drilling each of the geometric convergence paths by the BHA is determined by the computer system. An optimal geometric convergence path of the plurality of geometric convergence paths is determined responsive to the offset distance for drilling each of the geometric convergence paths, the drill path curvature associated with each of the geometric convergence paths and the time required for drilling each of the geometric convergence paths. The determined optimal geometric convergence path is fed to a controller associated with a display of a drilling rig and used to control the display of the drilling rig to display the determined optimal geometric convergence path. |
| US09865016B2 |
Constrained environmental monitoring based on data privileges
A sensor mechanism in an environmental monitoring device provides sensor data that represents an environmental condition in an external environment that includes the environmental monitoring device. Then, a control mechanism in the environmental monitoring device generates subsets of the sensor data based on data privileges of different entities, where the data privileges of at least some of the entities are different from each other, and at least some of the corresponding subsets of the sensor data are different. For example, the data privileges may specify: different spatial extents in the external environment monitored by the sensor mechanism; and/or different types of information associated with the external environment. Next, an interface circuit in the environmental monitoring device provides the subsets of the sensor data to electronic devices associated with the entities. |
| US09865014B2 |
Customer terminal and self-shopping system
A customer terminal of a “self-scanning shopping” system, which is configured to store at least one shopping session in a non volatile memory, includes a main processor, a product code reader, a location for non volatile storage of an open shopping session indicator and/or an identifier, either direct or indirect, of a shopping session, and a supervisor circuit. In a working operating state, the main processor periodically sends a heartbeat to the supervisor circuit. The supervisor circuit commands a reset of the main processor when, from the lack of receipt of the heartbeat, it detects a non working operating state of the main processor. The main processor, upon reset, checks whether there is an open shopping session based on the contents of said memory location and in the affirmative case restores said shopping session. |
| US09865011B2 |
Notifying registrants of domain name valuations
Systems and methods of the present invention provide for one or more server computers communicatively coupled to a network and configured to: receive at least one search for a domain name; generate the notice comprising: the at least one search; at least one unsolicited offer for the domain name; and/or a valuation of the domain name based on the at least one search or the at least one unsolicited offer; identify a contact data in a database; and transmit the notice to the registrant via the contact data. |
| US09865010B2 |
Online store product availability
A technique for effecting electronic commerce using a data network is described. The data network includes a plurality of subsystems which, together, form an integrated system for receiving customer orders for selected items via a data network, fulfilling the customer orders, and delivering the ordered products to the customers. Moreover, according to a specific embodiment, the integrated nature of the system architecture of the present invention allows the on-line merchant to provide a guarantee to the customer that the ordered items will be available to be delivered to the customer at the specified delivery date, time, and location. |
| US09865008B2 |
Determining a configuration of a content item display environment
Methods, and systems, including computer programs encoded on computer-readable storage mediums, including a method for determining a configuration of a content item display environment. The method includes receiving a content item request for a content item to display in a content item display environment in a resource, the resource hosted on a first domain and the content item display environment hosted on a second domain, wherein the first domain includes a publisher side file; providing the content item along with measuring instructions operable to interact with the publisher side file to generate a child display environment, wherein the measuring instructions interact with the resource through the child display environment to cause measurement data to be generated, wherein the measuring instructions are prevented from interacting with the resource through the content item display environment; and receiving the measurement data specifying a configuration of the content item display environment and the resource. |
| US09865007B2 |
System and method for managing multimedia sales promotions
A system for managing multimedia sales promotions includes an inventory database containing photos and videos of items in a sales inventory. A distribution server that distributes the photos and videos. The system further includes a computer having an input device that receives input from a user. The computer further includes an item selector that selects an item in the inventory based on a user input. The computer further includes a photo editor that edits photos based on a user input. The computer further includes a video editor that adds a soundtrack to the videos based on a user input. The computer further includes a display that displays the photos and videos and interfaces for the photo editor and video editor to the user. |
| US09865002B2 |
Ultrasonic near-field communication
Systems and methods for near-field communications with a mobile device are disclosed. In one embodiment, a computer-implemented method for near-field communication may comprise: detecting, by a source device located at a point-of-sale, the proximity of a receiving device; encoding purchase data on an audio signal with one or more ultrasonic frequencies; and transmitting the encoded purchase data to the receiving device, wherein the encoded purchase data is transmitted using a speaker of the source device. |
| US09864991B2 |
Method and apparatus for secure transaction management
Methods and apparatuses for secure transaction management are provided. An example method may include verifying that a mobile terminal identifier is registered with an account, generating an authorization code, and verifying that the received authorization code matches the authorization code stored in association with the account, and the received customer verification number matches the customer verification number associated with the account. The example method may also include providing for transmission of a verification reply to authorize the transaction. |
| US09864989B2 |
Method and apparatus for ordering goods, services, and content over an internetwork using a virtual payment account
A secure, closed virtual payment system comprising registered buyers and sellers for ordering and paying for goods, services, and content over an internetwork is disclosed. A buyer becomes registered by applying for a virtual payment account. A seller becomes registered by applying for a seller account. A credit processing component (53) immediately evaluates the buyer's application and assigns a credit limit to the account. Once an account is established, a digital certificate is stored on the registered participant's computer. The buyer can then order goods, services, or content from a seller and charge it to the virtual payment account. When the product is shipped, the seller notifies a commerce gateway component (52), which, in turn, notifies the credit processing server, which applies the charges to the buyer's virtual payment account. |
| US09864986B1 |
Associating a monetary value card with a payment object
Methods and apparatuses related to linking a monetary value card with a payment card. In some embodiments, a payer uses a gift card to pay for a purchase. The gift card is swiped by a point of sale (POS) system, and a computer system processes a payment. The computer system causes the POS system to display a message prompting the payer to provide an email address for an electronic receipt. The payer provides the email address, which the computer system uses to determine that the payer has a payment card. The computer system sends a message to the payer asking if he would like to link the gift card with the payment card, to which the payer responds affirmatively. The payer later uses the payment card to initiate a payment, and the computer system processes the payment based on the gift card that is linked with the payment card. |
| US09864985B2 |
Transmitter and method for substantially reducing dead zones in an inductive contactless mobile payment system
A transmitter to generate a signal to be read by a reader is described. The transmitter includes a driver circuit; and at least two inductors connected to the driver circuit. The driver circuit controls the current flow through the inductor and the current flow results in a signal such that the signal strength is above the detection limit of the reader for each of the inductors which may have at least one null region. Additionally, the inductors are positioned such that the null regions of the inductors do not overlap. |
| US09864980B2 |
Automatic processing of foreign currency tenderings
Various embodiments herein each include at least one of systems, methods, software, and data flows for automatic processing of foreign currency tenderings, such as on Point-Of-Sale (POS) terminals and other devices and system on which currency transactions may be conducted. One method embodiment includes receiving an image of an image flow captured by a camera of a scanner and determining whether a currency item is present in the image. In such embodiments, when a currency item is determined to be present in the image, sending a data representation of a received currency denomination and value as a currency tender input to a process of a POS terminal. |
| US09864976B2 |
Transferring funds between financial accounts of two accountholders
A facility for initiating a funds transfer operation is described. The facility displays on a mobile device identity verification information for other people each associated with another mobile device within a maximum distance. For example, the displayed identity verification information may be a picture of the person. The user may select one of these in order to initiate a funds transfer operation to the selected person. |
| US09864970B2 |
Shielded user-portable container configured to inventory items
The present disclosure is directed at systems, methods, and apparatus for precisely inventorying items placed within a user-portable container. The system may comprise one or more interrogators configured to repeatedly send interrogation signals to detect tagged items placed within the portable container by a user. The system may also comprise one or more readers configured to detect response signals produced by the tagged items in response to the repeated interrogation signals. The system may also comprise a communication interface configured to provide information regarding the detected response signals to an adjunct processor configured to analyze the signals and determine whether they originate from items within the user-portable container, as well as to maintain an inventory of items within the portable container. |
| US09864967B2 |
Machine-readable delivery platform for automated package delivery
A user requests a package delivery from a package delivery system. The package delivery system provides the user with a machine-readable code for display at the delivery location. An aerial delivery device receives, from the package delivery system computing device, information associated with the delivery location of the package. The information comprises information matching the information in the machine-readable code associated with the delivery location and a delivery address. The delivery device secures the package for transporting to the delivery location and transports the package to the delivery address. The delivery device locates the machine-readable code on a display at the delivery address and verifies that the information from the machine-readable code is associated with the package. The delivery device deposits the package on the display. |
| US09864964B2 |
Job monitoring support method and information processing apparatus
An information processing apparatus includes a memory and a processor. The memory stores job information including execution order information of a plurality of jobs. With respect to each of the plurality of jobs, the processor calculates the number of preceding jobs that hand over processed data to the job and the number of succeeding jobs that take over the processed data from the job, on the basis of the job information. The processor generates a graph that selectively displays selected jobs from the plurality of jobs on the basis of the number of preceding jobs and the number of succeeding jobs. |
| US09864962B1 |
Minimum suggested rate picking
A pick rate planning system is utilized to determine pick rates needed for the picking of items in a materials handling facility. Critical pull times (“CPTs”) are determined which indicate times by which items must be picked from inventory. Multiple pick rates that overlap in time are made to have an overall total pick rate that is relatively constant, so as to avoid spikes or other undesirable fluctuations in the overall total pick rate, which improves labor planning. Pick rates for later CPTs are designated as being for that CPT or any earlier CPTs, and all of the pick rates are designated as minimum suggested pick rates. These designations provide the picking scheduler with greater flexibility that results in higher pick density and productivity. |
| US09864956B1 |
Generation and use of trained file classifiers for malware detection
A method includes training a file classifier from one or more n-gram feature vectors received from a plurality of binary files as input, where the one or more n-gram vectors represent the occurrences of character pairs in printable characters within the file or characters representing the informational entropy sequence of the file. Another method also includes generating, by the file classifier, output including classification data associated with the file based on the one or more n-gram vectors, where the classification data indicates whether the file includes malware. |
| US09864955B2 |
Performing an operation during inferred periods of non-use of a wearable device
A wearable computing device is described that predicts, based on movement detected, over time, by the wearable computing device, one or more future periods of time during which the wearable computing device will not be used. Responsive to determining that the wearable computing device is not being used at a current time, the wearable computing device determines whether the current time coincides with at least one period of time from the one or more future periods of time. Responsive to determining that the current time coincides with the at least one period of time, the wearable computing device performs an operation. |
| US09864947B1 |
Near field communication for a tobacco-based article or package therefor
An apparatus embodied as a tobacco-based article including a consumable material that is tobacco, or that is made, derived from or incorporates tobacco, or as a package for one or more of the tobacco-based article or the consumable material, includes a housing and near field communication (NFC) tag. The housing is structured to retain the tobacco-based article or the consumable material. The NFC tag is configured to store or generate information related to the article or the material. The NFC tag is coupleable with a NFC reader to enable wireless transfer of the information to a computing device to enable authentication of the apparatus, or display or storage of the information, at the computing device or a service platform in communication with the computing device. |
| US09864942B2 |
Portable table number device and table number system
A portable table number device, comprising a housing having a bottom side with an outer edge arranged to rest on a table surface, said housing comprising a power source, an RFID reader arranged to detect an RFID table ID tag on or under said table surface, computer memory means comprising a table number device ID, wireless communication means arranged to wirelessly communicate a detected RFID tag table ID by said RFID reader together with said table number device ID to an external table number receiving device, a surface proximity sensor, such as a light sensor or micro-switch arranged in a recessed portion of said housing within said outer edge, said surface proximity sensor having a first state wherein no proximate surface is detected and a second state wherein a proximate surface is detected, said second state occurring if said bottom side of said housing is placed on said table surface, and power management means arranged to keep said RFID reading device in a sleep mode wherein no or relatively little power is used until the state of said surface proximity sensor changes from said first state to said second state, to power up said RFID reader temporarily for a period of time if the state of said proximity sensor changes from said first state to said second state, said period of time being long enough to enable said RFID reader to identify an RFID tag and transmit it to said external table number receiving device, and to put said RFID reader in said sleep mode after said period of time lapses. |
| US09864938B2 |
Information processing apparatus, information processing method, and non-transitory computer readable medium
An information processing apparatus includes an abnormal status detector and a display controller. The abnormal status detector detects an abnormal status of an image forming apparatus. The display controller controls, when the abnormal status detector detects the abnormal status, such that operation procedure images which are associated with plural operations defined in advance as operations to be performed by an operator in the abnormal status of the image forming apparatus are displayed on a display on which an operation screen regarding the image forming apparatus is displayed. When receiving a first operation which corresponds to a first operation procedure image displayed on the display, the display controller displays a second operation procedure image which corresponds to a second operation which is defined as the operation next to the first operation among the plural operations. |
| US09864937B2 |
Image recording apparatus, method of controlling image recording apparatus, and storage medium
Provided is an image recording apparatus, including: a recording unit recording an image on a recording sheet; a conveying unit conveying a plurality of recording sheets in an overlapping state to the recording unit; and a setting unit setting an overlapping amount so that the image is prevented from being printed on a region of a predetermined range which includes a boundary between an overlapping portion, in which a subsequent sheet and a preceding sheet overlap each other, and a non-overlapping portion, in which the subsequent sheet and the preceding sheet do not overlap each other. |
| US09864930B2 |
Clustering technique for optimized search over high-dimensional space
An approach is provided in which a knowledge manager locates centroids in a high-dimensional vector space that are closest to a new image feature set and performs nearest neighbor searches on feature sets included in clusters corresponding to the located centroids. The knowledge manager then selects feature sets closest to the new image feature set based on the nearest neighbor searches and in turn, marks images corresponding to the selected closest features sets as similar images to a new image corresponding to the new image feature set. |
| US09864926B2 |
Search method, search program, and search device
A search device according to an embodiment maps a feature vector onto a hyper-sphere on the basis of parameters which include an intersection and a distance, with the intersection at which an m-dimensional feature space and a straight line passing through the hyper-sphere present in a space greater in dimension than m intersect and the distance being from the north pole of the hyper-sphere to the feature space. In this case, the search device searches for the parameters which allow the positions of feature vectors mapped onto the hyper-sphere to be concentrated on a predetermined hemisphere of the hyper-sphere. |
| US09864919B2 |
Including information signals in product packaging and other printer media
The present disclosure relates generally to data hiding for retail product packaging and other printed objects. One embodiment embeds an information signal in a spot color for product packaging. The spot color is screened, and overprinted with process color tint. The tint is modulated prior to overprinting with optimized signal tweaks. The optimization can include consideration of a detector spectral dependency (e.g., red and/or green illumination). Many other embodiments and combinations are described in the subject patent document. |
| US09864918B2 |
Predicting vehicle movements based on driver body language
Systems, methods, and devices for predicting driver intent and future movements of a human driven vehicles are disclosed herein. A system for predicting future movements of a vehicle includes a camera system, a boundary component, a body language component, and a prediction component. The camera system is configured to capture an image of a vehicle. The boundary component is configured to identify a sub-portion of the image corresponding to an area where a driver of a vehicle is located. The body language component configured to detect a driver's body language. The prediction component configured to predict future motion of the vehicle based on the driver's body language detected by the body language component. |
| US09864913B2 |
Device and method for safeguarding an automatically operating machine
A device for safeguarding a monitoring area in which an automatically operating machine is arranged, having a camera system for monitoring the monitoring area, a configuration unit for defining at least one protection area within the monitoring area, and an analysis unit for triggering a safety-related function. The camera system supplies camera images of the protection area and the analysis unit analyzes whether a foreign object is present in the protection area or penetrates into the protection area. The analysis unit is configured to classify a foreign object, which is present in the protection area or penetrates into the protection area, by analysis of the camera images, to determine on the basis of one or more features characteristic of welding sparks whether the foreign object is a welding spark. The analysis unit triggers the safety-related function if the foreign object has not been recognized as a welding spark. |
| US09864907B2 |
Microform word search method and apparatus
A digital imaging system for real-time searching for expressions that appear on a microform medium, the system comprising a computer including a processor, a display, a temporary memory, and a non-volatile memory, and a digital microform imaging apparatus including a controller and an area sensor generating a real-time digital microform image of the microform medium. The controller is in communication with the area sensor and receives the image. The controller is in communication with the processor and outputs the image to the processor that temporarily stores the image in the temporary memory. The processor uses the image output by the controller to drive the display with the image being generated by the area sensor in real-time. The processor searches the image used to drive the display for instances of a search expression, the processor visually distinguishing identified instances of the search expression on the display. |
| US09864905B2 |
Information processing device, storage medium storing information processing program, information processing system, and information processing method
An example information processing system includes a camera. The information processing system calculates, based on a camera image obtained by the camera, a position or a direction of an object (e.g., a hand of a user) included in the camera image. The information processing system instructs an output device to produce an output in accordance with the position or the direction of the object. The information processing system displays, on a display device, a guide image including a range image representing a range and an indicator image whose position or direction changes in accordance with a change in the output within the range. |
| US09864903B2 |
System and method for matching faces
Disclosed herein are systems, computer-implemented methods, and tangible computer-readable media for matching faces. The method includes receiving an image of a face of a first person from a device of a second person, comparing the image of the face of the first person to a database of known faces in a contacts list of the second person, identifying a group of potential matching faces from the database of known faces, and displaying to the second person the group of potential matching faces. In one variation, the method receives input selecting one face from the group of potential matching faces and displays additional information about the selected one face. In a related variation, the method displays additional information about one or more face in the displayed group of potential matching faces without receiving input. |
| US09864899B2 |
Image processing apparatus, image processing method, and storage medium
There is provided an image processing apparatus. An image data acquisition unit acquires a plurality of image data items each containing one or more objects. A position acquisition unit acquires respective positions, in a depth direction, of a plurality of objects contained in the plurality of image data items. An object recognition unit performs, with respect to each of the plurality of objects, object recognition processing of detecting a corresponding object candidate from among a plurality of object candidates. The object recognition unit performs the object recognition processing, based on the respective positions of the plurality of objects in the depth direction, in such a manner that the closer to a front side an object is located, the more preferentially the object recognition processing of that object is performed. |
| US09864898B2 |
Feature point input assisting device, feature point input assisting method, and storage medium stored with program
To provide a feature point input assisting device that can carry out the input assistance of the feature point.A feature point input assisting device includes a processor circuitry. The processor circuitry configured to set a first feature point in an input image including a stripe pattern formed by ridge lines. The processor circuitry configured to extract a second feature point from the input image by using the first feature point. The processor circuitry configured to extract a feature point, which is the second feature point having no corresponding first feature point, as an input omission feature point candidate. The processor circuitry configured to output the input omission feature point candidate to a display device. |
| US09864897B2 |
Surface structure identification unit and circuit, identification method and electronice device
The present invention provides a surface structure identification unit including photoelectric sensing element, first and second signal input terminals, trace line, driving module, reset module and evaluation unit. The photoelectric sensing element is connected to the first signal input terminal, and the driving module. The reset module is configured to be connected to the driving module in a reset stage to reset the same. The control terminal of the driving module is configured to be connected to the second signal input terminal and the trace line in a charging stage and disconnected from the trace line in a detecting stage; the first terminal of the driving module is configured to be disconnected from the first signal input terminal in the charging stage and connected to the first signal input terminal in the detecting stage; and a second terminal of the driving module is connected to the trace line. |
| US09864894B2 |
Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one demodulated value for processing by a channel engine. The channel engine may generate a capacitance result value that is based, in part, on the demodulated value and is stored in a memory. |
| US09864892B2 |
Increasing information size in two-dimensional barcodes
Decoding or encoding information in a two-dimensional barcode, the barcode comprising an orientation pattern and a payload data pattern both being compiled of first and second type elements. The decoding or encoding involves a two-dimensional transformation applying at least to the payload data pattern in connection with second information that forms together with first information the information encoded in the two-dimensional barcode. |
| US09864891B2 |
Automatic print speed control for indicia printer
A label printing device and method include a proportional-integral-derivative controller and a variable speed printer motor. The variable speed printer motor is connected to the proportion-integral-derivative controller, and has an automatically optimized printing speed determined by a print duration history of one or more previously completed print jobs. |
| US09864889B2 |
Authenticity tag and methods of encoding and verification
An object is associated with an identifier which is detectable on the object. The identifier may be an inherent characteristic of the object itself or its packaging, or it may reflect a random or arbitrary value which may then be disposed on the object or its packaging deliberately in a readable form for the purposes of the invention. Additionally, there is disposed a machine readable code comprising a URI incorporating a representation of the object identifier encoded according to one of a number of predefined encoding methods (algorithm and associated parameters), and an encoding identifier, specifying the encoding method used. A reader can read the machine readable code, decode it according to specified encoding method, and prepare a representation of it for comparison with the characteristic reflecting the object identifier. The machine readable code and the characteristic reflecting the object identifier may be readable for example by optical, tactile, radio, olfactive or acoustic mechanisms. The URI may additionally be defined to call a local resource adapted to process the code. The URI may additionally be defined to specify a web site. |
| US09864887B1 |
Energizing scanners
A device, mobile system, and method for scanning a source of information are described. During scan operations, the scanning device is energized by an on-board supercapacitor power source and is worn upon an extremity of a user. The scanning device is operable for scanning the information source, accessing the information from the source based on the scanning, and generating a signal comprising data related to the accessed information. The generated scan data signal is transmitted for processing to a base station, which is worn remotely from the scanning device, for example on the user's belt. |
| US09864882B1 |
Energy harvesting for battery-less RFID tag devices with internal transmitters
A battery-less RFID tag device with an RFID antenna assembly and RFID transmitter, which harvests power from an RF source is disclosed. The RF source can be a mobile phone, and embedded system, and the like. The RFID device can include an energy harvesting component, an energy conversion component, an energy storing component, a non-transitory memory, a controller, and an RFID transmitting component. The energy harvesting component can inductively harvest energy from RF transmissions, which charges a capacitor to power other RFID device components, including the RFID transmitter. In one embodiment, the battery-less RFID tag device can be utilized in conjunction with a mobile phone for vehicle toll payments, which are RFID based. |
| US09864881B2 |
Method and apparatus to mitigate multipath in RFID
A distance between at least one antenna of an interrogation system and a transponder, such as an RFID tag, is determined based on derivatives with respect to frequency of the phase and the signal strength of responses transmitted by the transponder and received at the at least one antenna. The derivatives of the phase and the signal strength facilitate compensating for sources of multipath interference. Determining changes in distance may further facilitate determining location, speed, or bearing of the transponder by the interrogation system. |
| US09864878B2 |
Event log tamper detection
A computer implemented method includes generating, by a processor, a first event record in response to an event being performed by a computer; and generating, by the processor, a second event record in response to the first event record being generated, wherein the second event record comprises a signature corresponding to the first event record. |
| US09864877B1 |
Online repository for personal information and access of information stored therein
A first party's personal information is stored in a secure online database with security levels associated at granular level. A second party's request to access the first party's personal information is verified and a portion of the first party's personal information is sent to the second party based on the second party's request meeting certain conditions or criteria. |
| US09864874B1 |
Management of encrypted data storage
A data storage management process is directed to aspects of managing encrypted data via data storage volumes in conjunction with a service provider computer network that hosts virtual machine instances. A volume can be created and configured for managing encrypted data with an encrypted version of a volume key. The volume can be attached to a virtual machine instance such that the virtual machine instance accesses the volume in a transparent fashion based on the volume key. Encrypted data specific to the volume can be copied across multiple regions of data storage each associated with distinct encrypted versions of a volume key corresponding to the volume. |
| US09864872B2 |
Method for managing privacy of digital images
A captured digital image is stored in memory together with metadata derived from a location signal only if the location metadata is determined not to be within one or more predefined exclusion zones. A GPS receiver module can be implemented to obtain the location signal. |
| US09864869B2 |
Information processing apparatus configured to control access to content, control method therefor and system
A system in which a communication apparatus and first and second information processing apparatuses are communicably connected, comprises a comparison unit which compares a first disclosure range set in the first information processing apparatus with a second disclosure range set in the second information processing apparatus, and a notification unit which sends a notification to the communication apparatus. The information processing apparatuses distributes the content to a third-party terminal included in a disclosure range decided based on the result of the comparison. |
| US09864867B2 |
Secure persistent communication between related domains using cookies
A 1st domain makes a request to a 2nd domain using a URI including the name of the 2nd domain, a public path for the domains, and a cryptographically secure path generated by the 1st domain. The 2nd domain makes a request to the 1st domain using a URI including the name of the 1st domain, the pre-defined public path, and the cryptographically secure path. The 1st domain or the 2nd domain sets a cookie including a message (the cookie's path scope includes the pre-defined public path and the cryptographically secure path, the cookie's domain scope includes all sub-domains of the nearest common ancestor for the 1st and 2nd domains), and makes a request to the other domain using a URI including the name of the other domain, the pre-defined public path, and the cryptographically secure path, which causes a web browser to send the cookie to the other domain. |
| US09864858B2 |
Technologies for managing security threats to a computing system utilizing user interactions
Technologies for managing security threats on a computing system include detecting a security threat to the computing system, determining a plurality of mitigation scenarios to employ on the computing system to mitigate the security threat, and implementing the plurality of mitigation scenarios. Each mitigation scenario includes one or more threat mitigation actions to be taken by the computing system, one or more response systems of the computing system to perform the threat mitigation actions, and a temporal sequence in which the threat mitigation actions are to be taken. The results of each mitigation scenario is evaluated and a validated mitigation scenario is determined based on the results. A user of the computing device may be subsequently trained or habituated to mitigate the security threat by requesting interaction from the user during the implementation of the validated mitigation scenario in response to a threat scenario designed to replicate the security threat. |
| US09864857B2 |
Fault detection during operation of multiple applications at a mobile device
A particular method includes receiving authentication information at a device. The method also includes determining, by the device, whether a user is authenticated based on the authentication information. The method further includes executing, by the device, a first virtual machine in response to determining that the user is authenticated. The first virtual machine has access to sensitive information. The method also includes executing, by the device, a first application on the first virtual machine. The method further includes determining, by the device, whether execution of an instruction associated with a second virtual machine would result in a fault. The method also includes, in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction and allowing the second virtual machine to fail without adversely affecting the first virtual machine. |
| US09864853B2 |
Enhanced security mechanism for authentication of users of a system
A method and structure for authenticating users of a system that prevents theft of passwords and re-use of passwords. The method and structure use one-time passwords and a Secure CPU technology that cryptographically protects a software module known as a Secure Object from other software on a system. The method and structure generate and validate one-time passwords within Secure Objects and use a communications mechanism to securely communicate passwords or information used to generate passwords that makes use of cryptography and the protected and unprotected regions of a Secure Object to provide strong end-to-end security. |