最新美国发明专利
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US09755864B1 Fractionally spaced adaptive equalizer with non-integer sampling
An apparatus for performing fractionally spaced adaptive equalization with non-integer sub-symbol sampling has an adaptive equalizer that receives a continuous stream of input data having a non-integer, fractional delay between consecutive samples at a non-integer, sub-symbol rate and outputs a stream of equalized data based on tap weights of taps of the adaptive equalizer that are spaced at an interval corresponding to the non-integer, sub-symbol rate. The tap weights are updated independently of the fractional delay between consecutive samples of the input data using an error signal. An equalizer output alignment component downstream of the adaptive equalizer aligns the stream of equalized data with a corresponding transmitted symbol.
US09755857B2 Avionic ethernet network and method of transmitting blocks of data in the network
An avionics switched full-duplex Ethernet communication Arinc 664p7 network (100) includes at least two independent elementary networks (N1, N2). Each elementary network includes one or more end systems (ESI) suitable to act as source end systems for data frames transmitted over the network, and one or more end systems (ES4) suitable to act as destination end systems for such data frames. Each elementary network further includes a switching function block (SW1, SW2) connected between the source (ESI) and destination (ES4) end systems. The Ethernet network is has one of the source (ESI), destination (ES4) end systems and the switching function block (SW1, SW2) includes timers (204) suitable to generate a common piece of timing information to be sent to the other devices of the elementary network in-order to enable the transmission of the data frames over the elementary network by one of the source end systems (ESI).
US09755856B1 Method, apparatus and computer program to provide access to client records and data resources
A method, computer program and apparatus are disclosed that include accessing client data records, such as, medical records. The method may include receiving a data file at a server sent from at least one client and including client requirements. The method may also include storing the received data file locally at the server, executing an application that scans the server to determine if any new data files have been received. The method may also include storing the copied data file in a data folder stored in a file cluster, updating a table stored in a database to indicate that a new file has been stored, deleting the locally stored file from the server, and moving files specified by the client requirements from an export folder of the file cluster to the server so that the at least one client may access the exported files.
US09755855B2 VPN implementation method and PE device
A VPN implementation method and a PE device are provided. The method includes: sending VPN topology information of a local end to a PE device at a peer end, and receiving VPN topology information of the peer end sent by the PE device at the peer end; enabling, according to the VPN topology information of the local end and the VPN topology information of the peer end, the local end and the peer end to select a jointly supported topology; and connecting VPN members by using the jointly supported topology, so as to implement the VPN. A VPN in a multi-topology environment may be implemented, and service quality of a multi-topology VPN may be improved.
US09755853B2 Methods, systems and apparatus for the control of interconnection of fibre channel over ethernet devices
Systems, apparatus and methods are provided for interconnection of one or more Fibre Channel over Ethernet (FCoE) devices. The system preferably comprises a virtualized or virtual server which in turn comprises a virtual machine having an FCoE device interconnection apparatus controller, a virtual switch, the virtual switch being coupled to the FCoE device interconnection apparatus controller, and a network interface. The network interface is coupled to the virtual switch, which in turn couples to an Ethernet fabric. A first Ethernet link couples the network interface to the Ethernet fabric. One or more Fibre Channel over Ethernet (FCoE) devices are coupled to the Ethernet fabric via Ethernet links.
US09755852B2 Power over ethernet to USB adapter
A power adapter comprising a POE connector for receiving electrical power from the power lines of a POE cable, a transformer circuit and a USB connector for delivering electrical power to a USB powered device, wherein a POE cable provides power to the USB powered device. The power adapter can have a POE receptacle for receiving an Ethernet plug, to receive the POE power, and a USB receptacle to receive a USB plug from a USB powered device, or dedicated wires from one or more of the POE power supply and/or the USB powered device.Also, a method for providing USB power comprising the steps of running a POE cable from a power source to an adapter, adapting the POE power from the POE cable to USB power and making the USB power available to one or more USB powered devices.
US09755846B2 Leader device selection in control clusters using shared VLAN
A method for leader device selection in a control cluster using a shared virtual local area network (VLAN) is provided in the illustrative embodiments. A broadcast Hello packet is received from a sender virtual device over the VLAN at a first virtual device. When the first virtual device satisfies a partnership criterion specified in the Hello packet, a first ranking of the first virtual device is evaluated to be higher than a ranking of a sender virtual device. A first Live packet is unicast over the VLAN to the sender virtual device and a leadership role in the control cluster is taken by the first virtual device. The sender virtual device is caused to stop a broadcasting operation at the sender virtual device. A second Hello packet is broadcasted from the first virtual device over the VLAN.
US09755844B2 Techniques to transform network resource requests to zero rated network requests
Techniques to transform network resource requests to zero rated network requests are described. Some embodiments are particularly directed to techniques transform network resource requests on a cellular network to zero rating by replacing the destination of the request with a zero-rated source for the network resource. In one embodiment, for example, an apparatus may comprise a data store and a network access component. The data store may be operative to store a plurality of zero-rating rewrite rules. The network access component may be operative to receive a network request from an application component on the mobile device, the network request for access to a network resource; compare the network resource to the plurality of zero-rating rewrite rules to identify a zero-rating rewrite rule matching the network resource; transform the network request to a zero-rated network request for the network resource using the identified zero-rating rewrite rule; and perform the zero-rated network request. Other embodiments are described and claimed.
US09755841B2 Method, apparatus and system for security application for integrated circuit devices
At least one method, apparatus and system disclosed involves providing a restricted access protocol for accessing a memory device. A first memory portion of a memory device is selected for providing an access confirmation. At least one of setting or resetting of memory cells of the first memory portion is performed. A first voltage is provided for switching the memory cells. The first voltage is associated with a predetermined switching probability. A first input signal comprising at least one address associated with the memory cells is provided. A first responsive signal is received in response to the input signal. The first responsive signal comprises data relating to the state of the memory cells. An access key is provided for the access confirmation based upon a relationship between the first input signal and the first responsive signals for providing an access key.
US09755837B2 Apparatus and method for sponsored connectivity to wireless networks using application-specific network access credentials
At least one feature pertains to a method operational at a user device that includes receiving, from an application service provider, an application-specific certificate associated with at least one application service provided by the application service provider. The method also includes determining that a wireless communication network provides application-specific access to the application service provided by the application service provider, and transmitting a registration request including the application-specific certificate to the wireless communication network for authentication of the user device. The application-specific certificate includes a user device public key. The method further includes performing authentication and key agreement with the wireless communication network, and communicating with the application service after authentication and key agreement is successfully performed. In one aspect, authentication and key agreement with the network is performed directly between the user device and the network and independent to the application service provider.
US09755836B2 Identifying and locating authenticated services using broadcast encryption
Provided are techniques to enable, using broadcast encryption, a device to locate a service offered by a server with the knowledge that the service offered by the server is a trusted service. A signed enhanced Management Key Block (eMKB) includes a trusted service locator (TSL) that includes one or more records, or “trusted service data records” (TSDRs), each identifying a particular service and a corresponding location of the service is generated and transmitted over a network. Devices authorized to access a particular service parse the eMKB for the end point of the service, connect to the appropriate server and transmit a request.
US09755834B1 Providing cross site request forgery protection at an edge server
A request from a computing device for accessing a resource is received by an edge server, where the request includes a cookie containing a first token value and a second token value. The edge server validates the first token value and a second token value using a third token value generated using hashing algorithm with a secret key and one or more other values. The edge server then compares the received token values with the third token value. When the request is validated, the edge server retrieves the request resource.
US09755833B2 Identification information management system, method of generating and managing identification information, terminal, and generation and management programs
An identification information management system according to the present invention comprises a plurality of terminals communicable with servers and a site management apparatus which manages site containing the terminals. The terminal has an identification information processing unit which assuming that a one-way hash function is f(x) and a terminal-unique ID is a, generates values x satisfying a conditional equation f(x)=a as identification information. When acquiring multiple items of identification information, the site management apparatus substitutes the identification information as the value x into f(x) and decides whether f(x)=a is satisfied, thereby deciding the terminals.
US09755830B2 Dynamic seed and key generation from biometric indicia
Generating a seed and/or a key from live biometric indicia, such that all the information necessary for generating the seed and/or the key is not stored, is provided. A method comprises receiving and enrolling a biometric template from a user; assigning an optimization value to the enrolled biometric template; encrypting an item of test data using the optimization value, such that the optimization value is an encryption seed; storing the encrypted item of test data on the storage medium; destroying the encryption seed after encrypting the item of test data; receiving a live biometric template; comparing the templates and determining an interval based on a probability that the templates are specific to the same user; iteratively testing values within the interval to identify the value in the interval for decrypting the encrypted item of test data; and generating the key using the seed.
US09755829B2 Generation of cryptographic keys
Method for generating a pair of public and private cryptographic keys in the additive group of integers modulo n, where n is the product of two prime numbers p and q, the method including the following steps: calculating a public exponent e for said public key, and calculating a private exponent d for said private key from said public exponent and said public modulus, where d·e=1 mod λ(n), λ(n) being the least common multiple between p-1 and q-1, characterized in that the method furthermore comprises a step: of checking to check that λ(n)=0 mod (p-1) and λ(n)=0 mod (q-1).
US09755825B2 Device authentication and secure channel management for peer-to-peer initiated communications
A method and system for providing secure access to a device initiating communications using a peer-to-peer signaling protocol, such as a SIP or H.323. In a device registration phase, the device contacts a secure access server, and authenticates to the secure access server by providing an identification, such as its factory ID. The secure access server then issues a device ID and private key to the authenticated device. A client can then initiate a further communication session and be authenticated by the secure access server. The secure access server returns the device identification and the device's public key to the client. The client and device can then perform a symmetrical key exchange for their current communication session, and can communicate with appropriate encryption. The device's private key can be set to expire after one or more uses.
US09755824B2 Power line based theft protection of electronic devices
Technologies for establishing and managing a connection with a power line communication network include establishing a communication connection between an electronic device and a security server. A default device encryption key associated with the electronic device is changed to correspond with a new device encryption key of the security server. Thereafter, the electronic device may only join a power line communication network of a particular security server using a network membership key, which is encrypted with the device encryption key that the particular security server associates to the electronic device. The electronic device contains a circuit interrupt to interrupt a circuit of the electronic device if the electronic device is not able to successfully decrypt the network membership key.
US09755814B2 Method of determining transport block size and apparatuses thereof
The present disclosure relates to a method and apparatus for determining a Transport Block Size (TBS) in a wireless communication system, and more particularly, to a method and apparatus for determining a TBS table in association with 256 QAM. Particularly, a method for a base station to transmit data includes receiving Channel State Information (CSI) from a User Equipment, determining a Transport Block Size (TBS) value based on a TBS table including indices corresponding to the 256QAM modulation scheme and the number of allocable Physical Resource Block (PRB) pairs, and transmitting data using the TBS value.
US09755813B2 Method and apparatus for controlling deactivation timer of cell included in tag
The present specification proposes a scheme for controlling a deactivation timer of a cell. More specifically, the present specification proposes a method of controlling a deactivation timer of a cell in a mobile communication system. The method includes: configuring, at a user equipment (UE), a first deactivation timer of a first cell and a second deactivation timer of a second cell, wherein the first cell and the second cell belong to a same timing advance group (TAG); if the first deactivation timer of first cell expires, checking, at the UE, whether uplink timing of the same TAG is required to be maintained; and if the uplink timing of the same TAG is required to be maintained, restarting, at the UE, the first deactivation timer of the first cell.
US09755810B2 Precoder resource bundling information for interference cancellation in LTE
Methods, systems, and devices are described for interference cancellation/interference suppression (IC/IS) of neighbor cell transmissions. A UE may receive a downlink transmission from a base station and also receive interfering signals from one or more neighboring base stations. The UE may be configured to perform IC/IS operations on the interfering signals. In order to enhance IC/IS operations, the UE may evaluate whether resource bundling is used for the interfering signals. The UE may modify IC/IS operations for one or more subframes responsive to the evaluation. Modifying IC/IS operations may include, for example, using information related to the bundling at the neighboring base station(s) to cancel the interfering signals from the base station(s).
US09755807B2 Uplink channel estimation using a signaling channel
Techniques for efficiently deriving uplink channel estimates without consuming much additional uplink resources are described. A user equipment (UE) may send a request for uplink resources on a request channel (REQCH) whenever the UE desires to transmit data on the uplink. The UE may send the REQCH on a set of subcarriers and from multiple antennas, e.g., send REQCH data on data subcarriers and pilot on pilot subcarriers. A Node B may receive the request, estimate the complex channel gains for the pilot subcarriers based on received pilot symbols, and coherently demodulate received data symbols based on the channel gain estimates. The Node B may estimate the complex channel gains for the data subcarriers based on demodulated data symbols and derive a channel estimate for each UE antenna based on the channel gain estimates for the pilot and data subcarriers. The Node B may use the channel estimates for MIMO scheduling, subband scheduling, and rate selection.
US09755805B2 Communication apparatus and communication method thereof
This invention is directed to a terminal apparatus capable of preventing the degradation of reception quality of control information even in a case of employing SU-MIMO transmission system. A terminal (200), which uses a plurality of different layers to transmit two code words in which control information is placed, comprises: a resource amount determining unit (204) that determines, based on a lower one of the encoding rates of the two code words or based on the average value of the reciprocals of the encoding rates of the two code words, resource amounts of control information in the respective ones of the plurality of layers; and a transport signal forming unit (205) that places, in the two code words, the control information modulated by use of the resource amounts, thereby forming a transport signal.
US09755791B2 Eye diagram estimation, based on signal statistics collection
Method and system for estimating an eye diagram display of a real signal passing through a data communication channel, according to which decoded symbols of the transmitted real signal are captured, along with their corresponding ADC sample values and sampled at a rate of 1 SPS or more. Then statistic data is collected for each captured sequence of bits/symbols for each particular phase and a synthetic signal is created, based on the collected statistics, using a signal generator that produces samples by randomly creating a bit stream by generating a corresponding one or more samples for any symbol sequences in the bit stream according to the number of collected phases. Interpolation on the corresponding samples is then performed, according to required display time resolution and the synthetic signal is then displayed as a two-dimensional eye diagram image, representing all the statistics collected at all phases.
US09755789B2 Systems and methods for dynamic packet duplication in a network
Systems and methods are provided for facilitating communication sessions between endpoints over one or more networks. In one implementation, a method includes receiving, by at least one processor, first data indicating that a communication session has been initiated to at least one endpoint. The method also includes receiving, by the at least one processor, second data corresponding to one or more application level metrics associated with the communication session and determining, by the at least one processor, during the communication session, based on the second data, a packet duplication model for transmitting one or more data packets over one or more networks.
US09755788B2 Messages with attenuating retransmit importance
Certain data packets for transmission between a first device and a second device may have an importance that changes depending on different circumstances. After the data packet is initially communicated from the first device to the second device, if an acknowledgement is not received at the first device, the first device may retransmit the data packet. If no acknowledgement is received after a certain period of time, communication of the data packet may be considered to have a lower importance, and so additional retransmissions bay be delayed until a retransmission trigger is identified. Examples of such a trigger may be powering on of an antenna for a second different data packet transmission, or identification that a subsequent data packet was successfully received by the second device.
US09755786B2 Method of message retransmission and user equipment using the same
A method of message retransmission and a user equipment (UE) using the same are provided, which are adapted for performing a discovery procedure of the proximity service (ProSe). The UE includes a transceiver and a processor. The transceiver is used to transmit and receive a wireless signal. The processor is coupled to the transceiver and configured to perform the following steps. A first message used for an authorization request of the ProSe is transmitted through the transceiver, and a first timer is started. If a second message responding to the first message is not received through the transceiver when the first timer is expired, a second timer is started. And, the first message is not transmitted through the transceiver before the second timer is expired.
US09755781B2 Broadcast system and method for error correction using redundant data
A control device for use in a broadcast system includes a broadcast controller that controls a broadcast transmitter of the broadcast system that broadcasts broadcast signals in a coverage area for reception by terminals including a broadcast receiver and a broadband receiver, and a broadband controller that controls a broadband server of a broadband system that provides redundancy data to terminals within the coverage area. The broadband controller is configured to control the provision of redundancy data by the broadband server for use by one or more terminals which use the redundancy data together with broadcast signals received via said broadcast system for recovering content received within the broadcast signals and/or provided via the broadband system.
US09755780B2 Method and apparatus for determining modulation and coding scheme feedback in wireless local area network system
The present invention relates to a method of determining a Modulation and Coding Scheme (MCS) feedback in a Wireless Local Area Network (WLAN) system, including an MCS FeedBack (MFB) responder receiving a first frame, including a request message requesting to send the MFB, from an MFB requester and the MFB responder sending the MFB, including a recommended MCS value, to the MFB requester. The recommended MCS value is derived with reference to at least one of unsolicit type information indicative of a type of the MFB, transmit type information indicative of a transmission type of data, coding type information indicative of a coding scheme applied to the data, a group ID indicative of a group of target stations (STAs) to which the data will be transmitted, and MFB bandwidth information indicative of a bandwidth of a channel.
US09755777B2 Optical transmitter and optical transmission method
An optical transmitter includes a dummy optical source, a polarized wave beam coupler, and an auto gain control (AGC)-system amplifier. The dummy optical source outputs, out of an optical signal in which an optical path signal and an optical packet signal are mixed, a dummy signal having a wavelength identical to that of the optical packet signal. The polarized wave beam coupler multiplexes the dummy signal with the optical signal so that the dummy signal is orthogonal to the optical signal so as to output an output signal. The AGC-system amplifier inputs the output signal, and amplifies the output signal with a predetermined amplification factor corresponding to a power difference between input power and output power of an optical amplifier.
US09755774B1 Master/slave negotiation associated with a synchronous ethernet network
A device may determine a link master/slave relationship for an Ethernet link associated with a connection between a component of the device and a component of another device. The device may determine that Synchronous Ethernet (SyncE) is to be enabled on the Ethernet link. The device may identify the component of the device as a SyncE slave or a SyncE master associated with enabling SyncE on the Ethernet link. The device may provide an indication that the component of the device has been identified as the SyncE slave or the SyncE master. The device may determine a SyncE master/slave relationship associated with enabling SyncE on the Ethernet link. The SyncE master/slave relationship may supersede the link master/slave relationship without altering the link master/slave relationship. The device may cause the component of the device to recover a clock based on the SyncE master/slave relationship rather than the link master/slave relationship.
US09755773B2 Receiving apparatus
A receiving apparatus comprises: a plurality of tuners; and a controller that controls a frequency of a local oscillation signal from each tuner such that a frequency of a synthetic signal generated by multiplying the local oscillation signals from the plurality of tuners by each other does not fall in a frequency band of a channel selected by each tuner. Deterioration in reception quality due to the multiplication of the local oscillation signals is prevented.
US09755772B1 Vehicle communication system for receiving frequency modulation and digital audio broadcast radio frequency bands
An antenna system for a vehicle that includes at least one radio frequency (RF) antenna that receives both a digital audio broadcasting (DAB) RF broadcast and a frequency modulation (FM) RF broadcast. A single amplifier coupled to one or more antennas is used to process both the DAB and FM broadcasts.
US09755770B2 Method, device and system of encoding a digital interactive response action in an analog broadcasting message
Disclosed are a method, a device and a system of generation of a modified digital media file based on encoding of a digital media file with decodable data such that the decodable data is indistinguishable through a human ear from a primary audio stream. In one embodiment, a method includes validating a user as a publisher, associating a response action to a message of the user, using a processor and a memory, generating a unique identifier through a hash function applied to the response action, encoding a digital media file with a decodable data using the unique identifier such that the decodable data is indistinguishable from a primary audio stream through a human ear, and generating a modified digital media file based on the encoding of the message with the decodable data such that the decodable data is indistinguishable from a primary audio stream through the human ear.
US09755769B2 Method for estimating a radioelectric propagation channel
A method estimates a channel for radioelectric propagation between a transmitter and a receiver. The transmitter transmits a signal including frames that each use N1 frequency subcarriers, over each of which N1 symbols are transmitted, wherein, among the set of symbols, certain symbols, referred to as pilot symbols, are known to the receiver. The method implemented in the receiver includes; determining an overall intermediate covariance matrix M2 of the channel that embodies a time profile of the channel, which profile is symmetrical and centered on the time synchronization position, and a frequency profile of the channel, which profile is symmetrical and centered on the frequency synchronization position; calculating a vector for an intermediate channel C on the basis of the predetermined overall intermediate covariance matrix M2; and estimating the channel on the basis of the calculated vector for the intermediate channel C′.
US09755768B2 Method for measuring channel and interference in wireless communication system
Disclosed in the present invention is a method for user equipment performing a measurement in a wireless communication system. More particularly, the method comprises the steps of: receiving, from a network, information related to measuring resource combination; grouping into one time domain measurement resource group a plurality of time domain measuring resources of a time domain by using the information related to the measuring resource combination; and performing the measurement with the assumption that identical precoding is applied to or identical interference occurs in the time domain measurement resource group, wherein the information related to the measurement resource combination includes information related to the number of the plurality of time domain measurement resources.
US09755765B2 Magnetic antennas for ultra low frequency and very low frequency radiation
A communication system and a method of fabricating a communication system are described. The communication system includes a transmit antenna including two or more symmetric coils wound around a closed-loop magnetic transmitter core, the transmit antenna configured to transmit an outgoing signal of very low frequency (VLF) or ultra low frequency (ULF) energy. The communication system also includes a receive antenna including two or more coils formed from two or more wires wound around a closed-loop magnetic receiver core, the receive antenna configured to receive transmitted VLF or ULF energy as an incoming signal. The communication system also includes a processor to process the outgoing signal and the incoming signal.
US09755762B2 Optical signal recognition method and apparatus
An optical signal recognition method comprises: initializing a recognition apparatus; acquiring optical source voltage values in an acquisition channel to obtain a group of optical source voltage values; comparing the group of optical source voltage values with a comparison threshold, and converting the group of optical source voltage values into optical data; when the optical data is different from optical data obtained in a previous conversion, continuing to acquire optical source voltage values in the acquisition channel, converting a group of optical source voltage values into optical data, and sequentially storing the optical data in a conversion array; when a preset quantity of optical data in the conversion array is different, deleting optical data stored earliest in the conversion array, continuing to acquire optical data and sequentially storing the optical data in the conversion array; and when all optical data in the conversion array is the same, setting frame data as optical data in the conversion array, and returning the frame data. In the present invention, a synchronization signal is canceled, thereby improving the transmission quality and the transmission speed.
US09755753B2 Tunable U-laser transmitter with integrated Mach-Zehnder Modulator
According to the present invention, a monolithically integrated laser 102, also referred to herein as a U-laser 102, or integrated dual optical emission laser 102, having a first optical emission 104 and a second optical emission 106 where both the first and second optical emissions 104, 106 of the monolithically integrated laser 102 are in optical communication with a modulator 108 or other device is provided. The integrated dual emission laser 102 can be formed with a light bending portion 134 in variety of configurations including a waveguide in the form of a U-shape, or total internal reflection (TIR) mirrors, curved waveguides, and free-space etched gap mirrors. The integrated dual optical emission laser 102 can also have two laser gain sections 130, 148, one on each arm of the laser 102 to control gain.
US09755740B2 Receivers for optical narrowcasting
Systems and methods for optical narrowcasting are provided for transmitting various types of content. Optical narrowcasting content indicative of the presence of additional information along with identifying information may be transmitted. The additional information (which may include meaningful amounts of advertising information, media, or any other content) may also be transmitted as optical narrowcasting content. Elements of an optical narrowcasting system may include optical transmitters and optical receivers which can be configured to be operative at distances ranging from, e.g., 400 meters to 1200 meters. Moreover, the elements can be implemented on a miniaturized scale in conjunction with small, user devices such as smartphones, thereby also realizing optical ad-hoc networking, as well as interoperability with other types of data networks. Optically narrowcast content can be used to augment a real-world experience, enhance and/or spawn new forms of social-media and media content.
US09755738B2 Crosstalk suppression in a multi-photodetector optical channel monitor
An optical device includes an optical port array having first and second optical inputs for receiving optical beams and a first plurality of optical outputs associated with switching functionality and a second plurality of optical outputs associated with channel monitoring functionality. A dispersion element receives the optical beam from an input and spatially separates the beam into a plurality of wavelength components. The focusing element focuses the wavelength components. The optical path conversion system receives the plurality of wavelength components and selectively directs each one to a prescribed one of the optical ports. The photodetectors are each associated with one of the optical outputs in the second plurality of optical outputs and receive a wavelength component therefrom. The controller causes the optical path conversion system to simultaneously direct each of the wavelength components to a different one of the optical outputs of the second plurality of optical outputs.
US09755737B2 Multi-layer network resiliency systems and methods
Systems and methods providing resiliency between a server layer and a client layer include determining a minimal spanning tree in the client layer; determining a Steiner tree in the server layer based on vertices associated with the minimal spanning tree in the client layer; and determining one or more resiliency paths in the client layer based on the minimal spanning tree and the Steiner tree, wherein the one or more resiliency paths are added to the minimal spanning tree in the client layer based on potential failures in the Steiner tree. For example, the server layer is an optical layer and the client layer is a Time Division Multiplexing (TDM) layer.
US09755734B1 Subsea optical communication network
A communication system includes a first and second trunk terminals, a plurality of communication trunks disposed along a floor of a body of water, and power feed equipment. Each communication trunk couples the first trunk terminal to the second trunk terminal and includes at least one signal amplifier configured to amplify a signal conveyed along the corresponding communication trunk. The power feed equipment is coupled to the plurality of communication trunks and is configured to deliver power along each communication trunk to power the at least one signal amplifier of the communication trunk. The power feed equipment is also configured to receive a shunt fault notification identifying an electrical shunt fault along a faulted communication trunk of the plurality of communication trunks. In response to the shunt fault notification, the power feed equipment is configured to cease delivery of power along at least one communication trunk.
US09755731B2 Hardware TCP accelerator
A TCP/IP packet decoder fetches, from a packet received via a satellite communication system, IP version information, which is provided to version comparators. When a version comparator indicates a match, protocol information is provided to a TCP comparator. If the TCP comparator determines that the packet is a TCP data packet, a flag is raised causing generation of a TCP acknowledgment for transmission to a source device. In another embodiment, a layer 3 switch or router includes a TCP hardware filter to determine whether the received packet is a TCP data packet, thereby causing the TCP data packet to be mirrored for transmission to a modem. In a third embodiment, a TCP hardware filter, provides an indication to a layer 2 switch when a TCP data packet is received causing the TCP data packet to be mirrored for transmission to a modem, which generates and transmits a TCP acknowledgment.
US09755729B2 Satellite communication link
A device configure to wirelessly transmitting optical signals via a satellite communication link includes a first sending arrangement and a first receiving arrangement. The first sending arrangement is configured to transmit optical signals via a first transmission path and a second transmission path to the first receiving arrangement. The first transmission path has a first transmission channel and the second transmission path has a second transmission channel. In addition, the first transmission channel is physically separated from the second transmission channel, while the second transmission channel is a low-rate transmission channel for transmitting amplitude-modulated optical signals.
US09755728B2 Method and system for guard band detection and frequency offset detection
Methods and systems are provided for guard band detection and/or frequency offset detection. For example, a signal processing circuit may be operable to determine, for each of a plurality of downconverted signals, one or more frequency offsets that are associated with one or more corresponding local oscillators (LOs) used in obtaining the plurality of downconverted signals; and relating to the determined frequency offsets may be generated for the plurality of downconverted signals. The signal processing circuit may perform, based on the generated information, one or both of a band stacking operation and a channel stacking operation so as to prevent channels/bands being stacked on each other or being overlapped.
US09755727B2 Redundancy scheme for analog circuits and functions for transient suppression
An interference-suppression circuit produces an interference-reduced signal from output signals of a plurality of redundant functional blocks. A first extreme-value determination unit determines the specific output signal that represents a first extreme value from the output signals of the functional blocks. A processing unit offsets the output signals of the plurality of functional blocks against one another in such a manner that the interference-reduced signal is determined. The processing unit omits from consideration the first extreme value in determining the interference-reduced signal.
US09755726B2 Method and apparatus for improved multi-carrier communication
Various methods and apparatuses are provided to address the need for improved multi-carrier communication. In one apparatus, a radio access network (RAN) (402) includes multiple network nodes (403, 406) operative to transmit, via multiple carriers (411-412), packet data to a user element (UE) (401) using a protocol stack. The protocol stack includes a radio link control (RLC) layer split into an upper RLC processing layer and multiple lower RLC processing layers. Each lower RLC processing layer is associated with one carrier of the multiple carriers and each lower RLC processing layer supports packet data transmission via its associated carrier. The upper RLC processing layer supports packet data transmission via the multiple carriers.
US09755724B2 Electronic apparatus for determining relay apparatus and method thereof
The present disclosure relates to an electronic apparatus for determining a relay apparatus and a method thereof. An electronic apparatus according to various embodiments includes a communication unit that transmits and receives data. The electronic apparatus also includes a controller that determines whether disconnection between an electronic apparatus operating as a relay apparatus and at least one client apparatus is expected. The control also, if the disconnection is expected, informs the at least one client apparatus of the expected disconnection. The control also determines whether a status of the electronic apparatus satisfies a condition for a change to a new relay apparatus and informs the at least one client apparatus that the electronic apparatus no longer operates as the relay apparatus if the condition for a change to a new relay apparatus is satisfied. The control also determines any one of the at least one client apparatus as the new relay apparatus. The control also informs the at least one client apparatus of the determination on the new relay apparatus. Further, other embodiments are possible.
US09755720B2 Calibration data
Apparatus is provided for: storing at least one three-dimensional matrix C[M][N][K] of calibration data; performing singular value decomposition of each at least one three-dimensional matrix C[M][N][K] of calibration data to produce at least one first unitary rotation matrix U, at least one diagonal scaling matrix S and at least one second unitary rotation matrix V; and resizing each of the at least one first unitary rotation matrix U, the at least one diagonal scaling matrix S and the at least one second unitary rotation matrix V by removing dimensions therefrom, thereby producing resized matrices U, S and V. Corresponding decompression is also provided.
US09755719B2 Method for configuring codebook in multi-antenna wireless communication system and device therefor
The present invention relates to a method and device for transmitting a signal by a transmitting end in a wireless communication system supporting multiple antennas including a plurality of vertical domain antennas and a plurality of horizontal domain antennas. Specifically, the present invention comprises the steps of: pre-coding a signal for multiple antennas, using a specific pre-coding matrix selected on the basis of a first codebook for the plurality of vertical domain antennas and a second codebook for the plurality of horizontal domain antennas; and transmitting the pre-coded signal to a receiving end, wherein the specific pre-coding matrix is defined by using a Kronecker product of a first pre-coding matrix selected from the first codebook according to at least one first selection vector and a second pre-coding matrix selected from the second codebook according to at least one second selection vector.
US09755715B2 Distortion-aware multiple input multiple output precoding
Precoding parameters used for precoding of a source are selected to minimize distortion that would otherwise be induced in the source during encoding and transmission of the source over a multiple input multiple output (MIMO) channel.
US09755714B2 Method and system for compressed sensing joint channel estimation in an LTE cellular communications network
Methods and systems for performing compressed time domain joint channel estimation in a multi-user MIMO LTE wireless network include receiving training signals from a plurality of users, estimating a maximum delay spread for the received data according to a coherence bandwidth of the received data, limiting the received data in the time domain to the estimated maximum delay spread, selecting and estimating an active tap from the limited data set, and subtracting a contribution of the selected active tap from the reduced data set. These steps can be repeated until the residual signal falls below a specified minimum. The network can be a C-RAN network. The training data can be SRS or DMRS data. Limiting the received data ensures that only a few significant taps are analyzed, so that the system is not under determined and can be analyzed for accurate channel estimation using any of several existing algorithms.
US09755711B2 Large deviation delay analysis of queue-aware multi-user MIMO systems with multi-timescale mobile-driven feedback
A subset of mobile device candidates in a multi-input multi-output (MIMO) channel of network devices is selected for having a feedback priority among a set of mobile device candidates. The selection is based on a set of queue state information of a plurality of mobile device queues for transmitter and receiver devices of the MIMO channel in a multi-user MIMO network. A portion of the subset of mobile device candidates can be selected by a scheduling component of the system. Communications on the MIMO channels can be scheduled to the portion of the subset of mobile device candidates based on the feedback comprising channel state information and on the queue state information of the plurality of mobile device queues.
US09755709B2 Method and apparatus for measuring channel quality in multiple input multiple output system
A method and an apparatus for measuring channel quality in a MIMO system is provided. The method includes measuring a first SINR based on an assumption that a first detector is used, using a channel estimation value of a reception signal with respect to each of a plurality of space layers, and a second SINR for each of the plurality of space layers corresponding to a case where the plurality of space layers exist independently using the channel estimation value of the reception signal; determining a Log Likelihood Ratio of reception data based on an assumption that a second detector is used, with respect to each of the plurality of space layers; and generating channel quality information based on an assumption that the second detector is used, based on the first SINR and the second SINR with respect to each of the plurality of space layers, and the LLR.
US09755708B2 High data rate uplink transmission
A user equipment device has a control information decoder configured to receive and decode an uplink scheduling grant. A transmit module is configured to receive a rank indicator (RI) extracted by the decoder and adapt a transmission rank in response to the RI. At least two transmit antennas are configured to transmit according to the RI.
US09755702B2 Method of operating near field communication (NFC) device and NFC device
A method of operating a near field communication (NFC) device includes receiving, by the NFC device, a first signal from an NFC reader, transmitting, by the NFC device, a response to the first signal to the NFC reader and changing selectively, by the NFC device, a radio frequency (RF) configuration parameter associated with signal transmission operation during a signal transmission interval, based on determining whether the NFC reader recognizes the response.
US09755701B2 Hybrid tag for radio frequency identification system
RFID (radio frequency identification) systems are provided in which tag and interrogator devices implement a hybrid framework for signaling including an optical transmitter/receiver system and an RF transmitter/receiver system. For instance, an RFID tag device includes: optical receiver circuitry configured to receive an optical signal having an embedded clock signal from an interrogator device, and convert the optical signal into an electrical signal comprising the embedded clock signal; clock extraction circuitry configured to extract the embedded clock signal from the electrical signal, and output the extracted clock signal as a clock signal for controlling clocking functions of the tag device; voltage regulator circuitry configured to generate a regulated supply voltage from the electrical signal, wherein the regulated supply voltage is utilized as a bias voltage for components of the tag device; and data transmitter circuitry configured to wirelessly transmit tag data to the interrogator device.
US09755700B2 Authentication for near field communications
Methods, computer program products, and systems for use in near field communications systems for authenticating at a near field communications receiver, a user of a near field communications transmitter. The system includes a data receiver for receiving a signal comprising a first unique identifier from a near field communications transmitter. The system also includes a received signal strength indicator for measuring a signal strength of the received signal. The system further includes a signal strength tracker for tracking a variation with time of the signal strength of the received signal and converting the variation with time into a second unique identifier. The system further includes a comparator for comparing the received first unique identifier and the tracked and converted second unique identifier and for outputting a signal indicating the result of the comparison. The user is authenticated if the signal indicates that the first and second identifiers correlate correctly.
US09755697B2 Method and apparatus for sensing a condition in a transmission medium of electromagnetic waves
Aspects of the subject disclosure may include, for example, a device that facilitates transmitting electromagnetic waves along a surface of a wire that facilitates delivery of electric energy to devices, and sensing a condition that is adverse to the electromagnetic waves propagating along the surface of the wire. Other embodiments are disclosed.
US09755696B2 Method, based on composite modulation, of data transmission between power electronic devices without communication line
A method of data transmission between power electronic devices without a communication line involves generation of a digital signal in a data transmission process. The digital signal enables PWM modulation of specific data information via a composite modulation method. The composite modulation superimposes PWM modulation waves after modulating the PWM carrier frequency or conducting high-frequency modulation on the data. The composite modulation generates a PWM drive pulse signal which is transmitted to a power circuit via a main power electronic circuit to complete the data transmission process. In the data receiving process, signals are extracted on the voltage and current of a power line via software or hardware, and data demodulated to obtain the data information to complete the data receiving process.
US09755694B2 Wall-embedded power line communication device
A “wall-embedded” power-line-communication (PLC) enabled device connecting with the home network backbone through the PLC technology is disclosed. The wall-embedded PLC enabled device includes at least a system module, a front panel, and a holder. With flexible, modular architecture, the device can easily optionally integrate required functions, such as sensors, actuators and so on, or additional heterogeneous communication interfaces, to extend the service coverage, to support the specific smart-house services, and other uses.
US09755691B2 Method and system for mitigating the effects of a transmitted blocker and distortions therefrom in a radio receiver
A radio receiver processing path has a mixer with active interference/blocker cancellation to reduce the intensity of leaked and undesired signals by using a replica of the transmitted signal, emulating the phase and attenuation through the leakage path and subtracting the emulated signal within the mixer. Intermodulation distortions are predicted through the use of nonlinear modeling in the digital baseband between the baseband transmitter and baseband receiver and subsequently subtracted from the received signal. The nonlinear basis functions are combined to model the composite nonlinearity in the signal path based on digital baseband transmitted data. The modeled nonlinearity is subtracted from the received signal, and the result is observed and used to guide the nonlinear modeling parameters using self-contained control loops.
US09755690B2 Multiband wireless communication method and multiband wireless communication apparatus
A multiband wireless communication method for performing a reception operation in a second frequency band while performing a transmission operation in a first frequency band selectively changes a gain characteristic of a power amplifier (1 or 2) for performing the transmission operation so that gain is lowered in the second frequency band, based on performing of the reception operation.
US09755688B1 MemEx cell phone case systems
A MemEx Cell Phone Case for providing a combination of accessory functions in conjunction with a protective mobile device case, including a storable touchscreen stylus, a foldable, magnetically retained kickstand, an external memory expansion adapter, and openings for charging ports. The memory adapter permits consumers to increase the memory of their smart phone or other device which may be otherwise incapable or receiving a memory upgrade. The adapter includes a receptacle for commercially available memory storage devices such as a micro-SD card, and features a dust cover. The entire assembly is secured by a detachable phone retainer to ensure a positive connection between the phone and case functions. The MemEx case is designed to accommodate all the controls and functions of various mobile devices in a durable, utilitarian case while providing these additional accessories.
US09755686B2 Alloy encapsulation mobile phone protect case
A method for preparing an alloy encapsulation mobile phone protective case is provided, which includes steps of: selecting an alloy material as an edging material; CNC machining; making a surface treatment; drying; spraying and molding for shaping. The alloy encapsulated mobile phone protective case is formed after shaping the alloy outer frame and the soft rubber inner molding layer, which not only simplifies the assembly, but also strengthens the strength and hardness of the structure, thus effectively avoiding the splitting phenomenon caused by strong impact. Due to the combination of the alloy material with the soft rubber inner molding layer, the protective case has a certain flexibility, abrasion resistance, high strength and high formability. The rigidity of the protective case is in a range from 50° to 90°and has strong resilient force and curvature, which not only can effectively protect the mobile phone, but also has long service life.
US09755685B2 Protective device
There is provided a protective device (100) comprising a mobile phone protective portion (110) adapted for receiving at least a portion of a mobile phone device therein in use and an accessory protective portion (105) adapted for receiving at least a portion of an accessory item therein in use.
US09755678B2 Low noise transconductance amplifiers
Provided herein are apparatus and methods for transconductance amplifiers, such as split cascode low-noise transconductance amplifiers (LNTAs). In an embodiment, an LNTA includes split current paths each coupled to a different mixer by way of a different alternating current (AC) coupling capacitor. The split current paths of the LNTA can be enabled during different modes of operation, such as when the input to the LNTA is within different frequency bands.
US09755674B2 Method for encryption obfuscation
A system and method provide a signal carrier; an overt persistent digital channel containing a host signal and carried on the signal carrier; a non-persistent channel encoded onto the host signal by timing variation of the host signal, the non-persistent channel including access data for accessing hidden information in the host signal.
US09755664B2 Methods and apparatus for efficient illumination of individual keys in a keyboard
A keyboard is able to illuminate particular keys and to detect keypresses in an efficient manner. The keys of the array are logically arranged into one or more two-dimensional arrays (e.g., row/column arrays) so that the illumination and keypress detection functions share a common set of electrical signal lines in one dimension of the array. By coupling both the lights and the key actuation switches of each key to a common set of signal lines in one dimension, the number of signal lines used in the keyboard can be reduced.
US09755663B1 Parallel-serial conversion circuit, information processing apparatus and timing adjustment method
A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.
US09755656B2 Digital protective relay
The present disclosure relates to provide an active erroneous sample elimination device or erroneous sample elimination method for a relay capable of correctly implementing erroneous sample elimination processing even during a plurality of electrical disturbances mixed with an electrical quantity detection signal, and a digital protective relay according to the present disclosure may include a converter that samples an analog signal and converts the sampled signal to a digital signal; and a processor that searches an inflection point at which an electrical variation quantity varies from an increase to a decrease or from a decrease to an increase based on the digital signal, and compares an electrical variation quantity prior to and subsequent to the inflection point with a preset electrical quantity.
US09755647B1 Techniques for handling high voltage circuitry in an integrated circuit
An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.
US09755645B1 Current source logic gate
A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.
US09755639B2 Device and method for an electronic circuit having a driver and rectifier
In accordance with an embodiment, a method includes driving a transistor device by a driver having an output coupled to a control node of the transistor through a capacitor and limiting a magnitude of a voltage of one polarity between the control node and a first load node of the transistor device by a rectifier circuit.
US09755638B2 Output discharge techniques for load switches
An output discharge circuit for a load switch may include a capacitor coupled between a power rail of the output discharge circuit and a ground lead, and a diode coupled between a power input of the output discharge circuit and the power rail. The output discharge circuit may charge the capacitor via a current path formed by the diode while power is being supplied to the load switch. When the power supply to the output discharge circuit is turned off, the diode may prevent the capacitor from discharging through the current path, and the stored charge on the capacitor may be used to power the output discharge switch for a period of time after the power supply has been turned off. In this way, the output discharge circuit may continue to discharge the output of the load switch even when power is no longer being supplied to the load switch.
US09755636B2 Insulated gate device discharging
A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided. The inductive circuit is coupled to the gate of the switching device and further coupled to receive the charging voltage such that application of the charging voltage to the inductive circuit is with a polarity that induces a first current to flow through the inductor in a direction corresponding to charge moving away from the gate and such that discontinuation of the application of the charging voltage to the inductive circuit induces a second current flowing through the inductor in the direction corresponding to charge moving away from the gate such that the second current discharges the gate of the switching device. Faster turn off of the switching device is thus made possible and is synchronized to the discontinuation of the charging voltage.
US09755635B2 Electronic system for an electrical apparatus and related method
An electronic system is disclosed for an associated electrical apparatus, the system having at least a binary input adapted to receive one or more candidate signals; at least an electronic active load having one or more electronic active devices and operatively connected to the binary input; and a controller operatively associated to the binary input and to the active load. The controller can detect application of a candidate signal to the binary input and electrically drive the active load upon such detection; and after absorption of a predetermined amount of energy, validate the candidate signal if its residual content of energy exceeds a predetermined threshold.
US09755627B2 Series-resonance oscillator
An oscillator circuit comprises a first tank circuit comprising an inductive element and a capacitive element coupled in series between a first voltage rail and a first drive node. A feedback stage is coupled to a first tank output of the first tank circuit and to the first drive node. The feedback stage is arranged to generate, responsive to a first oscillating tank voltage present at the first tank output, a first oscillating drive voltage at the first drive node in-phase with a first oscillating tank current flowing in the inductive element and the capacitive element, thereby causing the oscillator to oscillate in a series resonance mode of the inductive element and the capacitive element.
US09755624B2 Ramp signal generating circuit and signal generator, array substrate and display apparatus
A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first shift register (11), a second shift register (12), a voltage decreasing unit (13) and a sampling unit (14); the voltage decreasing unit (13) is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register (11) is connected to the voltage decreasing unit (13) and is configured to control the voltage decreasing unit (13) to output voltages which are decreased continuously stage by stage; the sampling unit (14) has an output terminal and is connected to the voltage decreasing unit (13); the second shift register (12) is connected to the sampling unit (14) and is configured to control the sampling unit (14) to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit (13). Such ramp signal generating circuit is capable of reducing area of the ramp signal generating circuit and improving linearity of ramp signal.
US09755623B2 Multi-bit flip-flop with shared clock switch
A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.
US09755621B1 Single stage cascoded voltage level shifting circuit
A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.
US09755616B2 Method and apparatus for data filtering, and method and apparatus for constructing data filter
A method for data filtering includes segmenting a to-be-detected vector to obtain k to-be-detected sub-vectors, respectively performing an inner product operation on the k to-be-detected sub-vectors and corresponding detection vectors among preset k detection vectors to obtain k first operation results, determining a first operation result whose value is the maximum among the k first operation results and obtaining an identifier of a detection vector corresponding to the first operation result, where a detection vector is in a one-to-one correspondence to an identifier, and mapping the to-be-detected vector to a preset data filter according to the obtained identifier of the detection vector corresponding to the first operation result whose value is the maximum, and determining, using the data filter, whether to filter out the to-be-detected vector.
US09755615B2 Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
US09755611B2 Piezoelectric thin film resonator, filter and duplexer
A piezoelectric thin film resonator includes: a substrate; a piezoelectric film provided on the substrate; a lower electrode and an upper electrode that sandwich at least a part of the piezoelectric film and face with each other; and an inserted film that is inserted in the piezoelectric film, is provided on an outer circumference region in a resonance region in which the lower electrode and the upper electrode sandwich the piezoelectric film and face with each other, is not provided in a center region of the resonance region, and has a cutout in the resonance region.
US09755603B2 Active compensation for power amplifier gain droop
Some embodiments relate to a method and circuit for gain compensation. The method includes detecting a strength of an output signal generated by a power amplifier of a transmitter in response to a commanded transmission signal. The method also includes comparing the detected strength of the output signal to a delayed version of a detected strength of the commanded transmission signal to obtain an error signal. The method further includes compensating for gain drop of the output signal by adjusting a gain of the transmitter based on the error signal.
US09755602B2 Broadband microwave variable gain up-converter
A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.
US09755599B2 Amplifier with boosted peaking
In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.
US09755598B2 Method and apparatus for level control in blending an audio signal in an in-band on-channel radio system
A method for processing a digital audio broadcast signal includes: separating an analog audio portion and a digital audio portion of the digital audio broadcast signal; determining the loudness of the analog audio portion and the digital audio portion over a first short time interval; using the loudness of the analog and digital audio portions to calculate a short term average gain; determining a long term average gain; converting one of the long term average gain or the short term average gain to dB; if an output has been blended to digital, adjusting a digital gain parameter by a preselected increment to produce a digital gain parameter; if an output has not been blended to digital, setting the digital gain parameter to the short term average gain; providing the digital gain parameter to an audio processor; and repeating the above steps using a second short time interval.
US09755597B2 Fixed gain amplifier circuit
An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.
US09755593B2 Method for compensating a power amplification unit of a wireless RF module
The present invention relates to a method for compensating a power amplification unit of a wireless RF module that includes a baseband unit, a RF transceiver unit, a power amplification unit and a control unit. The baseband unit is connected to the power amplification unit through the control unit and the RF transceiver unit. Based on the characteristic of the power amplification unit, the baseband unit provides a control signal to regulate the output signal characteristic of the power amplification unit, or provides a RF transceiver unit control signal to regulate the characteristics of the RF signal being transmitted by the RF transceiver unit to the power amplification unit, or to regulate the characteristics of the baseband signal being transmitted to the RF transceiver unit, enabling the characteristics of the output signal of the power amplification unit to meet the specifications of the related system.
US09755592B2 Power amplifier modules including tantalum nitride terminated through wafer via and related systems, devices, and methods
One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.
US09755585B1 High power radio frequency amplifier with dynamic digital control
The present invention provides an RF power amplifier architecture which with dynamic digital control of the amplification by incorporating digitized RF input and output signal envelope data and environmental temperature sensor(s) readings into an arbitrary control algorithm implemented on a digital processor. Via the combination of digitally controlled DC/DC converter and a D/A converter, the quiescent bias of the power FET of the RF output stage can become a realization of virtually any function of the feedback and input data.
US09755583B2 Using fractional delay computations to improve intermodulation performance
Enhancing the intermodulation performance of an RF power amplifier by determining a coarse time delay represented by an integer TI; determining a reference point for a transmitted signal waveform of the RF power amplifier; shifting the waveform by a set of offsets including a plurality of non-integer fractional steps; correlating the transmitted signal waveform with a feedback signal waveform to obtain a respective correlation value for each of corresponding fractional steps; obtaining an accurate fractional delay value by selecting a fractional step having a highest respective correlation value; applying the obtained correct fractional delay value to the transmitted signal waveform to provide a compensated transmitted signal waveform and combining the compensated transmitted signal waveform with the feedback signal waveform to reduce at least one intermodulation product of the RF power amplifier.
US09755582B2 Switch circuit, sampling switch circuit and switch capacitor circuit
A switch circuit comprising: a plurality of switches; a switching module; and a capacitor, having a first terminal and a second terminal, wherein the first terminal is coupled to a predetermined voltage, and the second terminal is coupled to a control terminal of at least the switch in a conductive mode via the switching module, to thereby control a conductive state for the at least one switch.
US09755580B2 Tunable logarithmic amplifier
The disclosure concerns a tunable logarithmic detector amplifier (TLDA) system where dynamic tuning functionality is applied to resonant circuits used for feedback control as well as applying tuning to the amplifier. Control signals for the tuning function are generated from the baseband processor. The control of the amplifier tuning and resonator tuning can be performed from information derived from baseband where metrics such as SNR, SINR or CQI are used to optimize system performance. Bandwidth and sensitivity of the receiver are key specifications targeted for optimization using this technique. This technique can be implemented in designs where a wide bandwidth is required.
US09755578B2 Current-mode control for radio-frequency power amplifiers
Current-mode control for radio-frequency (RF) power amplifiers. In some embodiments, an RF power amplifier control circuit can include a sensor configured to measure a base current of a power amplifier and generate a sensed current. The control circuit can further include a sensing node configured to receive a reference current and perform a current-mode operation with the sensed current to yield an error current. The control circuit can further include a control loop configured to generate a control signal based on the error current to adjust an operating parameter of the power amplifier.
US09755572B2 Rail-less roof mounting system
A rail-less roof mounting system for installing photovoltaic (PV) modules on a roof structure comprises a base mount assembly that engages with a clamp assembly and attaches to the roof structure. The base mount assembly comprises a base member having a waterproof means, a block slider, a top slider and a covering means. An elevated seal portion of a block slider includes a borehole to receive the waterproof means. A vertical engaging portion of the block slider is attached with a sliding seal member of the top slider. The clamp assembly includes a clamp member and a plate member and the clamp member is attached with a track of the top slider. The clamp member interlocks the PV modules to provide a corner-to-corner coupling arrangement, which enables the connection of PV module corners to adjacent PV module corners by sandwiching above and beneath frame members of the PV modules.
US09755571B2 Photovoltaic mounting system with chemical flashing
Photovoltaic mounting systems having sealant injection system are provided herein. Such sealant injection systems provide improved directional control of sealant flow and improved sealing of roof penetrations during mounting with one or more fasteners. Such systems can include a bracket assembly having a removable sealant injection package. The sealant injection package includes a collapsible sealant injection reservoir and is adapted to provide directionally controlled release of sealant upon collapse. Such a system can further include sealant injection guides that direct flow of sealant during mounting and pads or caps that cover and enclose the injected sealant so as to ensure adequate sealing of any roof penetrations and maintain its integrity over time. Such systems further allow for sealant injection packages to be interchanged or replaced as needed and allow for ready removal or replacement of the bracket after mounting while maintaining the seal of any roof penetrations.
US09755567B2 Determination of permanent magnetic flux in an electric machine
An electric machine assembly has an electric machine having a stator and a rotor. The rotor has a rotor temperature and is configured to rotate at a rotor speed (ω). The stator has stator windings at a stator winding temperature (tS) and the electric machine defines a number of pole pairs (P). A controller is operatively connected to the electric machine and is configured to receive a torque command (T*). The controller has a processor and tangible, non-transitory memory on which is recorded instructions for executing a method for determining a total permanent magnetic flux (ψT) as a function of the rotor temperature. Execution of the instructions by the processor causes the controller to determine a high-speed magnetic flux factor (ψH) and a low-speed magnetic flux factor (ψL).
US09755559B2 Vibrator motor speed determination in a mobile communications device
One embodiment relates to testing and verifying vibrator motor operation during manufacturing of a device and during in-the-field use. The test relies on an integrated motion sensor or other mechanical measurement circuitry, such as, for example, an accelerometer. In one embodiment, a speed determination for a vibrator motor performance during initial manufacture of the device. Subsequently, when vibration is detected during the in-the-field use, the vibration may be sampled using the integrated mechanical measurement circuitry. Once sampled, a speed may be determined based on a resonance of the sampled signal. Over time, the various speed determinations for the vibrator motor may be analyzed to determine an overall health of the vibrator motor. A threshold for detecting when the overall health of the vibration motor over time has degraded may be predetermined. A notification of a degradation of vibrator motor performance is sent to either a manufacturer or user of the mobile communications device. Other embodiments are described and claimed.
US09755557B2 Field-winding rotating electrical machine
A field current limiting section includes a field current limitation instructing section for, when a field current limitation determining section determines that a determination value has reached a predetermined determination threshold value, generating a field current limiting instruction to a field current control section so as to limit field current to be equal to or smaller than a predetermined permissible value during a predetermined field current limitation time Tlim. A field current limitation releasing section outputs a field current limitation releasing instruction to the field current limiting section so as to release limitation of the field current during a predetermined field current limitation release time TC. When having received the field current limitation releasing instruction from the field current limitation releasing section, the field current limiting section releases limitation of the field current during the predetermined field current limitation release time.
US09755555B2 Drive circuit for a permanent magnet motor
A drive circuit for an electric motor connected in series with an AC power source between a first node and a second node. The drive circuit includes a controllable bidirectional AC switch, an AC-DC conversion circuit connected in parallel with the controllable bidirectional AC switch between the first node and the second node, a position sensor configured to detect a position of a rotor of the motor, and a switch control circuit configured to control the controllable bidirectional AC switch to be conductive or non-conductive in a predetermined way, based on the position of the rotor and a polarity of the AC power source.
US09755554B2 Apparatus and means for progressive motor start based on current derivative synchronisation
A method for controlling a switch that controls a power supply line of an electric motor from an alternating voltage source, including determination of a switch closing instant (tf) starting from a measurement of the derivative of the current carried on the power supply line. A starter system and a computer program product are capable of using this method.
US09755552B2 Frequency converter
A frequency converter includes: a primary winding 12 in which a plurality of windings on which a polyphase alternating voltage is applied are arranged periodically along a particular direction; a secondary winding 22 which is magnetically coupled to the primary winding 12 and in which a plurality of windings are arranged along the particular direction with a repetition period different from the primary winding 12; and a frequency modulation part 3 which is arranged on a magnetic path between the primary winding 12 and the secondary winding 22 and in which a plurality of magnetic materials 31 are arranged periodically. Then, the pitch of the plurality of magnetic materials 31 and the winding arrangement period of the primary winding 12 and the secondary winding 22 are different from each other so that an alternating voltage having a frequency different from the frequency of the polyphase alternating voltage is induced in the secondary winding 22.
US09755551B2 Power conversion device
A power conversion device includes: a plurality of 3-level converters (31 to 35) that are multiple-connected in series to an AC power supply; and a control device (10) controlling operations of the plurality of 3-level converters (31 to 35). The control device (10) includes: a calculation unit calculating an output voltage command for the plurality of 3-level converters (31 to 35); a carrier signal generation unit generating a carrier signal; a correction unit correcting a phase of the carrier signal based on a potential variation on a DC neutral point bus (7); and a pulse width modulation control. unit delaying the phase by a prescribed amount based on the carrier signal having the phase corrected by the correction unit as a reference phase, to generate a plurality of carrier signals, and comparing the output voltage command with each of the plurality of carrier signals to generate a control command for each of the plurality of 3-level converters (31 to 35).
US09755550B2 Converter
A voltage source converter includes a converter limb having limb portions separated by an AC terminal and extending between DC terminals, each limb portion including a primary switching element to switch the limb portion into and out of circuit. The converter further includes an auxiliary limb. The primary switching element of each limb portion is switchable to switch the auxiliary limb into and out of circuit with the corresponding limb portion. The converter further includes a control unit to, in one mode, inject a circulation current that flows in one direction in one of the limb portions and minimize a current flowing in the opposite direction in that limb portion. Each primary switching element switches the respective limb portion into or out of circuit following the minimization of the limb portion current by the circulation current.
US09755547B2 System for controlling an electrical load
The present invention relates to a control system for an electric charge, said system comprising: —A first power converter (VV1) and a second power converter (VV2) connected in parallel, —A first control unit (UC1) associated with the first power converter and a second control unit (UC2) associated with the second power converter, —The second control unit (UC2) comprises a main control module (M1_2) for determining a second output voltage (vσ2) to apply the electric charge and a secondary control module (M2_2) to determine a control voltage (Δvσk) to be applied to said second output voltage (vσ2), said control voltage being determined from the difference between the output current (iσ2) of the second power converter and the output current (iσ1) of the first power converter.
US09755545B2 System and method for unified common mode voltage injection
A power conversion system includes at least one multi-level power converter and a controller coupled to the at least one multi-level power converter. The controller includes a first CMV injection module and a second CMV injection module. The first CMV injection module generates a first CMV signal for modifying at least one voltage command to achieve a first function in association with operation of the power conversion system. The second CMV injection module generates a second CMV signal based at least in part on a three-level CMV limit either for modifying the at least one voltage command or for further modifying the at least one modified voltage command to achieve a second function in association with operation of the power conversion system.
US09755543B2 Power supply device and semiconductor device
Switching loss is reduced by decreasing the switching frequency of a PFC power supply in light load condition, whereas the switching frequency is maintained high in heavy load operation. Efficiency in light load operation is thus improved without enlarging a boosting inductor and an output smoothing capacitor. A capacitor is provided in a triangular wave generating circuit and the triangular wave generating circuit outputs a triangular wave by charging and discharging this capacitor. Charging and discharging of the capacitor are controlled by an oscillation frequency control circuit output current which is input to a comparator.
US09755538B2 Active AC-link power converter
A power converter includes an output converter having a 3-phase or higher output, an inductor coupled to the output converter and a switch device coupled to the inductor. The switch device charges the inductor via a DC input during a first stage of a switching cycle of the switch device. The output converter discharges the inductor to a load coupled to the 3-phase or higher output during a second stage of the switching cycle. The output converter includes a phase leg for each phase of the 3-phase or higher output, each phase leg having a first thyristor device connected in series with a second thyristor device. Each phase of the 3-phase or higher output originates between the first thyristor device and the second thyristor device of the corresponding phase leg.
US09755536B2 Contactless inductively coupled power transfer system
A contactless inductively coupled power transfer system includes a power supply device and a power receiving device. The power supply device includes a primary winding for generating an electromagnetic field (EMF) in response to an AC current flow having an operating frequency. The power receiving device includes a resonant circuit outputting an output voltage to a load and including a secondary winding and a reactance element. The reactance element is capable of forming a parallel resonant LC circuit with the secondary winding that resonates at the operating frequency, and forming a series resonant LC circuit that resonates at the operating frequency, and that is to be connected in series to the load.
US09755534B2 High efficiency high frequency resonant power conversion
A power converter comprises a switch network coupled to an input voltage, a power transformer having a primary winding and a secondary winding, wherein the primary winding is coupled to the switch network, and the secondary winding is coupled to a rectifier, wherein the rectifier is coupled to an output voltage, a primary resonant tank having a first resonant capacitor and a first resonant frequency, and coupled to the primary winding of the power transformer and the switch network, and a regulation circuit configured to control the output voltage of the power converter to be substantially proportional to the input voltage and the switch network to operate at a frequency substantially close to the first resonant frequency.
US09755530B2 Power converter with synchronous control function and control method thereof
The present invention discloses a power converter with synchronous control function and control method thereof. The power converter includes: a transformer, a power switch, a switch control unit, a signal coupling circuit, a synchronous rectifying switch and a secondary side control circuit. The switch control unit generates an operation signal according to a feedback signal, and generates a first synchronous signal which is related to the operation signal. The signal coupling circuit couples the first synchronous signal to generate a second synchronous signal. The synchronous rectifying switch is turned ON/OFF according to a synchronous rectifying switch signal, for synchronous rectification. The secondary side control circuit generates the synchronous rectifying switch signal according to a secondary side level detection signal and the second synchronous signal, to control the synchronous rectifying switch. The ON time of the power switch and the ON time of the synchronous rectifying switch do not overlap.
US09755524B2 DC-DC converter
Provided is a vehicle which enables a highly-efficient DC-DC converter and a highly-efficient power supply to a load, regardless of a power supply amount of to the load. When the power supply amount to a load R1 is a predetermined value or more, a control means 5 implements a first mode for making the switching elements S1 to S4 driven, and when the power supply amount of to the load R1 is the predetermined value or less, the control means 5 implements a second mode, for making the switching elements S3 and S4 stopped in an OFF state, and making only the switching elements S1 and S2 driven.
US09755523B2 Stereoscopic DC-DC converter and grid interconnector
The present invention discloses a stereoscopic DC-DC converter for power transfer between two DC grids, the converter comprises a first converter, a second converter and a third converter, a positive terminal of the first converter is connected to a positive terminal of a second DC grid, a negative terminal of the first converter is connected to a positive terminal of the second converter, a negative terminal of the second converter is connected to a positive terminal of the third converter, a negative terminal of the third converter is connected to a negative terminal of the second DC grid, in the meantime, a positive terminal of the second converter is also connected to a positive terminal of a first DC grid, and the negative terminal of the second converter is also connected to a negative terminal of the first DC grid. Compared with the conventional DC-DC converter employing the DC-AC-DC converting technology, the DC-DC converter of the invention makes full use of existing DC voltage of the first DC grid, which significantly reduces overall power of converters that are used, and thus cost and power loss caused thereby.
US09755518B2 Current measurments in switching regulators
Features and advantages of the present disclosure include a switching regulator and current measurement circuit. In one embodiment, a switching transistor in the switching regulator has a first voltage on a first terminal and a switching voltage on a second terminal. A current measurement circuit has first and second input terminals. A first switch couples the second terminal of the switching transistor to the first terminal of the current measurement circuit when the switching transistor is on, where the second input terminal of the current measurement circuit is coupled to the first terminal of the switching transistor and measurement(s) may be taken. When the switching transistor is off, the first and second input terminals of the current measurement circuit are coupled together, and measurements emulate zero current through the switching transistor.
US09755516B2 Switched mode DCDC converter efficiency improvement by adaptive driver stage
In a switched mode inductive DCDC converter having a first mode that conducts a first current path through an inductor and through a first switch, and a second mode that conducts a second current path through the inductor and through a second switch, a detecting component detects a parameter. The detecting component outputs a biasing signal extend the turn OFF time of one of the switches in order to decrease a voltage build up on the other switch.
US09755514B2 Charge shedding circuit
In one embodiment, a method receives a shed comparison signal that is based on a comparison of a voltage detected from a voltage converter to a reference voltage and receives a zero cross signal that indicates whether a current from the voltage converter has crossed zero. The shed comparison signal is sampled for a first number of clock cycles to generate shed comparison sampled values. Also, the zero cross signal is sampled for a second number of clock cycles to generate zero cross sampled values where the second number of clock cycles are less than the first number of clock cycles. The method determines a change between a shed state and an unshed state based on the shed comparison sampled values for the first number of clock cycles or the zero cross sampled values for the second number of clock cycles.
US09755507B2 Reference voltage generator having at least one bipolar junction transistor biased by negative base voltage and associated reference voltage generating method
A reference voltage generator has a bandgap reference circuit and a negative voltage generator. The bandgap reference circuit generates a reference voltage according to at least one base-emitter voltage of at least one bipolar junction transistor. The negative voltage generator generates a negative voltage, wherein at least one base terminal of the at least one bipolar junction transistor is arranged to receive a base voltage derived from the negative voltage.
US09755505B2 Power converter
A power converter consists of a power conversion circuit for converting alternating power into insulated direct power and a control unit. The control unit, based on a voltage of alternating voltage power supply and a circuital current flowing through the power conversion circuit, supplies pulse signals for alternatively opening or closing a group consisting of a first and a fourth switch and a group consisting of a second switch and a third switch to the two groups. Through the switching action, a current composed of the low-frequency component of an alternating voltage power supply mixed with the high-frequency component of a switch flows to the power converter.
US09755504B2 Flux converter with power factor correction
A flux converter for converting an input-side alternating current into an output-side DC current, wherein a power factor correction is provided and the flux converter comprises a transformer having at least two serially arranged primary windings and a secondary winding wound in same direction. In addition, a first switch is used to switch a storage capacitor in series with a first primary winding to the alternating current in a clocked manner via rectification elements and a second primary winding can be switched to the storage capacitor in a clocked manner by a second switch.
US09755498B2 Semiconductor device, and inverter, converter and power conversion device employing the same
A boost circuit includes multiple switching circuits connected in parallel. Each switching circuit includes first through third transistors and a resistor. The first transistor, the resistor, and the second transistor are serially connected between first and second nodes. The third transistor is connected between the source of the first transistor and the second node. A conductance Gm (S) of the second transistor and a resistance r (Ω) of the resistor are respectively configured to be within ranges of 1≦Gm≦1000 and 7×Gm−1.6≦r≦170×Gm−1. Since the first transistor having a high breakdown voltage is turned on by turning on the second transistor, variations in turn-on time of the boost circuit are reduced.
US09755496B2 Solid state wideband high impedance voltage converter
A front-end converter circuit may allow devices, e.g. oscilloscopes and digitizers, to receive input signals having a wide range of possible amplitudes while maintaining a high standardized input impedance. The converter may selectively couple, using low-voltage switches, a selected input network of two or more input networks to a virtual ground node, and a selected feedback network of two or more feedback networks to a transconductance stage input. The selected input network and selected feedback network together define a respective input signal amplitude range. The converter may also controllably adjust an AC gain of the converter to match a DC gain of the converter, and selectively couple non-selected input networks to signal ground. Output referred integrated resistor thermal noise may be reduced to a desired value by lowering the value of the transconductance stage coupled across the input of the converter (through an input resistance) and the virtual ground node.
US09755492B2 Rotatable transverse flux electrical machine
The invention concerns a rotatable transverse flux electrical machine (TFEM) comprising a stator portion; and a rotor portion rotatably located in respect with the stator portion, the rotor portion including an alternate sequence of magnets and concentrators radially disposed about a rotation axis thereof; the stator portion including at least one phase, the at least one phase including a plurality of cores cooperating with a coil disposed about the rotation axis, each core including a skewed pair of poles to progressively electromagnetically engage an electromagnetic field of respective cooperating concentrators. The invention is also concerned with a plurality of elements located in desired positions in the TFEM and also with a linear TFEM.
US09755489B2 Method for manufacturing rotor core
A rotor core is manufactured by forming thin plate-like core pieces including holes, forming a lamination body including insertion holes by laminating the core pieces, and inserting and embedding a permanent magnet in each of the insertion holes of the lamination body. The holes of each core piece include one or more first holes, in each of which a position determining portion for determining the position of the permanent magnet is formed, and one or more second holes, in which a position determining portion is not formed. Each insertion hole of the lamination body is formed by overlapping first holes of some of the core pieces and second holes of the remaining core pieces.
US09755485B1 Thermally enhanced hub motor
Apparatuses and methods relating to hub motors having enhanced thermal characteristics may include a hub motor having a stator comprising steel and a central axle (e.g., a mandrel and shaft) comprising a material with a substantially higher thermal conductivity than the stator (e.g., aluminum). Heat may be transferred from the stator through the axle of the motor to an outside heat sink. Manufacturing of thermally enhanced hub motors may include extrusion and/or cryogenic fitting methods relating to the central mandrel and shaft.
US09755484B2 Methods and systems of air bubble flushing in liquid cooled generators
A liquid cooled generator is provided having a rotor having a central core and a main stator winding wrapped around the central core. A first laminate at a first end of the central core is provided having a first orifice defining a first diameter and a second laminate at a second end of the central core is provided having a second orifice defining a second diameter that is the same as the first diameter. A flow line passes through the central core and is configured to extend from the first laminate to the second laminate, the flow line defining a third diameter that is larger than the first and second diameters. The first and second diameters are configured such that air flow is permitted to pass through the first and second laminates and to restrict the flow of a liquid through the first and second laminates.
US09755478B2 Brushless motor
The invention provides a brushless motor. A stator 16 of the brushless motor has a stator core 17 provided with a plurality of salient poles 18 arranged in its a circumferential direction, and a winding wire 20 wound around the plurality of salient poles 18 through an insulator 19. A rotor 22 of the brushless motor has a tubular rotor yoke 23 arranged to surround the stator 16, an annular magnet for detent torque 25 arranged in an inner peripheral portion of the winding wire 20 on the stator core 17 and surrounding the shaft 15, and a magnetic member 27 coupled to an interior surface of a ceiling portion of the rotor yoke 23 to be opposed to the magnet for detent torque 25, and surrounding the shaft 15.
US09755477B2 Magnetic mounting with force compensation
The aim of the invention is to better compensate for specifiable forces on a magnetic mounting. This is achieved by a magnetic mounting device with a first magnet device (10), which is designed in an annular manner and which has a central axis, for retaining a shaft on the central axis in a rotatable manner by means of magnetic forces. The magnetic mounting device additionally has a second magnet device (12), which is independent of the first magnet device (10), for compensating for a specifiable force acting on the shaft. In this manner, the magnetic mounting device can compensate for the gravitational force or forces based on imbalances.
US09755474B2 Versatile cooling housing for an electrical motor
An electrical device comprising a housing having cooling fins located in a central portion along an exterior surface of the housing and a laminated magnetic stack disposed within the housing and interfacing with an interior surface of the housing at the central portion. The cooling fins are configured alternatively higher and smaller on an inlet manifold and in opposition on an outlet manifold.
US09755473B2 Waterproof and dustproof motor
A motor structure is provided. The motor structure has: a motor; a circuit board including a driver circuit for controlling the motor; an upper shell; a base; a lower shell; an outlet, wherein wires of the circuit board is connected to the exterior of the motor structure through the outlet; a first tight chamber, formed by closing the upper shell and the base together, wherein the motor is disposed in the first tight chamber; and a second tight chamber, formed by closing the base and the lower shell together, wherein the circuit board is disposed in the second tight chamber.
US09755470B2 Rotary electric machine and electric power steering device using rotary electric machine
In a rotary electric machine, when armature coil bodies of respective phases in which first and second armature windings, are both wound around 6 k×n teeth are set as Ua, Va, and Wa, armature coil bodies of respective phases in which only the first and armature winding is wound around 6 m×n teeth are set as Ub, Vb, and Wb, and armature coil bodies of respective phases in which only the second armature winding is wound around 6 m×n teeth are set as Uc, Vc, and Wc, Ua, Va, Wa, Ub, Vb, Wb, Uc, Vc, and Wc are respectively arranged so as to exhibit 2 n-fold rotational symmetry about an axial center of a rotor.
US09755468B2 Electric motor/generator with multiple individually controlled turn-less structures
Systems and methods for generating currents in a plurality of CTS that may be independently controlled by a microprocessor. In some cases, a DC power source (such as a battery) is connected to each inverter. In other cases, a rechargeable DC power source (such as a capacitor) is connected to each inverter. Multiple controllable, turn-less structures may be provided in a suitable configuration with a single, main control processor or alternatively, with both a main control processor and several intermediate level command modules, each intermediate level command module coupled to a respective one of the inverters to control currents through each conductor of the respective inverter.
US09755466B2 Rotor for an electrical machine
A rotor that includes a rotor core assembly secured to a shaft. The rotor core assembly includes a magnet and an end cap secured to an end of the magnet. Each of the magnet and the end cap has a bore into which the shaft extends. The end cap forms an interference fit with the shaft. The magnet forms a clearance fit with the shaft and an adhesive is located in the clearance between the magnet and the shaft. Additionally, a method of manufacturing the rotor. The method includes inserting the shaft into the bore of the end cap. An adhesive is then introduced into the bore of the magnet and the shaft is inserted into the bore of the magnet so as to cause adhesive to be drawn into the clearance defined between the magnet and the shaft.
US09755463B2 Electric machine
An electric machine comprise a first carrier having an array of electromagnetic elements and a second carrier having electromagnetic elements defining magnetic poles, the second carrier being arranged to move relative to the first carrier. An airgap is provided between the first carrier and the second carrier. The electromagnetic elements of the first carrier include posts, with slots between the posts, one or more electric conductors in each slot, the posts of the first carrier having a post height in mm. The first carrier and the second carrier together define a size of the electric machine. The magnetic poles having a pole pitch in mm. The size of the motor, pole pitch and post height are selected to fall within a region in a space defined by size, pole pitch and post height that provides a benefit in terms of force or torque per weight per excitation level.
US09755462B2 Rotor geometry for interior permanent magnet machine having rare earth magnets with no heavy rare earth elements
An interior permanent magnet machine includes a wound stator, and a rotor core defining a plurality of pole cavities. Each of the pole cavities includes a cross section, perpendicular to a central axis of rotation, that defines a cross sectional shape having a centerline. The cross sectional shape of each of the pole cavities includes a radially inner barrier portion, a radially outer barrier portion, and a central portion. The centerline of the cross sectional shape of each of the radially outer barrier portion and the radially inner barrier portion, of each pole cavity, is defined by a generally arcuate segment. The centerline of the cross sectional shape of the central portion, of each pole cavity, is defined by a linear segment. One of a plurality of rare earth magnets, having no heavy rare earth elements, is disposed within the central portion of one of the plurality of pole cavities.
US09755461B2 Non-contact power feeding apparatus
There are provided with: a secondary winding 20 to which an electric power is supplied in a non-contact manner from a primary winding 10 by an alternating-current power source; a first circuit section 21 connected in parallel to the secondary winding 20; and a second circuit section 22 connected in series to a parallel circuit of the secondary winding 20 and the first circuit section 21. An impedance of the first circuit section 21 is larger than an impedance of the second circuit section.
US09755458B2 Bus recovery after overload
A set of generators are connected in parallel using a generator bus. At least one of the generators is associated with a controller. The controller detects an overload condition on the generator bus caused by a load and disconnects an initial generator from the generator bus in response to the overload condition. The initial generator continues to run during the overload condition after disconnecting from the generator bus but alternator excitation may be removed from the initial generator. The controller initiates starting one or more additional generator without alternator excitation. The controller also initiates connecting the initial generator and the one or more additional generators to the generator bus connected to the load. Alternator excitation is applied to the initial generator and the one or more additional generator so that adequate power may be applied to the load.
US09755457B2 Uninterruptible power supply apparatus
Provided is an uninterruptible power supply apparatus that can properly adjust the capacity of cooling a heat radiation source. A housing for housing an uninterruptible power module is provided with a cooling fan for cooling the internal space of the housing. The housing is further formed with an opening. The opening formed in one housing and the opening formed in an adjacent housing for housing another uninterruptible power module are configured to face each other. Furthermore, each uninterruptible power module includes a fan control circuit for controlling the cooling fan. The fan control circuit controls the actuation and suspension of the cooling fan on the basis of a total load of the plurality of uninterruptible power modules.
US09755446B2 Mobile charging table with hinged tabletop and selectively accessible battery compartment opening
A mobile charging table and a method of use are configured for ease of mobility and ease of service. The table has a tabletop, a base, a battery powered charging hub, and a battery compartment. The tabletop may be connected to the base by a hinge arrangement permitting tabletop movement between its first and second positions. Movement of the tabletop to its second position exposes an opening of the battery compartment for servicing a battery that supplies power to the charging hub. In the flipped down position, the tabletop extends substantially horizontally to overlie the opening in the battery compartment and to allow user(s) to use the tabletop as a workspace.
US09755442B2 Battery protection integrated circuit and circuit characteristic setting method
A battery protection IC has detection circuits to detect faults of an overcharge, an over-discharge, and an overcurrent of a secondary battery; a control circuit to protect the secondary battery, by controlling (dis)charging the secondary battery upon the fault; and a delay circuit to generate delay after the fault before the controlling. The IC includes a memory unit to store data for setting and adjusting a circuit characteristic of the IC; and a setting circuit to set and adjust the circuit characteristic, based on the data from the memory unit. The memory unit includes a pair of non-volatile memory cells to complementarily store one bit, and a latch circuit directly cross-coupled with the memory cells, for each bit of the data. The latch circuit statically outputs the data from the memory cells to the setting circuit when the IC is turned on.
US09755441B2 Battery authentication method and apparatus
Improved handling of battery recognition tasks in an electronic device such as a cell phone, smart phone, computer system, recording device or others is facilitated. Recognition of a battery so as to enable exchange of power between the device and the battery is determined by a match between one of a plurality of number strings stored in the device and the decrypted response to an encrypted challenge derived from the one of stored number string.
US09755439B2 Battery state control circuit, battery state control device, and battery pack
A battery state control circuit is provided for connection to multiple rechargeable batteries, the multiple batteries being connected in series, for connection to a primary coil connected in series to the multiple batteries, and for connection to multiple secondary coils to which electrical energy stored in the primary coil is transferred, the multiple secondary coils being connected in parallel to the multiple batteries, respectively. The battery state control circuit includes an adjustment unit to adjust the energy amount stored in the primary coil, in accordance with a state of at least one of the multiple batteries.
US09755437B2 Method, apparatus, and computer program product for wireless charging detection
Method, apparatus, and computer program product example embodiments provide wireless charging detection. According to an example embodiment of the invention, a method comprises advertising by a wireless charging device, an availability for wireless charging over a wireless communication interface; scanning, by the wireless charging device, for wireless signals from one or more other wireless devices; providing, by the wireless charging device, information usable for characterizing charging capabilities of the wireless charging device; transmitting, by the wireless charging device, one or more wireless communication packets over the wireless communication interface, including the information usable for characterizing the charging capabilities of the wireless charging device, in response to receiving one or more wireless signals from the one or more other wireless devices; and providing, by the wireless charging device, power to the one or more other wireless devices over a wireless power interface.
US09755436B2 Power receiving device and power transmitting device
A power receiving device includes: a power receiving unit that receives electric power from an externally provided power transmitting unit contactlessly; and a casing having the power receiving unit accommodated therein, the casing including: a lid member located on the power transmitting unit's side and allowing a magnetic field to pass therethrough, and a plurality of temperature sensors provided at the lid member and sensing in temperature a foreign matter present between the power transmitting unit and the power receiving unit, the temperature sensors being spaced closer together at the location of a strong portion of an electromagnetic field strength generated from the power receiving unit than the location of a weak portion of the electromagnetic field strength generated from the power receiving unit.
US09755433B2 Hybrid alternating current (AC)/direct current (DC) distribution for multiple-floor buildings
A hybrid alternating current (AC)/direct current (DC) distribution system for multiple-floor buildings includes per-floor rectifiers for converting supply side AC to DC. Each rectifier is configured to supply a plurality of DC loads associated with one floor of a multiple-floor building. The system further includes per-floor DC busses, each of the DC busses being configured to distribute the DC to the DC loads its respective floor. The system further includes at least one AC bus for supplying AC power to AC loads in the building.
US09755430B2 Virtual inverter for power generation units
A gateway controller allows a plurality of individual power generation units coupled to an electrical distribution grid to be controlled in a coordinated fashion. The gateway controller allows control of the plurality of individual power generation units as a single power generation unit. The gateway controller may determine required control parameters of the power generation units that will provide a desired combined behavior, such as combined alternating current injected into the grid, and issues commands to the power generation units based on the determined control parameters.
US09755418B2 Fuse protection for a line
A device and method for fuse protection of a line includes at least two sensors for sensing a corresponding electric variable in a first location and a second location along a conductor line, and for outputting a corresponding first value and second value of the electric variable at the first and second locations, respectively. An evaluation unit evaluates the generated first and second values in order to generate an evaluation result. The evaluation unit controls, based on the evaluation result, an isolating element to cause the isolating element to interrupt a current flow in the conductor line.
US09755413B2 Side-loading quadrant deadend clamp assembly
A clamp assembly includes a body member and a keeper. A cable groove is formed in the body member to receive a cable. The keeper has a lower surface to engage the cable received in the cable groove. A threaded fastener connects the keeper to the body member. A recess is formed in the body member to receive a washer on the fastener.
US09755412B2 Grommet for mounting cable gland or the like
A grommet for mounting a cable within a cable gland includes: an annular body having first and second opposed ends along a longitudinal axis; and a flange extending radially outwardly from the first end of the body. The second end is tapered to encourage insertion into an open end of a cable gland. The flange and body are formed as a monolithic component includes an elastomeric material.
US09755411B2 Electrical receptacle outlet draft shield cover
The present invention relates generally to an electrical receptacle and face plate outlet covering as an energy saving device by blocking any and all air infiltration from the receptacle area. The cover is made from recyclable plastic and is rectangular in shape, with insulating foam around the edges of the cover. There are sets of three cut-outs or Rule Steel Die Cut slits in the cover, which are matched and accommodated with a normal electrical plug or a plug lock to be plugged into the receptacle outlet.
US09755407B2 Draw out apparatus for air circuit breaker
The present invention relates to a draw out apparatus for an air circuit breaker, and more particularly, to a draw out apparatus for an air circuit breaker capable of allowing a circuit breaker body to be stopped at a preset position, by executing idling when an abnormal operation such as an over-draw in operation and an over-draw out operation occurs at the preset position such as a disconnect position, a test position or a connect position, and capable of preventing damage of a circuit breaker and a cradle.
US09755405B2 Corona suppression at the high voltage joint through introduction of a semi-conductive sleeve between the central electrode and the dissimilar insulating materials
A corona ignition assembly comprising a plurality of different insulators disposed between an ignition coil assembly and firing end assembly is provided. A high voltage center electrode extends longitudinally between an igniter central electrode and the ignition coil assembly. A high voltage insulator formed of a fluoropolymer surrounds the high voltage center electrode, and a firing end insulator firing of alumina surrounds the igniter central electrode. A sleeve formed of a semi-conductive and complaint material, such as silicone rubber with conductive filler, is disposed radially between the electrodes and adjacent insulators. The sleeve fills air gaps and minimizes the peak electric field within the corona igniter assembly. The sleeve is able to prevent unwanted corona discharge, and thus extends the life of the materials and directs energy to the firing end.
US09755403B2 Controlling the emission wavelength in group III-V semiconductor laser diodes
Methods are provided for modifying the emission wavelength of a semiconductor quantum well laser diode, e.g. by blue shifting the emission wavelength. The methods can be applied to a variety of semiconductor quantum well laser diodes, e.g. group III-V semiconductor quantum wells. The group III-V semiconductor can include AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP, and group III-V ternary semiconductors alloys such as AlxGai.xAs. The methods can results in a blue shifting of about 20 meV to 350 meV, which can be used for example to make group III-V semiconductor quantum well laser diodes with an emission that is orange or yellow. Methods of making semiconductor quantum well laser diodes and semiconductor quantum well laser diodes made therefrom are also provided.
US09755399B2 Packaged laser thermal control system
A thermal stabilization system for a packaged diode laser. An outer thermoelectric cooler (TEC) stabilizes the temperature of the laser package and an inner TEC stabilizes the temperature of the laser diode element of the packaged laser. The inner and outer TECs may be controlled by electronics which is also stabilized in temperature, for example using resistive heating. The packaged laser may be mounted on a heat spreader mounted on the outer TEC and may be surrounded by an insulated covering on all sides other than the surface mounted on the heat spreader. There may also be a thermally conductive cap over the packaged laser, with the insulation arranged outside the cap if both are present.
US09755397B2 Light amplifying device and laser processing apparatus
A light amplifying device includes, a light amplifying fiber to amplify a seed beam from a seed light source with an excitation beam from an excitation light source, and a controller. The controller causes the seed light source to emit the seed beam in an emission period in which the light amplifying fiber outputs the amplified light beam, causes the excitation light source to emit the excitation beam having first-level power in a non-emission period immediately before the emission period, and changes the excitation beam power to a second level higher than the first level at a beginning of the emission period. The controller increases the excitation beam power to a third level higher than the second level after starting of the emission period, and decreases gradually the excitation beam power from the third level to the second level.
US09755396B1 EUV LPP source with improved dose control by combining pulse modulation and pulse control mode
A method and apparatus for control of a dose of extreme ultraviolet (EUV) radiation generated by a laser produced plasma (LPP) EUV light source that combines pulse control mode and pulse modulation. The EUV energy created by each pulse is measured and total EUV energy created by the fired pulses determined, a desired energy for the next pulse is determined based upon whether the total EUV energy is greater or less than a desired average EUV energy times the number of pulses. If the desired pulse energy for the next droplet is within the range of one or more pulse modulation actuators, the pulse is modulated; otherwise, the pulse is fired to miss the droplet. This provides greater control of the accumulated dose as well as uniformity of the EUV energy over time, greater ability to compensate for pulses that generate EUV energy that is higher or lower than nominal expected values, and ability to provide an average EUV energy per pulse that is less than the nominal minimum EUV energy per pulse of the system.
US09755395B2 Ring laser optical system
An optical system includes an output waveguide to propagate an optical output signal and a plurality of ring laser systems. Each of the plurality of ring laser systems includes a ring laser to generate a ring laser optical signal and a local waveguide. The ring laser can be optically coupled to the output waveguide to provide a first portion of the ring laser optical signal on the output waveguide as part of the optical output signal, and can be optically coupled to the local waveguide to provide a second portion of the ring laser optical signal on the local waveguide. Each of the plurality of ring laser systems can be to control a phase of the second portion of the ring laser optical signal to provide constructive interference with the ring laser optical signal at an optical coupling of the ring laser and the local waveguide.
US09755391B2 Crosstalk reduction in electrical interconnects
Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.
US09755390B2 Process for making biosensor
A process for making a biosensor comprising a hollow coil having wires coiled in parallel and an electronic circuit component connected to the coil, the process including: 1) providing a mandrel on which wires including at least a first wire, a second wire and a third wire are wound in parallel, 2a) immersing the mandrel in a first buffer solution comprising a first bioreceptor, a first monomer and optional additives, 2b) arranging the wires such that the first wire may be used as a working electrode, the second wire may be used as a counter electrode and the third wire may be used as a reference electrode of a three electrode electrochemical cell used in an electropolymerization process, 3) passing electric current through the first wire to form a first biocompatible coating of a first polymer polymerized from the first monomer comprising the first bioreceptor on the first wire, 4) removing the coil from the mandrel, 5) connecting the wires to their respective points of the electronic circuit component such that the first wire may be used as a working electrode, the second wire may be used as a counter electrode and the third wire may be used as a reference electrode and wherein the electronic circuit component is configured such that it can generate an input signal for a wireless receiver based upon the activity of the bioreceptor and wirelessly send the input signal to the wireless receiver.
US09755388B2 Reconfigurable plug strip
A power strip for conducting electrical power between an electrical power outlet having at least a live receptacle and a neutral receptacle, and at least two electrical device power plugs, each plug having at least a live prong and a neutral prong. The power strip includes a first housing segment having a first receptacle configured to receive at least an electrically conductive portion of a first device plug and a second housing segment having a second receptacle configured to receive at least an electrically conductive portion of a second device plug. The second housing is coupled to the first housing for pivotal movement relative to said first housing.
US09755387B2 Elevating mechanism and socket for electrical component
A socket for electrical component capable of pressing and fixing an electrical component.A pressing part includes a first cam rotatably supported by the body part, and a second cam supported by the first cam. An elevating part includes a cam locking part provided on a rotational orbit of the second cam. A tip of the second cam is formed such that the tip of the second cam passes over the cam locking part when the elevating part is moved down by making the tip of the second cam abut against the elevating part and rotate, and the tip of the second cam is locked by the cam locking part so as to prevent the rotation when an attempt is made to perform the rotation in the opposite direction. The rotation in the opposite direction is enabled by moving the second cam in the radial direction of the rotation.
US09755386B2 Device for contacting electrical conductors and/or electrical contact elements, as well as lamp or electrical device
The invention relates to a device 1 for contacting electrical conductors and/or electrical plug connectors, said device comprising at least one front housing part 2 and a rear housing part 3, wherein the front housing part 2 and the rear housing part 3 are formed as one unit, wherein at least one first electrical contact connection is provided in the front housing part via contacting points 7, and at least one additional electrical contact connection is provided in the rear housing part 3 via contacting points 9, wherein a step 6 is formed between the front housing part 2 and the rear housing part 3 on one side of the device 1, and wherein contacting points 8 are provided in the region of the step 6 for the purposes of electrical contacting. The invention also relates to a lamp or an electrical device having a device of this type.
US09755385B1 Electrical receptacle assembly
An electrical receptacle assembly, comprising a housing including a back, a plurality of sides, and a front opening; a face plate attached to the housing; a support flange attached to the housing; at least one electrical outlet attached to one of the plurality of sides; a connection member attached to the back, the connection member including a plurality of openings; and a securing member for releasable engagement with the connection member, the securing member including an engagement tab and an opening for a fastener The electrical receptacle assembly can be secured to a supporting surface in an open position by a combination of fasteners and the securing member.
US09755382B2 Connector system with interchangeable connector modules for optical fibers, electrical conductors, or both
A modular connector system for various types of different fiber optic and/or electrical connectors may include a connector having a housing configured to accommodate various different configurations of inserts that are configured to hold different types of either fiber optic connector, electrical connectors, or a combination of fiber optic and electrical connectors.
US09755381B2 Telecommunications patch panel with angled connector modules
A telecommunications patch panel is provided having a plurality of connector modules rotatably mounted to a frame member. Each connector module has a front face and an opposite facing rear face, and each front face includes a plurality of connector jacks. Each rear face includes a plurality of wire termination blocks. The wire termination blocks are electrically connected to the connector jacks. Each connector module is rotatable about a rotation axis relative to the frame member. A lock selectively locks each connector module to the frame member as desired. The connector jacks and the connector modules are arranged in linear arrays perpendicular to the axis of rotation.
US09755377B2 Connector
A connector includes an outer connection element and an inner connection element. One of the outer connection element and inner connection element includes a plurality of fingers extending at an angle relative to a longitudinal axis of the connector.
US09755374B2 Wall socket plates and signal boosters and systems and methods thereof
The invention relates generally to a wall socket plate for replacing existing wall sockets in one simple installation step. The wall socket plate obtains electric current from socket terminal screws to power a signal booster fluidly coupled to a wall socket plate. The signal booster is powered by transferring electric current from the socket terminal screws through conductive material to the signal booster, in accordance with the invention described herein.
US09755373B2 Smart card connection circuit of electronic device and electronic device
A smart card connection circuit of an electronic device which includes a card holder, a travel switch, and a switching unit; a contact of the travel switch is located in the card holder, and an output end of the travel switch is connected to a control end of the switching unit; and when a smart card at a preset position in the card holder leaves the preset position, the smart card leaves the contact of the travel switch, the travel switch controls the switching unit to switch to a second output end, and each signal cable pin on the card holder is grounded by using the switching unit before a power cable pin on the card holder is grounded by using the switching unit. The present invention is applied to electronic devices such as a mobile phone and a tablet computer.
US09755372B2 Board-connecting electric connector
The connection state of contact members with respect to a wiring board can be easily visually checked by a simple configuration. A shield wall portion composed of an electrically-conductive member opposed to contact connecting portions (board connecting portions) of a plurality of contact members arranged in a multipolar shape is provided; each of ground connecting portions provided in the shield wall portion is disposed at the part between the contact connecting portions, which are adjacent to each other; a lateral check window composed of the space which enables visual check of the contact connecting portions is formed in the interval region in which the ground connecting portions are adjacent to each other; an electromagnetic shielding function with respect to the contact connecting portions is obtained by the shield wall portion; and, at the same time, the connection state of the contact connecting portions with respect to the wiring board can be visually checked through the lateral check window provided in the shield wall portion.
US09755367B2 Charging inlet
A charging inlet (10) has an inlet body (20) including a first mounting plate (22) mounted on a body (B) of a vehicle. The first mounting plate (22) has fixed short collars (24), an indicator plate (30) including a second mounting plate (32) arranged between the body (B) and the first mounting plate (22) and having through holes (33) and fixing nuts (34) having the fixed portions (24) fixed thereto. The indicator plate (30) is mounted on the inlet body (20) by fixing the fixed portions (24) to the fixing portions (34). Long collars (23) project from the first mounting plate (22) toward the body (B) and penetrate the through holes (33) of the second mounting plate (32). Bolts (40) inserted into the tubular parts (23) fix the inlet body (20) to the body (B) with ends (23A) of the tubular parts (23) held in contact with the body (B).
US09755360B1 Connector guide assembly with a protruding member
Examples herein disclose a connector guide assembly. The connector guide assembly includes a connector frame and multiple protruding members. The connector frame includes multiple side walls. The multiple protruding members are coupled to the side walls of the connector frame such that the multiple protruding members extend substantially perpendicular to the connector frame and are located on opposing side walls of the connectors frame.
US09755358B2 Connector assembly
A connector assembly including a first connector, a second connector and a latch for connecting the first and second connectors. A securing lock is rotatable between a release position and a securing position securing the latch in a latching position. Optionally, the assembly includes a sliding guide and a resilient element forcing the securing lock to slide via the sliding guide into the securing position.
US09755354B1 Cord management device
A cord management device securable to objects lacking a cord management system. An embodiment includes a flexible substratum on which two outwardly facing hooks are secured in a longitudinally spaced manner. An embodiment further includes a receptacle adapted to receiving and temporarily house the prongs on an electrical cord. The flexible substratum preferably includes an adhesive, magnet or fastener to temporarily or permanently secure the device to objects. The device is thereby attachable to an object to aid in the securement of an electrical cord.
US09755352B2 Waterproofing structure for connector
A waterproofing structure for a connector includes a first housing having a first terminal reception chamber for receiving a terminal and a second housing having a second terminal reception chamber for receiving a terminal. An opening end of the first terminal reception chamber is opposed to an opening end of the second terminal reception chamber, so that a gap with which circumferential edges of the opening ends are opposed to each other is configured to be sealed. An annular member made of resin is provided at the circumferential edge of the opening end of the first terminal reception chamber, the annular member having an inner circumferential surface widened toward the second housing. The circumferential edge of the opening end of the second terminal reception chamber abuts against the inner circumferential surface of the annular member.
US09755350B2 Connector
A waterproof connector (10) includes a retainer (30) composed of divided bodies (31, 32), and a housing (11) including a retainer mounting portion (14) into which the retainer is to be mounted. The retainer mounting portion (14) includes a first mounting portion (16) into which a first of the divided bodies (31) is to be mounted and a second mounting portion (17) into which a second divided body (32) is to be mounted. The first and second divided bodies (31, 32) have facing surfaces (31A, 32A) facing each other. The first divided body (31) includes a projection (31C) that projects toward the second divided body (32) from the facing surface (31A) and a sensor detected portion (38) provided on a back surface (31B) adjacent to the facing surface (31A), and the second divided body (32) includes a recess (32B) into which the projection (31C) is to be fit.
US09755349B1 Connector assembly with blocking member
A connector assembly and system assembling an electric connector assembly are provided. The connector assembly includes a connector housing having a plurality of terminal cavities greater than the predetermined number of electric connections so as to define an empty terminal cavity and a filled terminal cavity. The connector housing further includes a blocking member. The blocking member is the blocking member disposed within each of the empty terminal cavities. Accordingly, the blocking member closes off each of the empty terminal cavities so as to prevent fluid transfer between the terminal positioning assurance member and the connector positioning assurance member so as to prevent fluid and debris transfer between the terminal positioning assurance member and the connector positioning assurance member, or stated in another way, prevents fluid and debris transfer between the first open end and the second open end.
US09755348B2 Waterproof electrical connector assembly
An electrical connector includes: a terminal module including an upper and lower module parts; a metallic plate positioned between the upper and lower module parts; an insulative base insert molding the upper and lower module parts with the metallic plate; a shielding shell enclosing the upper and lower module parts; and a fastener extending through the upper module part, the metallic plate, and the lower module part and beyond a bottom of the lower module part for mounting to a printed circuit board.
US09755343B2 Plated member and plated terminal for connector
It is aimed to provide a plated member and a plated terminal for connector, to which a large current can be applied and which have both a low friction coefficient and high heat resistance, at low cost and provide a method for producing such a plated member and a method for producing such a plated terminal for connector. A silver-tin alloy layer for coating a surface of a base material made of copper or copper alloy and a silver coating layer for coating the silver-tin alloy layer and to be exposed on an outermost surface are simultaneously formed by heating to obtain a plated member after tin and silver plating layers are alternately laminated on the surface of the base material with the outermost surface formed by the silver plating layer.
US09755339B2 Connecting structure of connector and flat circuit body
A connecting structure includes a flat circuit body, a slider that is attached to a vicinity of a distal end portion of the flat circuit body, and a connector which includes a slider containing portion and a terminal arrangement portion. When the slider is connected to the slider containing portion, conductors of the flat circuit body are electrically connected to the connection terminals of the terminal arrangement portion. The slider has a narrow width end portion whose width at the distal end is smaller than width of the flat circuit body so that side edges of the distal end of the flat circuit body are projected from the narrow width end portion. The slider containing portion has a positioning face which contacts with one of the side edges of the distal end of the flat circuit body.
US09755337B2 Waterproof board-to-board connectors
Board-to-board connectors that may provide durable and reliable connections, may save board space, and may be easy to manufacture. One example may provide board-to-board connectors that provide durable connections by providing a seal between board-to-board plugs and receptacles. The seal may be an O-ring, gasket, or other seal. The seal may protect contacts on the board-to-board connectors from exposure to fluids, such as water or other corrosive fluids. This seal may provide a level of redundancy with one or more seals protecting a device from external fluids, such as a seal at or in the device enclosure.
US09755334B2 Retention mechanism for shielded flex cable to improve EMI/RFI for high speed signaling
A retention apparatus for a shielded cable is described. In one embodiment, the apparatus comprises a substrate having a ground; a connector coupled to the substrate; a cable shielded with a conductive material and having an end connectable to the connector to electrically connect with the connector; an electrically conductive material coupled to the ground of the substrate; and a grounding retention mechanism to cause the electrically conductive material to electrically connect the cable to the ground of the substrate by applying a force to the cable shield.
US09755329B2 Superconducting cable connections and methods
Superconducting cable connector structures include a terminal body (or other structure) onto which the tapes from the superconducting cable extend. The terminal body (or other structure) has a diameter that is sufficiently larger than the diameter of the former of the superconducting cable, so that the tapes spread out over the outer surface of the terminal body. As a result, gaps are formed between tapes on the terminal body (or other structure). Those gaps are filled with solder (or other suitable flowable conductive material), to provide a current path of relatively high conductivity in the radial direction. Other connector structures omit the terminal body.
US09755326B2 Crimp terminal and terminal crimping device
A crimp terminal includes a terminal connecting portion, an electric wire connecting portion, and a coupling portion. The electric wire connecting portion is divided into a bottom placed on a recessed surface of a first die and on which an end of an electric wire is placed during the crimping process, a first barrel piece extending from a first end of the bottom and wound around the end of the electric wire, and a second barrel piece extending from a second end of the bottom and wound around the end of the electric wire. The bottom has a recess formed on an outer wall surface on the recessed surface side and into which a protrusion formed on the recessed surface is inserted during the crimping process, and a protrusion on an inner wall surface formed along with formation of the recess.
US09755318B2 Mesh reflector with truss structure
A reflector assembly includes a frame centered about a longitudinal axis and having a first height along the axis. A curved body extends from the frame and has a second height along the longitudinal axis could be greater than the first height. A stretchable membrane has an electromagnetically reflective surface and is secured to the curved body.
US09755316B2 Diffraction device intended to be fixed onto the outer face of a wall
An electromagnetic wave diffraction device for fixing onto an outer wall face comprising a plurality of electrically conductive resonant elements having an L-shaped profile fixed parallel on the outer face. Each element comprises a first and second wall secured at right angles to one another along a common edge. The first wall is fixed at a right angle to the outer face by a fixing edge parallel to the common edge. The second wall has a free edge parallel to the common edge. The free edges of all elements are parallel and arranged on the same side relative to the common edge of the corresponding element. A weather protection arrangement for reinforcing the protection of a capacitive area generated in a space between the outer face and the second wall, in the form of a water impermeable dielectric material panel, is fixed to the outer face and covers the elements.
US09755313B2 Chip antenna for near field communication and method of manufacturing the same
Provided are chip antennas for near field communication and methods of manufacturing the chip antennas. A chip antenna for near field communication includes a substrate; a first antenna element on the substrate; and a second antenna element on the first antenna element. The substrate, the first antenna element, and the second antenna element are included in a single chip. The first and second antenna elements are formed outside the chip. The substrate is a lower layer including a plurality of devices. The first antenna element is a metal structure having a fish bone shape. The second antenna element is a dipole antenna.
US09755312B2 Antenna device and manufacturing method for antenna device
The present application discloses antenna device including first and second antenna elements which communicate radio waves; housing which stores processor for processing signals in response to the radio waves; first and second element covers for storing first and second antenna elements, respectively. First element cover includes first rotary cylinder, which is held by housing and rotatable around first rotational axis, and first protruding cylinder, which protrudes from first rotary cylinder, first rotary cylinder protruding from housing along first rotational axis. Second element cover includes second rotary cylinder, which is held by housing and rotatable around second rotational axis, and second protruding cylinder, which protrudes from second rotary cylinder, second rotary cylinder protruding from housing along second rotational axis. First included angle between first and second protruding cylinders storing first and second antenna elements is changed by rotation of at least one of first and second rotary cylinders.
US09755311B2 Circularly polarized patch antennas, antenna arrays, and devices including such antennas and arrays
For use in a wireless network, an apparatus for use in a wireless network includes an antenna having (i) a first patch element with two opposite corners truncated and (ii) a first microstrip line connected to a first side of the first patch element and configured to feed the first patch element. The first microstrip line forms an angle of substantially 45° with the first side of the first patch element. The antenna could also include (i) a second patch element with two opposite corners truncated and (ii) a second microstrip line connected to a side of the second patch element. The second microstrip line could form an angle of substantially 45° with the side of the second patch element. The patch elements could be series-coupled and form an antenna array. One patch element could represent a host patch element, and another patch element could represent a parasitic patch element.
US09755307B2 Antenna structure and wireless communication device employing same
An antenna structure includes a feeding portion, a first grounding portion, a second grounding portion, a first radiating portion, a second radiating portion, a third radiating portion, and a fourth radiating portion. The feeding portion is configured to feed current signals. The first and second grounding portions are positioned at two opposite sides of the feeding portion respectively. The first, second and third radiating portions cooperatively form a first current path to excite a low-frequency resonate mode and a first high-frequency resonate mode; the first radiating portion resonates with the first grounding portion to excite a second high-frequency resonate mode; the second, third and fourth radiating portion cooperatively form a second current path to excite a third high-frequency resonate mode.
US09755305B2 Active antenna adapted for impedance matching and band switching using a shared component
An active antenna and associated circuit topology is adapted to provide active impedance matching and band switching of the antenna using a shared tunable component. Using a shared tunable component, such as a tunable capacitor or other tunable component, the antenna provides a low cost and effective active antenna solution. In certain embodiments, one or more passive components can be further utilized to design band switching of the antenna from a first frequency to a second desired frequency.
US09755301B2 Circularly polarized compact helical antenna
The present invention relates to a circularly polarized directional helical antenna that is capable of being used in RFID devices and more particularly in RFID readers. The antenna is intended to transmit or receive signals in a predetermined frequency band, λ being the wavelength associated with the minimum frequency of the predetermined frequency band. It includes a helicoidal radiating element made of conductive material extending along a longitudinal axis (A) and the axial length (H) of which is less than the wavelength λ, and a cavity made of conductive material having an open end and a closed end and having an axis of symmetry that coincides with the longitudinal axis of the radiating element, at least one lower portion of the radiating element being arranged inside the cavity so that its lower end is in contact with the closed end of the cavity.
US09755292B2 Same-band combiner for co-sited base stations
The invention is a compact three-port signal combiner suitable for use in a base station having two different wireless systems. The combiner is designed as a four-port network, but one of the ports is terminated with a predetermined load, thus leaving three ports for connection to user equipment. A first port (A) receives from an antenna a first input signal comprising first and second receive bands and transmits to the antenna a first output signal comprising a transmit band. A second port (R), connected to the first wireless system, outputs to the first wireless system a second output signal comprising the first and second receive bands. A third port (T\R) outputs, to the second wireless system, a third output signal comprising the first and second receive bands and receives from the second wireless system a second input signal that is to be transmitted from the first port.
US09755288B2 Methods and devices for integrating radio frequency and other signals within a conductor
Non-coaxial conductors, such as direct current power conductors, may be inserted into, or separated from, a central section of a radio frequency (RF) coaxial conductor that is supplying RF signals.
US09755287B2 Frequency demultiplexer
A frequency demultiplexer comprising an input part (106) with an input port (101), a low pass filter (125) and a band-pass filter (108) with output ports (120, 145). The input part (106), the low-pass filter (125) and the band-pass filter (108) comprise open waveguide sections, and the band-pass filter (108) comprises gap-coupled resonators (130, 135, 140). The input part (106) and the low-pass filter (125) connect to the same resonator (130), the connection (121) of the low-pass filter (125) being at a first maximum distance (L1) from a center point (N) of the resonator and the connection (116) of the output port (101) being at a second maximum distance (L2) from said center point (N) of the resonator. The center point (N) corresponds to a wave node of a wavelength λ, where λ=2d/M, M is a positive integer value and d is the shortest end-to-end distance along the resonator.
US09755285B2 Frame for secondary battery and battery module comprising the same
In the present disclosure, disclosed are a frame for secondary batteries, which prevents gas from flowing into a cooling channel or a duct connected to it, when such gas is generated from secondary batteries; and a battery module comprising the same. A frame for secondary batteries according to the present disclosure comprises: an upper cooling plate which is plate-shaped and made of thermally conductive material; a lower cooling plate which is plate-shaped and made of thermally conductive material and is placed spaced apart from the upper cooling plate by a predetermined distance to face the upper cooling plate so that a channel is formed in a space between the upper cooling plate and the lower cooling plate; and a main frame which comprises four unit frames with both ends being connected to each other, encompasses the outer peripheral portions of the upper cooling plate and the lower cooling plate, allows an outer peripheral portion of a pouch-type secondary battery to be mounted thereon, comprises openings formed in the side surfaces of two of the unit frames for the channel to be opened, and has uneven parts, corresponding to each other, respectively formed on upper and lower portions of at least two of the unit frames.
US09755279B2 Battery protection circuit module and battery pack including the same
A battery protection circuit module and battery pack including the same are disclosed. In one aspect, the battery pack includes a first battery cell including a pair of first electrode tabs, a battery protection circuit module, and a frame accommodating the first battery cell and the battery protection circuit module. The battery protection circuit module includes a printed circuit board (PCB) having a first recess formed in a first side thereof and a pair of first tabs that are separated from each other, wherein each of the first tabs at least partially overlaps the first recess. The battery protection circuit module also includes a first temperature protection device having one end thereof electrically connected to one of the first tabs and the other end thereof electrically connected to the other first tab and a pair of first connection units respectively electrically connected to the first electrode tabs.
US09755278B2 Cable-type secondary battery and preparation thereof
The present disclosure provides a cable-type secondary battery, comprising: an inner electrode; and a sheet-form laminate of separation layer-outer electrode, spirally wound to surround the outer surface of the inner electrode, the laminate being formed by carrying out compression for the integration of a separation layer for preventing a short circuit, and an outer electrode.According to the present disclosure, the electrodes and the separation layer are compressed and integrated to minimize ununiform spaces between the separation layer and the outer electrode and reduce the thickness of a battery to be prepared, thereby decreasing resistance and improving ionic conductivity within the battery. Also, the separation layer coming into contact with the electrodes absorbs an electrolyte solution to induce the uniform supply of the electrolyte solution into the outer electrode active material layer, thereby enhancing the stability and performances of the cable-type secondary battery.
US09755276B2 Liquid electrolyte for fluoride ion battery and fluoride ion battery
An object of the present invention is to provide a liquid electrolyte for a fluoride ion battery with improved fluoride ion stability. By providing a liquid electrolyte for a fluoride ion battery comprising a fluoride salt and a diol compound in which one or two ether bonds are disposed between two OH groups, the present invention achieves the aforementioned object.
US09755275B2 Rechargeable lithium battery
A rechargeable lithium battery includes a negative electrode including a negative active material including a Si-based material, a positive electrode, and an electrolyte including a lithium salt, an organic solvent, and an additive including lithium triflate and fluoroethylene carbonate. Embodiments of the rechargeable lithium battery have excellent irreversible characteristics and cycle-life characteristics.
US09755272B2 Process for manufacturing a monolithic all-solid-state battery
An all-inorganic, all-solid-state monolithic Li-ion battery, the monolithic body having a plurality of elementary cells, and which is produced by producing dense electrode deposits directly on the two faces of a substrate acting as a battery current collector, and by depositing an all-solid-state dense electrolyte layer on at least one of the dense electrode deposits obtained.
US09755271B2 Cell and preparation method thereof
The present disclosure provides a cell and a preparation method thereof. The cell comprises a positive electrode plate (1); a negative electrode plate (2) and a composite solid electrolyte membrane (3) positioned between the positive electrode plate (1) and the negative electrode plate (2). The composite solid electrolyte membrane (3) comprises inorganic solid electrolyte layers (31) and structure supporting layers (32) which are alternately laminated along a laminating direction (D), and has abutted surfaces (S1) respectively abutting against the positive electrode plate (1) and the negative electrode plate (2), an angle between the laminating direction (D) and the abutted surface (S1) is defined as α, and 0°≦α<90°. The composite solid electrolyte membrane not only plays an advantage of a high lithium ionic conductivity of the inorganic solid electrolyte, but also has an excellent mechanical processing property, thereby significantly improving electrochemical performance and safety performance of the cell.
US09755270B2 Sodium secondary battery including graphite felt having pore channels formed therein
Provided is a sodium secondary battery including: a sodium ion conductive solid electrolyte separating an anode space and a cathode space from each other; an anode positioned in the anode space and containing sodium; a cathode solution positioned in the cathode space; and a cathode immersed in the cathode solution and including graphite felt formed with open pore channel of which an opening part is formed on a surface of the graphite felt facing the solid electrolyte.
US09755268B2 Gel electrolytes and electrodes
Gel electrolytes, especially gel electrolytes for electrochemical cells, are generally described. In some embodiments, the gel electrolyte layers comprise components a) to c). Component a) may be at least one layer of at least one polymer comprising polymerized units of: a1) at least one monomer containing an ethylenically unsaturated unit and an amido group and a2) at least one crosslinker. Component b) may be at least one conducting salt and component c) may be at least one solvent. Electrodes may comprise the components a), d) and e), wherein component a) may be at least one layer of at least one polymer as described herein. Component d) may be at least one electroactive layer and component e) may be at least one ceramic layer. Furthermore, electrochemical cells comprising component a) which may be at least one layer of at least one polymer as described herein, are also provided.
US09755267B2 Cable-type secondary battery
The present disclosure provides a cable-type secondary battery, comprising: an inner electrode; a separation layer surrounding the outer surface of the inner electrode to prevent a short circuit between electrodes; and a sheet-form outer electrode spirally wound to surround the separation layer or the inner electrode.
US09755263B2 Fuel cell mechanical components
A modular fuel cell system includes a metal base, a plurality of power modules arranged in a row on the base, a fuel processing module and a power conditioning module arranged on at least one end of the row on the base. Each of the plurality of power modules includes a separate cabinet comprising at least one fuel cell stack located in a hot box. The power modules are electrically and fluidly connected to the fuel processing and the power conditioning modules through the base.
US09755262B2 Resin panel structure
A resin panel structure capable of improving positioning precision of a resin panel is provided. A resin panel structure includes a fiber reinforced plastic upper panel, a fiber reinforced plastic lower panel disposed below the upper panel, a fiber reinforced plastic core panel that is installed between the upper panel and the lower panel and joined to the upper panel and the lower panel, and includes an opening into which a portion of the upper panel or a portion of the lower panel is inserted, and a joining member that joins the upper panel or the lower panel that is inserted into the opening, and the other of the upper panel or the lower panel, together.
US09755258B2 Integrated power generation and chemical production using solid oxide fuel cells
In various aspects, systems and methods are provided for operating a solid oxide fuel cell at conditions that can improve or optimize the combined electrical efficiency and chemical efficiency of the fuel cell. Instead of selecting conventional conditions for maximizing the electrical efficiency of a fuel cell, the operating conditions can allow for output of excess synthesis gas and/or hydrogen in the anode exhaust of the fuel cell. The synthesis gas and/or hydrogen can then be used in a variety of applications, including chemical synthesis processes and collection of hydrogen for use as a fuel.
US09755255B2 Apparatus and method for fuel cell start from freezing without melting ice
Fuel cell systems and related methods involving accumulators with multiple regions of differing water fill rates are provided. At least one accumulator region with a relatively more-rapid fill rate than another accumulator region is drained of water at shutdown under freezing conditions to allow at least that region to be free of water and ice. That region is then available to receive water from and supply water to, a fuel cell nominally upon start-up. The region having the relatively more-rapid fill rate may typically be of relatively lesser volume, and may be positioned either relatively below or relatively above the other region(s).
US09755254B2 Procedure for detecting the state of permeability of the ion exchange polymer membrane of a fuel cell
An automated method or procedure for detecting a permeability state of a membrane of a fuel cell stack is provided. The procedure is sensitive enough to detect a defective membrane, and is accurate enough to enable correct maintenance of the fuel cell stack. The fuel cell stack is formed of a stack of electrochemical cells each having an anode and a cathode sandwiching a polymeric ion-exchange membrane therebetween. The fuel cell stack includes a fuel gas supply system on the anode side of the electrochemical cells, and includes an oxidant gas supply system on the cathode side of the electrochemical cells.
US09755237B2 Negative-electrode active material for sodium-ion secondary battery, method for manufacturing said negative-electrode active material, and sodium-ion secondary battery
A negative-electrode active material for a sodium-ion secondary battery contains a porous carbon material which has a plurality of open pores that extend through to the surface, a plurality of closed pores that do not extend through to the surface, and a solid portion made of carbon material. The distance between (002) planes of carbon in at least a part of the solid portion is 0.36 nm or more. The plurality of closed pores account for a volume ratio of not less than 30% and not more than 90% with respect to a total volume of the plurality of open pores, the plurality of closed pores, and the solid portion.
US09755236B2 Dendrite-intercepting layer for alkali metal secondary battery
A dendrite penetration-resistant layer for a rechargeable alkali metal battery, comprising multiple graphene sheets or platelets or exfoliated graphite flakes that are chemically bonded by a lithium- or sodium-containing species to form an integral layer that prevents dendrite penetration through the integral layer, wherein the lithium-containing species is selected from Li2CO3, Li2O, Li2C2O4, LiOH, LiX, ROCO2Li, HCOLi, ROLi, (ROCO2Li)2, (CH2OCO2Li)2, Li2S, LixSOy, Na2CO3, Na2O, Na2C2O4, NaOH, NaX, ROCO2Na, HCONa, RONa, (ROCO2Na)2, (CH2OCO2Na)2, Na2S, NaxSOy, or a combination thereof, wherein X=F, Cl, I, or Br, R=a hydrocarbon group, x=0-1, y=1-4. Also provided is a process for producing a dendrite penetration-resistant layer based on the principle of electrochemical decomposition of an electrolyte in the presence of multiple graphene sheets.
US09755234B2 Method for preparing lithium iron phosphate nanopowder
The present invention relates to a method for preparing a lithium iron phosphate nanopowder, including the steps of (a) preparing a mixture solution by adding a lithium precursor, an iron precursor and a phosphorus precursor in a triethanolamine solvent, and (b) putting the mixture solution into a reactor and heating to prepare the lithium iron phosphate nanopowder under pressure conditions of 10 bar to 100 bar, and a lithium iron phosphate nanopowder prepared by the method. When compared to a common hydrothermal synthesis method and a supercritical hydrothermal synthesis method, a reaction may be performed under a relatively lower pressure. When compared to a common glycothermal synthesis method, a lithium iron phosphate nanopowder having effectively controlled particle size and particle size distribution may be easily prepared.
US09755233B2 Nonaqueous electrolyte battery and battery pack
According to one embodiment, a nonaqueous electrolyte battery includes a positive electrode, a negative electrode and a nonaqueous electrolyte. The positive electrode includes a first positive electrode active material which is represented by general formula LiMSO4F (M is at least one kind of element selected from the group consisting of Fe, Mn and Zn) and has a triplite type crystal structure, and a second positive electrode active material which is represented by general formula LiM′SO4F (M′ is at least one kind of element selected from the group consisting of Fe, Mn and Zn) and has a tavorite type crystal structure.
US09755231B2 Method of preparing iron oxide nanoparticles
Provided are a method of preparing iron oxide nanoparticles, iron oxide nanoparticles prepared thereby, and an anode material including the iron oxide nanoparticles.
US09755229B2 Intermetallic M—Sn5 (M=Fe, Cu, Co, Ni) compound and a method of synthesis thereof
Novel intermetallic materials are provided that are composed of tin and one or more additional metal(s) having a formula M(1-x)-Sn5, where −0.1≦x≦0.5, with 0.01≦x≦0.4 being more preferred and the second metallic element (M) is selected from iron (Fe), copper (Cu), cobalt (Co), nickel (Ni), and a combination of two or more of those metals. Due to low concentration of the second metallic element, the intermetallic compound affords an enhanced capacity applicable for electrochemical cells and may serve as an intermediate phase between Sn and MSn2. A method of synthesizing these intermetallic materials is also disclosed.
US09755228B2 Lithium metal electrode
A lithium metal electrode is disclosed in this invention. The lithium metal electrode includes a lithium metal layer, a plurality of gate layers and a current collector layer having a plurality of holes. The gate layers are disposed corresponding to the holes. The lithium metal layer and the gate layers are disposed correspondingly. The lithium metal layer is insulated via the gate layers and/or the current collector layer before formation. While the gate layers are alloyed with the lithium ions from the media such as the electrolyte, the alloyed gate layers may provide the ionic access for the lithium metal layer so that the lithium metal layer may feedback the lithium ions back to the chemical system of the electricity supply system. Also, at the same time, the potentials of all the gate layers may be kept equally to the potential of the lithium metal layer.
US09755223B2 Treatment process for a positive electrode active material for lithium-ion secondary battery
In a treatment process for a positive electrode active material for a lithium-ion secondary battery, Li compounds such as Li2CO3, LiOH, and the like, present in a positive electrode active material for a lithium-ion secondary battery but unsuitable for a positive electrode material, is removed. In a case wherein the resultant Li compound is used as a positive electrode material of the secondary battery, a discharge capacity and an average discharge voltage of the secondary battery do not decline, and gelation caused by a cleaning treatment is prevented. The positive electrode active material is cleaned with a cleaning fluid containing NH3, and then solid-liquid separation is performed, and a solid component is calcined at 600 to 700° C. in an oxygen atmosphere. The cleaning fluid has a conductivity of 11.6 mS/cm or less, and contains a recovered liquid component and may be repeatedly used as a cleaning fluid.
US09755221B2 Co-extruded conformal battery separator and electrode
A co-extrusion print head has at least one separator inlet port, at least a first, second and third series of channels arranged to receive a separator material from the separator inlet port, at least one electrode inlet port, a fourth series of channels arranged to receive an electrode material from the electrode inlet port, a first merge portion connected to the first, second, third and fourth series of channels, the merge portion positioned to receive and merge the separator material into a separator flow and the electrode material into an electrode flow, a second merge portion connected to the first merge portion, the second merge portion positioned to receive and merge the separator flows and the electrode flows, and an outlet port connected to the second merge portion, the outlet port arranged to deposit the separator and electrode materials from the merge portion as a stack on a substrate.
US09755219B2 Electrical storage apparatus
An electricity storage device includes an electrode assembly having primary electrodes and secondary electrodes, a case having a wall with an inlet, and an insulator. The electrode assembly has a facing surface facing the wall of the case. The primary electrodes have primary tabs protruding from one edge. The second electrodes have secondary tabs. The group of primary tabs and the group of secondary tabs each have a first side and a second side on the opposite sides. In each of the group of primary tabs and the group of secondary tabs, the first side faces the facing surface, and the second side is bent to face the wall of the case. The inlet is located at a position sandwiched regions of the wall onto which the primary tab group and the secondary tab group are projected when the wall is viewed from a direction perpendicular to the facing surface.
US09755213B2 Cathode including insulation layer on cathode tab and secondary battery including the cathode
Provided is a cathode including a cathode current collector, a cathode tab protruding from the cathode current collector, and an insulation layer coated with an insulating material on the cathode tab, and a secondary battery including the cathode. Since the cathode of the present invention includes an insulation layer on a cathode tab, the present invention may prevent an internal short circuit which may occur due to cell deformation or sharp edges of electrodes, which are formed during cutting of the electrodes in a preparation process of the battery, when the electrodes are stacked, or may prevent a physical short circuit between the cathode and the anode due to shrinkage of a separator in a high-temperature atmosphere. In a case where the cathode is used in a lithium secondary battery, safety and reliability in battery performance may be significantly improved.
US09755210B2 Battery pack and method for controlling charge of battery pack
A battery pack according to the present disclosure includes a battery cell including at least one unit cell, a first connector which is electrically connected to the battery cell, and a second connector which is electrically connected to the battery cell and the first connector, the second connector having a corresponding shape to the first connector to be coupled with the first connector.According to the present disclosure, a plurality of battery packs may be concurrently charged, and when needed, a battery capacity may be increased by easily connecting a plurality of battery packs, thereby ensuring a sufficient usage time of an electronic appliance.
US09755209B2 Method for grouping lithium secondary battery packs
A method for grouping lithium secondary battery packs comprises the following steps: charging and discharging a battery for 1-3 cycles, recording the last discharge capacity C0, setting a capacity lower limit, and determining the battery with the C0 thereof not less than the capacity lower limit to be an eligible battery; discharging the battery to a discharge cut-off voltage Vd so the battery is discharged to a power empty state; charging the empty battery to a capacity C1; storing the battery for time t1 in an environment with a temperature ranging between 20-50° C., recording the battery voltage V1, storing the battery again for time t2 in the environment with the temperature ranging between 20-50° C., recording the battery voltage V2, calculating a voltage difference ΔV=V2−V1 and setting the range of ΔV; and grouping eligible batteries in a previous step according to a certain capacity grouping standard.
US09755208B2 Non-aqueous-secondary-battery separator and non-aqueous secondary battery
Provided is a non-aqueous-secondary-battery separator including: a microporous membrane; and an adhesive porous layer which is provided on one or both surfaces of the microporous membrane and includes a fibrillar polyvinylidene fluoride resin, in which an average hole diameter acquired from the specific surface area of the microporous membrane is greater than 90 nm and equal to or smaller than 250 nm, peeling strength between the microporous membrane and the adhesive porous layer is equal to or greater than 0.10 N/cm, and a fibrillar diameter acquired from the specific surface area of the adhesive porous layer is from 50 nm to 70 nm.
US09755207B2 Pressure-sensitive adhesive tape for battery and battery using the pressure-sensitive adhesive tape
The present invention relates to a pressure-sensitive adhesive tape for battery containing: a substrate; and a pressure-sensitive adhesive layer provided on at least one side of the substrate, in which the pressure-sensitive adhesive tape has a thickness change ratio of 20% or less after immersion in a mixed solvent of ethylene carbonate/diethyl carbonate [former/latter (volume ratio)=1/1] at 60° C. for 8 hours; and a 180° peeling adhesive strength (against aluminum foil, peel temperature: 25° C., peel rate: 300 mm/minute) of 0.5 N/10 mm or more after the above immersion.
US09755202B2 Battery pack of electric vehicle, electric vehicle chassis and method for replacing battery modules
Provided are systems and methods for configuring battery packs in electric vehicles. A battery pack may include a plurality of battery modules, a support part, and at least one opening provided on the support part. The support part may be provided with a bottom for supporting the plurality of battery modules, sides, a top, and an accommodation space formed by the bottom, the sides, and the top for accommodating the plurality of battery modules. The opening provided on the bottom of the support part may enable the plurality of battery modules to be passed through the at least one opening and be detachably mounted to the bottom of the support part so as to be supported by the bottom.
US09755200B2 Equipment cabinet
An equipment cabinet having a corrugation in the side panels is disclosed. The panels are affixed to a base by bolting or welding so as to be disposed opposite each other. Holes are provided in opposing surfaces the so that cross members may be secured in a position between the opposing side panels of the cabinet to form a support structure for equipment, such as batteries. Equipment may also be attached using mounting brackets. An equipment retaining bracket includes a retaining cross member, an L-shaped bracket and a bolt to joint the retaining cross member and the L-shaped bracket so as to secure the battery in two dimensions. Retaining brackets may be provided at the front and the rear surfaces of the equipment and, in cooperation with the cross members, retain the equipment in the cabinet.
US09755198B2 Battery cell assembly
A battery cell assembly is provided. The battery cell assembly includes a first frame assembly having a first substantially rectangular ring-shaped frame and a first coupling member. The first coupling member of the first frame assembly has a first tongue portion with first and second resilient arm members. The battery cell assembly further includes a second frame assembly having a second substantially rectangular ring-shaped frame and a first coupling member. The first coupling member of the second frame assembly has a female member with a first aperture such that the first and second resilient arm members extend through the first aperture and engage an engagement surface defined by the female member of the first coupling member of the second frame assembly.
US09755197B2 Nonaqueous electrolyte secondary battery
Provided is a nonaqueous electrolyte secondary battery including a bottomed cylindrical positive electrode casing and a negative electrode casing which is fixed to an opening of the positive electrode casing through a gasket. The opening of the positive electrode casing is caulked to the negative electrode casing side to seal the accommodation space. A diameter d is in a range of 6.6 mm to 7.0 mm, and a height h1 is in a range of 1.9 mm to 2.3 mm. A shortest distance L1 between a caulking tip end and the negative electrode casing in the opening of the positive electrode casing is equal to or less than 110% of an average sheet thickness of the positive electrode casing, a shortest distance L2 between a tip end of the negative electrode casing and the positive electrode casing is equal to or less than 100% of the average sheet thickness of the positive electrode casing, and a distance L3 between the tip end of the negative electrode casing and the bottom of the positive electrode casing is equal to or less than 75% of the average sheet thickness of the positive electrode casing.
US09755194B2 Method for producing a battery with a metallic housing and an electrical insulation layer covering the outside of the housing, and battery produced by the method
A method is disclosed for producing a battery with a metallic housing and an electrical insulation layer covering the outside of the housing. The method includes: providing a metallic housing or housing part for a battery; corona treating the outside of the housing or of the housing part, with simultaneous extraction of the gases and particles which arise; and applying the electrical insulation layer onto the treated outside of the housing or housing part.
US09755191B2 Method and apparatus for manufacturing organic electroluminescent element, and organic electroluminescent module
Disclosed is a method for manufacturing an organic EL element, which has, on a supporting substrate, at least one intermediate electrode layer, and at least two light emitting units, each of which has one or a plurality of organic functional layers, the intermediate electrode layer being disposed between the light emitting units. The method is characterized in having: a first patterning step wherein at least one organic functional layer of each of the light emitting units is patterned using a mask; and a second patterning step wherein at least one organic functional layer in each of the light emitting units is patterned into, by means of light irradiation, a region where a light emitting function is modulated, and a region where the light emitting function is not modulated. The method is also characterized in that the second patterning step is performed for each light emitting unit that is manufactured.
US09755183B2 Organic light emitting display device and method for manufacturing the same
Disclosed is an organic light emitting display device that includes a foreign matter compensation layer on an inorganic layer. A passivation layer and a second inorganic layer are in direct contact with each other at the edge of the substrate. Accordingly, the number of interfaces between the inorganic layers is decreased. Thus, even if the organic light emitting display device is bent, a moisture permeation path, which may be unexpectedly formed, can be minimized.
US09755180B2 Light emitting device
A light emitting device (10) includes a substrate (100), an organic EL element (102), a buffer film (210), and a sealing film (220). The organic EL element (102) is formed over the substrate (100). The sealing film (220) is located over the substrate (100) and over the organic EL element (102), and seals the organic EL element (102). In addition, the buffer film (210) is located between the organic EL element (102) and the sealing film (220), and comes into close contact with the sealing film (220). The sealing film (220) includes at least one layer formed of, for example, an oxide.
US09755177B2 Organic electroluminescent display panel
The organic EL display panel includes: an active matrix substrate including a thin-film transistor; and an organic EL element disposed on the active matrix substrate, the organic EL element including, in the order from the active matrix substrate side, a cathode electrically connected to the thin-film transistor, a first charge conversion layer in contact with the cathode, a first hole injection layer, a first hole transport layer, a first light-emitting layer, a first electron transport layer, a first electron injection layer, a second charge conversion layer, and an anode in contact with the second charge conversion layer, the first charge conversion layer designed to inject electrons into the cathode and emit holes to the first light-emitting layer side, the second charge conversion layer designed to inject holes into the anode and emit electrons to the first light-emitting layer side.
US09755174B2 Light-emitting element, display element, display device, electronic device, and lighting device
A light-emitting element with high emission efficiency which includes a plurality of light-emitting layers and exhibits multi-color light emission is provided. The light-emitting element includes a first electrode, a second electrode, and an EL layer between the first electrode and the second electrode. The EL layer includes a first injection layer, a first light-emitting layer, and a second light-emitting layer in a first region, and a second injection layer, the first light-emitting layer, and the second light-emitting layer in a second region. The first light-emitting layer includes a first light-emitting material and a first host material, and the second light-emitting layer includes a second light-emitting material and a second host material. A color of light emitted from the first region is different from that of light emitted from the second region.
US09755173B2 Optoelectronic component, method for producing an optoelectronic component
An optoelectronic component is provided. The optoelectronic component includes an electromagnetic radiation source including an optically active region designed for emitting a first electromagnetic radiation, and a converter structure, which includes at least one converter material and is arranged in the beam path of the first electromagnetic radiation. The at least one converter material is designed to convert at least one portion of the first electromagnetic radiation into at least one second electromagnetic radiation. The at least one second electromagnetic radiation has at least one different wavelength than the at least one portion of the first electromagnetic radiation. The converter structure is formed in a structured fashion in such a way that the converter structure has a predefined region, such that the at least one second electromagnetic radiation is emittable only from the predefined region. The predefined region has a smaller area than the optically active region.
US09755168B2 Display apparatus and electronic apparatus
Disclosed herein is a display apparatus, including: a foldable substrate; a pixel array section including a plurality of pixels disposed on the substrate and each including an electro-optical device; the foldable substrate being folded at a substrate end portion at least on one side thereof around the pixel array section; a peripheral circuit section disposed on the substrate end portion and adapted to drive the pixels of the pixel array section; and a pad section provided on the substrate end portion on which the peripheral circuit section is provided and adapted to electrically connect the peripheral circuit section to the outside of the substrate.
US09755167B2 Light-emitting device
A novel light-emitting device that is highly convenient or reliable is provided. The light-emitting device includes a framework, a flexible first light-emitting panel supported by the framework so as to form a first developable surface, and a flexible second light-emitting panel supported by the framework so as to form a second developable surface.
US09755164B2 Organic electroluminescent materials and devices
Novel heteroleptic iridium carbene complexes are provided, which contain at least two different carbene ligands. Selective substitution of the carbene ligands provides for phosphorescent compounds hat are suitable for use in a variety of OLED devices.
US09755162B2 Organic light emitting device and display device
An organic light emitting device and a display device is provided. The organic light emitting device includes an anode, a cathode, and a light emitting layer disposed between the anode and the cathode; an electron transport layer disposed between the cathode and the light emitting layer, and the material of the electron transport layer is an organic metal chelate.
US09755160B2 Thin film transistor
Provided is a thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer provided between the gate electrode and the semiconductor layer and formed of an organic polymer compound, and a source electrode and a drain electrode provided in contact with the semiconductor layer and connected via the semiconductor layer, on a substrate, in which the content of metals selected from Mg, Ca, Ba, Al, Sn, Pb, Cr, Mn, Fe, Ni, Cu, Zn, and Ag in the gate insulating layer is 10 ppb to 1 ppm in terms of total amount, or the content of non-metal ionic materials selected from halogen ions, sulfate ions, nitrate ions, and phosphate ions is 1 ppm to 100 ppm in terms of total amount.
US09755158B2 Organic light-emitting device
An organic light-emitting device including a first electrode; a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; and an electron transport region between the second electrode and the emission layer, wherein the electron transport region includes at least one first compound represented by the following Formula 1, at least one second compound represented by the following Formula 2, and at least one third compound represented by the following Formula 30:
US09755156B2 Oxygen-containing fused ring amine compound, sulfur-containing fused ring amine compound and organic electroluminescence device
A fused amine compound including a furan ring or a thiophene ring and an organic electroluminescence device employing the amine compound. The organic electroluminescence device includes a cathode, an anode, and one or more organic thin film layers which are disposed between the cathode and the anode. The organic thin film layers include a light emitting layer and at least one layer of the organic thin film layers includes at least one amine compound.
US09755151B2 Organic semiconductors
An optoelectronic device comprising a charge transfer layer including a first semiconductive polymer comprising one or more zwitterions.
US09755150B2 Functionalized nanostructures and related devices
Embodiments described herein provide functionalized carbon nanostructures for use in various devices, including photovoltaic devices (e.g., solar cells). In some embodiments, carbon nanostructures substituted with at least one cyclobutyl and/or cyclobutenyl group are provided. Devices including such materials may exhibit increased efficiency, increased open circuit potential, high electron/hole mobility, and/or low electrical resistance.
US09755147B2 Ink for forming functional layer, method of manufacturing ink for forming functional layer, and method of manufacturing organic electro-luminescence element
An ink for forming a functional layer, which is used when any thin film layer among functional layers consisting of a plurality of thin film layers is formed, includes a functional layer forming material and a solvent for dissolving the functional layer forming material, and in which the number of particles of 0.5 μm or more is 7 or less in 10 ml of the ink for forming a functional layer.
US09755141B2 Method for fabricating MRAM bits on a tight pitch
A method for fabricating magnetoresistive random access memory (MRAM) devices on a tight pitch is provided. The method generally includes etching a pattern of columns into a hardmask layer disposed on a magnetic tunnel junction (MTJ) disposed on a substrate having electrically conductive contacts, the MTJ comprising a tunnel barrier layer between first and second ferromagnetic layers, the pattern of columns aligned to the electrically conductive contacts; etching the first ferromagnetic layer to expose the tunnel barrier layer and to form columns comprising the hardmask layer and the first ferromagnetic layer; forming a passivation layer on the exposed tunnel barrier layer and on top side surfaces of the columns; and etching the passivation layer on the exposed tunnel barrier layer, the exposed tunnel barrier layer, and the second ferromagnetic layer to form columns comprising the hardmask layer, the first ferromagnetic layer, the tunnel barrier layer, and the second ferromagnetic layer.
US09755140B2 Multilayered magnetic thin film stack and nonvolatile memory device having the same
A multilayered magnetic thin-film stack including a tunneling barrier layer; a magnetic finned layer formed on a first surface of the tunneling barrier layer; and a magnetic free layer formed on a second surface of the tunneling barrier layer, which is opposite to the first surface, wherein at least one of the magnetic finned layer and the magnetic free layer includes a FeZr alloy layer and a first magnetic layer having a (001) bcc structure between the FeZr alloy layer and the tunneling barrier layer.
US09755138B2 Method for producing an electronic component
A method for producing an electronic component includes providing a piezoelectric main body, which is provided with electrodes. A first electric polarization field having a first polarity direction is applied to the piezoelectric main body between the two electrodes and then a second electric polarization field is applied in a second polarity direction, opposite to the first polarity direction, to the piezoelectric main body between the electrodes. The absolute value of the second electric polarization field differs from that of the first electric polarization field.
US09755136B2 Piezoelectric material, piezoelectric element, and electronic apparatus
Provided is a lead-free piezoelectric material having satisfactory and stable piezoelectric constant and mechanical quality factor in a wide practical use temperature range. The piezoelectric material includes a perovskite-type metal oxide represented by Formula (1): (Ba1−xCax)a(Ti1−yZry)O3 (wherein, 1.00≦a≦1.01, 0.125≦x≦0.300, and 0.041≦y≦0.074), Mn, and Mg. The content of Mn is 0.12 parts by weight or more and 0.40 parts by weight or less based on 100 parts by weight of the perovskite-type metal oxide on a metal basis. The content of Mg is 0.10 parts by weight or less (excluding 0 part by weight) based on 100 parts by weight of the perovskite-type metal oxide on a metal basis.
US09755135B1 Highly electroactive materials and highly electroactive actuators that act as artificial muscle, tendon, and skin
This invention describes a method for producing a novel, superior, highly electroactive material and highly electroactive actuator, which act as artificial muscle, tendon, fascia, perimysium, epimysium, and skin that wrinkles and with the preferred movement of contraction, comprising ion-containing, cross-linked electroactive material(s); solvent(s); electrode(s); attachments to levers or other objects; and coating(s). The composition and electrode configuration of the highly electroactive material of the highly electroactive actuator can be optimized so that contraction occurs when activated by electricity, and when allowed to relax back to its original conformation or when the polarity of the electrodes is reversed, expansion occurs, and a combination of these movements can be arranged, such as antagonistic pairs. The highly electroactive material itself or the highly electroactive actuator may be used individually or grouped to produce movement when activated by electricity. This invention can provide for human-like motion, durability, toughness, and strength.
US09755133B1 Reconfigurable, tunable quantum qubit circuits with internal, nonvolatile memory
A tunable quantum qubit circuit comprising: a plurality of interconnected Josephson tunneling junctions sculpted in-situ on-chip, wherein each Josephson tunneling junction comprises a pair of high temperature superconductors separated by an active region having a controlled charge density; a capacitive-coupled control gate operatively coupled to the Josephson tunneling junctions and configured to simultaneously modulate energy levels of the Josephson tunneling junctions; and independent control gates operatively coupled to the Josephson tunneling junctions, wherein the independent control gates are reconfigurable on-the-fly by an operator.
US09755130B2 On-chip thermoelectric generator
An on-chip thermoelectric generator comprises an integrated circuit comprising a substrate and at least one thermocouple integrated with the substrate, wherein the thermocouple is configured to convert a temperature difference into a voltage. A metal bump or metal pillar is thermally connected to a portion of the thermocouple for generating the temperature difference. The metal bump or metal pillar is electrically insulated from said at least one thermocouple. The metal bump or metal pillar is electrically connected to a component of the integrated circuit which is different from the thermocouple.
US09755126B2 Light source unit
A light source unit includes a plurality of LED elements disposed on a plurality of band-shaped wirings on a substrate. The LED elements on one band-shaped wiring are electrically connected by wires to an adjacent band-shaped wiring. The LED elements are disposed on the substrate in a staggered arrangement as a whole. The LED elements can be densely disposed without poor connection occurring in the wires connected to the band-shaped wirings, and effective cooling can be carried out without impeding the dissipation of heat from the LED elements. One or more damming channels are formed between each two adjacent LED elements on each band-shaped wiring. A non-effusion region is formed, into which no solder flows, between each two adjacent LED elements. The wires are connected to the non-effusion regions.
US09755124B2 LED module with high index lens
An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.
US09755123B2 Light emitting device and method of manufacturing the light emitting device
A light emitting device includes a base member including a conductive member; a light mining element arranged on the base member, the light emitting element having a first surface, a second surface opposing the first surface, and at least one lateral surface between the first surface and the second surface; a die-bonding resin bonding the base member and the second surface; a first protective film continuously covering the base member, the die-bonding resin, the at least one lateral surface, and the first surface; and a second protective film continuously covering the base member, the die-bonding resin, the at least one lateral surface and the first surface of the light emitting element, over the first protective film, the second protective film having a linear expansion coefficient that is smaller than a linear expansion coefficient of the die-bonding resin and larger than a linear expansion coefficient of the first protective film.
US09755118B2 Light-emitting device, method for designing light-emitting device, method for driving light-emitting device, illumination method, and method for manufacturing light-emitting device
An object of the present invention is to provide a light-emitting device that can implement a natural, vivid, highly visible and comfortable appearance of colors and appearance of objects as if the objects are seen outdoors, and to provide a light-emitting device that can change the appearance of colors of the illuminated objects so as to satisfy the requirements for various illuminations, and a method for designing thereof. Another object of the present invention is to improve the appearance of colors of a light-emitting device which currently exists or is in use, and which includes a semiconductor light-emitting device of which appearance of colors is not very good. Moreover, another object of the present invention is to provide a method for driving the light-emitting device, an illumination method by the device, and a method for manufacturing the light-emitting device.These objects are achieved by the light-emitting device that incorporates light-emitting elements and satisfies predetermined requirements, in which φSSL (λ) emitted from the light-emitting device satisfies a predetermined condition.
US09755116B2 Method of manufacturing light emitting device
A method of manufacturing a light emitting device includes providing a package; disposing a light emitting element in a recess of the package; injecting a sealing material in the recess, the sealing material including fluorescent material particles and a binder, the fluorescent material particles including particles of fluoride fluorescent material that include a surface region and an inner region, both the surface region and the inner region having a composition including: tetravalent manganese ions, at least one element or compound selected from the group consisting of alkali metal elements and NH4+, and at least one element selected from the group consisting of Group 4 and Group 14 elements; sedimenting centrifugally the fluorescent material particles toward a bottom surface in the recess to form a sealing member that comprises a first sealing member portion and a second sealing member portion; and curing the binder to form a cured sealing member.
US09755114B2 Method for producing a plurality of optoelectronic components and optoelectronic component
The invention relates to a method for producing a plurality of optoelectronic components, comprising the following steps: —providing an auxiliary support wafer (1) having contact structures (4), wherein the auxiliary support wafer comprises glass, sapphire, or a semiconductor material, —applying a plurality of radiation-emitting semiconductor bodies (5) to the contact structures (4), —encapsulating an least the contact structures (4) with a potting mass (10), and —removing the auxiliary support wafer (1). The invention further relates to an optoelectronic component.
US09755109B2 Light-emitting device
A light-emitting device includes: a light-emitting stack including a first side, a second side opposite to the first side, a third side connecting the first side and the second side, and an upper surface between the first side and the second side; a first electrode pad formed on the upper surface; a second electrode pad formed on the upper surface, wherein the first electrode pad is closer to the first side than the second electrode pad; and a first extension electrode including a first section extended from the first electrode pad in a direction away from the third side, and a second section connecting to the first section and perpendicular to the first side; wherein a distance between the first electrode pad and the third side is smaller than a distance between the second electrode pad and the third side.
US09755106B2 Light emitting diode with improved light extraction efficiency
Disclosed is a light emitting diode (LED) having improved light extraction efficiency. The LED includes a light emitting structure positioned on a substrate and having a first semiconductor layer, an active layer and a second semiconductor layer. A first electrode pad is electrically connected to the first semiconductor layer. A second electrode pad is positioned on the substrate. An insulating reflective layer covers a portion of the light emitting structure, and is positioned under the second electrode pad, so that the second electrode pad is spaced apart from the light emitting structure. At least one upper extension is connected to the second electrode pad to be electrically connected to the second semiconductor layer. Further, a pattern of light extraction elements is positioned on the second semiconductor layer.
US09755103B2 Light-emitting element
A light-emitting element, a light-emitting element unit and a light-emitting element package are provided, which are each reduced in reflection loss and intra-film light absorption by suppressing multiple light reflection in a transparent electrode layer and hence have higher luminance. The light-emitting element 1 includes a substrate 2, an n-type nitride semiconductor layer 3, a light-emitting layer 4, a p-type nitride semiconductor layer 5, a transparent electrode layer 6 and a reflective electrode layer 7, and the transparent electrode layer 6 has a thickness T satisfying the following expression (1): 3 ⁢ λ 4 ⁢ n + 0.30 × ( λ 4 ⁢ n ) ≤ T ≤ 3 ⁢ λ 4 ⁢ n + 0.45 × ( λ 4 ⁢ n ) ( 1 ) wherein λ is the light-emitting wavelength of the light-emitting element 4, and n is the refractive index of the transparent electrode layer 6.
US09755099B2 Integrated micro-inverter and thin film solar module and manufacturing process
Embodiments of the present invention include a method for manufacturing, and a structure for a thin film solar module. The method of manufacturing includes fabricating a thin film solar cell and fabricating an electronic conversion unit (ECU) on a single substrate. The thin film solar cell has at least one solar cell diode on a substrate. The ECU has at least one transistor on the substrate. The ECU may further comprise a capacitor and an inductor. The ECU is integrated on the substrate monolithically and electrically connected with the thin film solar cell. The ECU and the thin film solar cell interconnect to form a circuit on the substrate. The ECU is electrically connected to a microcontroller on the solar cell module.
US09755097B2 Semiconductor photoreceiving device
According to one embodiment, a semiconductor photoreceiving device includes a substrate, a first structural layer provided on the substrate, in which light enters from the substrate side and in which a refractive index changes periodically, a semiconductor layer provided on the first structural layer and including an optical absorption layer, a reflective layer provided on the semiconductor layer, and a pair of electrodes configured to apply voltage to the optical absorption layer.
US09755095B2 Method and structure for multicell devices without physical isolation
The present technology relates to multi-cell devices fabricated on a common substrate that are more desirable than single cell devices, particularly in photovoltaic applications. Multi-cell devices operate with lower currents, higher output voltages, and lower internal power losses. Prior art multi-cell devices use physical isolation to achieve electrical isolation between cells. In order to fabricate a multicell device on a common substrate, the individual cells must be electrically isolated from one another. In the prior art, isolation generally required creating a physical dielectric barrier between the cells, which adds complexity and cost to the fabrication process. The disclosed technology achieves electrical isolation without physical isolation by proper orientation of interdigitated junctions such that the diffusion fields present in the interdigitated region essentially prevent the formation of a significant parasitic current which would be in opposition to the output of the device.
US09755092B2 Optical device including two-dimensional material and method of manufacturing the same
An optical device including a two-dimensional material and a method of manufacturing the same are provided. The optical device may include a barrier stack formed on a bottom channel layer, a top channel layer formed on the barrier stack, a drain electrode connected to the bottom channel layer, a source electrode formed on a substrate. The barrier stack may include two or more barrier layers, and one or more channel units at least partially interposing between the barrier layers. Channel units connected to the drain electrode and channel units connected to the source electrode may be formed, in an alternating sequence, between barrier layers included in the barrier stack. The barrier layers may each have a thickness which is less than a distance which may be traveled by electrons and holes generated by photo absorption prior to recombination. As a result, the optical device may provide improved photo separation efficiency.
US09755089B2 Solar cell and method for manufacturing the same
A solar cell is discussed. The solar cell includes a semiconductor substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type, which is positioned at a front surface of the semiconductor substrate, a front passivation part positioned on a front surface of the emitter region, a front electrode part which passes through the front passivation part and is electrically connected to the emitter region, a back passivation part positioned on a back surface of the semiconductor substrate, and a back electrode part which passes through the back passivation part and is electrically connected to the semiconductor substrate. The front passivation part and the back passivation part each include a silicon oxide layer. One of the front passivation part and the back passivation part includes an aluminum oxide layer.
US09755087B2 Silicon photonics integration method and structure
Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.
US09755086B2 Semiconductor device and a manufacturing method thereof
In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.
US09755085B2 Semiconductor device and method of manufacturing the same
A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.
US09755083B2 Semiconductor device and method for manufacturing the same
Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2.
US09755074B2 Semiconductor device including a multi-channel active pattern
A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.
US09755073B1 Fabrication of vertical field effect transistor structure with strained channels
A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.
US09755071B1 Merged gate for vertical transistors
Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.
US09755066B2 Reduced gate charge field-effect transistor
In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.
US09755065B2 Semiconductor device having super junction metal oxide semiconductor structure and fabrication method for the same
A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.
US09755064B2 Semiconductor device and method for manufacturing the same
A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×1020 cm−3 or more and a maximum concentration of hydrogen (H) in the region being 1×1019 cm−3 or less.
US09755063B1 RF SOI switches including low dielectric constant features between metal line structures
An RF SOI switch includes patterned or self-aligned low-k features (i.e., low-k polymer structures or voids) in the PMD and/or subsequently formed inter-metal dielectric layers to reduce capacitive coupling. All portions of the dielectric layers through which metal contact/via structures pass are pre-designated as reserved regions, and formation of the low-k features is restricted to interstitial regions located between adjacent reserved regions. After the low-k features are formed, dielectric material is deposited into all reserved regions, and then the metal contact/via structures are formed according to standard practices through the dielectric material disposed in the reserved regions. The low-k features are formed by polymer material sandwiched between two passivation layers. Optional openings are formed through the upper passivation layer, and then the polymer material is asked out to generate void-type features. Optionally, polymer is spin-coated over the metal line structures, then etched back to form self-aligned low-k features.
US09755062B2 III-N material structure for gate-recessed transistors
III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
US09755060B2 Fabrication methodology for optoelectronic integrated circuits
A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) bottom n-type ohmic contact layer, ii) p-type modulation doped quantum well structure (MDQWS) with a p-type charge sheet formed above the bottom n-type ohmic contact layer, iii) n-type MDQWS offset vertically above the p-type MDQWS, and iv) etch stop layer formed above the p-type MDQWS. P-type ions are implanted to define source/drain ion-implanted contact regions of a p-channel HFET which encompass the p-type MDQWS. An etch operation removes layers above the etch stop layer of iv) for the source/drain ion-implanted contact regions using an etchant that automatically stops at the etch stop layer of iv). Another etch operation removes remaining portions of the etch stop layer of iv) to form mesas that define an interface to the source/drain ion-implanted contact regions of the p-channel HFET. Source/Drain electrodes are on such mesas.
US09755057B1 Method of fabricating a semiconductor device
A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.
US09755053B2 Semiconductor device having fin-shaped semiconductor layer
An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.
US09755051B2 Embedded shape sige for strained channel transistors
An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
US09755046B2 Method of forming semiconductor device
A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.
US09755044B2 Method of manufacturing a transistor with oxidized cap layer
A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.
US09755042B2 Insulated gate semiconductor device and method for manufacturing the insulated gate semiconductor device
An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.
US09755041B2 NEMS devices with series ferroelectric negative capacitor
An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.
US09755037B2 Semiconductor device and method of manufacturing semiconductor device
According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.
US09755036B2 Semiconductor device, display device, and method for producing semiconductor device
This semiconductor device includes a substrate and a thin film transistor supported on the substrate. The thin film transistor includes a gate electrode, a semiconductor layer, a gate-insulating layer provided between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode respectively making contact with the semiconductor layer. The source electrode and the drain electrode respectively include a main layer containing aluminum or copper, a lower layer having a first layer containing refractory metal and positioned at a substrate side of the main layer, and an upper layer having a second layer containing refractory metal. The upper layer is provided so as to cover an upper surface of the main layer and at least the section of the side face of the main layer that overlaps the semiconductor layer.
US09755034B2 Semiconductor device having nanowire
A semiconductor device is provided as follows. A first nanowire is disposed on a substrate. The first nanowire is extended in a first direction and spaced apart from the substrate. A gate electrode surrounds a periphery of the first nanowire. The gate electrode is extended in a second direction intersecting the first direction. A gate spacer is formed on a sidewall of the gate electrode. The gate spacer includes an inner sidewall and an outer sidewall facing each other. The inner sidewall of the gate spacer faces the sidewall of the gate electrode. An end portion of the first nanowire is protruded from the outer sidewall of the gate spacer. A source/drain epitaxial layer is disposed on at least one side of the gate electrode. The source/drain is connected to the protruded end portion of the first nanowire.
US09755030B2 Method for reduced source and drain contact to gate stack capacitance
A structure and method for fabricating a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.
US09755028B2 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate.
US09755022B2 Epitaxial silicon wafer having reduced stacking faults
An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 mΩ·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.
US09755020B2 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first n− type layer and a second n− type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench that are disposed at the second n− type layer and are spaced apart from each other; a p type region surrounding a lateral surface and a lower surface of the first trench; an n+ type region disposed on the p type region and the second n− type layer; a gate insulating layer disposed in the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ type region disposed in the first trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate.
US09755019B1 Semiconductor device and manufacturing method thereof
A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is disposed over a substrate. The first and second fin structures are disposed over the substrate, and extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation layer. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation layer, and wraps side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation layer.
US09755018B2 Bipolar junction transistor structure for reduced current crowding
The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.
US09755015B1 Air gaps formed by porous silicon removal
Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.
US09755014B2 Semiconductor device with substantially equal impurity concentration JTE regions in a vicinity of a junction depth
A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm−3 or higher and 6×1017 cm−3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm−3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm−3 or higher and 8×1017 cm−3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm−3 or lower in a case of a junction barrier Schottky diode.
US09755003B2 Substrate and display device
A substrate and a display device are provided. The substrate includes a plurality of pixel groups arranged in rows and columns, the pixel groups each include a 3×3 array of sub-pixels which are at least two red sub-pixels (R), at least two green sub-pixels (G), at least two blue sub-pixels (B) and one white sub-pixel (W) with the white sub-pixel (W) in the center of the 3×3 sub-pixel array. Sub-pixels of the pixel group constitute two pixel units, which share the white sub-pixel (W). Each pixel unit includes at least one red sub-pixel (R), at least one green sub-pixel (G), at least one blue sub-pixel (B) and one white sub-pixel (W). With this substrate, data volume and the number of outputting lines of a data chip can be reduced so as to simplify the structure of an array substrate or a color filter substrate.
US09755002B2 Organic light-emitting display panel and method of manufacturing the same
An organic light-emitting display panel includes a first display region including a plurality of first sub-pixels and a second display region including a plurality of second sub-pixels. Each of the sub-pixels includes a pixel circuit having a driving transistor to output driving current to an output node based on a data signal, a storage capacitor to store a voltage difference between the driving voltage and the gate voltage of the driving transistor, a switching transistor to transfer the data signal to the driving transistor, and a light-emitter connected to emit light based on the driving current. An overlap area of the gate electrode of the driving transistor and an anode electrode of the light-emitter in the first sub-pixel is smaller than an overlap area of the gate electrode of the driving transistor and an anode electrode of the light-emitter in the second sub-pixel.
US09755001B2 Light-emitting device comprising films having different optical path lengths
A light-emitting device includes a first light-emitting element emitting blue light, a second light-emitting element emitting green light, and a third light-emitting element emitting red light. A first reflective electrode and a first transparent conductive film, a second reflective electrode and a second transparent conductive film, and a third reflective electrode and a third transparent conductive film are stacked in the first to third light-emitting elements, respectively. A first light-emitting layer, a charge-generation layer, a second light-emitting layer, and an electrode are stacked in this order over each of the first transparent conductive film, the second transparent conductive film, and the third transparent conductive film. The electrode has functions of transmitting and reflecting light. The first to third reflective electrodes contain silver. The first transparent conductive film is thicker than the third transparent conductive film. The third transparent conductive film is thicker than the second transparent conductive film.
US09755000B2 Memory device
A memory device includes a substrate, a first conductive layer above the substrate and extending in a first direction parallel to a surface of the substrate, a second conductive layer above the first conductive layer and extending in the first direction, wherein centers of the first and second conductive layers are aligned in a second direction that is substantially perpendicular to the surface of the substrate, and a contact extending in the second direction from a position lower than the first conductive layer to a position higher than the second conductive layer, the contact being electrically connected to and in direct contact with the first conductive layer and electrically insulated and physically separated from the second conductive layer.
US09754999B1 Vertical thin film transistors with surround gates
A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.
US09754996B2 Write current reduction in spin transfer torque memory devices
The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
US09754992B2 Integrated scintillator grid with photodiodes
Various embodiments of a structure implemented in an X-ray imaging system are described. In one aspect, a structure implemented in an X-ray imaging system includes a silicon wafer including a first side and a second side opposite the first side. The silicon wafer also includes an array of photodiodes on the first side of the silicon wafer with the photodiodes electrically isolated from each other as well as an array of grid holes on the second side of the silicon wafer. Each grid hole of the array of grid holes is aligned with a respective photodiode of the array of photodiodes. The structure also includes a layer of scintillating material disposed over the array of grid holes on the second side of the silicon wafer. The structure further includes a layer of reflective material disposed on the layer of scintillating material.
US09754990B2 Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus
A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
US09754988B2 Large format arrays and methods
A large format array is described having a series of smaller arrays daisy chained together to form the larger array. The smaller arrays are mounted on a base plate that may be of a non planar configuration. The daisy chaining together of the smaller arrays enables a smaller number of connections to be made to the external interface via connections.
US09754986B2 Solid-state imaging device
A solid-state imaging device includes unit pixels arrayed two dimensionally in a pixel area, wherein: a unit pixel disposed in a central region of the pixel area includes a first collecting element having a convex surface and a unit pixel in a region of the pixel area not including the central region includes a second collecting element having a convex surface and grooves having widths less than or equal to a wavelength of incident light; the second collecting element includes a sparse region and a dense region in which a density of formations of the grooves is higher than in the sparse region; and the sparse region is positioned closer to the central region of the pixel area than the dense region.
US09754983B1 Chip scale package and related methods
Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
US09754981B2 Solid state photomultiplier having an intermediate region coupled between high and low voltage regions and associated detector
Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include an epitaxial layer, a high voltage region formed in the epitaxial layer, a low voltage region formed in the epitaxial layer, and an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.
US09754972B2 Metal oxide film and method for forming metal oxide film
A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nmφ and less than or equal to 10 nmφ.
US09754970B2 Thin film transistor, fabricating method thereof, array substrate and display device
The present invention provides a thin film transistor, a fabricating method thereof, an array substrate and a display device. The fabricating method of the thin film transistor of the present invention comprises: forming an inducing layer film and an oxide active layer film in contact therewith on a substrate, the oxide active layer film being provided above or below the inducing layer film; and heating the substrate subjected to the above step, crystallizing the oxide active layer film through inducement of the inducing layer film to form a crystalline oxide active layer.
US09754969B2 Dual-material mandrel for epitaxial crystal growth on silicon
In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.
US09754966B1 Semiconductor on insulator (SOI) block with a guard ring
A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.
US09754963B1 Multi-tier memory stack structure containing two types of support pillar structures
A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support pillar structures are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed over the first tier structure. Memory stack structures and second support pillar structures are formed through the second tier structure. The first and second sacrificial material layers are replaced with first and second electrically conductive layers while the first support pillar structures, the second support pillar structures, and the memory stack structures provide structural support to the first and second insulating layers. By limiting the spatial extent of the first support pillar structures within the first tier structure, electrical short to backside contact via structures can be reduced.
US09754957B2 Nonvolatile memory devices and methods forming the same
Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.
US09754956B2 Uniform thickness blocking dielectric portions in a three-dimensional memory structure
A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers. Optionally, an inner portion of each annular semiconductor material portion can be converted into an annular dielectric material portion that includes a dielectric material. A memory film is formed in the memory opening. During removal of the second material layers, the annular semiconductor material portions can be employed as an etch stop material, thereby minimizing collateral etching of the memory film or annular dielectric material portions.
US09754951B2 Semiconductor device with a memory device and a high-K metal gate transistor
A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.
US09754949B2 Semiconductor device and method of manufacturing the same
An insulating film made of the same material as that of a gate insulating film is formed so as to cover one sidewall of a control gate on a conducting film for floating gate. By selectively removing the conducting film for floating gate with the insulating film as a mask, a floating gate is formed from the conducting film for floating gate, and a portion of the gate insulating film is exposed at the floating gate. A nitrogen introduced portion is formed by introducing nitrogen into the exposed portion of the gate insulating film. Then, the insulating film is removed to expose an upper surface of a lateral protrusion of the floating gate. An erase gate is formed so as to face the upper surface and a side surface of the lateral protrusion.
US09754948B2 Non-volatile programmable memory cell and array for programmable logic array
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
US09754947B2 Static random access memory and fabrication methods thereof
A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate. The method also includes forming a plurality of transistors on the semiconductor substrate. Further, the method includes forming a first metal layer having a word line electrically connecting with a partial number of the transistors. Further, the method also includes forming a second metal layer having a first bit line, a second bit line, a first power source line and second power source lines electrically connect with a partial number of the transistors.
US09754945B2 Non-volatile memory device employing a deep trench capacitor
A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.
US09754943B1 Dynamic random access memory device
A dynamic random access memory (DRAM) device includes a substrate, plural word lines and plural bit lines. The word lines are disposed in the substrate along a first trench extending along a first direction. Each of the word lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes TiSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof. The bit lines are disposed over the word lines and extended along a second direction across the first direction.
US09754942B2 Single spacer for complementary metal oxide semiconductor process flow
A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.
US09754940B2 Self-aligned contact metallization for reduced contact resistance
Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.
US09754939B2 Integrated circuits having multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits
Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes providing a semiconductor fin structure overlying a semiconductor substrate. The semiconductor fin structure has a first sidewall, a second sidewall opposite the first sidewall, and an upper surface. The method includes forming a first gate along the first sidewall of the semiconductor fin structure with a first threshold voltage. Further, the method includes forming a second gate along the second sidewall of the semiconductor fin structure with a second threshold voltage different from the first threshold voltage.
US09754933B2 Large area diode co-integrated with vertical field-effect-transistors
An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.
US09754932B2 Semiconductor device
A semiconductor device includes a substrate, an active layer, a transistor, and a capacitor. The active layer is disposed on the substrate, and the active layer is divided into a first portion and a second portion. The transistor and the capacitor are disposed on the substrate. The transistor includes the second portion, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively and electrically connected to the second portion. The gate electrode is disposed on the second portion. The capacitor includes the first portion, a first electrode, a first insulating layer, and a second electrode. The first electrode is electrically connected to the first portion and the source electrode. The first insulating layer is disposed on the first portion. The second electrode is disposed on the first insulating layer and is electrically connected to the gate electrode.
US09754931B2 Circuit and an integrated circuit including a transistor and another component coupled thereto
A circuit can include a transistor coupled to a resistor or a diode. In an embodiment, the circuit can include a pair of transistors arranged in a cascode configuration, and each of the transistors can have a corresponding component connected in parallel. In a particular embodiment, the components can be resistors, and in another particular, embodiment, the components can be diodes. The circuit can have less on-state resistance as compared to a circuit in which only one of the components is used, and reduces the off-state voltage on the gate of a high-side transistor. An integrated circuit can include a high electron mobility transistor structure and a resistor, a diode, a pair of resistors, or a pair of diodes.
US09754929B2 Positive strike SCR, negative strike SCR, and a bidirectional ESD structure that utilizes the positive strike SCR and the negative strike SCR
A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.
US09754928B2 SMD, IPD, and/or wire mount in a package
Various package structures and methods of forming package structures are described. According an embodiment, a structure includes a first package and a package component attached to the first package by external connectors. The first package comprises a device attached to a first pad and a second pad. The device is a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof. The device is attached to the first pad and the second pad through a dielectric layer. A spacer material is disposed laterally between the first pad and the second pad and is disposed between the device and the dielectric layer. An encapsulant surrounds the device and the spacer material.
US09754927B2 Method for fabricating multi-chip stack structure
A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.
US09754925B2 3DIC interconnect apparatus and method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
US09754923B1 Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.
US09754922B2 3D integration using Al—Ge eutectic bond interconnect
Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.
US09754914B1 Method to provide die attach stress relief using gold stud bumps
An integrated circuit is attached to a substrate with a controlled stand-off height, by mounting a plurality of stud bumps of the controlled stand-off height to the substrate at predetermined locations, placing adhesive dots over the stud bumps, placing the integrated circuit on the substrate over the adhesive dots, and applying downward pressure on the integrated circuit until the integrated circuit is in mechanical contact with the stud bumps.
US09754913B2 Integrated circuit package
Integrated circuit package including an integrated circuit, external connection elements (3) connected to the integrated circuit, a package material (2) enclosing the integrated circuit, and a mechanical element (5, 6, 7) allowing a mechanical connection of a further element to the integrated circuit package (1). The mechanical element (5, 6, 7) is e.g. an attachment element (5); a mechanical element (5), optionally with a thread; a bushing element; a bearing element (7); an electrical connector (6).
US09754911B2 IC structure with angled interconnect elements
Aspects of the present disclosure include integrated circuit (IC) structures with angled interconnect elements. An IC structure according to the present disclosure can include: an IC chip interconnect surface including a radially inner region positioned within a radially outer region; and a plurality of conductive pillars extending outward from the radially inner region of the IC chip interconnect surface, relative to a radial centerline axis of the radially inner region of the IC chip interconnect surface, wherein the radially inner region of the IC chip interconnect surface is free of conductive pillars thereon.
US09754908B2 Wafer with liquid molding compound and post-passivation interconnect
A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.
US09754905B1 Final passivation for wafer level warpage and ULK stress reduction
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
US09754903B2 Semiconductor structure with anti-efuse device
A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.
US09754901B1 Bulk thinning detector
In one embodiment, a semiconductor device comprises: a bulk comprising a bulk material characterized by a potential designated as a ground, and a bulk thinning detector being a section of the bulk that includes one or more conducting materials. The bulk thinning detector is adapted to be connected to the ground when a part of the bulk material is underneath and contiguous with a portion of the one or more conducting materials in the section. The semiconductor device further comprises: one more electronic components in at least one active layer of the semiconductor device, the one or more electronic components and the bulk thinning detector being included in a circuit for detecting whether there is backside thinning of the semiconductor device by detecting whether at least one of: the bulk thinning detector is disconnected from the ground, or there is a change in resistance of the bulk thinning detector.
US09754899B2 Semiconductor structure and method of fabricating the same
A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.
US09754897B2 Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits
A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.
US09754891B2 Low-temperature diffusion doping of copper interconnects independent of seed layer composition
Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
US09754887B2 Semiconductor devices
A semiconductor device includes a first power rail, a second power rail, at least one standard cell and at least one power bridge. The first power rail extends in a first direction over a substrate. The second power rail extends in the first direction over the substrate, and the second power rail is spaced apart from the first power rail in a second direction that intersects the first direction. The at least one standard cell receives a first voltage from the first and the second power rails. The at least one power bridge connects the first power rail and the second power rail in the second direction. The first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer.
US09754884B2 Method of manufacturing semiconductor device and semiconductor device
Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time, conditions are set such that partial pressure of the titanium tetrachloride is higher than 3 Pa. The conditions are set such that the product of the partial pressure of the titanium tetrachloride and supply time is greater than 800 Pa·second. The titanium tetrachloride continues to be supplied into the second chamber to form a titanium film under prescribed temperature conditions in a plasma atmosphere. The temperature conditions are set such that temperature is higher than temperature at which titanium silicide is formed and lower than temperature at which a metal silicide film agglomerates. A titanium nitride film is formed in a third chamber.
US09754883B1 Hybrid metal interconnects with a bamboo grain microstructure
A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top portion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.
US09754881B2 Designed-based interconnect structure in semiconductor structure
Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 ⁢ ⁢ P gate ⁢ ⁢ min + 0.35 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min - 20 0.2 ⁢ ⁢ L gate ⁢ ⁢ min + 0.8 ⁢ ⁢ H gate ⁢ ⁢ min - 5 × 0.3 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.
US09754878B2 Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch.
US09754877B2 Semiconductor device
A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.
US09754876B2 Semiconductor device and semiconductor device manufacturing method
A semiconductor device including: a fuse element; and a fuse window that is formed above a region including the fuse element, that includes a pair of first sidewalls extending in a first direction running along a direction that current flows in the fuse element and a pair of second sidewalls extending in a second direction intersecting the first direction, and that is formed with a projection projecting out from a sidewall side toward the inside at an inner wall of at least one out of the first sidewalls or the second sidewalls, the projection having a sidewall side width that is narrower than a projecting side width.
US09754874B2 Inductive capacitive structure and method of making the same
An inductive capacitive structure including a first substrate, a first conductive line over the first substrate, a first shielding layer over the first substrate and a second substrate over the first substrate.
US09754871B2 Switch circuit package module
A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors. The semiconductor switch unit includes a plurality of common electrodes, each common electrode connects the source electrode of one sub micro-switch element in the first semiconductor switch element with the drain of one sub micro-switch element in the second semiconductor switch element and is disposed adjacent to at least one drain electrode from the first semiconductor switch element or one source electrode from the second semiconductor switch element.
US09754867B2 Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
US09754864B1 Semiconductor power device having single in-line lead module and method of making the same
A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip. This invention further discloses a method for fabricating semiconductor power devices. The method comprises the steps of providing a lead frame strip having a plurality of lead frame units; providing two or more pluralities of single in-line leads; attaching two or more high-side semiconductor chips to each lead frame unit; connecting each of the two or more high-side semiconductor chips to a respective lead by a respective clip of two or more first clips; attaching a respective low-side semiconductor chip of the two or more low-side semiconductor chips to each clip of the two or more first clips; molding an encapsulation; and singulating the lead frame strip and the encapsulation to form the semiconductor power devices.
US09754860B2 Redistribution layer contacting first wafer through second wafer
A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer.
US09754858B2 Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.
US09754856B2 Apparatus comprising a functional component likely to be thermally overloaded during the operation thereof and a system for cooling the component
The invention relates to an apparatus comprising a functional component likely to be thermally overloaded during the operation thereof, and a system for cooling the component, comprising: a thermoelectric module comprising a cold surface and a hot surface, the cold surface being thermally coupled with the component; a heat sink thermally coupled with the hot surface of the module, the heat sink including an exchange surface with the surrounding environment and at least one cell containing a phase-change material (PCM), the PCM material contained in the cell or cells being suitable for melting when the heat released from the cold surface of the module is that of the thermally overloaded component, the exchange surface being suitable for bringing the PCM material from the molten phase to the solid phase thereof when the heat released from the cold surface of the module is that of the operational component which is not thermally overloaded.
US09754849B2 Organic-inorganic hybrid structure for integrated circuit packages
An organic-inorganic hybrid structure is described for integrated circuit packages. In one example, an integrated circuit package includes a ceramic frame having a top side and a bottom side, the top side having a pocket with a bottom floor and a plurality of conductive through holes in the bottom floor, an integrated circuit die attached to the bottom floor over the conductive through holes, and a redistribution layer on the bottom side connected to the conductive through holes.
US09754848B2 Gas sensor package
Provided is a gas sensor package, including: a gas sensing element; and a substrate on which the gas sensing element is disposed, in which a through hole corresponding to the gas sensing element is formed.
US09754844B2 Double sided NMOS/PMOS structure and methods of forming the same
A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
US09754833B2 Method for manufacturing semiconductor chip that includes dividing substrate by etching groove along cutting region of substrate combined with forming modified region by laser irradiating along cutting region in substrate
A method for manufacturing a semiconductor chip includes forming at least a portion of a front-side groove by anisotropic dry etching from a front surface of a substrate along a cutting region; forming a modified region in the substrate along the cutting region by irradiating the inside of the substrate with a laser along the cutting region; and dividing the substrate along the cutting region by applying stress to the substrate.
US09754827B1 Semiconductor device and fabrication method thereof
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
US09754826B2 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.
US09754824B2 Tungsten films having low fluorine content
Aspects of the methods and apparatus described herein relate to deposition of tungsten nucleation layers and other tungsten-containing films. Various embodiments of the methods involve exposing a substrate to alternating pulses of a tungsten precursor and a reducing agent at low chamber pressure to thereby deposit a tungsten-containing layer on the surface of the substrate. According to various embodiments, chamber pressure may be maintained at or below 10 Torr. In some embodiments, chamber pressure may be maintained at or below 7 Torr, or even lower, such as at or below 5 Torr. The methods may be implemented with a fluorine-containing tungsten precursor, but result in very low or undetectable amounts of fluorine in the deposited layer.
US09754821B2 Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
US09754820B2 Three-dimensional memory device containing an aluminum oxide etch stop layer for backside contact structure and method of making thereof
Collateral etching of a dielectric material around a trench during formation of a substrate contact via structure can be avoided employing an aluminum oxide layer. The aluminum oxide layer functions as an etch stop layer during an anisotropic etch that removes horizontal portions of an insulating material layer to form an insulating spacer. The aluminum oxide layer may be a conformal or a non-conformal material layer, and may, or may not, include a horizontal portion that overlies an alternating stack of insulating layers and electrically conductive layers. Electrical shorts caused by widening of the top portion of the trench can be avoided through use of the aluminum oxide layer. Memory stack structures can extend through the alternating stack to provide a three-dimensional memory stack structure. A source region can be formed underneath the trench, and the substrate contact via structure can be employed as a source contact via structure.
US09754819B2 Interlevel airgap dielectric
A method of forming a semiconductor device includes: forming a lower trace in a lower dielectric layer; reducing a height of the lower trace a distance equal to gap height (g) to form an initial void region; filling the initial void region with an amorphous carbon layer; forming an upper dielectric layer above the amorphous carbon layer; covering the amorphous carbon layer with at least an oxide layer and a nitride layer; forming a hole in the oxide and nitride layers to expose a portion of the amorphous carbon layer; exposing the amorphous carbon layer to oxygen plasma to remove the amorphous carbon layer; sputtering a metal layer over the oxide layer and into a void created removal of the amorphous carbon layer to divide the void such that it includes an airgap; and forming an upper trace over the airgap.
US09754815B2 Composite substrate and method for producing same
A composite substrate 1 according to the present invention comprises: a supporting substrate 10 that is formed of an insulating material; a semiconductor part 20 that is disposed over the supporting substrate 10; and interfacial inclusions 30 that are present at the interface between the supporting substrate 10 and the semiconductor part 20 and contains Ni and Fe so that the ratio of Ni to Fe is 0.4 or more. Consequently, the present invention is able to provide a highly reliable composite substrate wherein the interfacial inclusions 30 are prevented from diffusing into the semiconductor part 20.
US09754813B2 Bond chuck, methods of bonding, and tool including bond chuck
A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.
US09754812B2 Adaptable end effector
An adaptable end effector may include a substrate interface may be configured to support a substrate. The substrate interface may include multiple groups of vacuum openings that are associated with a plurality of types of substrates. A vacuum system may be configured to supply vacuum only to one or more selected groups of vacuum openings that are associated with a given type of substrates when the adaptable end effector supports a substrate of the given type of substrates.
US09754811B2 Dicing sheet with protective film forming layer and method for producing chip
[Problem] To provide a dicing sheet that is with a protective film formation layer, can easily produce a semiconductor chip having a protective film having high uniformity and superior printing precision, is such that the peeling of the protective film and the dicing sheet can be easily performed, and has superior affixing ability of chips during dicing. [Solution] The dicing sheet with a protective film formation layer is characterized by a protective film formation layer being peelably provided on the adhesive layer of an adhesive sheet resulting from the adhesive layer, which contains an adhesive component and a free epoxy group-containing compound, being laminated onto a substrate film.
US09754809B2 Tri-modal carrier for a semiconductive wafer
A tri-modal carrier provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The tri-modal carrier includes a doped semiconductive substrate, a plurality of electrostatic field generating (EFG) circuits, and a capacitance charging interface. A positive pole and a negative pole from each EFG circuit are embedded into the doped semiconductive substrate. An exposed portion of the doped semiconductive substrate is located between the positive pole and the negative pole, which is used as a biased pole for each EFG circuit. The combination of these poles for each EFG circuit is used to generate a non-uniform electrostatic field for bonding the semiconductive wafer. The tri-modal carrier also uses flat surface properties and the removal of trapped gas particles to strengthen the bond between the tri-modal carrier and the semiconductive wafer.
US09754797B2 Etching method for selectively etching silicon oxide with respect to silicon nitride
An etching method is provided for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride. The target object includes the second region, the first region and a mask. The etching method includes a first sequence and a second sequence. Each of sequence includes, a first step of generating a plasma of a processing gas containing a fluorocarbon gas in a processing chamber where the target object is accommodated and forming a deposit containing fluorocarbon on the target object, and a second step of etching the first region by radicals of fluorocarbon contained in the deposit. The first sequence is performed during a period including time when the second region is exposed, and an etching amount of the first region in the first sequence is smaller than an etching amount of the first region in the second sequence.
US09754794B2 Plasmonic nano-lithography based on attenuated total reflection
Techniques related to semiconductor fabrication are generally described herein. An example fabrication method may include coupling, by a lithographic equipment, a surface of a planar waveguide structure with a first surface of a photolithographic mask. Some example methods may also include directing, by the lithographic equipment, a lithography light beam into the planar waveguide structure, causing a surface plasmon being emitted from the surface of the planar waveguide structure when the lithography light beam is reflected by internal surfaces of the planar waveguide structure, effectuating an attenuated total reflection. Some example methods may further include directing, by the lithographic equipment, an evanescent wave caused by the surface plasmon through the photolithographic mask, wherein the evanescent wave has a sub-diffraction characteristic and is used as a photolithographic light source.
US09754791B2 Selective deposition utilizing masks and directional plasma treatment
Methods for selectively depositing different materials at different locations on a substrate are provided. A selective deposition process may form different materials on different surfaces, e.g., different portions of the substrate, depending on the material properties of the underlying layer being deposited on. Ion implantation processes may be used to modify materials disposed on the substrate. The ions modify surface properties of the substrate to enable the subsequent selective deposition process. A substrate having a mask disposed thereon may be subjected to an on implantation process to modify the mask and surfaces of the substrate exposed by the mask. The mask may be removed which results in a substrate having regions of implanted and non-implanted materials. A subsequent deposition process may be performed to selectively deposit on either the implanted or non-implanted regions of the substrate.
US09754790B2 Memory device and method for fabricating the same
A memory device comprises a patterned multi-layers stacking structure, a semiconductor capping layer, a memory layer and a channel layer. The patterned multi-layers stacking structure is formed on a substrate and has at least one trench used to define a plurality of ridge-shaped stacks comprising at least one conductive strip in the patterned multi-layers stacking structure. The semiconductor capping layer covers on the ridge-shaped stacks. The memory layer covers on sidewalls of the trench. The channel layer covers on the memory layer, the semiconductor capping layer and a bottom of the trench, wherein the channel layer is directly in contact with the semiconductor capping layer.
US09754787B2 Method for treating a semiconductor wafer
A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum.
US09754786B2 Method and apparatus for enhanced lifetime and performance of ion source in an ion implantation system
An ion implantation system and process, in which the performance and lifetime of the ion source of the ion implantation system are enhanced, by utilizing isotopically enriched dopant materials, or by utilizing dopant materials with supplemental gas(es) effective to provide such enhancement.
US09754784B2 Method for manufacturing oxide semiconductor device
An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.
US09754781B2 Semiconductor manufacturing method
A semiconductor manufacturing method in accordance with an embodiment includes feeding a first gas, which contains a component of a first film, to a reaction chamber, and forming a first film over a semiconductor substrate, which is accommodated in the reaction chamber, through plasma CVD. The semiconductor manufacturing method includes feeding a second gas to the reaction chamber after forming the first film, allowing the first gas in the reaction chamber to react on the second gas, and forming a second film, which has a composition different from that of the first film, over the surface of the first film. The semiconductor manufacturing method includes selectively removing the second film.
US09754779B1 Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.
US09754778B2 Metallization of fluorocarbon-based dielectric for interconnects
Embodiments of the present disclosure are directed towards metallization of a fluorocarbon-based dielectric material for interconnect applications. In one embodiment, an apparatus includes a semiconductor substrate, a device layer disposed on the semiconductor substrate, the device layer including one or more transistor devices, and an interconnect layer disposed on the device layer, the interconnect layer comprising a fluorocarbon-based dielectric material, where x represents a stoichiometric quantity of fluorine relative to carbon in the dielectric material, and one or more interconnect structures configured to route electrical signals to or from the one or more transistor devices, the one or more interconnect structures comprising cobalt (Co), or ruthenium (Ru), or combinations thereof. Other embodiments may be described and/or claimed.
US09754766B2 Plasma processing apparatus
A resonance frequency is adjusted or optimized by shifting the resonance frequency without reducing an impedance function or a withstand voltage characteristic against a high frequency noise, when blocking, by using a multiple parallel resonance characteristic of a distributed constant line, the high frequency noise introduced into a line such as a power feed line or a signal line from an electrical member other than a high frequency electrode within a processing vessel. Regarding winding pitches, each of the solenoid coils 104(1) and 104(2) is divided to multiple sections K1, K2, . . . in a coil axis direction, and, a winding pitch pi in each section Ki (i=1, 2, . . . ) is set independently. Comb teeth M inserted into winding gaps of both solenoid coils 104(1) and 104(2) are formed on inner surfaces of multiple rod-shaped comb-teeth member 114 provided adjacent to the solenoid coils 104(1) and 104(2).
US09754756B2 Vacuum integrated electronic device and manufacturing process thereof
A vacuum integrated electronic device has an anode region of conductive material; an insulating region on top of the anode region; a cavity extending through the insulating region and having a sidewall; and a cathode region. The cathode region has a tip portion extending peripherally within the cavity, adjacent to the sidewall of the cavity. The cathode region is formed by tilted deposition, carried out at an angle of 30-60° with respect to a perpendicular to the surface of device.
US09754748B2 Power generation switch
A power generation switch comprising: a case; a core, a coil being wound around the core; a magnet magnetically connected with the core; a yoke in which the magnet is disposed; an elastic element that supports the yoke and elastically deforms so as to deviate a position of the magnet from the core; a switch element that is operated to be moved; and a yoke driving mechanism that moves the yoke so that upon an engagement of the switch element and the yoke being released, the yoke moves between a first position and a second position due to elastic force of the elastic element, wherein first magnetic flux is generated by the core and the magnet when the yoke is at the first position and second magnetic flux different from the first magnetic flux is generated by the core and the magnet when the yoke is at the second position.
US09754747B1 Relay device
A relay device comprises a base, a pin, and an outer cap. A gap is arranged at a peripheral of the base. The pin has a convex plate and assembled to the gap of the base and one end thereof is protruded from the gap. The convex plate is covered/shielded the gap. The outer cap includes a receiving groove. A notch of the receiving groove is covered the base and the pin. A paste is applied among the peripheral of the base, the convex plate of the pin, and the notch of the receiving groove for fastening. The gap arranged at the peripheral of the base is providing the pin for assembling without directional limitation and advantageous to once assembly of the base and the pin in an automatic machine so as to simplify the manufacturing process of the relay device.
US09754739B2 Switch structure and explosion-proof device
A switch that includes a hermetically sealed container including a container wall separating an inside of the hermetically sealed container from an outside of the hermetically sealed container, a magnetic sensor arranged in the hermetically sealed container and configured to be turned ON/OFF by a magnetic field of a magnet acting from the outside of the hermetically sealed container through the container wall of the hermetically sealed container, and a first magnetic body provided at the container wall of the hermetically sealed container and serving as a path of the magnetic field acting on the magnetic sensor from the magnet.
US09754738B2 Network transformer primary disconnect assembly
A housing assembly for a network transformer primary disconnect assembly is provided. The housing assembly includes a visible break assembly and a number of sidewalls defining an enclosed space. The visible break assembly includes a number of viewing windows in at least one sidewall. The viewing windows are aligned with one of a contact assembly interface or a movable contact assembly distal end in the open, first position.
US09754729B2 Solid-state electrolytic capacitor with improved metallic anode and method for manufacturing the same
The instant disclosure relates to a solid electrolytic capacitor with improved metallic anode and a method for manufacturing the same. The solid electrolytic capacitor includes a substrate layer, a conductive polymer layer and an electrode layer. The substrate layer has a cathode portion and an anode portion having a smaller thickness than the cathode portion. The conductive polymer layer is formed to cover the cathode portion of the substrate layer. The electrode layer is formed to cover the conductive polymer layer. Therefore, the instant solid electrolytic capacitor can be applied to a packing process, and welding success yield rate can be improved.
US09754727B2 Energy charge storage device using a printable polyelectrolyte as electrolyte material
An energy charge storage device, particularly from the group consisting of super capacitor, a hybrid electrochemical capacitor, a metal hydride battery and a fuel cell, comprising a first and second electrode and an electrolyte wherein the electrolyte comprises a printable polyelectrolyte e.g. polystyrene sulfonic acid (PSSH). The present invention also refers to methods of obtaining such energy storage device.
US09754726B2 Nonaqueous electrolytic capacitor element
To provide a nonaqueous electrolytic capacitor element, which contains: a positive electrode containing a positive electrode active material capable of intercalating or deintercalating anions; a negative electrode containing a negative electrode active material; and a nonaqueous electrolyte, which contains a nonaqueous solvent, an electrolyte salt containing a halogen atom, and a compound having a site capable of bonding to an anion containing a halogen atom.
US09754725B2 Method for manufacturing lithium-ion capacitor
A method for drying an electrode pair is disclosed. In at least one embodiment, the method includes preparing a positive electrode by applying a positive electrode material to a current collector; preparing a negative electrode by applying a negative electrode material to a current collector; preparing one set of an electrode pair made up of a positive electrode, a separator, and a negative electrode which are laminated in this order or preparing sets of electrode pairs, the sets being laminated, a separator being provided between the respective sets, each of the electrode pairs being made up of a positive electrode, a separator, and a negative electrode which are laminated in this order; accommodating the electrode pair(s) in a container; and drying the container in which the electrode pair(s) has been accommodated by use of the freeze-drying method.
US09754724B2 Stress control during processing of a MEMS digital variable capacitor (DVC)
The present invention generally relates to a MEMS digital variable capacitor (DVC) (900) and a method for manufacture thereof. The movable plate (938) within a MEMS DVC should have the same stress level to ensure proper operation of the MEMS DVC. To obtain the same stress level, the movable plate is decoupled from CMOS ground during fabrication. The movable plate is only electrically coupled to CMOS ground after the plate has been completely formed. The coupling occurs by using the same layer (948) that forms the pull-up electrode as the layer that electrically couples the movable plate to CMOS ground. As the same layer couples the movable plate to CMOS ground and also provides the pull-up electrode for the MEMS DVC, the deposition occurs in the same processing step. By electrically coupling the movable plate to CMOS ground after formation, the stress in each of the layers of the movable plate can be substantially identical.
US09754715B2 Magnetic assembly
A magnetic assembly includes a magnetic core and at least one foil winding assembly. The magnetic core includes plural magnetic legs. At least one magnetic path is defined by the plural magnetic legs collaboratively. Moreover, at least one low-permeability structure is formed in at least one specified magnetic leg of the plural magnetic legs. The at least one foil winding assembly is wound around the specified magnetic leg. Consequently, plural winding parts in a multi-layered arrangement are sequentially stacked on the specified magnetic leg. A direction of a conductor thickness of each winding part is perpendicular to a direction of a magnetic flux through the specified magnetic leg. The plural winding parts are gradually close to the low-permeability structure along an arranging direction, and the conductor thicknesses of at least two of the plural winding parts are gradually decreased along the arranging direction.
US09754713B2 Choke
A choke includes a single-piece core made of a same material, the single-piece core having a first board, a second board, and a pillar located between the first and second boards, a winding space located among the first board, the second board and the pillar, wherein the pillar has a non-circular and non-rectangular cross section having a first axis and a second axis substantially perpendicularly intersecting with each other at a center of the cross section of the pillar, and wherein a circumference of the cross section of the pillar includes two arc edges, four first substantially straight edges substantially parallel to the first axis, and two second substantially straight edges substantially parallel to the second axis, each of the first substantially straight edges being a joint of and in direct contact with one of the arc edges and one of the second substantially straight edges.
US09754712B2 Embedded magnetic components and methods
Disclosed are apparatus and methods for a magnetic component. In accordance with an embodiment, a magnetic component comprises a base substrate defining a winding cup having a shape of a closed groove surrounding a hub. The winding cup defines a core space operable to receive a core therein. A first conductive pattern is disposed on at least a portion of the base substrate including the winding cup. A second substrate defines a second conductive pattern. The second substrate is coupled to the first base surface with the first conductive pattern in operable alignment with the second conductive pattern. The first and second conductive patterns are coupled in electrical communication so as to define one or more winding-type electric circuits surrounding the core space so as to induce a magnetic flux within the core space when the one or more electric circuits are energized by a voltage source.
US09754709B2 Nanoheterostructured permanent magnet and method for producing the same
A nanoheterostructured permanent magnet includes a hard magnetic material and a soft magnetic material of which one inorganic component is a matrix, and of which the other inorganic component is three-dimensionally and periodically arranged in the matrix, in a shape selected from the group consisting of a spherical shape, a columnar shape, and a gyroid shape, the nanoheterostructured permanent magnet having a three-dimensional periodic structure whose average value of one unit length of a repeated structure is 1 nm to 100 nm.
US09754706B2 Metal nitride material for thermistor, method for producing same, and film type thermistor sensor
Provided are a metal nitride material for a thermistor, which has a high heat resistance and a high reliability and can be directly deposited on a film or the like without firing, a method for producing the same, and a film type thermistor sensor. The metal nitride material for a thermistor consists of a metal nitride represented by the general formula: (M1−vVv)xAly(N1−wOw)z (where 0.0
US09754704B2 Making thin-film multi-layer micro-wire structure
A method of making a thin-film multi-layer micro-wire structure includes providing a substrate and a layer on the substrate with one or more micro-channels having a width less than or equal to 20 microns. A conductive material including silver nano-particles and having a percent ratio of silver that is greater than or equal to 40% by weight is located in the micro-channels and cured to form an electrically conductive micro-wire. The electrically conductive micro-wire has a width less than or equal to 20 microns and a depth less than or equal to 20 microns. Each micro-wire is electrolessly plated to form a plated layer located at least partially within each micro-channel between the micro-wire and the layer surface in electrical contact with the micro-wire. The plated layer has a thickness less than a thickness of the micro-wire so that the micro-wire and plated layer form the thin-film multi-layer micro-wire.
US09754703B2 Copper alloy wire rod and method for manufacturing the same
A copper alloy wire rod includes a copper parent phase and short fiber-shaped composite phases which are dispersed in the copper parent phase and which contain Cu8Zr3 and Cu, wherein the content of Zr is within the range of 0.2 atomic percent or more and 1.0 atomic percent or less. This copper alloy wire rod can be obtained by including the steps of melting a raw material in such a way that a copper alloy having a Zr content within the above-described range of is produced so as to obtain a molten metal in a melting step, casting the molten metal so as to obtain an ingot in a casting step, and subjecting the ingot to cold wire drawing in a wire drawing step, wherein the wire drawing step and a treatment after the wire drawing step are performed at lower than 500° C.
US09754701B2 Electrical insulation material
Provided is an article containing non-cellulosic nonwoven fabric layer between two non-cellulosic nonwoven paper layers wherein one or both of the nonwoven paper and nonwoven fabric are electrically insulating. At least some embodiments are flame retardant.
US09754699B2 Capacitor oil having excellent properties in wide temperature range
The present invention provides a capacitor oil that can maintain breakdown voltage at a high level in a wide temperature range of −50° C. to 30° C., extremely unlikely precipitates as crystals in particular at −50° C. and thus has excellent properties both at normal temperature and a lower temperature. The capacitor oil of the present invention comprises 1,1-diphenylethane and benzyltoluene, wherein the mass ratio of 1,1-diphenylethane to benzyltoluene is 0.8 to 2.0, the total amount of the ortho-isomer and para-isomer in the benzyltoluene is 90 percent by mass or less, and the composition has a 40° C. kinematic viscosity of 3.00 mm2/s or lower.
US09754698B2 Transparent conductor, method for preparing the same, and optical display including the same
A transparent conductor, a method for preparing the same, and an optical display including the same, the transparent conductor including a base layer; and a conductive layer on the base layer, the conductive layer including metal nanowires and a matrix, wherein the transparent conductor has a transmissive b* value of about 1.5 or less, and the matrix is prepared from a matrix composition including a tri-functional monomer and one of a penta-functional monomer or a hexa-functional monomer a base layer; and a conductive layer formed on the base layer and including metal nanowires and a matrix, wherein the transparent conductor has a transmissive b* value of about 1.5 or less, and the matrix is formed of a composition including a penta- or hexa-functional monomer and a tri-functional monomer.
US09754694B2 Method and device for producing a 99mTc reaction product
A method for producing a reaction product containing 99mTC may include providing 100Mo-metal targets to be irradiated, irradiating the 100Mo-metal target with a proton stream having an energy for the induction of a 100Mo(p, 2n)99mTC core reaction, heating the 100Mo-metal target to over 300° C., recovering incurred 99mTc in a sublimation-extraction process with the aid of oxygen gas which is conducted over the 100 Mo-metal target forming 99mTc-Technetium oxide. Further, a device for producing the reaction product containing 99mTc may include a 100Mo metal target, an acceleration unit for providing a proton stream, which can be directed to the 100Mo-Metal target, such that a 100Mo(p, 2n)99mTC core reaction is induced upon irradiation of the 100Mo-metal target by the proton stream, a gas supply line for conducting oxygen gas onto the irradiated 100Mo-metal target to form 99mTC-Technetium oxide, and a gas discharge line to discharge the sublimated 99mTC-Technetium oxide.
US09754693B2 Low-temperature solidification of radioactive and hazardous wastes
Treatment of a radioactive waste stream is provided by adding sodium hydroxide (NaOH) and/or potassium hydroxide (KOH) together with a rapidly dissolving form of silica, e.g., fumed silica or fly ash. Alternatively, the fumed silica can be first dissolved in a NaOH/KOH solution, which is then combined with the waste solution. Adding a binder that can be a mixture of metakaolin (Al2O3.2SiO2), ground blast furnace slag, fly ash, or other additives. Adding an “enhancer” that can be composed of a group of additives that are used to further enhance the immobilization of heavy metals and key radionuclides such as 99Tc and 129I. An additional step can involve simple mixing of the binder with the activator and enhancer, which can occur in the final waste form container, or in a mixing vessel prior to pumping into the final waste form container, depending on the particular application.
US09754692B2 System for decontaminating soil and the like
An object to be decontaminated contaminated with radioactive material, e.g., contaminated soil or water, is introduced into eluting solvent and dissolved, and the radioactive material is separated from the object to be contaminated by elution of the radioactive material into the eluting solvent. The eluting solvent containing the radioactive materials dissolved therein and the object to be decontaminated are separated into solid and liquid. The soil after solid-liquid separation and from which the radioactive material is removed is collected, and the eluting solvent after solid-liquid separation and a separated liquid containing contaminated water are introduced into an electrolysis tank and electrolyzed. Metal ions such as those of the radioactive materials are deposited on the cathode in the electrolysis tank. Hydrogen containing tritium generated in electrolysis is collected in the electrolysis tank. The hydrogen is moved to the outside of the electrolysis tank and trapped.
US09754691B2 Fluidtight chamber comprising an opening and closing control mechanism for a device providing fluidtight connection between two enclosed volumes
Device for the sealed connection between a first and a second closed space, with the first closed space comprising openings closed off by a door, comprising: first part (A) for securing two closed spaces, second part (B) for securing two doors and of unlocking one of the door, third part (C) for releasing the other door, fourth part (D) for opening a passage between the two closed spaces, a control ring (48) able to be put into rotation around a longitudinal axis (X), with the rotation of the control ring (48) actuating at least the second (B), third (C) and fourth (D), parts, and a device for actuating the control ring and first means.
US09754690B2 Flexible highly filled composition, resulting protective garment, and methods of making the same
A filled composition for radiation shielding includes at least one polymer ingredient and at least one metal-containing filler. The at least one polymer ingredient is selected from the group consisting of a polyolefin elastomer, a polyolefin co-polymer, a polyolefin ter-polymer, and a combination thereof. The polyolefin elastomer, the polyolefin co-polymer, or the polyolefin ter-polymer includes monomer units derived from ethylene and at least one vinyl monomer having more than three carbon atoms. The at least one metal-containing filler is selected from a metal filler, a metal compound or a combination thereof.
US09754687B2 ALD coating of nuclear fuel actinides materials
The invention provides a method of forming a nuclear fuel pellet of a uranium containing fuel alternative to UO2, with the steps of obtaining a fuel form in a powdered state; coating the fuel form in a powdered state with at least one layer of a material; and sintering the powdered fuel form into a fuel pellet. Also provided is a sintered nuclear fuel pellet of a uranium containing fuel alternative to UO2, wherein the pellet is made from particles of fuel, wherein the particles of fuel are particles of a uranium containing moiety, and wherein the fuel particles are coated with at least one layer between about 1 nm to about 4 nm thick of a material using atomic layer deposition, and wherein the at least one layer of the material substantially surrounds each interfacial grain barrier after the powdered fuel form has been sintered.
US09754686B2 Plasma confinement system and methods for use
A plasma confinement system is provided that includes a confinement chamber that includes one or more enclosures of respective helicity injectors. The one or more enclosures are coupled to ports at an outer radius of the confinement chamber. The system further includes one or more conductive coils aligned substantially parallel to the one or more enclosures and a further set of one or more conductive coils respectively surrounding portions of the one or more enclosures. Currents may be provided to the sets of conductive coils to energize a gas within the confinement chamber into a plasma. Further, a heat-exchange system is provided that includes an inner wall, an intermediate wall, an outer wall, and pipe sections configured to carry coolant through cavities formed by the walls.
US09754684B2 Completely utilizing hamming distance for SECDED based ECC DIMMs
In an Error Correction Code (ECC)-based memory, a Single Error Correction Double Error Detection (SECDED) scheme is used with data aggregation to correct more than one error in a memory word received in a memory burst. By completely utilizing the Hamming distance of the SECDED (128,120) code, 8 ECC bits can potentially correct one error in 120 data bits. Each memory burst is effectively “expanded” from its actual 64 data bits to 120 data bits by “sharing” additional 56 data bits from all of the other related bursts. When a cache line of 512 bits is read, the SECDED (128,120) code is used in conjunction with all the received 64 ECC bits to correct more than one error in the actual 64 bits of data in a memory word. The data mapping of the present disclosure translates to a higher rate of error correction than the existing (72,64) SECDED code.
US09754683B2 Method and system to obtain state confidence data using multistrobe read of a non-volatile memory
An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.
US09754682B2 Implementing enhanced performance with read before write to phase change memory
A method and apparatus are provided for implementing enhanced performance with read before write to phase-change-memory. Each write to PCM is preceded by a read and a calculation to discover a location of any bad bits. The write data is converted to a format that can be corrected for a given number of previously undiscovered bit errors, and the writes are unverified.
US09754677B2 Semiconductor memory device, memory system including the same, and operating method thereof
A semiconductor memory device includes a memory cell array including a plurality of memory cells, a read and write circuit temporarily storing program data to be programmed into the memory cell array during a program operation, and reading data stored in the memory cell array and temporarily storing read data during a read operation, and a control logic detecting an error in the program operation by comparing the program data with the read data.
US09754674B2 Concurrently reading first and second pages of memory cells having different page addresses
In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
US09754673B2 Method of initializing and driving 3D non-volatile memory device using time varying erase signal
A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.
US09754670B1 Semiconductor device having sub-block stack structures
A semiconductor device includes sub-block stack structures respectively including source layers, where the sub-block stack structures are disposed to be spaced apart from each other along a first direction, a memory block stack structure including word lines stacked over the sub-block stack structures, the word lines being coupled to memory cells, the memory block stack structure extending along the first direction to overlap the sub-block stack structures, and channel layers respectively coupled to the source layers by penetrating the memory block stack structure.
US09754668B1 Digital perceptron
In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.
US09754666B2 Resistive ratio-based memory cell
An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.
US09754665B2 Vacancy-modulated conductive oxide resistive RAM device including an interfacial oxygen source layer
A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.
US09754663B1 Apparatus for switching voltage and semiconductor memory apparatus having the same
A voltage switching apparatus includes a plurality of high voltage switching circuits operable in response to a single control signal, and suitable for pumping a voltage level of a switching signal to a target level based on the voltage level of the switching signal and a common control unit suitable for generating the single control signal.
US09754661B2 Semiconductor device
A semiconductor device with reduced power consumption. The device includes: an n-type well region overlying the main surface of a semiconductor substrate; an element isolation region overlying the main surface; a first and a second active region located in the n-type well region and surrounded by the element isolation region; an insulating film overlying the main surface in the first active region; a semiconductor layer overlying the insulating film; a gate electrode layer overlying the semiconductor layer through a gate insulating film; a p-type source and a drain region formed in the semiconductor layer at both ends of the gate electrode layer; a dummy gate electrode layer overlying the semiconductor layer through the gate insulating film; an n-type semiconductor region overlying an n-type well region surface in the second active region; and a power supply wiring coupled with the n-type semiconductor region. The dummy gate electrode layer is electrically floating.
US09754660B2 Semiconductor device
Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is electrically connected to the first channel pattern.
US09754655B2 Controlling a refresh mode of a dynamic random access memory (DRAM) die
In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.
US09754651B2 Modular magnetoresistive memory
A magnetoresistive memory element is provided with a read module having a first pinned layer with a magnetoresistance that is readable by a read current received from an external circuit. A write module has a nanocontact that receives a write current from the external circuit and, in turn, imparts a spin torque to a free layer that functions as a shared storage layer for both the read module and the write module.
US09754650B2 Memory device and system supporting command bus training, and operating method thereof
A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.
US09754645B2 Bit line charging for a device
An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.
US09754643B2 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
US09754642B2 Semiconductor memory device
A semiconductor memory device includes a plurality of memory cells, a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column, a data latch storing data indicating whether the first column is defective or not, and a transistor having a first terminal connected to the data bus, a second terminal connected to a voltage source, and a gate connected to an output of the data latch.
US09754638B1 Sense amplifier
Aspects of the disclosure provide a sense amplifier that includes a first amplifying circuit, a second amplifying circuit, a coupling circuit and a detection circuit. The first amplifying circuit is configured to receive an input signal that carries digital values and amplify the input signal to generate a first output. The coupling circuit is configured to combine the input signal with an offset signal to form a combined signal. The offset signal is used to cancel an offset of the first amplifying circuit. The second amplifying circuit is configured to receive the combined signal of the input signal and the offset signal and amplify the combined signal to generate a second output. The first output and the second output are combined to form a combined output. The detection circuit is configured to detect the digital values based on the combined output.
US09754636B2 Hardware-accelerated dynamic voltage and frequency scaling
One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion.
US09754631B2 Disc drive apparatus with hermetically sealed cavity
Certain exemplary aspects of the present disclosure are directed towards a disc drive apparatus. A base deck and a cover are joined to one another by a friction-stir weld along a lip of the cover that extends along a periphery of the cover and over a surface of the base deck. The base deck and cover enclose a cavity, which is hermetically sealed by the weld.
US09754629B2 Methods and apparatuses for processing or defining luminance/color regimes
To allow a better coordination between an image creation artist such as a movie director of photography and the final viewer, via a receiving-side display and its corresponding image processing, a method of adding display rendering specification information to an input image signal (I) comprises determining descriptive data (D) that includes at least identification information for at least one luminance regime subset of pixels of an input image; and encoding the descriptive data (D) into an output description data signal (DDO), relatable to an output image signal (O) based upon an input image signal (I), of the descriptive data (D) in a technical format standardized to be intended for use by a receiving-side display to control its image processing for changing the color properties of its rendered images.
US09754623B2 Intelligent print recognition system and method
A system and method for interactive printed media are disclosed in which a mobile or wearable computing device has an application that captures an image of a piece of printed media and associates a link to the piece of printed media using a backend component to make the piece of printed media interactive. The system and method may be used to generate a piece of printed media that is interactive that may be sent to third parties or to make an existing piece of printed media interactive.
US09754619B1 Optical disc apparatus controlling irradiation position based on cross-correlation value between reproduction signal and decoded signal
In an optical disc apparatus for reproducing information recorded on a track of an optical disc, an optical head irradiates a light beam onto the track, detects a reflected light reflected by the track, and generates a reproduction signal based on the reflected light. A decoder circuit decodes the reproduction signal, and generates a decoded signal including information recorded on the track. A correlation detector circuit calculates a cross-correlation value between the reproduction signal and the decoded signal. A servo circuit detects a deviation amount of an irradiation position of the light beam onto the track, from the reproduction signal, and controls the irradiation position of the optical head based on the cross-correlation value and the deviation amount.
US09754618B1 Heat-assisted magnetic recording (HAMR) medium including a split heat-sink structure (SHSS)
A heat-assisted magnetic recording (HAMR) medium includes a substrate, a split heat-sink structure (SHSS) and a magnetic recording layer. The SHSS includes a first heat-sink layer disposed on the substrate, a heat-sink break layer (HSBL) disposed on the first heat-sink layer, and a second heat-sink layer disposed on the HSBL. The magnetic recording layer is disposed on the SHSS. The SHSS is configured to enable use of a reduced operating current of the laser while maintaining about the same write performance properties as a thermal barrier layer, heat-assisted magnetic recording (TBLHAMR) medium that includes a thermal barrier layer (TBL) and a heat-sink layer that is greater than about 20% thicker than the thickness of the SHSS. A HAMR data storage device that incorporates the HAMR medium within a HAMR disk, and a method for making the HAMR medium are also described.
US09754617B2 Laser diode unit with enhanced thermal conduction to slider
An apparatus comprises a slider having a trailing edge and a leading edge. A laser diode unit comprises a submount and a laser diode mounted to the submount. The submount includes a mounting surface affixed to a first surface of the slider at the trailing edge such that a first surface of the submount faces toward the leading edge of the slider. A thermally conductive material covers the first surface of the submount and at least a portion of the first surface of the slider. The thermally conductive material serves as a thermal conduction pathway between the submount and the slider.
US09754616B2 Magnetic head and system having offset arrays
A computer program product for orienting a head includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a controller to cause the controller to: determine a desired pitch for transducers for reading and/or writing to a magnetic tape; and cause a mechanism to orient a head to achieve the desired pitch. The array of a first of the modules is offset from the array of a second of the modules in a first direction parallel to the axis of the array of the second module such that the transducers of the first module are about aligned with the transducers of the second module in the intended direction of tape travel thereacross when the axes are oriented at an angle greater than 0.2° relative to a line oriented perpendicular to the intended direction of tape travel.
US09754614B1 Plasmon generator including a heat sink layer interposed between two portions formed of different metal materials
A plasmon generator includes: a first portion formed of a first metal material and including a front end face configured to generate near-field light; a second portion formed of a second metal material and located at a distance from the front end face; and a heat sink layer formed of a third metal material, located at a distance from the front end face and interposed between the first portion and the second portion. The second metal material is lower in Vickers hardness and higher in thermal conductivity than the first metal material. The third metal material has a thermal conductivity higher than that of each of the first and second metal materials, and has a Vickers hardness lower than that of the first metal material and higher than that of the second metal material.
US09754611B1 Magnetic recording write apparatus having a stepped conformal trailing shield
A magnetic write apparatus has a media-facing surface (MFS), a pole having leading and trailing surfaces, a trailing shield having a pole-facing surface, a write gap and coil(s). The pole's trailing surface has a portion adjoining the MFS and oriented at a nonzero, acute bevel angle from a direction perpendicular to the MFS. The pole-facing surface includes a first portion adjoining the MFS and oriented at a first angle substantially the same as the bevel angle, a second portion oriented at a second angle greater than the first trailing shield angle, and a third portion oriented at a third angle substantially the same as the first angle. The write gap has first, second and third thicknesses adjacent to the first, second and third portions of the pole-facing surface, respectively. The first thickness is constant. The second thickness varies. The third thickness is constant and greater than the first thickness.
US09754609B2 Method of producing a data storage medium
The present invention relates a method of producing a data storage medium comprising the steps of: a) coating a layer comprising a polymer material onto at least a part of a template surface thereby to obtain a modified template surface; b) clamping the modified template surface produced in step (a) with a target surface thereby to obtain an assembly; and c) introducing a liquid to an environment of the assembly obtained in step (b) thereby to transfer the layer comprising the polymer material of the modified template surface onto at least an adjacent region on the target surface.
US09754607B2 Acoustic scene interpretation systems and related methods
An acoustic-scene interpretation apparatus can have a transducer configured to convert an acoustic signal to a corresponding electrical signal. A feature extractor can receive a sequence of frames representing the electrical signal and extract a plurality of acoustic features corresponding to each frame. An acoustic-scene classifier can be configured to determine a most-likely acoustic state for each frame in the sequence of frames in correspondence with the respective plurality of acoustic features corresponding to the frame and a selected probability distribution of duration of an acoustic state for each of one or more classes of acoustic scenes. Each respective probability distribution of duration can correspond to a selected class of acoustic scenes. The correspondence between acoustic state and probability distribution of duration can be learned from training data corresponding to each of a plurality of classes of acoustic scenes. Related methods also are disclosed.
US09754599B2 Encoder and encoding method, decoder and decoding method, and program
The present technology relates to an encoder and an encoding method, a decoder and a decoding method, and a program by which encoding efficiency is able to be improved by constraining an appearance probability of a predetermined quantization value of an encoding target to 0 when encoding with a combination of Huffman encoding and multidimensional encoding is performed.
US09754591B1 Dialog management context sharing
Features are disclosed for performing functions in response to user requests based on contextual data regarding prior user requests. Users may engage in conversations with a computing device in order to initiate some function or obtain some information. A dialog manager may manage the conversations and store contextual data regarding one or more of the conversations. Processing and responding to subsequent conversations may benefit from the previously stored contextual data by, e.g., reducing the amount of information that a user must provide if the user has already provided the information in the context of a prior conversation. Additional information associated with performing functions responsive to user requests may be shared among applications, further improving efficiency and enhancing the user experience.
US09754588B2 Method and apparatus for voice control user interface with discreet operating mode
An electronic device includes a voice control interface engine operative in a first mode to receive a speech command, through a microphone, from a first distance and produce, through a loudspeaker and in response to the speech command, an audible output at a first output level. One or more processors are operable with one or more proximity sensors to detect objects proximately located with a housing of the electronic device. Where there are none, a timer can be initiated. Upon expiration of the timer, the one or more processors can then transition the voice control interface engine to a second mode operative to receive the speech command from a second distance and produce, in response to the speech command, the audible output at a second output level, where the second distance is greater than the first distance and the second output level is greater than the first output level.
US09754587B2 System and method of using neural transforms of robust audio features for speech processing
A system and method for processing speech includes receiving a first information stream associated with speech, the first information stream comprising micro-modulation features and receiving a second information stream associated with the speech, the second information stream comprising features. The method includes combining, via a non-linear multilayer perceptron, the first information stream and the second information stream to yield a third information stream. The system performs automatic speech recognition on the third information stream. The third information stream can also be used for training HMMs.
US09754581B2 Reminder setting method and apparatus
The present invention, pertaining to the field of speech recognition, discloses a reminder setting method and apparatus. The method includes: acquiring speech signals; acquiring time information in speech signals by using keyword recognition, and determining reminder time for reminder setting according to the time information; acquiring text sequence corresponding to the speech signals by using continuous speech recognition, and determining reminder content for reminder setting according to the time information and the text sequence; and setting a reminder according to the reminder time and the reminder content. According to the present invention, acquiring time information in speech signals by using keyword recognition ensures correctness of time information extraction, and achieves an effect that correct time information is still acquired by keyword recognition to set a reminder even in the case that a recognized text sequence is incorrect due to poor precision in whole text recognition in the speech recognition.
US09754578B2 Loudspeaker horn and cabinet
According to various embodiments, a loudspeaker horn and cabinet are designed to achieve a sound coverage pattern characterized by narrow vertical dispersion and a wide horizontal dispersion. A loudspeaker horn may comprise at least two horn sections, each extending from an inlet to a mouth. A first plurality of outlet channels is disposed in an interleaved column with a second plurality of outlet channels. A loudspeaker cabinet may comprise a primary enclosure having a front wall, the front wall having an aperture in which a low frequency loudspeaker driver is mounted. The loudspeaker cabinet further comprises a top baffle section having a top end and a bottom baffle section having a bottom end, each extending vertically from the primary enclosure. The top baffle section has a first width that gradually increases towards the top end and the bottom section has a second width that gradually increases towards the bottom end.
US09754573B2 Electronic cymbal trigger
According to some aspects, a cymbal system is provided comprising a metal plate, a transducer coupled to the metal plate and configured to detect an acoustic signal generated by a strike of the metal plate, and processing circuitry, electrically connected to the transducer, configured to determine a cymbal articulation for the strike of the metal plate based on the detected acoustic signal. According to some aspects, a method is provided comprising the steps of detecting an acoustic signal generated by a strike of a metal plate, and determining a cymbal articulation for the strike of the metal plate based on the detected acoustic signal.
US09754569B2 Audio matching with semantic audio recognition and report generation
System, apparatus and method for determining semantic information from audio, where incoming audio is sampled and processed to extract audio features, including temporal, spectral, harmonic and rhythmic features. The extracted audio features are compared to stored audio templates that include ranges and/or values for certain features and are tagged for specific ranges and/or values. The semantic information may be associated with audio signature dataExtracted audio features that are most similar to one or more templates from the comparison are identified according to the tagged information. The tags are used to determine the semantic audio data that includes genre, instrumentation, style, acoustical dynamics, and emotive descriptor for the audio signal.
US09754567B1 System and method for transportation and performance of musical drums
A drum cart for supporting and transporting a drum set between locations. The drum cart includes support arms, a handle, wheels and a support bracket adapted to releasably couple a bass drum to the drum cart and place the bass drum into a performance position by lying the drum cart on the ground horizontally.
US09754563B1 Force adjustable spring-clamp capo
The present utility model discloses a force adjustable spring-clamp capo, comprises a string-engaging arm and a damping arm, the string-engaging arm and the clamping arm are hinged together by a composite pressing rivet, wherein a pressure adjustment mechanism is further arranged in a middle of the clamping arm, including: a pressure spring, a regulation screw and a regulation nut, by the pressure adjustment mechanism, a collapsing length of the pressure spring is adjusted, making the force of the spring change (Hooke's law), which makes the clamping force of the capo adjustable, it can also be operated by a single hand of a player as the spring-damp capo, thus owns a simple and easy operation, making a player be able to adjust to a best clamping force according to a requirement of the instrument thereof, to achieve a role of a tune transfer assistance perfectly. By a planar thrust bearing embedded in the regulation nut, the present utility model further reduces the resistance generated by the friction between the regulation nut and the clamping arm greatly, thus simplifies the operation of a force adjustment, and achieves the purpose of effort saving.
US09754562B2 Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.
US09754561B2 Managing memory regions to support sparse mappings
One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
US09754560B2 Pooling and tiling data images from memory to draw windows on a display device
The instant application discloses receiving a command via a processor to initiate a window creation operation on a client computing device, retrieving at least one image tile pre-allocated in a memory of the client computing device, performing a draw operation that places at least one image overplayed onto the at least one image tile and displaying the image overplayed onto the at least one image tile on a display of the client computing device.
US09754558B2 Heads-up scrolling
Methods, program products, and systems for heads-up scrolling are described. In heads-up scrolling, a scrolling control can be used to scroll through multiple data records in a database. When a slider of the scrolling control receives an input dragging the slider, a semitransparent window can be overlaid on content being displayed. The semitransparent window can have a user-specified layout for formatting one or more data fields of a data record. When the slider is dragged, the content being overlaid upon can remain static. Content in the semitransparent window can be updated to reflect content in a data record corresponding to a position of the slider. The content in the semitransparent window can be formatted according to the user-specified layout, which may be different from a format of the content under the semitransparent window.
US09754556B2 Electronic display locket and system
A locket includes a chamber and a door, with the chamber housing an electronic display, a microprocessor with associated memory coupled thereto, a wireless transceiver coupled to the microprocessor, and a power source. Messages/pictures can be displayed on the display through use of a system incorporating the locket, a mobile unit having a locket application and a wireless transceiver, and an application server device with a database. The system may also include a separately networked computer-type device. A locket user can log into the application server, register the locket, and create a user profile including one or more of interests, personal information, social connections, etc., that would establish how the locket can receive content. The system allows permitted friends to send messages/pictures through the application server to the locket for display.
US09754553B2 Electronic device and method of controlling a screen of an external electronic device
An electronic device and method of controlling a screen of an external electronic device are provided. The method includes connecting with the external electronic device; determining whether a screen control event for controlling the screen of the external electronic device is generated; and transmitting screen control information corresponding to the screen control event to the external electronic device, if the screen control event is generated.
US09754537B2 Organic light emitting display device and driving method thereof
An organic light emitting display device includes a scan driver progressively supplying a scan signal to scan lines, a data driver supplying data signals to output lines of the data driver during a period in which the scan signal is supplied, and demultiplexers respectively coupled to the output lines of the data driver, and supplying the data signals to data lines, each demultiplexer including first switches, each first switch being coupled between an output line of the data driver and a data line among a first set of data lines, and a second switch coupled between a first initialization power source and a data line among a second set of data lines, wherein the first set of data lines includes the second set of data lines and at least one other data line.
US09754525B2 Display panel and driving method thereof and display device
A display panel and a driving method thereof and a display device are disclosed, and the display panel includes two sets of pixel driving circuits; and, for every two adjacent pixel columns for each primary color, an operating voltage line for one pixel column is connected to a first set of pixel driving circuits via a connection point located at a side of a pixel array where the pixels in the first row of a pixel array are located, and an operating voltage line for the other pixel column which is connected to the second set of pixel driving circuits via a connection point located at a side of the pixel array where the pixels in the last row of the pixel array are located. The display panel can ensure the uniformity of the display luminance of the whole display panel.
US09754524B2 Display driver
A display driver is provided which can prevent concentration of currents flowing into a display device and display a high-quality image without uneven luminance. A plurality of delayed clock signals used to apply a plurality of pixel driving voltages to data lines of the display device at respective different timings are generated by a DLL circuit including a variable delay circuit group constituted by variable delay circuits are connected in series, and a phase comparator that detects a phase difference of a delayed clock signal with respect to a reference clock signal and adjusts a delay amount of each of the variable delay circuits so that the phase difference converges to zero.
US09754522B2 Curved display device and luminance correction method for driving the same
A display device includes a curvature-variable display panel including a plurality of pixels; a controller configured to correct and output an image signal supplied from the outside according to a radius of curvature of the display panel; a data driver configured to supply a data signal corresponding to the corrected image signal to a data line connected to the pixel; and a scan driver configured to supply a scan signal synchronized with the data signal to a scan line connected to the pixel. The controller may include a curvature detector configured to detect the radius of curvature of the display panel and a lookup table generator configured to generate a correction lookup table according to the radius of curvature of the display panel.
US09754520B2 Flexible display apparatus and controlling method thereof
A flexible display apparatus is provided. The flexible display apparatus includes a display unit, a sensor configured to sense a bending of the flexible display apparatus, and a controller configured to display first contents on a first screen of the display unit, and to reconfigure and display the first contents on a second screen generated on an area of the display unit based on the bending.
US09754517B1 Methods and apparatus for solar powered oscillating design display
An oscillating design display is described. Such a design may include virtually any personalized design a customer may desire. By generation of a magnetic field from an induction coil, such a displayed design may be made to oscillate between two endpoints in a single plane of motion. Such an induction coil may be powered by solar energy.
US09754515B2 Support for communication elements in points of sale of products
A support (1) for communication elements in points of sale of products comprising a supporting body (2), which can be anchored to the structure of an exhibitor (3) for products and defines at least one coupling region (4) for at least one electronic tag (5), which has at least one face (5a) for displaying commercial information; the electronic tag (5) supports engagement means (6) for at least one communication element (7).
US09754514B2 Adjustable friction joint assembly for crash test dummy
An adjustable friction joint assembly for a crash test dummy includes a first joint member for connection to a first member of the crash test dummy and a second joint member for connection to a second member of the crash test dummy. The adjustable friction joint assembly also includes a shaft operatively connected to the first joint member and the second joint member to allow rotation therebetween. The adjustable friction joint assembly further includes an adjustable friction assembly operatively connected to the shaft and operatively cooperating with the first joint member and the second joint member to adjust a friction tightness of the joint assembly.
US09754505B2 Method for training staff in quality control
A method for training staff for quality control when filling amorphous products into primary packaging. The method includes a provision step during which a test set having a plurality of primary packages filled with an amorphous product is provided, wherein at least one of the filled primary packages is afflicted by a contaminant comprising a fluorescent marker. A training step includes presenting the test set to a person to be trained, who carries out a visual quality control for detecting contaminants. The result of the training step is documented. A verification step is conducted during which the test set is irradiated by excitation light, wherein fluorescing contaminants are detected and the result of the verification step is documented. A comparison step is done during which the result of the training step and the result of the verification step are compared. Also disclosed is an inventive test kit and test set.
US09754502B2 Stimulus recognition training and detection methods
A method of monitoring a trainee to determine when the trainee subconsciously identifies an object previously associated with a desired trainee response includes attaching at least one biological response sensor to the trainee and receiving biological response data of the trainee from the at least one biological response sensor. The method further includes comparing the biological response data of the trainee to biological responses linked to different ones of a plurality of trainee responses using a processor in communication with the at least one biological response sensor, the plurality of trainee responses including the desired trainee response, and detecting trainee recognition of the object previously associated with the desired trainee response based, in part, on the biological response data being linked to the desired trainee response included with the plurality of trainee responses. The desired trainee response is below the conscious awareness of the trainee.
US09754500B2 Curriculum assessment
One or more embodiments of techniques or systems for curriculum assessment are provided herein. One or more assessments can be generated. For example, an assessment can be generated based on one or more forms. In this way, assessments can be created in a structured manner and distributed accordingly. One or more of the assessments may be administered. After one or more students or test takers take the assessments, one or more of the assessments can be analyzed or aggregated. Analysis can include statistical analysis related to one or more similar, related, or associated assessments. In this manner, curriculum assessment can be provided, thereby enhancing teaching efficiency and productivity, etc.
US09754496B2 System and method for management of airspace for unmanned aircraft
A system and method for management of airspace for unmanned aircraft is disclosed. The system and method comprises administration of the airspace including designation of flyways and zones with reference to features in the region. The system and method comprises administration of aircraft including registration of aircraft and mission. A monitoring system tracks conditions and aircraft traffic in the airspace. Aircraft may be configured to transact with the management system including to obtain rights/priority by license and to operate in the airspace under direction of the system. The system and aircraft may be configured for dynamic transactions (e.g. licensing/routing). The system will set rates for licenses and use/access to the airspace and aircraft will be billed/pay for use/access of the airspace at rates using data from data sources.
US09754493B2 Vehicular traffic guidance and coordination system and method
A system and method for guiding and coordinating vehicular traffic determine tasks to be completed by vehicles in a transportation network in order to complete an objective, allocate the tasks among the vehicles, and determine sets of allowable actions for the vehicles based on the allocation of the tasks. The sets of allowable actions dictate plural different allowable actions that the vehicles are allowed to perform in order to complete the tasks allocated to the vehicles. The allowable actions are determined such that the vehicles are scheduled to complete the tasks and complete the objective without the vehicles colliding or blocking movement of each other. The allowable actions are communicated to the vehicles such that the vehicles are permitted to select one or more of the allowable actions and prohibited from performing one or more other actions during performance of the tasks allocated to the vehicles.
US09754485B2 Traffic prediction and real time analysis system
A traffic routing and analysis system uses data from individual cellular or mobile devices to determine traffic density within a transportation network, such as subways, busses, roads, pedestrian walkways, or other networks. The system may use historical data derived from monitoring people's travel patterns, and may compare historical data to real time or near real time data to detect abnormalities. The system may be used for policy analysis, predicted commute times and route selection based on traffic patterns, as well as broadcast statistics that may be displayed to commuters. The system may be accessed through an application programming interface (API) for various applications, which may include applications that run on mobile devices, desktop or cloud based computers, or other devices.
US09754482B2 Remote control device and remote control system
A control target device is specified using a remote control device with a simple configuration. The remote control device includes: a communication unit that receives a received signal strength from each of a plurality of electronic devices and transmits a predetermined control command to a control target device; and a control target device specifying unit that specifies, as the control target device, a device having a maximum variation of the received signal strength among the plurality of electronic devices. The communication unit includes an antenna disposed at an end of a housing, and the antenna has directivity at which a direction in which the end of the housing is directed to a reception side is a substantially null direction.
US09754480B2 System and method for controlling device location determination
A controlling device such as a remote control has programming for transmitting a signal response to a plurality of control environments, each environment including a signaling device. Each signaling device in receipt of the signal request sends a signal response having a unique ID which is chosen to be characteristically attenuated by the surroundings of the environment. Because the controlling device can only be in one environment at a given time, and given the attenuation characteristics of the signal response from each signaling device, only one signal response will be received by the controlling device in each environment. Location definitions associated with the received unique ID may be used by programming in the controlling device to recall saved devices states, commands sets, macros, and even to dynamically generate commands based on the location information.
US09754478B1 Reducing nuisance notifications from a building automation system
Reducing nuisance notifications from building automation systems is described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to receive a notification of an alarm from a building automation system, compare attributes of the alarm to attributes of alarms included in a database of suppressed alarms, refrain from transmitting a notification of the alarm to a mobile device in response to the attributes of the alarm matching attributes of any of the alarms in the database, and transmit a notification of the alarm to a mobile device in response to the attributes of the alarm not matching the attributes of any of the alarms in the database.
US09754476B2 Hospital bed with patient weight and displacement sensors
A system for determining a location of a patient on a hospital bed comprising: at least one deformation sensor adapted to generate a signal indicative of a deformation of a frame of the bed; a location determination unit for determining a lateral and/or longitudinal location of the patient based on the deformation of the frame. A method for monitoring an exit of a patient from a hospital bed comprising: determining a patient location on the bed based on measured deformation and generating an alarm signal if the determined location is outside a predetermined area. A weight sensing system for a hospital bed having a base with a suspended frame suspended from a fixed frame comprising: a load sensor connecting the suspended frame and the fixed frame via a suspension member which is unsecured from the fixed frame to allow free vertical movement of the suspended frame relative to the fixed frame.
US09754473B1 Automotive on-board diagnostic computer system with audiovisual guiding function
An automotive on-board diagnostic (OBD) computer system with an audiovisual guiding function includes an OBD main unit and a transmission connector. The OBD main unit includes a transmission port, a control unit, a receiving unit, a guide light, a sound unit, and a first sensing unit. The transmission connector includes a control module, an illumination unit, a transmitting unit, and a second sensing unit. Once activated, the control module not only turns on the illumination unit to provide illumination light, but also drives the transmitting unit to send a control signal to the receiving unit of the transmission port, in order for the control unit to turn on the guide light and the sound unit according to the control signal. The guiding light and instruction sound provided respectively by the guide light and the sound unit can help the user locate the transmission port.
US09754467B1 Interactive notification system for remote control of a gun safe or the like
An interactive notification system allows the owner of a safe (or any type of vault for protecting personal property) to be contacted when an alarm condition is triggered. The system is configured to respond to a return message signal from the owner to either allow or deny any continued action with the safe. Thus, the owner remains in control of all actions involving the safe, regardless of his physical location. The notification is typically sent electronically to one or more of the owner's communication devices (phone, tablet, computer, etc.), where the owner responds via the same method.
US09754464B1 Haptic communications
Providing haptic communications includes attaching to skin of a user a haptic device that produces touch impulses, electronically transmitting a message to the haptic device, converting the message to touch impulses, and providing the touch impulses to the user. Messages may be converted to touch impulses using coding from the Braille system or Morse code. Messages may be converted to touch impulses using Braille coding where the touch impulses are provided by a positional matrix that is part of the device. Messages may be converted to touch impulses using Morse coding where a Morse code dot is provided by a brief touch and where a Morse code dash is provided by a longer touch. The haptic device may be a patch or a sticker attached to the user with a biocompatible adhesive. The haptic device may notify the user of receipt of a new message using special touch symbols.
US09754461B1 Service messaging system and method for a transaction machine
A method includes receiving identification information at a transaction machine, the identification information being associated with an account holder, accessing, using the identification information, activity profile information for the account holder, determining screen content for the transaction machine based on the activity profile information, and displaying the screen content to the account holder via a display screen of the transaction machine.
US09754459B1 Slot machine with synchronized spinning reels
A slot machine that can spin two or more of the reels in unison. Thus, the machine can spin and stop the reels in a standard fashion. If a special trigger occurs, then two or more reels can further spin with an identical offset. The further spin can generate additional rewards for the player.
US09754456B2 Amusement machine of the pusher type
Amusement machine of the pusher type, comprising a playing surface on which a plurality of playing pieces as well as one or more prizes are supported, wherein the prizes have a shape and/or size differing from the shape and/or size of a playing piece, and a playing piece pusher configured to move over the playing surface at successive points in time in order to disturb the plurality of playing pieces and prizes supported on the playing surface; a transport system with at least one collecting location for collecting the one or more playing pieces and prizes which have dropped over the edge, and at least one infeed location which lies higher than the at least one collecting location, which transport system is configured to reintroduce the one or more playing pieces and prizes onto the playing surface from the at least one infeed location; and to transport the one or more playing pieces and prizes from the at least one collecting location to the at least one infeed location.
US09754454B2 Method and system for lottery application
Systems and methods of the invention relate to integrating into an existing hard copy lottery ticket system for adaptation to sell soft copies of lottery tickets. A master virtual device can provide data communications related to a sale of a soft copy of a lottery ticket to a master terminal such that the master terminal processes the sale to a lottery authority as if the sale is for a hard copy of the lottery ticket. The master virtual device can include a virtual lottery application that is configured to receive data related to a request to purchase a soft copy of a lottery ticket, format and communicate such data to the master terminal, and communicate confirmation of the soft copy of the lottery ticket.
US09754453B2 System and method for enhanced sports pool raffle
A system for an electronic raffle based on the final score of at least one sporting event. Tickets are sold which are assigned at least one unique outcome of the at least one sporting event. The winning ticket is dictated by the matching of the scores on the ticket with the actual scores of the sporting event. If a winning ticket is not sold, or there is an anomaly in that a score or scores is outside the range of scores that are in the pool, a winner is chosen from a random drawing of the tickets sold.
US09754452B2 Bonus event in slot machine play
A method and apparatus provides a bonus event on an electronic video gaming machine having touchscreen sensitivity on a video display in communication with a processor. The method includes: a) triggering a bonus event; b) providing and displaying at least one wild card symbol in a fixed position in columns and rows used to determine a bonus outcome; c) the processor generates a first random symbol for use in the bonus game which is displayed on the video gaming machine; d) the touch screen is activated so that a final position for the first random symbol is selectable by touchscreen activity; e) the processor filling the unfilled frames with random symbols; and f) the processor resolving a bonus outcome of the bonus outcome according to paylines within the columns and rows used to determine the bonus outcome.
US09754446B2 Products and processes for operations management of casino, leisure and hospitality industry
In various embodiments of this invention, a suite of customized computer software applications, a linked or wireless computer network and accessory components cooperate to enhance and extend customer and employee resource management in the casino/gaming environment.
US09754445B2 Stress detecting input device for a gaming machine
A gaming system that includes an input device with a sensor configured to measure data associated with an interaction of a player with the input device during play of a game on the gaming machine. The gaming system further includes a processor programmed to receive measured data from the sensor, determine, from the received measured data, that the interaction of the player with the input device exceeds an acceptable interaction threshold level, associate one or more gaming events that correspond to the determination that the interaction of the player with the input device exceeds the acceptable interaction threshold level, and determine a mental state of the player based on: the associated one or more gaming events, and the determination that the interaction of the player with the input device exceeds the acceptable interaction threshold level.
US09754443B2 System and method for remote control gaming sessions using a mobile device
Various embodiments directed to systems and methods that enable remote play of a game hosted by a gaming machine using a mobile device are disclosed herein. In one embodiment, the system includes a network in communication with the gaming machine and the mobile device, and the network includes a first wireless access point located in a first area and a second wireless access point located in a second area of a venue. Also included is a remote gaming server in communication with the gaming machine and mobile device over the network. The remote gaming server enables remote play when the mobile device is connected to the second wireless access point and prevents remote play when the mobile device is connected to the first wireless access point.
US09754442B2 3D enhanced gaming machine with foreground and background game surfaces
Disclosed is an electronic gaming machine that includes an electronic data store storing game data for a given game; an electronic 3D-enabled gaming display; and one or more processors. The processors are configured to: generate, with at least a three-dimensional graphics processor, game surfaces using the game data, each of the game surfaces for displaying at least one game symbol thereon; present a three-dimensional view of the game surfaces on the electronic display, the game surfaces arranged in layers such that a foreground game surface appears to be closer to the user than a background game surface; and in response to a game trigger event: remove at least one game symbol displayed on the foreground game surface from the game; and integrate at least one game symbol displayed on the background game surface into the game such that the integrated game symbol interacts with remaining game symbols displayed on the foreground game surface.
US09754441B1 Game systems and related methods
A game system includes a server coupled with a database and an operator computer. The operator computer receives input from an operator to associate, through the database, a prize identifier and a winning tap number for a prize. A plurality of player devices coupled with the server through a telecommunication network display player interfaces including the prize identifier, winning tap number, and a defined tapping area. Each player device, in response to a tap in the defined tapping area, communicates a tap signal to the server. The server generates an assigned tap number for each tap signal. In response to determining that an assigned tap number matches the winning tap number, the server sends a winning signal to the sending device. The game system provides an advertising platform through sponsored prizes and paid advertising viewed by players to enable players to continue tapping for sponsored prizes.
US09754440B2 Game information consolidation system
A game playing information integration system is provided which is capable of objectively performing selection and/or settings according to preference of a player, and is capable of effectively making entry into market, based on a result of logical analysis of a gaming machine invoking demands of a player as a user and a manger in gaming facility in a well-balanced manner. The system includes a plurality of gaming machine units and a server connected to enable communication with each gaming machine unit. Each gaming machine unit includes player identification information reading means, number-of-consumptions data output means, and number-of-payouts data output means. Gaming machine unit identification information is individually assigned to each of the gaming machine units. The server stores data storage means for storing each of number-of-consumptions data and number-of-payouts data in association with reception time data, player identification information, and gaming machine unit identification information.
US09754436B1 Banknote cash unit
A banknote cash unit capable of securely sealing an opening of a storage bag is disclosed. The storage bag has a first fixation tab and a second fixation tab. The opening is defined between the first fixation tab and the second fixation tab. The banknote cash unit includes a housing, a banknote inlet unit and a paper sheet storing unit. The banknote inlet unit is disposed on the housing. The paper sheet storing unit is installed in the housing and for holding the storage bag. The paper sheet storing unit includes a first sealing module and a second sealing module disposed next to the first sealing module. When the second fixation tab is closed to the first fixation, the first sealing module generates a first sealing portion and the second sealing module generates a second sealing portion, so as to combine the first fixation tab and the second fixation tab.
US09754435B2 Device for the insertion of paper valuables in closable containers, with control and storage of valuables entering the container
A device for the insertion of banknotes into containers in machines suitable for receiving and handling banknotes, comprises a container for the banknotes, adapted to be closed and removed from the machine once filled, and a loading path, diverting from a circulation path inside the machine and ending at said container, for the insertion of banknotes into the container. The device further comprises at least one scanner, placed along the loading path, for the optical detection of images of the banknotes entering into the container and a memory connected to the scanner for storing the images detected thereby.
US09754432B2 Wireless communication protocol based lock management
In an approach for enhancing physical security, a processor receives, via a wireless communication protocol, a first set of information from a first device associated with a first person. A processor compares the first set of information to a predefined rule, wherein the predefined rule specifies whether a lock can be engaged. A processor determines that the lock cannot be engaged, based on the first information and the predefined rule.
US09754431B2 Method and system for a key fob base station enabling remote car access using a nomadic device
A vehicle key base station is configured to comprise at least one controller in communication with a key fob and a nomadic device using one or more transceivers. The at least one controller may be configured to receive a security code request from the nomadic device. The at least one controller may be further configured to verify the nomadic device is approved to communicate with vehicle key fob based on a pre-registration configuration. If the nomadic device is approved, the at least one controller may be further configured to transmit the request to the key fob and receive the vehicle security code from the key fob. The at least one controller may be further configured to transmit the vehicle security code to the nomadic device.
US09754430B1 Method and apparatus for providing instructions about manual release
A method and apparatus for providing instructions to operate a manual release are provided. The method includes detecting a condition for providing a notification to operate a manual release of the vehicle; and controlling to output the notification to operate the manual release based on the detected condition. The apparatus and method may be used in a vehicle or other apparatus to prevent a user from being hindered from egress in a vehicle during times at which the electronic door release is not operable.
US09754429B2 System for monitoring a set of components of a device
A system for monitoring a set of components of a device, including: a detecting system including a set of agents for detecting anomalies, with each agent receiving measurements on physical parameters relating to a sub-set of components of a device and delivering an initial distribution of the probability of an anomaly; an acquiring system which receives feedback information and the initial distributions of the probability of an anomaly from the agents; an emerging system which iteratively emerges current distributions of the probability of an anomaly, with the current distributions of the probability of an anomaly converging towards a set of optimum distributions of the probability of an anomaly; and a synthesizing system which synthesizes optimum distributions of the probability of an anomaly relating to at least one sub-set of interest of components of the device in order to extract the risks of an anomaly specific to the sub-set of interest.
US09754428B2 Interactive timeline interface and data visualization
A computer system and method for storing and processing GPS data for a plurality of drivers and vehicles to provide a visual representation of driver's activity for fleets of driver and vehicles.
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