| Document | Document Title |
|---|---|
| US09705885B2 |
Trusted social network
A trust management engine maintains transferable files in a file data store of a data server accessible to users in a trust list of trusted users authorized to access the transferable files. The trust management engine facilitates a transmission of an email message containing a link to the transferable files to each of the users in the trust list. The email message is stored in an email server that is separate from the data server. The trust management engine receives a request from one of the users in the trust list of trusted users to access the transferable files in response to a selection of the link in the email message. In response to the request, the trust management engine facilitates a transmission of the one or more transferable files from the file data store to the requesting user. |
| US09705881B2 |
Identity pool bridging for managed directory services
A customer of a computing resource service provider may utilize a set of credentials to request creation of an identity pool within a managed directory service. Accordingly, the managed directory service may create the identity pool. Instead of having the customer create a separate account within this identity pool, the managed directory service may create a shadow administrator account within the identity pool, which may be used to manage other users and resources in the identity pool within the managed directory service. The managed directory service further exposes an application programming interface command that may be used to obtain a set of credentials for accessing the shadow administrator account. The customer may use this command to receive the set of credentials and access the shadow administrator account. Accordingly, the customer can manage users and resources in the identity pool within the managed directory service. |
| US09705874B2 |
Communication apparatus, reminder apparatus, and information recording medium
Provided is a communication apparatus (121) that securely manages passwords for utilizing a server apparatus. A generator (203) generates a random table having the same number of rows and the same number of columns as a password table associated with a server name specified in an authentication request received by a receiver (202). An acceptor (205) accepts a key from a user to whom the random table is presented by a presenter (204). An identification unit (206) identifies, from the key and the random table, the user's of selection order of elements in the table. An acquirer (207) selects and arranges elements in the password table in the identified selection order, thereby acquiring a password. An output unit (208) displays the acquired password on a display or transmits the acquired password to the server apparatus, thereby allowing the user to utilize the server apparatus. |
| US09705873B2 |
Multi-tenant discovery and claiming of distributed storage nodes over an insecure network
A technique is introduced that enables a server to establish trust of and a secure channel of communication with an unverified client computer, which can be on a different insecure network. To establish trust, the server needs to ensure that the client computer is legitimate, and the client computer similarly needs to ensure that the server is legitimate. With mutual trust established, a secure channel of communication is established between the server and the client computer. With mutual trust and a secure channel of communication established, the client computer can safely communicate with the server, for example, to download software that enables the client computer to join a central management system at the server. |
| US09705871B2 |
Identity and access management
An access management account that includes an access identifier may be used to control access to telecommunications services or applications. An access identifier is designated for obtaining access to multiple telecommunications services or applications, in which the multiple telecommunications services or applications are accessible to a user through multiple user accounts that are protected by account credentials. Once the access credential is designated, the access credential may be used to determine whether access to the one or more telecommunications services or applications is to be granted instead of using the account credentials of the multiple user accounts. |
| US09705864B2 |
Media session resumption in web session restoration
A call establishing method comprising registering with a server to obtain authorization credentials, obtaining a client encryption key using the authorization credentials, wherein the client encryption key is uniquely associated with a web session, establishing a media session for the web session, creating a client side call state for the media session using the client encryption key, wherein the client side call state comprises call information that is associated with the web session and the media session, and wherein the client side call state is encrypted using the client encryption key, and storing the client side call state within a network device. |
| US09705861B2 |
Method of authorizing a person, an authorizing architecture and a computer program product
The invention relates to a method for authorizing a person. The method comprises the step of receiving authentication data from a personal authentication device transmitting said data to a reader associated with a central authorization system. Further, the method comprises the steps of including the received authentication data in a request message and transmitting the request message to the central authorization system, receiving the request message at the central authorization system and retrieving the authentication data from the request message. The method also comprises the steps of performing an authentication process at a central authentication system using said reader authentication data and executing an authorization process at the central authorization system based on the authentication process result. |
| US09705858B2 |
Information processing device and information processing method to maintain secret key for authentication
There is provided an information processing device including an information storage unit configured to store information about a state in which a first secret key used during authentication is held in devices, and information about connection between the devices, and a communication unit configured to send the first secret key so that the first secret key is delivered to the devices based on the information stored in the information storage unit. |
| US09705850B2 |
Enabling comparable data access control for lightweight mobile devices in clouds
A new efficient framework based on a Constant-size Ciphertext Policy Comparative Attribute-Based Encryption (CCP-CABE) approach. CCP-CABE assists lightweight mobile devices and storing privacy-sensitive sensitive data into cloudbased storage by offloading major cryptography-computation overhead into the cloud without exposing data content to the cloud. CCP-CABE extends existing attribute-based data access control solutions by incorporating comparable attributes to incorporate more flexible security access control policies. CCP-CABE generates constant-size ciphertext regardless of the number of involved attributes, which is suitable for mobile devices considering their limited communication and storage capacities. |
| US09705849B2 |
Technologies for distributed detection of security anomalies
Technologies for distributed detection of security anomalies include a computing device to establish a trusted relationship with a security server. The computing device reads one or more packets of at least one of an inter-virtual network function network or an inter-virtual network function component network in response to establishing the trusted relationship and performs a security threat assessment of the one or more packets. The computing device transmits the security threat assessment to the security server. |
| US09705843B2 |
Method and system for domain name system based discovery of devices and objects
The Specific service instances are requested by a client via a client application. The request is received by a Domain Name System (DNS). The request is resolved by the DNS by determining from information recorded in a DNS system memory and conveyed in the request, a first type T1 of service and a first list L1 of service instances associated with the first type T1. The DNS then searches for a linked structure in a TXT resource record for the first type T1. The linked structure identifies another list L2 of service instances associated with a subtype T2 of service. Then iteratively, for i=2, . . . , N+1, N being a number of the subtypes of service associated with the first type T1 of service, searching a TXT resource record for a linked structure identifying a corresponding subtype Ti of service and identifying a list Li+1 of service instances associated with the subtype Ti+1. |
| US09705842B2 |
Integrating communication modes in persistent conversations
Systems, methods and computer readable media for persistent conversations are described. In some implementations, a method can include receiving a communication message sent from a first user to at least one other user and generating a persistent conversation object having a conversation content section and conversation state information. The method can also include storing the communication message in the conversation content section of the persistent conversation object and forwarding the communication message to the at least one other user. The method can further include updating the conversation state information to reflect the receiving, storing and forwarding of the communication message. |
| US09705840B2 |
Automation platform for hub-based system federating disparate unified communications systems
An automation platform for a hub-based system federating disparate unified communications systems is provided. According to one embodiment, the method includes connecting a first unified communications system supporting a first domain and an automation platform to a federation server, where the automation platform includes a plurality of automated applications that includes a social media automated application, an instant messaging automated application and a directory search automated application. The method further includes routing a message from the first unified communications system to an automated application of the plurality of automated applications, processing the message by the automated application, and issuing a command based on the processed message. |
| US09705839B2 |
Client side social network response tracking
Embodiments of the present invention address deficiencies of the art in respect to response subscriptions and provide a method, system and computer program product for response tracking across social networks. In one embodiment of the invention, a social networking response tracking method can be provided. The method can be performed by client-side logic and can include associating subscribers with a user or a group of users based upon a posting by the user or a user in the group of users within a client computing device for the user, aggregating different postings from the user to correspondingly different forums disposed about a global computer communications network, and, notifying the subscribers of the aggregated postings. |
| US09705835B2 |
Collaboration management systems
Systems, configurations, and methods of managing collaboration of content are disclosed. A content collaboration system can be configured to manage collaborating subject matter within one or more activity streams. A user can create a new collaboration object associated with particular content using the content collaboration system. The content collaboration system is configured to format data related to the collaboration object according to the different activity stream formats and to insert the formatted data into the one or more activity streams. Other users are allowed to collaborate around the particular content on the different activity streams. The content collaboration system is configured to update the collaboration object according to the collaboration on the different activity streams. |
| US09705834B2 |
System and method for analyzing communications
The invention provides a system and method for analyzing a collection of communication messages. The communication messages may be any one of a collection of electronic mail messages, voicemail messages, instant messaging dialogues and other forms of communications. The collections of communications, such as electronic mail messages, may be selected by a user and then subsequently processed to determine the identity of any of the user's contacts within the communications. The contacts may then be arranged in a relative priority arrangement whereby contacts which have been identified as engaging in prior reciprocal communications with the user are given higher priority. Higher priority may also be given to contacts which engage in more recent communications with the user. Specific contact relationships may be inferred from the communications depending on whether specific contacts are repeatedly mentioned within the communication messages. |
| US09705828B2 |
Mobile terminal and controlling method thereof
A mobile terminal including a touchscreen; a wireless communication unit; and a controller configured to display a group chat window on the touchscreen including a history of messages transceived via the wireless communication unit with a plurality of counterpart terminals, receive a selection of a prescribed counterpart terminal for transmitting a private message to the prescribed counterpart terminal, receive an input message in the group chat window for the prescribed counterpart terminal, and transmit the input message as the private message to the prescribed counterpart terminal without switching to an individual chat window with the prescribed counterpart terminal. |
| US09705821B1 |
Methods for provisioning applications based on anticipated user work load and devices thereof
A method, non-transitory computer readable medium and an application manager computing device that assists with provisioning applications based on user anticipated workloads includes obtaining, a user anticipated resource based on information within a user workload database, prior to receiving a request from a client computing device. The obtained user anticipated resource is provisioned. The provisioned user anticipated resource is provided upon establishing a session with the requesting client computing device. |
| US09705819B1 |
Devices, systems, apparatus, and methods for transparent and automated optimization of storage resource allocation in a cloud services system
A device or system includes a plurality of storage resources each associated with a respective performance class, each being associated with selected performance characteristics such as IOPS, bandwidth, etc. The device or system includes a compute instance having access to allocated storage resources, the allocated storage devices including one or more storage resources. The device or system also includes an optimization component adapted to obtain information relating to utilization by the compute instance component of the allocated storage resources, determine that a change to the allocated storage resources is necessary, based on the information, cause data to be migrated from a first storage resource associated with a first performance class to a second storage resource associated with a second storage class, and cause a removal from the allocated storage resources of the first storage resource and an addition to the allocated storage resources of the second storage resource. |
| US09705818B2 |
Method, apparatus, and system for assigning tributary port number
Embodiments of the present invention relate a method, an apparatus, and a system for assigning a tributary port number. The method includes: receiving a service path request message including a service type for establishing a service path used to bear a Lower Order ODU service; determining an OTU link; determining a free tributary slot resource in the OTU link; if a MSI bytes in the OTU link indicates a service type, assigning a tributary port number other than tributary port numbers used by Lower Order ODU services having the same type as the Lower Order ODU service in the OTU link; or if the MSI bytes in the OTU link does not indicate a service type, assigning a tributary port number other than tributary port numbers used by all types of Lower Order ODU services in the OTU link; and sending a service path acknowledgment message to the neighboring node. |
| US09705809B2 |
Method and device for adjusting rate of data transmission in Ethernet
A method and device for adjusting rate of data transmission in Ethernet is provided. The method comprises: connection status of a data transmission link in the Ethernet is monitored; and a rate of data transmission in Ethernet is adjusted according to the monitored connection status. By way of monitoring the connection status of the data transmission link in Ethernet and then adjusting the rate of data transmission in Ethernet according to the monitored connection status, the problem in the related art that stability and reliability of data transmission are affected by a data transmission link failure in Ethernet is solved, thus greatly improving stability and reliability of data transmission, and improving user experience. |
| US09705808B2 |
Flow aware buffer management for data center switches
Systems and methods are provided that enable flow aware buffer management. The method includes storing in a queue of a buffer a first type of traffic, storing in the queue of the buffer a second type of traffic, wherein the first type of traffic is less sensitive to latency than the second type of traffic, and when an amount of the first type of traffic meets or exceeds a first threshold, effecting flow control of the first type of traffic to slow a flow of the first type of traffic into the buffer. Flow control can be effected using packet marking or discarding packets. The methodology has particular utility in connection with managing elephant and mouse flows in a network switch. |
| US09705793B2 |
Method for informing a node in a radio access network (RAN) about a type of service associated with an IP packet
A core network node for informing a node in a RAN about a type of service associated with an IP packet to be delivered to the node in the RAN, and a RAN node for delivering a received packet to a terminal are provided. The core network node receives the IP packet from a packet data network, the IP packet having an IP header comprising an original DSCP value, and determines a type of service associated with the packet. The core network node determines a second DSCP value based at least partly on the type of service of the packet, and adds the determined second DSCP value to the header. The core network node forwards the IP packet to the RAN node, to subsequently be delivered to a destination terminal. Thereby the RAN node is able to identify the type of service based on the second DSCP value for further processing of the packet when delivering the IP packet to the destination terminal. |
| US09705791B2 |
Route setting device and route setting method
A route setting device includes: a storage in which routing information is stored; and a processor configured to execute a procedure, the procedure including: selecting a network device among a plurality of network devices forming a network over which a signal including transmission source information and destination information is transmitted, the network device changing at least one of the transmission source information and the destination information included in the signal; categorizing the network device based on a type of the changed information; and generating the routing information according to a result of the categorizing, wherein the route setting device sets the generated routing information to the network device. |
| US09705790B2 |
Information processing apparatus, communication system, and communication method
An information processing apparatus is connected to and communicates with a terminal connected to a first communication network and a second communication network based on a predetermined communication protocol. The first and the second communication network are operable using the predetermined communication protocol. The second communication network is a closed communication network. The information processing apparatus includes first and second communication units. The first communication unit communicates with the terminal via the first communication network based on the predetermined communication protocol. The second communication unit communicates with the terminal based on the predetermined communication protocol via a relay unit arranged in a communication line between the second communication network and the information processing apparatus. The first and the second communication units have the same IP address having an anycast relation as an IP address of the predetermined communication protocol. |
| US09705787B2 |
Technique for ethernet access to packet-based services
An Ethernet Metropolitan Area Network provides connectivity to one or more customer premises to packet-bases services, such as ATM, Frame Relay, or IP while advantageously providing a mechanism for assuring security and regulation of customer traffic. Upon receipt of each customer-generated information frame, an ingress Multi-Service Platform (MSP) “tags” the frame with a customer descriptor that specifically identifies the recipient customer. In practice, the MSP tags each frame by overwriting the Virtual Local Area Network (VLAN) identifier with the routing descriptor. Using the customer descriptor in each frame, a recipient Provider Edge Router (PER) or ATM switch can map the information as appropriate to direct the information to the specific customer. In addition, the customer descriptor may also include Quality of Service (QoS) allowing the recipient Provider Edge Router (PER) or ATM switch to vary the QoS level accordingly. |
| US09705786B2 |
Demand advertisement method for shared mesh protection path computation
A method includes the steps of: (1) generating, by circuitry of a first node, an advertising message including (a) a working path bandwidth demand; (b) an identification of at least two communication links in a shared risk link group of the working path; and (c) at least one protecting path and a bitmap indicative of failure of at least one first communication link in the shared risk link group that causes the at least one protecting path to be used; and (2) transmitting the advertising message from the first node to second nodes within a mesh network. |
| US09705785B2 |
Cloud architecture with state-saving middlebox scaling
An enterprise computer system efficiently adjusts the number of middleboxes associated with the the enterprise, for example, with changes in demand, by transferring not only flows of instructions but also middlebox states associated with those flows. Loss-less transfer preventing the loss of packets and its state, and order-preserving transfer preserving packet ordering may be provided by a two-step transfer process in which packets are buffered during the transfer and are marked to be processed by a receiving middlebox before processing by that middlebox of ongoing packets for the given flow. |
| US09705784B2 |
Bit index explicit replication (BIER)forwarding for network device components
A network device receives multicast packets that include information identifying destinations in the network, identifies next hops associated with the destinations, and populates a cache with the destinations and addresses of the identified next hops. The network device receives a particular multicast packet that includes information identifying particular destinations included in the cache, identifies one or more next hops for the particular destinations from the cache, and forwards the particular multicast packet to the identified one or more next hops to permit the identified one or more next hops to forward the multicast packet toward the particular destinations. |
| US09705783B2 |
Techniques for end-to-end network bandwidth optimization using software defined networking
Techniques for end-to-end network bandwidth optimization using software defined networking are provided. In one embodiment, a computer system can receive information regarding a flow to be admitted to a network, where the flow is associated with a source and a destination. The computer system can further calculate, for each path in a plurality of paths between the source and the destination, a projected utilization of the path in view of the flow. If the projected utilization of the shortest path in the plurality of paths is less than or equal to a target utilization threshold, the computer system can assign the flow to the shortest path. Otherwise, the computer system can select a path in the plurality of paths that comes closest to the target utilization threshold without exceeding the threshold and can assign the flow to that selected path. |
| US09705781B1 |
Multi-topology resource scheduling within a computer network
In general, techniques are described for dynamically scheduling and establishing paths in a multi-layer, multi-topology network to provide dynamic network resource allocation and support packet flow steering along paths prescribed at any layer or combination of layers of the network. In one example, a multi-topology path computation element (PCE) accepts requests from client applications for dedicated paths. The PCE receives topology information from network devices and attempts to identify paths through a layer or combination of layers of the network that can be established at the requested time in view of the specifications requested for the dedicated paths and the anticipated bandwidth/capacity available in the network. The PCE schedules the identified paths through the one or more layers of the network to carry traffic for the requested paths. At the scheduled times, the PCE programs path forwarding information into network nodes to establish the scheduled paths. |
| US09705780B2 |
Non-disruptive integrated network infrastructure testing
Non-disruptive integrated testing of network infrastructure in which one or more processors of a first network interface device (NID) performs tests on a network cable connected to a first NID of a host system, and connected to a second NID. Tests verify connectivity of the cable, a bandwidth capacity baseline, and a maximum bandwidth of the network cable. A self-test determines the host operating system, host status, and operational status of the host NID, and responsive to changed conditions, NID settings are reverted to a pre-validated condition state, and confirmation of reverting is sent to the host. Network activity is suspended if received by the host ID during scheduled network cable tests. Upon completion of tests and storing of test results in NID memory network activity resumes. Results of the tests are transferred from memory of the first NID to persistent storage of the host system. |
| US09705778B2 |
Deploying operators of a streaming application based on physical location attributes of a virtual machine
A streams manager monitors operator performance of a streaming application to determine when the performance of an operator needs to be improved or optimized. The streams manager in conjunction with a cloud manager automatically determines one or more preferred virtual machines in a cloud with a specified streams infrastructure that best meet the needs of the underperforming operator or application component based on physical location attributes of the preferred virtual machines. The cloud manager determines the physical location attributes of the candidate virtual machines. The streams manager or the cloud manager can then determine a preferred virtual machine of the candidates to deploy the operator based on the physical location attributes. The streams manager then modifies the flow graph so one or more operators of the streaming application are deployed to a preferred virtual machine determined according to the physical location attributes of the preferred virtual machine. |
| US09705775B2 |
Passive performance measurement for inline service chaining
A method is implemented by a network device to monitor the performance of packet processing in an in-line service chain, the network device one of a plurality of network devices forming a software defined network (SDN) and the in-line service chain. The SDN includes a controller to configure the plurality of network devices. The method includes receiving a sequence of packets of a data flow traversing the in-line service chain, applying a hash function to the sequence of packets of the data flow to generate a set of hash values for the sequence of packets, and sending the set of hash values and a set of timestamps for the sequence of packets to the controller to determine delay and loss across a service of the in-line service chain. |
| US09705773B2 |
Parallelized network traffic flow availability simulation using stochastic process and traffic engineering algorithms
The present disclosure provides a probabilistic framework that can calculate the probability of fulfilling demands for a given set of traffic flows. In some implementations, the probability of fulfilling demands can be based on the probability of infrastructure component failures, shared risk link groups derived from a cross-layer network topology, and traffic engineering (TE) considerations. The consideration of the cross-layer network topology enables the systems and methods described herein to account for the relationship between the physical and logical topologies. |
| US09705772B2 |
Identification apparatus, identification method and identification program
It is provided an identification apparatus is configured to: obtain, from a first request group, same-type requests which are of the same type as an investigation subject request in a first request group; obtain, other-type requests that have been transmitted from a first apparatus to a second apparatus and a response to which has been transmitted from the second apparatus to the first apparatus, during a processing period; generate, for the investigation subject request and each of the same-type requests; search the generated sets for sets that have the matching other-type requests, and remove one of the found sets; obtain second requests that have been processed by the second apparatus during the processing period from the second request group; calculate, for the investigation subject request and each of the same-type requests after the removal, values of correlation with the obtained second requests. |
| US09705770B2 |
Determining asymmetries in a communication network
A method for measuring asymmetry in propagation delay of first and second links which connect a first node to a second node of a communication network. The method comprises measuring (101) a round trip delay of the first link. The round trip delay can be measured by transmitting (102) a test signal from the first node to the second node over the first link and receiving a reply to the test signal from the second node over the first link. The method further comprises measuring (105) a round trip delay of the second link. The round trip delay can be measured by transmitting (106) a test signal to the second node over the second link and receiving a reply to the test signal from the second node over the second link. A difference in the propagation delay of the first link with respect to the second link is determined (109) using the measured round trip delays of the first link and the second link. |
| US09705767B2 |
Detecting and measuring network route reconvergence using in-band data probes
The present disclosure is directed to systems and methods for detecting and measuring network route reconvergence using in-band data probes. The probes are generated and inserted into the network. The probes are routed to an insertion point, corresponding to a beginning of a measurement line, via an in-band connection such as a virtual private network. The in-band connection is configured such that the time-to-live field of the probes is not affected by network path changes occurring in the in-band connection. The probes are routed through the measurement line to measure network route reconvergence. The measurement line is configured to affect the time-to-live field of the probes to reflect network path changes occurring along the measurement line. The probes are extracted from an extraction point corresponding to an end of the measurement line and routed back to the measurement device for analysis. |
| US09705766B2 |
Distributed liveness reporting in a computer network
In one embodiment, liveness reporting is performed using a distributed approach. The embodiments include a management node that is configured to receive a message containing an indication of activity or inactivity of one or more subject nodes, and determine which of the one or more subject nodes are active based on the received message. The indication is derived from one or more observer nodes observing network traffic of the one or more subject nodes. The embodiments further include one or more observer nodes configured to observe network traffic of the one or more subject nodes in the network, generate the message containing the indication of activity or inactivity of the one or more subject nodes, and transmit the message to the management node. |
| US09705765B2 |
System, method and computer program product for sharing information in a distributed framework
A system, method and computer program product are provided for receiving information associated with a message, issuing a storage resource request in connection with a storage resource and determining whether the storage resource is available. In use, the information is capable of being shared in less than one second, utilizing an automotive electronic control unit which includes a plurality of interfaces. |
| US09705762B2 |
Systems and methods for detecting device identity at a proxy background
A system and method is provided for determining a client device identity. In one implementation, a method is provided that can include receiving a request from a client device. The method can also include determining, based on the client device request, a subscriber identification. After determining the subscriber identification, the method can include acquiring, from a transactional history database, transactional device data associated with the subscriber identification. In some embodiments, the transactional device data can include one or more counts associated with one or more device types. The method can also include determining, based on the transactional device data, the client device identity. In some embodiments, the determination of the client device identity can include selecting a device type of the one or more device types with the maximum count and setting the client device identity to the selected device type. |
| US09705761B2 |
Opinion information display system and method
The present invention discloses a system and a method for presenting network hotspot information and relates to the field of network information technologies. The system comprises: a web page capturing module configured to capture a web page containing network hotspot information on a current network; a web page analyzing module configured to analyze the web page to acquire body information of the web page; a region identification module configured to perform region identification on the body information to acquire a corresponding region which the body information belongs to and perform quantity statistics on the web pages belonging to the same region; and a presenting module configured to present a result of the quantity statistics in a manner of map coloring. The system and the method according to the present invention may objectively and intuitively reflect the network hotspot information in various regions through performing the region identification on the web page containing network hotspot information. |
| US09705759B2 |
Data leakage protection in cloud applications
A computer-implemented method for data leakage protection is disclosed. A monitoring template corresponding to the cloud application is selected based upon communication between a user and a cloud application and from a plurality of monitoring templates. A monitor is generated using the selected monitoring template. Identifying information of content shared between the user and the cloud application is obtained using the generated monitor. Data about the shared content for security analysis is obtained according to the identifying information of the shared content. |
| US09705758B2 |
Management of cloud provider selection
A computer-implemented method, a computer program product, and a system for selecting a host from a plurality of host for an application pattern component using a service level agreement (SLA) requirement are provided. The computer-implemented method for selecting a host from a plurality of hosts for an application pattern component using a service level agreement requirement can include receiving the service level agreement requirement for the application pattern component. The method can include receiving a first capability metric of the host from the plurality of hosts. The method can include determining whether the first capability metric of the host from the plurality of hosts is sufficient for the service level agreement requirement. The method can include selecting the host in response to the host being sufficient for the service level agreement requirement. |
| US09705757B2 |
Method and terminal, input method and device, cloud service card, and system for acquiring service
Embodiments of the present invention disclose a method and terminal, an input method and device, a cloud service card, and a system for acquiring a service and relate to the field of cloud computing technologies. A method for acquiring cloud service content according to an embodiment of the present invention includes: acquiring, by a cloud terminal, an identifier of a service card; acquiring, by the cloud terminal, a cloud service instruction set corresponding to the identifier of the cloud service card from a cloud instruction set server according to the identifier of the cloud service card; and acquiring, by the cloud terminal, cloud service content from a cloud service server according to a cloud service instruction in the cloud service instruction set. The present invention is applicable to quick acquisition of a latest cloud service provided by an operator. |
| US09705756B2 |
Network virtualization
Embodiments of the present disclosure may include methods, systems, and computer readable media with executable instructions. An example method for network virtualization can include providing, by a datacenter (100) having physical and/or virtual resources, a number of virtual tenant datacenters (tDatacenters), each tDatacenter being isolated from other tDatacenters. A tenant virtual local area network (T-VLAN) (226, 228, 682) is associated to each of the number of tDatacenters, and a value of an end-to-end invariant network virtual local area network (VLAN) identification (VID) label (T-VID) is associated to a particular T-VLAN (226, 228, 682). A network packet associated with the particular T-VLAN (226, 228, 682) is modified at an edge network boundary (561) to include the T-VID. The T-VID is configured to have more than 4096 possible values. |
| US09705752B2 |
Reliably updating a messaging system
A messaging system enables client applications to send and receive messages. The messaging system includes independent component programs performing different functions of the messaging system. The component programs include persistent connection managers that maintain connections with the client applications, a dispatcher that establishes connections, and a message router that sends received messages to recipient applications through corresponding connections. The connection managers share a state memory containing a received message and a completion state associated with the received message. The messaging system retains the message until the completion state fulfills a completion condition. The messaging systems supports live deployment of updates the message router and dispatcher because the state of the messaging system is stored independently from memory allocated to these component programs, so they may be restarted without loss of messages, connections or other state information. |
| US09705749B2 |
Executing data stream processing applications in dynamic network environments
In one embodiment, a computer-implemented method includes receiving a network graph describing a network having two or more nodes. An application graph is received describing a data stream application. The application graph includes one or more vertices, each corresponding to an operator of the application and associated with a list of nodes. A first vertex of the application graph corresponds to a first operator and is associated with two or more nodes. The application graph is augmented, which includes replicating the first operator such that the augmented graph includes a copy of the first operator at each of the nodes associated with the first vertex. The application is deployed over the network based on the augmented graph, such that a copy of the first operator is deployed at each of the nodes associated with the first vertex. A route through the augmented graph is selected for a data stream. |
| US09705744B2 |
Updating hardware and software components of cloud computing environment at optimal times
A method, system and computer program product for updating hardware and software components of a cloud computing environment. An administrative server monitors the usage statistics (e.g., compute utilization) of the hardware and software components of the cloud computing environment. Upon receiving user-selected thresholds for the usage statistics, which may be stored in a profile, the administrative server applies a user-provided patch to the hardware or software component whose threshold criteria has been met. Alternatively, the administrative server may automatically update the hardware and software components based on determined minimum usage points (i.e., minimum levels of usage activity) using the monitored usage statistics of the hardware and software components. In this manner, updates to the hardware and software components of the cloud computing environment can occur at optimal times, where the usage activity is low, thereby lessening the negative impact on servicing the user's computing requirements from the update. |
| US09705743B2 |
Method and device for sharing data
The present disclosure relates to a method and a device for sharing data, which relates to the field of communication. The method includes: monitoring an event of a removable storage device being plugged into the DLNA device; acquiring a mount path of the removable storage device through a DLNA server configured in the DLNA device, when the event of the removable storage device being plugged into the DLNA device has occurred; and sharing data in the removable storage device according to the mount path through the DLNA server. |
| US09705740B2 |
Using unified API to program both servers and fabric for forwarding for fine-grained network optimizations
As an overview, the present disclosure presents a system for increasing network optimization. In particular, the disclosure discusses a unified system for control of data routing in a dynamic network. In some implementations, edge devices (i.e., hosts or exterior switches) are interconnected through a network fabric (i.e., a plurality of interior switches). The hosts and switches include forwarding engines, which determine the next destination of incoming traffic. The disclosure discusses a network controller that collects application requirements and programs the forwarding engines of the edge devices and the network fabric responsive to the application requirements. |
| US09705735B2 |
System and method using RSVP hello suppression for graceful restart capable neighbors
A system, method and apparatus adapting one or more routers or nodes in a network to operate in a first mode to exchange hello messages with neighboring nodes to indicate thereby active or live status, and to operate in a second mode to avoid the use of hello messages by opportunistically relying upon service or management protocols to convey active or live status. |
| US09705732B2 |
Method and apparatus for sharing time information in an electronic device
A method for operating an electronic device is provided. The method includes identifying time information of at least one counterpart electronic device, displaying the time information of the counterpart electronic device when an application program for displaying time information is executed, when time change information of the counterpart electronic device is received, changing the time information of the counterpart electronic device according to the time change information, and displaying changed time information of the counterpart electronic device when the application program for displaying time information is executed. |
| US09705731B2 |
Mediation server, communication device, and connecting method
A mediation server for mediating subscription information to a communication device from a network operator providing network connectivity is provided. The server includes a management unit for managing context information of a communication device, which includes data relating to service provided by a network operator; an obtaining unit for obtaining device information of the communication device, which includes data needed to obtain subscription information from a network operator; a selecting unit for selecting, using the context information, a network operator that provides the best service to the communication device out of network operators that are able to provide network connectivity to the communication device; and a request unit for sending a request, with the obtained device information to the selected network operator, for subscription information which is to be used for the communication device to connect to the selected network operator as a home network operator. |
| US09705728B2 |
Methods, systems, and media for media transmission and management
Methods, systems, and media for media transmission and management are provided. In some implementations, a method for media content management is provided, the method comprising: receiving a portion of a media data stream from a first computing device prior to the first computing device processing the portion of the media data stream; processing the portion of the media data stream to identify an object of interest within the media data stream; determining an entity associated with the object of interest; associating a content item with the object of interest based on the determined entity; generating a first representation of the portion of the media data stream, wherein the first representation is associated with the content item; receiving a second representation of the media data stream from a second computing device; determining whether the second representation matches the first representation; and transmitting the content item associated with the first representation to the second computing device for placement within the media data stream in response to determining that the second representation matches the first representation. |
| US09705727B2 |
Remote viewing of media content using layered video encoding
Systems, devices and processes are described to transfer a media program from a media server to a playback device over a network. The media program is encoded in a multi-layer format having a plurality of layers comprising a base layer and at least one additional layer. The base layer supports playback of the entire media program at a lower resolution and each of the additional layers provides additional data that, when combined with the base layer, supports playback of the media program at a higher resolution. The base layer is initially transferred to allow playback of the media program at the lower resolution on the playback device. If sufficient resources remain after transfer of the base layer, then at least one of the additional layers may be subsequently transferred to allow playback of the media program at the higher resolution. |
| US09705725B2 |
OFDM system and method employing OFDM symbols with known or information-containing prefixes
Systems and methods for transmitting and receiving OFDM symbols are provided which enable the otherwise wasted transmission time normally used as a prefix for each OFDM symbol to contain useful information. At the receiver, the received signal is processed to convert received OFDM symbols from a linear convolution with the channel to a cyclic convolution. |
| US09705723B2 |
Apparatus and method for sending and receiving broadcast signals
Disclosed herein is a broadcast signal receiver. The broadcast signal receiver according to an embodiment of the present invention includes a synchronization and demodulation module configured to perform detection and OFDM demodulation on a received broadcast signal, a frame parsing and deinterleaving module configured to parse and deinterleave the signal frame of the broadcast signal, a demapping and decoding module configured to convert the data of at least one Physical Layer Pipe (PLP) of the broadcast signal into a bit domain and to FEC-decode the PLP data, and an output processing module configured to receive the data of the at least one PLP and to output the received data in a data stream form. |
| US09705720B2 |
Pilot symbol patterns for transmission via a plurality of antennas
A method and apparatus for improving channel estimation within an OFDM communication system. Channel estimation in OFDM is usually performed with the aid of pilot symbols. The pilot symbols are typically spaced in time and frequency. The set of frequencies and times at which pilot symbols are inserted is referred to as a pilot pattern. In some cases, the pilot pattern is a diagonal-shaped lattice, either regular or irregular. The method first interpolates in the direction of larger coherence (time or frequency). Using these measurements, the density of pilot symbols in the direction of faster change will be increased thereby improving channel estimation without increasing overhead. As such, the results of the first interpolating step can then be used to assist the interpolation in the dimension of smaller coherence (time or frequency). |
| US09705719B2 |
Method and apparatus for transmitting positioning reference signal in wireless communication system
Provided are a method and an apparatus for transmitting a positioning reference signal (PRS) in a wireless communication system. A terminal obtains positioning subframe configuration information to determine at least one positioning subframe among a plurality of downlink subframes in a wireless frame, obtains downlink subframe configuration information to determine the type of each downlink subframe in the wireless frame, receives PRSs in at least one positioning subframe from a plurality of cells, and reports measured time differences between the PRSs received from the plurality of the cells. The type of each downlink subframe of the wireless frame is classified into a 1st type subframe and a 2nd type subframe, and the type of at least one positioning subframe is either the 1st type subframe or the 2nd type subframe. In addition, the PRSs are mapped into at least one positioning subframe on the basis of a single PRS pattern. |
| US09705712B2 |
Highly linear-gain oscillator
A variable frequency oscillator includes an inductance unit having a first inductance, a first variable capacitor coupled across the inductance unit, and a second variable capacitor coupled across a part of the inductance unit. The inductance of the part of the inductance unit coupled by the second variable capacitor is a proportion of the first inductance. |
| US09705710B2 |
High speed signaling system with adaptive transmit pre-emphasis
A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level. |
| US09705704B2 |
Method and system of forming a mobile virtual network
An approach is provided for creating a mobile virtual network. A virtual network is created to include a plurality of mobile virtual routers. A determination is made whether the virtual network has sufficient resources to satisfy a dynamic virtual network requirement. The size of the virtual network is adjusted based on the determination. |
| US09705703B2 |
System and method for simultaneous communication on Modbus and DNP 3.0 over Ethernet for electronic power meter
A system and method is provided for simultaneous communications on Modbus and DNP 3.0 over Ethernet for an electronic power meter. The system incorporates one or more protocol wrappers to provide compatibility with both Modbus and DNP based applications. The system removes the appropriate wrappers and routes the incoming data packet to its destination. Additionally, the system also wraps outgoing response packets with the appropriate protocol wrapper based on the related data packet wrappers. |
| US09705700B2 |
Sparse graph coding scheduling for deterministic Ethernet
Embodiments provide techniques for transmitting data packets across a deterministic Ethernet network. Embodiments receive, at a first device in the deterministic Ethernet network, a deterministic binary schedule specifying timing information for transmitting data fragments relating to a plurality of data flows. Data packets to transmit to a destination device within the deterministic Ethernet network are received at the first device. Embodiments include fragmenting each of the data packets into two or more fragments and encoding at least one of the two or more fragments for each of the data packets with a respective sparse graph code. The encoded fragments are transmitted to the destination device, across multiple paths through the deterministic Ethernet network, according to timing information specified in the deterministic binary schedule. |
| US09705699B2 |
Method and apparatus for reducing load in can communication
The present disclosure provides a method and an apparatus for reducing a communication load in controller area network (CAN) communication. A method for reducing communication load in a transmission node connected to a CAN communication network may include: generating a first CAN data frame including first data and transmitting the first CAN data frame to the CAN communication network at a first transmission time; comparing second data with the first data at a second transmission time; and transmitting, to the CAN communication network, a second CAN data frame in which a data length code (DLC) field value is set to a predetermined value indicating that the data has not changed, when the second data is identical to the first data. Accordingly, CAN communication load can be effectively reduced without CAN hardware modification. |
| US09705696B2 |
Monitoring system
In a monitoring system, a master device transmits predetermined sound source list data to a mobile phone terminal in response to a first operation on a display/input unit. The mobile phone terminal displays the predetermined sound source list data transmitted from the master device on the display/input unit, and transmits information regarding a selected sound source to the master device in response to an operation of selecting one sound source from the sound source list data. When the information regarding the sound source is received from the mobile phone terminal, the master device outputs selection audio data corresponding to the information regarding the selected sound source from a speaker of a monitoring camera. |
| US09705695B1 |
Sensors and system for accessing and validating sensor data
This invention relates to apparatus and systems for providing home and building security and condition monitoring. More particularly, the invention relates to a plurality of devices, including intelligent, multi-sensing, network-connected devices, that communicate dynamically with each other and a remotes server. |
| US09705692B2 |
Method and device for receiving a multimedia broadcast multicast service in a mobile communication system
The present invention relates to a method and device for receiving a multimedia broadcast multicast service (MBMS) in a mobile communication system. The method for receiving the MBMS of a terminal in the mobile communication system according to an embodiment of the present invention is characterized in that it includes: determining whether service area ID (SAI) information on a serving cell is broadcast during the MBMS; receiving the SAI information on the serving cell when it is determined that the SAI information is broadcast; determining, by using the received SAI information of the serving cell, whether an SAI of the MBMS matches the SAI of the serving cell; and changing the cell reselection priority of the frequency of the serving cell to the highest priority if it is determined that the SAI of the MBMS matches the SAI of the serving cell. |
| US09705687B2 |
Applying user-specified permissions to distribution of content items to social networking system users
A social networking system user identifies one or more social networking system users authorized to present content items to the user via the social networking system (“authorized users”). When an additional user requests presentation of a content item to the user, the social networking system determines if the additional user is an authorized user. If the additional user is an authorized user, the content item is presented to the user. However, if the additional user is not an authorized user, the social networking system identifies the additional user to the user along with a request to identify the additional user as an authorized user. If the user identifies the additional user as an authorized user in response to the request, the content item is presented to the user. |
| US09705682B2 |
Extending DNSSEC trust chains to objects outside the DNS
The present invention generally relates to systems and methods for extending a chain of trust beyond the DNS. Some embodiments provide a verifier with the ability to validate a chain of trust starting with the trust anchor at the DNS root all the way to a service or object of interest outside the DNS. |
| US09705679B2 |
Data authentication device and data authentication method
For improving, when performing road-vehicle communication or vehicle-vehicle communication between a roadside device and in-vehicle devices or therebetween, efficiency of distribution information verification including digital signature verification and freshness verification, there are included a memory unit that stores, as an authentication information history, a history of second authentication information of communication data which was received in the past from another communication device and which includes first authentication information, distribution information, and the second authentication information and an authentication processing unit that verifies, on the basis of the first authentication information of new communication data being newly received communication data, authenticity of the second authentication information of the new communication data and that compares the second authentication information of the new communication data with the authentication information history stored in the memory unit to verify freshness of the new communication data. |
| US09705677B2 |
Method and system for control of code execution on a general purpose computing device and control of code execution in a recursive security protocol
Embodiments of systems and methods which provide highly specific control over the execution of general-purpose code block are disclosed. These embodiments may allow the exact circumstances under which a given code block is allowed to execute to be determined with specificity. Such a control mechanism may be coupled with embodiments of a data hiding system and method, based for example, on an ordered execution of a set of code segments implemented via recursive execution. When embodiments of these systems and methods are utilized together an unencumbered generality as well as a level of protection against attack that surpasses many other security systems may be obtained. |
| US09705674B2 |
Federated key management
A system uses information submitted in connection with a request to determine if and how to process the request. The information may be electronically signed by a requestor using a key such that the system processing the request can verify that the requestor has the key and that the information is authentic. The information may include information that identifies a holder of a key needed for processing the request, where the holder of the key can be the system or another, possibly third party, system. Requests to decrypt data may be processed to ensure that a certain amount of time passes before access to the decrypted data is provided, thereby providing an opportunity to cancel such requests and/or otherwise mitigate potential security breaches. |
| US09705673B2 |
Method, device, and system of provisioning cryptographic data to electronic devices
System, device, and method of provisioning cryptographic assets to electronic devices. A delegation message is generated at a first provisioning server. The delegation message indicates provisioning rights that are delegated by the first provisioning server to a second provisioning server with regard to subsequent provisioning of cryptographic assets to an electronic device. The delegation message includes an association key unknown to the first provisioning server, encrypted using a public key of the electronic device. The delegation message further includes a public key of the second provisioning server. The electronic device locally generates the association key, which is unknown to the first provisioning server. The delegation message is delivered to the electronic device. Based on the delegation message, cryptographic assets are provisioned by the second provisioning server to the electronic device, using the association key. |
| US09705672B2 |
Key management method and system
Disclosed are a key management method and system. A master key is remotely downloaded to avoid the problem that the master key is not issued to a merchant until the master key needs be downloaded on a POS terminal, so as to reduce logistics costs and maintenance costs. When a key is remotely downloaded, a KMS system uses a symmetric algorithm to encrypt the key to be transmitted to ensure that the encrypted key can only be decrypted by a corresponding POS terminal, thereby ensuring the security of data transmission. During bidirectional authentication, an application program of the POS terminal can only contact an encrypted text form of the key instead of a plain text key needing to be remotely downloaded to the POS terminal, thereby ensuring security in reproduction. |
| US09705668B2 |
Dual path timing jitter removal
A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator. |
| US09705667B2 |
Tracking of signals with at least one subcarrier
A system for tracking a received signal with a subcarrier, the received signal representing a carrier signal modulated with a code signal and with a subcarrier signal. The system comprises independent and cooperatively operating loops: a phase lock loop tracking the carrier signal, a subcarrier lock loop tracking the subcarrier signal, and a delay lock loop tracking the code signal. The subcarrier lock loop comprises a first controllable oscillator and a first early-minus-late discriminator generating a control signal for the first controllable oscillator. The delay lock loop comprising a second controllable oscillator and a second arctan discriminator generating a control signal for the second controllable oscillator. |
| US09705665B2 |
Oversampling CDR which compensates frequency difference without elasticity buffer
A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter. |
| US09705658B2 |
Method and apparatus for detecting inconsistent control information in wireless communication systems
In order to support low latency and bursty internet data traffic, the 3GPP LTE wireless communication system uses dynamic allocation. To keep the allocation overhead lower, the system is designed such that the client terminal must perform a number of decoding attempts to detect resource allocations. During course of the decoding attempts a false resource allocation may be decoded by the client terminal. The false detection may lead to multiple issues for the performance efficiency of the client terminal and the overall communication system. A method and apparatus are disclosed than enable the detection of false resource allocation. This in turn improves the performance and efficiency of the client terminal and the wireless communication system. |
| US09705657B2 |
Method and apparatus for scheduling in wireless communication system for coordinated scheduling
A method and apparatus for scheduling in a wireless communication system configured for coordinated scheduling are disclosed.The scheduling apparatus sets a gain to be obtained when a terminal performs coordinated scheduling in a neighboring cell. The scheduling apparatus determines whether the terminal in the neighboring cell has moved between a first region where coordinated scheduling is not performed and a second region where coordinated scheduling is performed. Next, if it is determined that the terminal in the neighboring cell has moved between the first region where coordinated scheduling is not performed and the second region where coordinated scheduling is performed, the scheduling apparatus controls the radio unit in the neighboring cell to set an Modulation and Coding Scheme (MCS) level based on the gain and perform scheduling based on the MCS level. |
| US09705654B2 |
Methods and apparatus for an extensible and scalable control channel for wireless networks
Methods and apparatus to enable an extensible and scalable control channel for wireless networks. In one embodiment, an Enhanced Physical Downlink Control Channel (ePDCCH) is disclosed that is implemented with a flexible number of Physical Resource Blocks (PRBs). Advantages of the ePDCCH include, for example: more efficient spectral utilization, better frequency management across multiple serving entities (e.g., base stations and remote radio heads), and extensible payload capabilities that can scale to accommodate higher or lower control information payloads, as compared to prior art PDCCH solutions. |
| US09705653B2 |
Downlink control transmission in multicarrier operation
A wireless communication network distributes resources for a Physical Downlink Control CHannel (PDCCH) over multiple carriers in accordance with a constraint that limits a number of blind decoding actions required by user equipment (UE). Distribution can entail segregating UE-specific and common search spaces to different monitored carriers. Distribution can entail segregating aggregation levels to different monitored carriers. Distribution can entail segregating a number of decoding candidates for a given aggregation level to different monitored carriers. The distribution can be orthogonal or non-orthogonal, and can be UE-based or per cell-based. The distribution can be static, semi-static or hop with time. |
| US09705647B2 |
Inter-UE interference cancellation
Interference cancellation occurs for devices, where the source of the interference is another UE. The victim UE receiver identifies subframes vulnerable to potential interference from other UEs. Candidate resource blocks in the identified vulnerable subframes are listed. Interference is cancelled for edge resource blocks and valid contiguous resource blocks. |
| US09705643B2 |
High-efficiency wireless local-area network devices and methods for acknowledgements during scheduled transmission opportunities
Embodiments of a system and method for acknowledging frames in a wireless network are generally described herein. In some embodiments, a wireless communication device may include a transmit/receive unit configured to receive data from a sender. In some embodiments, the transmit/receive unit may be configured to receive a schedule. The transmit/receive unit may be further configured to acknowledge (ACK) the data in a first scheduled transmission to the sender. The first scheduled transmission to the sender may be determined based on the schedule. In some embodiments, the acknowledgement may be an acknowledgement frame or a block acknowledgment frame. The scheduled transmission to the sender may be determined based on the schedule. |
| US09705634B2 |
Communication users predictive product
The system of the present invention allows a user to select one or multiple SATCOM radio and antenna equipment types, select their current location(s) or a route and select the UHF SATCOM satellite for a multi-user communication network or architecture. The system presents an assessment of the level of performance of the selected system equipment and provides a capability to assess the impact of degrading factors, such as man-made interference (jamming) and natural phenomena (e.g. rain, clouds, ionospheric scintillation). This predictive assessment is a tailored result showing the phenomenology effects. Natural phenomenology like ionospheric scintillation, clouds, and precipitation, plus man-made phenomenologies like SATCOM jammers need to be differentiated by behavior characteristics and performance on a SATCOM frequency. If the system assessment determines the communication link is weak or ineffective based off the user's inputs, the application provides the ability to select alternative configurations, e.g. other radio and antenna equipment pairing and/or other satellite options or access times. The system of the present invention can be updated and modified as the satellite communication community and users identify new equipment and additional ionospheric scintillation data resources. Using satellite communication equipment (radio, antenna and satellite specifications) databases and near-real time external data, if available, allows the system of the present invention to generate an assessment tool that shows the quality of the communication overarching architecture. |
| US09705630B2 |
Optical interconnection methods and systems exploiting mode multiplexing
Optical solutions to address and overcome the issues of superseding/replacing electrical interconnection networks have generally exploited some form of optical space switching. Such optical space switching architectures required multiple switching elements, leading to increased power consumption and footprint issues. Accordingly, it would be beneficial for new optical, e.g. fiber optic or integrated optical, interconnection architectures to address the traditional hierarchal time-division multiplexed (TDM) space based routing and interconnection to provide reduced latency, increased flexibility, lower cost, and lower power consumption. Accordingly, it would be beneficial to exploit networks operating in multiple domains by overlaying mode division multiplexing to provide increased throughput in bus, point-to-point networks, and multi-cast networks, for example, discretely or in combination with wavelength division multiplexing. |
| US09705629B2 |
Transmitting device and transmission control method
A transmitting device coupled to a first route and a second route as communication paths on a first ring network and coupled to a third route as a communication path on a second ring network, the transmitting device includes: a first branching unit configured to branch and output signal light input from the first route to a first terminating unit and a second output unit that outputs signal light to the second route; a second branching unit configured to branch and output signal light input from the second route to a second terminating unit, a first output unit that outputs signal light to the first route, and a third output unit that outputs signal light to the third route; and a third branching unit configured to branch and output signal light input from the third route to a third terminating unit that terminates signal light and the second output unit. |
| US09705626B2 |
Optical system, and dynamic wavelength bandwidth allocation method for optical system
An ONU requests a bandwidth of an uplink signal, and in accordance with this, an OLT calculates a time when the OLT transmits the uplink signal and a transmission duration time and performs an instruction, and a DBA cycle in which the ONU transmits the uplink signal in accordance with the instruction and a dynamic wavelength allocation cycle in which the OLT instructs wavelength switching, and the ONU switches the wavelength and belongs to a different LC are separated. While the ONU switches the wavelength, the DBA cycles can be performed plural times in the ONU whose wavelength is not switched, the switching of the wavelength is confirmed after the wavelength has been switched, and then DBA operation is performed at the switched wavelength. |
| US09705621B2 |
Radio telecommunications system and method of operating the same with polling
An apparatus or method for transmitting data blocks on a communications channel having a radio link between two stations including a user equipment comprises receiving first data blocks from the user equipment, and transmitting second data blocks to the user equipment. A polling interval is dynamically set for the transmission of polling messages to the user equipment after transmission of the second data blocks, the polling interval being set in accordance with at least one of: a size of one or more data blocks received by the apparatus from the user equipment, a size of one or more blocks transmitted from the apparatus to the user equipment, and a service to which the user equipment is subscribed. The apparatus may be used as a PCU in a cellular mobile telephone system. |
| US09705620B2 |
Synchronization of endpoints using tunable latency
A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin. |
| US09705619B2 |
Apparatus and method for synchronous hardware time stamping
Methods and apparatus that may be used to provide timestamps to physical layer devices are provided. One method includes obtaining a time value from a clock associated with a physical layer device that is communicatively coupled to a primary data packet switch. The method further includes adding a processing time to the time value to generate a timestamp and transmitting the timestamp to a multiplexer circuit. The method further includes writing the timestamp in parallel from the multiplexer circuit to a plurality of external physical layer devices that are communicatively coupled to a secondary data packet switch and are located external to a housing of the secondary data packet switch. |
| US09705618B1 |
Systems, methods and devices for public announcements
A public addressing system can identify user preferences including language, volume, and method of delivery to provide improved content in a given geographical area using perceptual computing techniques. The system can also support the use of personal devices including wearables in order to deliver private personalized messages discreetly. For example, one embodiment of a public announcement system gathers and aggregates demographic data of a population in a public place. The public announcement system creates inferences from this data to predict content delivery preferences, such as a sequence of languages or delivery characteristics (e.g., speech rate, content and volume). The delivery preferences can be ranked and then a recommendation for a public announcement provided. |
| US09705614B2 |
Testing a communications apparatus
A test arrangement includes a multi-port test interface having a first waveguide coupled to a plurality of second waveguides. The first waveguide is arranged to propagate an input signal and each of the second waveguides is arranged to output the input signal, providing a plurality of test signals to be supplied to a communications apparatus. Such a test interface may also be used to output respective channel signals in a multiplexed signal received from a communications apparatus. The test interface permits the provision and/or monitoring of a large number of channel signals without separate respective connections to the communications apparatus. This may be particularly useful where tests are performed in a constrained space and/or where repeated access to the apparatus is impractical. The simultaneous provision of many channel signals may allow evaluation of co-channel interference. |
| US09705610B2 |
Transmission device with impairment compensation and methods for use therewith
Aspects of the subject disclosure may include, for example, a waveguide system that includes a transmission device having a coupler positioned with respect to a transmission medium to facilitate transmission or reception of electromagnetic waves that transport communications data. The electromagnetic waves propagate along an outer surface of the transmission medium. A training controller detects an impairment on the transmission medium adverse to the transmission or reception of the electromagnetic waves and adjusts the electromagnetic waves to reduce the effects of the impairment on the transmission medium. Other embodiments are disclosed. |
| US09705608B2 |
Method and system for interference cancellation of data channel
The disclosure discloses a method for interference cancellation of a data channel. The method includes that: bit-level channel recoding is performed on received transport block data, and then channel estimation is performed on the coded data and multiplexed antenna data of a data channel to obtain channel estimation data; data channel reconstruction is performed on the coded data with a Reconstruction Unit (RU) as a unit by virtue of the channel estimation data; and obtained reconstruction data is subtracted from the antenna data to implement interference cancellation. The disclosure further discloses a system for interference cancellation of a data channel. |
| US09705607B2 |
System and methods of acoustic monitoring
A high performance computing strategy along with the capability to integrate various layers of data within a modeling framework incorporates various tools such as ambient noise, vessel and animal data to measure acute and chronic noise levels, detect and classify marine mammal vocalizations, and compute various metrics such as receive levels, signal excess, masking and communication space over relatively large temporal and spatial scales. |
| US09705606B2 |
Directional light transmitter and receiver
A system for supplying power wirelessly to a remote mobile device including (i) a transmitting unit for directing radiation into the region of the mobile device, the transmitting unit having a gain medium with a front surface directed towards the space, and a retroreflector on its back surface, and (ii) a receiver unit connected with or attached to the mobile device for receiving radiation transmitted from the transmitting unit. The receiver unit includes (i) a retroreflector for reflecting part of the radiation received from the transmitting unit back in the direction of the transmitting unit, where it is amplified and retransmitted back in the direction of the receiver unit, and (ii) a power detection element for absorbing that part of the radiation not reflected by the retroreflector, and converting it to electrical power for use by the mobile device. Modulation of the transmitted beam enables it to transmit data also. |
| US09705598B2 |
Methods and systems for reducing optical beat interference via polarization diversity in FTTx networks
Methods of reducing optical beat interference in a fiber optic network are provided. The optical fiber network may have a plurality of optical network units that communicate with a shared receiver. The optical signals that are transmitted from the optical network units to the receiver may have polarization states that are selected to reduce optical beat interference at the receiver. |
| US09705597B2 |
Modular light bar messaging system
Techniques for communicating lighting commands through a controller area network (CAN) bus of a light bar system include generating a light code message. The light code message has a metadata portion and a value portion. The metadata portion defines a purpose of value portion. The value portion controls a state of a lighting device (e.g., a keypad's LED brightness or activation of a directional light module) in the light bar system. A data field is generated by encapsulating the light code message with an ISO-TP single frame header and a message subtype. A CAN controller generates a CAN message having an extended frame format and the data field. The CAN message is then transmitted through the CAN bus. |
| US09705594B2 |
Optical communication for solid-state light sources
The disclosure relates to a lighting fixture, which includes an array of solid-state light sources that are configured to generate light for general illumination lighting purposes and control circuitry. A drive signal is used to drive solid-state light sources. The control circuitry is configured to use a control output to control the drive signal to at least one of the solid-state light sources. The control output is configured to control the drive signal to 1) set at least one characteristic of the light generated by the array of the solid-state light sources, and 2) modulate the light with data for transmission. The light is modulated such that any change in the at least one characteristic based on the light being modulated is anthropically imperceptible. The characteristic of the light generated by the array of solid-state light sources may include the intensity, color, color temperature and the like. |
| US09705585B2 |
Relaying device and communication system
A relaying device includes an uplink interface that continuously receives an audio signal in communication, a wireless apparatus interface to which a repeater acting as a wireless relaying apparatus is connected, a voice buffer that buffers the audio signal, and a control unit. The control unit performs a VOX processing of detecting whether or not a level of the audio signal is equal to or higher than a preset threshold. When the level of the audio signal is equal to or higher than the threshold, the control unit starts buffering the audio signal in the voice buffer, and requests the repeater to reserve a channel. After receiving, from the repeater, a reply indicating that a channel has been reserved, the control unit reads the buffered audio signal from the voice buffer, and transfers this audio signal to the repeater. |
| US09705583B2 |
Communication device and method of controlling same
A communication device and a method of controlling the same. The communication device includes at least one receiver configured to connect to a first antenna for receiving a first signal and a second antenna for receiving a second signal; and a processor electrically coupled to the at least one receiver, wherein the processor is configured to measure received signal strengths of the first signal and the second signal based on calibration operation for the first antenna and the second antenna, select one of the first antenna and the second antenna based on the measured received signal strengths, and control the at least one receiver to receive a signal through the selected one of the first antenna and the second antenna. |
| US09705581B2 |
Synchronization in a beamforming system
A beamforming system synchronization architecture is proposed to allow a receiving device to synchronize to a transmitting device in time, frequency, and spatial domain in the most challenging situation with very high pathloss. A detector at the receiving device detects the presence of control beams, synchronizes to the transmission and estimates the channel response by receiving pilot signals. The detector has low complexity when exploiting the structure of the pilot signals. The detector consists of three stages that break down the synchronization procedure into less complicated steps. The detector accurately estimates the parameters required for identifying the transmit device and performing subsequent data communication. |
| US09705573B2 |
Controlling multiple-input and multiple-output operation of a communication device when the device is attached to a battery charger
A method for controlling multiple-input and multiple-output operation in a communication device when the communication device is attached to a battery charger includes determining that a battery level of a communication device is below a first battery level threshold. The method further includes determining that the communication device is attached to a battery char and determining whether to disable multiple-input and multiple-output operation of the communication device while it is attached to the battery charger. |
| US09705572B2 |
Communication control method and base station
A communication control method used in a mobile communication system in which a plurality of cells managed by different eNBs 200 cooperate with one another to perform communication with one UE 100. The communication method comprises the steps of: in a eNB 200-1 that manages a cell #1, receiving a BCI fed back from each of a plurality of UEs 100-1 connected with the cell #1; generating, on the basis of the received BCI, mapping information that includes a plurality of BCIs with which a frequency resource is associated respectively; and transmitting the mapping information to a eNB 200-2 that manages a cell #2. |
| US09705568B2 |
Method and plug-in connection for informing a process control center about a sensor being disconnected from a measuring transducer
A method for informing a process control center about the fact that a sensor is being disconnected from a measuring transducer that is arranged spatially remote from the process control center and electrically connected with the process control center. The sensor is connected with the measuring transducer via a plug-in connection. A method involving automatic transmission of a signal to the process control center when the plug-in connection is opened is designed in such a way that, when opening a bayonet joint that covers the plug-in connection, or when disconnecting the plug-in connection, in order to disconnect the sensor from the measuring transducer, an electric signal is generated in the plug-in connection or the bayonet joint, which is transmitted to the process control center. |
| US09705567B2 |
Distributed data storage system and method
A system for storing long-term digital data comprises data storage equipment including one or more data storage devices 26 stored in a sealed data storage module 10, which is positioned within a data center enclosure 101, which contains a body 12 that is surrounded by a strengthening shield 14. The body contains a network of tunnels 16. One or more data storage modules 10 are stored in a tunnel 16 that is inaccessible to human beings and comprises robotic movement means. Data can be stored before or after the data storage device 26 is sealed within the data storage module body. A utility distribution system can be positioned in proximity to the data storage module 10 for the utility distribution module to provide contactless power and network connection to the data storage module and for the data storage module to retrieve and transmit to the utility distribution module 34 data that is held in the data storage device 26. Powering of the data storage module occurs only when access to the data storage devices is required. One the other or both of the data storage module 10 and the tunnel 16 is operable to self-destruct when tampering is detected. The data storage module can also process the data stored under user instruction and store the results, including secure encryption and decryption of data. |
| US09705560B1 |
Discrete fourier transform using GNSS tracking channel
A method of performing a discrete Fourier transform (DFT) on one or more data samples in a global navigation satellite system baseband tracking channel is provided. The method comprises loading a pseudorandom noise code generator with a constant value in the baseband tracking channel; setting a tracking loop integration time according to a selected frequency resolution; updating a carrier generator with a selected DFT frequency in the baseband tracking channel; integrating a data sample in the baseband tracking channel; and storing the integrated data sample in a DFT bin. The method determines whether all DFT bins have been received, and if all DFT bins have not been received, the method repeats starting with updating the carrier generator, until all DFT bins have been received. |
| US09705559B2 |
Method and apparatus for powering a portable device
A method of monitoring a process of powering a portable device through a cable connected between a power supply and a portable device is presented. The method includes applying a time-dependent current variation to one end of the cable in accordance with a spreading sequence, detecting a time-dependent voltage variation at the one end of the cable, the time dependent voltage variation resulting from the applying of the time-dependent current variation, and determining a quantity indicative of an impedance of the cable assembly based on the time-dependent voltage variation and the spreading sequence. Further, an apparatus for monitoring a process of powering a portable device through a cable connected between a power supply and a portable device is presented. |
| US09705558B2 |
Harmonic rejected antenna switch
The exemplary embodiments include a radio frequency antenna switch configured to reject harmonic frequencies. In addition, the harmonic-rejected radio frequencies of the radio frequency antenna switch may be tuned by use of a capacitor array. The capacitor array may be configured with fuse elements or by control logic. |
| US09705557B2 |
Front end circuit, module, and communication device
A front end circuit includes: a first antenna terminal from/to which transmission/reception signals of a low band (LB) and a high band (HB); a second antenna terminal from/to which a transmission/reception signal of a middle band (MB) is output/input; an LB terminal to/from which the transmission/reception signal of the LB is input/output, an MB terminal to/from which the transmission/reception signal of the MB is input/output; an HB terminal to/from which the transmission/reception signal of the HB is input/output; and a separating circuit that passes the transmission and reception signals of the LB and suppresses the transmission and reception signals of the MB and the HB between the first antenna terminal and the LB terminal, and that passes the transmission and reception signals of the HB and suppresses the transmission and reception signals of the LB and the MB between the first antenna terminal and the HB terminal. |
| US09705554B2 |
Circuits, devices and methods for achieving fast changes in voltage regulator outputs
Circuits, devices and methods for achieving fast changes in voltage regulator outputs. In some embodiments, a voltage regulation system can include a voltage regulator configured to receive an input voltage Vin and generate an output voltage Vout at an output node, and to transition Vout between V1 and V2. The voltage regulation system can further include a transition circuit coupled to the output node. The transition circuit can include a first voltage source that is switchably coupled to the output node and configured to provide a voltage associated with one of the V1 and V2 voltages to the output node during at least the transition of the voltage regulator. The voltage provided by the first voltage source can be substantially equal to one of the V1 and V2 voltages. |
| US09705552B1 |
Smart phone or tablet computer case with finger-engaging slots
The smart phone or tablet computer case with finger-engaging slots is a glorified smart phone case that includes a pivoting armature on a rear surface. The pivoting armature rotates from a flattened positioned with the rear surface of the case to a perpendicular orientation. The pivoting armature features a pair of finger holes that are each adapted to receive a finger therein. The pivoting armature is adapted to be secured to the hand via the pair of finger holes in order to prevent dropping of the case. |
| US09705548B2 |
Wristband-type handset and wristband-type alerting device
Proposed is a bracelet-type transmission/reception device comprising: a cartilage conduction vibration source provided in a portion to be attached to a wrist; a speaker; a variable directional microphone; and a control unit which sets the directivity of the variable directional microphone to the back side of a hand when the speaker is used and sets the directivity of the variable directional microphone to the palm side of the hand when the cartilage conduction vibration source is used. The bracelet-type transmission/reception device is provided together with a display means for information relating to a transmission/reception method or a handling explanation medium or advertising medium having the information relating to the transmission/reception method. An example of a method for use thereof is to conduct the vibration of the cartilage conduction vibration source to a thumb and to bring the thumb into contact with a tragus in a state where the back of the hand faces forward. The cartilage conduction vibration source is also used as a vibration source of an incoming vibrator, and when the cartilage conduction vibration source vibrates for cartilage conduction, a vibrational component in a low-frequency range that induces a sense of vibration is cut. The cartilage conduction vibration source vibrates for notification by announcement voice data in a storage unit. |
| US09705547B2 |
Ad-hoc wireless communication network including wearable input/output transducers
One or more sensors gather data, one or more processors analyze the data, and one or more indicators notify a user if the data represent an event that requires a response. One or more of the sensors and/or the indicators is a wearable device for wireless communication. Optionally, other components may be vehicle-mounted or deployed on-site. The components form an ad-hoc network enabling users to keep track of each other in challenging environments where traditional communication may be impossible, unreliable, or inadvisable. The sensors, processors, and indicators may be linked and activated manually or they may be linked and activated automatically when they come within a threshold proximity or when a user does a triggering action, such as exiting a vehicle. The processors distinguish extremely urgent events requiring an immediate response from less-urgent events that can wait longer for response, routing and timing the responses accordingly. |
| US09705545B2 |
Tunable radio frequency low noise amplifier
An apparatus comprising an amplifier comprising an input, a capacitor having a capacitor first side and a capacitor second side, wherein the capacitor first side is coupled to the input, a switch having a switch first side and a switch second side, wherein the switch first side is coupled to the capacitor second side, and a transistor having a transistor gate, and a transistor source, wherein the transistor gate is coupled to the input and the capacitor first side, wherein the transistor source is coupled to the switch second side and wherein the switch is positioned directly between the capacitor second side and the transistor source. |
| US09705544B2 |
Wireless receiver and method
A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analog-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols. |
| US09705543B2 |
Communication system, frequency control method, remote terminal and non-transitory computer-readable recording medium having stored therein program
A wireless-device-end communicator transmits, to a remote-end communicator, an IF signal and a wireless-device-end AF signal, the wireless-device-end AF signal being generated by demodulating the IF signal on a basis of a wireless-device-end local frequency. A remote-end controller starts a tuning mode when an instruction obtainer obtains the start instruction for the tuning mode, and adjusts a remote-end local frequency in accordance with the obtained adjustment instruction. A remote end demodulator demodulates the received IF signal on a basis of the remote-end local frequency, and outputs a remote-end AF signal. An outputter outputs the remote-end AF signal in the tuning mode, and outputs the wireless-device-end AF signal in a normal mode. At an end of the tuning mode, the wireless-device-end local frequency is adjusted in such a way that the reception frequency of a wireless device becomes consistent with the reception frequency indicated by the last adjustment instruction. |
| US09705542B2 |
Reconfigurable RF filter
A reconfigurable RF filter, which includes a first resonator, a second resonator, and a first coupling circuit, is disclosed. The first coupling circuit is coupled between the first resonator and the second resonator. The reconfigurable RF filter operates in one of a group of operating modes, which include a first operating mode and a second operating mode. During the first operating mode, the reconfigurable RF filter is a bandpass filter having a first bandwidth and a first insertion loss via the first resonator. During the second operating mode, the reconfigurable RF filter is a bandpass filter having a second bandwidth and a second insertion loss via the first resonator, such that the first bandwidth is greater than the second bandwidth and the first insertion loss is less than the second insertion loss. |
| US09705539B2 |
Digital pre-distortion of non-linear systems with reduced bandwidth feedback
Embodiments of the invention provide a DPD system where the transmit reference signal is transformed, including sub-sampling, frequency translation, and the like, to match the feedback signal, which goes thru a similar transformation process, to obtain an error signal. The same transformation is applied to a system model, which may be Jacobian, Hessian, Gradient, or the like, in an adaptation algorithm to minimize error. |
| US09705534B2 |
Electronic device using antenna
An electronic device is provided, which includes an antenna; and a communication processor configured to transmit and receive a first signal corresponding to a first frequency band through the antenna, and to perform one of transmitting and receiving a second signal corresponding to a second frequency band through the antenna. |
| US09705529B2 |
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. |
| US09705526B1 |
Entropy encoding and decoding of media applications
Symbols above a particular number are encoded with Rice encoding. Symbols of the predetermined number or less are encoded with a different technique. The encoded symbols are decoded by determining if the symbols are above the particular number and then applying the corresponding decoding technique. |
| US09705524B2 |
R2R digital-to-analog converter circuit
One example includes an R2R digital-to-analog converter (DAC) circuit. The circuit includes at least one scaling circuit configured to apply a scale-factor with respect to a nominal voltage range defined by a low-voltage rail and a reference voltage to define a scaled voltage range. The scale-factor can be positive and less than one. The circuit also includes an R2R ladder circuit configured to generate an analog ladder voltage corresponding to a digital input signal. The analog ladder voltage can have an amplitude in the scaled voltage range. The circuit further includes an output stage configured to apply an inverse of the scale-factor to the analog ladder voltage to generate an output voltage. |
| US09705522B1 |
High speed low power digital to analog upconverter
Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits. |
| US09705521B1 |
Noise shaping signed digital-to-analog converter
A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop. |
| US09705519B1 |
Correction technique for analog pulse processing time encoder
A circuit for correcting time encoder errors including a time encoder having a time encoder input, a time encoder output, and a current summing point, and a pulse width modifier coupled to the time encoder output, the pulse width modifier having a current output coupled to the current summing point, and having a corrected output. The pulse width modifier is configured to calibrate duty cycle errors and nonlinearity errors on the time encoder output, to correct the duty cycle errors and the nonlinearity errors on the time encoder output, and to output the corrected output. |
| US09705516B1 |
Reconfigurable phase-locked loop with optional LC oscillator capability
A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and delay generator is configured as the delay line circuit. |
| US09705514B2 |
Hybrid analog and digital control of oscillator frequency
A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action. |
| US09705512B1 |
Self-calibrating fractional-N phase lock loop and method thereof
A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise and an output of the timing detection circuit. |
| US09705505B2 |
Reconfigurable semiconductor device
There is provided a reconfigurable semiconductor device including a plurality of logic units connected to each other using an address line or a data line, each logic unit including a plurality of address lines, a plurality of data lines, a clock signal line configured to receive a system clock signal, a delay element configured to delay the system clock signal, a memory cell unit configured to operate in synchronization with a clock signal, and an address decoder configured to decode an address signal to output the decoded signal to the memory cell unit. The logic unit configuring a combination logic circuit operates in synchronization with a delayed clock signal outputted from the delay element. |
| US09705496B2 |
Switch device
A switch device may include a non-conductive operating portion provided with a plurality of operating areas inside an outer edge part of the operating portion, an electrode sheet spaced from the operating portion and having a plurality of electrodes each including at least one detection electrode and being arranged to face a respective operating area, and a detecting unit that may detect operations of the plurality of operating areas. An inner part of the operating portion positioned inward of the outer edge part may be displaceable in a facing direction of the operating areas and the electrodes. The detecting unit may be configured to determine an operated operating area, which may be operable by touch or push operation, based upon a position of at least one of the detection electrodes, a change in capacitance of the detection electrode, and a changing amount in capacitance of the detection electrode. |
| US09705495B2 |
Asymmetric sensor pattern
An embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace that intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to a corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. The capacitive sensor array may further comprise a plurality of open zones, where each of the plurality of open zones is staggered relative to an adjacent open zone. |
| US09705492B2 |
Switch circuit and SPDT switch circuit
The present invention relates to a switch circuit and a single pole double throw (SPDT) circuit. The switch circuit includes: a MOS transistor transferring or blocking a signal according to a turn on/off operation thereof; a gate resistor connected to a gate of the MOS transistor; and a variable gate resistor circuit increasing a resistance value of the gate resistor when the MOS transistor is changed from a turn-off state to a turn-on state. |
| US09705489B2 |
Cascode transistor circuit
A cascode transistor circuit comprising a depletion-mode switch in series with a normally-off switch between a drain output terminal and a source output terminal. The circuit also includes a controller comprising a controller output terminal configured to provide a normally-on control signal for a normally-on control terminal of the depletion-mode switch, wherein the normally-on control signal is independent of the normally-off control signal; a negative voltage source configured to provide a negative voltage to the normally-on control terminal of the depletion-mode switch; and a feedback capacitance between the drain output terminal and a control node in a circuit path between the controller output terminal and the normally-on control terminal of the depletion-mode switch. |
| US09705476B2 |
Optimal factoring of FIR filters
A method and system for the design and implementation of an optimally factored filter is presented. Pairs of angle values are organized in pairing candidates and a threshold is defined to indicate an upper bound on the number of pairing candidates. A first pairing candidate is exchanged above the threshold with a second pairing candidate below the threshold and a matrix is generated based on the pairing candidates below the threshold. A lowest predicted total quantization cost between all pairing candidates represented within the matrix is determined and the pairing candidates that result in the lowest predicted total quantization cost are used to determine the coefficients of the filter. |
| US09705473B2 |
Resonant circuit with variable frequency and impedance
A resonant circuit comprises an input terminal and an output terminal and at least: a group of N resonators, where N≧1, the resonators having the same resonance frequency and the same antiresonance frequency; a first and a second impedance matching element having a non-zero reactance, the first element being in series with the group of resonators, and the second element being in parallel with the group of resonators, the resonant circuit comprising: first means for controlling the group of resonators, enabling the static capacitance of the group to be fixed at a first value; second control means, enabling the impedance of the first impedance matching element and that of the second element to be fixed at second values; the first and second values being such that the triplet of values composed of the static capacitance of the group, the impedance of the first element, and the impedance of the second element can be used to determine the following triplet of parameters: the characteristic impedance Zc of the assembly formed by the group, the first impedance matching element and the second matching element; the resonance frequency ωr of the assembly; the antiresonance frequency ωa of the assembly, in order to stabilize the impedance of the circuit at a chosen characteristic impedance. |
| US09705467B2 |
Sub-network enhanced reflectionless filter topology
Reflectionless low-pass, high-pass, band-pass, band-stop, all-pass, and all-stop filters, as well as a method for designing such filters is disclosed, along with a method of enhancing the performance of such filters through the use of sub-networks to further modify and improve the frequency response. These filters preferably function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications. The sub-networks preferably offer additional degrees of freedom by which the leakage through the parent filter may be cancelled or reinforced to alter cutoff sharpness, stop-rejection, or other measures of performance. |
| US09705466B2 |
Semiconductor device with guard ring coupled resonant circuit
A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit. The semiconductor device further comprises a resonant circuit coupled with the guard ring. The resonant circuit comprises an input node coupled with the guard ring. The resonant circuit also comprises an inductor. The resonant circuit further comprises a capacitor coupled with the inductor. The resonant circuit additionally comprises a ground node configured to carry a ground voltage. The inductor and the capacitor are coupled between the input node and the ground node. |
| US09705465B2 |
Closed loop control system, and an amplifier in combination with such a closed loop control system
A control apparatus is provided that can provide high dynamic resolution and is suitable for inclusion within an integrated circuit. The control apparatus receives a demand signal representing a desired value of a measurand, and a feedback signal representing a present value or a recently acquired value of the measurand. The processing circuit forms a further signal a further signal which is a function of the demand and feedback signals. The further signal is then subjected to at least an integrating function. The demand signal, feedback signal or the further signal is processed or acquired in a sampled manner. The use of such sampled, i.e. discontinuous, processing allows integration time constants to be synthesized which would otherwise require the use of unfeasibly large components within an integrated circuit, or the use of off-chop components. Both of these other options are expensive. |
| US09705464B2 |
Audio signal processing circuit
An audio signal processing circuit includes a first obtaining unit, a regulation unit, a second obtaining unit, and a synthesis unit. The first obtaining unit obtains high-frequency audio signals from original audio signals. The regulation unit obtains a volume of the original signals and amplifies the high-frequency signals according to an amplification factor having a positive correlation with the volume of the original audio signals, to output improved audio components. The second obtaining unit obtains reference audio signals from the original audio signals. The synthesis unit synthesizes the improved audio components and the reference audio signals to output improved audio signals. |
| US09705461B1 |
Calculating and adjusting the perceived loudness and/or the perceived spectral balance of an audio signal
The invention relates to the measurement and control of the perceived sound loudness and/or the perceived spectral balance of an audio signal. An audio signal is modified in response to calculations performed at least in part in the perceptual (psychoacoustic) loudness domain. The invention is useful, for example, in one or more of: loudness-compensating volume control, automatic gain control, dynamic range control (including, for example, limiters, compressors, expanders, etc.), dynamic equalization, and compensating for background noise interference in an audio playback environment. The invention includes not only methods but also corresponding computer programs and apparatus. |
| US09705456B2 |
Class resonant-H electrosurgical generators
A generator for use with an electrosurgical device is provided. The generator has a gain stage electrically disposed between a first voltage rail and a second voltage rail, wherein the gain stage includes an input and an output. A voltage source operably coupled to the gain stage input and configured to provide an input signal thereto responsive to a drive control signal is also provided. The generator also has one or more sensors configured to sense an operational parameter of the amplifier and to provide a sensor signal corresponding thereto and a controller adapted to receive the sensor signal(s) and in response thereto provide a drive control signal to the voltage source. The generator has an amplifier output configured to supply an output voltage corresponding to the first voltage rail and the second voltage rail when the output of the gain stage falls between a voltage of the first voltage rail and a voltage of the second voltage rail and is configured to supply a peak voltage output when the voltage output is falls greater than the voltage of the first voltage rail or less than the voltage of the second voltage rail. |
| US09705453B2 |
Circuits and devices related to multi-harmonic control of amplified signals
Circuits and devices related to multi-harmonic control of amplified signals. In some embodiments, an amplifier circuit assembly can include an amplifier configured to provide a signal at an output. The amplifier circuit assembly can further include a matching network configured to provide impedance matching for the signal having a fundamental frequency, a broadband harmonic trap configured to substantially trap a plurality of harmonics associated with the fundamental frequency, and a dipole network configured to tune reactances associated with the broadband harmonic trap. The matching network, the broadband harmonic trap and the dipole network can be implemented in series from the output of the amplifier. |
| US09705452B2 |
Protection circuit for power amplifier
A power amplifier comprising a power stage comprises a voltage detection circuit configured to detect an output voltage of the power stage, a current detection circuit configured to detect an output current of the power stage, a control voltage generation circuit configured to generate a control voltage substantially proportional to the detected output voltage and the detected output current, and a control circuit configured to decrease an output power of the power stage when the control voltage exceeds a predetermined value. |
| US09705451B2 |
Power amplification module
An envelope tracking system is employed in a power amplification module that supports multiple frequency bands. The power amplification module includes multiple power amplification circuits, each of which includes: a first transformer to which a radio frequency signal is input; a differential amplification circuit, in which a first radio frequency signal output from transformer is input to a control electrode and in which a second radio frequency signal output from the transformer is input to a control electrode, the differential amplification circuit outputting an amplified signal obtained by amplifying a difference between the first and second radio frequency signals; and a second transformer for supplying, to the first differential amplification circuit, power-supply voltage varying according to the amplitude of the radio frequency signal and to which the first amplified signal is input. |
| US09705446B1 |
Modular multi-axial rotor
A modular, electricity generating apparatus comprises an elongate, central member comprising a first end and a second end; at least one solar foil disposed about the central member in fluid interacting relation thereto; the solar foil comprising an outer surface having photovoltaic properties; the first end and the second end dimensioned and configured to be connected to a connecting node; and, the elongate central member at least partially comprised of an electrically conductive material and configured to conduct electricity from at least one of the connecting nodes to the other of the connecting nodes. |
| US09705442B2 |
Asymmetrical multi-lane multi-phase motor drives
Motor drives and drive systems are provided. A motor drive of the subject invention can be an asymmetrical, multi-lane, multi-phase motor drive. The motor drive can include a master lane and slave lane having fewer phases than the master lane has. Each lane can be powered by a single direct current link. |
| US09705440B2 |
Fault tolerant electric power generating system
An electrical power generating system comprises a first permanent magnetic generator (PMG) stator winding of a generator machine, a first active rectifier communicatively connected to the first PMG stator winding, the first active rectifier operative to receive alternating current (AC) from the first PMG stator winding and convert the AC to direct current (DC), a direct current link communicatively connected to the first active rectifier, wherein the first active rectifier is operative to output the DC to the direct current link, a second PMG stator winding of the generator machine, and a second active rectifier communicatively connected to the second PMG stator winding, the second active rectifier operative to receive AC from the second PMG stator winding and convert the AC to DC, the second active rectifier communicatively connected to the direct current link and operative to output DC to the direct current link. |
| US09705437B2 |
Angular position estimation for PM motors
A method of determining the angular position (θ) of a rotor of an N-phase permanent magnet motor (PMM) includes providing a processor having an associated memory, wherein the memory stores an angular position determination (APD) equation or hardware is included implementing the APD equation. The APD equation determines the angular position from N-phase measurements obtained from the stator windings associated with each of the N-phases. A voltage or a current is forced upon the stator terminals of the stator windings for each of the N-phases, a resulting stator current or stator voltage is sensed to provide the N-phase measurements responsive to the forcing of the voltage or current, and the APD equation is used to determine the angular position from the N-phase measurements. |
| US09705434B2 |
Method for ascertaining a commutation angle
In a method for ascertaining a commutation angle in a permanently excited synchronous motor, the commutation angle indicates the position of a rotor within a magnetic period of the synchronous motor and is used for the field-oriented energization of the synchronous motor. The method includes the steps of specifying a random commutation angle as starting point of the method, impressing a current vector into the motor using the initially randomly specified commutation angle, ascertaining a positional deviation of the rotor, varying the commutation angle used for the energization with the aid of a controller structure in order to counteract the ascertained positional deviation, so that the commutation angle that comes about after a stabilizing period corresponds to the actual commutation angle of the rotor, an initial speed of the rotor being taken into account when ascertaining the positional deviation of the rotor. |
| US09705432B2 |
Micro pick up array pivot mount design for strain amplification
Systems and methods for aligning a transfer head assembly with a substrate are disclosed. In an embodiment a pivot mount is used for generating a feedback signal in a closed-loop motion control system. In an embodiment, the pivot mount includes primary spring arms and secondary spring arms extending between a pivot platform and a base of the pivot mount. The secondary spring arms are characterized by a lower stiffness than the primary spring arms, and strain sensing elements are located along the secondary spring arms. |
| US09705429B2 |
Power generating element, light emitting element, band-like light emitting body, and rescue display device
A power generating element is provided. The power generating element includes a pair of electrodes and an intermediate layer disposed between the pair of electrodes. The intermediate layer includes an insulating elastic body. The power generating element is flexibly bendable when receiving an external force, while causing a sliding transfer between at least one of the electrodes and at least one surface of the intermediate layer which faces the at least one of the electrodes, due to a difference in curvature between the electrodes and the intermediate layer. |
| US09705424B2 |
Ultrasound transducer with acoustic isolator and corresponding mounting method
An ultrasonic transducer device is disclosed. The device includes a body and an ultrasonic transducer mounted onto the body. The ultrasonic transducer comprises a shoulder and an O-ring placed on the shoulder. The O-ring substantially covers the interface between the ultrasonic transducer and the body. |
| US09705418B2 |
Power converter with oil filled reactors
It is provided a power converter for transferring power between a high voltage DC connection and a high voltage AC connection. The power converter includes a power converter assembly including: a first converter arm, a first reactor, a second reactor and a second converter arm, connected serially between the positive and negative terminals of the DC connection. The high voltage AC connection is provided between the first reactor and the second reactor. Each one of the converter arms includes a plurality of converter cells and each one of the converter cells includes a switching element and an energy storage element. Both the first reactor and the second reactor are oil filled reactors. |
| US09705412B2 |
Pulsed feedback switching converter
The present disclosure is directed to a switching power converter having a regulated output voltage or output current. The power converter uses a control unit having a signal conditioning circuit to produce a control voltage signal, which is used to drive a power stage of the converter. The signal conditioning circuit includes a comparator that compares a measured electrical quantity to a reference value representative of a desired regulated output quantity, and produces a digital detection signal based on the comparison. A control actuator uses the digital detection signal to produce a correction signal, which is received by an averaging circuit. The averaging circuit then produces the control voltage signal based on an average of the correction signal. |
| US09705408B2 |
Power converter with sleep/wake mode
Offline power converters draw very small amounts of power when unloaded or inactive (no load demand), power consumption may be further reduced by allowing the start-up controller and/or secondary-side controller to enter into a sleep mode (functions within the controllers shut down). When the energy storage capacitors for either the start-up controller or the secondary-side controller reach a low state-of-charge, either controller can wake itself and the other controller, thereby allowing the power converter to become active until both energy storage capacitors are refreshed enough for the controllers to go back into a low power sleep mode. This cycle, which draws very little average power from the AC line, continues until the power converter is required to remain awake (operational mode) and deliver power to the load. |
| US09705405B2 |
Power converters and methods for reducing voltage changes at an output of a power converter
Example switching power converters and methods for reducing voltage changes at an output of a power converter are generally disclosed. According to one aspect, a switching power converter includes an input, an output for providing an output voltage, at least one switch capable of causing a voltage overshoot of the output voltage when the switch is turned on, and a controller. The controller is configured to sense the output voltage, compare the sensed output voltage to a voltage reference, and adjust operation of the power converter based on the comparison of the sensed output voltage and the voltage reference to maintain the output voltage. The controller is further configured to decrease the voltage reference from a normal operation value to an overshoot reduction value before turning on the switch to decrease the output voltage and reduce an overshoot of the output voltage in response to turning on the switch. |
| US09705403B2 |
Apparatus and method for selective and adaptive slope compensation in peak current mode controlled power converters
An apparatus and a method for selective and adaptive slope compensation in peak current mode controlled power converter are disclosed. The selective and adaptive slope compensation in peak current mode controlled power converter is implemented by hardware, software, and/or combination of both to carry out start of a pulse width modulated period and delay of a start of slope compensation by a first time from the starting of the pulse width modulated period. |
| US09705400B2 |
Reconfigurable output stage
An output stage configuration with four configurable input/output terminals and four switches is specified. Each switch has a first main terminal, a second main terminal and a control terminal, which receives a control signal for controlling the open or closed state of the switch. The output stage is included in a circuit together with a first control apparatus and a second control apparatus. When a control stage of the first control apparatus is connected to the output stage, a control stage of the second control apparatus is electrically disconnected from the output stage, and the output stage operates in a first operating state. When the control stage of the second control apparatus is connected to the output stage, the control stage of the first control apparatus is electrically disconnected from the output stage, the output stage then operating in a second operating state. |
| US09705399B2 |
Adaptive threshold of a zero crossing comparator
A buck converter device with a zero-cross comparator with an adaptive threshold. The buck converter comprises of a control block that controls a first p-channel MOSFET switch, and a second n-channel MOSFET switch. The p-channel MOSFET switch and the n-channel MOSFET switch provide a sense signal utilizing parasitic bipolar junction transistors. The p-channel MOSFET provides a sense current for the pnp parasitic bipolar junction transistor, The n-channel MOSFET provides a sense current for the npn parasitic bipolar junction transistor. The sense current is stored on a capacitor, and establishes an adaptive offset adjustment to a zero-cross comparator. |
| US09705397B2 |
AC-DC converter with output power suppression
A power conversion apparatus for converting AC power supplied from an AC power source to DC power includes an AC-DC conversion circuit connected with the AC power source at an input end thereof for converting the AC power to DC power, a DC-DC conversion circuit connected with an output end of the AC-DC conversion circuit at an input end thereof for converting DC voltage level of the DC power generated by the AC-DC conversion circuit, a smoothing capacitor parallel connected to the output end of the AC-DC conversion circuit and the input end of the DC-DC conversion circuit, a DC link voltage detector for detecting a voltage of the smoothing capacitor as a DC link voltage, and a control unit for controlling operation of the DC-DC conversion circuit. The control unit suppresses an output power of the DC-DC conversion circuit, if the DC link voltage is smaller than a predetermined value. |
| US09705394B2 |
Overcurrent protection power supply apparatus
In a high voltage power supply apparatus, e.g., for an electric or hybrid vehicle, current is supplied from a high-voltage DC power source to a load via a power FET. A voltage detecting circuit detects the drain-source voltage VDS of the power FET when the current flows through the power FET. A first overcurrent protection signal generating circuit outputs a first overcurrent protection signal based on the detected drain-source voltage VDS of the power FET. A second overcurrent protection signal generating circuit outputs a second overcurrent protection signal based on a detected rate of increase of the drain-source voltage VDS of the power FET. A control circuit protects the components of the power supply apparatus from overcurrents by turning off the FET when the first overcurrent protection signal and/or the second overcurrent protection signal is generated and output to the control circuit. |
| US09705390B2 |
Oscillating type actuator having sufficient holding force without electric current
To provide a novel oscillating type actuator capable of securing a stoppage and holding when not energized, and producing a stable, responsive and highly durable oscillating arm even using a non-rare each magnet. The actuator is constituted by a housing; a shaft supported in the housing to be axially rotatable and has an output part to produce an output; a plate-shape oscillating arm that is fixedly supported to a shaft and has a swing surface perpendicular to the axis of the shaft, the oscillating arm performing a swing in a predetermine rotation angle range; two permanent magnets arranged along a swing direction of the oscillating arm and have pole faces different from each other on the swing surface; two magnet coils opposingly arranged to respectively face the permanent magnets; and a pair of interpoles arranged around a periphery of each of the magnet coils to opposingly sandwich one of the permanent magnets arranged side by side. |
| US09705385B2 |
Product specification setting apparatus and fan motor having the same
A product specification setting apparatus includes: an electronic tag for updatably storing specifications of a product; and a control computer for controlling the product according to the stored specifications. A fan motor includes: a motor driving unit for driving a motor for rotating a fan; an electronic tag for updatably storing specifications of the fan motor; and a control computer for controlling the motor driving unit according to the stored specifications. |
| US09705384B2 |
Rotor for rotating electric machine
A rotor is provided for a rotating electric machine. The rotor includes a magnetic pole core and a cooling fan. The cooling fan includes a base plate laser-welded to an axial end face of the magnetic pole core and a plurality of fan blades extending from the base plate. Further, in the rotor, a weld formed between the base plate of the cooling fan and the magnetic pole core has a pair of open ends. |
| US09705383B1 |
Light activated generator
Provided is a light activated generator comprising typically a plurality of vanes affixed to a hub rotatable around the longitudinal axis of an axle. Each vane comprises a conductor and comprises a planar surface oriented generally perpendicular to the longitudinal axis of the axle with each vane separated into a first surface and a second surface. The first and second surfaces are generally co-planer and perpendicular to the longitudinal axis of the axle. Additionally, the first and second surfaces have differing emissivities. When the light activated generator is illuminated with a radiant flux, the differing emissivities of the first and second surfaces produce a temperature gradient across the vane, and a thermal creep force across the planar surface generates a revolution of the vane around the longitudinal axis of the axle to motivate the conductor through a magnetic field, generating a voltage across the conductor. |
| US09705380B2 |
Electric motor equipped with deceleration device
An electric motor equipped with deceleration device (1) is provided with a main shaft component (200) that is formed substantially in a circular rod shape, and has one end portion (201) that is rotatably supported at a substantial center of a bottom portion (111) of a motor housing (110) and another end portion (202) that protrudes towards an outer side through an aperture in the motor housing (110), the main shaft component (200) is fixed to the motor housing (110) via the one end portion (201). An armature (130) is disposed inside the motor housing (110) so as to be on the same axis as the main shaft component (200) and so as to surround the main shaft component (200), and a deceleration device (10) is disposed between the armature (130) and the other end portion (202) of the main shaft component (200) so as to surround the main shaft component (200), and an output component (16), which is formed in a toroidal shape, is disposed on the same axis as the main shaft component (200) so as to surround the main shaft component (200). |
| US09705378B2 |
Drive device for electric vehicle
An object of the present invention is to prevent lubricant oil of a speed reduction unit from moving to an electric motor side and besides to prevent an eccentric load from acting on bearings supporting an input shaft. In a drive device for an electric vehicle including: a speed reduction unit including an input shaft driven by output of an electric motor; a hub unit rotationally driven by an output member of the speed reduction unit; and a housing accommodating the electric motor and the speed reduction unit, the configuration is made such that a partition for partitioning an accommodation section into respective accommodation spaces of the electric motor and the speed reduction unit is provided in the housing, and an oil seal member is placed between a peripheral edge portion of a center hole of the partition and a rotor support member the electric motor. |
| US09705377B2 |
Motor mount and damper
A system having a damper with six or more indentations on alternating sides of the damper, where each indentation is open to an outer circumferential surface of the damper and extends over halfway through a width of the damper, and six or more slots, each slot open to an undulating inner circumferential surface of the damper and extending through the width of the damper. |
| US09705376B2 |
Motor assembly
A motor assembly includes two cap bodies, a stator body, a rotor body and a fixing mechanism. Each cap body has a bearing holder and a plurality of positioning portions radially extended from the bearing holder. Each bearing holder has a bearing received. A shaft passes through a center part of the rotor body, and two ends of the shaft sleeved in the two bearings respectively. The stator body has a plurality of stator units aligned around an outer periphery of the rotor body. Under this arrangement, the stator units of the stator body is axially sandwiched by the positioning portions of the two cap bodies, and the stator body and the two cap bodies are fixed together via the fixing mechanism. The motor assembly simplifies the coil winding procedure for the stator body, so that the manufacturing costs of the stator body and the motor assembly are significantly reduced. |
| US09705372B2 |
Rotating electric machine and method of manufacturing same
A rotating electric machine includes: a stator including a stator core, slots provided in the stator core at equal intervals along the circumferential direction, and coils placed in the stator slots and configured to generate a rotating magnetic field; and a rotor rotatably provided with a predetermined rotation gap between the stator core and the rotor, wherein the rotating electric machine further includes a first varnish applied between the slots in the stator core and the coils for impregnation, and a second varnish applied directly onto enamel coating of the coils outside of the slots in the axial direction, the first varnish is a thermosetting varnish having a shear bond strength of a flat wire between the coils and the varnish is higher than that of the second varnish, and the second varnish is a thermosetting varnish having a glass transition temperature of approximately 104° C. or lower and the glass transition temperature of the second varnish by the Dynamic Mechanical Analysis (DMA) method is lower than that of the first varnish. |
| US09705369B2 |
Method of resin-sealing laminated core
A method of resin-sealing a laminated core, including inserting permanent magnets 24 into magnet insertion holes 18 of a core body 15, pressing the body 15 with upper and lower dies 11, 12, and injecting resin 29 to the holes 18 from a resin reservoir 17 of the die 11 or 12 via a runner 19 in a removable cull plate 14, one end of the runner 19 having plural resin injection holes 33, 34 per hole 18. The resin 29 presses the magnets 24 in the holes 18 to one sides in a radial direction of the holes 18. Thereby, resin-sealing is performed using the plate 14 and the magnets 24 are arranged in radially outward or inward sides even with narrow gaps between the magnets 24 and the holes 18 or without resin injection holes in centers in a width direction of the holes 18. |
| US09705365B2 |
Motor
A motor includes a stator, a rotor, a case, and back-surface magnet portions. The rotor has a first rotor core, a second rotor core and a field magnet. Each of the first and second rotor cores has a core base and claw-shaped magnetic poles. The field magnet is sandwiched between the first rotor core and the second rotor core and causes the claw-shaped magnetic poles of the first rotor core and the second rotor core to function as different magnetic poles. The back-surface magnet portions include a second and a first back-surface magnet portions respectively provided on the back surfaces of the claw-shaped magnetic poles of the second rotor core and the first rotor core. Size of the second back-surface magnet portion differs from size of the first back-surface magnet portion are different from each other. |
| US09705363B2 |
Communication control device and mounting board
In a communication control device in which an antenna electrode having an antenna connected thereto, a power supply circuit, and a communication circuit are mounted on a mounting board, the antenna electrode is disposed at one corner portion on a principal surface of the mounting board, the communication circuit is disposed on a side of a first side of the principal surface that shares the corner portion, and the power supply circuit is disposed on a side of a second side facing the first side. Further, a first signal path connecting the antenna electrode and the communication circuit extends along the first side, and a second signal path connecting the antenna electrode and the power supply circuit extends along a third side that shares the corner portion and is perpendicular to the first side. |
| US09705361B2 |
Power supply device and method of controlling power supply
A converter which converts first AC power input from an external power system to DC power, a storage device charged with the DC power from the converter, an inverter which converts DC power from the storage device to second AC power, an output AC power generating unit to which the first AC power and the second AC power are input, the unit which generates output AC power, and a controller which obtains external power information indicating a relationship between a power supply and a power demand in the external power system through a network and outputs a control signal to control the output AC power generating unit according to the external power information are provided. The controller controls the output AC power generating unit according to a state of a margin of the power supply. |
| US09705359B2 |
Mobile cart and power system therefor
A mobile cart has a battery assembly, which includes an on-board charger for selectively recharging one or more batteries to ensure constant operation of the powered equipment provided on the cart. The battery assembly possesses a removable battery configuration and is operated by a Battery Control System (BCS). The BCS is an intelligent control system for removable batteries and battery cell packs to provide an improved system of charging and discharging the individual batteries. |
| US09705352B2 |
Wireless charging method and apparatus
A wireless charging method includes determining whether at least one wireless charging device is in a wireless charging area. When it is determined that there is one wireless charging device in the wireless charging area, the wireless charging device is charged. When it is determined that at least two wireless charging devices are in the wireless charging area, the priority of wireless charging among the at least two wireless charging devices is determined, and the wireless charging device having higher priority is wirelessly charged. |
| US09705351B2 |
Battery exercising device
The disclosure relates to a battery exercising device configured to discharge and charge a rechargeable battery, such as a lead-acid battery, after a set amount of time has elapsed. The battery exercising device is configured to receive electrical power from a power source and periodically transfer this power into a battery connected to the battery exercising device. After a period has elapsed, for example two weeks, the device applies a discharging load to the connected battery to drain the battery to a predetermined discharge level. Thereafter, the device charges the connected battery to a predetermined charge level. Once charged to the predetermined charge level, the device again waits the set period of time and repeats the discharge/recharge sequence. |
| US09705349B2 |
Charge control device and charge time calculation method
A charge control device that charges a battery using a power output from a charger has a charge state (SOC) calculation unit for calculating the SOC of the battery using the voltage and current of the battery, a charger control unit that controls a charger that charges the battery, and a charge time calculation unit for calculating, on the basis of the SOC calculated by the SOC calculation unit, the remaining charge time of the battery till the SOC of the battery reaches a prescribed SOC. When the charge current falls below a current threshold, the charger control unit sends intermittent power commands to the charger based on the prescribed SOC, and the charge time calculation unit subtracts, from the charge time calculated when the charge current has fallen below the current threshold, predetermined time values based on the power commands. |
| US09705348B2 |
Method of assembling a power-conditioned solar charger
The present invention relates to methods, tools and systems for manufacturing a durable and portable power-conditioned personal solar system charging apparatus. Various voltage and amperage matching algorithms are manipulated to particularize the personal solar system to power and/or charge an intended portable device or a set of intended portable devices having direct current (DC) load requirements. The optimized personal solar system that is matched to an intended device allows direct coupling to the intended device without the use of an internal battery or ancillary electronic circuit boards to distract the personal solar system output, and facilitates “fast” charging modes. |
| US09705346B2 |
Electric vehicle charging station with cable retaining enclosure
In various embodiments, an enclosure for a charging station is provided having a peripheral casing configured to retain a charging cable on an upward facing surface of the peripheral casing between a front user interface side and a charging station mounting surface. |
| US09705342B2 |
Battery equalizing circuit
The present disclosure discloses a battery equalizing circuit, which comprises a first battery unit, a second battery unit, a current detecting resistor, an equalizing inductor, a first control switch, a second control switch and a feedback control circuit. The first battery unit is connected in series with the second battery unit. The first battery unit, the current detecting resistor, the equalizing inductor and the first control switch are electrically connected with each other to form a first circuit loop. The second battery unit, the current detecting resistor, the equalizing inductor and the second control switch are electrically connected with each other to form a second circuit loop. The feedback control circuit is connected in parallel with the current detecting resistor to detect a voltage drop across the current detecting resistor, and switch between the first and the second circuit loop so as to make an equalizing current substantially constant. |
| US09705337B2 |
Mitigating an effect of a downstream failure in an automatic transfer switching system
A system may comprise a first switch connected to an output of a first power source, a second switch connected to an output of a second power source, a first sensor connected to an output of the first switch, a second sensor connected to an output of the second switch, a third switch connected to the first sensor and the second sensor and connected to a load, and a control device connected to the first switch, the second switch, the first sensor, the second sensor, and the third switch. |
| US09705335B2 |
Method and system for allocating energy
A method for allocating energy to a plurality of devices, wherein each device is configured to consume, store and/or supply energy, the method includes the steps of: assigning each device to a group of devices; assigning an aggregation node device to each group of devices; for a selection of devices transmitting local power cost functions of the devices and/or power usage profiles of the devices with respect to a predetermined time slot to the assigned aggregation node device; at the aggregation node device, generating aggregated data as a function of the received local power cost functions and/or power usage profiles; transmitting the aggregated data to a central processing device; at the central processing device, optimizing a global cost function for allocating power to the devices as a function of the aggregated data. |
| US09705334B2 |
Method for operating a wind energy installation
The present invention concerns a method of feeding electric power into an electric network wherein the feed is effected by means of at least one wind power installation with a first feed-in arrangement at a feed-in point into the electric network, and the feed is effected in dependence on electric parameters in the network and measurement values of the electric parameters or measurement values for determining the electric parameters are detected at measurement times at predetermined time intervals and wherein the measurement times are synchronized to an external time signal available outside the first feed-in arrangement. |
| US09705332B2 |
Energy storage systems
A method for controlling an energy storage system for connection to a power system, and such an energy storage system are provided. The method makes use of a model based predictive controller to optimize the charging/discharging rates of energy storage elements in a hybrid energy storage system. The method includes determining respective desired charging/discharging rates for the energy storage elements in dependence upon state of charge predictions from respective models of the storage elements, using model predictive control, and adjusting respective charging/discharging rates of the storage elements in accordance with the determined rates. The energy system includes a controller configured to control respective charging/discharging rates of the energy storage elements in accordance with the method. |
| US09705326B2 |
Power consumption mode guiding device and system
A power consumption mode guiding device includes a local system wherein the frequency of power on an AC line, is controlled at a target frequency determined according to the state of charge of a power storage device. The power consumption mode guiding device includes a frequency detection unit that detects the actual frequency of power on the AC line, an information storage unit in which guidance information for guiding the mode of use of a power consumption device by a power consumer (D) to a prescribed mode are stored in advance in association with frequency information obtained from detection results from the frequency detection unit, and a guidance information output unit that reads out, from the information storage unit, the guidance information associated with the frequency information obtained from the detection result from the frequency detection unit, and outputs the guidance information to the power consumer (D). |
| US09705324B2 |
Converter system for AC power sources
A converter system for coupling to an ac power source includes a rectifier and a bi-directional converter. The rectifier has a first set of terminals inductively coupled to an ac power source and a second set of terminals coupled in series with a series dc bus, and is operable to convert ac power at the first set of terminals to dc power at the second set of terminals. The bi-directional converter has a first set of terminals coupled to the ac power source and a second set of terminals coupled to a parallel bus, and is operable to transfer power from the ac source to the parallel bus in a first operating mode and transfer power from the parallel bus to the series dc bus via the rectifier in a second operating mode. A corresponding power generation network and power transmission method are also provided. |
| US09705319B2 |
Power supply system providing fault detection using switching arrangement
A power supply system includes a first-battery, a battery unit including a second-battery, and a generator. The battery unit is connected to the generator and the first-battery via a conductor. The battery unit includes a connection-terminal connected to the conductor, an output-terminal connected to a load, a first-switch disposed on a wiring connecting the connection-terminal and the output-terminal, a branch line branching off from the wiring between the first-switch and the output-terminal and connected to the second-battery, a second-switch disposed on the branch line between the wiring and the second-battery, a first-voltage-detecting unit detecting voltage of the connection-terminal, and a switch control unit controlling the first and second-switches. The power supply system further includes a second-voltage-detecting unit detecting electromotive force of the first-battery, and a fault-determining unit determining a fault of the conductor based on opening/closing states of the first and second-switches and results of the first and second-voltage-detecting units. |
| US09705318B2 |
Over-limit electrical condition protection circuits for integrated circuits
Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit. |
| US09705315B2 |
Protection circuit for preventing an over-current from an output stage
A semiconductor device including: an output stage, including a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, including a first voltage clamping circuit, including a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are for clamping a gate voltage of the PMOS of the output stage and are connected in series, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor for selectively coupling the first supply voltage to the node. |
| US09705314B2 |
Electromagnetic DC pulse power system including integrated fault limiter
An electromagnetic direct current (DC) pulse power system includes a plurality of pulse forming networks (PFN) module, and an energy storage capacitor and circuit interruption apparatus. Each PFN module includes a PFN circuit configured to generate a pulsed DC output power. The PFN circuit includes an energy storage inductor with a primary winding having a primary inductance that controls a primary impedance of the PFN circuit. The electromagnetic direct current (DC) pulse power system further includes an auto-transformer having a multi-stage fault-limiting system configured to reduce fault current. |
| US09705312B2 |
Circuit breaking arrangement
A circuit breaking arrangement is adapted to be connected to a current path in at least one transmission line arranged to carry an electrical current for controllably effecting discontinuation of flow of electrical current in the at least one transmission line. The circuit breaking arrangement includes a plurality of series connections of a plurality of power semiconductor switching elements. The plurality of series connections of power semiconductor switching elements are connected in parallel relatively to each other. |
| US09705310B2 |
Adaptive fault clearing based on power transistor temperature
A system includes a current measurement unit, an overload timer, and a processing unit. The current measuring unit measures current through a power transistor, and the overload timer measures an overload time associated with the measured current. The processing unit receives a user-specified overload time setting or a user-specified overload amperage setting associated with a protection device connected in series with a load, receives a temperature measurement of a component associated with the power transistor or a measurement of overload time associated with the current, wherein the power transistor supplies the current to the load and the protection device, and selectively turns off the power transistor based on the measured temperature, the measured current through the power transistor, and the user-specified overload amperage setting or based on the measured temperature, the measured overload time, and the user-specified overload time. |
| US09705307B2 |
Self-sensing reverse current protection switch
A reverse current protection (RCP) circuit is provided that includes an RCP switch coupled between a power supply rail and a buffer power supply node. A control circuit powered by a buffer supply voltage on the buffer power supply node controls the RCP switch to open in response to a discharge of a power supply voltage carried on the power supply rail. |
| US09705305B2 |
Resilient communication for an electric power delivery system
A system for resiliently monitoring an electric power delivery system may include a plurality of server intelligent electronic devices (IEDs) configured to monitor and/or control the electric power delivery system. Each server IED may be communicatively coupled to a client control system by a plurality of communication paths. If a communication path fails, communication may continue along another path. In an embodiment, the client control system may include dual primary client controllers that continually request information from the server IEDs using multiple of the communication paths. The client controllers may request information from each other if the information is not received from the server IEDs, for example, due to a communication failure. In an embodiment, the client control system and server IEDs may be communicatively coupled in a loop topology, and each direction around the loop may be a distinct communication path. |
| US09705296B1 |
Snap-in electrical connector
A connector assembly including a connector body with a spring clip including a first free end for engaging an electrical cable received within the connector body and a second free end for engaging a side wall of an electrical box upon installation. During insertion of the connector body the second free end engages the knock-out hole perimeter and deforms so as to permit further insertion. Once the connector body is fully inserted, the spring clip cooperates with a lug on the connector body to hold the connector assembly onto the electrical box. A method of manufacturing a connector assembly via an orbital riveting process is also provided. |
| US09705294B2 |
Enclosed switchboard
An enclosed switchboard includes: a device containing board which contains main circuit devices such as circuit breakers; and a cable connection board which is arranged side by side adjacently to the device containing board, and contains cables that input and output electric power to/from the main circuit devices. In the enclosed switchboard, the cable connection board is configured by one housing; and the inside of the housing is divided into two by a partition plate to be comparted to a cable lead-in compartment which contains lead-in side cables and a cable lead-out compartment which contains lead-out side cables. |
| US09705291B2 |
Ignition plug
An ignition plug having a ground electrode that includes a base material layer and an erosion-resistant layer having a thermal conductivity of 40 w/m·K or more. The erosion-resistant layer extends at least from the center-electrode-facing portion to a location closer to the fixed end than a front end of the center electrode and 0.2 mm≦thickness t1 of the erosion-resistant layer≦thickness T of the ground electrode 30−0.6 mm is satisfied. |
| US09705290B2 |
Spark plug boot cover assembly
An electrically conductive cover which in assembly is received over at least part of a spark plug boot and at least part of a nut portion of a metal body of a spark plug received in the boot. The cover may have an opening through which an arm portion of the boot extends which arm portion receives an electric wire for supplying a current at a high potential voltage to the spark plug. |
| US09705289B2 |
High brightness multijunction diode stacking
An apparatus includes at least one multijunction diode laser situated to emit a plurality of beams along respective mutually parallel propagation axes, each beam having an associated mutually parallel slow axes and associated collinear fast axes, a fast axis collimator situated to receive and collimate the plurality of beams along the corresponding fast axes so as to produce corresponding fast axis collimated beams that propagate along associated non-parallel axes, and a reflector situated to receive the plurality of fast axis collimated beams and to reflect the beams so that the reflected fast axis collimated beams propagate along substantially parallel axes. |
| US09705286B2 |
Method for manufacturing semiconductor device, and semiconductor device
With a method for manufacturing a semiconductor device, a semiconductor layer having a protrusion on a main face is formed. The protrusion includes an upper face and side faces. A conductive layer on a region that includes at least the upper face and the side faces of the protrusion is formed. A first mask that partially covers a surface of the conductive layer is formed. A part of the conductive layer is etched by using the first mask in a first etching process. A second mask that at least partially covers the surface of the conductive layer that has undergone the first etching process is formed. A part of the conductive layer is etched by using the second mask to expose a part of the semiconductor layer and to form the conductive layer into an electrode in a second etching process. |
| US09705284B1 |
VCSEL with at least one through substrate via
In an illustrative embodiment, a VCSEL comprises a substrate, a first DBR on a first major surface of the substrate, an active region on the first DBR, a second DBR on the active region, and electrically conductive vias that pass through the substrate and provide ohmic contact with the DBRs so that electrical connections to both DBRs are available on the substrate side of the VCSEL. The VCSEL is formed by forming a first DBR on a first major surface of a substrate, forming an active region on the first DBR, forming a second DBR on the active region, thinning the substrate, making a first via hole through the substrate to the first DBR, making a second via hole through the substrate and the first DBR, filling the first via hole with an electrically conducting material to contact the first DBR, filling the second via hole with an electrically conducting material, and coupling the second via hole to the second DBR. |
| US09705283B1 |
Diffused channel semiconductor light sources
A semiconductor vertical resonant cavity light source includes an upper mirror and a lower mirror that define a vertical resonant cavity. A first active region is within the vertical resonant cavity for light generation between the upper mirror and lower mirror. The vertical resonant cavity includes an inner mode confinement region and an outer current blocking region. A depleted heterojunction current blocking region (DHCBR) is within the outer current blocking region of at least one of the upper mirror, lower mirror, and first active region. A conducting channel within the inner mode confinement region is framed by the DHCBR. The DHCBR forces current flow into the conducting channel during operation of the light source. A cavity length within the inner mode confinement region equals or exceeds the cavity length formed in the DHCBR. |
| US09705281B2 |
Semiconductor light source driving apparatus
A semiconductor light source driving apparatus of the present disclosure includes a switching power supply that supplies a DC voltage, a power source switching FET, a coil, an inverting FET driver, a semiconductor light source device, and a free-wheeling diode. The power source switching FET switches on/off an output of a positive terminal of the switching power supply in accordance with an input PWM signal. The coil has a first end connected to the output of the power source switching FET. The inverting FET driver is connected between a second end of the coil and a negative terminal of the switching power supply and switched on/off in accordance with an input signal. The semiconductor light source device is connected between the second end of the coil and the negative terminal of the switching power supply. The first end of the coil and the negative terminal of the switching power supply are connected to the free-wheeling diode. |
| US09705280B2 |
Systems and methods for adaptively controlling a thermoelectric cooler
A system, method, and device for efficiently maintaining a stable operational temperature for precise operation of a laser. The system can include an ambient temperature sensor, a cooler controller adapted to control a cooler having an adjustable setpoint, a processor, and a memory coupled to the processor. The memory can store software instructions that, when executed by the processor, cause the processor to perform operations that can include receiving data from the sensor and determining the ambient temperature based on the received data. The determined ambient temperature can be compared to a current setpoint. When the delta exceeds a predetermined threshold, the setpoint can be adjusted to enable the operating environment of the laser to reach a control temperature closer to ambient conditions (and within a predetermined operating temperature range of the laser). Adjusted setpoint data can be transmitted to the cooler controller to adjust the setpoint of the cooler. |
| US09705278B2 |
Resolution of mode hopping in the output of laser cavities
An optical system includes a laser cavity on a base. The laser cavity generates a light signal in response to application of an electrical current to the laser cavity. The system includes first electronics that apply a target level of the electrical current to the laser cavity so as to cause the laser cavity to generate the light signal. The light signal experiences mode hops at electrical current levels that shift to higher current levels in response to increasing laser operation times. A first one of the mode hops occurs at a first current level and a second one of the mode hops occurs at a second current level that is higher than the first current level. The system also includes a phase shifter that interacts with the laser cavity so as to shift the mode hops to lower current levels than occur in the absence of the phase shifter. |
| US09705275B2 |
Laser assembly
The invention relates to a laser assembly (100) having a laser (L) for generating primary laser pulses (1), beam splitting optics (15) for splitting a primary laser pulse into a plurality of temporally staggered sub-pulses, and having focusing optics (17-19) for focusing the sub-pulses in or on an object (20) so that every sub-pulse is focused in a separate focus volume (F). The invention is characterized in that the mutual spatial and/or temporal relationship of the focus volumes (F) of the sub-pulses originating from a common primary laser pulse is variably adjustable. The invention also relates to a corresponding method. |
| US09705271B2 |
Fitting structure for connector
Provided is a connector (10) whereof a cover (60) is prevented from falling off a housing (20). The connector (10) is provided with: the housing (20), which is capable of fitting to a counterpart housing (90) and arranged in proximity or in contact with a peripheral member such as a solenoid (80) when fitting to the counterpart housing (90); and the cover (60), which is independent from the housing (20) and attached to the housing (20) so as to cover an electric wire (100) drawn out from a wire outdrawing surface of this housing (20). When the housing (20) fits to the counterpart housing (90), the cover (60) is faced by the peripheral member in a separating direction from the housing (20) so that the cover (60) is arranged to be interposed between the housing (20) and the peripheral member such as the solenoid (80). |
| US09705270B2 |
Universal socket solution
A universal power outlet, a universal junction box associated with a cover, and a universal extension cord. Sensors within openings in electrical sockets detect different characteristics of plug contacts. In response to the detected characteristics, power requirements for an energy consuming device associated with the plug are correlated. Logic dynamically selects and delivers a level of required power, from multiple available levels of power, to the device based on the detected characteristics. |
| US09705268B1 |
Connector with configuration pin between ground pin and power pin
The present invention is to provide a connector having a configuration pin, configured to connect with a USB Type-C transmission port and including at least a ground terminal, at least a power terminal, at least a configuration channel and two signal transmission terminals, wherein each of the terminals and channels extends through an insulating base and has an inserting portion at the front end of the insulating base and a connecting portion at the rear end of the insulating base, and the connecting portion of the configuration channel lies between the connecting portion of the power terminal and the connecting portion of the ground terminal, thereby forming the configuration pin between a ground pin and a power pin of the connector. Thus, a resistor can be easily connected between the configuration pin and the ground pin or the power pin according to practical needs, without the risk of short-circuiting. |
| US09705265B2 |
Configurable electrical connector key for electronic door locks
A configurable electrical connector key for connecting an electronic door lock to an external unit, such as a lock monitoring or control system, includes a connector key housing shaped to engage the electronic door lock and a configurable circuit mounted within the connector key housing that makes a configured interconnection between selected components within the door lock and the external unit. The combination of an electrical connector key and an electronic door lock and a system and method including multiple differently configured electrical connector keys and one or more standardized electronic door locks allow selected sensors and functions of the door lock to be enabled by selecting an appropriately configured electrical connector key. |
| US09705263B2 |
Plug connector assembly with light pipe and plural LEDs
A plug connector assembly including a cable connected to a plug connector, the plug connector including an insulative cover having a light region, a printed circuit board (PCB) received in the insulative cover and having a first surface and an opposite second surface, a mating member mounted on the PCB and extending through the insulative cover, a pair of light-emitting diode (LED) lamps, and a light guide disposed between the two LED lamps, wherein the mating member is mounted on the first surface of the PCB and the two LED lamps are mounted on the second surface of the PCB and wherein the light guide has a top face exposed to the light region of the insulative cover. |
| US09705260B2 |
Collective ground connection structure for connectors
Connectors with internal noise filter (10A, 10B) are provided with a uniting means (17, 18) for uniting the connectors with internal noise filters with each other. A terminal fitting (20) connected to one electrode portion (32A) of a capacitor (30) is provided in a connector housing (11a, 11B). A ground connection terminal (40A, 40B) is composed of an electrode connecting portion (42) to be connected to the other electrode portion (32B) of the capacitor (30) and a ground connection portion (41A, 41B) extending outwardly of the connector housing (11A, 11B) from the electrode connecting portion (42) and including a bolt hole (46H) into which a bolt (B) is fittable. When the respective connectors with internal noise filter (10A, 10B) are united by the uniting means (17, 18), the respective ground connection portions (41A, 41B) are overlapped and the respective bolt holes (46H) are aligned. |
| US09705259B2 |
Electrical connector part having a resistance coding
An electrical connector part for transmitting a charging current has at least two contact elements for producing an electrical contact having associated contact elements of another electrical connector part, a support element on which the at least two contact elements are disposed, and a resistance device which is electrically connected to the at least two contact elements. The resistance device has a circuit board, an electrical resistor disposed on the circuit board, and at least one contact spring disposed on the circuit board and electrically connected to the resistance, the circuit board being retained on the support element and the at least one contact spring electrically contacts one of the at least two contact elements. Thus, an electrical connector part can be created which in a simple manner enables the integration of a resistance device into an electrical connector part for the purpose of a resistance coding to provide identification information to an electrical plug to be mated to the electrical connector part. |
| US09705250B2 |
Patch cord plug organizer
The present invention is directed to a cable organizer. The cable organizer has a base with a plurality of ports. Each port is configured to hold a plug extending from a patch cord. The cable organizer also has a plurality of flanges connected to the base and a plurality of latch mechanisms. Each flange defines a side of one of the ports and each latch mechanism is connected to the ports by a pivot element. |
| US09705245B2 |
Plug-in connection having a fixed line
A plug-in connection is described having a contact carrier including a contact element, which is mechanically connected to the contact carrier; a line has an electrical conductor, which is electrically connected to the contact element, and has an insulation which surrounds the electrical conductor. The line is mechanically connected to the contact carrier, the plug-in connection having a fixing element, into which is accommodated an uninsulated area of the line in which the electrical conductor is not surrounded by the insulation, and which fixes the electrical conductor to the contact carrier. |
| US09705244B1 |
Electric connector
The electric connector includes an outer shell, at least one terminal, at least one floating resilient part, at least one screw and a panel. The outer shell includes at least one terminal groove and at least two fastening grooves. The floating resilient part includes at least one inner resilient tab and at least one outer resilient tab. The terminal groove is provided at the middle portion of the outer shell and has an end opening provided at the center of the panel. The fastening grooves are respectively provided at two sides of the outer shell and have end openings provided at two sides of the panel. The terminal is pluggable into the terminal groove, and a head of the terminal passing through the ending opening of the terminal groove is connected with a terminal of a mating connector. |
| US09705237B2 |
Electrical connector with excellent waterproof function
An electrical connector has a mating cavity opening forwardly. The electrical connector has a main body, a terminal module and a sealing member. The terminal module has an insulator and a plurality of conductive terminals received therein. The conductive terminals have contacting portions exposed into the mating cavity and connecting legs. The terminal module is received in the main body. The sealing member is filled in a gap between the terminal module and main body to seal the gap. |
| US09705234B2 |
Modular electrical connector assembly and associated method of making
A method for producing modular electrical connectors having varying contact element configurations includes providing a common header component having a plurality of receptacle spaces defined therein. A plurality of different contact sub-assemblies are provided having varying contact element configurations, with each of sub-assembly having a common size configured for receipt in the receptacle spaces. A pattern of the contact sub-assemblies is defined for a particular desired connector configuration from any combination of the contact sub-assemblies, and the contact sub-assemblies are fitted and adhered into the receptacle spaces in the header component according to the pattern. A kit may be provided with the modular components for making the connectors. |
| US09705233B2 |
Connector
To lengthen the insulating distance from a conductive member to the outer surface of a housing while curtailing any increase in the size of a connector, a plurality of ribs are formed on a cover which protrude towards a housing and surround the outer periphery of a housing chamber in the housing. Grooves are formed in the housing for insertion of the ribs. The plurality of ribs provided in the cover include a first rib positioned in the longitudinal direction relative to the housing chamber, and a second rib positioned on the side of the housing chamber with an opening for insertion of another connector. |
| US09705232B2 |
Encased power receptacle
The present invention relates to encased receptacle embodiments for mounting to recessed electrical boxes. |
| US09705223B2 |
Socket, connector using such socket, and header used in such connector
A socket-side retaining fitting includes: a rising portion extending toward a header; a locking piece portion being a part continuing to an upper end portion of the rising portion while curving, and configured to lock a locked portion of a header-side retaining fitting attached to the header. A socket housing includes a covering portion provided in such a way as to cover at least part of the locking piece portion, and configured to restrict movement of the locking piece portion. |
| US09705222B2 |
Female terminal with resilient piece having a contact surface that gradually narrows to a contact point
A female terminal (10) includes a tubular portion (14) configured to receive a male terminal (11) therein. Resilient pieces (23, 26) extend in from a bottom wall (15) and a ceiling wall (17) of the tubular portion (14) and contact the male terminal (11). Each resilient piece (23, 26) includes a line-contact portion (29, 31) that slides in line or surface contact with the male terminal (11), a contact portion (25, 28) to contact the male terminal (11), and a gradually changing portion (30, 32) formed from an end (29B, 31B) of the line-contact portion (29, 31) to a top (25A, 28A) of the contact portion (25, 28) and not protruding from a plane flush with a contact surface (29A, 31A) of the line-contact portion (29, 31). Thus, a contact area with the male terminal (11) is reduced gradually toward the contact portion (25, 28). |
| US09705221B2 |
Electronic component
An electronic component includes at least a contact member having, on a surface of a contact portion adapted to come into contact with another contact member, at least an undercoat plating layer and a main plating layer formed on the undercoat plating layer. A coating containing a fluorine-based oil is provided on the main plating layer, and the coating has a dry coating weight per unit area on the main plating layer of greater than or equal to 0.011 mg/cm2. |
| US09705219B2 |
Connector in which contact is inserted into hole of housing to separate hole into multiple spaces, and connector unit including connector
A connector includes a housing and a signal plug contact provided in the housing. The housing includes a hole that expands from part of the housing in which the signal plug contact is provided. |
| US09705215B2 |
Electrical connector having two movable parts
A housing of a lower connector has an opening on a side of an upper connector, and houses two movable parts movably from a first state of, by having upper portions thereof engaged with the opening, being in proximity to each other to form a guide hole, and a second state of, by releasing the engagement, being distanced from an external signal terminal. At positions contactable with the two movable parts, the housing has a protrusion whose tip gradually tapers toward the two movable parts in directions in which the two movable parts face each other. The protrusion guides the two movable parts in mutually separating directions, when the engagement between the opening of the housing and the upper portions of the two movable parts is released associated with depression of the upper connector, and the tip enters the gap through which the two movable parts face each other. |
| US09705214B2 |
Electrical contact and electronic circuit
The electrical contact (200) comprises a contact part (212) exhibiting a surface (228, 230) intended to be in contact with the surface of a support, and a clip (202) intended to receive a pin of an electrical component, so that the pin received lies along a main axis parallel to an up/down direction. The clip (202) comprises at least two jaws (204, 206, 208, 210) around the axis A, which are intended to grip the pin laterally, each jaw (204, 206, 208, 210) exhibiting a fixed end and a free end, and the contact surface is formed by at least one flange (228, 230) intended to come to bear on said surface of the support. |
| US09705207B2 |
Single band dual concurrent network device
A network device comprising, a first radio module configured to transmit and receive first radio signals in a first frequency band, a first antenna array configured to transmit and receive the first radio signals for the first radio module in the first frequency band, a second radio module configured to transmit and receive second radio signals in the first frequency band, a second antenna array configured to transmit and receive the second radio signals for the second radio module in the first frequency band, wherein, in operation, the first radio module and the second radio modules function concurrently using the first frequency band while at least 40 dB of antenna isolation is maintained between the first antenna array and the second antenna array. |
| US09705205B2 |
Bi-polarized broadband annular radiation unit and array antenna
A bi-polarized broadband annular radiation unit, for being installed on a metal reflective plate thus constituting a communication antenna and defining an annular construction by two pairs of orthogonally polarized dipoles, includes two pairs of orthogonally polarized dipoles, each dipole comprising two symmetrical unit arms of a single line sheet shape, one end of a unit arm being facing to a corresponding end of the other unit arm, and a distal end of each unit arm of at least one pair of dipoles is provided with a loading line; and a plurality of balun arms feeding power to and supporting respective dipoles, each balun arm including two parallel balun lines, and the top ends of the two balun lines being connected with corresponding ends of the two unit arms of a corresponding dipole. Each unit arm and the balun line and/or loading line connected to the same unit arm are made by sheet metal stamping forming process or casting process. |
| US09705204B2 |
Low-profile wireless connectors
An electronic device may include a PCB having a substantially planar surface and one or more electronic components mounted thereon. A first EHF communication unit may be mounted on the substantially planar surface of the PCB. The first EHF communication unit may include a first planar die containing a first communication circuit, the first die extending along the substantially planar surface of the PCB in a die plane. A first antenna may be operatively connected to the first circuit by interconnecting conductors, the first antenna being configured to at least one of transmit and receive electromagnetic radiation along a plane of the substantially planar surface of the PCB. The first EHF communication unit may have an uppermost surface having a height from the substantially planar surface of the PCB, the first EHF communication unit height being determined by an uppermost surface of the die, the first antenna, and the interconnecting conductors. |
| US09705202B2 |
Semiconductor device, method of manufacturing the same, in-millimeter-wave dielectric transmission device, method of manufacturing the same, and in-millimeter-wave dielectric transmission system
A millimeter-wave dielectric transmission device. The millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween. |
| US09705199B2 |
Quasi TEM dielectric travelling wave scanning array
A dielectric travelling wave antenna (DTWA) using a TEM mode transmission line and variable dielectric substrate. |
| US09705197B2 |
Superimposed multimode antenna for enhanced system filtering
The disclosure concerns a method of designing antennas to reduce the amount of rejection and complexity from the filter system. A superposition of a symmetrical frequency response from the antenna structure coupled with a non-symmetrical frequency response from a counterpoise structure generates increased rejection of out-of-band components. |
| US09705195B2 |
Antenna device and wireless device
According to an embodiment, the antenna device includes a substrate, a through hole, first and second grounded conductors, a radiating element and a feeder line. The substrate includes first to third layers. The third layer is formed between the first and the second layers. The through hole is formed on a substrate. The first grounded conductor is formed in the first layer and has a gap positioned between the first grounded conductor and the through hole. The second grounded conductor is formed in the second layer. The radiating element transmits or receives linearly-polarized waves. The feeder line is formed in the third layer, and is electrically continuous with the through hole. The feeder line includes a straight line that is formed in the third layer in an area of projection of the gap in thickness direction of the substrate and that is formed to be substantially parallel to a plane of polarization of the linearly-polarized waves. |
| US09705192B2 |
Antenna device and communication terminal apparatus
An antenna device includes an antenna coil including a first conductive pattern disposed on a first major surface of a magnetic sheet, a second conductive pattern disposed on a first major surface of a non-magnetic sheet, and an interlayer conductor connecting the first conductive pattern and second conductive pattern. The antenna coil including the first conductive pattern and second conductive pattern defines a spiral or substantially spiral pattern. The antenna device is a resin multilayer structure in which its base body is a laminate of the magnetic layer and non-magnetic layer and the predetermined patterns are disposed inside and outside the laminate. |
| US09705185B2 |
Integrated antenna and antenna component
An antenna is disclosed. The antenna can include an aerodynamic surface and an antenna component comprising a structure configured to extend from the aerodynamic surface. The structure and at least a portion of the aerodynamic surface can form an antenna, such as a half double-ridge horn antenna or a half Vivaldi antenna. In one aspect, the structure can be configured to support a pod, thus integrating the antenna with a mechanical mounting structure for the pod. |
| US09705181B2 |
Antenna connecting structure and electronic device including same
An antenna connecting structure includes a battery as a first component having a first main surface and a second main surface directed oppositely to the first main surface, a housing component including a flat portion located on the first main surface side, a spacer located on the first main surface, a sheet-like antenna unit main body located on a surface of the spacer opposite to the first main surface and abutting on the flat portion in surface contact, a circuit board disposed on the second main surface side and having a connector, an antenna connecting cable extending from the antenna unit main body and having flexibility, and an antenna connecting terminal disposed at an end of the antenna connecting cable and connected to the connector. |
| US09705180B2 |
Antenna having flexible feed structure with components
Electronic devices may include antenna structures. The antenna structures may form an antenna having first and second feeds at different locations. Transceiver circuitry for transmitting and receiving radio-frequency antenna signals may be mounted on one end of a printed circuit board. Transmission line structures may be used to convey signals between an opposing end of the printed circuit board and the transceiver circuitry. The printed circuit board may be coupled to an antenna feed structure formed from a flexible printed circuit using solder connections. The flexible printed circuit may have a bend and may be screwed to conductive electronic device housing structures using one or more screws at one or more respective antenna feed terminals. Electrical components such as an amplifier circuit and filter circuitry may be mounted on the flexible printed circuit. |
| US09705176B2 |
E-Z fit antenna base
An apparatus for securing an antenna to a surface by means of an antenna base and stand off with internal cable routing, which prevents any cables showing. With only one drilled hole at time of installation. With a device for holding an antenna vertical yet allowing said antenna to be lowered easily and quickly without tools or clumsy mechanisms attached to the antenna. A unique way to eliminate water penetration by means of clamping into the surface with gaskets and o-rings in a simple, relatively unskilled process. Therefore eliminating troublesome holes and sharp protrusions made by screws. While allowing free movement of the antenna for raising and lowering prepossess. A one hole, one nut installation that can be preformed by a single relatively unskilled person. Simple to manufacture with a minimal number of parts. With a beautiful streamlined appearance, that can be used for mounting any standard antenna. |
| US09705173B2 |
Waveguide structure and manufacturing method thereof
A waveguide structure includes a signal line and two static lines. The signal line is disposed between the static lines in a first direction. The static lines and the signal line are disposed parallel to one another. Each static line includes a first conductive pattern, a second conductive pattern, and a third conductive pattern. The first conductive pattern and the signal line are disposed on an identical plane of a dielectric layer. A thickness of the first conductive pattern is substantially equal to a thickness of the signal line. The second conductive pattern is disposed on the first conductive pattern. A width of the first conductive pattern is larger than a width of the second conductive pattern in the first direction. The third conductive pattern is disposed on the second conductive pattern. A width of the third conductive pattern is larger than the width of the second conductive pattern. |
| US09705169B2 |
Waveguide device, communication module, method of producing waveguide device, and electronic device
An electronic device includes a central control unit and a waveguide device. The waveguide device includes a high-frequency signal waveguide for transmitting a high-frequency signal emitted from a communication module having a communication function, and an attachment/detachment unit capable of attaching/detaching the communication module so that coupling between the high-frequency signal waveguide and the high-frequency signal is possible. The communication module includes a communication device and a transfer structure configured to cause the high-frequency signal emitted from the communication device to be transferred to the high-frequency signal waveguide of the waveguide device. |
| US09705168B2 |
Mobile energy carrier and energy store
A mobile energy carrier with which energy in the form of materials from zones distributed widely throughout the world, for example with a large amount of solar energy, wind energy or other CO2-neutral energy, for example the equator, can be transported to zones where there is a high energy requirement, for example Europe. |
| US09705163B2 |
Battery module
A battery module including a plurality of battery cells arranged in one direction; heat insulating members interposed between the plurality of battery cells so as to control heat generated in the battery cells; and a housing fixing the battery cells and the heat insulating members. |
| US09705162B2 |
Temperature control plate for a lithium ion battery
A temperature control plate for controlling the temperature of components. The temperature control plate is formed of a plastic-metal composite material which includes a metal fiber fabric that is surrounded by a thermoset plastic. A casing contains the components. The temperature control plate is configured for conducting heat away from temperature-exposed components. |
| US09705159B2 |
Method for fabricating a nonaqueous electrolyte secondary battery
A nonaqueous electrolyte secondary battery includes: a positive electrode 4 including a positive electrode current collector and a positive electrode mixture layer containing a positive electrode active material and a binder, the positive electrode mixture layer being provided on the positive electrode current collector; a negative electrode 5; a porous insulating layer 6 interposed between the positive electrode 4 and the negative electrode 5; and a nonaqueous electrolyte. The positive electrode 4 has a tensile extension percentage of equal to or higher than 3.0%. The positive electrode current collector is made of aluminum containing iron. In this manner, the tensile extension percentage of the positive electrode is increased without a decrease in capacity of the nonaqueous electrolyte secondary battery. Accordingly, even when the nonaqueous electrolyte secondary battery is destroyed by crush, occurrence of short-circuit in the nonaqueous electrolyte secondary battery can be suppressed. |
| US09705155B2 |
Electrode for solid electrolyte secondary battery, solid electrolyte secondary battery, and battery pack
According to one embodiment, a solid electrolyte secondary battery includes a positive electrode, a negative electrode, and a solid electrolyte layer, wherein at least one selected from the positive electrode and the negative electrode comprises active material particles, first solid electrolyte particles located the vicinity of a surface of the active material particles, and second solid electrolyte particles located a gap between the active material particles. A particle size ratio of a second solid electrolyte particle size D2 to a first solid electrolyte particle size D1 (D2/D1) satisfies the relation of 3 |
| US09705149B2 |
Nonaqueous electrolyte composition, nonaqueous electrolyte secondary battery, and method for manufacturing nonaqueous electrolyte secondary battery
A nonaqueous electrolyte composition includes an electrolyte salt, a nonaqueous solvent, a matrix polymer, and a ceramic powder, wherein the ceramic powder has an average particle size of 0.1 to 2.5 μm and a BET specific surface area of 0.5 to 11 m2/g. |
| US09705143B2 |
Electronic apparatus, control method and program thereof, and battery for operating electronic apparatus
An electronic apparatus using a fuel cell as at least one electric power source. The fuel cell has an electric power output unit for outputting an electric power through a chemical reaction between fuel gas and oxidant gas, a purge device for purging the electric power output unit and a purge control unit for issuing a purge instruction to the purge device. The electronic apparatus has a monitor unit for monitoring a consumption power, an operation state or a manipulated state of the electronic apparatus, and a purge permission unit for judging from an output of the monitor unit whether the purge control unit is permitted to issue the purge instruction, and outputting a judgment result to the purge control unit. |
| US09705136B2 |
High capacity energy storage
An energy storage device includes a nano-structured cathode. The cathode includes a conductive substrate, an underframe and an active layer. The underframe includes structures such as nano-filaments and/or aerogel. The active layer optionally includes a catalyst disposed within the active layer, the catalyst being configured to catalyze the dissociation of cathode active material. |
| US09705134B2 |
Organic negative electrode with chlorophyll and battery using the organic negative electrode
An organic negative electrode is provided in the present application. The organic negative electrode comprises a first element having conductive material, a second element formed by a high polymer solution and set on the first element, and a third element having chlorophyll and formed on the second element. A battery with said organic negative electrode is also provided. |
| US09705132B2 |
Olivine oxide-containing positive active material for rechargeable lithium battery with improved electro-conductivity, rate characteristics and capacity characteristics, method for manufacturing the same, and rechargeable lithium battery including the same
A rechargeable lithium battery with improved electro-conductivity and improved rate characteristics and capacity characteristics is disclosed. The battery includes a positive active material that includes an olivine-type composite oxide; and a metal or an alloy thereof adhered to a surface of the olivine-type composite oxide, wherein the metal or the alloy is selected from the group consisting of germanium (Ge), zinc (Zn), gallium (Ga), and a combination thereof. |
| US09705130B2 |
Antimony-based anode on aluminum current collector
An electrochemical battery is provided with an aluminum anode current collector and an antimony (Sb)-based electrochemically active material overlying the aluminum current collector. The Sb-based electrochemically active material may be pure antimony, Sb with other metal elements, or Sb with non-metal elements. For example, the Sb-based electrochemically active material may be one of the following: Sb binary or ternary alloys of sodium, silicon, tin, germanium, bismuth, selenium, tellurium, thallium, aluminum, gold, cadmium, mercury, cesium, gallium, titanium, lead, carbon, and combinations thereof. The aluminum current collector may additionally include a material such as magnesium, iron, nickel, titanium, and combinations thereof. In one aspect, the anode further composed of a coating interposed between the aluminum current collector and the Sb-based electrochemically active material. This coating may be a non-corrodible metal or a carbonaceous material. The cathode is may be composed of a number of different active materials including sodium-based Prussian Blue analogs. |
| US09705129B2 |
Process for producing an electrode for an electrochemical energy storage means and electrode
The subject matter of the present is a method for manufacturing an electrode for an electrochemical energy reservoir, in particular for a lithium-ion battery, encompassing the method steps of: a) furnishing a mixture of initial substances for formation of a lithium titanate; b) calcining the mixture of initial substances for formation of a lithium titanate; c) adding to the mixture of initial substances for formation of a lithium titanate, before and/or after calcination, a component encompassing sulfur and optionally lithium; and/or d) adding a pore former, before and/or after calcination, to the mixture of initial substances for formation of a lithium titanate; e) sintering the calcined product; and f) optionally removing the pore former from the calcined and optionally sintered product. Electrodes having a particularly defined pore structure can be generated with a method of this kind, thereby making possible particularly good capacity that is stable over the long term. A further subject is an electrode for use in a lithium-ion battery, as well as a lithium-ion battery. |
| US09705126B2 |
Battery electrode and use thereof
An objective is to reduce the sheet resistance and gas evolution in a battery electrode comprising a conductive intermediate layer capable of reducing or shutting off a current when overcharged. A battery electrode (12) comprises a conductive intermediate layer (123) being placed between a current collector (122) and an active layer (124) while comprising conductive particles (50) and a binder (60). The mass proportion of conductive particles (50) is equal to or larger than the mass proportion of the binder (60). Conductive particles (50) has a size distribution that exhibits a first peak with the maximum at a first particle diameter value and a second peak with the maximum at a second particle diameter value larger than the first particle diameter value. The intermediate layer (123) contains 10% to 60% by mass of conductive particles (52) having particle diameters that belong to the second peak. |
| US09705122B2 |
Battery terminal with unintended deformation prevention features
A battery terminal (1) includes a main body (10) with upper and lower plates (20U, 20L). The upper plate (20U) includes an upper mounting hole (23U), and upper plate fastening portions (26U, 27U). The lower plate (20L) includes a lower mounting hole (23L) and lower plate fastening portions (26L, 27L). A first receiving wall (41A) is connected to a first upper plate fastening portion (26U) and engages a first lower plate fastening portion (26L). A second receiving wall (41B) is connected to the second upper plate fastening portion (27U) and engages the second lower plate fastening portion (27L). A bracket (70) is mounted on the main body (10) and has a first pressing portion (73A) with a first tapered surface (74A) to contact the first receiving wall (41A) and a second pressing portion (73B) with a second tapered surface (74B) to contact the second receiving wall (41B). |
| US09705119B2 |
Energy storage device, energy storage apparatus, vehicle, and method for using energy storage device
An energy storage device comprises a positive electrode, a negative electrode, a separator arranged between the positive electrode and the negative electrode, and a nonaqueous electrolyte. The negative electrode has a negative substrate layer, and a negative composite layer arranged on the surface of the negative substrate layer. The separator has a separator substrate layer. The negative composite layer contains a non-graphitizable carbon having a particle diameter D50 of 2.0 μm or more and 6.0 μm or less. A corrected negative electrode density, which is defined as a value obtained by dividing, by a thickness of the separator substrate layer, a value obtained by multiplying a density of the negative composite layer by a thickness of the negative composite layer, is 1.2 (g/cm3) or more and 5.1 (g/cm3) or less. |
| US09705118B2 |
Method for preparing separator of battery
A method for preparing a separator of a battery comprises the steps of: respectively stretching a first polypropylene film and a second polypropylene film in one direction at −3-7° C., and keeping at 45-60° C. to provide a first polypropylene microporous film and a second polypropylene microporous film; perpendicularly compounding the films along the stretching direction to provide a polypropylene microporous composite film; and subjecting the polypropylene microporous composite film to hydrophilic treatment to provide the separator of the battery. The through micro-pores in the first and the second polypropylene film in the invention are attached and staggered to form tortuous pores, which greatly reduce the aperture of the through pores. Therefore, the passing of fine zinc particles and zincate can be blocked without influence on the passing of organic ions and the penetration of dendritic crystals is avoided. |
| US09705101B2 |
White organic light emitting device having emission area control layer separating emission areas of at least two emission layers
Disclosed is a white organic light emitting device in which a lifetime of a device is enhanced. The white organic light emitting device includes a first emission part between a first electrode and a second electrode and a second emission part on the first emission part. At least one among the first and second emission parts includes an emission area control layer. The white organic light emitting device includes a first emission part between a first electrode and a second electrode, a second emission part on the first emission part, and a third emission part on the second emission part. At least one among the first to third emission parts includes an emission area control layer. |
| US09705100B2 |
Organic electroluminescent element and method for manufacturing the same
Organic electroluminescent element capable of conveniently and precisely establishing the emission color of the element and capable of fine-adjusting the emission color in the white region. The organic electroluminescent element includes a pair of electrodes and a light-emitting layer provided between the electrodes and presents an emission color at the coordinate Ao (Xo, Yo) in the CIE 1931 chromaticity coordinate system. The light-emitting layer contains in the same layer, a white light emitting material A1 that presents an emission color at the coordinate A1 (x1, y1) in the CIE 1931 chromaticity coordinate system and a white light emitting material A2 that presents an emission color at the coordinate A2 (x2, y2) different from the coordinate A1(x1, y1) in the CIE 1931 chromaticity coordinate system. A distance LA1-A2 between the coordinates A1 (x1, y1) and A2 (x2, y2) in the CIE 1931 chromaticity coordinate system satisfies LA1-A2<0.13. |
| US09705097B2 |
Metal complex and light-emitting device containing the metal complex
A highly stable metal complex useful for the manufacture of a light-emitting device has an excellent lifetime property, particularly in a blue region, specifically a metal complex represented by Formula (1): wherein M is a metal atom; each R0 independently represents a divalent linking group; i and j each independently represent 0 or 1; RP1, RP2, RP3, RP4, RP5 and RP6 each independently represent a hydrogen atom and the like, with a proviso that at least one of RP1, RP2, RP3, RP4, RP5 and RP6 is a dendron; m is an integer of from 1 to 3, n is an integer of from 0 to 2, and m+n is 2 or 3; and the portion represented by Formula (2): represents a bidentate ligand; wherein Rx and Ry are an atom bonding to the metal atom M, and each independently represents a carbon atom and the like. |
| US09705094B2 |
Organic semiconductor compound, organic thin film including same, and electronic device including the organic thin film
An organic semiconductor compound represented by Chemical Formula 1 is highly fused due to fusion of greater than or equal to 4 rings, and has smooth intermolecular charge transfer due to relatively high planarity. |
| US09705092B2 |
Phosphorescent organic light emitting devices combined with hole transport material having high operating stability
An improved OLED includes an emitter layer disposed between a cathode and an anode where the emitter layer includes a host material and a phosphorescent emitter material. A first hole transport layer is disposed between the emitter layer and the anode and a second hole transport layer is disposed between the first hole transport layer and the anode. The first hole transport layer includes a first hole transport material that is a carbazole type compound and the second hole transport layer includes a second hole transport material that is different from the first hole transport material. The phosphorescent emitter material includes a phosphorescent organometallic compound that is a heteroleptic compound represented by the formula L2MX, LL′MX, LL′L″M, or LMXX′, wherein L, L′, L″, X, and X′ are inequivalent, bidentate ligands and M is a metal that forms octahedral complexes, wherein L, L′, and L″ are monoanionic inequivalent bidentate ligands coordinated to M through an sp2 hybridized carbon and a heteroatom. |
| US09705091B2 |
Aromatic heterocycle derivative and organic electroluminescent element using same
An aromatic heterocyclic derivative represented by the following formula (1)-1 or (1)-2: wherein in the formula (1)-1 or (1)-2, A is a substituted or unsubstituted nitrogen-containing heterocyclic group including 2 to 30 ring carbon atoms; B is a substituted or unsubstituted aromatic hydrocarbon group including 6 to 30 ring carbon atoms or a substituted or unsubstituted aromatic heterocyclic group including 2 to 30 ring carbon atoms; n is an integer of 2 or more; and Czs are independently an aromatic heterocyclic group including a predetermined structure. |
| US09705089B2 |
Organic light emitting element
Provided is an organic light emitting element having stable performance in the air. The organic light emitting element includes: an anode; a cathode; and an emission layer placed between the anode and the cathode, in which: the organic light emitting element further includes a first organic compound layer placed between the cathode and the emission layer, and a second organic compound layer placed between the emission layer and the first organic compound layer, and contacted with the first organic compound layer; the first organic compound layer contains a first organic compound; the second organic compound layer contains a second organic compound; and the first organic compound includes a viologen compound represented by the following general formula [1] and the second organic compound includes an organic compound different from the viologen compound. |
| US09705085B2 |
Method for manufacturing organic light-emitting device
The present application relates to a method of preparing an organic light emitting device. The method of preparing the organic light emitting device according to the present application includes: 1) forming a first electrode on a substrate; 2) forming an auxiliary electrode on at least a partial region on the first electrode; 3) forming an insulating layer on the auxiliary electrode, and forming an overhang structure, in which the insulating layer has a greater width than that of the auxiliary electrode; and 4) forming a second electrode on the first electrode and the insulating layer, so that the second electrode provided on the first electrode and the second electrode provided on the insulating layer are electrically short-circuited to each other. |
| US09705081B2 |
Electric field control element for phonons
Generally discussed herein are techniques for and systems and apparatuses configured to control phonons using an electric field. In one or more embodiments, an apparatus can include electrical contacts, two quantum dots embedded in a semiconductor such that when an electrical bias is applied to the electrical contacts, the electric field produced by the electrical bias is substantially parallel to an axis through the two quantum dots, and a phononic wave guide coupled to the semiconductor, the phononic wave guide configured to transport phonons therethrough. |
| US09705080B2 |
Forming self-aligned conductive lines for resistive random access memories
Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines. |
| US09705079B2 |
Tunable voltage margin access diodes
The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices. |
| US09705077B2 |
Spin torque MRAM fabrication using negative tone lithography and ion beam etching
A method for forming a memory device includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A planarizing layer is etched to establish a pillar of planarizing material defined by the island of photoresist material. A metal layer is etched to form a metal pillar having a diameter about the same as the pillar of planarizing material. A memory stack is etched to form a memory stack pillar having a diameter about the same as the metal pillar. A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar. |
| US09705076B2 |
Magnetoresistive element and manufacturing method of the same
According to one embodiment, there is provided a magnetoresistive element, including a lower electrode having crystallinity on a substrate, a first conductive layer including an amorphous state on the lower electrode, a buffer layer on the first conductive layer, and an MTJ element on the buffer layer. |
| US09705073B2 |
Magnetic memory element and magnetic memory
According to one embodiment, a magnetic memory element includes a first magnetic unit, a second magnetic unit, a nonmagnetic unit, and a controller. The second magnetic unit includes a first portion and a second portion. The first portion includes a first region and a second region. The controller performs a first operation and a second operation. In the first operation, the controller changes a direction of a magnetization of the first region by causing a first current to flow through the first portion in a first current direction. The first current has a first current value. In the second operation, the controller changes a direction of a magnetization of the second region by causing a second current to flow through the first portion in a second current direction. The second current has a second current value. The second current value is less than the first current value. |
| US09705072B2 |
Spin transfer torque tunneling magnetoresistive device having a laminated free layer with perpendicular magnetic anisotropy
A spin transfer torque magnetic junction includes a magnetic reference layer structure with magnetic anisotropy perpendicular to a substrate plane. A laminated magnetic free layer comprises at least three sublayers (e.g. sub-layers of CoFeB, CoPt, FePt, or CoPd) having magnetic anisotropy perpendicular to the substrate plane. Each such sublayer is separated from an adjacent one by a dusting layer (e.g. tantalum). An insulative barrier layer (e.g. MgO) is disposed between the laminated free layer and the magnetic reference layer structure. The spin transfer torque magnetic junction includes conductive base and top electrodes, and a current polarizing structure that has magnetic anisotropy parallel to the substrate plane. In certain embodiments, the current polarizing structure may also include a non-magnetic spacer layer (e.g. MgO, copper, etc). |
| US09705070B2 |
Ferroelectric thin film, method of manufacturing same and method of manufacturing piezoelectric element
In order to obtain a ferroelectric thin film that is formed to have a predetermined thickness on a substrate, that have satisfactory crystallization and that achieves a high piezoelectric property, a method of manufacturing such a ferroelectric thin film and a method of manufacturing a piezoelectric element having such a ferroelectric thin film, when a dielectric material of a perovskite structure is formed into a film on the substrate, a predetermined amount of additive is mixed with PZT, and the concentration of the additive mixed is varied in the thickness direction of the thin film. |
| US09705069B2 |
Sensor device, force detecting device, robot, electronic component conveying apparatus, electronic component inspecting apparatus, and component machining apparatus
A sensor device includes a charge output element including a plurality of piezoelectric bodies and an internal electrode formed between the piezoelectric bodies, a package that houses the charge output element, first conductive paste electrically connected to a plurality of the internal electrodes, and second conductive paste that electrically connects the first conductive paste and an output terminal and has a modulus of elasticity lower than a modulus of elasticity of the first conductive paste. A Young's modulus of the first conductive paste is equal to or higher than 3.4 GPa and equal to or lower than 5.0 GPa and a Young's modulus of the second conductive paste is equal to or higher than 0.1 GPa and equal to or lower than 0.2 GPa. |
| US09705067B2 |
Piezoelectric actuator
A piezoelectric fan includes a vibration sheet, piezoelectric elements, a reinforcing sheet bonded to at least one of principal surfaces of the piezoelectric element, a reinforcing sheet bonded to at least one of principal surfaces of the piezoelectric element, and a fixing sheet. The vibration sheet is fixed to the inside of an electronic device by the fixing sheet disposed at one end of the vibration sheet. The total thickness of the reinforcing sheets and a region of the vibration sheet adjacent to the piezoelectric elements is greater than the average thickness of a region of the vibration sheet in which the piezoelectric elements are not disposed. The piezoelectric elements are disposed symmetrically to the center plane of the thickness direction of the vibration sheet. The reinforcing sheets are disposed symmetrically to the center plane of the thickness direction of the vibration sheet. |
| US09705066B2 |
Head and liquid ejecting apparatus
A head includes a channel formation substrate having two piezoelectric actuator rows formed thereon, a driving circuit, and a driving circuit board which is provided with a first bump and a second bump, in which the first bump is provided on the outside of the piezoelectric actuator row, an adhesive layer is provided on both sides of the first bump and the second bump, a first through hole and a second through hole are provided on the driving circuit board, a first connection wiring and a second connection wiring are provided in the first through hole and the second through hole, and a first electrode of the piezoelectric actuator is electrically connected to a first connection wiring via the first bump and a second electrode is electrically connected to a second connection wiring via the second bump. |
| US09705064B2 |
Circuit assembly and method for controlling a piezoelectric transformer
A circuit assembly is used for controlling a piezoelectric transformer having an input capacitance in a first circuit branch. The circuit assembly also includes a second circuit branch for compensating for the input capacitance, preferably by means of a capacitive element, and a differential amplifier having two inputs. The first input is coupled to the first circuit branch and the second input is coupled to the second circuit branch. |
| US09705063B2 |
Sacrificial shorting straps for superconducting qubits
A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate. The first and second electrode paddles oppose one another. A sacrificial shorting strap is formed on the substrate. The sacrificial shorting strap connects the first electrode paddle and the second electrode paddle; The tunnel junction is formed connecting the first electrode paddle and the second electrode paddle, after forming the sacrificial shorting strap. The substrate is mounted on a portion of a quantum cavity. The portion of the quantum cavity is placed in a vacuum chamber. The sacrificial shorting strap is etched away in the vacuum chamber while the substrate is mounted to the portion of the quantum cavity, such that the sacrificial shorting strap no longer connects the first and second electrode paddles. The tunnel junction has been protected from electrostatic discharge by the sacrificial shorting strap. |
| US09705060B2 |
Thermoelectric materials
Disclosed is a thermoelectric conversion material having excellent performance. The thermoelectric material according to the present disclosure includes Cu and Se, and has a plurality of different crystal structures together, in which Cu atoms and Se atoms are arranged in the crystal, at a predetermined temperature. |
| US09705057B2 |
Method for producing a laser diode, mount and laser diode
In a method for producing a laser diode, a number of laser diodes are produced on a wafer. The wafer is broken down into wafer pieces, each wafer piece having a plurality of laser diodes being arranged side by side. One wafer piece is inserted into a first mount that includes a first covering element overlapping a front face of the wafer piece and shadowing a bottom area of the front face of the wafer piece. A minor layer is deposited on an unshadowed upper area of the wafer piece's front face. The wafer piece is inserted into a second mount, which includes a second covering element that shadows the minor layer of the upper area of the front face. An electrically conductive contact layer is deposited on an unshadowed bottom area of the wafer piece's front face. The wafer piece is subsequently broken down into individual laser diodes. |
| US09705055B2 |
Light emitting diodes
An LED comprises a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked in that order and located on a surface of the first electrode. The second electrode is electrically connected with the second semiconductor layer. A number of first three-dimensional nano-structures are located on a surface of the second semiconductor layer away from the active layer. The first three-dimensional nano-structures are linear protruding structures, a cross-section of each linear protruding structure is an arc. |
| US09705052B1 |
LED package structure
An LED package structure includes a substrate, a circuit layer and an insulating layer both disposed on the substrate, a light-emitting unit, and a reflective housing integrally formed with the insulating layer. The light-emitting unit includes an LED chip and a fluorescent body encapsulating the LED chip. The light-emitting unit is mounted on the insulating layer and the circuit layer. The fluorescent body of the light emitting unit is spaced apart from the circuit layer with a gap in a range of 3˜10 μm. The reflective housing is formed on the insulating layer and the circuit layer and is further filled within the gap. A top plane of the reflective housing arranged away from the substrate is lower than or equal to that of the light-emitting unit, and a distance between the two top planes is in a range of 0˜30 μm. |
| US09705051B2 |
Light emitting device
A light emitting device includes an epitaxial structure and a sheet-shaped wavelength converting layer. The sheet-shaped wavelength converting layer is disposed on the epitaxial structure and at least includes a first wavelength converting unit layer and a second wavelength converting unit layer. The first wavelength converting unit layer is disposed between the second wavelength converting unit layer and the epitaxial structure. An emission peak wavelength of the first wavelength converting unit layer is greater than an emission peak wavelength of the second wavelength converting unit layer. A full width half magnitude of the second wavelength converting unit layer is greater than a full width half magnitude of the first wavelength converting unit layer. |
| US09705050B2 |
Phosphor sheet, light-emitting device having the phosphor sheet and method of manufacturing the same
A light-emitting device includes a substrate including a first electrode and a second electrode, a light-emitting diode (LED) chip electrically connected to the first and the second electrodes, and a phosphor sheet disposed on an upper surface of the LED chip, a first transparent part disposed under the phosphor sheet, and a second transparent part disposed between the phosphor sheet and the LED chip. The first transparent part contacts the second transparent part. |
| US09705049B2 |
Phosphor, light-emitting apparatus including the same, and phosphor production method
A phosphor is provided which is represented by the general formula MxCeySi6-zBzN8+w. M is at least one element selected from the group consisting of La, Y, Tb and Lu. And w, x, y, and z satisfy 2.0 |
| US09705044B2 |
Semiconductor device and method for manufacturing same
To suppress or prevent erosion (decrease in film thickness), water absorption, or cracking of a DBR film surface in washing or etching treatment in a downstream process. The DBR film structure of a DBR film 7D includes a pair of or a plurality of pairs of a deposited SiO2 film and a deposited TiO2 film. Such a top layer of DBR film structures has hitherto been a deposited SiO2 film that provides high reflectance. In order to prevent erosion while maintaining high reflectance, the top layer herein is a high-refractive-index thin film (for example, a deposited TiO2 film) having a thickness in the range of 1 to 13 nm, and a tapered DBR end portion (a slope having a taper angle in the range of 15 to 45 degrees) is formed by vapor deposition in a lift-off process. The high-refractive-index thin film is overlaid with a reflective metal film 8D serving as a first layer. |
| US09705042B2 |
Micro assembled LED displays and lighting elements
The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 μm to 50 μm), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible. |
| US09705040B2 |
Light-emitting device
A light-emitting device includes: a substrate; a light-emitting structure including first and second nitride-based semiconductor layers on the substrate and an active layer between the first and second nitride-based semiconductor layers; an insulating layer on a top surface of the light-emitting structure; a protrusion on the insulating layer, a top surface of the protrusion being larger than a bottom surface thereof, the protrusion having a trapezoidal cross-section; a transparent conductive layer covering a top surface of the light-emitting structure, a top surface of the insulating layer, and the top surface of the protrusion and having a constant thickness along the top surface of the light-emitting structure, the top surface of the insulating layer, and the top surface of the protrusion; and an electrode covering at least one of inclined surfaces of the protrusion on the transparent conductive layer. |
| US09705038B2 |
Engineered substrate assemblies with epitaxial templates and related systems, methods, and devices
Engineered substrates having epitaxial templates for forming epitaxial semiconductor materials and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a first semiconductor material at a front surface of a donor substrate. The first semiconductor material is transferred to first handle substrate to define a first formation structure. A second formation structure is formed to further include a second semiconductor material homoepitaxial to the first formation structure. The method can further include transferring the first portion of the second formation structure to a second handle substrate such that a second portion of the second formation structure remains at the first handle substrate. |
| US09705037B2 |
Light emitting device, light emitting device package and lighting system including the same
Provided are a light emitting device, a light emitting device package and a lighting system including the same. The light emitting device (LED) comprises a substrate, a 5 second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer and a first electrode. The vertical distances between the first conductive type semiconductor layer and the second conductive type semiconductor layer are varied. |
| US09705036B2 |
Light emitting device and light emitting device package
Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer and a second conductive semiconductor layer on the active layer; a first electrode pad on the first conductive semiconductor layer; a second electrode pad on the second conductive semiconductor layer; and a current blocking pattern overlapping an edge of at least one of the first and second electrode pads. |
| US09705034B2 |
Light-emitting diode, method for manufacturing light-emitting diode, light-emitting diode lamp and illumination device
A light-emitting diode, a method of manufacturing the same, a lamp and an illumination device. A light-emitting diode (100) is provided with a compound semiconductor layer (10) including a light-emitting layer (24) provided on a substrate (1); an ohmic contact electrode (7) provided between the substrate and compound semiconductor layer; an ohmic electrode (11) provided on the side of the compound semiconductor layer opposite the substrate; a surface electrode (12) including a branch section (12b) provided so as to cover the surface of the ohmic electrode and a pad section (12a) coupled to the branch section; and a current-blocking portion (13) provided between an under-pad light-emitting layer (24a) arranged in an area of the light-emitting layer that overlaps the pad section (12a) and a light-emitting layer arranged in an area except the area that overlaps the pad section, to prevent current from being supplied to the under-pad light-emitting layer. |
| US09705030B2 |
UV LED with tunnel-injection layer
An ultraviolet (UV) light emitting structure, a UV light emitting device, and a method of making a UV light emitting structure or device, wherein the UV light emitting structure or device has an AlN or AlGaN injection layer with high aluminum content between the light emitting active region and the p-doped layers and wherein the injection layer has a thickness such that holes can tunnel from the p-side of the semiconductor-based ultraviolet light emitting diode structure through the injection layer in the active zone and also reducing leakage electrons out of the active zone. |
| US09705028B2 |
Light emitting diodes with N-polarity and associated methods of manufacturing
Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment. |
| US09705023B2 |
Avalanche photodiode and manufacturing method thereof
An avalanche photodiode includes a GeOI substrate; an I—Ge absorption layer configured to absorb an optical signal and generate a photo-generated carrier; a first p-type SiGe layer, a second p-type SiGe layer, a first SiGe layer, and a second SiGe layer, where a Si content in any one of the SiGe layers is less than or equal to 20%; a first SiO2 oxidation layer and a second SiO2 oxidation layer; a first taper type silicon Si waveguide layer and a second taper type silicon Si waveguide layer; a heavily-doped n-type silicon Si multiplication layer; and anode electrodes and a cathode electrode. |
| US09705020B2 |
Sheet and module structure
A module structure is provided, which includes a front sheet, a back sheet opposite the front sheet, and a solar cell disposed between the front sheet and the back sheet. A first encapsulate film is disposed between the solar cell and the front sheet, and a second encapsulate film disposed between the solar cell and the back sheet. One or both of the front sheet and the second sheet includes a support layer and a light conversion layer on the support layer, wherein the light conversion layer includes a fluorescent molecule and hydrogenated styrene elastomer resin. The light conversion layer is disposed between the support layer and the solar cell. |
| US09705019B2 |
Solar cell module and method of fabricating the same
Disclosed are a solar cell module and a method of fabricating the same. The solar cell module includes a back electrode layer disposed on a support substrate and having a first separation pattern, a light absorbing layer disposed on the back electrode layer and having a second separation pattern, and a plurality of solar cells disposed on the light absorbing layer and formed with a front electrode layer including an insulator. |
| US09705015B2 |
Component for the detection of electromagnetic radiation in a range of wavelengths and method for manufacturing such a component
A component intended for the detecting and/or the measuring of an electromagnetic radiation in a first range of wavelengths. The component includes a support including at least one first structure and a reception face in order to receive the electromagnetic radiation; an optical filter of the band-pass type in the first range of wavelengths arranged on the reception face of the support. The optical filter includes an adaptation zone covering the reception face of the support and with a refractive index less than 2; a first metal layer covering the adaptation zone and including regularly distributed through-holes. Each one of the through-holes contains a filling material. |
| US09705009B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer. |
| US09705008B2 |
Manufacturing method and structure of oxide semiconductor TFT substrate
The present invention provides a manufacturing method and a structure of an oxide semiconductor TFT substrate, in which an oxide conductor layer is used to define a channel of an oxide semiconductor TFT substrate. Since the oxide conductor layer is relatively thin and compared to the known techniques, the width of the channel can be made smaller and the width of the channel can be controlled precisely, the difficult of the manufacturing process of the oxide semiconductor TFT substrate can be reduced and the performance of the oxide semiconductor TFT substrate can be enhanced and the yield rate of manufacture can be increased. In a structure of an oxide semiconductor TFT substrate manufactured with the present invention, since the oxide conductor layer and the oxide semiconductor layer are similar in structural composition, excellent ohmic contact can be formed; the oxide conductor does not cause metal ion contamination in the oxide semiconductor layer; and the oxide conductor layer is transparent so as to help increase aperture ratio. |
| US09705006B2 |
Semiconductor device and manufacturing method of the same
A semiconductor device with high aperture ratio is provided. The semiconductor device includes a nitride insulating film, a transistor over the nitride insulating film, and a capacitor including a pair of electrodes over the nitride insulating film. An oxide semiconductor layer is used for a channel formation region of the transistor and one of the electrodes of the capacitor. A transparent conductive film is used for the other electrode of the capacitor. One electrode of the capacitor is in contact with the nitride insulating film, and the other electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor. |
| US09705004B2 |
Semiconductor device
A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface. |
| US09705001B2 |
Semiconductor device
The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented. |
| US09705000B2 |
III-V layers for n-type and p-type MOS source-drain contacts
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures. |
| US09704999B2 |
Thin film transistors with trench-defined nanoscale channel lengths
Thin film transistors (TFTs), including radiofrequency TFTs, with submicron-scale channel lengths and methods for making the TFTs are provided. The transistors include a trench cut into the layer of semiconductor that makes up the body of the transistors. Trench separates the source and drain regions and determines the channel length of the transistor. |
| US09704996B2 |
Semiconductor device
A semiconductor device comprises a semiconductor film and a gate electrode with a gate insulating film interposed therebetween, a conductive film, an insulating film over the gate electrode and the conductive film, and a gate wiring over the insulating film. The gate wiring extends across the conductive film. |
| US09704994B1 |
Different shallow trench isolation fill in fin and non-fin regions of finFET
A fin field effect transistor (finFET) and a method of fabricating the finFET. The method includes forming one or more fins above a substrate in a channel region, depositing a first insulating material conformally on the one or more fins and the substrate, and depositing a second insulating material over the first insulating material in non-channel regions adjacent to the channel region. A selective etch of the first insulating material in the channel region is performed to form a trench. The trench is filled with the second insulating material. The second insulating material in the channel region is adjacent to the first insulating material in the non-channel regions. |
| US09704993B2 |
Method of preventing epitaxy creeping under the spacer
After forming a gate spacer on each sidewall of a sacrificial gate structure, portions of each dielectric fin cap portion underneath the gate spacer is intentionally etched and undercut regions that are formed are filled and pinched off with a dielectric material of a conformal dielectric liner. Portions of the conformal dielectric liner in the undercut regions are not subject to the undercut during an epitaxial pre-clean process performed prior to forming an epitaxial source region and an epitaxial drain region on opposite sides of the sacrificial gate structure and remain in the undercut regions after forming the epitaxial source region and the epitaxial drain region. |
| US09704990B1 |
Vertical FET with strained channel
A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transistor. In one or more embodiments, an initial transistor structure is formed including a substrate, a dummy fin, and a hard mask. The dummy fin structure is narrowed. A channel is epitaxially grown on the dummy fin structure to create a strain on the channel. A first gate stack is formed over the channel. The hard mask and dummy fin are removed. A second gate stack is formed over the channel. Excess material is removed from the second gate stack. The formation of the transistor is finalized using a variety of techniques. |
| US09704989B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction. |
| US09704988B2 |
Dual work function buried gate type transistor and method for fabricating the same
A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; and a low resistance layer contacting the high work function liner layer and the low work function liner layer, and partially filling the trench. |
| US09704980B2 |
Insulated gate bipolar transistor and method for manufacturing same
An insulated gate bipolar transistor includes: a drift layer having a semiconductor substrate with N-type conductivity; a collector layer having P-type conductivity at a surface layer of the semiconductor substrate at a back surface side; and a field stop layer between the drift layer and the collector layer that has a higher impurity concentration than the drift layer. In a thickness direction of the semiconductor substrate, a lifetime control layer is arranged with a predetermined half value width by helium ion implantation; and the field stop layer is arranged with a predetermined half value width by hydrogen ion implantation. Further, a half value width region of the lifetime control layer and a half value width region of the field stop layer overlap each other. |
| US09704978B2 |
Integrated circuit heat dissipation using nanostructures
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer. |
| US09704977B2 |
Energy-filtered cold electron devices and methods
Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V. |
| US09704975B2 |
Method of manufacturing non volatile memory device
A non-volatile memory device includes a semiconductor substrate, a well region situated on the semiconductor substrate, a floating gate situated on the well region, a floating gate channel region, a control gate situated on both sides of the floating gate, a control gate channel region, and an ion implantation area for regulating a program threshold voltage integrally formed between an area underneath of the floating gate and the control gate and a foreside of the well region, wherein a doping concentration of the ion implantation area for regulating a program threshold voltage is greater than a doping concentration of the well region. Therefore, the non-volatile memory device of examples integrally forms an ion implantation area for regulating a program threshold voltage irrespective of a channel region of a floating gate and a control gate so as to guarantee durability of a non-volatile memory device. |
| US09704974B2 |
Process of manufacturing Fin-FET device
A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8. |
| US09704969B1 |
Fin semiconductor device having multiple gate width structures
A semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion. |
| US09704966B1 |
Fin-based RF diodes
Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region. |
| US09704956B2 |
Electrical devices with graphene on boron nitride
Methods of forming and resulting devices are described that include graphene devices on boron nitride. Selected methods of forming and resulting devices include graphene field effect transistors (GFETs) including boron nitride. |
| US09704954B2 |
Semiconductor device and a method for forming a semiconductor device
A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type. Further, the at least one strip-shaped cell compensation region is connected to a first electrode structure of the vertical electrical element arrangement. The at least one strip-shaped edge compensation region extends into the semiconductor substrate within an edge termination region of the semiconductor device and outside the cell region. Further, the at least one strip-shaped edge compensation region comprises the first conductivity type. The bridge structure electrically connects the at least one strip-shaped edge compensation region with the at least one strip-shaped cell compensation region within the edge termination region. |
| US09704952B2 |
Semiconductor device and method for manufacturing semiconductor device
An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with. |
| US09704950B2 |
Method to form SOI fins on a bulk substrate with suspended anchoring
A method of fabricating non-tilted, electrically isolated fins from a bulk substrate is provided. A plurality of semiconductor fins is formed extending upwards from a remaining portion of a bulk semiconductor substrate. Each semiconductor fin includes a hard mask cap. A sacrificial dielectric material portion is formed between each semiconductor fin, wherein each sacrificial dielectric material portion has a topmost surface that is vertically offset and located below a topmost surface of each hard mask cap. An anchoring structure having an opening is then formed atop each sacrificial dielectric material portion and each hard mask cap. Next, an entirety of each sacrificial dielectric material portion is removed by etching through the opening. An oxide layer is then formed within an upper portion of the remaining portion of the bulk semiconductor substrate, wherein a portion of the oxide layer extends beneath each semiconductor fin. Next, the anchoring structure is removed. |
| US09704948B2 |
Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof
A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. |
| US09704944B2 |
Three precision resistors of different sheet resistance at same level
An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks. |
| US09704943B2 |
Inductor structure and manufacturing method thereof
A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed. |
| US09704942B2 |
OLED lighting device with short tolerant structure
A first device that may include a short tolerant structure, and methods for fabricating embodiments of the first device, are provided. A first device may include a substrate and a plurality of OLED circuit elements disposed on the substrate. Each OLED circuit element may include a fuse that is adapted to open an electrical connection in response to an electrical short in the pixel. Each OLED circuit element may comprise a pixel that may include a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. Each of the OLED circuit elements may not be electrically connected in series with any other of the OLED circuit elements. |
| US09704937B2 |
Pixel structure having high aperture ratio and circuit
A pixel circuit and a pixel structure having high aperture ratio are provided. A first gate electrode, a layer including a first source electrode and a first drain electrode, and an etching stopper layer, a first semiconductor layer, and a gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor. A second gate electrode, a layer including a second source electrode and a second drain electrode, and an etching stopper layer, a second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor. A transparent electrode, a pixel electrode and a flat isolation layer sandwiched between the transparent electrode and the pixel electrode construct a transparent capacitor. |
| US09704930B2 |
OLED display panel and fabrication method thereof, and display device
An OLED display panel and a fabrication method thereof, and a display device are disclosed. The OLED display panel comprises: an array substrate and a package cover plate disposed opposite to each other, and an OLED layer which is formed on a surface of the array substrate facing the package cover plate and comprises a plurality of OLEDs. The OLED display panel further comprises: a first thin film packaging layer, covering the OLED layer and bonded to the array substrate; a color filter layer, provided on a side of the first thin film packaging layer facing the package cover plate; and a bonding adhesive, filled between the array substrate and the package cover plate to bond the array substrate and the package cover plate, the bonding adhesive covering the color filter layer and the first thin film packaging layer. |
| US09704928B2 |
Organic light emitting diode display
An organic light emitting diode display including a substrate, a thin film transistor on the substrate, a first electrode connected to the thin film transistor, a first layer on the first electrode, an emission layer on the first layer, a second layer on the emission layer, and a second electrode on the second layer. |
| US09704926B2 |
Organic light-emitting display apparatus
An organic light-emitting display apparatus is provided. The organic light-emitting display apparatus includes: a display substrate including a non-pixel area and a plurality of pixel areas including a first pixel and a second pixel having a shortest distance from the first pixel among pixels of the plurality of pixel areas; an encapsulation substrate facing the display substrate; and a spacer in the non-pixel area of the display substrate to maintain a space between the display substrate and the encapsulation substrate, wherein the spacer is between the first pixel and the second pixel. |
| US09704918B2 |
Semiconductor storage device
A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle. |
| US09704913B2 |
Manufacturing of an imager device and imager device
Embodiments related to the manufacturing of an imager device and an imager device are disclosed. Embodiments associated with methods of an imager device are also disclosed. |
| US09704908B2 |
Methods and applications of non-planar imaging arrays
System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface. |
| US09704906B2 |
Manufacturing method of semiconductor device and semiconductor device
The performance of a solid state image sensor which is formed by performing divided exposure that exposes the entire chip by a plurality of times of exposure and in which each of a plurality of pixels arranged in a pixel array portion has a plurality of photodiodes is improved.In the divided exposure performed when the solid state image sensor is manufactured, a dividing line that divides an exposure region is defined to be located between a first photodiode and a second photodiode aligned in a first direction in an active region in a pixel and is defined to be along a second direction perpendicular to the first direction. |
| US09704905B2 |
Solid-state image sensor and method of manufacturing the same
A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions. |
| US09704902B2 |
Backside illumination image sensor and image-capturing device
A backside illumination image sensor that includes a semiconductor substrate with a plurality of photoelectric conversion elements and a read circuit formed on a front surface side of the semiconductor substrate, and captures an image by outputting, via the read circuit, electrical signals generated as incident light having reached a back surface side of the semiconductor substrate is received at the photoelectric conversion elements includes: a light shielding film formed on a side where incident light enters the photoelectric conversion elements, with an opening formed therein in correspondence to each photoelectric conversion element; and an on-chip lens formed at a position set apart from the light shielding film by a predetermined distance in correspondence to each photoelectric conversion element. The light shielding film and an exit pupil plane of the image forming optical system achieve a conjugate relation to each other with regard to the on-chip lens. |
| US09704900B1 |
Systems and methods for forming microchannel plate (MCP) photodetector assemblies
A MCP photodetector assembly includes an anode plate including a plurality of electrical traces positioned thereon, a plurality of MCPs and a plurality of grid spacers. The MCPs are positioned between the grid spacers. The grid spacers have a grid spacer shape defining at least one aperture. A plurality of shims are positioned between the grid spacers and the MCPs so as to form a stack positioned on the anode plate. Each of the plurality of shims have a shim shape which is the same as the grid spacer shape such that each of the plurality of shims and each of the plurality of grid spacers overlap so as to define at least one MCP aperture. At least a portion of the plurality of MCPs are positioned within the MCP aperture. The shims are structured to electrically couple the MCPs to the anode plate. |
| US09704895B2 |
Display device and method for manufacturing the same
A display device and a method for manufacturing the same are provided. The display device includes a first substrate, a second substrate and a light curable sealant. The first substrate has a displaying area and a non-displaying area, in which the displaying area includes a pixel array, and the non-displaying area includes a driving circuit. The driving circuit includes at least a capacitor which is made of transparent conductive material. The second substrate has an opaque area. The light curable sealant is located between the first substrate and the second substrate. When viewing from a normal vector of the first substrate or the second substrate, the light curable sealant, the capacitor and the opaque area are at least partially overlapped with each other. |
| US09704893B2 |
Semiconductor device and electronic device
A low-power-consumption semiconductor device or the like is provided. Charge is accumulated in a node connected to a capacitor for a certain period to perform a current-voltage conversion. A gate of a transistor is connected to the node and the potential of one of a source and a drain of the transistor is changed gradually or continuously so that the potential is read when the transistor is turned on. The threshold voltage of the transistor and the capacitance value of the node are measured, so that the current-voltage conversion is performed more precisely. |
| US09704891B2 |
Thin film transistor having germanium thin film and manufacturing method thereof, array substrate, display device
A thin film transistor and manufacturing method thereof, an array substrate and a display device are provided. In the manufacturing method of the thin film transistor, manufacturing an active layer includes: forming a germanium thin film, and forming pattern of the active layer through a patterning process; conducting a topological treatment on the germanium thin film with a functionalized element, so as to obtain the active layer (4) with topological semiconductor characteristics. The resultant thin film transistor has a higher carrier mobility and a better performance. |
| US09704888B2 |
Display circuitry with reduced metal routing resistance
A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. An oxide liner may be formed on the passivation layer. A first low-k dielectric layer may be formed on the oxide liner. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. Thin-film transistor gate structures may be formed in the passivation layer. Conductive routing structures may be formed on the oxide liner, on the first low-k dielectric layer, and on the second low-k dielectric layer. The use of routing structures on the oxide liner reduces overall routing resistance and enables interlaced metal routing, which can help reduce the inactive border area outside the active display regions. |
| US09704886B2 |
Signal processing device
A plurality of writing transistors are connected in series, and a gate of a pass transistor, an input terminal of an inverter, or the like is directly or indirectly connected to each connection portion of the writing transistors. For example, a signal processing device includes first to third pass transistors, one semiconductor layer, and first to third wirings that overlap with the semiconductor layer and do not overlap with each other. Potentials of the first to third wirings can each change conductivities of at least portions of the semiconductor layer that overlap with the respective wirings. Gates of the first to third pass transistors are electrically connected to the semiconductor layer and are brought into a floating state depending on the conductivities of the portions of the semiconductor layer. Conduction between sources and drains of the pass transistors is controlled by potentials of the gates in the floating state. |
| US09704885B2 |
Pixel structure, array substrate and display device
A pixel structure, an array substrate and a display device. The pixel substrate comprises a first pixel electrode and a second pixel electrode arranged in a first direction, and a thin film transistor (TFT) disposed between the first pixel electrode and the second pixel electrode. The TFT includes a comb-shaped source, a comb-shaped first drain and a comb-shaped second drain; and a channel region of the TFT is defined by the comb-shaped source respectively and the comb-shaped first drain and the comb-shaped second drain. The channel region has a greater ratio of width to length, thus improving the driving capability of the TFT for driving the first pixel electrode and the second pixel electrode. |
| US09704884B2 |
Low temperature poly-silicon (LTPS) thin film transistor based liquid crystal display
An array substrate comprises a substrate, a common electrode formed on the substrate, a light shielding layer disposed on the common electrode, an insulating layer disposed on the light shielding layer and the common electrode, a poly-silicon layer, a gate insulating layer, a gate connected with the common electrode by a hole, a medium layer and a source drain. A method for manufacturing the array substrate comprises forming a transparent conductive layer and a first metallic layer on the substrate, forming patterned common electrode and light shielding layer by multiple steps of etching so that a process of photomask can be saved, and forming holes connecting with the common electrode and the gate by a photomask etching process, then manufacturing a medium layer and a source drain. The method adopts seven processes of photomask so that the process is simplified, and the cost is lowered. |
| US09704883B2 |
FETS and methods of forming FETS
A fin structure on a substrate can have a lower portion formed from the substrate, a middle portion, and an upper portion. The middle portion can include a dielectric region having a dielectric composition and a concentrated region of a first material. The first material can be an element of the dielectric composition. The concentrated region can be located at an interface of the middle portion and lower portion. The structure can also include isolation regions in the substrate on opposing sides of the fin. The structure can also include a gate structure over the upper portion of the fin that are exposed from the isolation regions. The gate structure can include a gate dielectric and gate material over the gate dielectric. The structure can also include source/drain regions extending laterally from the upper portion and the middle portion of the fin. |
| US09704882B2 |
Logic circuit, processing unit, electronic component, and electronic device
A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor. |
| US09704881B2 |
Semiconductor device with reduced poly spacing effect
A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate with a semiconductor layer, forming a first gate electrode over the semiconductor layer, forming a second gate electrode over the semiconductor layer, forming a mask layer between the first and second gate electrodes, etching a cavity into the semiconductor layer between the first and second gate electrodes using the mask layer as an etching mask, and forming a semiconductor material in the etched cavities. |
| US09704880B2 |
Systems and methods for a semiconductor structure having multiple semiconductor-device layers
A semiconductor structure having multiple semiconductor-device layers is provided. The semiconductor structure comprises a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide. The first semiconductor device layer comprises a patterned top surface. A blanket layer comprising insulator material is fabricated over the patterned surface. The semiconductor structure further comprises a second buried oxide bonded to the blanket layer and a second semiconductor device layer fabricated above the second buried oxide. |
| US09704879B2 |
Integrated circuitry components, switches, and memory cells
A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. Ferroelectric material is laterally between the graphene structure and at least one of the first and second electrically conductive structures. The first and second electrically conductive structures are configured to provide the switch into “on” and “off” states by application of an electric field across the graphene structure and the ferroelectric material. Other embodiments are disclosed, including components of integrated circuitry which may not be switches. |
| US09704873B2 |
Semiconductor device including memory cell array with transistors disposed in different active regions
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions. |
| US09704870B2 |
Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. |
| US09704865B2 |
Semiconductor devices having silicide and methods of manufacturing the same
Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area. |
| US09704862B2 |
Semiconductor devices and methods for manufacturing the same
According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view. |
| US09704858B2 |
Integrated device having multiple transistors
An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring. |
| US09704857B2 |
Semiconductor device and method of forming RF FEM with LC filter and IPD filter over substrate
A semiconductor device has a substrate and RF FEM formed over the substrate. The RF FEM includes an LC low-pass filter having an input coupled for receiving a transmit signal. A Tx/Rx switch has a first terminal coupled to an output of the LC filter. A diplexer has a first terminal coupled to a second terminal of the Tx/Rx switch and a second terminal for providing an RF signal. An IPD band-pass filter has an input coupled to a third terminal of the Tx/Rx switch and an output providing a receive signal. The LC filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The IPD filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The RF FEM substrate can be stacked over a semiconductor package containing an RF transceiver. |
| US09704855B2 |
Integration of active power device with passive components
A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device. |
| US09704849B2 |
Electrostatic discharge protection device structures and methods of manufacture
An ESD protection device comprising an SCR-type circuit including a PNP transistor and NPN transistor incorporates a Zener diode which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area of an N-type well. One or more diodes connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers between doped regions instead of gate oxide technology significantly reduces unwanted leakage currents. |
| US09704848B2 |
Electrostatic discharge devices and methods of manufacture
Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material. |
| US09704846B1 |
IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same
The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same. |
| US09704843B2 |
Integrated system and method of making the integrated system
A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. |
| US09704830B1 |
Semiconductor structure and method of making
A semiconductor structure in the form of a die comprises a silicon-containing core having a first surface, an opposite second surface and a peripheral edge surface. A circuit structure on the first surface is circumscribed by a peripheral crackstop structure which stops short of the second surface, thereby leaving an accessible portion of the peripheral edge surface free of the crackstop structure. One or more angular or orthogonal edge connector through-silicon conductive vias (“edge connector TSVs”) connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure. A method of making the structure includes forming the edge connector TSVs in the silicon wafer from which the semiconductor structures, i.e., dies, are cut. |
| US09704825B2 |
Chip packages and methods of manufacture thereof
Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip. |
| US09704824B2 |
Semiconductor device and method of forming embedded wafer level chip scale packages
A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less. |
| US09704819B1 |
Three dimensional fully molded power electronics module having a plurality of spacers for high power applications
A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate. |
| US09704810B2 |
Method and apparatus for determining an overlay error
A method of, and associated apparatuses for, determining an overlay error resultant from structure defects such as asymmetry. The method comprises measuring scattering properties of a first target comprising a first structure and a second structure, constructing a model of the first structure using the measured scattering properties, the model comprising a first model structure corresponding to the first structure, modifying the model by overlaying the first model structure with an intermediate model structure, further modifying the model by replacing the intermediate model structure with a second model structure, corresponding to the second structure, calculating a second defect-induced overlay error between the first model structure and the second model structure, the first and second model structures being overlaid with respect to each other in the further modified model and determining an overlay error in a second target using the calculated second defect-induced overlay error. |
| US09704809B2 |
Fan-out and heterogeneous packaging of electronic components
Aspects of the disclosure pertain to a packaging structure configured for providing heterogeneous packaging of electronic components and a process for making same. The packaging structure includes a carrier substrate having a plurality of cavities formed therein. The packaging structure further includes a first die and a second die. The first die is at least substantially contained within a first cavity included in the plurality of cavities. The second die is at least substantially contained within a second cavity included in the plurality of cavities. The first die is fabricated via a first fabrication technology, and the second die is fabricated via a second fabrication technology, the second fabrication technology being different than the first fabrication technology. The packaging structure also includes electrical interconnect circuitry connected to (e.g., for electrically connecting) the first die, the second die and/or the carrier substrate. |
| US09704808B2 |
Semiconductor device and wafer level package including such semiconductor device
An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad. |
| US09704807B2 |
Pattern placement error compensation layer
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer. |
| US09704805B2 |
Semiconductor device and manufacturing method of same
To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view. |
| US09704804B1 |
Oxidation resistant barrier metal process for semiconductor devices
An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm. |
| US09704801B1 |
Semiconductor memory device
A semiconductor memory device includes first and second stacked bodies and a conductive body. The first and second stacked bodies are disposed side by side on the conductive layer. The conductive body is provided between the first and second stacked bodies. The first and second stacked bodies each includes a plurality of electrode layers stacked on the conductive layer, a first insulating layer between adjacent electrode layers, a second insulating layer including a first portion and a second portion, and a semiconductor layer extending through the plurality of electrode layers. The first portion is provided between the first insulating layer and one of the adjacent electrode layers. The second portion is separated from the first portion and provided on an end surface of the first insulating layer facing the conductive body. The second insulating layer has a dielectric constant higher than a dielectric constant of the first insulating layer. |
| US09704797B2 |
Waterfall wire bonding
A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact. |
| US09704794B2 |
Electronic device with die being sunk in substrate
An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals. |
| US09704793B2 |
Substrate for electronic device and electronic device
A substrate includes a plurality of through electrodes. The through electrode has a nanocomposite structure including a nm-sized carbon nanotube and is a casting formed by using a via formed in the substrate as a mold. |
| US09704790B1 |
Method of fabricating a wafer level package
A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side, opposite to the first side. The RDL interposer comprises a first passivation layer, at least one dielectric layer on the first passivation layer, a metal layer in the at least one dielectric layer, a second passivation layer on the at least one dielectric layer, and a plurality of ball pads in the first passivation layer. At least one semiconductor die is mounted on the first side of the RDL interposer. A solder mask covers a lower surface of the first passivation layer and exposes the plurality of ball pads through a plurality of openings in the solder mask. An under-bump mettalization (UBM) layer is disposed at a bottom of each of the plurality of openings. A solder bump or solder ball is disposed on the UBM layer in each of the plurality of openings. |
| US09704788B2 |
Power overlay structure and method of making same
A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface. |
| US09704787B2 |
Compact single-die power semiconductor package
Disclosed is a power semiconductor package including a power transistor having a first power electrode and a gate electrode on its top surface and a second power electrode on its bottom surface. The second power electrode is configured for attachment to a partially etched leadframe segment, where the partially etched leadframe segment is attached to a substrate. A conductive clip is situated over the first power electrode and extends to the substrate in order to couple the first power electrode to the substrate without using a leadframe. |
| US09704782B2 |
Three-dimensional integrated circuit and TSV repairing method thereof
A three-dimensional (3D) integrated circuit (IC) includes a plurality of through silicon vias (TSVs) configured to provide paths via which digital signals are transmitted or received; at least one redundant TSV configured to provide a path via which a digital signal to be transmitted or received via a failed TSV with a defect among the plurality of TSVs is transmitted or received; a digital-to-analog converter (DAC) configured to convert a digital signal transmitted via the at least one redundant TSV into an analog signal; an analog-to-digital converter (ADC) configured to convert an analog signal received via the at least one redundant TSV into a digital signal; and a multilevel modulator configured to perform multilevel modulation on a digital signal transmitted via the at least one redundant TSV. |
| US09704780B2 |
Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias. |
| US09704774B2 |
Thermal management structure with integrated heat sink
A thermal management structure for a device is provided. The thermal management structure includes electroplated metal, which connects multiple contact regions for a first contact of a first type located on a first side of the device. The electroplated metal can form a bridge structure over a contact region for a second contact of a second type without contacting the second contact. The thermal management structure also can include a layer of insulating material located on the contact region of the second type, below the bridge structure. |
| US09704772B2 |
Chip package and method for forming the same
A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad. |
| US09704762B2 |
Application of in-line glass edge-inspection and alignment check in display manufacturing
Methods and apparatus for determining substrate integrity and alignment are described. Devices as described herein can include a transfer chamber, one or more process chambers, a loadlock chamber a first optical device, a second optical device and a radiation source positioned outside and above an opening for the loadlock chamber. Methods as described herein can include delivering a substrate to an opening in a process chamber, activating the optical device and the radiation source and capturing a plurality of images, extracting a substrate edge pattern from the plurality of images, comparing the substrate edge pattern to an expected edge pattern to determine a level of edge variance and adjusting or stopping a process if the level of edge variance is outside of an edge variation range. |
| US09704753B2 |
Minimizing shorting between FinFET epitaxial regions
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another. |
| US09704746B1 |
Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask
A method of forming a metallization layer by ASAP is provided. Embodiments include forming an ULK layer; forming a SAC SiN layer over the ULK layer; forming mandrels directly on the SAC SiN layer; cutting the mandrels; selectively etching the SAC SiN layer across the cut mandrels, forming first trenches; filling the first trenches with a metal oxide; forming a conformal metal oxide layer over the cut mandrels, the metal oxide, and the SAC SiN layer; removing horizontal portions of the conformal metal oxide layer over the cut mandrels and the SAC SiN layer; removing the cut mandrels; removing exposed portions of the SAC SiN layer and etching the underlying ULK layer, forming second trenches; and stripping a remainder of the metal oxide, conformal metal oxide layer, and SAC SiN layer. |
| US09704738B2 |
Bulk layer transfer wafer with multiple etch stop layers
Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, multiple etch stop layers are formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layers are incorporated into in a layer transfer process to enable very thin high quality active device layers of substantially uniform across-wafer thickness to be separated from bulk semiconductor wafers and bonded to handle wafers. As a result, these examples can produce high-performance and low-power semiconductor devices while avoiding the high cost of SOI wafers. |
| US09704736B2 |
Method of forming a flexible semiconductor layer and devices on a flexible carrier
A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate. |
| US09704731B2 |
Plasma processing apparatus and plasma processing method
A plasma processing method is provided for a plasma processing apparatus which includes a plurality of upstream-side expansion valves and a plurality of downstream-side expansion valves connected to respective refrigerant inlets and respective refrigerant outlets to adjust a flow rate or a pressure of a refrigerant flowing into the respective refrigerant inlets and a flow rate or a pressure of a refrigerant flowing out from the respective refrigerant outlets. The method includes adjusting openings of the upstream-side expansion valves and openings of the downstream-side expansion valves so that no change in flow rate of the refrigerant occurs in a plurality of refrigerant channels between the plurality of upstream-side expansion valves and the plurality of downstream-side expansion valves via the plurality of refrigerant channels in a refrigeration cycle allowing the refrigerant to flow therein. |
| US09704730B2 |
Substrate cleaning apparatus, substrate cleaning method and non-transitory storage medium
A cleaning liquid and a gas are discharged in sequence to a central portion of a substrate while the substrate is being rotated, and after nozzles that discharge them are moved to a peripheral edge side of the substrate, discharge of the cleaning liquid is switched to a second cleaning liquid nozzle set at a position deviated from a movement locus of the first cleaning liquid nozzle. Both of the nozzles are moved toward the peripheral edge side of the substrate while discharging the cleaning liquid and discharging the gas so that a difference between a distance from the discharge position of the second cleaning liquid nozzle to the central portion of the substrate and a distance from the discharge position of the gas nozzle to the central portion of the substrate gradually decreases. |
| US09704728B2 |
Substrate cleaning apparatus and substrate cleaning method
A substrate cleaning apparatus performs scrub cleaning of a surface of a substrate with an elongated cylindrical roll cleaning member. The substrate cleaning apparatus includes a roll holder for supporting the cleaning member and rotate the roll cleaning member, a vertical movement mechanism for vertically moving the roll holder so that the roll cleaning member applies a roll load to the substrate at the time of cleaning the substrate by actuation of an actuator having a regulating device, a load cell for measuring the roll load, and a controller for performing feedback control of the roll load through the regulating device based on the measured value of the load cell. The substrate cleaning apparatus further includes a monitor unit for monitoring whether an operation amount of the regulating device falls outside an allowable range of a preset reference value of an operation amount corresponding to a preset roll load. |
| US09704727B2 |
EFEM
An EFEM includes a housing 3 that constitutes a wafer transport chamber 9 that is substantially closed by connecting load ports 4 to an opening 31a provided on a wall 31, and connecting a processing apparatus 6; a wafer transport apparatus 2, and transports a wafer between the processing apparatus 6 and the FOUPs 7 mounted on the load ports 4; a gas delivery port 11; a gas suction port 12; a gas feedback path 10; and a FFU 13 that includes a filter 13b that is provided in the gas delivery port 11, and eliminates particles contained in the delivered gas, wherein the gas in the wafer transport chamber 9 is circulated by generating a downward gasflow in the wafer transport chamber 9 and feeding back the gas through the gas feedback path 10. |
| US09704724B2 |
Photosensitive resin composition and method for producing semiconductor device
Disclosed is a photosensitive resin composition which exhibits positive or negative photosensitivity and is used as a mask in an ion implantation step, the photosensitive resin composition including, as a resin, (A) a polysiloxane. The photosensitive resin composition of the present invention has high heat resistance and is capable of controlling a pattern shape, and also has excellent ion implantation mask performance, thus enabling application to a low-cost high-temperature ion implantation process. |
| US09704719B2 |
Systems and methods to mitigate nitride precipitates
A method of fabricating a semiconductor device is disclosed. A substrate having an oxide layer is provided. At least a portion of the oxide layer is removed and forms a nitride layer. The nitride layer is removed, leaving nitride precipitates. The nitride precipitates are removed using phosphoric acid. |
| US09704717B2 |
Electrochemical plating methods
An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles. |
| US09704716B2 |
Deposition of smooth metal nitride films
In one aspect, methods of forming smooth ternary metal nitride films, such as TixWyNz films, are provided. In some embodiments, the films are formed by an ALD process comprising multiple super-cycles, each super-cycle comprising two deposition sub-cycles. In one sub-cycle a metal nitride, such as TiN is deposited, for example from TiCl4 and NH3, and in the other sub-cycle an elemental metal, such as W, is deposited, for example from WF6 and Si2H6. The ratio of the numbers of each sub-cycle carried out within each super-cycle can be selected to achieve a film of the desired composition and having desired properties. |
| US09704713B1 |
Siloxanes, doped siloxanes, methods for their synthesis, compositions containing the same, and films formed therefrom
In one aspect, the present invention provides undoped and doped siloxanes, germoxanes, and silagermoxanes that are substantially free from carbon and other undesired contaminants. In a second aspect, the present invention provides methods for making such undoped and doped siloxanes, germoxanes, and silagermoxanes. In still another aspect, the present invention provides compositions comprising undoped and/or doped siloxanes, germoxanes, and silagermoxanes and a solvent, and methods for forming undoped and doped dielectric films from such compositions. Undoped and/or doped siloxane compositions as described advantageously provide undoped and/or doped dielectric precursor inks that may be employed in forming substantially carbon-free undoped and/or doped dielectric films. |
| US09704712B1 |
Method of making a semiconductor device formed by thermal annealing
According to various embodiments, a method may include: structuring a semiconductor region to form a structured surface of the semiconductor region; disposing a dopant in the semiconductor region; and activating the dopant at least partially by irradiating the structured surface at least partially with electromagnetic radiation having at least one discrete wavelength to heat the semiconductor region at least partially. |
| US09704710B2 |
Photocured product and method for producing the same
It is intended to provide a photocured product that is prepared using the photo-imprint method and has favorable pattern precision and improvement in pattern defects. The present invention provides a photocured product obtained by irradiating a coating film in contact with a mold with light, the photocured product containing a fluorine atom-containing surfactant, wherein of secondary ion signals obtained by the surface analysis of the photocured product based on time-of-flight secondary ion mass spectrometry, the intensity of a C2H5O+ ion signal is higher than that of a C3H7O+ ion signal. |
| US09704706B2 |
Ultra long lifetime gallium arsenide
A novel bulk GaAs with an increased carrier lifetime of at least 10 microseconds has been produced. This novel GaAs has many uses to improve optical and electrical devices. The method of producing the GaAs crystal involves using a technique called low pressure hydride vapor phase epitaxy (LP-HVPE). In this technique, a gas containing Ga (typically GaCl) is reacted with a gas containing As (typically AsH3) at the surface of a GaAs substrate. When grown under the proper conditions, the epitaxial, vapor grown GaAs crystal has ultra-long free carrier lifetimes of at least one order of magnitude greater than that of the previous art of 1 microsecond. This very long free carrier lifetime GaAs will be particularly useful as a semiconductor radiation detector material and is also expected to be useful for many other applications than include medical imaging, solar cells, diode lasers, and optical limiters and other applications. |
| US09704705B2 |
Parasitic channel mitigation via reaction with active species
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates. |
| US09704701B2 |
Method and device for ion mobility separations
Methods and devices for ion separations or manipulations in gas phase are disclosed. The device includes a single non-planar surface. Arrays of electrodes are coupled to the surface. A combination of RF and DC voltages are applied to the arrays of electrodes to create confining and driving fields that move ions through the device. The DC voltages are static DC voltages or time-dependent DC potentials or waveforms. |
| US09704699B2 |
Hybrid ion source and mass spectrometric device
In order to provide an ion source that can be easily switched with high sensitivity and in a short time, the ion source includes an ionization probe for spraying a sample, a heating chamber for heating and vaporizing a sample; and driving portions and for changing the distance between an outlet end (i.e., an end on the spray side) of the ionization probe and an inlet end (i.e., an end on the ionization probe side) of the heating chamber. The positions of the ionization probe and the heating chamber are controlled by the driving portions so that an ionization region that uses the ionization probe or an ionization region that uses the heating chamber is positioned near the ion inlet port of the mass spectrometer. |
| US09704695B2 |
Sputtering target and manufacturing method therefor
A backing plate integrated sputtering target includes a flange part having a Vicker's hardness (Hv) of 90 or more and a 0.2% yield stress of 6.98×107 N/m2 or more. Enhancing the mechanical strength of only the flange part of the target inhibits the target from being deformed during sputtering, and further, does not vary the original sputtering characteristics. Consequently, the target can form a thin film having excellent uniformity. This can improve the yield and the reliability of semiconductor products, which have been progressing in miniaturization and integration. |
| US09704691B2 |
Plasma generator
The invention relates to devices intended for treatment of materials in gas discharge plasma of low temperature, namely the induction plasma generator, placed inside the process volume (working chamber). The technical problem to be solved by the proposed invention is to increase the efficiency of the device; to improve the reliability of the device, increase purity of plasma environment and increase density of plasma generated; increase the life of device; reduce the level of noise; reduce the size of the device. |
| US09704684B2 |
Circuit breaker crossbar assembly
A circuit breaker crossbar assembly includes an elongate crossbar having a longitudinal axis, a first end and a second end, and having at least one support portion disposed therebetween. The crossbar is rotatable with respect to the longitudinal axis between a first rotational position and a second rotational position. The crossbar is coupleable to a plurality of moveable contacts of the circuit breaker. The support portion includes a first stop wall and a second stop wall defining a recess therebetween. A support structure is disposed in the recess, and comprises a support end pivotally coupled to the crossbar. The support structure has a first wall arranged to engage the first stop wall upon rotation of the crossbar toward the first rotational position, and a second wall arranged to engage the second stop wall upon rotation of the crossbar toward the second rotational position. |
| US09704677B2 |
Contact contacting structure
Provided is a contact contacting structure that reliably prevents the development of arc discharge in a simple configuration regardless of the magnitude of electric energy accumulated between a pair of contacts that are connected and disconnected. An intermediate contact body disposed continuously with a first contact along a movement path of a second contact is formed from material with higher electric resistivity than the first contact in a shape such that the cross sectional area of a transverse section perpendicular to the movement path is gradually decreased in a separating direction along the movement path. |
| US09704676B1 |
Slot motor assembly and arc plate assembly combination
A modular slot motor assembly and arc plate assembly combination for a circuit breaker is disclosed. The modular slot motor assembly is positioned proximate the arc plate assembly by lockingly securing it to a subcomponent housing in order to better provide an enhanced separation of the contact arms. During a short circuit event the modular slot motor assembly provides added acceleration to a moving contact arm. To protect the modular slot motor assembly from damage, an insulating casing is applied to at least a portion of the modular slot motor assembly. |
| US09704673B2 |
Circuit breaker
A circuit breaker includes a main body case, an operating handle having a base portion and a knob portion protruding outwardly through a handle window frame opened in a cover of the main body case; a first shutter arranged between the base portion of the operating handle and the handle window frame, and disposed on the base portion, the first shutter being formed with a loose-fit hole to loosely fit the knob portion therethrough; and a second shutter disposed on the first shutter to move along with the knob portion. At ON and OFF positions of the operating handle, the first shutter extends beyond a front/rear edge of the handle window frame in a front-back direction to close the handle window frame, and the second shutter extends beyond a front/rear edge of the loose-fit hole in the front-back direction to close the loose-fit hole. |
| US09704670B2 |
Keycaps having reduced thickness
An illuminated glass keycap having a glyph diffuser layer that may diffuse light through a glyph window opened in a background layer. The background layer may be opaque and the glyph window may be transparent. The keycap is adhered to a scissor mechanism positioned above electrical switch circuitry. Included within, below, or adjacent to the scissor mechanism may be one or more light sources positioned to emit light through the keycap, around the perimeter of the keycap, and/or through the background layer. |
| US09704669B2 |
Key input device for multifunction peripheral equipment
A key input device includes: keys each including a contact portion provided on its back surface; a holder holding the keys movably; a conductive member opposed to the holder; and a circuit board having a switch surface and switches arranged on the switch surface and each contactable with the contact portion of a corresponding key. The conductive member is interposed between the switch surface and the holder. The holder has first through holes, and the conductive member has second through holes. At least one of the contact portion and the switch is inserted in a corresponding one of the first through holes, and at least one of the contact portion and the switch is inserted in a corresponding one of the second through holes. |
| US09704667B2 |
Method of manufacturing a switch
A switch includes a case, fixed electrodes, a movable electrode and a pressing member. The fixed electrodes and the movable electrode are arranged inside the recess. The pressing member is arranged so as to cover at least a part of the recess, and displaces the movable electrode from the second position to the first position by a pressing force from the outside. The pressing member includes a first bent part and a second bent part, and a deforming part disposed therebetween. The deforming part is opposed to the movable electrode with a gap in a state where the movable electrode is in the second position. The deforming part is configured to be flexibly deformed toward the outside of the case in a state where the movable electrode is in the first position in which the fixed electrodes are in a conductive state. |
| US09704665B2 |
Backlit keyboard including reflective component
A backlit keyboard including a reflective component. The backlit keyboard may include a top case forming a top portion of an exterior surface of the keyboard. The backlit keyboard may further include a set of keys positioned within the top case and a membrane positioned below the set of keys. The backlit keyboard may further include a light guide positioned below the membrane and a light source positioned on a portion of the light guide. The light source may be configured to emit light coupled into the light guide and emit stray light not coupled into the light guide. The backlit keyboard may further include a bottom case attached to the top case and forming a bottom portion of the exterior surface of the keyboard. Additionally, the backlit keyboard may include a reflector positioned on an interior surface of the bottom case below the light guide and separated from the light guide by a gap. In some embodiments, the reflector may be configured to redirect the stray light towards the set of keys and provide structural support for the light guide. |
| US09704662B2 |
Switch system with high temperature operating plunger
A switch system includes a snap action switch, an operating plunger, and an actuator. The snap action switch is configured to move, with snap-action, from a first switch position to a second switch position. The operating plunger is disposed adjacent to the snap action switch and is coupled to selectively receive an actuating force. The operating plunger is configured, upon receipt of the actuating force, to retain the snap action switch in the first switch position. The operating plunger is further configured, upon removal of the actuating force, to allow the switch to move from the first switch position to the second switch position. The actuator contacts the operating plunger and is configured to selectively supply the actuating force to, and remove the actuating force from, the operating plunger. The operating plunger comprises a dielectric material having low thermal conductivity. |
| US09704659B2 |
Device for operating multiple functions in a motor vehicle
A device for operating multiple functions includes an operating element and a base. The base has side bearings and pins. The operating element has rotational axle end sections mounted in guide slots of the side bearings, respectively, to pivotably be mounted to the base about an axis of rotation to thereby be movable between at least two positions. At least one of the positions is assigned to a switching function. The operating element is further mounted to the base on a centered bearing between the side bearings of the base, and the operating element is supported on the pins of the base. |
| US09704644B2 |
Flexible circuit assembly and method therof
An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly. |
| US09704639B2 |
Non-planar inductive electrical elements in semiconductor package lead frame
The present disclosure relates to non-planar inductive electrical elements in semiconductor package lead frames. A non-planar inductive element is formed from a lead frame in a semiconductor package. The semiconductor package also includes at least one semiconductor die coupled to the lead frame. The non-planar inductive element could be formed by deforming portions of a patterned planar lead frame blank to form the non-planar inductive element in a deformed lead frame blank. The deformed lead frame blank and the at least one semiconductor die could then be packaged into a semiconductor package. A setting tool could be used to deform the lead frame blank. A configurable lead frame blank could be configurable into any of a variety of inductive elements, through interconnection of lead frame segments using wire bonds, for example. |
| US09704638B2 |
Output noise reducing device
One end of a bus bar for leading an output voltage output from a switching power supply to the outside is a connection terminal connected to an output end associated with the switching power supply, while the other end is an output terminal VO. A ferrite core has a through-hole through which the bus bar is disposed. Electromagnetic coupling from the switching power supply is suppressed between the output terminal VO of the bus bar and at least a part of the ferrite core on the output terminal VO side along the bus bar. In this way, electromagnetic coupling of a part of a choke coil including the ferrite core with the bus bar penetrating therethrough on the output terminal VO side and the switching power supply is suppressed, whereby propagation of noise to the output terminal VO is suppressed. |
| US09704636B2 |
Solenoid apparatus
An apparatus may include a ferromagnetic housing defining a housing cavity, an electrically-conductive coil disposed in the housing cavity and defining a coil cavity, a ferromagnetic core piece disposed in the coil cavity, a ferromagnetic pole piece comprising a first face in contact with the core piece and a projection extending from a second face of the pole piece opposite the first face, a flexible element defining an opening, where the projection is disposed within the opening and the flexible element is disposed between a portion of the projection and the first face of the pole piece, and a ferromagnetic armature coupled to the flexible element, where the flexible element is disposed between at least a portion of the armature and the first face of the pole piece. |
| US09704629B2 |
Coupled inductors with non-uniform winding terminal distributions
A coupled inductor includes a ladder magnetic core including two opposing rails extending in a lengthwise direction and joined by a plurality of rungs. The coupled inductor further includes a respective winding wound around each of the plurality of rungs. The plurality of rungs are divided into at least two groups of rungs, and a lengthwise separation distance between adjacent rungs in each group of rungs is less than a lengthwise separation distance between adjacent rungs of different groups of rungs. |
| US09704628B2 |
Ferrofluid-MWCNT hybrid nanocomposite in liquid state
A water based double surfacted ferrofluid having magnetite nanoparticles (2-18 nm) coated with primary and secondary surfactants is synthesized. On the other hand, an aqueous dispersion of functionalized MWCNT (diameter=14-18 μm, length=1.6-2.5 μm) is prepared by acid treatment. A hybrid solutions in different v/v ratios yielded stable dispersions having both nanoparticles and nanotubes in itself behave as one system. The synthesized hybrid fluid show magnetic response and self-sustained homogeneity of in presence of magnetic field. In addition, the hybrid fluids exhibits a long term sedimentation and magnetic stability which enables one to use them for various applications like MRI, EMI shielding, energy conversion etc. |
| US09704627B2 |
Metal powder core comprising copper powder, coil component, and fabrication method for metal powder core
In a metal powder core constructed from soft magnetic material powder and a coil component employing this, a configuration suitable for reduction of a core loss is provided. The metal powder core constructed from soft magnetic material powder is characterized in that Cu is dispersed among the soft magnetic material powder. It is characterized in that, preferably, the soft magnetic material powder is pulverized powder of soft magnetic alloy ribbon and that Cu is dispersed among the pulverized powder of soft magnetic alloy ribbon. Further, it is characterized in that, preferably, the soft magnetic alloy ribbon is a Fe-based nano crystal alloy ribbon or a Fe-based alloy ribbon showing a Fe-based nano crystalline structure and that the pulverized powder has a nano crystalline structure. |
| US09704625B2 |
Magnetic nanoparticles, bulk nanocomposite magnets, and production thereof
Provided herein are systems, methods, and compositions for magnetic nanoparticles and bulk nanocomposite magnets. |
| US09704616B2 |
Fluorinated elastomer composition and method for its production, molded product, cross-linked product, and covered electric wire
To provide a fluorinated elastomer composition which is excellent in flexibility and oil resistance to lubricant oil such as automatic transmission oil, is less susceptible to heat discoloration and is excellent also in moldability, and a molded product, cross-linked product and covered electric wire, using such a fluorinated elastomer composition. A fluorinated elastomer composition comprising a tetrafluoroethylene/propylene copolymer (a), an ethylene/tetrafluoroethylene copolymer (b) and an ethylene copolymer (c) containing epoxy groups, wherein the mass ratio [(a)/(b)] of the tetrafluoroethylene/propylene copolymer (a) to the ethylene/tetrafluoroethylene copolymer (b) is from 70/30 to 40/60, and the mass ratio [(b)/(c)] of the ethylene/tetrafluoroethylene copolymer (b) to the ethylene copolymer (c) containing epoxy groups is from 100/0.1 to 100/10. |
| US09704615B2 |
Shielded cable
A shielded cable comprising two insulated wire covered with first and second metal clad resin tapes each of which has a laminated metal layer and a resin layer. The first metal clad resin tape covers the circumference of the two insulated wires by open-wrapping and the second metal clad resin tape is spirally wrapped around the circumference of the first metal clad resin tape. The first and second metal clad resin tapes are disposed while the metal layers face each other and, in the portion where the second metal clad resin tape is overlapped by wrapping, the metal layer of the overlapped one second metal clad resin tape and the metal layer of the other second metal clad resin tape are in contact with the first metal clad resin tape. The shielded cable can prevent sharp signal attenuation in a high frequency region and is easy to bend and flexible. |
| US09704612B2 |
Composition of silver-conjugated compound composite
A composition of a silver-conjugated compound composite containing (1) a silver-conjugated compound composite containing a silver particle with a Feret diameter of 1,000 nm or less and a conjugated compound having a weight average molecular weight of 3.0×102 or more being adsorbed to the silver particles and (2) an ionic compound. The ionic compound may be a compound having a structure represented by the following Formula (hh-1): [Chem. 1] Mm′+aX′n′−b (hh-1) wherein Mm′+ represents a metal cation, X′n′− represents an anion, a and b each independently represent an integer of 1 or more, and when Mm′+ and X′n′− are each plurally present, they may be the same as or different from each other. |
| US09704606B2 |
Closure device for containers for transporting radioactive substances
A closure device for containers for transporting radioactive substances, having a first and a second component each with a comb-like portion, wherein the comb-like portions, with the closure device locked, has a bolt element passing through them. The bolt element has a head with an accommodating recess running transversally to the longitudinal axis of the bolt element, that one of the components has a through-opening which, with the bolt passing through the comb-like portions, is aligned with an accommodating recess. |
| US09704604B2 |
Nuclear fission reactor fuel assembly and system configured for controlled removal of a volatile fission product and heat released by a burn wave in a traveling wave nuclear fission reactor and method for same
A nuclear fission reactor fuel assembly and system configured for controlled removal of a volatile fission product and heat released by a burn wave in a traveling wave nuclear fission reactor and method for same. The fuel assembly comprises an enclosure adapted to enclose a porous nuclear fuel body having the volatile fission product therein. A fluid control subassembly is coupled to the enclosure and adapted to control removal of at least a portion of the volatile fission product from the porous nuclear fuel body. In addition, the fluid control subassembly is capable of circulating a heat removal fluid through the porous nuclear fuel body in order to remove heat generated by the nuclear fuel body. |
| US09704598B2 |
Use of in-field programmable fuses in the PCH dye
A processor has a limited set of guard bands that the processor uses, and when a certain amount of stress is accumulated as indicated by the cumulative stress counters (Seff), and the threshold for the current guard is about to be exceeded, the processor switches to the next wider guard band with this technique occurring until all the guard bands are used and end of life settings are reached. This data that can be stored in the FPFs, and in accordance with one exemplary embodiment, the guard band index itself is also stored in the FPFs and used to ensure the most accurate guard band is used by the processor/device. |
| US09704585B2 |
High voltage architecture for non-volatile memory
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL). |
| US09704583B2 |
Memory system and operating method thereof
A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane. |
| US09704579B1 |
Non-valatile semiconductor memory device and location based erasure methods
A non-volatile semiconductor memory device comprising a control circuit is provided, the control circuit performing a data erasure by applying predetermined erase voltages to predetermined blocks of a memory cell array including memory cells disposed on each intersection of a plurality of word lines and a plurality of bit lines, and the control circuit applying the erase voltages to the memory cells to erase data by applying word line voltages different to each other to even-numbered word lines and odd-numbered word lines of the memory cell array except to an edge part thereof, and by applying a voltage different to the word line voltages to the word line in the edge part of the memory cell array. |
| US09704577B2 |
Two transistor SONOS flash memory
A two transistor SONOS flash memory is disclosed. In one aspect, an apparatus, includes a control gate transistor having source and drain diffusions deposited in an N-well, a charge-trapping region formed on the N-well that overlaps the source and drain diffusions, and a control gate formed on the charge-trapping region. A channel region of the N-well between the source and drain diffusions is less than 90 nm in length. The apparatus also includes a select gate transistor having a select source diffusion deposited in the N-well. A drain side of the select gate transistor shares the source diffusion. A channel region of the N-well between the select source diffusion and the source diffusion also is less than 90 nm in length. |
| US09704574B1 |
Method and apparatus for pattern matching
Aspects of the disclosure provide an apparatus that includes a key generator, a first memory, a second memory, and a controller. The key generator is configured to generate a first search key, and one or more second search keys in response to a pattern. The first memory is configured to compare the first search key to a plurality of entries populated in the first memory, and determine an index of a matching entry to the first search key. The second memory is configured to respectively retrieve one or more exact match indexes of the one or more second search keys from one or more exact match pattern groups populated in the second memory. The controller is configured to select a search result for the pattern from among the index output from the first memory and the one or more exact match indexes output from the second memory. |
| US09704572B2 |
Sense amplifier with integrating capacitor and methods of operation
A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current. |
| US09704569B1 |
One time programmable read-only memory (ROM) in SOI CMOS
A programmable read-only-memory (ROM) cell and method of operating. The ROM cell comprises: a silicon-on-insulator (SOI) substrate having a bottom substrate layer, an insulating layer formed over said bottom substrate layer, and a top semiconductor substrate layer. A series coupled CMOS NFET and PFET device is formed at said semiconductor substrate layer, each NFET and PFET device having a respective gate, drain and source terminals, wherein a source terminal of said PFET device is electrically shorted to a drain terminal of said NFET device. An injected charge storage layer is provided at an interface between a channel formed beneath a gate terminal of said PFET and the insulating layer. The charge storage layer having trapped charge carriers representative of a logic bit value. The stored bit value is physically undetectable data. Biasing conditions established at the substrate and PFET device enable injection of charge carriers into the charge storage layer. |
| US09704568B1 |
Reducing SRAM power using strategic data pattern storage
Embodiments herein describe a SRAM that selectively flips received chunks of data from a high power state to a low power state before storing the chunks of data. The SRAM generates a flip bit for each of the data chunks stored in memory. The state of the flip bit varies depending on whether the corresponding data chunk was flipped before being stored in the SRAM. In one embodiment, the SRAM flips the bits in a data chunk before storing the bits only if all the bits are in the high power state. If so, the SRAM sets the flip bit for the data chunk to a first state and changes all the bits to the low power state before storing the data chunk. If not, the SRAM sets the flip bit to a second state and stores the data chunk without changing the states of the bits. |
| US09704564B2 |
SRAM structure with reduced capacitance and resistance
A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad. |
| US09704562B2 |
Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board, and electronic device
A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL. |
| US09704560B2 |
Memory component with staggered power-down exit
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path. |
| US09704559B2 |
Electronic device
An electronic device includes a mounting substrate, a first semiconductor component including a first semiconductor chip that operates in synchronization with a first clock signal and being mounted on a first semiconductor component mounting area of the mounting substrate, a second semiconductor component including a second semiconductor chip that operates in synchronization with a second clock signal and being mounted on a second semiconductor component mounting area of the mounting substrate, the second semiconductor component mounting area being next to the first semiconductor component mounting area, and a third semiconductor component including a third semiconductor chip that controls the first and second semiconductor chips and being mounted on a third semiconductor component mounting area of the mounting substrate, the third semiconductor component mounting area being next to the first and the second semiconductor component mounting areas. |
| US09704557B2 |
Method and apparatus for storing retention time profile information based on retention time and temperature
Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information. |
| US09704554B2 |
Sense amplifier with offset compensation
An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits. |
| US09704543B2 |
Channel controlling device for improving data reading efficiency
A channel controlling device includes: a multiplexing circuit coupled to a plurality of channels for selecting a specific channel from the channels to output a channel data according to a selecting signal, wherein the channels correspond to a plurality of predetermined digital numbers; a sorting circuit arranged to queue the predetermined digital numbers to form a plurality of queued digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selecting signal according to the plurality of queued digital numbers. |
| US09704540B2 |
Apparatuses and methods for parity determination using sensing circuitry
The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line. |
| US09704538B2 |
Environmentally controlling an enclosure
An apparatus and associated method contemplating a sealed container operably enclosing a storage device in an operating environment. A storage device controller is operably coupled to the storage device and configured to monitor operational parametric values of the storage device. An environment modifier is operably coupled to the container and configured to selectively alter the operating environment. A container controller is configured to selectively activate the environment modifier in response to parametric values from the storage device controller. |
| US09704531B2 |
Creating composition of content captured using plurality of electronic devices
Disclosed is a master electronic device configured to create a composition based on content captured using a plurality of client electronic devices. The master electronic device may include each of a communication module, a playback module, a touch-enabled input module and a composition module. The communication module may be configured to receive a plurality of content streams from a plurality of client electronic devices. The playback module may be configured to synchronously playback the plurality of content streams. The touch-enabled input module may be configured to receive one or more composition-inputs during the playback of the content. The one or more composition-inputs may correspond to a selection of a content stream to be included in a composition. Accordingly, the composition module may be configured to create the composition based on the one or more composition-inputs. |
| US09704522B2 |
Magnetic disk, method of track following on a magnetic disk, and method of writing a servo pattern in a dedicated servo layer of a magnetic disk
Magnetic disk, method of track following on a magnetic disk, and method of writing a servo pattern in a dedicated servo layer of a magnetic disk. The magnetic disk comprises a servo pattern in a dedicated servo layer of the magnetic disk, the servo pattern having a first burst A and a second burst B arranged to be within one period of a servo sample, each of burst A and burst B comprising DC+ and DC− magnetic bursts; wherein a center of the DC+/DC− bursts of burst B is shifted relative to the DC+/DC− bursts of burst A in a substantially radial direction of the magnetic disk. |
| US09704519B1 |
Sorting of HAMR read/write heads based on reader and writer widths
For each head in a collection of heat-assisted magnetic recording read/write heads, a reader width and a writer width is measured. A predicted life is determined for each head based on the respective reader width and writer width. In a first set of drives having relatively fewer heads per drive, a first subset of the heads having a higher value of the predicted life are used. In a second set of drives having relatively more heads per drive, a second subset of the heads having a lower value of the predicted life are used. |
| US09704517B2 |
Magnetoresistive sensor with SAF structure having amorphous alloy layer
A magnetoresistive (MR) sensor including a synthetic antiferromagnetic (SAF) structure that is magnetically coupled to a side shield element. The SAF structure includes at least one magnetic amorphous layer that is an alloy of a ferromagnetic material and a refractory material. The amorphous magnetic layer may be in contact with a non-magnetic layer and antiferromagnetically coupled to a layer in contact with an opposite surface of the non-magnetic layer. |
| US09704513B2 |
Magnetic head for perpendicular magnetic recording with a coil including a first winding portion of one turn and a second winding portion of less than one turn
A magnetic head includes a coil, a main pole and a return path section. The return path section is located on the trailing side relative to the main pole so that a space is defined between the main pole and itself. The coil includes a first winding portion and a second winding portion connected in series. The first winding portion extends to pass through the aforementioned space, and extends once around the entire perimeter of the main pole as viewed from the medium facing surface. The second winding portion does not pass through the aforementioned space, and surrounds only a part of the entire perimeter of the main pole as viewed from the medium facing surface. |
| US09704512B2 |
Electromagnetic data storage devices having improved magnetic structure
The present invention relates to an electromagnetic data storage device comprising a data storage medium including a magnetic material, and a write head including an electromagnetic element operable to generate a magnetic field that impinges on a selected portion of the magnetic material of the data storage medium adjacent the write head, so as to affect the magnetization direction of the selected portion of magnetic material. The electromagnetic element includes a magnetic structure including a matrix material, and a plurality of magnetic nanoparticles held in the matrix material. |
| US09704508B2 |
Drone detection and classification methods and apparatus
A system, method, and apparatus for drone detection and classification are disclosed. An example method includes receiving a sound signal in a microphone and recording, via a sound card, a digital sound sample of the sound signal, the digital sound sample having a predetermined duration. The method also includes processing, via a processor, the digital sound sample into a feature frequency spectrum. The method further includes applying, via the processor, broad spectrum matching to compare the feature frequency spectrum to at least one drone sound signature stored in a database, the at least one drone sound signature corresponding to a flight characteristic of a drone model. The method moreover includes, conditioned on matching the feature frequency spectrum to one of the drone sound signatures, transmitting, via the processor, an alert. |
| US09704504B2 |
Voice analysis device and voice analysis system
The voice analysis device includes: a voice information acquiring unit that acquires a voice signal generated by plural voice acquiring units disposed at different distances from a speaking section of a speaker and acquiring voice of the speaker; and an identification unit that identifies the speaker corresponding to the voice having been acquired, on the basis of intensities of respective peaks in a frequency spectrum of a first enhanced waveform and a frequency spectrum of a second enhanced waveform. The first enhanced waveform is a waveform where a voice signal of a predetermined target speaker has been enhanced, and the second enhanced waveform is a waveform where a voice signal of a speaker other than the target speaker has been enhanced. |
| US09704497B2 |
Method and system of audio power reduction and thermal mitigation using psychoacoustic techniques
Method of audio power reduction and thermal mitigation using psychoacoustic techniques starts by receiving a decoded audio signal in a reproduction system. Decoded audio signal is a signal that is decompressed and to be played back by a speaker. A masking curve is generated based on psychoacoustic models and the decoded audio signal. The masking curve is applied to the decoded audio signal to remove unheard frequencies and to generate a power-reduced audio signal. Other embodiments are also described. |
| US09704496B2 |
High frequency regeneration of an audio signal with phase adjustment
According to an aspect of the present invention, a method for reconstructing an audio signal having a baseband portion and a highband portion is disclosed. The method includes obtaining a decoded baseband audio signal by decoding an encoded audio signal and obtaining a plurality of subband signals by filtering the decoded baseband audio signal. The method further includes generating a high-frequency reconstructed signal by copying a number of consecutive subband signals of the plurality of subband signals and obtaining an envelope adjusted high-frequency signal. The method further includes generating a noise component based on a noise parameter. Finally, the method includes adjusting a phase of the high-frequency reconstructed signal and obtaining a time-domain reconstructed audio signal by combining the decoded baseband audio signal and the combined high-frequency signal to obtain a time-domain reconstructed audio signal. |
| US09704489B2 |
Portable acoustical unit for voice recognition
A portable acoustic unit is adapted for insertion into an electrical receptacle. The portable acoustic unit has an integrated microphone and a wireless network interface to an automation controller. The portable acoustic unit detects spoken voice commands from users in the vicinity of the electrical receptacle. The portable acoustic unit merely plugs into a conventional electrical outlet to provide an extremely simple means of voice control through a home or business. |
| US09704487B2 |
Speech recognition solution based on comparison of multiple different speech inputs
Disclosed herein are speech recognition apparatuses, vehicles having the speech recognition apparatuses, and methods for controlling vehicles. According to an aspect, a speech recognition apparatus includes a speech input unit configured to receive a speech command from a user, a communication unit configured to receive the result of processing for speech recognition acquired by at least one user terminal located near the user, and a controller configured to compare the result of processing for speech recognition acquired from the speech command received by the speech input unit to the result of processing for speech recognition acquired by the at least one user terminal, thus processing the speech command according to the result of the comparison. |
| US09704484B2 |
Speech recognition method and speech recognition device
Provided is a speech recognition device that executes a speech recognition method capable of improving speech recognition accuracy. The speech recognition device includes a trigger generation unit for generating a trigger signal on the basis of at least mouth movement and a speech recognition unit which extracts a sound signal on the basis of the trigger signal and starts speech recognition for speech in the extracted sound signal. When the trigger generation unit is generating a trigger signal solely on the basis of opening of the mouth, the trigger generation unit generates the trigger signal so as to precede the opening of the mouth by a predetermined period. Alternatively, when the trigger generation unit is generating a trigger signal on the basis of opening of the mouth and changes in eye orientation, the trigger generation unit generates the trigger signal from the moment any of the above occurs. |
| US09704482B2 |
Method and system for order-free spoken term detection
A method for spoken term detection, comprising generating a time-marked word list, wherein the time-marked word list is an output of an automatic speech recognition system, generating an index from the time-marked word list, wherein generating the index comprises creating a word loop weighted finite state transducer for each utterance, i, receiving a plurality of keyword queries, and searching the index for a plurality of keyword hits. |
| US09704478B1 |
Audio output masking for improved automatic speech recognition
Features are disclosed for filtering portions of an output audio signal in order to improve automatic speech recognition on an input signal which may include a representation of the output signal. A signal that includes audio content can be received, and a frequency or band of frequencies can be selected to be filtered from the signal. The frequency band may correspond to a desired frequency band for speech recognition. An input signal can be obtained comprising audio data corresponding to a user utterance and presentation of the output signal. Automatic speech recognition can be performed on the input signal. In some cases, an acoustic model trained for use with such frequency band filtering may be used to perform speech recognition. |
| US09704470B2 |
Method and apparatus for nonlinear compensation in an active noise control system
A self tuned apparatus (100) for active noise control includes a first transducer (105) and a second transducer (110), a noise controlling module (115), a power amplifier (120) and a first loudspeaker (125) and a second loudspeaker (130) coupled to the power amplifier (120). The noise controlling module (115) is coupled to the first transducer (105) and the second transducer (110). The power amplifier (120) is coupled to the noise controlling module (115). Particularly, the noise controlling module (115) employs at least one control algorithm. |
| US09704468B2 |
Apparatus and method for cancelling, reducing and modulating noise signal and for signal enhancing and signal proofing
The embodiments herein provide an apparatus and method for cancelling signal noise. According to one embodiment, an apparatus for cancelling signal noise has a sensor or receiver to capture the undesirable signals. A transducer converts the energy of the captured signals and modulates the captured undesirable signals. A signal inverting circuit is connected to the transducer to generate the inverse of the captured undesirable signals by inverting the amplitude of the undesirable signal while maintain the frequency at the same level. The generated inverse of the undesirable signal transmitted by a transmitter is received by a receiver and output through a speaker so that the output inverse of the undesirable signal is combined with the undesirable signal to produce a desired signal environment. |
| US09704466B2 |
Sound control apparatus
A sound control apparatus capable of improving the quality of the reproduction sound output from an electronic apparatus includes a sound control mat, and a support unit for supporting an electronic device having a speaker on the sound control mat. The sound control mat has a sound controlling structure configured to control the resonance of sound output from the speaker of the electronic apparatus when it is supported by the sound control mat. With this sound control apparatus, it is possible to enjoy a good tone directly output from a television, a stereo system or any other device having a small speaker without needing a special devising. |
| US09704463B2 |
Musical sound control apparatus, electric musical instrument, musical sound control method, and program storage medium
A musical sound control apparatus includes: an operator which as an index portion and changes values of a plurality of kinds of parameters by moving a position of the index portion; and a parameter control unit which executes processing of changing the values of the plurality of kinds of parameters according to an operated position as a position at which the index portion was moved from a standard position by an operation and processing of, when changing an assignment to the operator from a first parameter among the plurality of kinds of parameters to a second parameter among the plurality of kinds of parameters in a state in which the index portion is positioned at a position other than the standard position, setting a value of the second parameter assigned to a value which does not correspond to the position of the index portion. |
| US09704456B2 |
Keyboard positioning apparatus and method for retrofitting onto an existing piano assembly
An apparatus is provided comprising a frame; an enclosure; a keyboard including a plurality of black and white keys; the plurality of black and white keys each having a top surface and a bottom surface; the enclosure having a surface finish; the enclosure encloses the frame and the keyboard, such each top surface of the plurality of black and white keys is exposed; the frame comprises a first beam, a second beam, a first keyboard support bar, a second keyboard support bar, a third keyboard support bar, a first guide pin rail, a second guide pin rail, and a third guide pin rail; the first, second, and third keyboard supports bars are perpendicular to the first and second beams. |
| US09704455B2 |
Information display apparatus and information display method for superimposing additional information on an image
An information display apparatus includes an image pick-up unit configured to picking up an image, a display unit configured to display the image picked up by the image pick-up unit, a first correcting unit configured to correct the image picked up by the image pick-up unit to generate a first image, a second correcting unit configured to correct the image picked up by the image pick-up unit to generate a second image, a recognizing unit configured to recognize the second image generated by the second correcting unit, and a display control unit configured to display an additional information according to a result of the recognition performed by the recognizing unit with superimposing the additional information on the first image generated by the first correcting unit on the display unit. |
| US09704450B2 |
Driver IC for display panel
For each display line cycle, inputs to a pair of differential input terminals of a driving circuit are alternately switched in a cycle shorter than the display line cycle between a gradation voltage and a reference voltage. According to this, a chopping operation of switching polarities of offset appearing at the output of the driving circuit within one display line is performed for a plurality of times, and accordingly, a pixel of each display line maintains brightness information in which the chopping operation is already performed. As a result, although a frame cycle is lengthened, it is difficult to visually recognize a brightness difference caused by the offset. |
| US09704448B2 |
Array substrate, display panel and repairing method thereof
An array substrate, a display panel and a repairing method thereof are provided. In the array substrate, except the last gate line, both ends of each of the remaining gate lines are provided respectively with first leads connected to the gate line; in each group of gate integrated drive circuits, except a first level shift register, an input terminal of every other shift register is provided with a second lead connected to the input terminal; the first lead connected to one of the gate lines and the second lead connected to an input terminal of the shift register at the next level adjacent thereto have an overlapping area (A) therebetween, and are insulated from each other. |
| US09704446B2 |
Display device and driving method
An object is to reduce power consumption of a display device and to suppress deterioration of display quality. As a transistor provided for each pixel, a transistor including an oxide semiconductor layer is used. Note that off-state current of the transistor can be decreased when the oxide semiconductor layer is highly purified. Therefore, variation in the value of a data signal due to the off-state current of the transistor can be suppressed. That is, display deterioration (change) which occurs when writing frequency of the data signal to the pixel including the transistor is reduced (when a break period is lengthened) can be suppressed. In addition, flickers in display which generates when the frequency of an alternating-current driving signal supplied to a signal line in the break period is reduced can be suppressed. |
| US09704443B2 |
Liquid crystal display apparatus and display method
The liquid crystal display apparatus include a control unit controlling so that a first difference is smaller than a second difference, which the first difference is a difference between an intermediate value between any high gradation value and low gradation value and a gradation value in which a gradation value during a transition from the high gradation value to the low gradation value is equal to a gradation value during a transition from the low gradation value to the high gradation value, when a frame of the converted image is switched, and the second difference is a difference between the intermediate value between the high gradation value and the low gradation value and the gradation value in which the gradation value during the transition from the high gradation value to the low gradation value is equal to the gradation value during the transition from the low gradation value to the high gradation value, when the frame of the acquired image is switched. |
| US09704439B2 |
Automatic luminance correction system, optical gray scale measurement device and automatic luminance correction method
The present invention discloses an automatic luminance correction system, a optical gray scale measurement device and an automatic luminance correction method. The automatic luminance correction system comprises a computing unit for computing correction parameters according to the luminance-gray scale linear equation; a collecting unit for collecting the current luminance value; and a correcting unit for calculating the target luminance value according to the correction parameter and the current luminance value. By this way, the luminance of the lamp can be corrected automatically. |
| US09704436B2 |
Pixel circuit, driving method thereof, array substrate, and display device
The present invention provides a pixel circuit, a driving method thereof, an array substrate, and a display device. The pixel circuit comprises: a reset unit, configured to output a reference signal; a data writing unit, configured to output a data signal; a compensation unit, which is connected to the reset unit and the data writing unit as well as an output node, and receives a power voltage signal, and a light-emitting unit, which is connected to the output node and a cathode of a power supply and configured to emit light under the drive of the light emission drive signal in a light emission phase. |
| US09704434B2 |
Display device and driving method thereof
A display device includes a plurality of pixel rows including a plurality of pixel circuits; a scan driver supplying scan signals to the plurality of pixel rows; and a data driver supplying a data voltage to the plurality of pixel circuits of the plurality of pixel rows, wherein the plurality of pixel circuits each include driving transistors and an organic light emitting diode which emit light depending on a current flowing in the driving transistors, the plurality of pixel rows are divided into a plurality of blocks, each of the blocks including at least one pixel row, and a period for which the data voltage is written in the plurality of pixel circuits in a first block among the plurality of blocks and a period for which a threshold voltage of the driving transistors of the plurality of pixel circuits in a second block temporally close to the first block is compensated partially overlap each other. |
| US09704433B2 |
Organic light emitting display and method for driving the same
An organic light emitting display and associated method includes: initializing a first node of a storage capacitor, connected between the first node and a second node, with a first driving voltage that is provided from a first power terminal; applying a sustain voltage to the first node and placing a driving transistor in a diode connection state, wherein the driving transistor comprises a gate electrode connected to the second node, an electrode connected to the first power terminal, and another electrode connected to an organic light emitting diode through a third node; applying a data signal, provided from the data line through a switching transistor comprising a gate electrode connected to a scan line, an electrode connected to the data line, and another electrode connected to a first node, to the first node; and generating a compensation voltage by applying the first driving voltage to the first node. |
| US09704426B2 |
Display device, display system, and image processing circuit
A display device includes a first processing circuit mounted on a substrate separate from a translucent substrate constituting a display panel, and a second processing circuit mounted on the translucent substrate. The first and the second processing circuits receive the same image data. The first processing circuit includes a determination unit that uses color values of a plurality of pixels constituting an image based on the image data to determine an expansion coefficient value serving as a value for improving luminance of the image, and outputs the expansion coefficient value to the second processing circuit. The second processing circuit includes an expansion processing unit that uses the expansion coefficient value to provide expansion processing for improving the luminance of the image for the image based on the image data. |
| US09704424B2 |
Array substrate and display device
The disclosure relates to a field of display technology and discloses an array substrate and a display device, which improves quality of a displaying picture of a display device. The array substrate includes a plurality of pixel units arranged in an array, sub-pixels of each pixel unit are arranged in an ACBC-type array or a Delta-type array. The array substrate further includes a set of data lines configured to output data signals to the sub-pixels of the plurality of pixel units, the set of data lines each drives the sub-pixels of the same color. Compared with the prior art, the technical solution of the present disclosure avoids displaying errors caused by different corresponding relationship curves between the data output signals and the pixel grey levels for different colors, thereby improving quality of a displaying picture of a display device including the array substrate. |
| US09704422B2 |
Manipulation of color illumination using light diffusing fiber
An illuminated color displaying device having at least one light diffusing waveguide coupled to a plurality of different light sources emitting light at different wavelengths, to provide color modulation. |
| US09704419B2 |
Magnetic label-stock systems
A magnetic label stock tape that is less prone to damage during handling in labeling machines, storage, shipping, etc. |
| US09704417B2 |
Breadboard
A breadboard includes a panel having a top side and a bottom side, a first and second plurality of spaced component receiving openings extend through the top side surface and communicate with a larger first and second terminal receiving open surfaces extending from the bottom side surface which are configured to receive a first and second conductive terminals, respectively, and on a side of at least one of the first and second plurality of spaced openings in the top side surface is formed a raised surface and spanning a length approximate the larger terminal receiving open surfaces and parallel thereto and which forms part of the top side surface thereby defining a row of said plurality of spaced component receiving openings in which the conductive terminals lie. |
| US09704409B2 |
Piggybacking unmanned aerial vehicle
Various embodiments include methods for piggybacking an unmanned aerial vehicle (UAV) on a vehicle (e.g., motor vehicles and trailers coupled to motor vehicles) to reach a destination. Various embodiments may include determining whether to dock on a vehicle. One or more candidate vehicles may be identified for docking. Travel profile characteristics of the one or more candidate vehicles may be identified. A first vehicle may be selected from the one or more candidate vehicles based on one or more travel profile characteristics that assist the UAV in reaching the UAV destination. The UAV may dock with the first vehicle. While docked to the first vehicle the UAV may charge an onboard battery via an electrical connection in a docking structure or by harvesting energy in the wind caused by movement of the vehicle by configuring the UAV rotors to charge the battery. |
| US09704408B2 |
Flight control for flight-restricted regions
Systems, methods, and devices are provided for providing flight response to flight-restricted regions. The location of an unmanned aerial vehicle (UAV) may be compared with a location of a flight-restricted region. If needed a flight-response measure may be taken by the UAV to prevent the UAV from flying in a no-fly zone. Different flight-response measures may be taken based on the distance between the UAV and the flight-restricted region and the rules of a jurisdiction within which the UAV falls. |
| US09704398B2 |
Method and apparatus for enhancing driver situational awareness
Aspects of the subject disclosure may include, for example, determining, by a system comprising a processor, a driver profile according to a driver identity for a driver of a vehicle, selecting a driver-specific enforcement scenario for the vehicle according to the driver profile and traffic enforcement information that is associated with a vehicle location, and presenting an in-vehicle alert to convey the driver-specific enforcement scenario to the driver. Other embodiments are disclosed. |
| US09704395B2 |
Traffic sign determination device
A traffic sign determination device includes: an image recognition section which detects a first traffic regulation sign by performing an image recognition process on an image of an area in front of a vehicle picked up by an imaging section provided on the vehicle; a map information acquisition section which, using a position of the vehicle, acquires a road link, including a second road at the position of the vehicle, from a storage section; and a traffic sign determination section which, upon detection of a current first traffic regulation sign on a current road link, determines, until the vehicle passes an end point of the current road link, that a current traffic regulation sign to be notified to an occupant of the vehicle is the current first traffic regulation sign detected on the current road link. |
| US09704386B2 |
Mobile terminal and controlling method thereof
A mobile terminal and controlling method thereof are disclosed, by which a mobile terminal of a watch type or an external device can be remotely controlled. The present invention includes a display unit configured to display information, a wireless communication unit configured to communicate with an external device as a target of a remote control, a sensing unit configured to sense a motion of the mobile terminal and a variation according to a muscle movement of a part having the mobile terminal worn thereon, and a controller creating a control command for remotely controlling either the mobile terminal and the external device based on a sensing signal of the sensing unit. |
| US09704385B2 |
Implantable medical device adapted for radio frequency telemetry with frequency hopping
An implantable medical device has a broadband RF receiver operating within an RF band and having stored information of a characteristic receiver frequency representing the RF within the RF band at which the broadband RF receiver has sufficient receiver sensitivity. The stored information is retrieved in response to a message from an external communication device and is included in a response generated by the implantable medical device and transmitted to the communication device. The information enables the communication device to select its transmission frequency at a subsequent transmission instance to the relevant implantable medical device. The chances of successful reception at the subsequent transmission instance are thereby increased. |
| US09704383B2 |
Calibration system for equipment
A method of and apparatus for calibration of instrumentation and provision of calibration certificates comprises a portable field operable communication device and a remote information management device in wireless communication with one another, a data store comprising information related to each instrument to be calibrated, the portable device being operable to receive calibration requests from the management device and to facilitate input of data from an instrument the subject of calibration, and the management device being operable to facilitate generation of a calibration certificate or error report subsequent to receipt of input data from the portable device. |
| US09704382B2 |
Method for calculating error rate of alarm
Disclosed is a method for calculating an error rate of alarm that reports a failure of facility, calculating a true probability and a false probability of alarms generated for each time zone by a past failure record data and calculating the error rate of the alarm at a rate of the false probability to the true probability of the alarms generated for each time zone. |
| US09704381B2 |
Method for implementing quality alarms in an energy management system remote terminal
Methods for creating high quality alarms raise EMS operator awareness to abnormal conditions in monitored assets across multiple sites in a single EMS software platform. An embodiment includes steps for accessing an alarm designer software tool that contains a library of alarm definitions and the ability to create new alarm definitions, clone and edit existing alarm definitions, lock alarm definitions and delete alarm definitions. Applicable data is defined using channel attributes identifying which channel or channels associated with the multiple monitored sites are to be evaluated for alarming conditions. The alarm frequency, trigger conditions, pending open duration, close conditions, and pending close duration are also defined. Alarms can trigger upon one or more channels' behavior over periods of time and conditional relationships between multiple channels. Close conditions for an alarm can be, but are not required to be, the resolution of the trigger conditions. |
| US09704379B2 |
Sensor-containing electronic device button with optimized tactile characteristics
According to one embodiment, a displacement control member may be operationally coupled with a selectable button of a hazard detector so that axial depression of the selectable button effects pivoting of the selectable button and the displacement control member into contact with a switch of the hazard detector. The displacement control member may be coupled with the selectable button so that a ratio of a distance from the switch to a point of user contact with the selectable button and a distance from the switch to a pivot point of the displacement control member is similar regardless of where the user contacts the selectable button. The displacement control member may equalize a user input force that is required to activate the hazard detector's switch. |
| US09704373B2 |
Smart lug system
A device includes a device body that further includes a first attachment mechanism for attaching to another object, structure, or item of equipment. The device also includes wireless communication circuitry affixed to the device body, and one or more sensor components affixed to the device body, coupled to the wireless communication circuitry, and configured to sense environmental parameters associated with the device or with the object, structure or item of equipment. The device may further include powering circuitry, affixed to the device body, and configured to provide electrical power to the wireless communication circuitry and/or the one or more sensor components. The device may include a lug, connector or terminal. |
| US09704369B2 |
Autonomous fall monitor using an altimeter with opposed sensing ports
A system, a method and an apparatus for autonomous monitoring, detecting and tracking of at least one of movement and orientation of a body or portion of a body. The apparatus comprises a device configured to monitor the translational movement and/or rotational movement of the body; and an altimeter including at least one pair of opposed high sensitivity sensors configured to measure changes in height of the body. An alert condition is determined based on the translational and/or rotational movement of the body and changes in height of the body or portion of the body. The alert condition may comprise a hard fall event, a soft fall event, a susceptibility to a fall, or a near fall event. |
| US09704368B2 |
Personal alarm system
A personal alarm system includes an electronic device that may be carried. The electronic device has an output port. An alarm is removably coupled to the electronic device and the alarm may be manipulated. The alarm is selectively turned on such that the alarm emits an audible alarm. Thus, the alarm may alert an observer to provide assistance. The alarm is turned on when the alarm is removed from the electronic device. |
| US09704367B2 |
Clean-room monitoring device and method for monitoring clean-room
A clean-room monitoring device for monitoring the interior of a clean-room having a floor in which a removable cover such as a grating or a non-porous cover is disposed, includes: a monitoring camera which captures an image of the removable cover; a monitor which detects the existence of an opening exposed when the removable cover is removed, based on an image signal obtained from the monitoring camera, detects the presence of a workman approaching the opening if it is detected that the opening exists, and outputs a warning signal if the workman is detected; and a warning generator which receives the warning signal from monitor and issues a warning. |
| US09704364B2 |
Notification appliance
A notification appliance is disclosed. The notification appliance may be a strobe notification appliance, such as an LED strobe notification appliance. The notification appliance may be wall-mounted or ceiling-mounted. Further, the notification appliance may include an optic that is configured to shape the light output from the notification appliance. For example, in a wall-mount, the optic may be mounted off-axis of a plane defined by a back plate of the notification appliance. Further, the notification appliance may be composed of a back plate, a driver board, and a front housing, with the front housing being attached to one or both of the back plate and the driver board. Moreover, the notification appliance may be used with an adapter bracket, which may be used to connect the notification appliance with one or more types of junction boxes. |
| US09704363B2 |
Human identification detection system, method and device
The invention provides a system, device and method designed to detect, alert and identify unwanted entry into areas by intruders. The invention is also designed to prevent escape from secured facilities. If escape from such a secured facility is realized, the system will identify and mark the intruder or escapee for immediate or later capture by local and or federal law enforcement authorities. The system will accomplish this by mechanical, electronic and chemical means. The system is also designed to be a territory denial system. Although the system will accomplish its means by clandestine deployment, the unseen but known presence of the device will cause a profound psychological block to any would be intruder to a given area that it is deployed in. The devices are deployed below ground just below the surface as a non-lethal landmine and subterranean several feet below ground as an anti-tunneling device. |
| US09704361B1 |
Projecting content within an environment
A user may input one or more messages (e.g., visual or audio content) with respect to a projection device that is to project the messages to users within an environment. The user may additionally input related information that dictates a context and manner in which the messages are to be projected. The projection device may monitor the environment to identify users, events or actions within the environment. Upon detecting and identifying a particular user, the projection device may visually project the messages onto a surface within the environment, or may audibly output the messages within the environment, which may convey a particular meaning to that user. Optionally, the projection device may authenticate the user in order to determine that the user is the intended recipient of the messages. |
| US09704359B2 |
Lighting control for location finding
Lighting control for location finding is disclosed. According to embodiments, lighting control can include determining, using a group of location detectors, a first location of a computing device of a user, and obtaining, from the computing device, a target location for the user. Lighting control can include determining a path from the first location to the target location, the path determined at least based on a lighting system including a group of light emitting diode (LED) arrays, and indicating, using a first LED array of the group of LED arrays, a first portion of the path to the target location. The first portion of the path can be indicated by determining, for the plurality of LEDs of the first LED array, at least one LED that is visible at the first location, and outputting light from the at least one LED that is visible at the first location. |
| US09704357B2 |
Transport goods monitoring device
There is disclosed inter alia a transport goods monitoring device having a cover which is configured to cover transport goods received by a transport goods receptacle, the cover comprising a conductor arrangement, the conductor arrangement being in a first state when the cover is intact, the conductor arrangement being transformable from the first state into a second state by damage of the cover and the conductor arrangement being connectable to a detector which is configured to detect the existence of the second state. Furthermore, there is disclosed an arrangement comprising a transport goods receptacle which is configured to receive transport goods, and such a transport goods monitoring device, the cover of the transport goods monitoring device covering the transport goods receptacle and optionally transport goods arranged thereon. Also disclosed is the use of such a transport goods monitoring device for safeguarding transport goods received by a transport goods receptacle. |