| Document | Document Title |
|---|---|
| US09680739B2 |
Information transmission system, information communication apparatus, and information transmission apparatus
The information which can be acquired at the information communication apparatus side is treated as additional information. The information communication apparatus transmits the additional information and packet data, and the information transmission apparatus communicably connected to the information communication apparatus receives the packet data from the information communication apparatus. Conditions on the basis of the additional information to be received are stored in association with process instruction information. A condition which can be satisfied by the additional information received from the information communication apparatus is searched from among the stored conditions. If a condition which can be satisfied by the additional information is present, predetermined feature information of the packet data received from the information communication apparatus is extracted, the packet data is processed on the basis of the process instruction information associated with the condition, and the extracted feature information is stored in association with the process instruction information. |
| US09680738B2 |
Tracking prefixes of values associated with different rules to generate flows
Some embodiments provide a method for a forwarding element that forwards packets. The method receives a packet. The method consults a tree structure to generate a wildcard mask. The consulting includes traversing the tree structure by tracing a set of bits from the packet header and un-wildcarding the corresponding set of bits from the wildcard mask. The method identifies a matching rule for the packet. The method generates a flow based on the matching rule and the wildcard mask. The flow is used to process each other packet that matches each un-wildcarded bit of the flow. |
| US09680735B2 |
Method for operating a communication network, and network arrangement using prioritized data interchange
A method for operating a communication network, in particular an ethernet network is provided. Each network device coupled to the network has a first control device, a first switch device which is assigned to the first control device, a second control device, and a second switch device which is assigned to the second control device. Each switch device has a transmitting and receiving port for transmitting and receiving data via the communication network, a first internal transmitting and receiving port for transmitting and receiving data between the switch devices, and a second internal transmitting and receiving port for transmitting and receiving data to or from the control device. A respective data exchange at the first and second internal transmitting and receiving port is prioritized over a data exchange at the transmitting and receiving port for transmitting and receiving data via the communication network. |
| US09680734B1 |
Ingress protection for multipoint label switched paths
Techniques include providing ingress protection for multipoint label switched paths (LSPs). According to the techniques, a primary ingress node and a backup ingress node of a network are both configured to advertise a virtual node identifier of a virtual node as a next hop for a multicast source. Two or more egress nodes of the network then use the virtual node as a root node reachable through the primary ingress node to establish a multipoint LSP. After the multipoint LSP is established, the primary ingress node forwards traffic of the multicast source on the multipoint LSP. When failure occurs at the primary ingress node, the backup ingress node forwards the traffic of the multicast source along a backup path and onto the same multipoint LSP with the virtual node as the root node reachable through the backup ingress node. The techniques enable ingress protection without tearing down the multipoint LSP. |
| US09680727B2 |
Utilizing devices nearby
The present invention relates generally to network communications, and more particularly to detecting devices having communications issues on a network. The present invention provides for determining a communications performance status in relation to a device on a communications network experiencing a communications issue by identifying the device, locating reference devices in relation to the identified device, and determining where a performance deficiency may exist in relation to the identified device and the communications network. |
| US09680726B2 |
Adaptive and extensible universal schema for heterogeneous internet of things (IOT) devices
The disclosure is related to determining an association among Internet of Things (IoT) devices. A first IoT device receives an identifier of a second IoT device, obtains a schema of the second IoT device based on the identifier of the second IoT device, and determines whether or not there is an association between the first IoT device and the second IoT device based on a schema of the first IoT device and the schema of the second IoT device, where the schema of the first IoT device comprises schema elements and corresponding values of the first IoT device and the schema of the second IoT device comprises schema elements and corresponding values of the second IoT device. |
| US09680721B2 |
Ascertainment method and device
An ascertainment device includes a processor that executes a process. The process includes: acquiring addresses of a plurality of respective data processing devices and virtual network identification data associated with the plurality of respective data processing devices; ascertaining the identification data for each of the plural data processing devices based on the acquired virtual network identification data and addresses, association data, stored in a storage section, of addresses and data processing devices, and association data, stored in the storage section, of virtual network identification data and data processing devices; and ascertaining as a data processing device group configured redundantly with respect to execution of specific processing, any data processing devices out of the plural data processing devices with the same virtual network identification data and the same address as each other associated with the identification data of the data processing devices. |
| US09680719B2 |
Communication system, client terminal, and server
A batch request processing device that, when a response corresponding to a performance request issued by a GUI processing device is stored in a response storage device, outputs an output command for outputting the response to the GUI processing device, whereas when no response corresponding to the performance request is stored in the response storage device, commands a request pattern management device to predict a request which may be issued following the performance request and generate a request pattern which consists of the performance request and the predicted request, and generates a batch request including the request pattern generated by the request pattern management device. |
| US09680710B2 |
Systems and methods for processing packets tapped from a network using discovery protocol
A network device includes: one or more ports for tapping to a network; and a processing unit configured for receiving a first packet tapped from the network, wherein the first packet is received at a first network port of the network device; determining a first identity of a first network equipment associated with the first packet based on a discovery protocol; and associating the first identity of the first network equipment with a first identity of the first network port of the network device at which the first packet is received; and a non-transitory medium for storing the first identity of the first network equipment and the first identity of the first network port in association with each other. |
| US09680705B2 |
Competency based device access
A system and method are provided to enable competency based device access. The ability for a user to use a particular device may require demonstration of a skill or competency. Access control can be provided for a device to limit user access and to configure the device based upon the user competencies to utilize or perform functions on the device. The competency of the user can be defined in a competency checklist used to determine the skill or certifications of a user maintained by a resource management system. |
| US09680700B2 |
Device, system and method of configuring a radio transceiver
Some demonstrative embodiments include devices, systems and/or methods of configuring a radio transceiver. For example, some embodiment include a radio virtual machine (RVM) to configure a radio transceiver, the RVM including a radio processor to execute a first code configuring one or more transceiver functionalities independent of a configuration of the radio transceiver, and to generate a second code based on the configuration of the radio transceiver and the first code, wherein the second code is to be executed by the radio transceiver to configure the one or more transceiver functionalities for the radio transceiver. |
| US09680697B2 |
Dynamic product installation based on user feedback
A method and technique for utilizing user feedback of product installation disclosed. The technique includes: initiating an installation process to install an instance of a product, by an install module of the product, on a client computing system of a first user; interfacing, by the install module, with a server system to retrieve install path data defining a default installation path for the product, the default installation path based on previous feedback data received from at least a second user previously installing another instance of the product; modifying, by the install module, a default installation path for the product on the client computing system of the first user using the install path data; during the installation process, obtaining current feedback data from the first user corresponding to the installation process on the client computing system of the first user; and transmitting the current feedback data to the server system. |
| US09680696B1 |
Cloud migration and maintenance controls
Improved cloud migration tools are provided. In some embodiments, improved cloud migration tools may provide complex cloud migration analysis techniques for automated monitoring of aggregate compliance with cloud migration protocols, including user- and/or organizational defined architectural guidelines. In some embodiments, improved cloud migration tools may provide automated detective cloud controls, particularly in the management across multiple cloud computing platform accounts, virtual private clouds (VPCs), and/or a large numbers of numbers of resources. |
| US09680695B2 |
Facilitating mobility dimensioning via dynamic configuration of a switch
Dynamic grouping of cell site devices to network devices that include a group of baseband processing devices is facilitated. One method includes determining, by a device including a processor, respective load information for cell site devices of respective cell sites associated with a network; and determining, by the device, interference information associated with the cell site devices. The method also includes determining, by the device, configuration information of a switch device communicatively coupled between the cell site devices and network devices that include a group of baseband processing devices. The determining the configuration information is based on the respective load information of the cell site devices and the interference information associated with the cell site devices. |
| US09680690B2 |
Method, network adapter, host system, and network device for implementing network adapter offload function
A method, a network adapter, a host system, and a network device for implementing a network adapter offload function. If a data packet received by the network adapter or the host system is a data packet unknown to the network adapter, the data packet unknown to the network adapter is parsed, a new policy entry is generated, and the new policy entry is updated into the host policy table and the network adapter policy table. Therefore, for a packet that includes a new proprietary or standard protocol header Tag, only a functional module that parses the packet needs to be updated, so that the functional module is capable of processing such a packet and delivering a new policy entry to the host policy table and the network adapter policy table and the network adapter does not need to be changed. |
| US09680688B2 |
Near field information transmission
The present application provides a near field information transmission method and system, an information transmitting client, an information receiving client, and an information system. The information transmitting client transmits an acquisition request to the information system. The information transmitting client receives a random number that corresponds to the acquisition request and is returned by the information system. The random number corresponds to the information of said information transmitting client. The information transmitting client uses the random number as a service set identifier of a hotspot, and the service set identifier is broadcast through a beacon frame of a wireless communication protocol. The present techniques conduct near field information transmission conveniently and accurately. |
| US09680686B2 |
Media with pluggable codec methods
A container file containing a media file and a pluggable codec is sent to a receiver where the pluggable codec interfaces to a media player application, according to a predefined interface, to play the media file. A header in the container file indicates the locations of the media file and the pluggable codec. |
| US09680681B2 |
Transmission apparatus, reception apparatus, and communication system
A transmission apparatus that transmits a block signal including a plurality of data symbols, includes a data-symbol generation unit that generates data symbols; a fixed-symbol arrangement unit that arranges a data symbol and a fixed symbol such that the fixed symbol is inserted at a predetermined position in the block signal to generate a block symbol; an interpolation unit that performs interpolation processing on the block symbol; and a CP insertion unit that inserts a Cyclic Prefix into a signal on which the interpolation processing has been performed to generate the block signal. |
| US09680677B2 |
Weather band receiver
A weather band receiver, which may be part of an FM receiver, is disclosed. FSK-encoded data units in an alert packet transmission are detected using a quadrature matched filter circuit. At least one FSK-encoded data unit is captured from the alert packet transmission. Soft quantized bits are extracted from the FSK-encoded data units. The soft quantized bits are saved to memory and used to recover an alert message. Soft quantized bits from two or more FSK-encoded data units may be combined before recovering the alert message. |
| US09680667B2 |
Adaptive equalization circuit, digital coherent receiver, and adaptive equalization method
A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a setting value based on the second signal. |
| US09680665B2 |
Apparatus and method for dynamic hybrid routing in SDN networks to avoid congestion and balance loads under changing traffic load
Given a large number of traffic matrices, the matrices are divided into M clusters, where M is a relatively small number. A load-balancing apparatus is implemented as an application over the SDN controller. Such an application is executed to configure and reconfigure the switches to achieve near-optimal load balancing, even when the traffic load changes. For each cluster, a near-optimal explicit routing configuration is determined. The combination of explicit routing (cluster-specific) and destination-based routing (same for all clusters) is used to achieve near-optimal load balancing for each cluster. |
| US09680664B2 |
Using a multicast address as a tunnel remote gateway address in a layer 2 tunneling protocol access concentrator
A layer 2 tunneling protocol access concentrator (LAC) may receive an indication to set up a layer 2 tunneling protocol (L2TP) tunnel. The LAC may determine, based on the indication, a multicast address associated with initiating setup of the L2TP tunnel. The LAC may provide, to the multicast address, a request associated with initiating the L2TP tunnel. The request may be provided such that a plurality of L2TP network servers (LNSs) receives the request. The LAC may receive a set of responses to the request. The set of responses may be provided by a respective set of LNSs. The plurality of LNSs may include the respective set of LNSs. The LAC may select, based on the set of responses, a particular LNS, of the respective set of LNSs, with which to set up the L2TP tunnel. |
| US09680658B2 |
Collaborative group communication method involving a context aware call jockey
A system and method comprises establishing a group communication session between a first participant and a second participant. The method may include a dynamic point of control entity within the communication session. The dynamic point of control entity may be designated to operate in different roles and may have access to information regarding the conduct and participants of the call session, and also have control authority required in order to execute the designated role. |
| US09680656B2 |
Multipurpose wall outlet with USB port
A multipurpose wall outlet that provides electrical power via at least one standard electrical socket(s) and at least one USB port as well as providing a wired and wireless internet connection is disclosed. The multipurpose wall outlet has a housing in which is assembled at least one receiver for receiving a signal from a wireless data network, at least one processor for processing the signal from the wireless data network, at least one electrical socket, at least one USB port, at least one ethernet port, and a transmitter for transmitting a wireless data signal. |
| US09680655B2 |
Public-key certificate management system and method
Methods and systems for public-key certificate management comprise storing digital certificates in data structures that allow the manager to provide a verifiable proof about the validity status of a certificate. The certificates are stored in two data structures in a database. One data structure stores items in chronological order and is queried to establish a proof that a later snapshot of the database is an extension of an earlier snapshot of the database. Another data structure is ordered by user identifier and is queried to establish a proof that a given digital certificate is currently valid. |
| US09680653B1 |
Cipher message with authentication instruction
An instruction to perform ciphering and authentication is executed. The executing includes ciphering one set of data provided by the instruction to obtain ciphered data and placing the ciphered data in a designated location. It further includes authenticating an additional set of data provided by the instruction, in which the authenticating generates at least a part of a message authentication tag. The at least a part of the message authentication tag is stored in a selected location. |
| US09680652B2 |
Dynamic heterogeneous hashing functions in ranges of system memory addressing space
Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a general-purpose hashing function block that defines a default interleaving sequence for memory requests to alternately access the multiple memory channels and multiple specific-purpose hashing function blocks that define different interleaving sequences for the memory requests to alternately access the multiple memory channels. The MCU also includes a hashing-function selection block. The hashing-function selection block is operable to select one of the specific-purpose hashing function blocks or the general-purpose hashing function block for a current memory request in view of a requesting functional unit originating the current memory request. |
| US09680651B2 |
Secure data shredding in an imperfect data storage device
Apparatus and method for secure data shredding in an imperfect data storage device. In some embodiments, a hash function is applied to multi-bit random sequence to generate an output hash. A combinatorial logic function logically combines the output hash with a secret to provide an output value. The random string is processed into a plurality of secret shares which are stored in a first location in a non-volatile memory and the output value is stored in a different, second location of the memory. The secret is subsequently shredded by applying an erasure operation upon the secret shares in the first location of the memory. |
| US09680648B2 |
Securely recovering a computing device
A method and an apparatus for establishing an operating environment by certifying a code image received from a host over a communication link are described. The code image may be digitally signed through a central authority server. Certification of the code image may be determined by a fingerprint embedded within a secure storage area such as a read only memory (ROM) of the portable device based on a public key certification process. A certified code image may be assigned a hash signature to be stored in a storage of the portable device. An operating environment of the portable device may be established after executing the certified code. |
| US09680644B2 |
User authentication system and methods
Authenticating a user by presenting an authentication instruction to an individual via any computing device output interfaces, the authentication instruction selected from an identity authentication profile, receiving a response to the authentication instruction via any input methods supported by the computing device, the response including content provided through the performance of an action, determining a current action measurement for characteristics associated with the action, and a current content measurement for characteristics associated with the content, where the characteristics are associated with the authentication instruction, determining that each of the measurements matches a corresponding benchmark associated with the authentication instruction to within a predefined tolerance, where the benchmarks are selected from the identity authentication profile and performing the presenting, receiving, and determining steps for each of a predefined number of authentication instructions selected from the identity authentication profile, thereby authenticating the individual. |
| US09680637B2 |
Secure hashing device using multiple different SHA variants and related methods
A monolithic integrated circuit (IC) secure hashing device may include a memory, and a processor integrated with the memory. The processor may be configured to receive a message, and to process the message using a given secure hash algorithm (SHA) variant from among different SHA variants. The different SHA variants may be based upon corresponding different block sizes of bits. |
| US09680636B2 |
Transmission system, transmission method and encrypting apparatus
In a first transmission apparatus, a first head encryption unit encrypts a head block of first plain text using ID. A non-head encryption unit encrypts a block using the preceding encrypted block. A first transmitter transmits first encrypted data and the ID to a second transmission apparatus. A first holding unit holds end encrypted data. A second head encryption unit encrypts a head block of second plain text using the end encrypted data. A second transmitter transmits second encrypted data generated by the second head encryption unit to the second transmission apparatus. In the second transmission apparatus, a first decryption unit performs decryption on the first encrypted data using the ID. A second holding unit holds the end encrypted data included in the first encrypted data. A second decryption unit decrypts the second encrypted data using the end encrypted data. |
| US09680635B2 |
Sensor subassembly and method for sending a data signal
A sensor subassembly having a memory unit for storing a sensor data value from the sensor subassembly and a transmission unit for sending a data signal with information about the stored sensor data value to an external receiver at a data rate that is dependent on a clock frequency of a clock signal produced by the sensor subassembly. The transmission unit sends the data signal with the information about the stored sensor data value on the basis of a piece of trigger information in an externally received control signal. |
| US09680629B2 |
MAC cycle alignment method for neighboring network coordination
Representative implementations of devices and techniques provide communication between networked nodes while minimizing interference from neighbor network communication. Medium Access Control (MAC) cycles at the nodes may be aligned to MAC cycles of neighbor nodes and/or networks based on decoded timing information detected by the nodes. |
| US09680620B2 |
Signal transmission method and user equipment
Embodiments of the present disclosure provide a signal transmission method and a user equipment. The method includes: receiving, by a user equipment, an indication signal, where the indication signal is used to indicate resource numbers corresponding to physical resources occupied by one or more control signals, where a resource number corresponding to a physical resource includes time information and frequency information of the physical resource; allocating, by the user equipment according to the resource numbers, one or more physical resources corresponding to the one or more control signals; and sending, by the user equipment, the one or more control signals. With the embodiments of the present disclosure, energy consumption at a receive end can be saved. |
| US09680618B2 |
Local area optimized uplink control channel
A method for performing uplink signaling and data transmission between a terminal device and a network element is described. The method includes applying, during a transmission, at least one of TDM and FDM between a SRS, a control channel, a DRS and a data channel. Clustered sub carrier mapping is applied for the SRS and the control channel. The SRS is transmitted so as to function as a DRS for the control channel. The control channel and the data channel are transmitted during a same sub-frame. The method also includes receiving the SRS and receiving the control channel and the data channel during a same sub-frame. Control information and data are extracted from the control channel and the data channel. The SRS is used as a DRS for the control channel is included in the method. Apparatus and computer readable media are also described. |
| US09680614B2 |
Interleaving, modulation, and layer mapping in an LTE physical control channel
In described embodiments, a physical downlink control channel of a device operating in accordance with a 3GPP LTE standard is processed to provide interleaving, modulation and multi-layer mapping and pre-coding. A Resource Element Group interleaver applies interleaving to an input signal representing an input bitstream, and a modulator modulates the input signal. After interleaving and modulating the signal, a multi-layer mapper and pre-coder layer-maps and pre-codes the interleaved and modulated input signal into a plurality of different layers. |
| US09680607B2 |
Channel quality reporting in a multi-antenna wireless communication system
In MU-MIMO scenarios, a receiving node (1000) provides feedback on a feedback channel to a transmitting node (1300) regarding a channel between the receiving and the transmitting nodes (1000, 1300). To reduce signaling overhead, a feedback channel structure, such as HS-DPCCH, is used in which the fields that carry feedback information are specifically agreed upon. For example, in uplink signaling in a 4-branch MIMO, it was agreed that two codewords be used for CQI reporting and to send all information in one subframe. This structure is valid when the preferred rank is 2, 3, or 4. But when the preferred rank is 1, the CQI information does not fill the two codewords. To address such issues, mechanisms to map such feedback information to completely fill the allocated space are proposed. Padding and repeating are examples of such mechanisms. |
| US09680605B2 |
Method of offloading cyclic redundancy check on portions of a packet
A method and apparatus are provided for computing a CRC value for a data stream packet with a modified portion and an unmodified portion extending a distance to the end of the data stream packet by computing a first CRC value from the unmodified portion, computing a second CRC value from the modified portion, adjusting the second CRC value based on a shift length equal to the distance of the unmodified portion to compute a perspective shifted second CRC value by using a fixed number of distance lookup table operations, and generating an updated CRC value from the first CRC value and perspective shifted second CRC value, thereby avoiding recalculating a complete CRC value based on an entirety of the data stream packet. |
| US09680603B2 |
High-efficiency (HE) communication station and method for communicating longer duration OFDM symbols within 40 MHz and 80 MHz bandwidth
Embodiments of a high-efficiency (HE) communication station and method for HE communication in a wireless network are generally described herein. The HE communication station may communicate 4× longer-duration OFDM symbols on channel resources in accordance with an OFDMA technique. The channel resources may comprise one or more resource allocation units with each resource allocation unit having a predetermined number of data subcarriers. The station may also configure the resource allocation units in accordance with one of a plurality of subcarrier allocations for one of a plurality of interleaver configurations. The station may process the longer-duration OFDM symbols with a 512-point fast-Fourier Transform (FFT) for communication over a 40 MHz channel bandwidth comprising a 40 MHz resource allocation unit, and with a 1024-point FFT for communication over an 80 MHz channel bandwidth comprising either two 40 MHz resource allocation units or one 80 MHz resource allocation unit. |
| US09680601B2 |
Apparatus for transmitting a broadcast signal, apparatus for receiving a broadcast signal, and method for transmitting/receiving a broadcast signal using an apparatus for transmitting/receiving a broadcast signal
Disclosed is an apparatus for transmitting a broadcast signal, an apparatus for receiving a broadcast signal, and a method for transmitting/receiving a broadcast signal using an apparatus for transmitting/receiving broadcast signal. A method for transmitting a broadcast signal according to the present invention comprises the steps of: generating a first PLP which includes an IP stream having at least one service component; signaling IP-PLP mapping information for linking the IP stream and the PLP in binary form and generating a second PLP which includes the signaled binary information; performing FEC-encoding and bit-interleaving on the first and second PLPs; generating a transmission frame including the first and second bit-interleaved PLPs; and modulating the transmission frame and transmitting a broadcast signal including the modulated transmission frame, wherein the IP-PLP mapping information includes IP information for identifying the IP stream and PLP information for identifying the PLP. |
| US09680598B2 |
Wavelength division multiplexing optical transmission apparatus and wavelength division multiplexing optical transmission method
A wavelength division multiplexing optical transmission apparatus includes a plurality of polarization multiplexing optical modulation means, polarization-maintaining optical multiplexing means, and delay adjustment means. The polarization multiplexing optical modulation means generate a plurality of polarization multiplexed optical modulation signals having different wavelengths. The polarization-maintaining optical multiplexing means multiplexes the wavelengths of the polarization multiplexed optical modulation signals to generate a wavelength multiplexed optical signal (WDM). The delay adjustment means adjusts a delay such that light intensities of polarization multiplexed optical modulation signals having adjacent wavelengths in the wavelength multiplexed optical signal (WDM) vary inversely with respect to each other. |
| US09680595B2 |
Optical line terminal and optical network unit
An optical line terminal which includes an observing unit that observes information of any one or all of an arrival interval of frames, an instantaneous bandwidth under use of a flow, a queue length of a queue temporarily storing the frames, and a traffic type, and a stop determining unit that dynamically determines a sleep time to be a period in which a sleep state where partial functions of the ONU are stopped is maintained, on the basis of the information obtained by the observing unit. The ONU is entered into a sleep state, immediately after communication ends, after a predetermined waiting time passes from when the communication ends, or after a waiting time determined on the basis of the information passes from when the communication ends. |
| US09680594B2 |
Generating method and device, receiving method and device for dual-frequency constant envelope signal with four spreading signals
The application relates to a generating method and device, receiving method and device for a dual-frequency constant envelope multiplexed signal with four spreading signals. According to the method, the four baseband spreading signals s1(t), s2(t), s3(t), s4(t) can be modulated to a frequency f1 and a frequency f2 respectively, so as to generate the constant envelope multiplexed signal on a radio carrier frequency fp=(f1+f2)/2, where the signals s1(t) and s2(t) are modulated on the frequency f1 with carrier phases orthogonal to each other, the signals s3(t) and s4(t) are modulated on the frequency f2 with carrier phases orthogonal to each other, f1>f2. The method comprises: determining a power ratio allocated to the four baseband spreading signals s1(t), s2(t), s3(t), s4(t) in the constant envelope multiplexed signal; storing an additional phase lookup table, wherein the table includes additional phases of an in-phase baseband component I(t) and a quadrature-phase baseband component Q(t) of the constant envelope multiplexed signal; obtaining an additional phase θ of a segment of the current time by looking up the additional phase lookup table; and generating an in-phase baseband component I(t) and a quadrature-phase baseband component Q(t) of the constant envelope multiplexed signal, and generating the constant envelope multiplexed signal SRF(t) based on the obtained additional phase θ. |
| US09680592B1 |
Method and apparatus for estimating a gain of a channel in a wireless network
A physical layer (PHY) device including a first module and a second module. The first module is configured to (i) measure noise based on signals received by the PHY device via a channel and (ii) generate information in response to measuring the noise based on the signals received by the PHY device via the channel. The second module is configured to determine, depending on whether the first module is able to (i) measure the noise based on the signals received by the PHY device via the channel and (ii) generate the information in response to measuring the noise based on the signals received by the PHY device via the channel, whether to estimate a gain of the channel using (i) a first procedure to estimate the gain of the channel or (ii) a second procedure to estimate the gain of the channel. |
| US09680591B2 |
Method for reporting channel state information having reflected interference cancellation capability therein, and apparatus therefor
A method for reporting channel state information (CSI) having reflected interference cancellation capability therein in a wireless communication system is performed by a terminal and includes receiving interference configuration information indicating a first group of cells corresponding to targets for which interference cancellation capability is reflected, and scheduling information of a serving cell, from the serving cell, receiving a specific sequence transmitted from a second group of cells, determining whether to reflect the interference cancellation capability for the first group of cells and the second group of cells, using the interference configuration information, the scheduling information or the specific sequence, and transmitting CSI having reflected the interference cancellation capability therein, wherein the second group of cells correspond to candidate cells capable of reflecting the interference cancellation capability other than the indicated cells. |
| US09680588B2 |
OTN switching systems and methods using an SDN controller and match/action rules
A method and network include receiving a Time Division Multiplexing (TDM) connection; determining information in overhead of the TDM connection; and if match/action rules defined by controller exist for the TDM connection, establishing the TDM connection based on matching an associated rule in the match/action rules. A Software Defined Networking (SDN) controller is configured to receive a request from a node related to a new TDM connection in the network; determine one or more routes in the network for the new TDM connection; determine match/action rules for the one or more routes at associated nodes of the one or more nodes; if the one or more routes include at least two routes, determine a group table at associated nodes of the one or more nodes to distinguish between the at least two routes; and provide the match/action rules and the group table to the associated nodes. |
| US09680586B2 |
Method of controlling TDD Tx/Rx switching timing in cloud radio access network
Provided is a method for controlling a time division duplexing (TDD) Tx/Rx switching timing in a cloud radio access network (CRAN) that can finely control a switching timing between transmission and reception of TDD signals with an additional component added to a digital unit (DU) and a radio unit (RU) in the CRAN. |
| US09680583B2 |
Methods and apparatus to report reference media data to multiple data collection facilities
Methods and apparatus to report reference media data to multiple data collection facilities are disclosed. An example method includes determining whether a reference media monitoring site located in a first reference area is within a threshold distance of a second reference area. The reference media monitoring site providing reference media data to a first data collection facility associated with the first reference area. The example method also includes transmitting the reference media data to a second data collection facility associated with the second reference area if the reference media monitoring site is within the threshold distance. |
| US09680582B2 |
Method and apparatus for acquiring service area information in wireless communication system
Provided are a method and apparatus for acquiring multimedia broadcast/multicast service (MBMS) service area information in a wireless communication system. User equipment (UE) acquires at least one first MBMS service area identity (SAI), which corresponds to a MBMS service provided at a first carrier frequency, from system information broadcasted from a first cell. The UE acquires at least one second carrier frequency, which neighbors the first carrier frequency and at which the MBMS service is provided, and at least one second MBMS SAI, which corresponds to the MBMS service provided at the at least one second carrier frequency, from the system information. |
| US09680578B2 |
Soft packet combining for superposition coding
A method is proposed to enable a UE performing codeword level interference cancellation (CW-IC) to know whether an interfering transport block (TB) is a new transmission or retransmission. With this knowledge, the UE knows whether the soft channel bits stored in a soft buffer are to be discarded or combined with the soft channel bits newly obtained. |
| US09680577B2 |
Method for removing interference in wireless communication system and device for same
A method by which a base station supports the removal of an interference signal from a reception signal of a terminal in a wireless communication system, according to one embodiment of the present invention, comprises the steps of receiving, from the terminal, information on capability relating to carrier aggregation (CA); determining a method for removing an interference signal of the terminal, on the basis of information on the capability relating to the CA; and transmitting, to the terminal, the determined interference signal removal method, wherein the information on the capability relating to the CA can include a CA bandwidth class and MIMO capability of the terminal for the respective bands of respective band combinations for the CA. |
| US09680576B1 |
Photonic frequency converting transceiver and related methods
A photonic frequency converting transceiver may include a laser, and a downconverter receiver branch including a first optical modulator optically coupled to the laser and configured to modulate laser light based upon an RF input signal and a first optical bandpass filter. An upconverter transmitter branch may include a second optical modulator optically coupled to the laser and configured to modulate laser light based upon an intermediate frequency input signal, and a second optical bandpass filter. A shared local oscillator branch may include a third optical modulator optically coupled to the laser and configured to modulate laser light based upon a local oscillator signal, and a third optical bandpass filter. The transceiver may further include photodetectors optically coupled to the optical bandpass filters to generate a downconverted intermediate frequency output signal and an upconverted RF output signal. |
| US09680571B2 |
Techniques for selective use of light-sensing devices in light-based communication
Techniques are disclosed for selective use of light-sensing devices in light-based communication (LCom). In accordance with some embodiments, the disclosed techniques can be used, for example, in determining how and when to utilize a given light-sensitive device, such as a camera or an ambient light sensor, of a receiver device for purposes of detecting the pulsing light of LCom signals transmitted by an LCom-enabled luminaire. In accordance with some embodiments, determination of whether to utilize only a camera, only an ambient light sensor, or a combination thereof in gathering LCom data may be based, in part or in whole, on factors including time, location, and/or context. In some cases, improvements in system resource usage may be realized using the disclosed techniques. |
| US09680567B2 |
Fault localization and fiber security in optical transponders
Designs, methods, and applications for fault localization and fiber security in optical transponders is described. In one embodiment a two-way time transfer protocol or other suitable method for synchronizing clocks between distant transponders is used. The clock synchronized transponders have digital signal processing to continually detect high precision time-histories of physical layer attributes in the transmission between the two transponders. Physical layer attributes can include: state-of-polarization changes, changes in polarization-mode-dispersion, change in propagation delay, changes or loss-of-light, changes in OSNR, changes in BER between the two nodes. By recording these physical layer changes and time-stamping them information on the magnitude and estimated location of the changes can be inferred by from the time records. In one aspect the method may be used in a distributed optical sensor for monitoring trespassing events that are a risk to fiber security of an optical transmission link. |
| US09680566B2 |
Transmission apparatus and method
A transmission apparatus includes: a storage unit to store a table in which a wavelength terminated by each of transmission apparatuses is associated with each of the transmission apparatuses; a transmission unit to transmit a message including failure information to other transmission apparatus when a failure occurs; a switch controller to determine whether its own transmission apparatus is a last transmission apparatus that terminates the wavelength among transmission apparatuses that are present on a path up to a link where the failure, based on the table, when receiving the message from other transmission apparatus, and to perform a control of switching a transmission direction of a signal having the wavelength when the switch controller determines that its own transmission apparatus is the last transmission apparatus to terminate the wavelength; and a switch to switch a transmission direction of the signal for each wavelength under a control of the switch controller. |
| US09680564B2 |
Protection in metro optical networks
An optical network is configured to optimize network resources. The optical network includes multiple optical nodes, light paths between the multiple optical nodes, and a network monitoring device. The network monitoring device monitors the optical network to identify a failure in the optical network. When the failure is a fiber failure, light paths are re-routed around the fiber failure while maintaining the required bandwidth for the optical network. When the failure is a transponder card failure within one of the multiple nodes, a floating spare card may be provisioned to service a particular light path associated with the transponder card failure. When the failure is a node failure, transponder cards in some of the multiple optical nodes are provisioned to reconfigure some of the plurality of light paths to route traffic around the failed node. |
| US09680563B2 |
System and method for partial bandwidth communication
A system and method for partial bandwidth communication. The system includes a device that has a transceiver configured to connect to a network, a memory storing an executable program and a processor. The program causes the processor to perform operations including receiving data to be transmitted to second device, determining if the data uses less than a predetermined bandwidth used as a unit for a carrier aggregation, determining a plurality of sub-bands in the predetermined bandwidth, each sub-band including at least one pilot and a plurality of frequency tones, receiving network information from the second device, the network information indicating a preferred sub-band of the sub-bands, assigning one of the sub-bands to the second device based upon the network information, generating a packet including an indication, the indication indicating the assigned sub-band; transmitting the packet to the second device and transmitting the data in the assigned sub-band. |
| US09680562B2 |
Inroute burst header in a VSAT system
A satellite terminal and a machine-implemented method are provided for encoding a burst header of a burst for transmission on an inroute. One component of a group of satellite terminal components consisting of an ASIC, a FPGA, and a DSP, generates a burst header having five information bits encoded therein. The five information bits may be encoded using a Reed-Muller code, a (32, 5) block code or a convolutional code having a code rate of either 1/5 or 1/10. The five information bits may represent one or more of a modulation type for a payload of the burst, a code rate for encoding the payload, a code type, and a spreading factor for spreading the payload during transmission. A satellite gateway and a machine-implemented method are also provided for decoding a burst header of a burst received on an inroute as described above. |
| US09680559B1 |
Hierarchichal beam management
Information associated with a communication service need of the user is received from a user of a client computer system. A set of communication service requirements that indicate satellite resources required to satisfy the communication service need of the user are computed based on the received information, and transmitted to a server computer system. A first beam plan that satisfies the set of communication service requirements is received from the server computer system. The first beam plan includes information on satellite beams and spectra for allocation to the user when the first beam plan is deployed to provide a communication service to the user that satisfies the communication service need of the user. Instructions are transmitted to the server computer system to deploy the first beam plan. Information is received from the server computer system indicating that the first beam plan is deployed. |
| US09680554B2 |
Method and system for distributed transceivers for distributed access points connectivity
A controlling entity communicates with a plurality of network devices having a plurality of distributed transceivers and one or more corresponding antenna arrays. The controlling entity receives information, such as location information, propagation environment characteristics, physical environment characteristics and/or link parameters and quality from the network devices and/or communication devices that are communicatively coupled to the plurality of network devices. The controlling entity coordinates communication of data streams for the distributed transceivers and the antenna arrays based on the received information. The network device comprises an access point, a router, a switching device, a gateway and/or a set top box. The controlling entity is located within or external to one of the network devices. One or more functions performed by the controlling entity are split between the controlling entity and one or more of the network devices. |
| US09680553B1 |
System and method for a beamformer
In accordance with an embodiment a beamforming circuit having a radio frequency (RF) front end and a plurality of beamforming delay circuits coupled to the RF front end. Each of the plurality of beamforming delay circuits includes a common delay circuit and a plurality of individual delay circuits coupled to the common delay circuit. Each of the individual delay circuits are configured to be coupled to an antenna element of a beamforming array. |
| US09680549B2 |
User scheduling and beamformer design method, apparatus, and storage medium based on two-stage beamformer for massive MIMO downlink
Disclosed herein are a user scheduling and beamformer design method, apparatus, and storage medium for multi-user MIMO downlink based on two-stage beamforming or single-stage beamforming. The user scheduling and beamformer design method includes 1) a two-step feedback approach, 2) the use of orthonormal reference beam vectors, 3) computation of the angle between the user's channel vector and each of the orthonormal reference beam vectors, 4) first-step feedback of the reference beam index to which the user's channel vector's angle is less than a certain threshold and feedback of the user's channel vector's norm, 5) selection of roughly orthogonal users with large channel norm based on the use of reference beam vectors and the channel norm feedback, 6) second-step feedback of the channel state information (CSI) from the scheduled users, 7) design of multi-user downlink beamformer for the scheduled users based on the second-step feedback of the CSI of the scheduled users. The main key point of this invention is that in the first step of user selection, we propose to use the channel norm or noise-plus-interference-divided channel norm as the feedback quantity and we propose to use only the angle between each of the reference beam vectors and the user's channel vector to identify the closest reference beam vector. |
| US09680547B2 |
Methods for efficient beam training and network control device utilizing the same
A network control device. A wireless communications module receives a plurality of first signals each including information regarding a preferred transmitting beam in a first beam level determined by a communications apparatus. A controller selects a group of communications apparatuses to join a 1-to-many beam training according to the received first signals and selects one or more transmitting beams in a second beam level to be trained. The communications apparatuses in the group have the same preferred transmitting beam in the first beam level and the transmitting beam(s) in the second beam level associates with the preferred transmitting beam in the first beam level. The wireless communications module further uses the transmitting beam(s) in turn to transmit signals to perform the 1-to-many beam training for training the transmitting beam(s) in the second beam level among the group of communications apparatuses at the same time. |
| US09680545B2 |
Multi-transceiver system with MIMO and beam-forming capability
A system and method for communicating with a second communication system utilizing a plurality of antennas. Various aspects of the present invention may comprise determining whether communicating with the second communication system utilizing a plurality of antennas in a first configuration, which comprises a beam-forming configuration, is preferable to utilizing a plurality of antennas in a second configuration, which comprises a MIMO or MISO configuration. If it is determined that the first configuration is preferable to the second configuration, the communication system may be configured to communicate with the second communication system by utilizing at least a portion of the plurality of antennas in the first configuration. If it is determined that the second configuration is preferable to the first configuration, then the communication system may be configured to communicate with the second communication system by utilizing at least a portion of the plurality of antennas in the second configuration. |
| US09680543B2 |
Beamforming using base and differential codebooks
Embodiments of methods and apparatus for determining and/or quantizing a beamforming matrix are disclosed. In some embodiments, the determining and/or quantizing of the beamforming matrix may include the use of a base codebook and a differential codebook. Additional variants and embodiments are also disclosed. |
| US09680542B2 |
Precoding in a wireless communication network
A method for performing precoding in a wireless communication system is disclosed. The method includes obtaining a parameter indicative of reception quality on a downlink channel from a base station to a user equipment (UE) served by the base station; comparing the parameter with a predetermined reception quality threshold; and based on the comparison result, selecting a precoding mechanism for use in communicating with the UE. |
| US09680541B2 |
Methods and apparatuses for channel estimation and feedback in a three-dimensional multiple input and multiple output system
Embodiments of the present disclosure relate to methods and apparatuses for channel estimation and feedback in a three dimensional multiple input multiple output (3D-MIMO) system. A method may comprise: transmitting a plurality of reference signals for a plurality of columns in an antenna array; receiving indication information on configuration adjustment of a precoding information feedback, wherein the indication information is based on measurement on the plurality of reference signals; and adjusting a configuration of the precoding information feedback based on the indication information so that a multiple vertical precoding information feedback is enabled when it can obtain a performance gain. Especially, the multiple vertical precoding information feedback may represent feeding back a plurality of vertical precoding matrix indicators for the plurality of columns in the antenna array. In embodiments of the present disclosure, there is provided a new solution for channel estimation and feedback in a 3D-MIMO system, and it may achieve a more accurate beamforming and/or a higher order spatial multiplexing, thereby improving the performance of the 3D-MIMO system. |
| US09680534B2 |
Wideband near field communication method
A method for performing a wideband short-range wireless communication which may use a directional antenna in a millimeter wave band, and the method for wideband short-range wireless communication according to an embodiment may determine a change of a relay operation type based on a link quality between a source node and a relay node, a link quality between the relay node and the destination node, and a link quality between the source node and the destination node, transmit a relay operation change (ROC) request message in response to a determination of the change of the relay operation type, and receive an ROC response message corresponding to the ROC request message. |
| US09680531B2 |
System and method for detecting inadequate wireless coupling and improving in-band signaling in wireless power transfer systems
An apparatus for receiving wireless power is provided. The apparatus comprises a receive coupler configured to receive the wireless power from a wireless power transmitter. The apparatus comprises a receive circuit electrically connected to the receive coupler, the receive circuit configured to provide power to a load. The apparatus comprises a controller circuit configured to provide a first amount of power from the receive circuit to the load. The controller circuit is further configured to reduce the first amount of power to a second amount of power for a duration of communication with the wireless power transmitter to increase a difference between a first impedance and a second impedance of the receive circuit compared to when the first amount of power is provided to the load. |
| US09680530B2 |
Non-contact power supply apparatus and non-contact power supply system
A non-contact power supply apparatus is configured to transmit power in a non-contact manner from a primary-side coil to a secondary-side coil by supplying alternating current power to the primary-side coil. The non-contact power supply apparatus is provided with an alternating current power output unit, a power transmitting unit, wiring, a detecting unit, and a determining unit. The alternating current power output unit is capable of outputting alternating current power. The power transmitting unit has the primary-side coil. The wiring electrically connects the alternating current power output unit and the power transmitting unit to each other. The detecting unit detects a ratio between an output voltage and an output current, which are outputted from the alternating current power output unit, or a phase difference between the output voltage and the output current. On the basis of the ratio and/or the phase difference detected by means of the detecting unit, the determining unit determines whether an abnormality has generated or not in the non-contact power supply apparatus. |
| US09680527B2 |
Radiation hardened 10BASE-T ethernet physical layer (PHY)
Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened. |
| US09680522B2 |
Dynamic reconfiguration of uplink transmission in a TDD wireless communication system
Embodiments of the invention use signaling mechanisms that enable dynamic reconfiguration of the UL/DL resource partitioning by user equipment (UE) in a TDD wireless communication system, such as the 3GPP TDD Long Term Evolution (TD-LTE) system. The dynamic reconfiguration of the UL/DL resource partitioning disclosed herein may also be applied to any other TDD wireless system employing dynamic reconfiguration of the TDD UL/DL configuration. |
| US09680518B2 |
Power case for electronic device
A protective case for an electronic device includes a cover, a rechargeable battery, first and second electrical connectors, and electrical circuitry. The first electrical connector is accessible at an outer surface of the cover for electrically connecting to an external power source. The second electrical connector is accessible at an inner surface of the cover for electrically connecting the protective case to the electronic device. The electrical circuitry distributes the received electrical power to the electronic device and to the rechargeable battery. The electrical circuitry also distributes stored electrical power from the rechargeable battery to the electronic device. Distribution of the stored electrical power to the electronic device is conditioned upon an input received from the electronic device, a mode of the protective case, and or a signal received at the protective case. |
| US09680513B2 |
Signal transceiver
A signal transceiver is provided. The signal transceiver includes: signal convert circuit adapted to convert single-ended signals into differential signals; first power amplifier; receiving amplifier; impedance convert circuit; first capacitive circuit; second capacitive circuit; and first switch circuit; wherein output terminals of the signal convert circuit are connected with output terminals of the first power amplifier and first set of terminals of the first capacitive circuit; second set of terminals of the first capacitive circuit is connected with first set of terminals of the impedance convert circuit; second set of terminals of the impedance convert circuit is connected with input terminals of the receiving amplifier and first set of terminals of the second capacitive circuit; second set of terminals of the second capacitive circuit is connected with first set of terminals of the first switch circuit; and second set of terminals of the first switch circuit is connected to ground. |
| US09680511B1 |
Distortion compensator, distortion compensation method and radio equipment
A distortion compensator, includes: an input terminal configured to receive a transmission signal; a processor configured to perform operations to process the transmission signal, wherein the operations includes: compensating a nonlinear distortion of an amplifier which amplifies a power of the transmission signal, by using a distortion compensation coefficient corresponding to an amplitude value of the transmission signal; calculating a difference between a power value of the transmission signal and a power value of a feedback signal from the amplifier; calculating an imaginary part of a first complex vector based on an error between the transmission signal and the feedback signal in a cartesian coordinate system; and updating the distortion compensation coefficient by using a second complex vector of which a real part is the difference, and an imaginary part is the imaginary part of the first complex vector. |
| US09680510B2 |
Radio communication using tunable antennas and an antenna tuning apparatus
The invention relates to a method for radio communication using one or more tunable antennas and an antenna tuning apparatus, and to an apparatus for radio communication using one or more tunable antennas and an antenna tuning apparatus. An apparatus for radio communication of the invention comprises: 4 antennas, each of the antennas being a tunable passive antenna; a radio device; an antenna tuning apparatus having 4 antenna ports, each of the antenna ports being coupled to one of the antennas through a feeder, the antenna tuning apparatus having 4 radio ports, each of the radio ports being coupled to the radio device through an interconnection; and a tuning control unit, the tuning control unit receiving a tuning instruction generated automatically within the apparatus for radio communication, the tuning control unit delivering a plurality of tuning control signals to the antenna tuning apparatus and to the tunable passive antennas. |
| US09680509B2 |
Errors and erasures decoding from multiple memory devices
Embodiments are generally directed to errors and erasures decoding from multiple memory devices. An apparatus may include logic to store a portion of an error correction codeword in each of multiple memory devices, and logic to decode errors and erasures for the memory devices. The decoding of the errors and erasures includes reading the portions of the error correction codeword from a subset of the memory devices to generate a partial codeword, with the subset excluding at least one of the memory devices. The decoding of the errors and erasures further includes decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword if the errors and erasures can be decoded from the partial codeword, and, upon determining that the errors and erasures cannot be decoded from the partial codeword, then reading the one or more portions of the error correction codeword from the memory devices excluded from the first subset to generate a complete codeword. |
| US09680504B2 |
Controller, semiconductor memory system, data storage system and operating method thereof
An operating method of a controller includes iterating a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the first read voltage is updated on basis of a number of an unsatisfied syndrome check (USC); and when the first ECC decoding fails until the predetermined iteration number, performing a second ECC decoding on the codeword by generating soft decision data according to the first read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding. |
| US09680500B2 |
Staged data compression, including block level long range compression, for data streams in a communications system
Approaches for staged data compression are provided, where each stage reflects a progressive increase in granularity, resulting in a scalable approach that exhibits improved efficiency and compression performance. The first stage comprises a long-range block-level compressor that determines redundancies on a block-level basis (based on entire data blocks, as opposed to partial segments within data blocks). The second stage comprises a long-range byte-level compressor that compresses an uncompressed block based on byte segments within the block that match previously transmitted segments. The duplicate segments are replaced with pointers to matching segments within a decompressor cache. Nonmatching segments of the data block are left uncompressed and passed to a third stage short-range compressor (e.g., a grammar-based compressor). The staged progression in granularity provides advantages of maximizing the compression gain while minimizing processing and storage requirements of the compressor and decompressor. |
| US09680499B2 |
Data compression device and method
A data compression device including a processor to perform a procedure comprising: obtaining data of a predetermined number (Z) of digits in a time series; and performing a compression process on the data. The data is obtained by encoding a vibration state of a measurement target. The compression process includes: deleting upper digits when the upper digits do not include significant information; and adding a unique code to a top of the upper digits when the upper digits include significant information. A digit number (X) of the upper digits is smaller than the predetermined number (Z). |
| US09680496B2 |
Apparatus for overload recovery of an integrator in a sigma-delta modulator
Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output. |
| US09680491B2 |
Signal processing circuit
A signal processing circuit includes: a plurality of daisy chain-connected AD converters each including a data ready output terminal, a synchronizing signal input terminal, and a serial clock input terminal; a calculator connected to the data ready output terminal of any of the AD converters and for outputting a serial clock to the serial clock input terminal of each of the AD converters when a data ready signal is input; and a reset processor included in the calculator and for outputting a synchronizing signal to the synchronizing signal input terminal of each of the AD converters when an output time lag among data ready signals from each of the AD converters is detected for a predetermined number of times. |
| US09680488B2 |
Switchable secondary playback path
In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude. |
| US09680486B2 |
DCO phase noise with PVT-insensitive calibration circuit in ADPLL applications
A calibration procedure that uses direct measurement of digital phase error performance for low cost calibration of all-digital phase locked loop (ADPLL)/digitally-controlled oscillator (DCO) is described. Direct measurement of digital phase error, or difference in digital phase error, is used to adjust the operating point of the DCO and thereby determine the operating point that provides the optimal phase noise of the output signal. Calibration may be performed at any time so that changes in external factors such as process, voltage and temperature (PVT) may be incorporated into the setting of the operating point of the DCO. |
| US09680485B2 |
Automatic frequency control
An automatic frequency control device, a method for automatic frequency control, a receiver, a mobile station and a non-transitory computer-readable digital storage medium are provided. The automatic frequency control device may include a quality calculation unit to calculate quality of a received signal, a state machine controller to generate a control signal based on the calculated quality of the received signal, and a filter to filter an estimated frequency offset of the received signal based on the control signal. |
| US09680484B2 |
Clock conditioner circuitry with improved holdover exit transient performance
Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation. |
| US09680483B2 |
Current mirror circuit and charge pump circuit
A current mirror circuit includes: a reference current circuit including a reference transistor and a constant current source coupled between a high potential source and a low potential source; a first proportional current circuit, including a first transistor that forms a first current mirror circuit with the reference transistor, to generate a first current having a first ratio to a reference current of the reference current circuit; a second proportional current circuit, including a second transistor that forms a second current mirror circuit with the reference transistor, to generate a second current having a second ratio to the reference current; a comparison circuit to output a difference between a drain voltage of the first transistor and a drain voltage of the second transistor; and a current adjustment transistor coupled to a drain of the second transistor and including a gate to which an output of the comparison circuit is applied. |
| US09680482B2 |
Phase-locked loop device
A phase-locked loop device may include the following elements: a phase frequency detector configured to generate a control signal; a charge pump connected to the phase frequency detector; a loop filter connected to the charge pump and configured to generate a control voltage based on a first current received from the charge pump, wherein the charge pump is configured to generate a second current based on the control signal and a first copy of the control voltage and to provide the second current to the loop filter, the second current being linearly related to the control voltage; a voltage-controlled oscillator connected to the loop filter and configured to generate an output signal based on a second copy of the control voltage, wherein a frequency of the output signal is directly proportional to the control voltage; and a signal processor connected between the voltage-controlled oscillator and the phase frequency detector. |
| US09680481B2 |
Phase detection circuit and signal recovery circuit that includes phase detection circuit
A phase detection circuit includes: a first circuit configured to generate a first phase detection signal that indicates a result of sampling a first clock signal at a transition timing of an input data signal; a second circuit configured to generate a second phase detection signal that indicates a result of sampling a second clock signal at the transition timing of the input data signal, a phase of the second clock signal being different from a phase of the first clock signal; and a third circuit configured to generate a third phase detection signal that indicates a phase of the first clock signal with respect to the input data signal based on the first phase detection signal and the second phase detection signal. |
| US09680479B1 |
Electronic apparatus and controlling method
An electronic apparatus includes a voltage-controlled oscillator and a biasing circuit. The voltage-controlled oscillator includes varactors. The voltage-controlled oscillator is configured to output an oscillating frequency at a first temperature. The biasing circuit electrically coupled with the varactors is configured to provide a first biasing voltage to the varactors at the first temperature, and provide a second biasing voltage to the varactors at a second temperature, in which the varactors have a first temperature coefficient, and the biasing circuit generates the first biasing voltage and the second biasing voltage according to values of the first temperature coefficient and a second temperature coefficient. |
| US09680478B2 |
Initializing a ring counter
A technique includes driving a node of a stage of a ring counter to a predetermined signal state; and clocking the ring counter to cause the signal state to propagate to at least one additional stage of the ring counter to initialize the ring counter with a reset sequence. |
| US09680477B2 |
Printed circuit board security using embedded photodetector circuit
Systems and methods to obstruct analysis of a microchip may include an electrical component of a microchip and a photodetector positioned within the microchip. The photodetector may be configured to sense electromagnetic radiation. Circuitry in electrical communication with the photodetector may be configured to initiate an action to obstruct analysis of the electrical component in response to a change in a level of the electromagnetic radiation. |
| US09680474B1 |
System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices
An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device. |
| US09680472B2 |
Voltage level shifter circuit
Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed. |
| US09680469B1 |
Circuits and methods for impedance calibration
A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and/or to compensate for parasitic resistance. |
| US09680465B2 |
Switching circuit
A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The switching circuit further includes a gate voltage generating circuit configured to switch voltage applied to the gate of the PLDMOS between a first voltage and a second voltage, wherein the first voltage is substantially the same as an input voltage from the converting circuit, and wherein a difference between the first voltage and the second voltage is lower than the gate-source breakdown voltage of the PLDMOS. |
| US09680457B2 |
Semiconductor apparatus and radio communication apparatus
A semiconductor apparatus that can detect the amplitude level of harmonics is provided. A semiconductor apparatus includes a common mode detector circuit that detects alternating current (AC) signals in a common mode, and a detector circuit that detects the amplitude level of an even-order harmonic output from the common mode detector circuit. The common mode detector circuit combines the AC signals being differential signals in common mode, thereby cancelling out odd-order harmonics to obtain direct current and even-order harmonics. The detector circuit detects the amplitude level of the even-order harmonics from a signal obtained by the common mode detection, and outputs the detected amplitude level. |
| US09680451B2 |
Integrated circuit
An integrated circuit includes: a latch unit suitable for inverting a voltage level of a first node and driving a second node with the inverted voltage level of the first node, and inverting a voltage level of the second node and driving the first node with the inverted voltage level of the second node; and a sink unit coupled with one or more among the first and second nodes, and suitable for sinking a charge of the coupled node. |
| US09680450B2 |
Flip-flop circuit with latch bypass
In one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. The slave latch has an input coupled to the output of the master latch, and an output, and operates in the transparent and latching modes during the second and first phases of the clock signal, respectively. The multiplexer has a first input coupled to the output of the slave latch, a second input coupled to the output of the master latch, and an output for providing a data output signal, and provides the first input to the output during the first phase of the clock signal, and the second input to the output during the second phase of the clock signal. |
| US09680449B2 |
Encoder input device
An encoder input device includes a connection terminal to be connected to one of encoders and made common to a plurality of types of signal systems of the encoders, a plurality of power supplies for signals according to the plurality of types of signal systems of the encoders, and a software switch that switches connection arrangement between the connection terminal and the power supplies for signals in a software manner according to the signal system of the encoder connected to the connection terminal among the plurality of types of signal systems of the encoders. |
| US09680437B2 |
Equalization contouring by a control curve
A method for equalization contouring provides a reduction of equalization in certain frequency regions either by user control or by automated selection of frequency, without introducing artifacts. A control curve smoothly scales the magnitude of the equalization in the areas where less equalization is desired to obtain a contoured equalization. The control curve varies by frequency and may be defined specifically for every sampled frequency value of the equalization, may be a continuous function of frequency, or may be a function of control points at a select number of frequency points. The control curve may also have automatic inputs, e.g. a machine-detected cutoff frequency of a speaker may be used to determine a control point in the control curve. As another example, the reverberation time (e.g. RT60) may be used to determine a control point in the control curve. The result is a contoured equalization curve without sudden steps. |
| US09680435B1 |
Method and device for improving acoustics of an AM demodulation output signal
A method for improving acoustics of amplitude modulation (AM) audio signal, comprising: amplifying and mixing, with an amplitude modulation (AM) front-end module, an analog AM signal and an automatic gain control (AGC) signal from an AGC module; converting and sampling, with an analog-digital converter and down-sampling module, the amplified and mixed signal to generate a digital AM signal; digitally mixing, with a digital mixer module, the digital AM signal to generate a first digital AM envelope signal; compensating, with an AM compensator module, the first digital AM envelope signal by an AM compensating AGC signal from the AM compensator module to generate a second digital AM envelope signal; demodulating, with a demodulation module, the second digital AM envelope signal; and outputting, with an output module, a demodulated AM audio signal. |
| US09680429B2 |
Amplifier system
An amplifier system is described. The amplifier system may amplify an audio signal transmitted via a connected loudspeaker in a first mode of operation. In a second mode of operation the amplifier system may amplify a signal generated by the loudspeaker operated in reverse as a microphone. Because a loudspeaker is less sensitive than a microphone the amplifier system may be used to acquire audio at high sound pressure levels for example at a concert or while making a phone-call in a noisy environment for example with a high level of wind noise. |
| US09680427B2 |
Power amplifier having stack structure
A power amplifier having a stack structure comprises a first driver stage that receives a power voltage from a power supply and receives and amplifies an input signal; a second driver stage that receives the power voltage from the power supply, has an input terminal connected with an output terminal of the first driver stage, and receives and amplifies an output signal from the first driver stage; and a power stage that has a power input terminal connected with a ground terminal of the first driver stage and a ground terminal of the second driver stage and receives a virtual ground voltage, and has an input terminal connected with an output terminal of the second driver stage and receives and amplifies an output signal from the second driver stage. |
| US09680420B2 |
Apparatus for compensation of electronic circuitry and associated methods
An apparatus includes a multi-stage amplifier. The multi-stage amplifier includes first, second, and third amplifier circuits coupled in a cascade configuration. The multi-stage amplifier further includes first, second, and third compensation networks. The first compensation network is coupled between the output of the third amplifier circuit and the input of the second amplifier circuit. The second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit. The third compensation network is coupled between the output of the second amplifier circuit and the input of the second amplifier circuit. |
| US09680419B2 |
Power controllable wireless communication device
A power controllable wireless communication device includes a variable gain amplifier having a gain that can be controlled based on a gain control signal, a reference power generation circuit, which generates first reference power and second reference power differing from the first reference power, a sensor circuit supplied with selectively power of a high frequency signal output from the variable gain amplifier, and the first reference power and the second reference power generated by the reference power generation circuit, and a control circuit which generates the gain control signal based on a sensor output from the sensor circuit. When controlling power, the control circuit generates the gain control signal based on ratios among a first sensor output corresponding to the first reference power, a second sensor output corresponding to the second reference power, and a high frequency sensor output corresponding to the power of the high frequency signal. |
| US09680415B2 |
Apparatus and method for filtering radio frequency signals of transceiver integrated circuits
Devices and methods are disclosed for generating, filtering, and amplifying signals that are sent and received using SOCs. These improved methods and devices advantageously provide filtering of composite RF signals such that the RF signals can be transmitted with an improved SNR. Such filtered signals can then be transmitted at a higher power. Because filtering is performed at an intermediate frequency, the higher cost of low-noise RF-transmitters and/or RF filtering components can be avoided. Accordingly, less expensive (e.g., noisier) components, such as readily available wireless transceiver SOCs, can be used for generating RF signals, filtering the signals, and then transmitting the filtered signals at higher power. As a result of these devices and methods, inexpensive SOCs may be used at higher powers and over longer ranges than would be normally expected. |
| US09680413B2 |
Systems and methods of low power clocking for sleep mode radios
Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator. |
| US09680410B2 |
Corrugated roof sheet and photovoltaic assembly comprising the same
A corrugated roof sheet has a bottom, a first-side roof sheet edge portion, a second-side roof sheet edge portion, a retaining cap and a protruding portion. The first-side roof sheet edge portion has a height H1 from the bottom. The retaining cap covers the first-side roof sheet edge portion and has a lower fringe. The lower fringe has a height h2 from the bottom. The protruding portion is between the first-side roof sheet edge portion and the second-side roof sheet edge portion and has a height h3 from the bottom. The height h2 is greater than the height h3. |
| US09680409B2 |
Adjustable combined flashing and mounting apparatus and method of mounting to be used therewith
The present disclosure is directed to a roof mounting system that utilizes a base plate that is affixed to a roof surface by multiple fasteners (e.g., lag bolts, screws etc.) and a cap (e.g., top cap) that attaches to the base plate covering the fasteners affixing the base plate to the roof surface. Once attached, the top cap covers the fasteners preventing water infiltration. To further waterproof the fasteners affixing the base plate to the roof surface, the base plate includes a raised or elevated section on its top surface with a planar flange extending around the elevated section. A portion of the flange may be disposed beneath a single or shingles on a roof surface. The fasteners extend through the elevated section. Accordingly, water drains around the elevated section when the base plate is attached to a roof surface further isolating the fasteners. |
| US09680396B2 |
Multi-vector outphasing DC to AC converter and method
DC to AC multi-vector, multi-module switch mode converter capable of producing a fully regulated quazi-sinusoidal output voltage with cancelled N odd harmonics comprises two sets of 2N switch mode modules each with equal output amplitude operating with the output frequency and the means for summation of their outputs. Each switch mode module in the first set operates with its own fixed phase shift, in reference to the first module. Each module phase shift is calculated as a weighted sum of phase shifts for all harmonics to be cancelled Φn=π/n, where n is a number of harmonic and weights are defined by module number. The second set of modules is identical to the first set and produces its own output voltage with cancelled N harmonics too. The output voltages of the first and second sets are proportional to the DC bus voltage. The amplitude of the combined output voltage is regulated by the variable phase shift between the output voltages of the first and the second sets. The switch mode module DC inputs of both sets may be connected to DC power bus in parallel, in series, or in groups. |
| US09680392B2 |
Modular multi-level converter
Provided is a modular multi-level converter (MMC) including a plurality of sub-modules including switching elements, and a central control unit which assigns an address to each of the plurality of sub-modules for distinguishing each of the plurality of sub-modules, determines switching operation conditions of the plurality of sub-modules based on the assigned addresses, and outputs switching signals corresponding to the determined switching operation conditions. The central control unit determines a switching sequence of the plurality of the sub-modules according to the sequence of the assigned addresses. |
| US09680391B2 |
Multi-input scalable rectifier droop detector
A droop detector includes: a plurality of input nodes, each input node configured to receive a supply voltage; an output node; a plurality of detector modules, each detector module comprises: an input terminal coupled to each input node, an output terminal coupled to the output node; and an input tracking unit configured as a voltage follower to detect a droop in the supply voltage coupled to each input node and output an output voltage that follows the supply voltage on the output terminal when the droop is detected on the supply voltage; and a comparator coupled to the output node and configured to output a control signal when the droop is detected. |
| US09680383B2 |
Input overvoltage protection using current limit
A controller for use in a power converter includes a state selection circuit coupled to receive an input voltage sense signal representative of an input voltage, a switch current sense signal representative of a switch current of a power switch, and a feedback signal representative of an output quantity of the power converter. The state selection circuit is coupled to generate an input voltage signal in response to the input voltage sense signal, an input current signal in response to the switch current sense signal, and an input threshold signal in response to the feedback signal. A state machine circuit is coupled to the state selection circuit to generate a drive signal in response to the input voltage signal, the input current signal, and the input threshold signal to switch the power switch to control a transfer of energy from an input to an output of the power converter. |
| US09680382B2 |
Input frequency measurement
A frequency determination circuit includes a positive crossing sense circuit coupled to receive an input voltage to sense a positive crossing of an input voltage. A validation circuit is coupled to the positive crossing sense circuit to validate a previous zero crossing and the positive crossing of the input voltage after the positive crossing of the of the input voltage has occurred. A measurement circuit is coupled to the positive crossing sense circuit and the validation circuit to count a time between positive crossing pulses of the input voltage. The measurement circuit is coupled to output a frequency signal that is representative of a frequency of the input voltage in response to the time between the positive crossing pulses of the input voltage. |
| US09680379B2 |
DC-DC converter using a power driving signal with fixed on-time
A DC-DC converter includes a voltage converting block that converts an input supply voltage to an output voltage and includes a power switch turning on at on-time of a power driving signal, a power driving block that generates the power driving signal using an oscillation output signal, wherein a cycle of the power driving signal varies according to a cycle of the oscillation output signal and a length of the on-time of the power driving signal is fixed to a power time regardless of variation of the cycle of the oscillation output signal, a voltage-controlled oscillating block that generates the oscillation output signal, the cycle of which is controlled according to a level of an oscillation control signal, and a target tracking block that generates a feedback voltage and controls the level of the oscillation control signal such that a feedback voltage follows a target reference voltage. |
| US09680374B2 |
DC to DC boost converter utilizing storage capacitors charged by parallel inductor
A high frequency inductive emf circuit charges storage capacitors, one at a time, from a DC source to a voltage that is higher than the DC output voltage. After each storage capacitor is charged, it is disconnected from the charging circuit and then connected to an output device/regulator that uses the energy in each storage capacitor to provide the desired DC output voltage to a load. While one storage capacitor is being charged, a previously charged storage capacitor is being discharged through an output device/regulator. After being discharged, each storage capacitor is disconnected from its output device/regulator and reconnected to the charging circuit and is charged again. While being charged, the storage capacitors are in a parallel circuit to the inductor in the charging circuit. The inductor in the charging circuit and the DC source are never in a current loop with the load. |
| US09680367B1 |
System and method for limiting output current in a switching power supply
A switching power supply comprises one or more power supply stages configured to receive power from an input power source and to generate an output voltage for powering a load by alternately opening and closing a set of switches. An output current sensor is configured to monitor a level of an output current of the switching power supply. The opening and closing of the set of switches is controlled so as to maintain the output voltage at a desired level when the level of the output current is below the threshold and so as to limit the output current when the level of the output current exceeds the threshold. |
| US09680365B2 |
Systems and methods of over-load protection with voltage fold-back
In a typical DC-DC converter, an error amplifier is used to sense and amplify the difference between the feedback voltage and the reference voltage. In the event of current overloading (limit condition), example embodiments of the disclosed systems and methods of over-load protection with voltage fold-back fold back the reference voltage proportional to the current limit. The regulator may continue to regulate in this fold-back voltage reference condition without shutting down the converter, saturating the inductor, or causing a catastrophic failure at the power FETs. The disclosed systems and methods of over-load protection with voltage fold-back resolve consecutive switching cycle current build up in high input voltage DC/DC convertor applications due to the latency of current limit circuitry. |
| US09680363B2 |
Low ripple mechanism of mode change in switched capacitor voltage regulators
Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed. |
| US09680356B2 |
Architecture of interconnected electronic power modules for rotary electrical machine, and rotary electrical machine comprising architecture of this type
An architecture of interconnected electronic power modules for a polyphase rotary machine, includes electrically interconnected power modules (5) and a connector (6) including one or more layers formed by pluralities of conductive traces borne by plates, such as to connect the power modules (51 to 53) to one another and to electrical elements of the rotary machine. The power modules (51 to 53) include a plurality of connection elements (510 to 530) brazed directly to components of the power modules (51 to 53) and, in the upper part, to conductive traces of the connector (6). This architecture includes a heat sink (4) equipped with open cavities (41 to 43) for receiving the power modules (51 to 53). A polyphase rotary machine is also provided using such an architecture, in particular a dual three-phase alternator with synchronous rectification. |
| US09680354B2 |
Winding cooling structure of shaft motor
A winding cooling structure of shaft motor includes a chamber in which multiple annular windings are received. A cooling fluid is filled up in the chamber to possibly contact the surfaces of every part of the respective windings. Therefore, heat generated by the windings can be quickly transferred to the cooling fluid around the windings and dissipated. Accordingly, in operation, the heat dissipation efficiency of the shaft motor can be enhanced to prolong lifetime of the motor and ensure the performance of the motor. |
| US09680352B2 |
Convection cooling system for motors
An apparatus includes a lamination stack for a motor stator. The lamination stack comprises a plurality of conductive laminates. The laminates are coupled to each other in a stacking direction along a stacking axis. Each laminate comprises a base, a plurality of fins extending from a first side of the base, a plurality of spacings between the fins, a row of teeth extending from a second side of the base opposite the first side, each tooth constructed and arranged to communicate with windings of a conductive coil, and a plurality of spacings between the teeth. The lamination stack also comprises a plurality of first channels formed from the spacings between the fins and a plurality of second channels formed from the spacings between the teeth. The first and second channels extend along the stacking axis. |
| US09680349B2 |
Power tool with substrate having apertures for cooling coils and switching elements
An electric power tool including: a housing; a brushless motor accommodated in the housing; a fan attached to a rotation shaft of the brushless motor; a switching element configured to control the brushless motor; and a substrate on which the switching element is mounted, wherein a first through-hole is provided to a switching element arranged portion of the substrate. |
| US09680347B2 |
Electric motor/gear mechanism unit
The invention relates to an electric motor/gear mechanism unit including a housing, an iron-free rotor winding rotatably arranged in the interior of the housing, a collector connected to the rotor winding, a rotor shaft extending through the collector, and a gear mechanism which is connected to the rotor shaft and which has an output shaft. The present invention is so conceived that the gear mechanism is produced from a non-magnetic material and arranged in the interior of the rotor winding. |
| US09680331B2 |
System and method for frequency protection in wireless charging
This disclosure provides systems, methods, and apparatuses for controlling wireless charging between a first entity and a second entity. For example, the apparatus may include a receiver communication circuit of the first entity configured to receive a current from a second entity via electromagnetic induction during the charging or alignment with the second entity. The apparatus may include a frequency measurement circuit configured to determine an operating frequency of the received current or a voltage induced by the electromagnetic induction. The apparatus may include a controller configured to compare the operating frequency to a threshold and adjust an operation of the charging or the alignment based on the comparison. |
| US09680325B2 |
Lithium-based battery pack for a hand held power tool
An electrical combination. The electrical combination comprises a battery pack configured to be interfaced with a hand held power tool, a control component, and a semiconducting switch. The transfer of power from the battery pack to the hand held power tool is controlled by the control component and the switch based on one of a battery pack state of charge and a respective state of charge of one of a plurality of battery cells. A discharge current of the battery pack is regulated based on the switch being controlled into one of a first state and a second state by the control component to selectively enable the transfer power from the plurality of battery cells to the hand held power tool. |
| US09680324B2 |
Energy harvesting damper control and method of operation
A system for controlling a damper, comprising an energy harvesting device is disclosed. A voltage conditioning and storage unit coupled to the energy harvesting device, the voltage conditioning and storage unit configured to apply overvoltage and undervoltage protection to a storage capacitor. A controller coupled to the voltage conditioning and storage unit, the voltage conditioning and storage unit configured to apply overvoltage protection to the controller. |
| US09680323B2 |
Single inductor DC-DC converter with regulated output and energy harvesting system
An energy harvesting circuit receives an input voltage from a transducer and uses a single inductor operating in a DC-DC converter charging mode to generate charging current at a first output coupled to an energy storage device where a supply voltage is stored. The energy harvesting circuit further receives the supply voltage from the energy storage device and uses the same single inductor operating in a DC-DC converter regulating mode to generate load current at a second output where a regulated load voltage is provided. The energy harvesting circuit switches between the charging mode and the regulating mode in accordance with a discontinuous mode (DCM) control process. |
| US09680320B2 |
Battery control apparatus
A battery control apparatus is provided which can keep an inter-terminal voltage of each single cell within a permitted range while permitted power is controlled in units of a battery pack. The battery control apparatus of the invention restricts the permitted power of the battery pack according to a degree of closeness of a close circuit voltage of the single cell to an upper limit or a lower limit of the permitted range. |
| US09680318B2 |
Modular share pack battery
Described is an energy share pack comprising a housing, at least one energy storage component within the housing, at least one energy conversion component within the housing, and a connection point for connecting to more than one of energy users, energy sources and other energy share packs simultaneously for sharing energy. The energy share pack may have an energy generation component for generating harvestable energy, and two or more ports of any combination of the following types: bidirectional power port, bidirectional USB port, unidirectional output power port, and unidirectional input power port. The share pack ports may operate simultaneously at different voltage levels, and at least one port may be bi-directional. Furthermore, the share packs may have an integrated display for providing information on the energy share pack in which the display is integrated and information about other energy share packs connected thereto. |
| US09680315B2 |
On-board control apparatus
An on-board control apparatus has a power generation means that has a communication part; a storage battery that is chargeable by receiving electric power from the power generation means; a control means that is configured to be communicatable with the communication part and controls charging of the storage battery; and a state-of-charge measurement means that measures a state of charge of the storage battery. The control means transmits a signal that is to prohibit charging the storage battery to the communication part when an ignition of a vehicle is turned off, and the state-of-charge measurement means measures the state of charge of the storage battery, during a period of time in which charging the storage battery is prohibited, after the ignition of the vehicle is turned off. |
| US09680310B2 |
Integrated implantable TETS housing including fins and coil loops
Systems and methods for wireless energy transfer are described. A transmitter unit has a transmitter resonator with a coil that is coupled to a power supply to wirelessly transmit power to a receiver unit. A receiver unit has a receiver resonator with a coil coupled to a device load. The receiver unit can include a ferrite enclosure to prevent transmission of magnetic flux into electronics of the receiver unit, and can include ferrite fins to increase a coupling between the transmitter resonator and the receiver resonator. |
| US09680307B2 |
System and method for voltage regulation of a renewable energy plant
Systems and methods for regulating the voltage at a point of interconnection of a renewable energy plant, such as a solar plant, with a grid are provided. A voltage signal indicative of the voltage at the point of interconnection can be received and filtered with a high pass filter to generate a filtered error signal. The high pass filter can block components of the voltage signal at a frequency less than a threshold frequency. A reactive power command for the renewable energy plant can be generated based on the filtered error signal. One or more inverters of the renewable energy plant can be controlled to output reactive power based on the reactive power command. A rejection module can be implemented to prevent adverse interaction with other voltage control devices. In addition, a reset module can be implemented to preserve dynamic reactive power range of the inverters. |
| US09680306B2 |
Wind power generation control device and wind power generation system having the same
A wind power generation control device, coupled between a wind power generator and a power grid, includes a converter unit and a switching unit. The converter unit includes a generator-side converter, a DC bus capacitor and a grid-side converter, wherein an AC-side of the generator-side converter is coupled to a rotor-side of the wind power generator, a DC-side of the generator-side converter is coupled to the DC bus capacitor, a DC-side of the grid-side converter is coupled to the DC bus capacitor, and an AC-side of the grid-side converter is coupled to the power grid. The switching unit is configured to switch the wind power generation control device between the doubly-fed power generation operating mode and the full-power operating mode according to a wind speed. A wind power generation system uses the wind power generation control device. |
| US09680304B2 |
Method for distributed power harvesting using DC power sources
A system and method for combining power from DC power sources. Each power source is coupled to a converter. Each converter converts input power to output power by monitoring and maintaining the input power at a maximum power point. Substantially all input power is converted to the output power, and the controlling is performed by allowing output voltage of the converter to vary. The converters are coupled in series. An inverter is connected in parallel with the series connection of the converters and inverts a DC input to the inverter from the converters into an AC output. The inverter maintains the voltage at the inverter input at a desirable voltage by varying the amount of the series current drawn from the converters. The series current and the output power of the converters, determine the output voltage at each converter. |
| US09680301B2 |
Master-slave architecture for controlling operation of photovoltaic power plants
A photovoltaic power plant with master-slave control architecture. The photovoltaic power plant includes slave plant controllers, with each slave plant controller controlling operation of photovoltaic inverters that convert direct current generated by solar cells to alternating current suitable for delivery to a utility power grid at a point of interconnection (POI). A master plant controller controls and coordinates the operation of the slave plant controllers. The master plant controller generates a global inverter real or reactive power setpoint, which is provided to each slave plant controller. In each slave plant controller, the global set point is processed to generate individual inverter real or reactive power setpoints that are provided to corresponding photovoltaic inverters controlled by that slave plant controller. A photovoltaic inverter generates an output based on received individual inverter setpoint to achieve a desired real power, voltage or power factor. |
| US09680295B2 |
Anti-icing coating for power transmission lines
Provided are methods and systems for forming piezoelectric coatings on power line cables using sol-gel materials. A cable may be fed through a container with a sol-gel material having a piezoelectric material to form an uncured layer on the surface of the cable. The layer is then cured using, for example, infrared, ultraviolet, and/or other types of radiation. The cable may be suspended in a coating system such that the uncured layer does not touch any components of the system until the layer is adequately cured. Piezoelectric characteristics of the cured layer may be tested in the system to provide a control feedback. The cured layer, which may be referred to as a piezoelectric coating, causes resistive heating at the outer surface of the cable during vibration of the cable due transmission of alternating currents and environmental factors. |
| US09680294B2 |
Conductor system for use in a dielectric
A conductor system for use in a surrounding dielectric has a first member with a first conductive surface having a first edge and arranged to be in contact with the surrounding dielectric; a second member arranged such that there is a gap between the first member and the second member at the first edge; and a protector arranged to be partially held in the gap by elastic forces in the protector and having a conductive protector surface arranged to be pressed against the first edge by the elastic forces and arranged to protrude out of the gap on the side of the first member. |
| US09680293B2 |
Surface mounted multiple cable or wire organizer
A surface mounted multiple cable or wire organizer that includes a rigid connector body with a center void and plurality of transversely aligned holes configured to receive a twist tie. The connector body includes a bottom surface, a top surface, and outer side walls. Adhesive tape or a threaded connector is used to attach the bottom surface of the connector body to a flat surface. During use, a twist tie is inserted through the holes in the connector body. The ends of the twist tie extend outward from the holes on opposite sides of the connector body. A single cable or wire or a bundle of cables or wires is extended over the top surface of the connector body and the ends of the twist tie are bent and twisted over the connector body and the cables and wires to hold them over the top surface of the connector body. |
| US09680289B2 |
Long-life, high-efficiency laser apparatus having plurality of laser diode modules
A laser apparatus includes laser diode module groups (LDMGs) and power supply units and provides a laser light source by collecting laser beam from the LDMGs, and comprises: a driving current supply circuit network for injecting the driving currents into the respective LDMGs, independently; a control unit which controls the driving currents independently; a first recording unit in which are recorded data representing a relationship between the driving current and optical output power, and data representing a relationship between the driving current and drive voltage; and a first calculating unit which calculates the driving currents to be allocated to the LDMGs so as to achieve maximum electrical to optical conversion efficiency, wherein the control unit allocates the driving currents to the LDMGs in accordance with the results calculated by the first calculating unit so that the LDMGs as a whole can achieve maximum electrical to optical conversion efficiency under conditions. |
| US09680288B2 |
Optical amplification device
An optical amplification device includes: a semiconductor optical amplifier; a first detector that detects an input optical power of the semiconductor optical amplifier; a second detector that detects an output optical power of the semiconductor optical amplifier; and a controller that controls a driving current of the semiconductor optical amplifier, wherein the controller supplies a predetermined driving current to the semiconductor optical amplifier when an optical signal is not input to the semiconductor optical amplifier, the second detector detects an optical power of Amplified Spontaneous Emission (ASE) output from the semiconductor optical amplifier when the predetermined driving current is supplied to the semiconductor optical amplifier, and the controller controls the driving current of the semiconductor optical amplifier based on the input optical power of the semiconductor optical amplifier detected by the first detector, and the optical power of the ASE. |
| US09680285B2 |
Laser light-source apparatus and laser pulse light generating method
A laser light-source apparatus includes: fiber amplifiers and a solid state amplifier configured to amplify pulse light output from a seed light source based on gain switching; nonlinear optical elements configured to perform wavelength conversion on the pulse light output from the solid state amplifier; an optical switching element configured to permit or stop propagation of pulse light from the fiber amplifier to the solid state amplifier; and a control unit configured to control the optical switching element in such a manner that the propagation of the light is stopped in an output period of the pulse light from the seed light source, and permitted in a period other than the output period of the pulse light from the seed light source. |
| US09680284B2 |
Lessening variations of spectral characteristic of an optical device
Devices and methods for lessening a thermal dependence of gain profile of an optical amplifier are disclosed. An optical beam is split in a plurality of sub-beams with a thermally variable power splitting ratio, e.g. one sub-beam may travel a longer optical path length than another. When the sub-beams are recombined, they interfere with each other, causing the throughput to be wavelength dependent. An amplitude of this wavelength dependence is thermally variable due to the thermally variable power splitting ratio. The thermally variable power splitting ratio and the optical path length difference are selected so as to offset a thermal variation of a spectral gain profile of an optical amplifier. |
| US09680281B2 |
Laser system having switchable power modes
In a method, a laser pump module is set to a first power mode and pump energy is output at a first power level through the activation of a first subset of laser diodes. Laser light is emitted from a gain medium at the first power level in response to absorption of the pump energy. An operator input corresponding to a power mode setting is received. The laser pump module is switched to a second power mode and pump energy is output at a second power level through the activation of a second subset of the laser diodes. Laser light is emitted from the gain medium at the second power level in response to absorption of the pump energy. |
| US09680278B2 |
Semiconductor optical cryocooler
There is provided a laser cooling apparatus including: a laser for providing an emission; a silicon-on-insulator substrate; and a thin film microstructure thermally anchored to the silicon-on-insulator substrate, the thin film microstructure being made from a material selected from either a II-VI binary compound semiconductor or a II-VI tenary compound semiconductor. |
| US09680277B2 |
Slab amplifier, and laser apparatus and extreme ultraviolet light generation apparatus including slab amplifier
There is provided a slab amplifier including an optical system (48, 51) provided in a chamber (47) to allow a seed beam having entered from a first window into the space between a pair of electrodes (42, 43) to be repeatedly reflected between the space so that the seed beam is amplified to be an amplified beam; a first aperture plate (61) provided between the first window and the electrodes, and having an opening of a dimension equal to or greater than a cross-section of the seed beam and equal to or smaller than a dimension of the first window; and a second aperture plate (62) provided between the second window and the electrodes, and having an opening of a dimension equal to or greater than a cross-section of the amplified beam and equal to or smaller than a dimension of the second window. |
| US09680276B2 |
Vision enhancement illuminators
An illuminator includes a short wave infrared (SWIR) laser, a lens collimator, a first beam shaping diffuser, a second beam shaping diffuser, and a bandpass filter. The lens collimator is optically coupled to the laser for diverging a beam emitted by the laser. The first beam shaping diffuser is optically coupled to the lens collimator to diffuse a diverged beam produced by the lens collimator. The second beam shaping diffuser is optically coupled to the first beam shaping diffuser to further diffuse a diffused beam produced by the first beam shaping diffuser. The bandpass filter is optically connected to the second beam shaping diffuser configured to filter the emissions of a further diffused beam produced by the second beam shaping diffuser. |
| US09680275B2 |
Wire singulating device
A wire singulating device includes a stationary plate and a movable plate that define a wire funnel and a wire channel therebetween. The movable plate is movable relative to the stationary plate to control a width of the wire channel. The wire funnel receives a wire bundle that includes plural wires. The wire channel is below the wire funnel and receives the wires from the wire funnel through a top opening in the wire channel. The wire channel directs the wires one at a time to a take away zone below a bottom opening of the wire channel. A wire transfer member below the bottom opening of the wire channel has a slot that receives the wire in the take away zone. The wire transfer member moves relative to the stationary plate and the movable plate to separate the wire in the slot from the wire bundle. |
| US09680270B2 |
Apparatus for enhanced merchandise display
A power distribution apparatus including a power supply conduit extending a length of a fixture and at least one power tap connected into the conduit, one embodiment of which may feature a saddle and at least one prong making operative contact with the power supply conduit. An electronic control module may be located proximate the saddle. The power tap may also be connected to a power distribution trough, which may have a plurality of walls, with lips, about a base. Power conductor strips may extend from the prongs along a length of the trough. Product enhancement devices may then access the power distribution trough at any point along the power distribution trough's length. A power-out-connector may be positionable along a power distribution trough for enhancement device access. The power-out-connector may feature at least one spring prong which interfaces with at least one lip and at least one power conductor strip. |
| US09680268B1 |
Genderless electrical connectors
Various components and methods related to electrical connectors are disclosed. The electrical connectors can be configured to receive a plurality of cables. The electrical connectors can be configured to accommodate a plurality of cables so as to provide a high density packaging within each of the pair of electrical connectors. In order to provide appropriate shielding against electric flux and to reduce noise, each of the plurality of cables can be retained within a genderless insert that can be inserted through each of the pair of electrical connectors. Each of the genderless inserts can include an engagement end that allows the interconnection of the cables retained within the pair of electrical connectors. In some examples, the engagement end of each of the genderless inserts includes both a male and female component. |
| US09680265B2 |
Female connector and method for manufacturing the same
The present disclosure relates to a female connector and a method for manufacturing the same. The female connector coupled with a male terminal unit in which a plurality of male terminals are arranged includes: a housing configured to have one side provided with a male insertion hole into which the male terminal unit is inserted and the other side provided with an insertion groove; a body configured to be inserted into the insertion groove to be coupled with the housing; and a female terminal configured to be formed on a surface of the body and provided with a pattern part electrically connected to the male connector by activating the surface by a laser. |
| US09680263B2 |
Coaxial cable connector having electrical continuity member
A coaxial cable connector includes, in one embodiment, a body, post, coupler and continuity member. The continuity member has an anchored post contact portion and a plurality of arcuate coupler contact portions. The connector is configured to form an electrical grounding continuity path. |
| US09680261B2 |
Intrinsic safe in-line adaptor with integrated capacitive barrier for connecting a wireless module with antenna
An intrinsic safe in-line adaptor with an integrated capacitive barrier for connecting a wireless module with an antenna. The in-line adaptor (e.g., N-type to N-type) can be designed to include an intrinsic safe circuit and the integrated capacitive barrier. The intrinsic safe circuit further includes a multi-layer PCB and the PCB can be potted and sealed with a mechanical metal casing. The intrinsic safe capacitive barrier can be integrated with a coaxial connector and mounted as part of a flameproof enclosure to meet an explosion safety standard and an intrinsic safety requirement. The mechanical metal casing can be isolated by the enclosure (e.g., rubber) to meet isolation requirements. The wireless module can be directly connected with the antenna utilizing the in-line adaptor via the coaxial connector and without any specific cable assembly. |
| US09680259B2 |
Electrical jack with a plurality of parallel and overlapping capacitive plates
An electrical connector for transmitting data signals between the insulated conductors of a first data cable and corresponding insulated conductors of a second data cable, including a first part having a socket shaped to at least partially receive a plug of said first data cable; a second part having a plurality of insulation displacement contact slots shaped to receive end sections of the conductors of the second data cable; and a plurality of electrically conductive contacts including resiliently compressible spring finger contacts extending into the socket for electrical connection with corresponding conductors of the first cable; insulation displacement contacts seated in corresponding insulation displacement contact slots for effecting electrical connection with corresponding conductors of the second data cable; and mid sections extending therebetween, wherein relative movement between the mid sections of the contacts is inhibited by a fastener. |
| US09680258B2 |
Plug comprising a pin pivoted out of a socket
A plug (1) for electrical equipment, the plug comprising a pin (2) and the pin comprising an electrical terminal contact, the plug further comprising a housing (3), the plug arranged to be received in a socket (10), wherein the pin and the housing configured to enable the pin to be pivoted out of the socket by way of a force applied to a cable entry region of the plug by a cable attached to the plug. |
| US09680257B2 |
Card holding member and card connector
A card holding member is provided which is able to hold a card having terminal members and which is able to be inserted into a card connector. The card holding member includes a frame portion, side frame portions, and a movable lock portion. The frame portion includes a front frame portion positioned forward in the insertion direction of the card holding member into the card connector. The side frame portions are connected at both ends to the front frame portion. The movable lock portion is positioned on a side frame portion and is able to engage and disengage from a lock portion on the card connector. The movable lock portion receives force from the lock portion of the card connector forward in the insertion direction when engaging the lock portion of the card connector. |
| US09680255B2 |
Plug connector having a latching system
A plug-in connector includes a latching system, for being received in and latched to an additional plug-in connector. The latching system is arranged on a connector housing and comprising at least one latching tab having a latching lug. The latching tab includes a pressure tab that can be positioned against the connector housing in order to exert a spring force. |
| US09680253B2 |
Connectors to connect electronic devices and other devices
An example electronic device is provided in accordance with an aspect of the present disclosure. The electronic device includes a housing having at least a front section and a rear section that is opposite to the front section, a connector embedded in a center of the rear section, wherein the connector includes a connection portion to electronically connect the electronic device to an external system and an attachment portion to mechanically attach the connector to an external system. |
| US09680251B2 |
Gapping measurement sensor for HV connector
A cable for connecting to a connector of a high-voltage device includes an integral yield sensor. The yield sensor may be a pressure or force sensor, or a displacement sensor, including a stator part and a mobile part, and a spring for maintaining a compression force on the end portion of the cable towards the connector of the high-voltage device. The displacement sensor can include a Hall effect sensor and a linear array of magnetic elements arranged such that the Hall effect sensor moves relative to the linear array if there is any movement between the stator and mobile parts of the sensor, The magnetic field readings are interpreted in order to determine the amount of movement. A system for controlling a high voltage device in response to pressure and other information received from sensors in the cable is also provided. |
| US09680247B1 |
Round terminal with low profile cap
An electric connector terminal body defines an interior space that extends along an axis. An electric contact located within the interior space includes a contact base and a plurality of contact arms that extend from the contact base toward an outer end of the terminal body. An end cap located on the outer end of the terminal body includes a cap base that defines a cap opening that is co-axial with the interior space. The end cap also includes a flange that extends from the cap base in an inner direction into the interior space of the terminal body. The flange includes an engagement tab that extends from the flange in a radial direction generally perpendicular to the axis of the interior space and engages a terminal groove located in a wall of the interior space. |
| US09680240B2 |
Connectors including apertures for grounding outer conductors of conduits and connectors including grounding grooves for grounding outer conductors of conduits
Connectors including apertures for grounding outer conductors of conduits and connectors including grounding grooves for grounding outer conductors of conduits are disclosed. In some embodiments, a connector includes a bore, a gripping portion axially surrounding the bore, a generally cylindrical aperture for receiving a grounding wire, and a securing port for securing the grounding wire in the aperture. An exterior gripping surface of the gripping portion is symmetric. The generally cylindrical aperture extends along an aperture centerline through at least a portion of the gripping portion. The securing port extends along a securing port centerline and intersects the generally cylindrical aperture. In other embodiments, a connector includes a grounding groove extending at least partially around an outer diameter of the connector that is adapted to receive the grounding wire, and a securing port longitudinally offset from the grounding groove and extending along a securing port centerline. |
| US09680223B2 |
Mobile device and manufacturing method thereof
A mobile device includes a ground plane, a first radiation branch, and a second radiation branch. The second radiation branch is coupled to the ground plane, and is disposed adjacent to the first radiation branch. An antenna structure is formed by the first radiation branch and the second radiation branch. The first radiation branch is fed from a signal source. The second radiation branch is excited by the first radiation branch through coupling therebetween. |
| US09680222B2 |
Antenna structure and wireless communication device using the same
A wireless communication device includes a metallic housing and an antenna structure. The metallic housing includes a bottom frame and a side frame spaced from the bottom frame. The antenna structure includes a feed end plate, a ground end plate, a main radiator, and a coupling section. The ground end plate is coupled to the bottom frame. The main radiator is coupled between the feed end plate and the side frame. The coupling section is coupled to the main radiator and extending parallel to the bottom frame. A first end of the coupling section is coupled to a distal end of the feed end plate, and a second end of the coupling section extends towards the ground end plate, current is coupled from the feed end plate to the ground end plate via the coupling section and is coupled from the coupling section to the bottom frame. |
| US09680220B2 |
Method and apparatus for transitioning between cell sites
A system that incorporates the subject disclosure may include, for example, a circuit for initiating a first multiple-input and multiple-output (MIMO) communication session with a primary base station, and initiating a second MIMO communication session with a first secondary base station of a plurality of secondary base stations without terminating the first MIMO communication session with the primary base station. The primary base station can include a primary antenna system having a first communication range, while each of the plurality of secondary base stations can include a secondary antenna system having a second communication range that is a subset of the first communication range of the primary antenna system. The plurality of secondary base stations can correspond to a plurality of small cell sites distributed within the first communication range of the primary base station. Other embodiments are disclosed. |
| US09680219B2 |
Antenna switching devices, systems, and methods
This disclosure provides systems, methods, and apparatus for antenna switching. In one embodiment, a wireless communication apparatus is provided. The wireless communication apparatus includes a plurality of antennas including a first antenna and a second antenna. The wireless communication apparatus further includes at least one receive circuit including a first receive circuit. The wireless communication apparatus further includes a controller configured to selectively switch the first receive circuit from receiving wireless communications via the first antenna to receive wireless communications via the second antenna if one or more performance characteristics of the first antenna are below a threshold in one or more measurement cycles, the one or more measurement cycles including a wake-up cycle outside of a predetermined wake-up cycle. Other aspects, embodiments, and features are also claimed and described. |
| US09680218B2 |
Method and apparatus for controlling an antenna
A method and apparatus for controlling an antenna is provided. A load on a second antenna of a device is determined, the device comprising at least one processor, a first antenna, a variable tuning circuit connected to the first antenna, and the second antenna, wherein the processor determines the load. The processor controls the variable tuning circuit based on the load on the second antenna to change a match of the first antenna. |
| US09680217B2 |
Dynamic real-time calibration for antenna matching in a radio frequency receiver system
Real-time calibration of a tunable matching network that matches the dynamic impedance of an antenna in a radio frequency receiver system. The radio frequency receiver system includes two non-linear equations that may be solved to determine the reflection coefficient of the antenna. The tunable matching network is repeatedly perturbed and the power received by the antenna is measured after each perturbation at the same node in the matching network. The measured power values are used by an optimizer in converging to a solution that provides the reflection coefficient of the antenna. The reflection coefficient of the antenna may be used to determine the input impedance of the antenna. The elements of the matching circuit are then adjusted to match the input impedance of the antenna. |
| US09680214B2 |
Antenna assemblies
Embodiments are provided for antenna assemblies. An example apparatus includes a first plate forming a first ground plane for an antenna; a second plate forming a second ground plane for a circuit, wherein a first edge of the first plate is orthogonally adjacent to a second edge of the second plate; and a coupler to form a capacitive coupling between the first ground plane and the second ground plane. |
| US09680212B2 |
Capacitive grounding methods and apparatus for mobile devices
Grounding apparatus for mobile devices and methods of utilizing and manufacturing the same. In one embodiment, an outer metallized surface of a mobile device is configured to capacitively couple a metal back cover to the device ground. Specifically, in one implementation, an exterior surface of the mobile device is metalized and coupled to the device ground via galvanic contacts. The exterior metalized surface is configured to be capacitively coupled a metal back cover of a mobile device to the device ground when the back cover is installed on the mobile device. By capacitively coupling the back cover to the device ground via the exterior metalized surface, the need to otherwise ground the back cover through the use of galvanic contacts is obviated, thereby reducing the number of components needed. |
| US09680210B2 |
Antenna arrangement
An antenna arrangement including a first antenna element connected to a first feed point and having a first electrical length; a second antenna element connected to a second feed point, different to the first feed point, and including: a first portion which extends from the second feed point and has a second electrical length, similar to the first electrical length, which enables the first portion to electromagnetically couple with the first antenna element, and a second portion which extends from the second feed point and has a third electrical length, different to the first electrical length of the first antenna element and to the second electrical length of the first portion. |
| US09680209B2 |
RF antenna and hearing device with RF antenna
The present disclosure relates to an RF antenna adapted to receive and/or transmit electromagnetic RF signals within a first frequency range enclosing a first frequency of resonance of the RF antenna, the RF antenna comprising: an electrically conductive antenna element having a feed for electrically connecting to an RF transmitter and/or an RF receiver; an electronic component adapted to receive and/or provide one or more electric signals from/to an electronic circuit within a second frequency range not overlapping the first frequency range; and one or more electric leads electrically connected to lead the one or more electric signals between the electronic component and the electronic circuit, each of the one or more electric leads being electrically connected to the electronic circuit through a respective inductor adapted to reflect and/or attenuate signals within the first frequency range and pass signals within the second frequency range. |
| US09680202B2 |
Electronic devices with antenna windows on opposing housing surfaces
An electronic device housing may have a base unit and a lid. Aligned antenna windows may be formed on opposing upper and lower surfaces of the base unit along a hinge. Antenna structures that are located between respective upper and lower antenna windows on the upper and lower surfaces may be based on a pair of antennas that are coupled to switching circuitry that can select which antenna to switch into use or may be based on an antenna having a position that may be adjusted relative to the upper and lower antenna windows using a mechanical coupling to the lid or using a positioner. A sensor such as a lid position sensor may monitor how the lid is positioned relative to the base unit. Information from the lid position sensor may be used in adjusting the antenna structures to optimize performance. |
| US09680198B2 |
Lightning protection system for radome and associated assembly method
A lightning protection system for a radome, the system comprising at least one lightning protection strip positioned on an inner wall of the radome, wherein the lightning protection strip defines, on the inner wall of the radome, a curve that is substantially perpendicular, at all points thereof, to the polarization direction of the electrical field vector radiated by an antenna across from the inner wall of the radome. |
| US09680197B2 |
Micro bandpass filter
A micro bandpass filter comprises a substrate, a first signal transmission member, a second signal transmission member and a resonator structure. The resonator structure includes a plurality of microstrip lines. The present invention realizes the function of a bandpass filter in a smaller area via curving the first signal transmission member, the second signal transmission member and the resonator structure. |
| US09680193B2 |
Electrically rechargeable, metal anode cell and battery systems and methods
The invention provides for a fully electrically rechargeable metal anode battery systems and methods of achieving such systems. An electrically rechargeable metal anode cell may comprise a metal electrode, an air contacting electrode, and an aqueous electrolyte separating the metal electrode and the air contacting electrode. In some embodiments, the metal electrode may directly contact the liquid electrolyte and no separator or porous membrane is needed between the air contacting electrode and the electrolyte. Rechargeable metal anode cells may be electrically connected to one another through a centrode connection where a metal electrode of one cell and an air contacting electrode of a second cell are electrically connected. Air tunnels or pathways may be provided between individual metal anode cells arranged in a stack. In some embodiments, an electrolyte flow management system may also be provided to maintain liquid electrolyte at constant levels during charge and discharge cycles. |
| US09680189B2 |
Solar cell phone
A solar cell phone includes a housing having a keypad, a display screen, other electronic components and a rechargeable battery. A diode switch within the housing is electrically connected to the rechargeable battery. A plurality of solar panels are mounted to the housing and electrically connected to the diode switch. The diode switch will allow the solar panels to supply electrical power to the rechargeable battery. An auxiliary battery within the housing receives electrical power from the solar panels. The auxiliary battery will store the electrical power to recharge the rechargeable battery when the diode switch is in a non-operative position, so that the rechargeable battery will continue to operate the keypad, the display screen and the other electronic components within the housing. |
| US09680187B2 |
Battery removal apparatus
This application relates generally to battery removal apparatuses. For example, one battery removal apparatus disclosed herein comprises a pull tab configured to be disposed between a battery and a casing of a portable computing device. The pull tab is shaped such that at least one area of the battery and the casing are exposed to one another when the battery, the pull tab and the casing are compressed together. An adhesive layer is shaped to cover the at least one exposed area such that the battery adheres to the casing, and the pull tab is reinforced so as to prevent the pull tab from tearing when used to remove the battery from the portable computing device. Other battery removal apparatuses include a pull string battery removal apparatus as well as a battery removal apparatus that incorporates both a pull tab and one or more pull strings. |
| US09680176B2 |
Energy storage battery
A positive electrode electrolyte (22) and a negative electrode electrolyte (32) that are used in this energy storage battery have a pH within the range from 2 to 8 (inclusive). An ion exchange membrane, which is obtained by graft-polymerizing styrenesulfonate to a resin film base material that uses an ethylene-vinyl alcohol copolymer as a matrix, is used as a diaphragm (12) of this energy storage battery. |
| US09680175B2 |
Integrated fuel line to support CPOX and SMR reactions in SOFC systems
A fuel cell system comprises at least one fuel cell stack, a CPOX reactor, and a conduit for providing a fuel stream to the at least one fuel cell stack through the CPOX reactor during both a start up and a steady state modes of operation of the system. |
| US09680174B2 |
Redox flow battery system and method of controlling it
A novel multi cell stack architecture has specific features allowing deployment of simple electrical instrumentation of data collection/monitoring of crucial hydraulic, electrical and electrochemical quantities, on the basis of which the operator or electronic controller is able to gather/process critical information of such a depth and enhanced reliability, for immediately identifying any cell in “state of sufferance” and eventually to exclude it from the system and possibly substitute it with a spare cell. A method of monitoring/controlling the operation of an all-vanadium redox flow battery system is also disclosed. |
| US09680171B2 |
Methods for operating a fuel cell system
Purge valves that are manually turned ON but are automatically or electrically turned OFF as the fuel cell production of electricity reaches a predetermined level, e.g., steady state or thereabout are disclosed. The purge valve may be opened at system start-up, or may be opened at system shut-down so that the purge valve is armed and the fuel cell system is purged at the next start-up. Also disclosed is an integrated fluidic interface module that contains various fluidic components including one of these purge valves. The integrated fluidic interface module can operate passively or without being actively controlled by a processor. Methods of operating a fuel cell system, wherein the fuel cell system is purged at system start-up, are also disclosed. The purging automatically stops when the anode plenum is fully purged and replaced with fuel. |
| US09680167B2 |
System for adjusting temperature of cooling-liquid for fuel cell, and thermostat valve
A system for adjusting temperature of cooling-liquid comprises: a radiator; a cooling-liquid circulation flow-channel; a radiator bypass flow-channel; a thermostat valve; and a valve bypass flow-channel through which the cooling-liquid of the radiator bypass flow-channel is allowed to flow in a predetermined amount even if the thermostat valve is completely closed. |
| US09680165B2 |
Separator and fuel cell with the same
A separator for a fuel cell is provided. The separator is disposed at both sides of a membrane-electrode assembly and is configured to supply a reaction gas to the membrane-electrode assembly. In addition, the separator includes a conductive microporous body that is formed on a reaction surface corresponding to the membrane-electrode assembly and a channel unit that is connected to an inlet manifold and an outlet manifold through which the reaction gas flows and is configured to guide the reaction gas to the reaction surface. |
| US09680162B2 |
Stainless steel sheet for a separator for a solid polymer fuel cell and a solid polymer fuel cell employing the separator
A stainless steel member for a separator of a solid polymer fuel cell has excellent cell properties with little deterioration in performance over long periods of operation without worsening of the corrosion resistance of a stainless steel separator. The stainless steel member has a stainless steel base metal, and a passive film and electrically conductive precipitates both provided on a surface of the stainless steel base metal. The electrically conductive precipitate penetrates the passive film and includes a substance originating from the stainless steel base metal. An electrically conductive layer comprising a nonmetallic electrically conductive substance is preferably provided on the surface of the passive film, and the electrically conductive layer is preferably electrically connected to the stainless steel base member through the electrically conductive precipitates. |
| US09680160B2 |
Extended two dimensional metal nanotubes and nanowires useful as fuel cell catalysts and fuel cells containing the same
Metal nanotubes are provided comprising a composition having formula (M1)NT: wherein M1=Pt, Pd, or Au; wherein the nanotubes have: a wall thickness of from 2 to 12 nm; an outer diameter of from 30 to 100 nm; and a length of from 5 to 30 μm. Metal nanowires are also provided comprising a composition having formula (M2)NW: wherein M2=Ag or Cu; wherein when M2=Ag, the nanowires have a diameter of from 25 to 60 nm and a length of from 1 to 10 μm; and when M2=Cu, the nanowires have a diameter of from 50 to 100 nm and a length of from 10 to 50 μm. In other embodiments, fuel cells are also described having at least one anode; at least one cathode; an electrolyte membrane between the at least one anode and at least one cathode; and a catalyst comprising either of the above described metal nanotubes or nanowires. |
| US09680158B2 |
Highly active and durable fuel cell electro-catalyst with hybrid support
A fuel cell includes: (1) an anode; (2) a cathode; and (3) an electrolyte disposed between the anode and the cathode. At least one of the anode and the cathode includes an electro-catalyst dispersed on a hybrid support, the hybrid support includes a first, carbon-based support and a second support different from the first, carbon-based support, and a weight percentage of the second support is at least 10% relative to a combined weight of the first, carbon-based support and the second support. |
| US09680156B2 |
Composition, polymer thereof, electrode and electrolyte membrane for fuel cell, and fuel cell including the same
A composition including a compound having a fluorine functional group, a polymer as a polymerization product of the composition, an electrode and an electrolyte membrane for a fuel cell, which include the composition or the polymer thereof, and a fuel cell including at least one of the electrode and the electrolyte membrane. |
| US09680142B2 |
Polyolefin microporous membrane, separator for non-aqueous secondary battery, non-aqueous secondary battery and method of producing polyolefin microporous membrane
A polyolefin microporous membrane, the membrane having, when measured by DSC, a degree of crystallinity of from 65 to 85%, a lamellar crystal/crystal ratio of from 30 to 85%, a crystal length of from 5 nm to 50 nm and an amorphous length of from 3 nm to 30 nm, and a polyolefin microporous membrane, the membrane having, when measured by X-ray diffractometry, crystal size of from 12.5 nm to 13.5 nm and a degree of crystallinity of from 64 to 68%. |
| US09680141B2 |
Separator comprising an organic-inorganic adhesion promoter
The invention relates to a process for producing a separator comprising the steps of: providing a sheetlike porous substrate, a solvent, ceramic particles and an adhesion promoter; preparing a slip by mixing the solvent, the adhesion promoter and the ceramic particles; coating the substrate with the slip and thermally drying the coated substrate to obtain the separator. The problem addressed is that of specifying a process useful for producing separators having a higher ceramic content. The problem is solved when the solvent used is a mixture of water and at least one organic component; the adhesion promoter used is a mixture of silanes and at least one thermally crosslinkable acrylic polymer; the slip is admixed with a carboxylic acid preparation and also with a defoamer component free from silicone oil. |
| US09680138B2 |
Battery pack
Battery cells are fixed by a cell holder and are housed inside a case in a state where both electrodes are sandwiched by a positive-electrode current collecting plate and a negative-electrode current collecting plate, and springs are arranged above and under the current collecting plates. Claws are provided on side surfaces of the case, which can temporarily fix the springs to the current collecting plates at the time of assembly and prevents the case from being ejected suddenly when a fastener is released at the time of disassembly. |
| US09680134B2 |
Packaging method, packaging structure and display device
The present disclosure provides a packaging method, a packaging structure and a display device. The packaging method comprises forming a pattern of a packaging adhesive on a packaging area of a first substrate, and forming a heat dissipating structure on the packaging area of any of the first substrate and a second substrate; attaching the first substrate and the second substrate, and aligning the packaging area of the first substrate with that of the second substrate; illuminating the pattern of the packaging adhesive by a laser beam to melt and frit it, so as to form a packaging adhesive structure between the first and second substrates. In the present invention, in the case that the heat dissipating structure is manufactured on the packaging area, when the packaging adhesive is illuminated by the laser beam to be melted, the heat dissipating structure can quickly dissipate the heat, effectively suppress the rapid increase of the substrate temperature caused by the laser illumination, and reduce the damage to the drive back plate. |
| US09680132B1 |
Display device and optical film
A display device including a substrate, a light absorption layer, an optical matching layer, a first transparent electrode, a light emitting layer, and a second transparent electrode is provided. The light absorption layer is disposed on the substrate, and the optical matching layer is disposed on the light absorption layer. The first transparent electrode is disposed on the optical matching layer, the light emitting layer is disposed on the first transparent electrode, and the second transparent electrode is disposed on the light emitting layer. An output luminance and a reflectance of ambient light are controlled by adjusting refractive indices of the optical matching layer and the light absorption layer. |
| US09680127B2 |
Display device and manufacturing method thereof
In an organic EL display device, an improvement in the performance of a barrier film that blocks entry of a substance that causes degradation, such as moisture, into an organic electroluminescent element is achieved. The organic EL display device includes the barrier film, which is a stacked film including a barrier base material layer made of silicon oxide or silicon nitride and a base material coating layer in contact with an impregnated barrier base material layer. The barrier film blocks transmission of a substance that degrades the organic electroluminescent element. Nano-ink is applied on a surface of the barrier base material layer, and the barrier base material layer is impregnated with the nano-ink. The barrier base material layer subjected to the impregnation treatment serves as the impregnated barrier base material layer, while the nano-ink after impregnation serves as the base material coating layer. |
| US09680126B2 |
Organic light emitting diode
Disclosed is an organic light emitting diode (OLED) that includes an OLED panel; a back cover supporting the OLED panel and including a reinforcing bent portion; and a heat dissipation member between the OLED panel and the back cover. |
| US09680122B1 |
Organic light emitting display device and method of manufacturing the same
An organic light emitting display device may include: a cell array comprising gate lines and data lines intersecting each other on a substrate so as to define a plurality of pixel areas, a plurality of thin film transistors formed at intersections between the gate lines and the data lines to correspond to the plurality of pixel areas, and a protective film evenly formed over the substrate to cover the thin film transistors; a plurality of first electrodes formed such that portions of an metal oxide layer corresponding to emission areas of the respective pixel areas, is made conductive, the metal oxide layer evenly disposed on the protective film; a bank constituting the remaining portion of the metal oxide layer in which the first electrodes are not formed and formed so as to have insulating properties; an emission layer formed over the metal oxide layer; and a second electrode formed on the emission layer so as to face the first electrodes. |
| US09680121B2 |
Organic light-emitting diode and an electronic device including an organic light-emitting diode
The present invention discloses an organic light-emitting diode (OLED) and an electronic device, wherein the OLED includes a first carrier transport layer and a second carrier transport layer that are set opposite to each other, and a light-emitting layer; the light-emitting layer includes a first light-emitting sub-layer with a hollow structure, and a second light-emitting sub-layer which includes a body part and a projecting part, wherein the projecting part projects from the body part and is accommodated in the hollow structure; wherein a surface of the first light-emitting sub-layer and a surface of the projecting part form the first surface of the light-emitting layer, and a surface of the body part forms the second surface of the light-emitting layer. By the present invention, the working voltage is lowered, the power consumption is reduced, and in addition, the manufacturing process is simplified due to the reduction of the number of layers. |
| US09680115B2 |
Light-emitting device and manufacturing method thereof
A light-emitting device having a curved light-emitting surface is provided. Further, a highly-reliable light-emitting device is provided. A substrate with plasticity is used. A light-emitting element is formed over the substrate in a flat state. The substrate provided with the light-emitting element is curved and put on a surface of a support having a curved surface. Then, a protective layer for protecting the light-emitting element is formed in the same state. Thus, a light-emitting device having a curved light-emitting surface, such as a lighting device or a display device can be manufactured. |
| US09680110B2 |
Compounds for use in opto-electrical devices
A composition for use in fabricating opto-electrical devices comprising a solution processable triazine host material and a phosphorescent moiety. |
| US09680107B2 |
Compound and organic electronic device comprising the compound
Provided are a novel compound and an organic electronic device (OED) including the same. The novel compound has better hole injection and hole transport properties than a conventional material, and thus may enhance thermal stability and efficiency when used as a material for a hole injection or hole transport layer of the OED. |
| US09680105B2 |
Hybrid carbon-metal interconnect structures
Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed. |
| US09680104B2 |
Photoelectric conversion device, solid-state image pickup unit, and electronic apparatus including ternary system of organic semiconductors
A solid-state image pickup unit of the invention includes a plurality of pixels, each of which includes a photoelectric conversion element. The photoelectric conversion element includes a photoelectric conversion layer; and first and second electrodes provided with the photoelectric conversion layer in between, the photoelectric conversion layer including a first organic semiconductor of a first conductive type and a second organic semiconductor of a second conductive type, and being configured by addition of a third organic semiconductor made of a derivative or an isomer of one of the first and second organic semiconductors. |
| US09680101B2 |
Copolymer and organic solar cell comprising same
The present specification provides a copolymer and an organic solar cell including the same. |
| US09680097B2 |
Organic thin film transistors and methods for their manufacturing and use
Methods of forming an organic thin film transistor are provided. The methods include providing a substrate and depositing and patterning a gate electrode on a first surface of the substrate. The methods include dispensing a first droplet of an insulating material on the gate electrode on the substrate and dispensing a second droplet of a semiconductor material on a first surface of the first droplet. The second droplet forms a hydrophobic structure having a central cavity. The methods also include dispensing a third droplet of a conductor material on a first surface of the second droplet such that the conductor material substantially fills the central cavity of the hydrophobic structure and forms a conductor material layer around the central cavity to define a source electrode and a drain electrode of the organic thin film transistor. |
| US09680094B2 |
Memory device and method for manufacturing the same
According to one embodiment, a memory device includes a first electrode, a first resistance change layer, a first insulating section, a second electrode and an intermediate layer. The first resistance change layer is provided on the first electrode. The first insulating section is provided on the first resistance change layer. The second electrode is provided on the first resistance change layer. The second electrode is in contact with the first resistance change layer. The intermediate layer is provided between the second electrode and the first insulating section. The intermediate layer is in contact with the second electrode and the first insulating section. |
| US09680085B2 |
Ceramic powder, piezoelectric ceramic, piezoelectric element, and electronic equipment
A ceramic powder contains a metal oxide represented by the following general formula (1). The ceramic powder has a single perovskite-type crystal phase. The ceramic powder is composed of particles having an average equivalent circular diameter in the range of 100 nm or more and less than 1000 nm and has a ratio c1/a1 in the range of 1.000≦c1/a1≦1.010, wherein c1 and a1 denote the c-axis length and a-axis length, respectively, of unit cells of the perovskite-type metal oxide, c1 being greater than or equal to a1. formula (1)(Ba1-xCax)α(Ti1-y-zZryMnz)O3(0.9900≦α≦1.0100, 0.125≦x≦0.300, 0.020≦y≦0.095, 0.003≦z≦0.016). |
| US09680071B2 |
Light emitting device having substrate including heat dissipation terminals
A light emitting device includes a substrate having a first main surface that serves as the light extraction surface, a second main surface that is opposite the first main surface, and a mounting surface that is adjacent to at least the second main surface, and that is provided an insulating base material, a pair of connection terminals disposed on the second main surface, and a heat dissipation terminal disposed on the second main surface and between the pair of connection terminals; a light emitting element that is mounted on the first main surface of the substrate and; a sealing member that seals the light emitting element and is formed substantially in the same plane as the substrate on the mounting surface. |
| US09680066B2 |
Phosphor, light emitting element, and light emitting device
The present invention relates to an Mn4+-activated complex fluoride phosphor with improved moisture resistance due to modification of the particle surface, and a light emitting element and light emitting device having excellent color rendering properties and stability due to the use of this phosphor.The phosphor of the present invention is characterized in that it is represented by the general formula: A2MF6:Mn4+, wherein element A is an alkali metal element comprising at least K, element M is one or more metal elements chosen from among Si, Ge, Sn, Ti, Zr and Hf, F is fluorine, and Mn is manganese, wherein the phosphor comprises a Ca-containing compound on a particle surface. |
| US09680065B2 |
Light emitting device and light emitting device package including the same
A light emitting device and a light emitting device package are provided. The light emitting device may include a substrate, a light emitting structure provided under the substrate and including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first insulating layer configured to expose the second conductive semiconductor layer and provided on a lower edge of the light emitting structure, a first light permeable electrode layer provided under the second conductive semiconductor layer exposed by the first insulating layer, a second light permeable electrode layer provided under the first insulating layer and the first light permeable electrode layer, and a reflective layer provided under the second light permeable electrode layer. |
| US09680063B2 |
Semiconductor light-emitting device and semiconductor light-emitting device array
A semiconductor light-emitting device comprises an optical semiconductor multilayer disposed above a support substrate, which has a structure in which a first semiconductor layer having a first conductivity type, an active layer having light emitting properties, and a second semiconductor layer having a second conductivity type different from the first conductivity type are sequentially stacked from the support substrate side, in which a groove, which has a height exceeding at least the active layer from the support substrate side, is formed along an outer edge of the optical semiconductor multilayer, and which includes an external region being a region further outside than the groove, an inner region being a region further inside than the groove, and a connection region corresponding to a region where the groove is provided, in plan view. |
| US09680061B2 |
Patterned layer design for group III nitride layer growth
A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. |
| US09680060B2 |
Light emitting diode having a plurality of light emitting units
A light emitting diode includes a substrate including a concave-convex pattern having concave portions and convex portions, a first light emitting unit disposed on the substrate, a second light emitting unit disposed on the substrate, a first wire connecting the first light emitting unit to the second light emitting unit over the concave-convex pattern, and an insulation layer disposed between the concave-convex pattern and the wire. The insulation layer has a shape corresponding to the concave-convex pattern. |
| US09680059B2 |
Flip chip light emitting diode and method for manufacturing the same
A flip-chip light emitting diode, including a substrate, an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer series mounted along a height direction of the flip-chip light emitting diode. A P electrode is formed on the P-type semiconductor layer and an N electrode is formed on the N-type semiconductor. A top surface of the substrate is away from the light emitting layer. A plurality of micron main portions is formed on the top surface. An outer surface of each main body has a plurality of nanometer protrusions. A method for manufacturing the flip chip light emitting diode is also provided. |
| US09680053B2 |
Nitride semiconductor device
A nitride semiconductor device includes a transistor having a semiconductor stacked body formed on a substrate, and a pn light-emitting body formed on the semiconductor stacked body. The semiconductor stacked body includes a first nitride semiconductor layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than that of the first nitride semiconductor layer. The transistor includes: the semiconductor stacked body; a source electrode and a drain electrode formed away from each other on the semiconductor stacked body; and a gate electrode provided between the source electrode and the drain electrode and formed away from the source electrode and the drain electrode. The pn light-emitting body includes a p-type nitride semiconductor layer and an n-type nitride semiconductor layer to emit a light beam having an energy value higher than an electron trapping level existing in the semiconductor stacked body, in which the p-type nitride semiconductor layer of the pn light-emitting body is electrically connected to the gate electrode, and functions as a gate of the transistor. |
| US09680048B2 |
Method for producing a radiation-emitting semiconductor component
A method for producing a radiation-emitting semiconductor component is provided, comprising the following steps: —providing a growth substrate (1), —depositing a nucleation layer (2) on the growth substrate (1), —applying a structured dielectric layer (3) to the nucleation layer (2), —applying an epitaxial layer (4) by means of a FACELO process to the structured dielectric layer (3), —epitaxial growth of an epitaxial layer sequence (5) on the epitaxial layer (4), wherein the epitaxial layer sequence (5) comprises an active zone (6) that is suitable for producing electromagnetic radiation. |
| US09680047B2 |
Method for manufacturing polycrystalline silicon thin-film solar cells by means method for crystallizing large-area amorphous silicon thin film using linear electron beam
One embodiment of the present invention relates to a method of manufacturing polycrystalline silicon thin-film solar cell by a method of crystallizing a large-area amorphous silicon thin film using a linear electron beam, and the technical problem to be solved is to crystallize an amorphous silicon thin film, which is formed on a low-priced substrate, by means of an electron beam so as for same to easily be of high quality by having high crystallization yield and to be processed at a low temperature. To this end, one embodiment of the present invention provides a method of manufacturing polycrystalline silicon thin-film solar cell by means of a method for crystallizing a large-area amorphous silicon thin film using a linear electron beam, the method comprising: a substrate preparation step for preparing a substrate; a type 1+ amorphous silicon layer deposition step for forming a type 1+ amorphous silicon layer on the substrate; a type 1 amorphous silicon layer deposition step for forming a type 1 amorphous silicon layer on the type 1+ amorphous silicon layer; an absorption layer formation step for forming an absorption layer by radiating a linear electron beam to the type 1 amorphous silicon layer and thus crystallizing the type 1 amorphous layer and the type 1+ amorphous silicon layer; a type 2 amorphous silicon layer deposition step for forming a type 2 amorphous silicon layer on the absorption layer; and an emitter layer formation step for forming an emitter layer by radiating a linear electron beam to the type 2 amorphous silicon layer and thus crystallizing the type 2 amorphous silicon layer, wherein the linear electron beam is radiated from above type 1 and type 2 amorphous silicon layers in a linear scanning manner in which to reciprocate in a predetermined area. |
| US09680038B2 |
Photodetectors based on double layer heterostructures
A photodetector is provided with a thin film double layer heterostructure. The photodetector is comprised of: a substrate; a channel layer of a transistor deposited onto a top surface of the substrate; a source layer of the transistor deposited on the top surface of the substrate; a drain layer of the transistor deposited on the top surface of the substrate, the source layer and the drain layer disposed on opposing sides of the channel layer; a barrier layer deposited onto the channel layer; and a light absorbing layer deposited on the barrier layer. The light absorbing layer is configured to absorb light and, in response to light incident on the light absorbing layer, electrical conductance of the channel layer is changed through hot carrier tunneling from the light absorbing layer to the channel layer. |
| US09680037B2 |
Solar cell and method of manufacturing same, and solar cell module
A solar cell of the present invention includes a collecting electrode on one main surface of a photoelectric conversion section. The collecting electrode includes first and second electroconductive layers in this order from the photoelectric conversion section side, and an insulating layer between the first and second electroconductive layers, the insulating layer having an opening section formed therein. The first electroconductive layer is covered with the insulating layer, contains a low-melting-point material, and is conductively connected with a part of the second electroconductive layer via the opening section. The surface roughness of the second electroconductive layer is preferably 1.0 μm to 10.0 μm. The second electroconductive layer is preferably formed by a plating method. In order to conductively connect the first and second electroconductive layers, annealing of the first electroconductive layer by heating is preferably performed prior to forming the second electroconductive layer. |
| US09680035B1 |
Surface mount solar cell with integrated coverglass
Photovoltaic cells, methods for fabricating surface mount multijunction photovoltaic cells, methods for assembling solar panels, and solar panels comprising photovoltaic cells are disclosed. The surface mount multijunction photovoltaic cells include through-wafer-vias for interconnecting the front surface epitaxial layer to a contact pad on the back surface. The through-wafer-vias are formed using a wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers. |
| US09680030B1 |
Enhancement-mode field effect transistor having metal oxide channel layer
An enhancement-mode n-type field effect transistor is disclosed to have a metal oxide channel layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The metal oxide channel layer has a material selected from SnO2, ITO, ZnO, SnO2 and In2O3. The metal oxide channel layer has a thickness less than a threshold value to exhibit pinch-off behavior in transfer characteristics and has a mobility trend without saturation under positive operational voltage. |
| US09680026B2 |
Semiconductor device having gate electrode overlapping semiconductor film
A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions. |
| US09680024B2 |
Semiconductor device
To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer. |
| US09680019B1 |
Fin-type field-effect transistors with strained channels
Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain. |
| US09680018B2 |
Method of forming high-germanium content silicon germanium alloy fins on insulator
A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin. |
| US09680012B1 |
Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a top surface. The semiconductor device structure includes a first pillar structure over the substrate. The first pillar structure includes a first heavily n-doped layer, a first p-doped layer, an n-doped layer, and a first heavily p-doped layer, which are sequentially stacked together. The first pillar structure extends in a direction away from the substrate. |
| US09680010B1 |
High voltage device and method of fabricating the same
A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI. |
| US09680009B2 |
High voltage semiconductor device
In some embodiments, a semiconductor device includes a transistor, an isolation component, and a conductive layer. The transistor includes a source region and a drain region. The isolation component surrounds the source region. The conductive layer is configured for interconnection of the drain region. The conductive component is between the conductive layer and the isolation component, configured to shield the isolation component from an electric field over the isolation component. |
| US09680007B2 |
Method for fabricating a metal high-k gate stack for a buried recessed access device
A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain. |
| US09680001B2 |
Nitride semiconductor device
A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers. |
| US09680000B2 |
Terahertz radiating device and fabricating method for the same
The present invention relates to a terahertz radiating device, which includes a high electron mobility transistor (HEMT); a source provide to the HEMT; a gate right to the HEMT; a drain provide to the HEMT; a first antenna connected with the drain; a drain bias for applying a direct current (DC) voltage to the drain; and a source-gate connector for connecting the source and the gate in a device unit. Thereby, commercially available terahertz waves may be radiated, and high output power may be obtained. |
| US09679998B2 |
Bi-directional punch-through semiconductor device and manufacturing method thereof
In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor. |
| US09679997B2 |
Semiconductor device with suppressed two-step on phenomenon
A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front surface side of the bottom-body region, and a top-body region on a front surface side of the IGBT barrier region. A diode region is include with a bottom-anode region on a front surface side of the diode drift region, a diode barrier region on a front surface side of the bottom-anode region, a top-anode region on a front surface side of the diode barrier region, and a pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region. An impurity concentration of the top-body region is lower than an impurity concentration of the bottom-anode region. |
| US09679992B2 |
FinFET device and method
A fin field effect transistor (FinFET) and a method of forming the same are introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions. |
| US09679991B2 |
Method for manufacturing semiconductor device using gate portion as etch mask
Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion. |
| US09679989B2 |
Insulated gate type switching device and method for manufacturing the same
A method of manufacturing an insulated gate type switching device includes forming a gate trench that has a first portion with a first width in a first direction and a second portion with a second width in the first direction, the second width being wider than the first width. In an oblique implantation, second conductivity type impurities are irradiated at an irradiation angle inclined around an axis orthogonal to the first direction. The first width, the second width, and the irradiation angle are set such that the second conductivity type impurities are suppressed, at a first side surface of the first portion, from being implanted into a part below a lower end of a second semiconductor region, and at a second side surface of the second portion, the impurities are implanted into the part below the lower end of the second semiconductor region. |
| US09679987B2 |
Fabrication methodology for optoelectronic integrated circuits
A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) n-type modulation doped quantum well structure (MDQWS) structure with n-type charge sheet, ii) p-type MDQWS, iii) undoped spacer layer formed on the n-type charge sheet, iv) p-type layer(s) formed on the undoped spacer layer, v) p-type etch stop layer formed on the p-type layer(s) of iv), and vi) p-type layers (including p-type ohmic contact layer(s)) formed on the p-type etch stop layer. An etch operation removes the p-type layers of vi) for a gate region of an n-channel HFET with an etchant that automatically stops at the p-type etch stop layer. Another etch operation removes the p-type etch stop layer to form a mesa at the p-type layer(s) of iv) which defines an interface to the gate region of the n-channel HFET, and a gate electrode is formed on such mesa. |
| US09679979B2 |
Semiconductor structure for flash memory cells and method of making same
Semiconductor structures are presented. An exemplary semiconductor structure comprises a common source region having a sawtooth profile, and a flat erase gate disposed above the common source region. Methods of making semiconductor structures are also presented. An exemplary method comprises forming a plurality of trenches in a substrate thereby forming a plurality of active regions; forming a common source region in the substrate in a direction perpendicular to the active regions. The exemplary method further comprises, after forming the common source region, forming a dielectric feature on the substrate thereby filling the trenches and forming a plurality of shallow trench isolation features, and forming an erase gate on the dielectric feature. |
| US09679977B2 |
Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided. |
| US09679973B2 |
Light emitting device having vertical structure and package thereof
A light emitting device having a vertical structure and a package thereof, which are capable of damping impact generated in a substrate separation process, and achieving an improvement in mass productivity. The device and package include a sub-mount, a first-type electrode, a second-type electrode, a light emitting device, a zener diode, and a lens on the sub-mount. |
| US09679968B2 |
Field effect transistors and methods of forming same
Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate, the substrate having a first source/drain feature and a second source/drain feature formed thereon. The semiconductor device further includes a first nanowire on the first source/drain feature and a second nanowire on the second source/drain feature, the first nanowire extending vertically from an upper surface of the first source/drain feature and the second nanowire extending vertically from an upper surface of the second source/drain feature. The semiconductor device further includes a third nanowire extending from an upper end of the first nanowire to an upper end of the second nanowire, wherein the first nanowire, the second nanowire and the third nanowire form a channel. |
| US09679962B2 |
FinFET and method of manufacturing the same
There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening. |
| US09679960B2 |
Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors
Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material. |
| US09679958B2 |
Methods for manufacturing integrated multi-layer magnetic films
Methods of manufacture of integrated multi-layer magnetic films for use in passive devices in microelectronic applications. Soft ferromagnetic materials exhibiting high permeability and low coercivity are laminated together with insulating layers interposed. Electrical conductors coupled to interconnects are magnetically coupled to magnetic film layers to engender an inductor (self and mutual). Soft ferromagnetic materials are provided in an alternating array of parallel plate capacitors. Each alternating magnetic film is electrically coupled to either a primary or secondary electrical conductor interconnects and separated by an electrically insulating dielectric material. Alternatively, each alternating magnetic layer comprises an induced anisotropy material, which can also be combined with coiled conductor giving rise to a hybrid inductive/capacitive device. Also, soft ferromagnetic material are also selected and tuned to provide for FMR notch filtering. |
| US09679956B2 |
Organic light-emitting diode display with bottom shields
A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor. Each display pixel may also have control transistors for compensating and programming operations. The array of display pixels may have rows and columns. Row lines may be used to apply row control signals to rows of the display pixels. Column lines (data lines) may be used to apply display data and other signals to respective columns of display pixels. A bottom conductive shielding structure may be formed below each drive transistor. The bottom conductive shielding structure may serve to shield the drive transistor from any electric field generated from the adjacent row and column lines. The bottom conductive shielding structure may be electrically floating or coupled to a power supply line. |
| US09679950B2 |
Organic el display device
An organic EL display device includes a lower electrode that is provided at each pixel, a bank that surrounds an outer circumference of the lower electrode and overlaps an outer circumferential edge of the lower electrode, an organic layer that is formed on the lower electrode and the bank, and an upper electrode that is formed on the organic layer. The bank contains a hygroscopic material. According to this display device, it is possible to confine an influence of moisture which has permeated thereinto to a more restricted area. |
| US09679949B2 |
Organic light emitting display device
An organic light emitting display device is disclosed. The organic light emitting display device includes a first sub-pixel that includes a first emission region which makes a first color, a second sub-pixel that is disposed adjacent to the first sub-pixel, and includes a second emission region which makes a second color, a third sub-pixel that is disposed adjacent to the first sub-pixel, and includes a third emission region which makes a third color, and a fourth sub-pixel that is disposed adjacent to the second sub-pixel and the third sub-pixel, and includes a fourth emission region which makes a fourth color. At least one of the first to fourth sub-pixels includes a transmission region which cannot emit light and through which external light is transmitted. The transmission region is surrounded by at least one of the first to fourth emission regions. |
| US09679946B2 |
3-D planes memory device
The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors). |
| US09679944B2 |
Electronic device and method for fabricating the same
An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad. |
| US09679934B2 |
Semiconductor device
A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad. |
| US09679932B2 |
Solid-state imaging device, method of manufacturing a solid-state imaging device, and electronic apparatus
Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode. |
| US09679930B2 |
Imaging apparatus and electronic apparatus
An imaging apparatus includes: an interposer on which an image sensor including a light reception section is disposed; a translucent member that is provided on the light reception section; and a mold that is formed in sides of the interposer having a rectangular shape and bonded to the translucent member to support the translucent member, the mold including a seal surface that is bonded to the translucent member, the seal surface being provided with a protrusion. |
| US09679920B2 |
Liquid crystal display
A liquid crystal display includes a first substrate, a gate line and a data line disposed on the first substrate, a first insulating layer disposed on the gate line and the data line, a first electrode disposed on the first insulating layer and having a flat form in a planar shape, a second insulating layer disposed on the first electrode, and a second electrode disposed on the second insulating layer and including a plurality of branch electrodes, where a width of a branch electrode of the plurality of branch electrodes is equal to or less than about 2 micrometers. |
| US09679919B2 |
Display device
A display device includes a first substrate having an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing part between the first substrate and the second substrate, the sealing part covering at least a portion of the circuit area, a wiring part in the circuit area of the first substrate and electrically connected to elements in the active area of the first substrate, the wiring part including at least one level-difference compensation part, and a stepped part between the sealing part and at least a portion of the wiring part, the at least one level-difference compensation part of the wiring part being adjacent to the stepped part. |
| US09679917B2 |
Semiconductor structures with deep trench capacitor and methods of manufacture
An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes. |
| US09679914B2 |
Pads and pin-outs in three dimensional integrated circuits
A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array. |
| US09679910B2 |
Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes: a substrate; a first stacked body; a semiconductor film; a charge storage film; and a second stacked body. The first stacked body includes: a plurality of first insulating layers; and a plurality of electrode layers. The second stacked body includes: a plurality of second insulating layers; a first insulating film provided between the plurality of second insulating layers and including a material different from that of the plurality of first insulating layers, the plurality of second insulating layers, and the plurality of electrode layers; and a second insulating film provided between the first insulating film and the substrate via the plurality of second insulating layers, including a same material as the first insulating film, and having lower film density than the first insulating film. |
| US09679909B2 |
Method for manufacturing a finger trench capacitor with a split-gate flash memory cell
A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region. |
| US09679903B2 |
Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse
An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved. |
| US09679902B2 |
Layouts and fabrication methods for static random access memory
A layout of a random access memory is provided. The layer comprises a first sub-layout having a first pattern including a first number (N1) of first patterns and an adjacent second pattern having a second number (N2) of second patterns; a second sub-layout having a first gate pattern and a second gate pattern; and an interchangeable third sub-layout having covering patterns variable for forming different static random access memory when used with the first sub-layout and the second sub-layout. |
| US09679894B1 |
Semiconductor variable resistor and semiconductor manufacturing method thereof
A semiconductor variable resistance device includes: a substrate; a gate formed on the substrate, the substrate further including a first trench the first trench formed outside a side of the gate; first and second doped regions, formed in the substrate, the first and second doped regions formed on two sides of the gate, the first trench formed between the gate and the first doped region; and first and second lightly-doped drain (LDD) regions, formed in the substrate. The first LDD region is formed between the first trench and the first doped region. The second LDD region is formed between the gate and the second doped region. The first and second doped regions form a source and a drain, respectively. The first trench is deeper than the first and the second lightly-doped drain regions. |
| US09679890B2 |
Junction-less insulated gate current limiter device
In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state. |
| US09679885B2 |
Integrated protection devices with monitoring of electrical characteristics
Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip. |
| US09679882B2 |
Method of multi-chip wafer level packaging
A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer. |
| US09679877B2 |
Semiconductor device comprising PN junction diode and Schottky barrier diode
A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode. |
| US09679876B2 |
Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other
A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region. |
| US09679875B2 |
Reduced volume interconnect for three-dimensional chip stack
A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers. |
| US09679871B1 |
Multi-access memory system and a method to manufacture the system
A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data rate. |
| US09679869B2 |
Transmission line for high performance radio frequency applications
This disclosure relates to a transmission line for high performance radio frequency (RF) applications. One such transmission line can include a bonding layer configured to receive an RF signal, a barrier layer, a diffusion barrier layer, and a conductive layer proximate to the diffusion barrier layer. The diffusion barrier layer can have a thickness that allows a received RF signal to penetrate the diffusion barrier layer to the conductive layer. In certain implementations, the diffusion barrier layer can be nickel. In some of these implementations, the transmission line can include a gold bonding layer, a palladium barrier layer, and a nickel diffusion barrier layer. |
| US09679867B2 |
Semiconductor device having a low-adhesive bond substrate pair
A semiconductor device includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate. |
| US09679864B2 |
Printed interconnects for semiconductor packages
A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads. |
| US09679863B2 |
Semiconductor device and method of forming interconnect substrate for FO-WLCSP
A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement. |
| US09679856B2 |
System and method for a microfabricated fracture test structure
According to an embodiment, a micro-fabricated test structure includes a structure mechanically coupled between two rigid anchors and disposed above a substrate. The structure is released from the substrate and includes a test layer mechanically coupled between the two rigid anchors. The test layer includes a first region having a first cross-sectional area and a constricted region having a second cross-sectional area smaller than the first cross-sectional area. The structure also includes a first tensile stressed layer disposed on a surface of the test layer adjacent the first region. |
| US09679855B1 |
Polymer crack stop seal ring structure in wafer level package
Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting. |
| US09679853B2 |
Package-on-package type package including integrated circuit devices and associated passive components on different levels
A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed. |
| US09679849B1 |
3D NAND array with sides having undulating shapes
Area overhead is reduced between adjacent blocks of a 3D vertical channel memory device. In various embodiments, vertically oriented pillars that intersect layers of string select lines and word lines are arranged at intersections of a regular grid that is rotated, in a “twisted” array of pillars. Sides of shapes of the 3D NAND array structure are undulating, and follow undulating lines in which the outer pillars are disposed. For example, any of the string select lines, word lines, ground select lines, and ground lines have sides with undulating shapes. |
| US09679844B2 |
Manufacturing a damascene thin-film resistor
In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module may include: depositing a dielectric barrier layer across at least two structures; depositing a second dielectric layer atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material into the trench and bridging across the resulting at least two exposed copper surfaces. |
| US09679842B2 |
Semiconductor package assembly
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure. |
| US09679839B2 |
Chip on package structure and method
A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die. Alternatively, instead of forming vias over the carrier wafer, through silicon vias may be formed within a semiconductor substrate and the semiconductor substrate may be attached to the carrier wafer. |
| US09679838B2 |
Stub minimization for assemblies without wirebonds to package substrate
A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. |
| US09679836B2 |
Package structures and methods for forming the same
A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface. |
| US09679829B2 |
Semiconductor devices and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. |
| US09679827B2 |
3D VLSI interconnection network with microfluidic cooling, photonics and parallel processing architecture
A three-dimensional VLSI integrated circuit apparatus is disclosed having a plurality of VLSI layers. A first VLSI layer includes a first silicon sublayer coupleable to at least one heat sink, and a first active silicon sublayer having a (first) plurality of photonic receivers (or transceivers); and a second VLSI layer including a second silicon sublayer having a first plurality of microfluidic cooling channels, and a second active silicon sublayer of the plurality of second VLSI sublayers having an interconnection network. Additional VLSI layers may also include a third VLSI layer having a third silicon sublayer having a second plurality of microfluidic cooling channels and a third active silicon sublayer having a (second) plurality of photonic transmitters (or transceivers). Additional VLSI layers may also include a third VLSI layer having microfluidic cooling channels and memory circuits, and a fourth VLSI layer having microfluidic cooling channels and parallel processing circuitry. |
| US09679826B2 |
Method for fabricating semiconductor package with stator set formed by circuits
A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface with the bottom surface, and a stator set formed by circuits; an axial tube axially installed in the via of the substrate; a plurality of electronic components mounted on the top surface of the substrate and electrically connected to the substrate; an encapsulant formed on the top surface of the substrate for encapsulating the electronic components and the axial tube; and an impeller axially coupled to the axial tube via the bottom surface of the substrate. In the semiconductor package, the stator set is formed in the substrate by a patterning process. Therefore, the thickness of the semiconductor package is reduced significantly. |
| US09679820B2 |
Evaluation method of device wafer
An evaluation method of a device wafer on which plural devices are formed on a front surface and inside which a gettering layer is formed is provided. In the evaluation method, electromagnetic waves are radiated toward a back surface of the device wafer and excitation light is radiated to generate excess carriers. Furthermore, the gettering capability of the gettering layer formed in the device wafer is determined based on the damping time of reflected electromagnetic waves. |
| US09679819B1 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump. |
| US09679816B2 |
Method for fabricating semiconductor device
A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface. |
| US09679809B1 |
Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines
A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions. |
| US09679802B2 |
Method of etching a porous dielectric material
A method for producing interconnection lines including etching a layer of porous dielectric material forming a trench and filling the trench is provided. The etching is carried out in a plasma so as to grow, all along the etching, a protective layer on flanks of the layer of porous dielectric material. The plasma is formed from a gas formed from a first component and a second component, or a gas formed from a first component, a second component and a third component. The first component is a hydrocarbon of the CXHY type, where X is the proportion of carbon in the gas and Y the proportion of hydrogen in the gas; the second component is taken from nitrogen or dioxygen or a mixture of nitrogen and dioxygen; the third component is taken from argon or helium; and the protective layer is based on hydrocarbon. |
| US09679801B2 |
Dual molded stack TSV package
Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick. |
| US09679798B2 |
Substrate conveyance apparatus and substrate peeling system
Disclosed is a substrate conveyance apparatus capable of suppressing a substrate from being damaged. The substrate conveyance apparatus includes a plurality of nozzles, and a main body unit. The plurality of nozzles are configured to jet a gas toward a surface of a substrate to hold the substrate in a non-contact manner. The main body unit is provided with the plurality of nozzles. At least surfaces of the plurality of nozzles are formed of a resin. |
| US09679790B2 |
Singulation apparatus and method
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process. |
| US09679785B2 |
Semiconductor device and method of encapsulating semiconductor die
A semiconductor device has a semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die. An insulating layer is formed over an active surface of the semiconductor die. A trench is formed in a non-active area of the semiconductor wafer between the semiconductor die. The trench extends partially through the semiconductor wafer. A carrier with adhesive layer is provided. The semiconductor die are disposed over the adhesive layer and carrier simultaneously as a single unit. A backgrinding operation is performed to remove a portion of the semiconductor wafer and expose the trench. The adhesive layer holds the semiconductor die in place during the backgrinding operation. An encapsulant is deposited over the semiconductor die and into the trench. The carrier and adhesive layer are removed. The encapsulated semiconductor die are cleaned and singulated into individual semiconductor devices. The electrical performance and functionality of the semiconductor devices are tested. |
| US09679784B2 |
Wafer-level packaged optical subassembly and transceiver module having same
A wafer-level packaged optical subassembly includes: a substrate element, the substrate element including a top layer and a base layer being bonded with the top layer; a top window cover being bonded with the top layer of the substrate element; and a plurality of active optoelectronic elements disposed within the substrate element. At least one primary cavity is defined in the substrate element by the top layer and the base layer, and configured for accommodating the active optoelectronic elements. A plurality of peripheral cavities are defined around the at least one primary cavity as alignment features for external opto-mechanical parts. |
| US09679783B2 |
Molding wafer chamber
A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase. |
| US09679780B1 |
Polysilicon residue removal in nanosheet MOSFETs
A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then filled with polysilicon, etching a portion of the polysilicon material via a first etching process, and pre-cleaning the surface native oxide layer. The method further includes etching the remaining polysilicon material via a second etching process, and removing polysilicon etch residue formed adjacent the fin structure by a cleaning process. The pre-cleaning is performed by applying NH3 (ammonia) and NF3 (nitrogen trifluoride) or by applying BHF (buffered hydrofluoric acid). The first etching process is RIE (reactive ion etching) and the second etching process involves applying NF3 and H2 (hydrogen gas). |
| US09679776B2 |
Masking for high temperature implants
A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices. |
| US09679775B2 |
Selective dopant junction for a group III-V semiconductor device
An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature. |
| US09679773B1 |
Method for thermal annealing and a semiconductor device formed by the method
According to various embodiments, a method may include: disposing a dopant in a semiconductor region; forming a radiation absorption layer including or formed from at least one allotrope of carbon over at least a portion of the semiconductor region; and activating the dopant at least partially by irradiating the radiation absorption layer at least partially with electromagnetic radiation to heat the semiconductor region at least partially. |
| US09679771B1 |
Fabrication and design methods using selective etching and dual-material self-aligned multiple patterning processes to reduce the cut-hole patterning yield loss
Design and fabrication methods to reduce the effect of edge-placement errors in the cut-hole patterning process are invented using selective etching and dual-material self-aligned multiple patterning processes. The invented methods consist of a series of processing steps to decompose the original cut-hole mask into multiple separate masks, pattern the cut holes on the resist to expose certain targeted lines, and selectively etch the exposed targeted lines (formed by dual-material self-aligned multiple patterning processes) without attacking the non-target lines. This invention provides production-worthy methods for the semiconductor industry to continue IC scaling down to sub-10 nm half pitch. |
| US09679767B2 |
SiC epitaxial wafer and method for manufacturing the same
Provided is a method of manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a SiC substrate using a SiC-CVD furnace which is installed in a glove box. The method includes a SiC substrate placement step of placing the SiC substrate in the SiC-CVD furnace while circulating gas in the glove box. |
| US09679765B2 |
Method of fabricating rare-earth doped piezoelectric material with various amounts of dopants and a selected C-axis orientation
A method of fabricating a rare-earth element doped piezoelectric material having a first component, a second component and the rare-earth element. The method includes: providing a substrate; initially flowing hydrogen over the substrate; after the initially flowing of the hydrogen over the substrate, flowing the first component to form the rare-earth element doped piezoelectric material over a surface of a target, the target comprising the rare-earth metal in a certain atomic percentage; and sputtering the rare-earth element doped piezoelectric material from the target on the substrate. |
| US09679763B1 |
Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate
A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped semiconductor layer on the first diffusion stop layer, forming a second diffusion stop layer on the doped semiconductor layer, forming a fin layer on the doped semiconductor layer, patterning the first and second diffusion stop layers, the doped semiconductor layer, the fin layer and a portion of the bulk substrate, oxidizing the doped semiconductor layer to form an oxide layer, and forming a dielectric on the bulk substrate adjacent the patterned portion of the bulk substrate, the patterned first diffusion stop layer and the oxide layer. |
| US09679760B2 |
Customizable light bulb changer
A light bulb changing tool comprising a holding structure configured to engage a light bulb, the holding structure configured along an axis, the motorized holding structure configured to actuate in a first direction and a second direction. The light bulb changing tool further includes a force generator configured to selectively force the light bulb against the holding structure and a control unit configured to remotely communicate with the holding structure and the force generator, wherein the electronic control unit sends control signals to drive the holding structure to selectively move in the first direction and the second direction and/or to activate the force generator. The tool further comprises an arm member for positioning the holding structure in a desired configuration to engage the light bulb, wherein the arm member is coupled to the holding structure. The holding structure further comprises a rotator mechanism configured to rotate the holding structure in the first direction about the axis. |
| US09679758B2 |
Multi-reflection mass spectrometer
A multi-reflection mass spectrometer is provided comprising two ion-optical mirrors, each mirror elongated generally along a drift direction (Y), each mirror opposing the other in an X direction, the X direction being orthogonal to Y, characterized in that the mirrors are not a constant distance from each other in the X direction along at least a portion of their lengths in the drift direction. In use, ions are reflected from one opposing mirror to the other a plurality of times while drifting along the drift direction so as to follow a generally zigzag path within the mass spectrometer. The motion of ions along the drift direction is opposed by an electric field resulting from the non-constant distance of the mirrors from each other along at least a portion of their lengths in the drift direction that causes the ions to reverse their direction. |
| US09679756B2 |
Projection-type charged particle optical system and imaging mass spectrometry apparatus
Provided is a projection-type charged particle optical system in which a projection magnification can be changed while a decrease in the accuracy in measuring a mass-to-charge ratio is being suppressed. A projection-type charged particle optical system according to the present invention includes a first electrode disposed so as to face a sample and having an opening formed therein for allowing a charged particle to pass, a second electrode disposed on a side of the first electrode opposite to where the sample is disposed and having an opening formed therein for allowing the charged particle to pass, and a flight-tube electrode disposed such that the charged particle that has been emitted from the sample and has passed through the second electrode enters the flight-tube electrode and being configured to form a substantially equipotential space thereinside. A principal plane is formed at at least two positions in a travel path of the charged particle. |
| US09679752B2 |
Mass spectrometer
A mass spectrometer is disclosed comprising a mass selective ion trap (12) and a quadrupole rod set mass filter (14) arranged downstream of the mass selective ion trap (12). Ions are mass selectively ejected from the ion trap (12) in a substantially synchronized manner with the scanning of the mass filter (14) in order to increase the duty cycle of the mass filter (14). |
| US09679751B2 |
Chamber filler kit for plasma etch chamber useful for fast gas switching
A chamber filler kit for an inductively coupled plasma processing chamber in which semiconductor substrates are processed by inductively coupling RF energy through a window facing a substrate supported on a cantilever chuck. The kit includes at least one chamber filler which reduces the lower chamber volume in the chamber below the chuck. The fillers of the kit can be mounted in a standard chamber having a chamber volume of over 60 liters and by using different sized chamber fillers it is possible to reduce the chamber volume to provide desired gas flow conductance and accommodate changes in vacuum pressure during processing of the substrate. The chamber filler kit can be used to modify a standard chamber to accommodate different processing regimes such as rapid alternating processes wherein wide pressure changes are needed without varying a gap between the substrate and the window. |
| US09679750B2 |
Deposition apparatus
A deposition apparatus according to an exemplary embodiment of the present invention includes: a reactor; a plasma chamber connected to the reactor; a plasma electrode mounted inside of the plasma chamber; and a gas supply plate coupled with the plasma chamber to supply gas into the plasma chamber, wherein a plurality of gas holes is formed at an inner wall of the gas supply plate, and the plurality of gas supply holes is spaced apart from each other by a predetermined interval. |
| US09679744B2 |
Charged particle beam apparatus and method of correcting landing angle of charged particle beam
A scanning electron microscope (SEM) is configured so that SEM images are acquired while scanning a pyramid pattern on a sample plane from four directions. Landing angle of the electron beam is calculated from these SEM images, which are then averaged, whereby inclination angle of the electron beam that is less influenced from scan distortion can be found. |
| US09679742B2 |
Method for optimizing charged particle beams formed by shaped apertures
The present invention provides a method for optimizing a shaped working beam having a sharp edge for making sufficiently precise cuts and a high beam current for faster processing. An ion beam is directed along an optical column through a reference aperture to form a reference beam that has a preferred shape and an associated reference current. The reference beam is optimized using selected parameters of the optical components within the optical column. The ion beam is then directed through a working aperture to form a working beam for use in a processing application. The working beam has a different shape from the reference beam and an associated working current that is higher than the reference current. The reference aperture and working aperture have at least one corresponding dimension. The working beam is then optimized using the selected optical component parameters used to align and focus the reference beam. |
| US09679741B2 |
Environmental cell for charged particle beam system
An environmental cell for a charged particle beam system allows relative motion between the cell mounted on an X-Y stage and the optical axis of the focusing column, thereby eliminating the need for a sub-stage within the cell. A flexible cell configuration, such as a retractable lid, permits a variety of processes, including beam-induced and thermally-induced processes. Photoelectron yield spectroscopy performed in a charged particle beam system and using gas cascade amplification of the photoelectrons allows analysis of material in the cell and monitoring of processing in the cell. Luminescence analysis can be also performed using a retractable mirror. |
| US09679738B2 |
Electron microscope
The present invention relates to a lens-less Foucault method wherein a transmission electron microscope objective lens (5) is turned off, an electron beam crossover (11, 13) is matched with a selected area aperture (65), and the focal distance of a first imaging lens (61) can be changed to enable switching between a sample image observation mode and a sample diffraction pattern observation mode, characterized in that a deflector (81) is disposed in a stage following the first imaging lens (61), and conditions for an irradiating optical system (4) can be fixed after conditions for the imaging optical system have been determined. This allows a lens-less Foucault method to be implemented in a common general-use transmission electron microscope with no magnetic shielding lens equipped, without burdening the operator. |
| US09679736B2 |
Encapsulated structure for X-ray generator with cold cathode and method of vacuuming the same
An encapsulated structure of an X ray generator with a cold cathode and method of vacuuming the same are disclosed. The X ray generator has a glass ball-tube having a base, a tungsten filament, a cold cathode, a focus cap, and an anode target inside, associated with a first electrode pin, a second electrode pin, a single-used pin, and anode pin extended out. The tungsten filament located at the periphery of the base has a first wire end connected with the second electrode pin and a second wire end connected with the single-used pin. While vacuuming the glass ball-tube before melting an end to seal, a voltage is exerting on the single use pin to heat the tungsten, and a high voltage is exerting on the anode target to accelerate the hot electrons emitting from the filament to bombard the inside wall of the glass ball-tube and the anode target so as to shorten the vacuuming time and increase the vacuum level. |
| US09679735B2 |
Travel lockout monitoring system
A vehicle system including a housing, an extendable/retractable member coupled to the housing, an electrically controlled actuator and a lockout system. The electrically controlled actuator is connected to the extendable/retractable member, and is configured to extend and retract the extendable/retractable member relative to the housing. The lockout system includes a detection sensor and a controller. The detection sensor generates a signal upon a detection of a motion of the vehicle system or an anticipated movement of the vehicle system. The controller is in commanding communication with the electrically controlled actuator, and the controller locks the electrically controlled actuator from functioning upon receipt of the signal. |
| US09679733B2 |
Actuation system for an electrical switching device
An actuation system for a switch assembly having at least one switch includes a linear actuator drivable for actuating the switch, and a handle configured for selectively driving the linear actuator. The handle is operable in a first state in which the handle is coupled to the linear actuator such that turning the handle does not drive the linear actuator, and a second state in which the handle is coupled to the linear actuator such that turning the handle drives the linear actuator. |
| US09679729B2 |
Electrical disconnect contactors
A low-profile electrical contactor is provided comprising at least one electrical contact switch, an actuation means and a current determining device. The or each electrical contact switch has first and second electrical terminals, an electrically-conductive busbar in electrical communication with the first electrical terminal, the busbar having two end faces between which a current can flow in a flow direction and at least two flat sides in parallel with the flow direction, at least one fixed electrical contact which is attached to the busbar, an electrically-conductive moveable arm in electrical communication with the second electrical terminal, and at least one moveable electrical contact which is attached to the electrically-conductive moveable arm to form an electrical contact set with the fixed electrical contact. The actuation means can actuate the electrically-conductive moveable arm of the or each electrical contact switch between open and closed conditions. The current determining device has a first field-modifying element formed of a magnetic material located at or adjacent to the first end face of the busbar, a second field-modifying element formed of a magnetic material and located at or adjacent to the second end face of the busbar, at least one sensing coil at or adjacent to the busbar and the first and second field-modifying elements, and having a coil axis between planes of the first and second flat sides. An electromagnetic field induced by the current flowing in the busbar is modified by the first and second field-modifying elements to extend more or substantially more in parallel with the coil axis of the sensing coil. |
| US09679725B2 |
Magnetic switch
The present invention relates to a magnetic switch, and more particularly, a magnetic switch capable of preventing degradation of breaking efficiency by utilizing magnetic force to the utmost, in a manner of matching contact centers of fixed and movable cores. A magnetic switch according to one embodiment includes a bobbin provided with a cylindrical body and a plurality of flanges and having a coil wound on an outer circumferential surface thereof, a fixed core fixed to an inside of the cylindrical body with a predetermined spaced interval from the cylindrical body, and a movable core slidably installed in the cylindrical body and contactable with or separated from the fixed core, wherein a guide portion protrudes from a lower portion of the cylindrical body along an inner circumferential surface of the cylindrical body, such that the movable core can linearly move along a central axis of the fixed core. |
| US09679720B1 |
Arc motivation device
A circuit interrupter including an arc extinguisher which functions to arrest an arc that develops between electrical contacts. The circuit interrupter includes a permanent magnet coupled at opposite ends to two magnetically permeable pole pieces that are configured to drive or urge an arc into toward an arc extinguisher. The device allows for arc motivation due to the magnetic field without requiring the use of electrical power and allows for a rugged, light-weight design. |
| US09679713B2 |
Key switch and analog pressure detection system including the same
A key switch is disclosed. The key switch includes an axis, a pressure sensor layer, an axis component, and a key cap. The axis support includes a first opening. The pressure sensor layer is made of a pressure-sensitive electronic material and disposed on an upper surface of the axis support. The axis component is disposed in the first opening and vertically movable with respect to the axis support and the pressure sensor layer. The keycap is mounted on the axis component and includes a lower surface facing the upper surface of the axis support. When the keycap is depressed, the lower surface of the keycap depresses the pressure sensor layer and an electronic property of the pressure sensor layer varies. An analog pressure detection system including the key switch is also disclosed. |
| US09679712B2 |
Switch assembly and method of using same
A switch assembly and method of using same comprises a switch assembly for operating a power take off unit on a lawn tractor, the switch assembly further includes a housing supporting a selectively locatable activation knob facilitated by an actuation assembly and an internal switch arrangement coupled to a printed circuit board within the housing. The internal switch arrangement comprises a microcontroller and switch for determining the relative position of the selectively locatable activation knob and provides a digital output signal for enabling or disabling a power take off unit based on the digital output signal. |
| US09679709B2 |
Devices and methods for activating circuit breaker accessories
A device is provided for use with a circuit breaker that includes an actuator adapted to move in a first direction in response to an over-current and/or a short circuit condition, and a circuit breaker accessory that includes an actuation mechanism. The device includes a linkage having a first end adapted to be coupled to the actuator and a second end adapted to be disposed adjacent the actuation mechanism. Movement of the actuator in the first direction allows the linkage to move in a second direction different from the first direction from a first position to a second position to activate the circuit breaker accessory. Numerous other aspects are provided. |
| US09679704B2 |
Cathode for a lithium ion capacitor
A cathode in a lithium ion capacitor, including: a carbon composition comprising: an activated carbon; a conductive carbon; and a binder in in amounts as defined herein; and a current collector that supports the carbon composition, wherein the activated carbon has: a surface area of from 500 to 3000 m2/g; a pore volume where from 50 to 80% of the void volume is in pores less than 10 Å; a pore volume higher than 0.3 cm3/gm occupied by the micropores less than 10 Å; and a microporosity of greater than 60% of the total pore volume. Also disclosed is a method of making the cathode and using the cathode in a lithium ion capacitor. |
| US09679702B2 |
Dye comprising a chromophore to which an acyloin group is attached
The present invention related to a dye comprising a chromophore to which an acyloin group as anchoring group is attached, to a method of synthesis of such dye, to an electronic device comprising such dye and to the use of such dye. |
| US09679699B2 |
Dielectric film, film capacitor, and electric device
There are provided a dielectric film, a film capacitor and an electric device capable of achieving an increase in relative permittivity without causing a decrease in breakdown field strength. A dielectric film includes an organic resin and ceramic particles contained in the organic resin. The ceramic particles each have a crystal lattice defined by three axes composed of axis a, axis b, and axis c, and including two or more crystalline phases of different axial ratios c/a. Owing to each crystal phase having different extents of dielectric polarization originating from the differences in shapes (sizes) of the crystal lattices, the ceramic particles each have regions with different permittivities, achieving an increase in relative permittivity without causing a decrease in breakdown field strength. |
| US09679697B2 |
Method for manufacturing multilayer ceramic condenser
Disclosed are a multilayer ceramic condenser and a method for manufacturing the same. There is provided a multilayer ceramic condenser including: a multilayer main body in which a plurality of dielectric layers including a first side, a second side, a third side, and a fourth side are stacked; a first cover layer and a second cover layer forming the plurality of dielectric layers; a first dielectric layer disposed between the first cover layer and the second cover layer and printed with a first inner electrode pattern drawn to the first side; a second dielectric layer alternately stacked with the first dielectric layer and printed with a second inner electrode pattern drawn to the third side; and a first side portion and a second side portion each formed on the second side and the fourth side opposite to each other. |
| US09679693B2 |
Subsea transformer with seawater high resistance ground
A seawater-based high resistance grounding device for a subsea transformer includes an insulated pipe mounted to the outside of the transformer so as to be exposed to seawater. The insulated pipe has two or more cylindrical metallic electrodes electrically connected to ground and to the neutral node of the secondary transformer windings. The volume of seawater within the pipe and between the electrodes provides one or more high resistance ground paths for protection of the transformer. |
| US09679689B2 |
Magnetic clamping device for magnetically clamping to a magnetically attracted material and having a dampening means
There is provided a magnetic clamping device (10) for magnetically clamping to a magnetically attracted material (30). The device comprises at least one permanent clamping magnet (14, 44) for magnetically clamping to the magnetically attracted material wherein the magnet is movable relative to the magnetically attracted material from a position remote from the magnetically attracted material to a clamping position for the clamping of the material by the magnet. The device also includes damping means (22, 24) for damping the movement of the clamping magnet to the clamping position. The damping means biases the clamping magnet away from the magnetically attracted material to assist release of the clamping magnet from the magnetically attracted material. In addition, the device has support means (16, 40, 58) to which the clamping magnet is mounted for the relative movement of the clamping magnet from the remote position to the clamping position and for withdrawing the clamping magnet relative to the magnetically attracted material to release the magnetically attracted material. There is also provided a method for clamping the magnetically attracted material (30) using the clamping device (10). The clamping device may, for example, be a device for securing a load to the magnetically attracted material, a lifting device, a device for holding a work piece in position, or a welding clamp. |
| US09679688B2 |
Magnetic tape and shield cable
A shield cable includes an insulated electrical cable of a conductor wire sheathed about the circumference by an insulator, and a magnetic tape layer formed by wrapping magnetic tape about the circumference of the insulated electrical cable. The magnetic tape is a magnetic tape shaped by continuously cutting to constant width an elongated sheet comprising a magnetic material. The magnetic tape, on at least the insulated electrical cable-facing surface thereof, has grooves extending in the lengthwise direction, for accommodating at least one of pairs of burrs that are formed at both widthwise edge surfaces during cutting of the elongated sheet. |
| US09679683B2 |
Over-current protection device and protective circuit module containing the same
An over-current protection device comprises a PTC device and a first external lead. The PTC device comprises first and second conductive layers and a PTC material layer laminated therebetween. The first conductive layer forms an upper surface of the PTC device. The first external lead has a lower surface soldered to the first conductive layer. The lower surface is provided with a plurality of protrusions of which tops are in direct contact with the first conductive layer to form a gap between the first external lead and the first conductive layer. Solder paste fills the gap to form an electrically conductive connecting layer. The over-current protection device may further comprise a second external lead with protrusions soldered to the second conductive layer to form an axial-lead or a radial-lead type device. |
| US09679682B2 |
Fence post insulator for electrifiable plastic coated wire
An insulator for holding an electrifiable wire includes a base, a first connecting portion provided on a first end of the base, and a second connecting portion provided on a second end of the base. The first connecting portion and the second connecting portion may be movable between a first, open position and a second, closed position. |
| US09679676B2 |
Copper wire rod and magnet wire
A copper wire rod with an excellent surface quality and a magnet wire, in which the occurrence of blister defects is suppressed, are provided. The copper wire rod has a composition consisting of: more than 10 ppm by mass and 30 ppm by mass or less of P; 10 ppm by mass or less of O; 1 ppm by mass or less of H; and the balance Cu and inevitable impurities, wherein hydrogen concentration after performing a heat treatment at 500° for 30 minutes in vacuum is 0.2 ppm by mass or less. The magnet wire includes: a drawn wire material produced by using the copper wire rod; and an insulating film coating an outer periphery of the drawn wire material. |
| US09679672B2 |
Low band gap conjugated polymeric compositions and applications thereof
In one aspect, electrically conductive conjugated polymeric compositions are described herein demonstrating compatibility with aqueous solvents and/or phases. The ability to provide aqueous compatible compositions from previously water insoluble conjugated polymeric systems, in some embodiments, can facilitate use of such systems in a variety of aqueous applications, including biological applications. |
| US09679671B2 |
Low ohmic loss radial superlattice conductors
Various examples are provided for low ohmic loss radial superlattice conductors. In one example, among others, a conductor includes a plurality of radially distributed layers that include a non-permalloy core, a permalloy layer disposed on and encircling the non-permalloy core, and a non-permalloy layer disposed on and encircling the permalloy layer. The non-permalloy core and non-permalloy layer can include the same or different materials such as, e.g., aluminum, copper, silver, and gold. In some implementations, the non-permalloy core includes a void containing air or a non-conductive material such as, e.g., a polymer. The permalloy layer can include materials such as, e.g., NiFe, FeCo, NiFeCo, or NiFeMo. In another example, a via connector includes the plurality of radially distributed layers including the permalloy layer and the non-permalloy layer disposed on and encircling the permalloy layer. The via connector can extend through glass, silicon, organic, or other types of substrates. |
| US09679663B2 |
OTP cell with reversed MTJ connection
A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. |
| US09679662B1 |
Memory device
A memory device includes a semiconductor pillar, a first memory cell that includes a first memory film between a first word line and a side surface of the semiconductor pillar, a second memory cell that includes a second memory film between a second word line and the side surface of the semiconductor pillar, and a control circuit configured to carry out first and second operations on the first memory cell and the second memory cell during a reading operation. During the first operation, a read voltage is applied to the first word line and a read pass voltage is applied to the second word line, and during the second operation following the first operation, a first voltage is applied to the second word line, such that a potential of the second word line is lower than a potential of the semiconductor pillar. |
| US09679660B1 |
Semiconductor memory device and operating method thereof
There are provided a semiconductor memory device having improved reliability and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of strings coupled between a bit line and a source line, the plurality of strings including select transistors respectively coupled to select lines and a plurality of memory cells respectively coupled to a plurality of word lines, and a peripheral circuit for performing a read operation on selected memory cells among the plurality of memory cells. The peripheral circuit discharges the select lines earlier than the plurality of word lines in the read operation. |
| US09679659B2 |
Methods of operating a nonvolatile memory device
An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed. |
| US09679658B2 |
Method and apparatus for reducing read latency for a block erasable non-volatile memory
Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation. |
| US09679657B2 |
Semiconductor memory device including dummy memory cells and method of operating the same
A method of operating a semiconductor memory device including a plurality of cell strings coupled to dummy word lines and normal word lines includes performing a first sub-program operation on selected normal memory cells by sequentially applying first program pulses to a selected normal word line and performing a second sub-program operation on the selected normal memory cells by sequentially applying second program pulses greater than the first program pulses to the selected normal word line, wherein at least one of the dummy word lines is biased in a same manner as the selected normal word line whenever each of the first program pulses is applied to the selected normal word line. |
| US09679656B2 |
Method, electronic device and controller for recovering array of memory cells
A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure. |
| US09679653B2 |
Programming scheme for next starting pulse based on a current program pulse for improving programming speed
A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a cell and executing a program and program verify operation for the cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the program verify level. |
| US09679647B2 |
Semiconductor memory device including a resistance change element and a control circuit for changing resistance of the resistance change element
Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell. |
| US09679646B2 |
Nonvolatile semiconductor storage device and rewriting method thereof
A bitwise bidirectionally rewritable nonvolatile semiconductor storage device capable of performing a high-speed data rewrite, while enhancing endurance characteristics and data-retention characteristics of a memory cell. To achieve high-speed generation of rewrite-bit information indicating that a data rewrite is needed or not, the structure employs a logic circuit corresponding to the number of change patterns of write conditions and concurrently compares between read-out data RO of memory at the start of the data rewrite and prepared write data DIN. After an electrical data rewrite of the memory, the data rewrite is verified based on the rewrite-bit information stored in an internal buffer circuit. This protects an already-rewritten memory cell from unnecessary additional rewrite. |
| US09679645B2 |
Non-volatile, piezoelectronic memory based on piezoresistive strain produced by piezoelectric remanence
A nonvolatile memory storage device includes a ferroelectric (FE) material coupled with a piezoresistive (PR) material through an inherent piezoelectric response of the FE material, wherein an electrical resistance of the PR material is dependent on a compressive stress applied thereto, the compressive stress caused by a remanent strain of the FE material resulting from a polarization of the FE material, such that a polarized state of the FE material results in a first resistance value of the PR material, and a depolarized state of the FE material results in a second resistance value of the PR material. |
| US09679644B2 |
Semiconductor storage device and driving method of the same
A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read. |
| US09679642B2 |
Cross-point memory compensation
The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop. |
| US09679637B1 |
Single-ended memory device with differential sensing
A memory device includes a first memory array comprising a first bit cell and a second bit cell that are configured to provide a first reference signal and a second reference signal, respectively; a second memory array comprising a third bit cell that is configured to store a first logical state; a reference signal provision (RSP) unit, coupled to the first memory array, and configured to short the first and second reference signals so as to provide an averaged reference signal; and a sensing amplifier, coupled between the RSP unit and the second memory array, and configured to use the averaged reference signal to read out the first logical state stored by the third bit cell. |
| US09679635B2 |
Overvoltage protection for a fine grained negative wordline scheme
A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage. |
| US09679629B2 |
Memory device having wiring layout for electrically connecting to switch and capacitor components
Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage. |
| US09679622B2 |
Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system
A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission. |
| US09679618B2 |
Sense structure based on multiple sense amplifiers with local regulation of a biasing voltage
A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascode configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal. |
| US09679617B2 |
Amplifier
According to one embodiment, an amplifier includes a first inverter which inverts and delays a first signal to generate a second signal. A second inverter inverts and delays a third signal to generate a fourth signal. A first transistor includes a gate electrode supplied with the second signal. A second transistor includes a gate electrode supplied with the fourth signal. An output terminal is coupled to one terminal of the second transistor and outputs a fifth signal. A third inverter inverts and delays the fifth signal to generate a sixth signal. A first discharge circuit discharges one terminal of the first transistor and the one terminal of the second transistor based on the first, sixth, or fourth signal, and includes one terminal coupled to the other terminal of each of the first and second transistors. |
| US09679616B2 |
Power management
Methods of operating a die, including counting primary clock cycles of a clock signal in a counter, monitoring a signal indicative of high current demand during secondary clock cycles of the clock signal, determining a total unit consumption of current responsive to a particular value of the signal indicative of high current demand during the secondary clock cycles of the clock signal, and pausing an access operation for the die at a designated point. When a value of the counter matches an assigned counter value of the die while the access operation is paused, determining whether a value of the total unit consumption of current exceeds a unit limit, and resuming the access operation and resetting the value of the total unit consumption of current if the value of the total unit consumption of current is less than or equal to the unit limit. |
| US09679615B2 |
Flexible memory system with a controller and a stack of memory
Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults. |
| US09679614B1 |
Semiconductor device with single ended main I/O line
Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines. |
| US09679608B2 |
Pacing content
Users may have a set duration during which they may consume content, or they may have a variable duration during which they may consume content. A content pacing service is disclosed so that a portion of an item of content may be conveyed in the set duration during which a user is to consume the content. In one embodiment, the rate at which the content is conveyed is increased or decreased so that a reference point in the item of content (e.g., the end of a chapter in an audiobook) is reached approximately when the duration of the user's content consumption ends. |
| US09679607B2 |
Storage and editing of video and sensor data from athletic performances of multiple individuals in a venue
Video and sensor data from multiple locations in a venue, in which multiple individuals are engaged in athletic performances, is stored and edited to create individualized video programs of athletic performances of individuals. Each camera provides a video feed that is continuously stored. Each video feed is stored in a sequence of data files in computer storage, which data files are created in regular time intervals. Each file is accessible using an identifier of the camera and a time interval. Similarly, data from sensors is continuously received and stored in a database. The database stores, for each sensor, an identifier of each individual detected in the proximity of the sensor and the time at which the individual was detected. Each sensor is associated with one or more cameras. |
| US09679606B2 |
Method of modifying play of an original content form
A method of facilitating modified content play such that modification actions may be implemented during play of original content form. The modification actions may be specified by users to modify the original content form. The modification may be disseminated to subscribers or other users desiring similar content modifications. The method may be useful in social networking systems to allow social members to share commentary and otherwise modify original content forms to include their personal reflections. |
| US09679604B2 |
Playback speed adjustable apparatus for playback of moving picture
The present invention provides an apparatus for playback of a moving picture, which compares an action speed of a specific action of an object in a moving picture played back and displayed by a playback unit with an action speed of a separately acquired specific action which is a comparison target, controls a playback speed during the playback of the specific action by the playback unit based on the comparison result, and displays comparison information relating to the comparison result during the playback of the specific action by the playback unit. |
| US09679601B2 |
Post-write scan operations for interlaced magnetic recording
A storage device includes a data degradation management module that tracks a risk of data degradation by incrementing a track write counter of a first data track responsive to each data write command to a second data track, such as a data track directly adjacent to the first data track. If a count of the track write counter exceeds a count threshold, one or more post-write scan operations are performed to assess and/or repair data degradation of the first data track. |
| US09679599B1 |
Adaptive field adjustment of transducer power levels
Method and apparatus adaptively adjusting power levels of a data transducer in a data storage device. In some embodiments, an initial power value is applied to a powered element of a transducer to write user data from a host device to a rotatable data recording medium. An exception condition is declared responsive to a measured parameter. The transducer is used to read data from an evaluation track using a range of different input power values for the powered element. A different, new power value is selected for the powered element responsive to an error rate associated with each of the range of different input power values, with the new power value being lower than the initial power value. Thereafter, the new power value is applied to the powered element during a subsequent writing of user data to the rotatable data recording medium. |
| US09679598B2 |
Writer core incorporating thermal sensor having a temperature coefficient of resistance
A writer core of a transducer is configured to interact with a magnetic recording medium and comprises an upper core and a lower core. At least one of the upper and lower cores comprises a return pole having a return shield. The apparatus also comprises a writer pole between the upper and lower cores, and a writer gap defined between the writer pole and the return shield. The apparatus further comprises a sensor element within one of the upper and lower cores that includes the writer gap. The sensor element has a temperature coefficient of resistance and is configured to sense for a change in temperature indicative of one or both of a change in spacing and contact between the transducer and the magnetic recording medium. |
| US09679597B1 |
Bidirectional shingled magnetic recording in a heat-assisted magnetic recording device
An apparatus and method involves a writer configured for heat-assisted magnetic recording of data to a magnetic storage medium. A controller is coupled to the writer. The controller and writer are configured to write data to a plurality of concentric bands of the medium each comprising a plurality of partially overlapping narrow data tracks and a wide track. The wide tracks of successive bands are positioned adjacent to one another with no intervening narrow data track therebetween. |
| US09679595B1 |
Thermal asperity detection apparatus and method
A method comprises sensing for thermal asperities while sequentially scanning a plurality of tracks of a magnetic recording medium in a first direction relative to an inner or outer diameter of the medium. The method comprises halting the scanning at a first track in response to detecting a thermal asperity at the first track, and skipping a predetermined number of tracks in the first direction to a second track. The method also comprises sensing for the thermal asperity while sequentially scanning the plurality of tracks beginning with the second track in a second direction opposite the first direction. The method further comprises halting the scanning at a third track in response to detecting the thermal asperity at the third track, and logging the first and third tracks as tracks between which the thermal asperity is located. |
| US09679594B1 |
Reflector configured to prevent reflection from a recording medium to an energy source
An apparatus includes a waveguide that has a core between the first and second cladding layers. A near-field transducer in the first cladding layer is configured to receive the energy from the waveguide and deliver the energy to a recording medium. A reflector in the second cladding layer is configured to reduce reflection of the energy from the recording medium back to an energy source. |
| US09679593B2 |
Circuit connection pad design for improved electrical robustness using conductive epoxy
Disk drives including head suspensions within dual stage actuation systems have improved electrical connectivity between electrical connection pads from flexible circuits as are applied to head suspension assemblies with piezoelectric microactuators as also provided to head suspension assemblies. A more robust electrical connection provides for better control of microactuator actuation for fine movements and positioning of magnetic read/write heads relative to disk data tracks as part of dual stage actuated suspension systems. Electrical connections utilize conductive epoxy for physically and electrically connecting electrically conductive trace connection pads with one or more surfaces of piezoelectric microactuators. Electrical connections include better conductivity by utilizing plural surface portions of electrical connection pads. The result is a more robust and predictable performance for high data resolution within disk drives. |
| US09679589B2 |
Magnetoresistive sensor with enhanced uniaxial anisotropy
A read sensor that includes a free layer having a magnetization that changes according to an external magnetic field. The read sensor also includes an additional magnetic layer and a non-magnetic layer. The non-magnetic layer may include a corrugated surface facing the additional magnetic layer. The corrugated surface is configured to enhance uniaxial anisotropy in the read sensor. |
| US09679583B2 |
Managing silence in audio signal identification
An audio identification system determines whether a portion of a sample of an audio signal includes silence and generates a test audio fingerprint for the audio signal based on the presence of silence. In one embodiment, the audio identification system uses a value indicating silence for a portion of the test audio fingerprint corresponding to the portion of the audio signal that includes silence. When comparing the test audio fingerprint to reference audio fingerprints, the portion of the test audio fingerprint including the value indicating the presence of silence is not used. In another embodiment, the audio identification system replaces the portion including silence with additive audio and generates a test audio fingerprint for comparison based on the resulting modified sample. |
| US09679581B2 |
Sign-language video processor
The present invention relates to implementing a system and method for enhancing the recording of a sign-language video by automatically associating the prompter text with the segment(s) of the sign-language video recording. The segment(s) of the sign-language video recording is automatically determined based on the phrases identified within the video recording. Further, the system and method implements a plurality of features to manage the sign-language video and facilitates a means to actively collaborate, upload, and store the sign-language video within the network. |
| US09679580B2 |
Signal processing apparatus and signal processing method, encoder and encoding method, decoder and decoding method, and program
Methods and apparatus for performing signal processing. The signal processing comprises demultiplexing input encoded data into data including information for a segment including frames and coefficient information for a coefficient selected in the frames of the segment, and low band encoded data, decoding the low band encoded data to produce a low band signal, selecting a coefficient of a frame to be processed from a plurality of the coefficients based on the data, calculating a high band sub-band power of a high band sub-band signal of each sub-band constituting a high band signal of the frame to be processed based on a low band sub-band signal of each sub-band constituting the low band signal of the frame to be processed and the selected coefficient, and producing the high band signal of the frame to be processed based on the high band sub-band power and the low band sub-band signal. |
| US09679579B1 |
Systems and methods facilitating selective removal of content from a mixed audio recording
Systems and methods facilitating removal of content from audio files are described. A method includes identifying a sound recording in a first audio file, identifying a reference file having at least a defined level of similarity to the sound recording, and processing the first audio file to remove the sound recording and generate a second audio file. In some embodiments, winner-take-all coding and Hough transforms are employed for determining alignment and rate adjustment of the reference file in the first audio file. After alignment, the reference file is filtered in the frequency domain to increase similarity between the reference file and the sound recording. The frequency domain representation (FR) of the filtered version is subtracted from the FR first audio and the result converted to a time representation of the second audio file. In some embodiments, spectral subtraction is also performed to generate a further improved second audio file. |
| US09679576B2 |
Speech audio encoding device, speech audio decoding device, speech audio encoding method, and speech audio decoding method
A speech/audio coding apparatus and method is provided. The number of encoding bits allocated to encoding of extended-band spectrum is reduced while degradation of sound quality in the extended band is suppressed. A band compression unit creates combinations of sub-band spectra in pairs of two samples each in order from a low-range side in a band compression target sub-band, selects a spectrum having a large absolute-value amplitude among the combinations, and arranges the selected spectrum close to the low-range side on a frequency axis. A number-of-units recalculation unit redistributes bits saved in the sub-band for which band compression was performed to a low range outside the extended band, and redistributes the number of units on the basis of the redistributed bits. |
| US09679572B2 |
Method and apparatus for encoding/decoding scalable digital audio using direct audio channel data and indirect audio channel data
Apparatuses and methods for encoding/decoding scalable digital audio are disclosed. An apparatus for decoding scalable digital audio according to the present invention includes: an audio packet reception unit configured to receive a digital audio packet, including a plurality of pieces of direct audio channel data mapped to respective physical channels and a plurality of pieces of indirect audio channel data indirectly mapped to respective physical channels; an indirect audio channel extraction unit configured to extract the digital audio packet from the pieces of indirect audio channel data; an indirect audio channel decoding unit configured to generate pieces of audio channel data corresponding to a number of physical channels more than the number of pieces of indirect audio channel data using the pieces of indirect audio channel data; and an audio channel output unit configured to match the pieces of audio channel data to the respective physical channels and perform output. |
| US09679571B2 |
Encoder and encoding method for multi-channel signal, and decoder and decoding method for multi-channel signal
An encoder and an encoding method for a multi-channel signal, and a decoder and a decoding method for a multi-channel signal are disclosed. A multi-channel signal may be efficiently processed by consecutive downmixing or upmixing. |
| US09679569B2 |
Dynamic threshold for speaker verification
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a dynamic threshold for speaker verification are disclosed. In one aspect, a method includes the actions of receiving, for each of multiple utterances of a hotword, a data set including at least a speaker verification confidence score, and environmental context data. The actions further include selecting from among the data sets, a subset of the data sets that are associated with a particular environmental context. The actions further include selecting a particular data set from among the subset of data sets based on one or more selection criteria. The actions further include selecting, as a speaker verification threshold for the particular environmental context, the speaker verification confidence score. The actions further include providing the speaker verification threshold for use in performing speaker verification of utterances that are associated with the particular environmental context. |
| US09679561B2 |
System and method for rapid customization of speech recognition models
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for generating domain-specific speech recognition models for a domain of interest by combining and tuning existing speech recognition models when a speech recognizer does not have access to a speech recognition model for that domain of interest and when available domain-specific data is below a minimum desired threshold to create a new domain-specific speech recognition model. A system configured to practice the method identifies a speech recognition domain and combines a set of speech recognition models, each speech recognition model of the set of speech recognition models being from a respective speech recognition domain. The system receives an amount of data specific to the speech recognition domain, wherein the amount of data is less than a minimum threshold to create a new domain-specific model, and tunes the combined speech recognition model for the speech recognition domain based on the data. |
| US09679560B2 |
Server-side ASR adaptation to speaker, device and noise condition via non-ASR audio transmission
A mobile device is adapted for automatic speech recognition (ASR). A user interface for interaction with a user includes an input microphone for obtaining speech inputs from the user for automatic speech recognition, and an output interface for system output to the user based on ASR results that correspond to the speech input. A local controller obtains a sample of non-ASR audio from the input microphone for ASR-adaptation to channel-specific ASR characteristics, and then provides a representation of the non-ASR audio to a remote ASR server for server-side adaptation to the channel-specific ASR characteristics, and then provides a representation of an unknown ASR speech input from the input microphone to the remote ASR server for determining ASR results corresponding to the unknown ASR speech input, and then provides the system output to the output interface. |
| US09679559B2 |
Source signal separation by discriminatively-trained non-negative matrix factorization
A method estimates source signals from a mixture of source signals by first training an analysis model and a reconstruction model using training data. The analysis model is applied to the mixture of source signals to obtain an analysis representation of the mixture of source signals, and the reconstruction model is applied to the analysis representation to obtain an estimate of the source signals, wherein the analysis model utilizes an analysis linear basis representation, and the reconstruction model utilizes a reconstruction linear basis representation. |
| US09679553B2 |
Conversation-sentence generation device, conversation-sentence generation method, and conversation-sentence generation program
A conversation-sentence generation device according to the invention of this application receives, as input information, a conversation sentence given from a user to an agent, first clue information based on which a physical and psychological state of the agent is estimated, and second clue information based on which a physical and psychological state of the user is estimated, stores the physical and psychological state of the agent as an agent state, stores the physical and psychological state of the user as a user state, estimates a new agent state based on the input information and the agent state, estimates a new user state based on the input information and the user state, generates, based on the input information, the agent state, and the user state, an utterance intention directed from the agent to the user, and generates and outputs, based on the input information, the agent state, the user state, and the utterance intention, a conversation sentence given from the agent to the user. |
| US09679551B1 |
Noise reduction headphone with two differently configured speakers
There is disclosed a noise reducing headphone including a headphone housing, a microphone generate an ambient audio signal representative of ambient noise, a processor to generate an anti-sound signal based on the ambient audio signal. A first speaker is disposed within the headphone housing to convert the anti-sound signal into anti-sound. A second speaker is disposed within the headphone housing to convert an audio input signal into high fidelity sound. At least one characteristic of the second speaker is different from a corresponding characteristic of the first speaker. |
| US09679545B1 |
Drum hoop fastening device and drum having the same
A drum hoop fastening device and a drum having the same are provided. The drum hoop fastening device is disposed on a drum. A drum shell has a connecting portion, and a drum hoop has a first through hole along an axial direction. The drum hoop fastening device includes a bearing member which is positioned within the first through hole has a second through hole along the axial direction and a fastening member which is disposed through the second through hole and screwed with the connecting portion; and one of a wall of the second through hole and the fastening member has a first engaging portion extending radially, and the other of a wall of the second through hole and the fastening member radially interferes with the first engaging portion. |
| US09679543B2 |
Recessed concave fingerboard
A musical instrument having a plurality of strings is provided, the strings extending along a longitudinal dimension. The instrument includes a concave fingerboard extending along the longitudinal dimension and spaced from the plurality of strings to define the action, wherein a portion of the concave fingerboard is below an adjacent surface of a body of the musical instrument. |
| US09679537B2 |
Bit expansion method and apparatus
Disclosed is a bit expansion process portion that expands p bits, which a resolution of a brightness value of a digital input picture has, to q bits (where q>p). When a brightness value of an attention pixel of the digital input picture is bit-expanded, the bit expansion process portion applies a weight to the brightness value of the attention pixel according to a magnitude relation of the brightness value of the attention pixel and brightness values of a plurality of surrounding pixels, which are located surrounding the attention pixel, and conducts a gain compensation for the brightness value of the attention pixel after the weight is applied, thereby performing a bit expansion process from the p bits to the q bits. |
| US09679536B2 |
Light emitting apparatus, illumination apparatus and display apparatus
A light emitting apparatus including: one or a plurality of light emitting devices each having a plurality of electrodes and each emitting light from the upper surface of the light emitting device; a plurality of terminal electrodes provided on the lower side of the light emitting devices in a positional relation with the light emitting devices and electrically connected to the electrodes of the light emitting devices; a first metal line brought into contact with the upper surfaces of the light emitting devices and one of the terminal electrodes, provided at a location separated away from side surfaces of the light emitting devices and created in a film creation process; and an insulator in which the light emitting devices and the first metal line are embedded. |
| US09679533B2 |
Illumination apparatus with image projection
An illumination apparatus includes: an illumination light setter which sets illumination light for illuminating an illumination area which includes at least one of a space or an object; an image light setter which sets image light for projecting a projection image which includes at least one of a graphic or a character; and a light projector which emits the illumination light set by the illumination light setter, and projects the image light set by the image light setter. |
| US09679531B2 |
Correcting method, correcting apparatus and method for establishing color performance database for display apparatus
A correcting method for a display apparatus is provided. For N original grayscale combinations, color performances of the display apparatus are respectively measured to generate N measurement results. A set of color blending equations are utilized for M original grayscale combinations according to the N measurement results to generate M blended results. From the N measurement results and the M blended results, P color performances respectively most approximate to P target performances are identified. The P target color performances correspond to P target grayscale combinations. The P color performances correspond to P original grayscale combinations in the (N+M) original grayscale combinations. A look-up table for correcting the display apparatus is established according to the P target grayscale combinations and the P corresponding original grayscale combinations. |
| US09679529B2 |
Driver having capacitor circuit including first to nth capacitors provided between first to nth capacitor driving nodes and a data voltage output terminal
In a display device including a driver that drives a load line of an electro-optical panel through capacitor charge redistribution, a data voltage will change in the case where an electro-optical panel-side capacitance changes, even when tone data is the same. Accordingly, by detecting a voltage at a data voltage output terminal, a connection state and outputs between the data voltage output terminal and the electro-optical panel can be detected. |
| US09679526B2 |
Display system, an integrated circuit for use in the display system, and a method of displaying at least two images on at least two screens
A display system and a method of displaying a separate image on each one of at least two N-bit screens simultaneously, are hereby presented. The display system comprises at least two data processing units arranged for controlling the display of pixels on the corresponding N-bit screen, and a single merger block arranged for receiving pixel data from each respective data processing unit and for transmitting said pixel data to the corresponding N-bit screen. The merger block comprises a multiplexer unit arranged for selectively coupling one of the data processing units to an output of the merger block, a selection unit arranged for driving the multiplexer unit, and a clock generating unit adapted for generating at least one clock signal and for shifting the at least one generated clock signal compared to a main clock signal, the main clock signal and the generated clock signal being used to clock one of the N-bit screens, respectively. |
| US09679525B2 |
Display device and support unit for the same
The present disclosure discloses a support unit for a display device and a display device, which relate to the technical field of a liquid crystal display device. The present disclosure is created to solve the problem of complicated assembling and disassembly of the support unit of the display device in the prior art. The present disclosure provides a support unit for the display device, which includes a pedestal and a bracket, wherein one end of the bracket is connected to a display panel, the other end of the bracket is insert-connected with the pedestal through an insert-connecting structure and is locked by a snap structure. The insert-connecting structure includes a first insert-connecting portion disposed at the pedestal and a second insert-connecting portion disposed at the bracket. The snap structure includes a first snap portion disposed at the pedestal and a second snap portion disposed at the bracket. The cooperating insert-connection between the first insert-connecting portion and the second insert-connecting portion can guide the first snap portion and the second snap portion to be snap-fitted mutually, so that the disengaging of the pedestal from the bracket along an insert-connecting direction can be prevented. |
| US09679521B2 |
Electro-optical device and electronic apparatus
An electro-optical device includes a first pixel circuit provided so as to correspond to a first data line, a second pixel circuit provided so as to correspond to a second data line, a first storage capacitor of which one end is connected to the first data line and the other end is potential-shifted according to a current to be supplied to a light emitting element of the first pixel circuit, a second storage capacitor of which one end is connected to the second data line and the other end is potential-shifted according to a current to be supplied to a light emitting element of the second pixel circuit, and a constant potential line provided between the first storage capacitor and the second storage capacitor in plan view. |
| US09679511B2 |
Subpixel arrangement for displays and driving circuit thereof
An apparatus includes a display panel. In one example, the display panel includes an array of subpixels in a first, a second, and a third colors. Subpixels in the first, second, and third colors are alternatively arranged in every three adjacent rows of the array of subpixels. Every two adjacent rows of the array of subpixels are staggered with each other. A first subpixel in one of the first, second, and third colors and a second subpixel in a same color as the first subpixel are offset by 3 units in the horizontal axis and 4 units in the vertical axis. The first and second subpixels have a minimum distance among subpixels in the same color. |
| US09679508B2 |
Display panel and repair method thereof
A display panel includes scan lines, data lines, organic light emitting diodes, pixel circuits configured to supply drive currents, and electrically coupled to the scan lines and the data lines, repair pixel circuits configured to generate repair drive currents when there is a malfunctioning pixel circuit, repair lines, and repair data lines, wherein a corresponding repair pixel circuit corresponds to the malfunctioning pixel circuit, and is configured to generate the repair drive current based on a repair data voltage from a corresponding repair data line, wherein the repair drive current is configured to be supplied to a corresponding organic light emitting diode that corresponds to the malfunctioning pixel circuit through a corresponding repair line that corresponds to the malfunctioning pixel circuit, and wherein a portion of the repair data lines that extends in the first direction is longer than a portion that does not extend in the first direction. |
| US09679499B2 |
Systems and methods for sensing hand motion by measuring remote displacement
Systems and methods for sensing hand motion by measuring remote displacement are disclosed. For example, one disclosed apparatus includes a first surface configured to engage a first distal member of a surgical tool and a second surface configured to engage a second distal member of the surgical tool, the second surface coupled to the first surface at a pivot point. The apparatus further includes a sensor configured to detect a relative movement of the first surface and the second surface about the pivot point and to generate a signal based at least in part on the relative movement. |
| US09679498B2 |
Method and apparatus for providing a presentation model for an exercise
A method, apparatus and computer program product are provided in order to provide a presentation model. An example method may include receiving a selection of an exercise backdrop, displaying a representation of the exercise backdrop, receiving user input performed against an interface displaying the representation of the exercise backdrop, mapping the user input to an action, and generating an exercise comprising the exercise backdrop and a plurality of actions comprising the action. |
| US09679496B2 |
Reverse language resonance systems and methods for foreign language acquisition
Reverse Language Resonance methods are described for instructing a target language to a learner who speaks a native language. The methods may include providing to the learner a predetermined lesson comprising a lesson text of a plurality of lesson words that are exclusively in the target language. The methods may further include priming implicit memory of the learner. The methods may further include displaying the lesson text on a display and playing a recorded version of spoken words of the lesson text on an audio output while the lesson text is displayed. The methods may further include instructing the learner to perform Concurrent Triple Activity including simultaneously reading the lesson text on the display, listening to the spoken words from the audio output, and repeating the spoken words along with the recorded version into an audio input while the recorded version is playing. |
| US09679495B2 |
Systems and methods for computerized interactive training
Interactive electronic training systems and methods are described herein. Certain embodiments provide preprogrammed video, audio, and/or textual presentations of training materials which provide information related to skills/information to be trained. A scenario including real or animated actors is presented, simulating an interaction. The training system presents related queries for the trainee who audibly responds. The training system stores a score based in part on a comparison of the trainee's response with an answer stored in training system memory. Optionally, the scores are substantially immediately presented by the system to the trainee. |
| US09679494B2 |
Performance monitoring systems and methods
Systems and methods for electronically providing coaching feedback to a user during an athletic activity are disclosed. The method may include receiving electronic data, collecting second electronic data, generating comparison electronic speed data by comparing the second electronic speed data to the first electronic speed data, prompting the user. |
| US09679489B2 |
Ride chaining
A system for determining a dispatch includes an input interface, a processor, and an output interface. The input interface is to receive a request for a first pickup including a first pickup location and a first destination. The processor is configured to determining a driver to dispatch to the first pickup location. The output interface is to provide a first pickup indication to the driver to go to the first pickup location. The input interface is further to receive a first pickup arrival indication indicating the driver arrived at the first pickup location. The output interface is further to provide a first destination indication indicating to the driver to go to the first destination. The input interface is further to receive a request for a second pickup including a second pickup location and a second destination. |
| US09679486B2 |
System and method to detect whether a parked vehicle is in an enclosed space or an open space
An exemplary positioning method for a parked electrified vehicle, includes using an electrified vehicle charging system to compare at least one expected temperature outside a parked vehicle to at least one actual temperature outside the parked vehicle to determine whether the parked vehicle is in an open space or an enclosed space. |
| US09679483B2 |
System and method for providing traffic information
A traffic information providing system includes a traffic information collector configured to collect information on traffic flow. A traffic information generator is configured to detect a speed change point at which an average vehicle speed on a road changes based on the information on the traffic flow and to generate traffic information including position information on the speed change point and a target speed after a vehicle passes the speed change point. A traffic information provider is configured to transmit the traffic information to a vehicle controller for automatically controlling acceleration or deceleration of the vehicle based on the target speed. |
| US09679481B2 |
Systems and methods for variable detection based on traffic counter input
In an Electronic Article Surveillance (“EAS”) system a response is detected to an electromagnetic field. The response is caused by one or more objects present within the surveillance zone and an alarm condition is then selectively generated in accordance with one or more detection algorithms. A speed of a person traveling through the surveillance zone is measured, and if the speed exceeds a threshold then at least one characteristic of the detection algorithm(s) is varied to decrease a rigor of the detection algorithm. |
| US09679480B2 |
Vehicle driver responsibility factor assessment and broadcast
A vehicle includes one or more controllers that, in response to identification of an accident involving the vehicle, transmit a parameter indicative of a degree to which a driver of the vehicle is at fault for the accident. The parameter is based on data collected by another vehicle that was within a predetermined distance from a location of the vehicle at a time of the accident. |
| US09679479B2 |
Induction vehicle detection and identification system, induction license plate, and induction reader
An induction vehicle detection and identification system comprising electronic identification devices with electronic memory, mounted on vehicles, and a reader capable of reading and/or writing data obtained from devices in HF-band. Devices have a non-volatile memory and are integrated into the vehicle's license plate. The reader combined with a magnetic frame is in a dielectric casing, which is mounted under the roadway. It generates an alternating magnetic field, which determines the detection and identification range. Minimum time the reader requires to read discrete responses generated by electronic identification devices and to identify the vehicle is less than 25 ms. The identification devices and the reader exchange data at the rate of 1 Kbit/sec or higher, and provide data encoding and decoding, as well as data access restriction. |
| US09679466B2 |
Personal safety device and a harness for breathing apparatus
A personal safety device, comprising: a housing; attachment means provided on the housing, the attachment means being configured to receive a strap so as to attach the device to a wearer; a motion sensor arranged to monitor the motion of the wearer; and an alarm configured to be activated when the motion sensor has not detected motion for a predetermined period of time; wherein the alarm comprises a first sounder disposed within a first chamber formed by the housing, the first chamber having a first outlet passage; wherein the first outlet passage is arranged such that, in use, it is aligned with a longitudinal axis of the strap. |
| US09679464B2 |
System and a method for monitoring hand sanitizing opportunities in hospital wards
A system for monitoring the hand sanitizing opportunities in hospital wards (1), the system (1) comprising a plurality of sensors (8, 9, 10) arranged inside a ward (2), capable of detecting at least one hand sanitizing action according to a set of hand sanitizing opportunities, the system (1) further comprising at least one indication device (7) of the hand sanitizing action related to the set of hand sanitizing opportunities.The present invention further relates to a method of monitoring the hand sanitizing opportunities in wards. |
| US09679462B1 |
Wireless wake-up alarm with occupant-sensing apparatus
A wake-up alarm with occupant-sensing apparatus attached to a bed which is configured via wireless protocol with a personal computing device of the occupant of the bed. During an alarm period, defined by a turn-on time and turn-off time, the alarm will emit an alarm sound when an occupant is detected in the bed. During the alarm period, the alarm cannot be disabled. |
| US09679458B2 |
Information processing system, information processing apparatus, information processing method, information processing program, portable communication terminal, and control method and control program of portable communication terminal
To readily and effectively take a crime and disaster prevention countermeasure, there is provided an information processing apparatus including an acquirer that, when a crime and disaster prevention assistant device is connected to a portable communication terminal, acquires specifying information for specifying the crime and disaster prevention assistant device from the crime and disaster prevention assistant device via the portable communication terminal, a driver executor that executes a driver program corresponding to the specifying information to control the crime and disaster prevention assistant device, and an application executor that executes a crime and disaster prevention application program corresponding to the specifying information to acquire status detection information detected by the crime and disaster prevention assistant device connected to the portable communication terminal, specifies countermeasure processing corresponding to the acquired status detection information with reference to a management database, and controls the crime and disaster prevention assistant device via the portable communication terminal based on the countermeasure processing. |
| US09679456B2 |
System and method for tracking assets
A computer-based system, computer-implemented method, and computer-readable medium for tracking assets, such as objects and persons. The current invention involves associating a GPS-tracked tag with a targeted asset, registering a serial number associated with the tag, storing the serial number onto a database, and tracking the tag—and thus, associated asset—through the database. Authorized third parties, such as law enforcement personnel, may also access the database and track the asset, if needed, for example if the asset is stolen. The user is able to activate and deactivate the tracking ability of the tag and immediately track the tag when needed. |
| US09679454B2 |
Systems, methods, and devices for managing coexistence of multiple transceiver devices using control signals
A camera device communicates using a first transceiver configured to transmit and receive, over a first communication protocols, signals for configuring the camera device. Furthermore, the camera device communicates with one or more smart home devices using a second transceiver configured to transmit and receive, over a second communication protocols, signals comprising one or more of alerts, control signals and status information to and from the one or more smart home devices. Furthermore, the camera device communicates using a third transceiver configured to transmit and receive, over a third communication protocols, data corresponding to video captured by the camera device. |
| US09679453B2 |
System and methods for correlating sound events to security and/or automation system operations
A method for security and/or automation systems is described. In one embodiment, the method may include detecting a first sound event at a home entry point using one or more sensors. The method may further include receiving input to associate at least one home automation system operation with the first sound event, and may further include storing the first sound event. The method may further include initiating the at least one home automation system operation associated with the first sound event. |
| US09679451B2 |
Fibre optic based intrusion sensing system
A fiber optic based intrusion sensing system includes two or more fiber optic cables buried in a shallow trench in the ground, side by side in a predetermined nonzero distance to each other and at one or more predetermined depths. A dynamic distributed fiber optic interrogator measures a predetermined property related to a change in the length of the cables connected to it. A control unit is connected to all interrogators and analyzes the measurements of the predetermined property and identifies objects on the surface by combining the simultaneous measurements of all cables and correlating the measurements to the type of object on the ground surface, the location of the object on the perimeter, the weight, speed and direction of the object, particularly the direction in or out of the secured perimeter. |
| US09679449B2 |
Evacuation system
An illustrative apparatus includes a protective housing and a recording device. The protective housing can include a water-resistant layer comprising a material that is impervious to water. The water-resistant layer can define an inside space of the protective housing. The protective housing can also include a fire-resistant layer that surrounds the water-resistant layer and an outside layer that surrounds the fire-resistant layer. The recording device within the inside space can include a transceiver configured to receive sensed data from one or more sensory nodes and from a commercial panel of a building, a memory configured to store the data received by the transceiver, and a processor operatively coupled to the transceiver and the memory. The processor can be configured to publish the sensed data such that the sensed data is accessible to a first responder. |
| US09679446B2 |
Gaming system, device and method involving competitive elements
A gaming system, device and method are operable upon a wager. The system, in an embodiment, is operable to generate a visual output related to a plurality of competing elements or competitors. The system is operable to receive wager inputs from a plurality of wager submitters and generate a visual output including at least part of a grid. Also, the system is operable to provide a first monetary value based on which competitor wins as well as a second monetary value based on a winning intersection on the grid. |
| US09679445B2 |
Method, apparatus, and program product for providing alternative win opportunities with wild symbols in a wagering game
A reel-type wagering game includes at least one wild symbol in the game symbol set. The wild symbol or symbols may appear at multiple game symbol locations across an array of game symbol locations through which results are shown for a play in the game, and may assist in forming winning combinations of game symbols along pay lines. Wild symbols that appear in the array of game symbols for a play of the game, but do not contribute to any winning combination along a pay line, represent noncontributing wild symbols which may provide an alternate winning result for the given play of the wagering game. |
| US09679442B2 |
System and method for playing bingo
Systems and methods for playing a game of chance include determining a winner based on the number of player indicia matching selected house indicia and continuing game play until at least one winner is determined. Embodiments include a fixed draw with prizes awarded to all players based on the number of player indicia matching house indicia, as well as a draw that continues until at least one player matches a predetermined number of house indicia. Embodiments include a player indicia selection device with available indicia arranged in rows having associated letters similar to a bingo flashboard. Player cards or tickets include at least some player indicia selectable by players, which may include players requesting an easy pick ticket with one or more randomly generated player indicia recorded at time of purchase. |
| US09679441B2 |
Gaming device providing an award based on a count of outcomes which meets a condition
Methods and apparatus for providing an award based on a multiplicity of game outcomes. In one implementation the invention provides a method for providing a game. The method includes placing a bet by a player, playing of a game to produce a game outcome, evaluating a primary game outcome, paying a direct award if the primary outcome merits it, advancing a bonus accumulator if the primary outcome merits it, and if the bonus accumulator has advanced sufficiently, paying a bonus award to the player and clearing the bonus accumulator. |
| US09679436B2 |
Functional identifiers on wireless devices for gaming/wagering/lottery applications and methods of using same
A user interface and a method of using the user interface are provided for conducting a business-related action and/or transaction for at least one remote product or service, by providing user interaction with a functional component on a wireless gaming device. Functional components are identified via functional identifiers, such as a company's mark, including logos, trademarks, brands, names, and etc. The functional identifiers are strategically placed in or on the functional components of the wireless gaming device. The business-related action and/or transaction are for gaming, wagering, betting, gambling, and/or lottery play. |
| US09679435B2 |
Gaming machine mounting apparatus and system for supporting an overhead display
A system and apparatus for mounting an overhead display device to gaming machines. The system and apparatus featuring mounting elements securable to a display device at a selected distance and mounting hardpoints on one or a plurality of gaming machines. The hardpoints having a recess with a size and shape corresponding to that of the mounting elements. Wherein the display is securable to gaming machines in an overhead configuration when the mounting elements are secured to hardpoints and where the distance between the mounting elements corresponds to the distance between the hardpoints to which they are respectively secured. |
| US09679434B2 |
Gaming system including wild symbols
A gaming system configured to operate a game associated with a plurality of symbols. For a play of the game, the gaming system displays a plurality of reels, each of the reels including a plurality of the symbols and being associated with a plurality of symbol display areas. For an activation of the reels, the gaming system randomly generates and causes each of the reels to display one of the symbols on that reel at each of the symbol display areas associated with that reel. Upon an occurrence of a triggering event, the gaming system: adds one or more wild symbols to one or more of the reels and provides a plurality of additional activations of the reels. If a removal condition is satisfied prior to a final one of the additional activations of the reels, the gaming system removes a remaining wild symbol from one of the reels. |
| US09679430B2 |
Vehicle remote function system and method for determining vehicle FOB locations using adaptive filtering
A vehicle remote function system is provided for determining locations of a fob relative to a vehicle. The system may include a controller configured for communication with antennas mounted at different locations in the vehicle, the controller for use in determining locations of the fob based on ultra-wide band wireless signals transmitted between the antennas and the fob. The controller is configured to use a first filtering of the wireless signals to determine an initial location of the fob, and a second filtering of the wireless signals to determine a subsequent location of the fob. A method is also provided which may include transmitting ultra-wide band wireless signals between the fob and antennas mounted in the vehicle, using a first filtering of the wireless signals to determine an initial location of the fob, and using a second filtering of the wireless signals to determine a subsequent location of the fob. |
| US09679425B2 |
Control and monitoring system and method for access to a restricted area
We describe a control and monitoring system and method for access to a restricted area, such as mass transport systems (subways, trains, airports, ships and others), commercial buildings, schools, factories, datacenters, and other places with people moving, composed of a Processing Unit (10) that receives information both from a User Authentication Device (20) and an Image Capture Device (40). The Processing Unit (10) processes this information determining user category as well as user location, speed and direction of movement within a Gated Area (GA). In turn, the Processing Unit (10) triggers one or more Bars of Luminous Elements (31) arranged in Barriers (30) limiting a Gated Area (GA), giving every user (Authorized User [AU], Unauthorized User [UU] or Special User [SU]) a User Category Window (311, 312 or 313) that follows the movement of the user within the Gated Area (GA). A Blocking Device (50) can be activated by the Processing Unit (10) to be partially or fully closed or opened and at a speed proportional to the location, velocity and direction of movement of the user within the Gated Area (GA). |
| US09679423B2 |
Systems and methods of creating and delivering item of manufacture specific information to remote devices
An asset authoring and delivery system generates a number of authored assets. Each of the authored assets includes a number of asset content objects that are logically associated with one or more components included in the item of manufacture. The authored assets generated by the asset authoring and delivery system are formatted and communicated to one or more remote devices logically associated with the item of manufacture. Authored assets may be provided responsive to one or more sensed characteristics, for instance vehicle operational parameters, vehicle operation and/or driver behavior, and may be customized to a make and/or model of vehicle. |
| US09679421B2 |
Vehicle lift configured for integration with vehicle diagnostic computing devices
A vehicle lift comprising a main housing and a carriage assembly configured to engage a wheel of a vehicle, with the carriage assembly being vertically shiftable relative to the main housing. The vehicle lift additionally includes a lift control module for controlling actuation of said carriage assembly. The vehicle lift further includes a docking area configured to receive a diagnostic device, with the docking area including a power port configured to provide power to the diagnostic device. |
| US09679418B1 |
Sensor and feedback assembly for a bicycle
A feedback system and indicator for aerodynamic positioning while bicycling comprising one or more sensors located on the bicycle in positions that indicate when rider is in an aerodynamic position that activates and or otherwise records data associated with aerodynamic positioning while riding. |
| US09679417B1 |
System and method for presenting virtual reality content to a user
This disclosure describes a system configured to present primary and secondary, tertiary, etc., virtual reality content to a user. Primary virtual reality content may be displayed to a user, and, responsive to the user turning his view away from the primary virtual reality content, a sensory cue is provided to the user that indicates to the user that his view is no longer directed toward the primary virtual reality content, and secondary, tertiary, etc., virtual reality content may be displayed to the user. Primary virtual reality content may resume when the user returns his view to the primary virtual reality content. Primary virtual reality content may be adjusted based on a user's interaction with the secondary, tertiary, etc., virtual reality content. Secondary, tertiary, etc., virtual reality content may be adjusted based on a user's progression through the primary virtual reality content, or interaction with the primary virtual reality content. |
| US09679416B2 |
Content creation tool
A server for content creation is described. A content creation tool of the server receives, from a first device, a content identifier of a physical object, a virtual object content, and a selection of a template corresponding to an interactive feature for the virtual object content. The content creation tool generates a content dataset based on the content identifier of the physical object, the virtual object content, and the selected template. The content creation tool provides the content dataset to a second device, the second device configured to display the interactive feature corresponding to the selected template |
| US09679413B2 |
Systems and methods to transition between viewpoints in a three-dimensional environment
Systems and methods to transition between viewpoints in a three-dimensional environment are provided. One example method includes obtaining data indicative of an origin position and a destination position of a virtual camera. The method includes determining a distance between the origin position and the destination position of the virtual camera. The method includes determining a peak visible distance based at least in part on the distance between the origin position and the destination position of the virtual camera. The method includes identifying a peak position at which the viewpoint of the virtual camera corresponds to the peak visible distance. The method includes determining a parabolic camera trajectory that traverses the origin position, the peak position, and the destination position. The method includes transitioning the virtual camera from the origin position to the destination position along the parabolic camera trajectory. An example system includes a user computing device and a geographic information system. |
| US09679412B2 |
3D face model reconstruction apparatus and method
Apparatuses, methods and storage medium associated with 3D face model reconstruction are disclosed herein. In embodiments, an apparatus may include a facial landmark detector, a model fitter and a model tracker. The facial landmark detector may be configured to detect a plurality of landmarks of a face and their locations within each of a plurality of image frames. The model fitter may be configured to generate a 3D model of the face from a 3D model of a neutral face, in view of detected landmarks of the face and their locations within a first one of the plurality of image frames. The model tracker may be configured to maintain the 3D model to track the face in subsequent image frames, successively updating the 3D model in view of detected landmarks of the face and their locations within each of successive ones of the plurality of image frames. In embodiments, the facial landmark detector may include a face detector, an initial facial landmark detector, and one or more facial landmark detection linear regressors. Other embodiments may be described and/or claimed. |
| US09679411B2 |
Hardware management and reconstruction using visual graphics
In an approach for updating instructions of machine repairs to a user interface, a processor populates a quantity of machine components used to construct a machine model. A processor receives the machine model constructed from the quantity of machine components. A processor couples the machine model with a set of vital product data. A processor associates a set of instructions for a repair procedure with the machine model and the vital product data file. A processor generates a visual representation of the repair procedure specific to the machine model. |
| US09679407B2 |
Electronic device, storage medium, program, and displaying method
An electronic device is provided which displays an object (body) on a flexible display screen in accordance with a three-dimensional shape of the display screen by utilizing the flexibility of the display screen. An electronic device including a display portion which includes a flexible display device displaying an object on a display screen; a detection portion detecting positional data of a given part of the display screen; and an arithmetic portion calculating a three-dimensional shape of the display screen on the basis of the positional data and computing motion of the object to make the object move according to a given law in accordance with the calculated three-dimensional shape of the display screen. |
| US09679405B2 |
Simulator, simulation method, and simulation program
A command value for moving a virtual machine is calculated according to a control program and based on model data of a virtual object (step S313, step S314) where the virtual machine corresponds to a machine and the virtual object is manipulated by the virtual machine in a virtual space and corresponds to an object; motion of the virtual machine which is moved in accordance with the calculated command value is calculated (step S315); motion of the virtual object which is moved in accordance with the calculated motion of the virtual machine (step S315); a virtual space image is generated (step S115) where the virtual space image is assumed to be acquired in the case where the calculated motion of the virtual machine or the calculated motion of the virtual object is virtually photographed; and the command value is calculated further based on the generated virtual space image (step S313, step S314). An integrated simulation of a machine system covering a visual sensor in a real space corresponding to a virtual photographing part can be realized. A test in the case where the visual sensor is used in machine control can be carried out. |
| US09679403B2 |
Method and system for utilizing transformation matrices to process rasterized image data
A method and system render rasterized data by receiving non-rasterized page description language data and a corresponding transformation matrix representing transformation operations to be performed. The non-rasterized page description language data is rasterizing to create rasterized data. The corresponding transformation matrix is decomposed into a plurality of individual transformation operation matrices and a discrete transformation operation value, from each corresponding individual transformation operation matrix, is generated for each transformation operation to be performed upon the rasterized data. The transformation operations are performed upon the rasterized data based upon the generated discrete transformation operation values. |
| US09679402B1 |
System and method for rapidly assessing system components with gauges
A method includes determining utilization metrics and range data for each of a plurality of system components and formatting for display a list comprising the plurality of system components and respective component attributes of the system components. The component attributes include the respective utilization metrics over a selected time range. The method further includes determining, using a processor, a selected system component based on a cursor position with respect to the list of system components and, in response to determining the selected system component, formatting for display a gauge indicative of the selected system component. The gauge includes an average utilization of the selected system component over the selected time range. The gauge also includes the range data that includes a minimum utilization of the selected system component over the selected time range and a maximum utilization of the selected system component over the selected time range. |
| US09679390B2 |
Systems and methods for removing a background of an image
An image such as a depth image of a scene may be received, observed, or captured by a device. A grid of voxels may then be generated based on the depth image such that the depth image may be downsampled. A background included in the grid of voxels may then be discarded to isolate one or more voxels associated with a foreground object such as a human target and the isolated voxels associated with the foreground object may be processed. |
| US09679389B2 |
Method and system for blood vessel segmentation and classification
A method of analyzing structure of a network of vessels in a medical image, comprising:receiving the medical image depicting the network of vessels;obtaining a mask of the network of vessels in the image; andgenerating a non-forest graph mapping a plurality of paths of vessels in the network to directed paths in the graph, with each edge in the graph either directed to indicate a known direction of flow in the corresponding vessel, or undirected to indicate a lack of knowledge of direction of flow in the corresponding vessel, and with all directed edges in a path directed in a same direction as the path. |
| US09679385B2 |
Three-dimensional measurement apparatus and robot system
There are provided a three-dimensional measurement apparatus capable of speeding up image processing, and a robot system including the same. |
| US09679382B2 |
Georeferencing method and system
A method of georeferencing a first image of a scene acquired from a first imaging device based on at least one second image of the scene acquired from a second imaging device. The method includes obtaining data indicative of an eligibility parameter for one or more areas of the scene; selecting one or more pivot areas among the one or more areas of the scene, wherein the eligibility parameter of the pivot areas satisfy a predefined criterion; for at least some of the selected pivot areas, identifying tie points for the first and second images; and solving the external orientation of the first image using the identified tie points and a first imaging device model. |
| US09679377B2 |
Medical image processing apparatus and a medical image processing method
According to embodiment, a medical image processing apparatus includes input interface circuitry and processing circuitry. The input interface circuitry inputs at least three landmarks in a first and second slice image group. The processing circuitry determines, in each of the first and second slice image group, a first axis connecting two points in the landmarks and a second axis that passes through another point different from the two points and is orthogonal to the first axis. The processing circuitry performs a registration between first slice images belonging to the first slice image group and second slice images belonging to the second slice image group by using the first and second axes in the first slice image group and the first and second axes in the second slice image group. |
| US09679376B2 |
Medical image processing apparatus, method, and recording medium
A determination unit makes a determination as to whether or not at least either one of at least a portion of an upper end vertebra and at least a portion of a lower end vertebra is included in a first medical image of a subject. If the determination is negative, an image obtaining unit obtains a second medical image that allows recognition of a label of the vertebra of the subject. A labeling unit aligns the first medical image with the second medical image and labels the vertebra included in the first medical image. |
| US09679374B2 |
Systems and methods for predicting location, onset, and/or change of coronary lesions
Systems and methods are disclosed for predicting the location, onset, or change of coronary lesions from factors like vessel geometry, physiology, and hemodynamics. One method includes: acquiring, for each of a plurality of individuals, a geometric model, blood flow characteristics, and plaque information for part of the individual's vascular system; training a machine learning algorithm based on the geometric models and blood flow characteristics for each of the plurality of individuals, and features predictive of the presence of plaque within the geometric models and blood flow characteristics of the plurality of individuals; acquiring, for a patient, a geometric model and blood flow characteristics for part of the patient's vascular system; and executing the machine learning algorithm on the patient's geometric model and blood flow characteristics to determine, based on the predictive features, plaque information of the patient for at least one point in the patient's geometric model. |
| US09679373B2 |
Retrospective MRI image distortion correction
The invention relates to a method for correcting MRI image distortion, in which a distortion correction procedure is carried out on an acquired MRI image data set (1) of a body region by graphical data processing, characterized in that: —after the MRI image data set (1) has been acquired, its distortion is determined by carrying out an image registration process for registering the acquired MRI image data set (1) to a previously available, less distorted or undistorted image data set (2) of substantially the same body region; —a transformation is determined from the image registration process; and —by applying the transformation to the MRI image data set (1), its distortion is corrected. |
| US09679370B2 |
Image processing device and image processing method
The present invention provides an image processing device whereby the probability of outputting a restored image which accurately corresponds to an original image which is included in a low-quality input image is improved. This image processing device comprises: an image group generating means for generating, from the input image, using a dictionary which stores a plurality of patch pairs wherein a degradation patch which is a patch of a degraded image wherein a prescribed image is degraded is associated with a restoration patch which is a patch of this prescribed image, a plurality of restored image candidates including a plurality of different instances of content which have a possibility of being the original content of the input image; and an image selection presentation means for clustering the generated plurality of restored image candidates, and selecting and outputting an image candidate on the basis of the result of this clustering. |
| US09679369B2 |
Depth key compositing for video and holographic projection
According to embodiments herein, depth key compositing is the process of detecting specific desired portions/objects of a digital image using mathematical functions based on depth, in order to separate those specific portions/objects for further processing. In one particular embodiment, a digital visual image is captured from a video capture device, and one or more objects are determined within the digital visual image that are within a particular depth range of the video capture device. From there, the one or more objects may be isolated from portions of the digital visual image not within the particular depth range, and the isolated objects are processed for visual display apart from the portions of the digital visual image not within the particular depth range. Also, in certain embodiments, the detected portion of the digital image (isolated objects) may be layered with another image, such as for film production, or used for holographic projection. |
| US09679368B2 |
Radiographic image processing device, radiographic image processing method, and recording medium
A radiographic image processing device includes: an image acquisition section that acquires a subject image detected by a shielded detection portion and a non-shielded detection portion; an area information acquisition section that acquires area information which is information for specifying a non-shielded image area and a shielded image area; and a scattered ray suppression section that estimates spreading of scattered rays generated in a non-shielded subject portion, estimates that scattered rays that spread to the non-shielded image area from a shielded subject portion are not present, calculates a scattered ray component in each position in the non-shielded image area as the estimated scattered rays reach each position in the non-shielded image area, and suppresses the scattered ray component in each position in the non-shielded image area according to the calculated scattered ray component. |
| US09679366B2 |
Guided color grading for extended dynamic range
Novel methods and systems for color grading are disclosed. The color grading process for a visual dynamic range image can be guided by information relating to the color grading of other images such as the standard dynamic range image. |
| US09679362B2 |
System and method for generating textured map object images
A method of producing a textured or pseudo-3D image of one or more map objects is provided comprising acquiring at least one image representing at least part of the one or more map objects. Laser scan data is acquired for the at least one map object, the laser scan data representing distances from a laser scanner to one or more points on at least one surface of the at least one map object. Texture or lighting data associated with the at least one map object is generated from the laser scan data, and the texture or lighting data and the image is processed in order to generate at least one textured or pseudo 3D image at least partially representing the one or more map objects. |
| US09679359B2 |
Vehicle surround view system
A surround view system that can provide a surround view, e.g., a 360° view, from a vehicle by way of cameras positioned at various locations on the vehicle. The cameras can generate image data corresponding to the surround view, and a processing device can process the image data and generate the surround view on a simulated predetermined shape that can be viewed from a display. The simulated predetermined shape can have a flat bottom with a rectangular shape and a rim with a parabolic shape. |
| US09679358B2 |
Pixel interpolation processing apparatus, imaging apparatus, interpolation processing method, and integrated circuit
A pixel interpolation processing apparatus and an image capturing apparatus are provided that are capable of performing a pixel interpolation process properly even when the pattern of color filter array is unknown. An imaging apparatus includes an imaging unit having a single-chip image sensor having four-color filter array for obtaining an image signal, and the imaging apparatus uses pixel data for a surrounding area around a target pixel to calculate a plurality of sets of correlation values in two directions orthogonal to each other, and determines the correlation direction based on these correlation values. The imaging apparatus obtains first to fourth color component pixel values for the target pixel relying on the fact that the high-frequency components of pixel signals in a direction orthogonal to a direction with high correlation have high correlation regardless of the color of color filters, thus allowing for performing pixel interpolation processing properly even if the four colors of color filters are unknown. |
| US09679357B2 |
Image processing device, and an image processing method
An image processing device includes an edge direction determination unit, a filter coefficient calculation unit, and a filter processing unit. The edge direction determination unit determines a first edge direction of an edge including a first pixel of input image data, and calculates a first reliability value of the determined edge direction corresponding to the first pixel. The filter coefficient calculation unit calculates a first filter coefficient corresponding to the first pixel, a second filter coefficient corresponding to a second pixel, and a third filter coefficient corresponding to a third pixel at least based on the first reliability value of the first edge direction. The filter processing unit performs filter processing on the input image data on the basis of the calculated first through third filter coefficients, and outputs output image data. |
| US09679354B2 |
Duplicate check image resolution
A system and method for comparing digital images, such as checks images used by banks, includes receiving and processing the images to be compared, including scaling the images to a common resolution, as well as filtering them to remove spot noise, background pels, and other non-information carrying elements. One or more regions of each image are selected for comparison. The selected regions are compared to one another by subtracting the pels of one image from the other's pels. A determination is made of whether the two or more images are duplicates of one another, or depict a substantially identical subject, based on the results of the subtractions. Furthermore, the amount of filtering and scaling may be adjusted to enhance the effects of the system to take advantage of common characteristics that may be known or detected in a particular set of images to be compared. |
| US09679350B2 |
Techniques for optimizing stencil buffers
One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment. |
| US09679349B2 |
Method for visualizing three-dimensional data
A method for providing a set of data files from a server computer to a mobile client device is disclosed according to at least one embodiment described herein. The method may include providing geometry data in a memory of the mobile client device, the geometry data being associated with a three-dimensional surface in an image scene; selecting data files with texture data for being provided by the server computer, wherein selecting data files is performed by a calculation unit of the mobile client device based on the geometry data and on visibility conditions of the three-dimensional surface in the image scene; and requesting the provision of the selected data files from the server computer to the client device. In some embodiments, the set of data files may include texture data being associated with a portion of the three-dimensional surface in the image scene. |
| US09679347B2 |
Shader pipeline with shared data channels
A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units. |
| US09679346B2 |
Graphics engine and environment for efficient real time rendering of graphics that are not pre-known
This disclosure pertains to the operation of graphics systems and to a variety of architectures for design and/or operation of a graphics system spanning from the output of an application program and extending to the presentation of visual content in the form of pixels or otherwise. In general, many embodiments of the invention contemplate a high level graphics framework to receive graphic requests from an application. The graphics request is analyzed by the high-level framework and sorted into groups of command statements for execution. The command statements are sorted to cause the most efficient processing by the underlying hardware and the groups are submitted separately to a GPU using a low-level standard library that facilitates close control of the hardware functionality. |
| US09679341B2 |
Methods, systems, and computer readable media for evaluating a hospital patient's risk of mortality
A method for evaluating a hospital patient's risk of mortality includes collecting data from physiologic signals generated by patient monitors, physiologic signals of organ function, and demographic information for a patient. A measure of the variability of at least one of the physiologic signals is determined. Data and the measure of variability are analyzed to determine whether a value for a particular physiologic or demographic variable falls within a critical interval for the variable that indicates that the value is predictive of mortality or survival. Each time a value for a physiological or demographic variable for the patient falls within a critical interval, the occurrence of an event for the patient is recorded. The number of events for the patient is counted over a time period. Output perceptible by human user that indicates the patient's risk of mortality or likelihood of survival is generated based on the count. |
| US09679340B2 |
Multi-location learning-activity state management for distance education
A method for delivering distance education for real clients, each either a teacher client or a student client, at multiple teaching sites and a system using the method are provided. A multi-layer arrangement is used to arrange computing servers to be one first-level server and one or more second-level servers each communicable with the first-level server. Each server serves real clients located in a pre-determined site. Furthermore, each server sets up a virtual client to execute the teacher client's activity command so as to locally generate application-specific data, which are then stored in this server. When a communication link to a student client is re-established after an activity interruption, resynchronization of the student client's learning-activity state with the teacher client's is regained based on the locally-generated application-specific data stored in the server that serves the student client without a need to burden other servers. |
| US09679339B2 |
Scheduling usage or provision of resources
Methods and systems for obtaining a value indicative of resource-related activity in respect of a plurality of devices using a network of metering means arranged to be in communication with one another, the metering means being associated with resource-consuming or resource-providing devices and being arranged to obtain local resource-related activity data therefrom, the method comprising: a first metering means initiating a circulation procedure by sending a token to a downstream metering means, the token comprising an activity field for carrying a value indicative of resource-related activity data; the circulation procedure continuing, until the token has returned to the first metering means, by each downstream metering means in turn receiving the token, updating the activity field in dependence on its own locally-obtained resource-related activity data, and forwarding the token to a further downstream metering means; and once the token has returned to the first metering means, obtaining a value indicative of the combined level of resource-related activity in respect of devices associated with the metering means in said network in dependence on the value carried by the activity field. |
| US09679334B2 |
System and method for facilitating trading of multiple tradeable objects in an electronic trading environment
A system and method are provided for trading multiple tradeable objects. One example method includes displaying at least one combined quantity indicator representing a combined quantity associated with at least two tradeable objects, detecting an input associated with an order for a predetermined order quantity in relation to one of the combined quantity indicators, and allocating the order quantity between the at least two tradeable objects using at least one quantity allocation rule. In one example embodiment, a plurality of quantity allocation rules can be user-configurable, and different rules can be defined and applied in relation to different order types. |
| US09679322B2 |
Secure messaging with user option to communicate with delivery or pickup representative
Systems and methods are disclosed for automated computer based notification systems. The systems and methods enable secure notification communication sessions. A representative method, among others that are disclosed herein, can be broadly summarized by the following steps: enabling a first party associated with a personal communication device (PCD) to input or select authentication information for use in connection with a subsequent notification communication session involving advance notice of a delivery or pickup of a good or service at a stop location by a mobile thing (MT); storing the authentication information; monitoring location or travel information in connection with the MT; causing initiation of the notification communication session to the PCD, in advance of arrival of the MT at the stop location, based at least in part upon the location or travel information associated with the MT; during the notification communication session, providing the authentication information to the PCD that indicates to the first party that the notification communication session was initiated by an authorized source; and during the notification communication session, enabling the first party to select whether or not to communicate with a second party having access to particulars of the pickup or delivery. An embodiment of a related system, among others, has a computer-based architecture with computer software, or code, that is stored in one or more memories and executed by one or more processors for performing the foregoing steps. Yet another embodiment of a related system can be implemented in software and/or hardware and has a means for performing each of the aforementioned steps. |
| US09679320B2 |
User-personalized media sampling, recommendation and purchasing system using real-time inventory database
A user-personalized product sampling, recommendation and purchasing system uses customer identification numbers and associated customer profile data to tailor specific product recommendations to a customer at a content sampling station of a retail location. The customer also can use her customer profile to receive the same information from an Internet website of the merchant. In-store sampling stations also may have the capability of checking store inventory and central warehouse inventory and providing recommendations to the customer in accordance with product availability, and optionally may provide the customer with the ability to place product orders directly through the sampling station. The recommendation system also can be used to tailor product recommendations in accordance with a rule-based model and real-time inventory data from a POS database. |
| US09679311B2 |
System and method for adding advertisements to a location-based advertising system
A location-based advertising system automatically analyzes messages posted on social networking systems or other publicly accessible or private computer systems for posting messages for viewing by others. The messages are analyzed to identify messages that contain offers, such as offers that may be construed as location-based offers. Information about the offers is extracted from the messages and placed in a database. The database may be used by a location-based advertising application to send advertisements to targeted users or to respond to user who are qualified according to their current or recent geographic location. Optionally or alternatively, merchants may send messages, such as e-mail messages or instant messages (IMs), to the system to notify the system of offers. These messages are also analyzed and information about their respective offers is extracted and placed in the database. |
| US09679304B1 |
Accentuating terms or features of interest in an advertisement
Accentuating terms of interest in an advertisement to be served in an interactive environment. Such terms of interest can be determined from information in a request for the advertisement. Such ad request information may include query information, geolocation information, etc. In the context of text-based ads, accentuation may include bolding the term(s), underlining the term(s), increasing the font size of the term(s), coloring the font of the term(s), shading the font of the term(s), flashing the text of the term(s), etc. Such accentuation helps users to quickly identify how an advertisement is related to what they are looking for. For example, in the context of a search engine which returns search results, as well as multiple text-based ads, users viewing a search result page in response to their query can quickly scan such a search result page for relevant information. This helps to improve the performance of ads, particularly if advertisers wordsmith their advertisements with care. |
| US09679301B2 |
Method, apparatus and computer program product for developing, aggregating, and utilizing user pattern profiles
A method, apparatus and computer program product are provided for generating and utilizing a user pattern profile. In this regard, the user pattern profile can include information regarding service selections made on a user node and movements of a user. The generated user pattern profile can compared to a threshold profile, and based on the results of the comparison, an action can be undertaken. |
| US09679299B2 |
Systems and methods to provide real-time offers via a cooperative database
In one aspect, a computing apparatus is configured to: store transaction data recording transactions processed by a transaction handler; organize third party data according to community, where the third party data includes first data received from a first plurality of entities of a first community and second data received from a second plurality of entities of a second community; and responsive to a request from a merchant in the second community, present an offer of the merchant in the second community to users identified via the transaction data and the first data received from the first plurality of entities of the first community. In one embodiment, the first data provides permission from the merchant in the first community to allow the merchant in the second community to use intelligence information of the first community to identify users for targeting offers from the merchant in the second community. |
| US09679296B2 |
Promotion code validation apparatus and method
A method including interacting with a promotion code provider programmatically, providing a promotion code to a validation function of the promotion code provider, and evaluating a response from the promotion code provider. The act of interacting with a promotion code provider can include controlling an interface that simulates user actions, such as but not limited to controlling an in-memory web browser through an API, where the API provides a set of functions for simulating user actions. Accordingly, the method can be used to quickly and easily determine whether one or more promotion codes, such as online coupons, are valid. |
| US09679295B2 |
Methods and apparatuses for sorting lists for presentation
Methods and apparatuses for sorting seller listings or advertisements of a seller network. In one embodiment, a method includes: determining an indicator of potential revenue for a first party from price information of a list of entities, wherein revenue generated according to the price information of at least some of the list of entities is to be split among a plurality of parties; and, sorting the list of entities into a first list based at least partially on the indicator of potential revenue. |
| US09679291B2 |
System and method of transmitting data over a voice channel
A method for transmitting data over a voice channel by transcoding a bit of the data stream into two bits, and converting each of such two bits into a value of a parameter of a curve of a sound frequency that can be carried on the voice channel. At the receiving end of the voice channel, the values of the parameters of the curve are reconverted into bits, and the pairs of bits are transcoded back into the bit of the data stream. |
| US09679286B2 |
Methods and apparatus for enabling secure network-based transactions
An apparatus includes a transaction card bearing data and having an output interface capable of transmitting the data, a card reader having an input interface enabled to accept the data from the output interface of the transaction card, conversion circuitry converting the card data to an analog modulated signal, and an output pin from the card reader adapted to engage in a microphone port of a computerized appliance, the output pin providing the analog modulated signal to the port, and thence to the computerized appliance. |
| US09679279B1 |
Managing transfer of hosted service licenses
Systems and methods are disclosed which facilitate transfer of licenses corresponding to hosted services. Customers may purchase licenses to services implemented by a hosted computing environment. Thereafter, customers may elect to transfer all or a portion of that license to a second customer. In some embodiments, a customer may transfer the entirety of their service license. In other embodiments, a customer may transfer only a portion of their service license. In still more embodiments, a customer may temporarily transfer a license. For example, a customer may transfer a license only when they are not using the license. |
| US09679276B1 |
Systems and methods for using a block chain to certify the existence, integrity, and/or ownership of a file or communication
A block chain may be used to certify the existence, integrity, and/or ownership of a file or communication. The present disclosure describes receiving a plurality of data units; hashing the plurality of data units to provide a plurality of hashes, individual hashes being unique cryptographic identifiers of corresponding data units such that an individual hash verifiably relates to a corresponding data unit and the individual hashes cannot be used by themselves to obtain corresponding data units; temporarily storing the hashes; generating a first cryptographic structure based on the plurality of hashes; publishing the first cryptographic structure on the block chain; providing proofs associated with individual ones of the plurality of data units that allow independent verification that the data units are certified; and verifying certification of data units based on roots of reconstructed cryptographic structures. |
| US09679273B2 |
Method, system and communication device for generating notification signals
According to embodiments described in the specification, a method, system and apparatus for generating notification signals are provided. The method includes storing an identifier of a slave device in a memory of a master device; detecting, at a processor interconnected with the memory, a notification message via execution of a notification application; in response to detecting the notification message, retrieving the slave device identifier and transmitting an instruction message to the slave device, the instruction message including an identifier of the notification message and an alert parameter; and generating an alert via an output device interconnected with the processor according to the alert parameter. |
| US09679271B2 |
System and method for product delivery
A system and method for delivering a product such as a pharmacy bottle from a conveyor system to a delivery container via a delivery chute. A sensor is placed at a top opening of the chute to sense for product in the chute area and to provide instructions to complete the delivery order if the chute area is clear. |
| US09679270B2 |
Robotic ordering and delivery system software and methods
Systems, methods and devices for the automated delivery of goods form one to another using a robotic tug and accompanying cart. A computer within the tug or cart stores an electronic map of the building floor plan and intended paths for the tug to take when traversing from one location to the next. During the delivery, a variety of different sensors and scanners gather data that is used to avoid obstacles and/or adjust the movement of the tug in order to more closely follow the intended path. The system preferably includes both wired and wireless networks that allow one or more tugs to communicate with a tug base station, a primary network located at the site of the delivery and a remote host center that monitors the status and data collected by the tugs. |
| US09679267B2 |
High performance map editor for business analysts
At least one model synchronization map table is built that facilitates navigation between elements of business objects of a business object model and corresponding elements of an extensible markup language (XML) schema definition-based (XSD-based) model. The XSD-based model includes at least one XML schema and is generated from the business object model. The business object model and the XSD-based model are displayed in a dual-view editor. The dual-view editor enables a user to toggle between and independently edit the business object model and the XSD-based model. In response to independent edits made to one of the XSD-based model and the business object model within the dual-view editor, the elements of the business object model are automatically synchronized with the corresponding elements of the XSD-based model using the at least one model synchronization map table. |
| US09679266B2 |
Systems and methods for intelligent batch processing of business events
Systems and methods are provided for intelligent batch processing of business events. An exemplary method includes accessing a business process having a plurality of events for execution, determining, using one or more hardware processors, a batch group for processing comprising at least one of the plurality of events, wherein the batch group is determined using a time delay for collecting the at least one of the plurality of events to determine the batch group, and submitting the batch group for processing the at least one of the plurality of events. The method may further include processing the batch group as a first transaction. Processing the first transaction may include determining a resource required by the at least one of the plurality of events and attempting to lock the resource for use during the processing the batch group. |
| US09679264B2 |
Role discovery using privilege cluster analysis
Systems and methods used in human resource management systems. The method optimizes the assignment of permissions (e.g., ability to write to a database, ability to create a new account, etc.) to jobs. The method discovers relationships between jobs, duties and privileges by accessing an organization chart that relates a plurality of jobs, a plurality of specific duties to be performed within the purview of a given job, and a plurality of permissions for the respective duties of the job. The method then flattens the organization chart to enumerate the permissions inherited by the jobs. The method proceeds to mine the inherited permissions across the jobs to optimize the sets of permissions. The sets can be optimized (e.g., minimize number of sets, maximize coverage, etc.) and named so as to be conveniently assigned (e.g., by an HR person) to a job (e.g., in the case of a new employee). |
| US09679263B2 |
Multi-phase search and presentation for vertical search websites
The present invention provides a methodology and system for efficiently performing travel reservation queries and presenting significant search results to a user. A travel reservation search engine constructs a first query from one or more constraints. The first query has a threshold probability of returning a first set of search results that will lead to the purchase of a travel reservation. Additionally, if determined necessary by the search engine a second query is constructed from one or more constraints. The second query returns a second set of search results. |
| US09679261B1 |
Machine learning classifier that compares price risk score, supplier risk score, and item risk score to a threshold
A machine learning classifier based procurement system determines a price risk score, a supplier risk score, and an item risk score for bids based on classifications performed by a machine learning classifier. The scores are compared to respective thresholds to determine if any of the bids are associated with a high-risk procurement. |
| US09679260B2 |
System and method for adaptive filter
In one embodiment, a method for training an adaptive filter includes receiving, by a processor from a device, an input signal and a training reference signal and determining a correlation matrix in accordance with the input signal, the training reference signal, and a filter type. The method also includes determining a plurality of coefficients in accordance with the correlation matrix and adjusting the adaptive filter in accordance with the plurality of coefficients. |
| US09679259B1 |
Systems and methods for training and employing a machine learning system in evaluating entity pairs
A matching or pairing system and method for matching first and second entities having a greater likelihood of forming a successful pairing includes a trained machine learning system to provide heuristic values useful in determining a compatibility score for the pairing. During training of the machine learning system, a training example selection device can provide attribute values logically associated with entities engaged in historically successful pairings and a number of hypothetically successful pairings. The hypothetically successful pairings may be based at least in part on historically successful pairings where at least one attribute value logically associated with at least one entity in the pairing is varied, adjusted, or subjected to a loosened constraint. During run-time operation a screening device can screen unsuccessful pairings and forward potentially successful pairings that meet a threshold value to the neural network. The system can then determine a compatibility score for the pairing. |
| US09679258B2 |
Methods and apparatus for reinforcement learning
We describe a method of reinforcement learning for a subject system having multiple states and actions to move from one state to the next. Training data is generated by operating on the system with a succession of actions and used to train a second neural network. Target values for training the second neural network are derived from a first neural network which is generated by copying weights of the second neural network at intervals. |
| US09679255B1 |
Event condition detection
A method includes receiving data from a sensor over time. The data comprises a plurality of values that are each indicative of a sensed condition at a unique time. The method also includes determining a real-time value, a mid-term moving average, and a long-term moving average based on the data and determining a most-recent combined average by averaging the real-time value, the mid-term moving average, and the long-term moving average. The method further includes determining an upper setpoint by adding an offset value to the most-recent combined average and determining a lower setpoint by subtracting the offset value to the most-recent combined average. The method also includes transmitting an alert based on a determination that a most recent value of the data is either greater than the upper setpoint or lower than the lower setpoint. |
| US09679254B1 |
Extrapolating trends in trust scores
Systems and methods are described herein for extrapolating trends in trust scores. A trust score may reflect the trustworthiness, reputation, membership, status, and/or influence of the entity in a particular community or in relation to another entity. An entity's trust score may be calculated based on data from a variety of data sources, and this data may be updated periodically as data is updated and new data becomes available. However, it may be difficult to update a trust score for an entity due to a scarcity of information. The trust score for such entities may be updated based on trends observed for the updated trust scores of other entities over a similar period of time. In this manner, trust scores may be updated for entities for which updated data is not available. |
| US09679251B2 |
Augmented knowledge base and reasoning with uncertainties and/or incompleteness
A knowledge-based system under uncertainties and/or incompleteness, referred to as augmented knowledge base (AKB) is provided, including constructing, reasoning, analyzing and applying AKBs by creating objects in the form E→A, where A is a rule in a knowledgebase and E is a set of evidences that supports the rule A. A reasoning scheme under uncertainties and/or incompleteness is provided as augmented reasoning (AR). |
| US09679243B2 |
System and method for detecting platform anomalies through neural networks
A system and method for detecting behavior of a computing platform that includes obtaining platform data; for each data motif identifiers in a set data motif identifiers, performing data motif detection on data in an associated timescale, wherein a first data motif identifier operates on data in a first timescale, wherein a second data motif identifier operates on data in a second timescale, wherein the first timescale and second timescale are different; in a neural network model, synthesizing platform data anomaly detection with at least a set of features inputs from data motif detection of the set of motif identifiers; and signaling if a platform data anomaly is detected through the neural network model. |
| US09679241B2 |
Thermodynamic random access memory for neuromorphic computing utilizing AHaH (anti-hebbian and hebbian) and memristor components
A thermodynamic random access memory includes one or more AHaH (Anti-Hebbian and Hebbian) node wherein read out of data is accomplished via a common summing electrode through memristive components and wherein multiple input cells are simultaneously active. A ktRAM architecture comprising a memory wherein each input synapse or “bit” of the memory interacts on or with a common electrode through a common “dendritic” electrode, and wherein each input can be individually driven. Each input constitutes a memory cell driving a common electrode. |
| US09679234B2 |
Charging card using power harvested from reader
Disclosed is a rechargeable payment card that can harvest charging energy from card readers. The rechargeable payment card includes a card body and electrical circuitry, a rechargeable energy storage device and a reader interface. The electrical circuitry and the rechargeable energy storage device are attached to the card body. At least a portion of the electrical circuitry needs power to operate when the card is not coupled to an external electrical energy source. The rechargeable energy storage device supplies power to said at least a portion of the electrical circuitry. The reader interface can draw an electrical current from a card reader when the card is coupled to the card reader via the reader interface. At least a portion of the drawn electrical current is used to charge the rechargeable energy storage device. |
| US09679232B2 |
Electronic apparatus
An electronic apparatus includes the following elements. A circuit forming device forms a circuit configured in accordance with configuration information. A first storage unit stores first configuration information externally obtained via a first communication line. The first configuration information is used for forming a first circuit implementing a function including a first communication function in the circuit forming device. A second storage unit stores second configuration information different from the first configuration information. The second configuration information is used for forming a second circuit implementing a function including the first communication function in the circuit forming device. A recovery controller performs control so that the second circuit is formed in the circuit forming device by using the second configuration information, upon the occurrence of an error in communication via the first communication line when the first circuit is formed in the circuit forming device by using the first configuration information. |
| US09679229B2 |
Credential production device card substrate rotator
Some embodiments of a card rotator include a card receptacle, a feed roller, and a motor. The card receptacle is configured to rotate about a pivot access that is approximately perpendicular to a plane of a card substrate supported by the card receptacle. The feed roller is configured to discharge a card substrate from the card receptacle. The feed roller has an axis of rotation that is approximately perpendicular to the pivot axis. The motor is configured to drive rotation of the card receptacle about the pivot axis relative to the axis of rotation of the feed roller. |
| US09679228B2 |
Image forming apparatus, image forming system, image forming method, and non-transitory computer readable medium
An image forming apparatus includes a generating unit, a print instruction providing unit, and a display. The generating unit generates print data of a sample sheet if a request for outputting the sample sheet is received while print data formed of plural pages is being generated. The print instruction providing unit provides a print instruction for the print data of the sample sheet after providing a print instruction for the print data that has been generated. The display displays, based on the print data of the sample sheet, an attribute of the sample sheet. |
| US09679227B2 |
System and method for detecting features in aerial images using disparity mapping and segmentation techniques
A system for aerial image detection and classification is provided herein. The system comprising an aerial image database storing one or more aerial images electronically received from one or more image providers, and an object detection pre-processing engine in electronic communication with the aerial image database, the object detection pre-processing engine detecting and classifying objects using a disparity mapping generation sub-process to automatically process the one or more aerial images to generate a disparity map providing elevation information, a segmentation sub-process to automatically apply a pre-defined elevation threshold to the disparity map, the pre-defined elevation threshold adjustable by a user, and a classification sub-process to automatically detect and classify objects in the one or more stereoscopic pairs of aerial images by applying one or more automated detectors based on classification parameters and the pre-defined elevation threshold. |
| US09679226B1 |
Hierarchical conditional random field model for labeling and segmenting images
An image processing system automatically segments and labels an image using a hierarchical classification model. A global classification model determines initial labels for an image based on features of the image. A label-based descriptor is generated based on the initial labels. A local classification model is then selected from a plurality of learned local classification model based on the label-based descriptor. The local classification model is applied to the features of the input image to determined refined labels. The refined labels are stored in association with the input image. |
| US09679225B2 |
Extracting card data with linear and nonlinear transformations
Embodiments herein provide computer-implemented techniques for allowing a user computing device to extract financial card information using optical character recognition (“OCR”). Extracting financial card information may be improved by applying various classifiers and other transformations to the image data. For example, applying a linear classifier to the image to determine digit locations before applying the OCR algorithm allows the user computing device to use less processing capacity to extract accurate card data. The OCR application may train a classifier to use the wear patterns of a card to improve OCR algorithm performance. The OCR application may apply a linear classifier and then a nonlinear classifier to improve the performance and the accuracy of the OCR algorithm. The OCR application uses the known digit patterns used by typical credit and debit cards to improve the accuracy of the OCR algorithm. |
| US09679223B2 |
Image processing method and apparatus
An image processing method includes searching for areas matching each other between a plurality of input images, the plurality of input images comprising a reference image and a target image, generating hierarchical image structures formed of a plurality of hierarchical images having different resolutions with respect to the matching areas between the plurality of input images, repeatedly performing image processing based on a similarity of values of pixels matching each other in the plurality of hierarchical images of the same level by using the hierarchical image structures generated with respect to the matching areas, and generating an output image by using pixel values according to the repeated image processing. |
| US09679222B2 |
Apparatus and method for detecting a feature in an image
An apparatus for detecting a feature in an image includes an image input section for receiving at least part of the image in the form of image data having a plurality of pixels, the plurality of pixels comprising a plurality of non-border pixels, a feature detection module adapted to attribute a feature probability value to each of the pixels of the image data, and an extremum determination module for determining at least one local extremum among the feature probability values, wherein the extremum determination module is adapted to output, for each of the plurality of pixels, a final indication if the feature probability value of the pixel in question is a local extremum. The extremum determination module is adapted to use, for each of the plurality of non-border pixels, comparison results of at least two comparison operations, with each comparison operation including a comparison of the feature probability value of the non-border pixel in question with the feature probability values of a respective subset of neighboring pixels, with the respective subsets of neighboring pixels being different subsets. |
| US09679217B2 |
Information processing apparatus, information processing system, information processing method and storage medium
According to one embodiment, an information processing apparatus includes an image acquisition module, an elevation-angle acquisition module, a character deformation specification module, a character detection dictionary storage, a character detection dictionary selector and a character detector. The elevation-angle acquisition module is configured to acquire an elevation angle of a photographic device assumed when the photographic device has obtained an acquired image. The character deformation specification module is configured to specify how an appearance of the character in the acquired image is deformed, based on the acquired elevation angle. |
| US09679208B2 |
Traffic light detecting device and traffic light detecting method
A traffic light detecting device includes an image capturing unit configured to repeatedly capture images in a travelling direction of a vehicle to obtain a series of multiple images and a traffic light detecting unit configured to detect traffic lights from the images. The traffic light detecting unit detects phase information of an electric power system used in an area around the vehicle including the traffic lights from a cycle of a luminance variation in the series of multiple images and extracts from the images a synchronized pixel with a luminance which varies in synchronization with an alternating current cycle of electric power supplied to the traffic light by using the phase information of the electric power system. The traffic light detecting device judges from the synchronized pixel whether or not the traffic light is present. |
| US09679205B2 |
Method and system for displaying stereo image by cascade structure and analyzing target in image
A method and a system for analyzing a target in a stereo image by displaying the stereo image using a cascade structure are disclosed. The method includes for the input stereo image, generating, based on a first relevant feature, rule or model of the stereo image, at least a first first-level structure map, each of the first first-level structure maps being generated based on an individual tolerance level of the first relevant feature, rule or model, and each of the first first-level structure maps including the target at an individual first division level; and at least partly integrating the first first-level structure maps and analyzing the target in the stereo image, to obtain a structure map of a first-level target analysis result including the target. |
| US09679200B2 |
Image processing to derive movement characteristics for a plurality of queue objects
In queues, persons—or objects (120) in general—move inside an area (110) to a target (112), such as to a counter. The queue has movement characteristics in terms of speed, waiting times and queue form. A computer-implemented approach obtains the characteristics by receiving a sequence (140) of image frames (141, 142, 143, 49) that represent the surveillance area (110); calculating flow vectors that indicate an optical displacement for the sequence (140) of image frames (141/142, 142/143); extending one of the flow vectors as lead vector in extension directions; determining intermediate vectors by using flow vectors along the extension directions; and selecting one the intermediate vectors as the new lead vector. The steps are repeated to concatenate the lead vectors to the movement characteristics (190). |