最新美国发明专利第2016-09-06期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US09438258B1	Preamplifier, comparator and analog-to-digital converting apparatus including the same A preamplifier may include: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing an output polarity of output nodes; a multi-differential input stage suitable for receiving an input voltage, a coarse ramping voltage, a fine ramping voltage and a common mode voltage, and sampling the common mode voltage and the coarse ramping voltage for amplification operations; and a coupling blocking unit suitable for blocking a coupling between the output nodes and input nodes that are included in the multi-differential input stage.
US09438254B1	Charge pump circuit for a phase locked loop A phase-locked-loop includes a phase-frequency-detector (PFD) comparing phases of an input signal and feedback signal, and generating therefrom control signals. An attenuation circuit in series with the PFD includes a filter between a voltage-controlled-oscillator (VCO) control node and ground. A buffer is coupled to the VCO control node. An impedance network is coupled to the VCO control node and has an impedance element coupled to a first current source so voltage at the VCO control node increases when control signals indicate the phase of the input signal leads the feedback signal, and coupled to a second current source so voltage at the VCO control node decreases when control signals indicate a lagging phase. A VCO is coupled to the VCO control node to generate an output signal, with the phase of the output signal matching the input signal. The feedback signal is based upon the output signal.
US09438241B1	Multipurpose pads used as digital serial and analog interface An Integrated Circuit, a system, and a method are provided. The disclosed Integrated Circuit may include a plurality of pads exposing internal components of the Integrated Circuit to external circuits, a digital interface connectable to the plurality of pads, an analog interface connectable to the plurality of pads, and sensing circuitry configured to detect whether a digital circuit or an analog circuit is externally connected to the plurality of pads and based on such detection selectively connect at least one of the digital interface and analog interface to the plurality of pads.
US09438240B1	Biasing circuit for level shifter with isolation A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.
US09438236B2	Input/output driver circuit, integrated circuit and method therefor An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.
US09438230B2	Gate drive circuit A gate drive circuit in an aspect of the present disclosure includes a modulated signal generation circuit that generates a first modulated signal, a first isolator that isolatedly transmits the first modulated signal, and a first rectifier circuit that generates a first output signal by rectifying the first modulated signal. The first modulated signal includes a first amplitude, a second amplitude larger than the first amplitude, and a third amplitude larger than the second amplitude. The first output signal includes a first output voltage value according to the first amplitude, a second output voltage value according to the second amplitude, and a third output voltage value according to the third amplitude.
US09438228B2	High efficiency gate drive circuit for power transistors An improved gate drive circuit is provided for a power device, such as a transistor. The gate driver circuit may include: a current control circuit; a first secondary current source that is used to control the switching transient during turn off of the power transistor and a second secondary current source that is used to control the switching transient during turn on of the power transistor. In operation, the current control circuit operates, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor. The first and second secondary current sources adjust the gate drive current to control the voltage or current rate of change and thereby the overshoot during the switching transient.
US09438221B2	Switch device Switch devices with a first switching path and a second switching path are provided in some embodiments. When a voltage drop across the first switching path exceeds a predetermined voltage, the second switch may be activated.
US09438219B2	Hybrid digital pulse width modulation (PWM) based on phases of a system clock Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers.
US09438218B2	Photorepeated integrated circuit with compensation of the propagation delays of signals, notably of clock signals Integrated circuits of large size produced by photorepetition of several mutually identical partial patterns are provided, more precisely to the compensation of propagation delays of signals (notably of clock signals) from one partial circuit to the following whereas the signals concerned must reach the various partial circuits simultaneously for proper operation of the whole. The compensation circuit provided in each partial circuit comprises a main transmission line for a master clock signal and a compensation line with multiple outputs, as well as a multiplexer for selecting one of the outputs, the output selected being different in the various partial circuits. The multiplexer provides a local clock signal in each partial circuit and these clock signals are synchronous despite the propagation delays.
US09438215B2	Buffer circuit for buffering and settling input voltage to target voltage level and operation method thereof A buffer circuit includes an amplifying unit suitable for comparing an input voltage of an input terminal with an output voltage of an output terminal, a current sinking unit suitable for controlling a sinking current of the amplifying unit when the input voltage is varied, and a current compensation unit suitable for uniformly maintaining a sinking current amount of the current sinking unit.
US09438213B2	Low power master-slave flip-flop A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.
US09438211B1	High speed latch and method An embodiment latch device includes a first stage having circuitry that receives a differential input and generates a clocked data signal according to a clock signal and the differential input, and a second stage connected to the first stage and having circuitry that generates differential outputs according to the clock signal and the clocked data signal. The second stage further has a reset circuit that resets a latch storage to a high value according to the clock signal.
US09438210B1	Semiconductor devices employing a data inversion scheme for improved input/output characteristics A semiconductor device may include a data output circuit and a control signal output circuit. The data output circuit may compare a first input signal or a second input signal with a storage datum to generate a first comparison selection signal and may compare the first input signal with the second input signal to generate a second comparison selection signal. The control signal output circuit may detect logic levels of bits included in the first and second comparison selection signals to generate first and second detection signals, generate first and second flag signals from the first and second detection signals in response to a storage flag signal, and sequentially output the first and second flag signals as transmission control signals.
US09438209B2	Implementing clock receiver with low jitter and enhanced duty cycle A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.
US09438206B2	Storage circuit and semiconductor device The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.
US09438204B2	Signal processing device and signal processing method Embodiments of the invention disclose a signal processing device and a signal processing method and a device and a method for signal processing. The signal processing device includes a sampling module, a first segmentation module, a second segmentation module, and a detection module. The sampling module samples an input signal to generate a sample signal. The first segmentation module calculates a first segment value according to the sample signal during a first time interval. The second segmentation module calculates a second segment value according to the sample signal during a second time interval different in length from the first time interval. The detection module generates a detection signal according to the determination of whether the first segment value lies out of a first range, and whether the second segment value lies out of a second range.
US09438201B2	Composite substrates for acoustic wave elements, and acoustic wave elements A composite substrate for an acoustic wave element includes a support substrate 1 and a propagation substrate 3 for propagating an acoustic wave. The propagation substrate is bonded to the support substrate 1 and composed of a piezoelectric single crystal. The propagation substrate 3 includes a surface lattice distortion layer 11 in which crystal lattices of the piezoelectric single crystal are distorted.
US09438199B2	Component package including matching circuit and matching method thereof Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.
US09438197B2	Reconfigurable multi-band filter Reconfigurable multi-band filter techniques are described. In one or more implementations a device includes a radiating structure and a filter connected to the radiating structure configured to filter wireless signals received by the radiating structure. The filter includes switchable resonators configured to tune to different frequency bands and tunable capacitors configured to tune to different frequencies within the different frequency bands.
US09438190B1	Amplification circuit adjusting duty cycle of output signal and receiver including the same A receiver includes a first stage buffer, a second stage buffer and a third stage buffer. The first stage buffer includes an input portion electrically coupled to a first voltage node, and configured to change a voltage level of an output node in response to an input signal, first and second load portions electrically coupled between a second voltage node and the output node, and electrically coupled to each other and a duty cycle adjustment portion electrically coupled between the first and second load portions, and configured to provide a correction current to the output node through the first load portion.
US09438188B2	Common-gate amplifier for high-speed DC-coupling communications In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage.
US09438186B2	Power amplifier with envelope injection A device and a method for an amplifier having reduced intermodulation (IM) distortion output products are presented. An amplifier has an output, and at least one of a gate bias input and a drain supply input. The amplifier is configured to receive an input signal and output an amplified signal at the output of the amplified. An input is configured to receive an envelope signal. The input is connected to the at least one of the gate bias input and the drain supply input and the envelope signal is at least partially determined by an attribute of the input signal to the amplifier. A controller is configured to modify at least one of an amplitude and a phase of the envelope signal to reduce a magnitude of an intermodulation distortion product of the amplifier.
US09438183B2	Amplifier device and method for activating an amplifier device or the amplifier unit Known types of amplifiers include so-called class D amplifiers, which first use a pulse-width modulator to convert an analog signal into a pulse-width modulated switching signal, which is then amplified and subsequently converted back into a continuously variable voltage via a filter. This type of amplifier is particularly energy-efficient and is therefore preferably used for high-power amplifiers. The invention relates to an amplifier device 1 comprising a control device (5), wherein the control device (5) has an input interface for an audio signal (2), and comprising an amplifier unit (9) for amplifying the audio signal (2, 8) downstream of the control device (5), wherein the control device (5) has a delay module (6) that is designed to transmit the audio signal (2), delayed by a delay value delta_t, to the amplifier unit (9) and to automatically and/or autonomously reduce the delay value delta_t from a starting value delta_t to a final value during an adaptation phase AP.
US09438180B2	Radio frequency power amplifier and method for increasing power added efficiency and linearity A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes an impedance transformation circuit, a current unit gain amplifier, and an output match circuit. The impedance transformation circuit receives a first input power signal and outputs a second input power signal correspondingly, wherein the impedance transformation circuit transforms an input impedance to an output impedance according to an impedance matching parameter for increasing power added efficiency of a pre-stage circuit. The current unit gain amplifier provides a linear transimpedance so as to transmit an input current to an output impedance, and then generate a linear output power for increasing power added efficiency of the current unit gain amplifier, wherein the impedance matching parameter is determined by a first system voltage, a second system voltage, and a predetermined power gain value.
US09438178B1	Mixer impairment correction based on volterra series Techniques for compensating for signal impairments introduced by a mixer are discussed. One example system employing such techniques can include mixer predistortion circuitry configured to receive signal in-phase (I) and signal quadrature (Q) components of a signal and to generate a mixer predistortion signal based at least in part on the signal I and Q components, wherein the mixer predistortion signal compensates for nonlinearities caused by a mixer that upconverts the signal. Optionally, imbalance correction circuitry to compensate for gain and phase imbalance and/or skew correction circuitry to compensate for gain and phase skew can also be included.
US09438174B2	Quasi-broadband amplifier according to the Doherty principle An amplifier comprises a first amplifier circuit, a second amplifier circuit, a hybrid-coupler circuit and a termination. The hybrid-coupler circuit comprises an output port and an isolation port. The termination in this context is connected to the isolation port of the hybrid-coupler circuit. The termination comprises a first switch, a first capacitor and a first inductance.
US09438173B2	Multiple-series amplifying device A multiple-series amplifying device (100) of the present invention includes multiple series of amplifiers (110, 120) which are formed in parallel so as to input and output signals individually. Each of multiple-series of amplifiers (110, 120) includes a plurality of semiconductor amplifying elements (111, 112, 121, 122) which are driven in parallel so as to amplify signals. A pair of semiconductor amplifying elements (112, 121) adjoining together in a pair of amplifiers (110, 120) is formed in a single package (130).
US09438170B2	Power amplifier A power amplifier includes an input circuit configured to receive an input signal. At least two transistors connected in series. A first transistor of the at least two transistors is located at a first end of the at least two transistors. A second transistor of the at least two transistors is located at a second end of the at least two transistors. The first transistor is coupled to a low voltage power supply node. The first gate of the first transistor is coupled to a first bias voltage. The input signal is coupled to a first gate of the first transistor. At least one capacitor is coupled between a second gate of the second transistor and the low voltage power supply node. An output circuit coupled to a second gate of the second transistor.
US09438168B2	Oscillator An oscillator includes a resonator configured to resonate an electromagnetic wave in a resonant axis direction and a capacitance unit electrically connected in parallel to the resonator. The resonator includes a negative resistor, a first conductive layer, and a second conductive layer, where the negative resistor has a gain to the electromagnetic wave and is disposed between and in contact with the first conductive layer and the second conductive layer. At a resonant frequency fLC generated by an inductance Ls which the wiring configured to electrically connect the capacitance unit to the resonator and the capacitance unit constitute, and an inner capacitance Cwg of the resonator, a conductance including the inductance Ls, a resistance component Rs of the wiring and the capacitance unit, and a capacitance C of the capacitance unit is equal to or higher than an absolute value Gwg of negative conductance of the negative resistor.
US09438167B2	Oscillation circuit, oscillator, manufacturing method of oscillator, electronic device, and moving object An oscillation circuit includes: an oscillation unit which includes a first terminal and a second terminal connected to a resonator, a third terminal, a fourth terminal to which at least one of a power supply potential and a signal for inspecting the resonator is applied, a first switching unit which switches modes of electrical connection between the first terminal and the third terminal, and a second switching unit which switches modes of electrical connection between the second terminal and the fourth terminal.
US09438164B2	System and method for calibrating capacitor-based oscillators in crystal-less devices A method for calibrating an oscillator in an electronic device and an electronic device configured for calibration are provided. Multiple signals are sent to the electronic device from another electronic device, such as from a host device. With knowledge of the time interval between the multiple signals, the electronic device may calibrate the oscillator in the electronic device. For example, the electronic device may be a USB-compliant electronic device. The USB-compliant electronic device may receive Start of Frame (SoF) signals from a host device, which in one USB implementation is received at 1 mSec intervals. The USB-compliant electronic device may count the output of the oscillator between receipt of different SoF signals in order to determine the frequency of the oscillator at different oscillator settings.
US09438163B2	Ultra-low voltage-controlled oscillator with trifilar coupling The present disclosure relates to a device and method to reduce voltage headroom within a voltage-controlled oscillator by utilizing trifilar coupling or transformer feedback with a capacitive coupling technique. In some embodiments of trifilar coupling, a VCO comprises cross-coupled single-ended oscillators, wherein the voltage of first gate within a first single-ended oscillator is separated from the voltage of a second drain within a second single-ended oscillator within the cross-coupled pair. A trifilar coupling network is composed of a drain inductive component, a source inductive component, and a gate inductive component for a single-ended oscillator, wherein a coupling between drain inductive components and gate inductive components between single-ended oscillators along with a negative feedback loop within each single-ended oscillator forms a cross-coupled pair of transistors which reduces the drain-to-source voltage headroom to approximately a saturation voltage of a transistor within the cross-coupled pair. Other devices and methods are also disclosed.
US09438161B2	Bracket for connection of a junction box to photovoltaic panels A device for attaching a junction box to a photovoltaic. The photovoltaic panel has a photovoltaic side and a non-photovoltaic side. The device includes a bracket with a first side attachable to the junction box and a second side attachable to the non-photovoltaic surface of the photovoltaic panel. A central fastener is attachable at one end to the bracket and a plate is adapted for connecting to the other end of the central fastener and for mounting on the photovoltaic side of the photovoltaic panel. One or more rotatable spacers, connectible to the central fastener, may be located on the non-photovoltaic side of the photovoltaic panel. One or more fixed spacers may be located on the non-photovoltaic side connectible to the bracket.
US09438157B2	Method for operating a multiphase electric machine and corresponding multiphase electric machine In a method for operating a multiphase electrical machine, which includes a rotor and a rotary encoder operatively connected to the rotor, an actual rotational angle of the rotor is determined from a measured rotational angle determined by means of the rotary encoder and a rotational angle offset. To determine the rotational angle offset the rotor is brought to a specific rotational speed and then an active short circuit of the electrical machine is initiated, wherein an actual current vector is determined, using a dq-transformation, from the current intensities of the currents flowing in at least two of the phases of the electrical machine and the measured rotational angle determined by means of the rotary encoder, and wherein the rotational angle offset is calculated from the actual current vector and a reference current vector.
US09438154B2	Method and device for controlling a motor vehicle windscreen wiper motor Method of controlling a motor vehicle windscreen wiper motor, powered and controlled by pulse width modulation (PWM) with duty ratio (T) of determined value, in which the instantaneous fundamental period of the modulated pulses is switched successively between at least two discrete period values (T1, T2), the duty ratio (T) of the pulses (PWM) being substantially established at a determined value for at least one determined duration (Tc) of switching of the modulated pulses. Application to the reduction of the EMC noise level in the radio frequency bands to be protected.
US09438152B2	Electronically commutated electric motor comprising rotor position detection with interference field compensation An electronically commutated electric motor includes a stator and a rotor formed as a permanent magnet. A control unit is connected to the stator and configured to energize the stator to produce a rotating magnetic field. The electric motor further includes at least one Hall sensor configured to detect at least a magnitude of a sensor magnetic field produced by a sensor magnet connected to the rotor. The electric motor also includes at least one magneto resistive sensor configured to detect an alignment of a total magnetic field during a rotor revolution of the rotor and to generate a rotor position signal representing this alignment. The total magnetic field includes the sensor magnetic field and an interference magnetic field superimposed thereon. The control unit is further configured to determine the rotor position of the rotor at least depending on the alignment of the total magnetic field.
US09438146B2	Reducing the power consumption of a brushless motor A method of controlling a brushless motor. The method includes measuring a temperature of the motor, adjusting a control value in the event that the measured temperature is lower than a threshold, and exciting a winding of the motor. The control value is then used to define an attribute of excitation, and the adjustment to the control value reduces the input power of the motor.
US09438144B2	System and method for fault protection of a motor An exemplary motor driving system includes a power source, a driving circuit, a controller, a motor, and a protection circuit. The driving circuit including at least one switching device coupled with the power source. The motor includes a plurality of windings. The motor is coupled with the driving circuit and driven by the driving circuit. The controller is configured to provide first switch signals to the at least one switching device of the driving circuit in a normal mode. The protection circuit is coupled with the controller, and configured to generate second switch signals based at least in part on a fault signal in a fault mode and provide the second switch signals to the at least one switching device of the driving circuit so as to reconstruct circuit loops between the driving circuit and the plurality of windings. A method for operating the motor driving system is also described.
US09438143B2	Drive control device A PWM signal generator section for generating a plurality of PWM signals with different phases to be respectively fed to a plurality of loads, and a phase difference setting section for setting phase differences among the PWM signals are provided. The phase difference setting section sets phase differences Δt_shift(n,n+1) calculated based on an effective current Ia(n) flowing to each of the loads, where the number of the loads is N, according to the equations below: Ia_all = ∑ n = 1 N ⁢ Ia ⁡ ( n ) ⁢ t_shift ⁢ ( n , n + 1 ) = t_pwn × Ia ⁡ ( n ) / Ia_all where n=1 to N (where N is an integer of two or more, and n+1=1 when n+1>N), and t_pwm is a cycle of the PWM signals.
US09438141B2	Braking apparatus for electric power tool One aspect of an embodiment of the present disclosure is a braking apparatus for an electric power tool that includes a switching circuit with six switching elements and a brake control unit. The brake control unit switches any one selected switching element of three switching elements forming one selected switch group of a high-side switch group and a low-side switch group to an off state from an on state at a timing at which braking current flows through a diode connected in parallel to the selected switching element upon turn-off of the selected switching element.
US09438139B2	Energy harvesting devices for low frequency applications An energy harvesting device has been developed for low frequency applications. The energy harvesting device is comprised of a buckling member having a longitudinal axis and configured to exhibit multiple snap-through events in response to a deformation applied axially thereto, where the buckling member is constrained laterally in relation to the longitudinal axis; and at least one cantilever extends outwardly from the buckling member. The cantilever(s) is coated with a piezoelectric material and supports a mass disposed at an opposing end from which it is attached to the buckling member. In this arrangement, the buckling member is able to respond to axial deformations occurring at a frequency less than one Hertz.
US09438138B2	Magnetostrictive devices and systems The device generates electrical energy from mechanical motion. The device includes at least one magnetostrictive element and at least one force modifier. The force modifier is coupled to the magnetostrictive element. The force modifier receives an input force and applies a modified force to the magnetostrictive element.
US09438137B2	Method and device for operating a piezoelectric actuator A method for operating a piezoelectric actuator which may be activated with the aid of an activation signal. The piezoelectric actuator is operable in a passive and in an active operating mode. The piezoelectric actuator is activated without a functional operating request if the piezoelectric actuator is in a passive operating mode.
US09438136B2	Converter for electric power The present invention relates to a converter for electric power having multiple sub-modules connected in series, the sub-modules having an energy storage unit and multiple power semiconductor circuits connected in parallel to the energy storage unit, and which causes an electric current to bypass a sub-module in case the breakdown of the sub-module occurs. To this end, the converter for electric power according to the present invention has multiple sub-modules connected to each other in series, the sub-modules having an energy storage unit and at least one power semiconductor circuit that is connected in parallel to the energy storage unit and comprises multiple power semiconductor switches and freewheeling diodes, wherein each of the sub-modules comprises a bypass switching unit, which is connected in parallel to any one of said at least one power semiconductor circuit, and bypasses an electric current via the bypass switching unit.
US09438132B2	Multilevel AC/DC power converting method and converter device thereof A multilevel AC/DC power converter device includes a high-frequency power converter including a first AC port and a low-frequency power converter including a second AC port and a DC port. A power converting method includes: serially connecting the first AC port of the high-frequency power converter and the second AC port of the low-frequency power converter; operating frequency of the low-frequency power converter synchronized with frequency of an AC power source and operating the high-frequency power converter with high-frequency PWM to generate a multilevel AC voltage; and controlling the multilevel AC voltage to obtain a current of an input AC port being sinusoidal and in a same phase with a voltage of the AC power source. Accordingly, the input power factor approaches unity and the low-frequency power converter supplies a DC voltage to a load via a DC output port.
US09438130B2	Semiconductor device, switching system, and matrix converter A semiconductor device includes a semiconductor switch, a first rectifier circuit, and a second rectifier circuit. The semiconductor switch, the first rectifier circuit, and the second rectifier circuit are integrated on a common board. On the board, a first output terminal of the first rectifier circuit is coupled to a first gate terminal of the semiconductor switch, and a first output reference terminal of the first rectifier circuit is coupled to a first source terminal of the semiconductor switch. On the board, a second output terminal of the second rectifier circuit is coupled to a second gate terminal of the semiconductor switch, and a second output reference terminal of the second rectifier circuit is coupled to a second source terminal of the semiconductor switch.
US09438129B2	Input/output power and signal transfer isolator device Input/output power and signal transfer and power and signal isolator device using pulsed, alternating or high frequency signal current having a capacitive structure which provides power and signal limiting control, unidirectional power and signal transfer and input/output decoupling and transceiver-receiver isolation barrier. The device includes at least two decoupled input electrodes arranged in parallel to each other, and at least two decoupled output electrodes arranged in parallel to each other. Each electrode is connected to at least one terminal. Each electrode has a surface that which is opposed to another electrode surface with at least one layer of dielectric material therebetween. The input electrodes are decoupled from the output electrodes by dielectric material and are disposed such that two output electrodes are separately disposed external to the two input electrodes.
US09438126B2	Power conversion device and power conversion method A power conversion method of a power conversion device including a plurality of primary side ports disposed in a primary side circuit and a plurality of secondary side ports disposed in a secondary side circuit magnetically coupled to the primary side circuit with a transformer, the power conversion device adjusting transmission power transmitted between the primary side circuit and the secondary side circuit by changing a phase difference between switching of the primary side circuit and switching of the secondary side circuit, the power conversion method including: calculating a transmission efficiency setting an adjustment value of the phase difference to a value obtained by dividing the transmission efficiency by a specified efficiency; and setting the phase difference to a value obtained by dividing the calculated value by the adjustment value when the adjustment value is less than the specified value.
US09438124B2	Power supply circuit A power supply circuit includes a plurality of output terminals that output voltages (voltages may have the same or different voltage values among the output terminals), and a transformer that has a plurality of output windings. First and second output windings of the plurality of output windings are coupled to each other. The first and second output windings have the same number of turns. First terminals, which have a first polarity, of the first and second output windings are connected to each other via a capacitor. Further, second terminals, which have a second polarity opposite to the first polarity, of the first and second output windings are electrically connected to each other. The second terminals of the first and second output windings may be directly connected to each other.
US09438121B2	Power converter for reducing standby power consumption A power converter according to examples reduces standby power consumption. The power converter includes a rectifier configured to rectify AC power into DC power, a transformer configured to output power by converting a voltage of DC power rectified by the rectifier, a PWM control module configured to control an output power by switching a power switching device connected to the transformer, a first external switch configured to provide a disable signal, a first capacitor that is connected in parallel to one side of the first external switch, a second external switch configured to provide an enable signal, and a second capacitor that is connected in parallel to one side of the second external switch.
US09438116B2	Control unit for a boost converter device A boost converter device includes a converter, a current sensor which detects a reactor current flowing through a reactor, and a control unit which controls the converter by using feedback control of the reactor current. The control unit executes at least one of reducing a carrier frequency which is used in the control of the converter and reducing a duty command value which is used in the control of the converter, detects an amplitude of current ripple by the current sensor during execution of the reduction of the carrier frequency or the reduction of the duty command value, and detects the current sensor as being abnormal in a case where the amplitude of the current ripple is less than a predetermined current fluctuation range at the time of abnormality of the current sensor.
US09438115B2	Power supply system A power source system (5) includes a direct current power source (10), a direct current power source (20), and a power converter (50) having a plurality of switching elements (S1-S4) and reactors (L1, L2). The power converter (50) performs a direct current voltage conversion between the direct current power sources (10, 20) and a power source line (PL) in parallel by controlling the switching elements (S1-S4). Each of the switching elements (S1-S4) is disposed to be included in both a power conversion path formed between the direct current power source (10) and the power source line (PL), and a power conversion path formed between the direct current power source (20) and the power source line (PL). A phase difference (φ) between a carrier signal used for a pulse width modulation control to perform the direct current voltage conversion for the direct current power source (10), and a carrier signal used for a pulse width modulation control to perform the direct current voltage conversion for the direct current power source (20) is controlled according to the operation condition of the power converter (50).
US09438112B2	Power converter including integrated driver for depletion mode group III-V transistor In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor.
US09438111B2	Circuit and method for reducing inductor magnetic-core loss A circuit for reducing inductor magnetic-core loss is disclosed. The circuit includes a switch transistor, a PWM signal source connecting to the switch transistor, an inductor connecting to the switch transistor, a load connecting to the switch transistor, and a frequency adjustment circuit. The frequency adjustment circuit obtains PWM signals from the PWM signal source and modulates the PWM signals to be a new square-wave signals to be outputted to the switch transistor. The switch transistor is configured for setting the frequency of the square-wave signals as the operation frequency so as to control a duration for which the current flowing through the inductor. The operation frequency of the switch transistor may be adjusted by modulating the frequency of the PWM signals. As such, the duration for which the current flowing through the inductor may be controlled so as to decrease the current amount flowing through the inductor.
US09438109B2	Bi-directional voltage positioning circuit, voltage converter and power supply device including the same A bi-directional voltage positioning circuit includes a voltage to current converter, a current mirror circuit and a switch. The voltage to current converter converts a sensing voltage to a first current, and the sensing voltage is sensed based on a current flowing through an output coil connected between a switching node and an output node. The current mirror circuit mirrors the first current to generate a second current and a third current, the second current is N times greater than the first current, the third current is M times greater than the first current, and N and M are real numbers greater than zero. The switch provides a feedback node with one of the second current and third current in response to a switching control signal, and an output voltage of the output node is divided at the feedback node.
US09438108B2	Bias voltage generating circuit and switching power supply thereof Disclosed herein are bias voltage generating circuits configured for switching power supplies, and associated control methods. In one embodiment, a bias voltage generating circuit can include: (i) a first control circuit configured to compare a drain-source voltage of a switch against a bias voltage; (ii) a capacitor, with the bias voltage across the capacitor; (iii) a second control circuit configured to control the switch, and that is enabled when the bias voltage is at least as high as an expected bias voltage; (iv) the first control circuit being configured to control the capacitor to charge when the drain-source voltage of the switch is greater than the bias voltage; and (v) the bias voltage being less than an overvoltage protection voltage when the capacitor charges, and where the overvoltage protection voltage comprises a voltage that is a predetermined amount higher than the expected bias voltage.
US09438103B2	Low voltage and high driving charge pump The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.
US09438102B2	Phase locked loop having dual bandwidth and method of operating the same A phase locked loop having a dual bandwidth is disclosed. The phase locked loop divides a loop filter into a zero filter and a pole filter, disposes the zero filter in front of a phase-frequency detector (PFD), and performs high-pass filtering on a voltage-controlled oscillator (VCO) noise with a maximum bandwidth and performs low-pass filtering on a charge pump noise (CP noise) with a minimum bandwidth to divide the VCO noise and the CP noise.
US09438101B1	High speed switching solid state relay circuit The invention discloses a high speed switching solid state relay circuit with a switching section, a current limiting section and a voltage limiting section. The switching section comprises a bridge rectifier receiving the load voltage inputs, a MOSFET with a source connected to the negative voltage of the load through the bridge rectifier, a drain connected to the load voltage output, and a gate. The switching section further includes an isolator circuit comprising an optically-coupled LED. The isolator circuit is configured to receive a logic input signal and generate an isolated output signal based on the logic input signal, and the gate of the MOSFET is driven by the isolated output signal. The current limiting section includes a first set of resistors connecting the voltage drop across the load to the gate of the MOSFET through diodes. The voltage limiting section comprises a Zener diode connected to the gate of the MOSFET.
US09438099B2	Harmonic displacement reduction Reducing voltage excursions in a circuit comprises: performing resonant commutation, including transferring, via a first set of one or more diodes, energy stored by a set of one or more parasitic inductances to a set of one or more capacitors; and performing recovery-to-load, including discharging energy stored in the set of one or more capacitors via a second set of one or more diodes, through the set of one or more parasitic inductances to a load of the circuit.
US09438094B2	Connecting system for connection of an electric machine to a converter The arrangement of an electric machine, a connecting system and a converter, includes the connecting system connected between the electric machine and the converter. The connecting system has an enclosure that houses non-shielded conductors each non-shielded conductor is connected between a phase of the electric machine and the inner side of the converter. The non-shielded conductors of the connecting system that are connected to an operating phase of the electric machine are adjacent to conductors of the connecting system that are not connected to operating phases of the electric machine.
US09438091B2	Permanent magnet machine with two stators A permanent magnet machine includes two stationary stators and a rotating rotor. Electromagnetic fields occurring in one stator are displaced by an angle of thirty electrical degrees with respect to electromagnetic fields occurring in the other stator due to currents fed to the stators.
US09438090B2	Method of assembling a rotary electric machine A motor includes a driving shaft, a rotor attached to the driving shaft, and a stator having a substantially cylindrical stator core provided around the rotor, and a plurality of coils wound around the stator core in a distributed winding manner. The stator core includes three separated stator core parts aligned along a peripheral direction, and each of the coils is disposed so as not to lie astride any two of the three separated stator core parts. At least one coil end of the plurality of the coils is disposed to pass through an inner side relative to an inner peripheral surface of the stator core.
US09438087B2	Energy reclamation from air-moving systems A data center includes a computing room, computing devices in the computing room, an air handling system, and a turbine system. Air moved by the air handling system flows across heat producing components in the computing devices in the computing room. A rotor of the turbine system rotates in response to at least a portion of the air moved by the air handling system. The turbine system generates electricity from rotation of the rotor.
US09438083B2	Motor having a braking function and used in linear actuator A motor, which has a braking function and is used in a linear actuator includes a main body, a rotation shaft, a braking means and a stopping means. The rotation shaft penetrates the center of the main body. The braking means includes a braking ring and a helical ring. The braking ring includes a plurality of curved plates. The helical ring surrounds outer edges of the curved plates. Each curved plate is put on the outer periphery of the rotation shaft. The stopping means is disposed between the main body and the braking means for restricting the rotation of any of the curved plates. By this arrangement, a better braking and decelerating function can be achieved.
US09438077B2	Electric machine rotor bar and method of making same A method, system, and apparatus including an electric machine having a plurality of rotor bars and a first coupling component configured to electrically couple the plurality of rotor bars together. Each rotor bar of the plurality of rotor bars includes a first metallic material having a first electrical resistivity and a second metallic material cast about the first material, where the second metallic material has a second electrical resistivity greater than the first electrical resistivity. The first metallic material has a first end and a second end opposite the first end and the first coupling component is coupled to the first end of the first metallic material.
US09438075B2	Motor stator and motor A motor stator of the invention is provided with a laminated stator core comprising a plurality of core pieces having teeth and linked by intermediate thin-wall portions. The thin-wall portions are bent to form the stator core into an annular shape with two ends of the stator core joined by welding, and slots are formed between adjoining pairs of the teeth. A welded portion of the stator core is not near a center line in a radial direction of any of the slots.
US09438064B2	System and method for alignment and compatibility detection for a wireless power transfer system Systems, methods, and apparatuses for receiving charging power wirelessly are described herein. One implementation may include an apparatus for receiving charging power wirelessly from a charging transmitter having a transmit coil. The apparatus comprises a receiver communication circuit, coupled to a receive coil and to a load. The receiver communication circuit is configured to receive information associated with at least one characteristic of the charging transmitter. The apparatus further comprises a sensor circuit configured to measure a value of a short circuit current or an open circuit voltage associated with the receive coil. The apparatus further comprises a controller configured to compare the value of the short circuit current or the open circuit voltage to a threshold charging parameter set at a level that provides charging power sufficient to charge the load. The controller may be further configured to initiate receiving the charging power from the charging transmitter when the short circuit current or the open circuit voltage associated with the receive coil is greater than or equal to the threshold charging parameter.
US09438059B2	Battery control apparatus and battery control method It is intended to prevent degradation of battery cells (cells). A battery control apparatus obtains a cell voltage value of each of the cells (201) (S1), calculates a cell SOC at each of the cells based on the measured cell voltage value (S2), calculates an integrated current value (Ah) by integrating current values of a battery pack (2) configured with a plurality of the cells (201), calculates a cell capacity value of each of the cells (201) based on the integrated current value and the cell SOC (S3), calculates a dischargeable cell capacity value from the cell capacity value and the cell SOC (S4), and controls charging/discharging of the battery pack (2) based on the dischargeable cell capacity value (S5).
US09438056B2	Battery pack, battery apparatus including the same, and cell balancing method thereof A battery pack includes: a cell module including a plurality of battery cells; an antenna connected to each of the battery cells; and a waveguide installed at one side of the cell module and having the antenna housed therein.
US09438055B2	Method for charging a power device of a portable device using a current-adaptive process In the charging process of a power device of a portable device, a control unit or firmware of the power device dynamically acquires the status of the charging current and the charging voltage, and by incrementing the charging current, the power device correctly obtains maximum charging current affordable by a charger without overly drawing the current from the charger that causes overly low charging voltage. Such current-adaptive charging process optimizes the charging process.
US09438053B2	Scalable harvesting system and method A scalable energy harvesting system comprising at least one charging control device, at least one energy storage device responsive to the charging control device, at least one energy harvesting device operatively coupled to the charging control device, and a plurality of bus based power connectors operatively coupled to the charging control device.
US09438052B1	Mobile device holder-charger Mobile device holder-charger with a rotating three prong plug that allows for use in either horizontal or vertical outlets. There is a bracket to secure the phone. The device can be used on a support surface with a grounded extension cord. There is non-skid material disposed on the bottom. The device is a one piece unit for easy portability.
US09438051B2	USB power outlet/charger direct replacement for automotive cigar lighter/power outlet A power outlet/charger for a portable electronic device, the power outlet/charger comprising an electrically insulating housing having a proximal end having an opening and a distal end having a first electrical connector; an electronic converter circuit fixedly housed in the housing for receiving a first voltage from a vehicle electrical power source through the first connector and for converting the first voltage to a second voltage compatible with the USB (Universal Serial Bus) standard; and a USB connector disposed through the proximal end opening and connected to receive the second voltage; the housing being sized to directly replace a standard vehicle electrical cigar lighter socket/power outlet and fit into an opening in a vehicle panel for the standard vehicle electrical cigar lighter socket/power outlet, the first electrical connector being connectable to an electrical wiring harness of the vehicle having a connector that releasably connects with the first connector. Preferably, the first connector comprises a US-CAR connector.
US09438049B2	Control circuit and method for a portable charging carrying case for providing uninterruptible power to charge electronic cigarette batteries A control circuit and method for use with an electronic cigarette box, the control circuit includes a charge management module, an inner battery, a control module, a voltage booster, a batter voltage detective module, a load detective module and an indicative module. According to received signals form the battery voltage detective module, the load detective module and the charge management module, the control module control the voltage booster adjusting a charge voltage supplied from the inner battery and outputting a voltage to charge a charge load, and the control module further control the indicative module displaying a charge state. The control circuit provides indications of various operation states or breakdown states, various charge interfaces, functions of detecting load and protection for inner battery and circuits.
US09438048B2	Modular battery cell architecture and control method Embodiments of the invention relate to a configuration of a multi-cell battery pack, with at least two cells electrically connected in a first parallel arrangement, which is connected in series to a second parallel arrangement of at least two additional cells. Each cell is locally connected to a sensor to sense and control the current of the cells in parallel or parallel-series combination in the multi-cell battery pack. A control module is in communication with each sensor, and associated instructions electrically remove or disable a cell from the multi-cell battery pack determined to be defective based on measurements from an associated sensor. Accordingly, the configuration measures and monitors a state of health of each cell in the multi-cell battery pack, the measurements including temperature, voltage and current sensing.
US09438046B1	Methods and systems for maximum power point transfer in receivers A MPPT management method in a receiver used for wireless power transmission may include the monitoring of the power extracted from RF waves at a dedicated antenna element in the receiver; detecting MPPT at an intelligent input boost converter in the receiver; comparing the detected MPPT with MPPT tables stored or calculated within a main system micro-controller in the receiver; adjusting the MPPT at the intelligent boost converter to find a suitable maximum peak that may enable an optimal power extraction from RF waves.
US09438044B2	Method using wearable device with unique user ID and telemetry system in communication with one or more social networks A method is provided for using telemetry data, and a wearable device that communicates with a social network. One or more sensors, coupled to the wearable device that has a unique user ID, are used to acquire at least one of a user's activities, behaviors and habit information. The wearable device has ID circuitry and a communication system that reads and transmits the unique ID from an ID storage. The wearable device communicates with a social network. A telemetry system communicates with the one or more sensors. The telemetry system includes a database of user ID's. Telemetry data is analyzed based on at least one of, user's activities, behaviors and habit information. Personalized information is created about the user.
US09438043B2	Airplane cabin environment management A system has a power source connected to power access points and at least one environmental control system. A threshold compare device is effective to compare the proportional load on the environmental control systems to a preset threshold. If the threshold is exceeded, unused power access points are disabled. This prevents such access points from placing additional loads on the environmental control systems. Conversely, when the proportional load on the environmental control systems drops below a preset threshold, power can be restored to the disabled power access points. A master control unit can monitor the load on the environmental control systems and either or both the environmental conditions in environment zones or the power loading of the power access points and determine whether to disable unused power outlets.
US09438042B2	Direct current power delivery system and method A power transmission system includes a first unit for carrying out the steps of receiving high voltage direct current (HVDC) power from an HVDC power line, generating an alternating current (AC) component indicative of a status of the first unit, and adding the AC component to the HVDC power line. Further, the power transmission system includes a second unit for carrying out the steps of generating a direct current (DC) voltage to transfer the HVDC power on the HVDC power line, wherein the HVDC power line is coupled between the first unit and the second unit, detecting a presence or an absence of the added AC component in the HVDC power line, and determining the status of the first unit based on the added AC component.
US09438040B2	Energy supply system and conductor loop enclosure An energy supply system for supplying electrical energy to a building, comprising a grid connector unit for providing a connection to an external power grid, a load connector unit for connecting to a building power grid, a conductor loop for electrically connecting the grid connector unit to the load connector unit, an energy storage device connected to the conductor loop, and a disconnector placed in the conductor loop for, upon activation of the disconnector, disconnecting the electrical connection between the grid connector unit and the load connector unit, whereby the energy storage device is connected to the conductor loop via a discharging line such that electrical energy stored in the energy storage device may be discharged through part of the conductor loop to the load connector unit when the disconnector is activated.
US09438035B2	Power converter for a solar panel A solar array power generation system includes a solar array electrically connected to a control system. The solar array has a plurality of solar modules, each module having at least one DC/DC converter for converting the raw panel output to an optimized high voltage, low current output. In a further embodiment, each DC/DC converter requires a signal to enable power output of the solar modules.
US09438032B2	Semiconductor device The semiconductor device includes a power chip including a switching element that switches a supply of power from a power supply to a load between an on-state and an off-state, a control chip in which is incorporated a control circuit that controls the switching element of the power chip, and a reverse connection protection circuit, provided in the control chip, that controls the switching element of the power chip into an on-state when the power supply is reverse-connected, wherein the reverse connection protection circuit has protective resistors, interposed between the control circuit and the positive electrode side of the power supply, and a control voltage formation circuit into which is input an intermediate voltage of the protective resistors and which forms a control voltage that controls the switching element of the power chip into an on-state when the power supply is reverse-connected.
US09438031B2	Electrostatic discharge protection circuit arrangement, electronic circuit and ESD protection method An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.
US09438030B2	Trigger circuit and method for improved transient immunity A trigger circuit detects a transient voltage increase on an integrated circuit. The trigger circuit controls a conductivity state of a clamping device to limit the transient voltage increase. The trigger circuit comprises a common capacitive element having a capacitive value, wherein a first time value and a second time value are dependent upon the capacitive value of the common capacitive element, the first time value applicable to an unpowered state of the integrated circuit and the second time value applicable to a powered state of the integrated circuit. The first time value and the second time value control a trigger circuit parameter which may include a detection range within which a rate of transient voltage increase causes the trigger circuit to become active or an “on” time upon which an active duration of control of the conductivity state of the clamping device depends.
US09438027B2	Systems and methods for power interruption A power interruption circuit for use in a power distribution module is provided. The power interruption circuit is configured to provide power to a load and includes a shunt resistor, a plurality of switches, and microprocessor. The microprocessor is configured to determine a digitized value of a current flowing through the shunt resistor, determine a digitized value of an output voltage of the power interruption circuit, calculate, from the digitized current value and the digitized output voltage value, a power provided by the power interruption circuit to the load, compare the calculated power to a threshold power level, and control the plurality of switches based on the comparison.
US09438026B2	Circuit breaker panel with wireless communications capability In at least some embodiments, a system includes a plurality of circuit breakers and trip control logic external to and coupled to the circuit breakers. The trip control logic enables a plurality of different tripping options to be selected for each of the circuit breakers.
US09438023B2	Power entry unit electrical power distribution system An electrical power system including a first power entry unit, at least one receptacle and a second power entry unit. The at least one receptacle is electrically connected to the first power entry unit. The second power entry unit is electrically connectable to the at least one receptacle. The first power entry unit and/or the second power entry unit include at least one detection device. Either the first power entry unit or the second power entry unit being a selected power entry unit and the remaining one being an other power entry unit. The detection device being configured to detect an attempted electrical power connection of both the selected power entry unit and the other power entry unit to the at least one receptacle.
US09438022B2	Modular device for protecting cables and conduits This specification discloses a modular device for protecting cables and conduits includes cable and conduit protector sections. Each cable and conduit protector section includes a channel, a first ramp, a second ramp and a lid. The channel further includes a bottom, a first side, a second side and plurality of cross members including a first end cross member and a second end cross member, the first ramp is connected to the channel first side and the second ramp is connected to the channel second side. The lid preferably has an arched shape running the length of the channel and is connected to the channel second side.
US09438018B2	Junction box A junction box includes a box body, an upper cover, and a side cover. The box body has a side wall portion, an electric distribution portion, and a drain hole which is located at the inside of the side wall portion. The upper cover has a top panel and a down wall portion which are downwardly provided from the peripheral end of the top panel. The side cover has a terminal connected to the electric distribution portion and a case portion which covers the terminal. A drain groove is provided on an upper face of the case portion along the side wall portion. A downward slope is formed towards the drain hole on a bottom face of the drain groove.
US09438015B2	Triangle flap arc vent An arc blast vent for an electrical equipment enclosure has a plate forming a part of the enclosure with triangular cutouts arranged within a regular polygonal area of the plate and having a frame of the plate material in between them. Substantially identical triangle shaped flaps, each having hold downs along and adjacent to a first leg of the triangle for attachment to the plate, and in from the first leg have a line of perforations through the triangle forming a weakened area for a deformable hinge. Each of the triangle shaped metal flaps have the second and third legs with their edges resting without tenacious engagement on the frame of the plate material.
US09438013B2	Drive assembly for an electrical switching apparatus racking assembly A drive assembly for an electrical switching apparatus racking assembly is provided. The drive assembly includes a positioning assembly, a motor assembly, and a control assembly. The positioning assembly is structured to impart movement to said carriage assembly and to move said carriage assembly from said first position to said second position. The motor assembly is structured to impart movement to said positioning assembly. The control assembly is structured to control said motor assembly. The control assembly is in electronic communication with the motor assembly. The motor assembly is operatively coupled to the positioning assembly.
US09438010B1	Vertical cavity surface emmiting laser A VCSEL according to the invention, configured to emit a light having about 850 nm wavelength, comprises an active region which comprises one or more InxGa1-xAs quantum wells; two or more GaAs1-yPy barriers bonding to the one or more quantum wells; and x ranges from 0.05 to 0.1, and y ranges from 0.2 to 0.29. The VCSEL has increased optical confinement and high transmission speed, good reliability characteristics, high-temperature performance, and long life time.
US09438008B1	Temperature insensitive external cavity lasers on silicon A technique related to a semiconductor chip is provided. An optical gain chip is attached to a semiconductor substrate. An integrated photonic circuit is on the semiconductor substrate, and the optical gain chip is optically coupled to the integrated photonic circuit thereby forming a laser cavity. The integrated photonic circuit includes an active intra-cavity thermo-optic optical phase tuner element, an intra-cavity optical band-pass filter, and an output coupler band-reflect optical grating filter with passive phase compensation. The active intra-cavity thermo-optic optical phase tuner element, the intra-cavity optical band-pass filter, and the output coupler band-reflect optical grating filter with passive phase compensation are optically coupled together.
US09438007B2	Optical modulator An optical modulator including an information-containing radio frequency signal input; a semiconductor device having an optical input optically for receiving the coherent light beam, and a electrode connected to said radio frequency signal input and having a modulated bias potential so that current is generated in the second semiconductor device and extracted therefrom, while the coherent light beam is optically modulated by the signal changing the carrier density in the semiconductor device.
US09438006B2	Compact Raman generators According to an embodiment of the disclosure, a Raman generator includes a Raman medium and one or more optical elements. The Raman medium is configured to receive a pump pulse at a first wavelength and shift at least a portion of the pump pulse energy or power into a Stokes-shifted pulse at a second wavelength. The one or more optical elements are configured to pass the pump pulse and the Stokes-shifted pulse multiple times through the Raman medium. Each pass of the pulses through the Raman medium follows a path. Each path is parallel or anti-parallel to the other paths.
US09438004B2	Optical pumping and powering in spatially multiplexed transmission links A spatially multiplexed optical link having a plurality of transmission paths, wherein at least one transmission path is configured to carry an optical-pump signal while one or more other transmission paths carry data-bearing signals. Disposed within the optical link are an optical signal-distribution module and an amplifier module. The optical signal-distribution module is configured to couple portions of the optical-pump signal into the data-bearing transmission paths. The amplifier module is configured to amplify the data-bearing signals using these portions of the optical-pump signal as a power source in a suitable all-optical amplification scheme. The optical-pump signal can optionally be tapped and applied to a photovoltaic element configured to directly power a device, e.g., an optical performance monitor, or to charge the battery of that device to enable its autonomous operation if external electrical power is not available where the device is deployed.
US09438002B2	Laser system Provided is a laser system. The laser system includes: a laser device providing a laser pulse; a pulse compressor decreasing a pulse width of the laser pulse; a pulse stretcher disposed between the compressor and the laser device and dispersing the laser pulse; and a filament portion disposed between the pulse stretcher and the pulse compressor, wherein the filament portion transmits the laser pulse to expand a spectrum of the laser pulse by using self focusing and a filament phenomenon of the laser pulse.
US09437997B2	Process for attaching devices to a circuit board Systems, methods and apparatuses for attaching devices to ends of a circuit board. An exemplary method includes removing or creating at least a portion of a sacrificial part of a circuit board based on a predefined pattern, inserting a holder device into a remaining portion of the sacrificial part of the circuit board, placing a device at a predefined location on the circuit board, wherein the device is at least partially supported by a portion of the holder device, attaching the device to the circuit board and removing the holder device and the sacrificial part of the circuit board.
US09437994B2	Electronic apparatus, category determination method for transmission cable and transmission cable An electronic apparatus includes a receptacle having a plurality of pins for connecting a plug of a transmission cable and a transmission cable determination section adapted to apply a predetermined voltage to a predetermined one of the pins of the receptacle to determine a category of the transmission cable.
US09437990B2	Managed electrical connectivity systems A receptacle block defines at least one socket at which a plug connector may be received. First contact members extend into each socket to receive a primary signal from a plug connector. Second contact members extend into one or more of the sockets to read physical layer information from any plug connector inserted into the socket. A sensing contact is positioned to electrically connect to one of the second contact members when a plug connector is inserted into the respective socket. At least a portion of the sensing contact is flexible to follow the movement of the one second contact member. In certain implementations, the second contact members have resilient sections that are identical to each other.
US09437985B2	Connector with integral fuse holder A connector with an integral fuse holder is described herein. The connector can include a portion having a fuse receiver disposed within a cavity and coupled to an electrical connection feature. The connector can include an end coupled to the portion, where the end includes a wall that forms a cavity. The connector can further include a fuse assembly having a contact member, a fuse, a fuse holder, and a conductor receiver. The contact member can couple to the electrical connection feature. The fuse holder can include a first end that couples to a top end of the fuse and the contact member, and a second end that couples to a bottom end of the fuse. The conductor receiver can couple to the second end of the fuse holder and to the bottom end of the fuse. A receiving feature of the conductor receiver can couple to a conductor.
US09437980B2	Connector A connector includes a plurality of signal contacts and a plurality of non-signal contacts arranged on at least one contact array plane, a ground plate disposed on a ground plane parallel to the contact array plane so as to face the plurality of signal contacts and the plurality of non-signal contacts, and an insulator which holds the plurality of signal contacts, the plurality of non-signal contacts and the ground plate, at least one of the non-signal contacts being disposed between each of the signal contacts and other of the signal contacts, the ground plate having at least one opening at a location facing the at least one of the non-signal contacts disposed between each of the signal contacts and other of the signal contacts, none of the signal contacts being disposed on the ground plane.
US09437978B2	Modular electrical connector A system for providing electrical energy and related components is provided. More specifically, a universal module that is adapted to fit within a junction box commonly found in building construction is provided. The wire cable associated with a dwelling, for example, is interconnected to the module, which provides a plurality of locations for receipt of corresponding electrical connectors of an outlet or switch. The modules quickly and safely receive an electrical component, which reduces time and associated costs related to electrical system installation, repair, or modification.
US09437977B1	Grounding and retention member A grounding and retention member which includes a plate having openings positioned therein. First contact and retention projections extend from proximate edges of the plate. The first contact and retention projections cooperate with a shell of the connector to provide an electrical connection between the plate and the shell of the connector. Second contact and retention projections extend from proximate edges of at least one of the openings. The second contact and retention projections cooperate to retain contacts in contact receiving passageways of a connector and to provide an electrical connection between the contacts and the plate.
US09437973B2	Connector for preventing release of an object received therein in an ejecting direction A connector is receivable an object along a receiving direction. The connector ejects the object along an ejecting direction opposite to the receiving direction. The object has a mating terminal, a pressed portion and a regulated portion. The connector comprises a holding member, a terminal and an operation member. The operation member is supported by the holding member so as to be movable between a first position and a second position. The operation member includes a press portion and a regulating portion. When the operation member is operated to be moved from the first position toward the second position, the press portion presses the pressed portion in the ejecting direction to move the object in the ejecting direction. At the latest until the operation member reaches the second position, the regulating portion enters into an ejecting path to regulate a movement of the regulated portion in the ejecting direction so that the regulating portion prevents the object from being released off the connector in the ejecting direction. The ejecting path is a movement path on which the regulated portion passes when moved in the ejecting direction.
US09437970B2	Multi-pole plug connection unit for three-phase alternating current systems A multi-pole plug connection unit for three-phase alternating current systems having two plug connection parts which complement one another for the purpose of kink-free plug connection and having a locking sleeve which axially secures the plug connection parts in relation to one another in the plug-connected state is known. Each plug connection part is constructed as a monolithic insulating body in which a plurality of electrical plug contacts are axially latched, and an outside diameter of the plug connection parts and the locking sleeve is less than 23 mm, and the plug connection unit is designed to transmit voltage and current intensity ranges of up to 630 volts/16 amperes. The multi-pole plug connection unit is used for energy and signal transmission in machine tools.
US09437968B2	Magnet connector The receptacle connector comprises a receptacle housing, a receptacle connecting surface, a contact, a first receptacle magnetic pole portion, a second receptacle magnetic pole portion and a third receptacle magnetic pole portion. The plug connector comprises a plug housing, a plug connecting surface, a contact, a first plug magnetic pole portion, a second plug magnetic pole portion and a third plug magnetic pole portion. The first receptacle magnetic pole portion and the first plug magnetic pole portion have opposite magnetic polarities. The second receptacle magnetic pole portion and the third receptacle magnetic pole portion have opposite magnetic polarities. The second plug magnetic pole portion and the third plug magnetic pole portion have opposite magnetic polarities. The second receptacle magnetic pole portion and the second plug magnetic pole portion have opposite magnetic polarities.
US09437965B2	Connector having coupling mechanism A connector includes a shell having a mating end configured to be mated with a mating connector and that holds at least one contact. A coupling mechanism is rotatable about the shell. The coupling mechanism includes an inner coupling nut and an outer coupling nut separate from the inner coupling nut. The inner coupling nut has threads configured to be threadably coupled to a mating connector. The inner coupling nut has a track defined by track walls formed into an outer surface of the inner coupling nut. The outer coupling nut has a cavity receiving the inner coupling nut. The outer coupling nut has a post extending into the cavity and being received in the track. The post engages the track walls and is released from the track wall into the track when the connector is fully mated to the mating connector.
US09437964B2	RF coaxial cable connector with retention member An electrical connector assembly is adapted for electrical connecting and retained on a wireless module with a receptacle RF connector mounted on an end of the wireless module is provided. The assembly includes a coaxial cable connector including a connector end and a coaxial cable extending from the connector end and a retention member including a main base and a retention cavity in front of the main base, the main base defining a corresponding cable receiving groove through a front end and a rear end of the main base. The retention cavity further defines a projecting portion elastically pressing against a surface of the end of the wireless module when the end of the wireless module, the receptacle RF connector and the connector end of the coaxial cable connector are receiving in the retention cavity and the coaxial cable go through the cable receiving groove.
US09437962B2	Waterproof adapter and connector for accessory device A waterproof adapter can provide a liquid-tight seal between a waterproof housing for a mobile electronic device and an accessory connector extending from an accessory device, such as a jack plug extending from a pair of headphones. The waterproof adapter can be an integral part of the accessory connector or can be installed on the accessory connector using, for example, a threaded or bayonet-style connection. In one example, the waterproof adapter can include an exterior gasket channel circumscribing an exterior surface of its body, an exterior gasket disposed at least partially within the exterior gasket channel, thereby permitting the waterproof adapter to provide a liquid-tight seal between a connector aperture in the waterproof housing and the accessory connector. When the accessory device is disconnected from the mobile electronic device, a port-sealing bung can be inserted into the connector aperture of the waterproof housing and can provide a liquid-tight seal therewith.
US09437960B2	Dustproof cover for charging port of electronic device and charging base corresponding to dustproof cover A dustproof cover of the disclosure is inserted into a charging port of an electronic device to prevent dust entering into the charging port. The charging port includes a pair of charging terminals. The dustproof cover includes a plug, a cover body fixed with one end of the plug, a plurality of metal connecting posts, and a conductive part located between the plug and the cover body. A first end of each metal connecting post extends into the plug, and a second end of each metal connecting post is electrically connected to the conductive part. In use, the plug is inserted into the charging port, the plurality of metal connecting posts contact the charging terminals, the conductive part is electrically connected to the charging terminals, and the cover body covers the charging port. The present disclosure also discloses a charging base corresponding to the dustproof cover.
US09437959B2	Slim line while in use cover and methods for making and using the same In one embodiment, a while in use cover assembly 10, comprising: a lid 14 hingedly attached to a base 12 having a back wall 64; and socket assembly 52,152 comprising a receiver socket 20 attached to the lid 14 and/or the base 12, and located between the lid 14 and the base 12; wherein the receiver socket 20 comprises a face 122 with blade apertures configured to receive a power cord plug 86; wherein the socket face 122 changes orientation with respect to the back wall 64 when the lid is opened; and wherein the while in use cover assembly 10 is configured to be attached to an outlet socket 50.
US09437958B2	Terminal connecting structure and terminal connecting method A terminal connecting structure includes: an electric wire in which a conductor is covered by an insulative covering; a conductor connecting terminal to which a conductor exposed portion in which the covering of an end portion of the electric wire is removed and the conductor is exposed is electrically connected; a water sealant for molding the conductor connecting terminal; and a fixing terminal which includes a terminal fixing portion that is to be fixed and electrically connected to a mount part, and which is electrically connected to a part of the conductor connecting terminal in a state where the water sealant is removed from the part of the conductor connecting terminal.
US09437954B2	Series connector A configurable and modular probe device for electrical connections. The probe device has multiple blocks capable of inter-fitting into various layouts. Each block has four sidewalls. Two adjacent sidewalls have a protrusion and the respective opposite sidewalls have a cavity corresponding to the protrusion. The protrusion of one block can removably mate with the cavity of a neighboring block. Each block further has a central cavity extending from a top surface to a bottom surface of the block. A probe snugly fits into the central cavity.
US09437951B2	Apparatuses and methods for a plug connector A plug connector has a housing and a plurality of metallic plug connections in the housing together with a plurality of contact feet which project from the bottom face of the housing in order to make electrical contact and be mechanically fixed to a support of a heating apparatus which is electrically connected to the plug connector. A contact foot has a U-shaped foot end with two limbs and with a cutout in-between, an upper limb merging with the contact foot, and a lower limb being provided on that side which faces away from the housing.
US09437947B2	Electrical connector having hold down member An electrical connector include a movable hold down member that is configured to receive a fastener so as to secure the electrical connector to an underlying substrate to which the electrical connector is mounted.
US09437943B1	Stacked symmetric printed circuit boards A printed circuit board (PCB) is provided. The PCB includes a connector extending from a surface of the PCB and a bypass feature extending through the PCB. The PCB is constructed so that a first copy of the PCB is configured to be assembled to a second copy of the PCB with the second copy rotated and/or flipped relative to the first copy. An electrical connection to the first copy is accessible via the connector of the first copy, and an electrical connection to the second copy is accessible via the connector of the second copy through the bypass feature of the first copy.
US09437941B1	Splitter type terminal block connector A splitter type terminal block connector having front metal contact pieces while each of them has two front wire connection metal blocks each having a front rectangular frame, a front resilient metal strip curled upward from the bottom side of one end of the front rectangular frame to abut against an inner top side of the front rectangular frame, a long pin and a short pin provided at another end of the front rectangular frame, and a front hole; also having a rear metal contact piece each having two rear wire connection metal blocks while each of them has a rear rectangular frame, a rear resilient metal strip curled upward from the bottom side of one end of the rear rectangular frame to abut against an inner top side of the rear rectangular frame, two rear pins provided at another end of the rear rectangular frame, and a rear hole.
US09437932B1	Two-arm delta mode spiral antenna A two-arm delta mode spiral antenna includes a dielectric substrate having an upper side, a lower side, and an outward edge. A flat top cone with cylinder sidewall is attached to the lower side of the dielectric substrate, forming a scalable feed cavity. Two spiraling conductive radiator arms are mounted on the dielectric substrate. A magic-T is electrically connected to the two spiraling conductive radiator arms.
US09437930B2	Circular polarized antenna structure A circular polarized antenna structure is provided, including: an antenna having a main body, a protruding portion, and a stopping portion formed between the main body and the protruding portion; a base; a radiation conductor disposed on an upper surface of the base and having at least a first through hole formed above the via hole; a ground conductor disposed on a lower surface of the base and has at least a second through hole formed below the via hole; solder partially covering an end of the stopping portion opposing the main body and the first through hole; and colloid partially formed on the solder, the radiation conductor, and the upper surface of the base. The antenna penetrates the base, and the stopping portion abuts against the lower surface of the base, such that the antenna can be prevented from dropping due to the impact of an external force.
US09437922B2	Method for manufacturing fluidic structures A method of manufacturing a fluidic structure is disclosed. A cavity that defines a shape of an element of the fluidic structure within a material is formed. The cavity is filled with liquid metal. The cavity is sealed. The fluidic structure behaves as an antenna. A fluidic antenna includes a material that defines a shape of the fluidic antenna by a cavity filled with liquid metal formed within the material, where the material further defines at least one mechanical property of the fluidic antenna.
US09437920B2	Push-button switch A push-button switch includes a wiring board having a first surface on which electronic components are mounted. The push-button switch is used for an immobilizer system and supplies power to a portable device from the first surface side of the wiring board. The push-button switch includes a coil antenna and a conductor pattern. The coil antenna includes a magnetic core and a coil conductor wound around the magnetic core. The coil antenna is attached to a second surface of the wiring board. The conductor pattern is formed in at least one wiring layer so as to surround the coil conductor in plan view. The wiring board has an inner layer including the at least one wiring layer. A direction of current flowing through the coil conductor is the same as a direction of current flowing through the conductor pattern.
US09437917B2	Antenna designs According to one embodiment of the invention, a network device comprises a plurality of antennas comprising a first antenna, wherein the first antenna comprises: a first set of one or more elements that form an Alford loop and that is configured for electrical excitation via a current transmitted over a conductive medium from a signal source and a second set of one or more elements that is configured for electromagnetic induction without contact with the conductive medium from the signal source.
US09437909B2	Dielectric waveguide filter with direct coupling and alternative cross-coupling A waveguide filter comprising a base block of dielectric material defining at least first and second resonators and a bridge block seated on top of the base block and defining at least a third resonator. In one embodiment, the base block comprises first and second base blocks that have been coupled together in an end to end relationship. An external transmission line or an interior RF signal transmission window or an RF signal transmission bridge provides a cross-coupling RF signal transmission path between the first and second resonators. At least first and second interior RF signal transmission windows provide a direct RF signal transmission path between the first and third resonators and the second and third resonators respectively.
US09437908B2	Dielectric waveguide filter with direct coupling and alternative cross-coupling A dielectric waveguide filter comprising a block of dielectric material including a plurality of resonators defined by a plurality of slots defined in the block of dielectric material. The resonators are arranged on the block of dielectric material in one or more rows and columns. First and second RF signal input/output electrodes are defined on the block of dielectric material. A first direct RF signal transmission path for the transmission of an RF signal is defined by the first and second RF signal input/output electrodes and the plurality of resonators. In one embodiment, internal windows define a first direct RF signal transmission means and additional RF signal transmission means define alternate or cross-coupling paths for the transmission of the RF signal from resonators in one column to resonators in another column. In one embodiment, the filter is comprised of two separate blocks of dielectric material which have been coupled together.
US09437905B2	Traction battery thermal plate manifold A traction battery system for a vehicle is provided. The system may include a plurality of battery cells, a thermal plate, and an inlet manifold. The thermal plate may support the battery cells and includes a heat exchange region and two lateral sides defining two planes. The inlet manifold may be positioned downstream of an inlet port and upstream of the heat exchange region. The inlet manifold may define distribution channels throughout the inlet manifold and includes an outlet to the heat exchange region having a cross-sectional area defining a third plane. The two planes and third plane define a region normal to the cross sectional area and the inlet manifold may be positioned such that the inlet port is located outside the region.
US09437901B2	Additive for electrolyte and electrolyte and rechargeable lithium battery An electrolyte additive represented by the following Chemical Formula 1, an electrolyte, and a rechargeable lithium battery are disclosed: In Chemical Formula 1, R1 to R3 and L1 to L3 are the same as defined in the detailed description.
US09437900B2	Electrolyte, method for fabricating electrolyte solution, and lithium ion battery An electrolyte for a lithium ion battery is provided, including a carrier, a lithium salt dissolved in the carrier, and an additive uniformly dispersed in the carrier, wherein the additive is an inorganic clay modified by an organic quaternary phosphonium salt. Also provided is a method for fabricating an electrolyte solution and a lithium ion battery.
US09437898B2	Secondary battery including plurality of electrode assemblies Disclosed is a secondary battery including a plurality of electrode assemblies. The secondary battery includes a first electrode assembly including a first cathode, a first separator and a first anode, and a second electrode assembly including a second cathode, a second separator and a second anode, wherein, when an electrode plate area of the second electrode assembly is smaller than that of the first electrode assembly, a cross-sectional thickness of the second electrode assembly is larger than that of the first electrode assembly.
US09437896B2	Method of preparing lithium secondary battery A method of preparing a lithium secondary battery is disclosed, the method including coating a coating layer-forming composition including an inorganic compound and an organic/inorganic bindable silane compound having a first reactive functional group on a substrate to form a separator including a coating layer; preparing an electrode including an active material and a binder having a second reactive functional group; stacking the electrode to contact the coating layer of the separator, and adding an electrolyte to the electrode and separator to prepare a lithium secondary battery; and heat-treating the lithium secondary battery to react the first reactive functional group with the second reactive functional group and form a chemical bond.
US09437890B2	Purge assembly for a fuel cell system A fuel cell purge apparatus for a fuel cell system has a separator defining a chamber for receiving a recirculated fuel stream including a fluid and impurities. The apparatus has a drain conduit with an outer passage connected to the chamber. The outer passage forms a fluid trap to collect the fluid. The drain conduit also has an inner passage nested within the outer passage through the fluid trap for delivering the impurities to a purge valve. The inner passage has a free end extending into the chamber of the separator.
US09437888B2	Fuel cell system and control method therefor During an intermittent operation of the fuel cell, a demanded FC voltage calculation portion calculates a predetermined voltage that is below a heightened potential avoidance threshold voltage as a demanded FC voltage, and outputs the voltage to a converter. When during the intermittent operation of the fuel cell, a deviation obtained by subtracting a generated power of the fuel cell from a system's allowable power that is allowable in the fuel cell system becomes less than or equal to a value 0, the demanded FC voltage correction portion corrects a command value provided for the converter so that the deviation becomes equal to the value 0.
US09437883B2	Manufacturing method of fuel cell module and manufacturing method of fuel cell A manufacturing method of a fuel cell module includes: forming an outer divided body having a frame shape and formed from an uncrosslinked item of solid rubber having adhesiveness in a seal member arrangement portion of a separator to produce an outer temporary assembly, and forming an inner divided body having a frame shape and formed from an uncrosslinked item of solid rubber in a peripheral edge portion of an electrode member to produce an inner temporary assembly; fitting the inner temporary assembly into a frame of the outer temporary assembly to produce a cell assembly temporary assembly; arranging a cell assembly stack, in which a plurality of the cell assembly temporary assemblies are stacked, in a forming die; and pressurizing and heating the forming die to crosslink the uncrosslinked item
US09437882B2	Holding apparatus for fuel cell gasket A holding apparatus for a fuel cell gasket has a support having a flat surface part which attracts the gasket and serves to stack a frame-shaped gasket on an outer circumference of an electrolyte membrane or a gas diffusion layer constituting a membrane electrode assembly on which a catalyst layer is disposed. The flat surface part has a frame-shaped recess corresponding to a shape of the gasket, and the recess is connected to an air-sucking section, with the gasket attracted by sucking air in the recess.
US09437879B1	Oxidation process for interconnects and end plates Methods and systems for oxidizing an interconnect for a fuel cell stack include introducing at least one interconnect to an oxidizing gas containing water vapor, the oxidizing gas being at least substantially free of nitrogen, and oxidizing the at least one interconnect in the presence of the oxidizing gas at an elevated temperature. The oxidation may be performed at a sub-atmospheric pressure. The oxidation of the interconnect may be a controlled oxidation that is performed prior to incorporating the interconnect into a fuel cell stack.
US09437876B2	Production method of electrode catalyst, electrode catalyst, composition for forming gas diffusion electrode, gas diffusion electrode, membrane-electrode assembly (MEA), and fuel cell stack Provided is a production method of an electrode catalyst that can reduce the content of chlorine species reliably and sufficiently through a simple operation, even when using an electrode catalyst precursor containing a high concentration of chlorine (Cl) species as a raw material of the electrode catalyst. The production method of the electrode catalyst has a core-shell structure including a core part formed on a support and a shell part formed to cover at least a part of a surface of the core part. The production method includes a first step (1) of preparing a first liquid with an electrode catalyst precursor (I) being dispersed in ultrapure water by adding the electrode catalyst precursor (I) to the ultrapure water, the electrode catalyst precursor (I) being produced using a material containing chlorine (Cl) species, and exhibiting a chlorine (Cl) species concentration not lower than a first chlorine (Cl) species concentration when measured by X-ray fluorescence (XRF) spectroscopy; and a second step (2) of preparing a second liquid by dispersing an electrode catalyst precursor (II), the electrode catalyst precursor (II) being obtained by filtrating and washing the electrode catalyst precursor (I) contained in the first liquid with ultrapure water, and then performing washing until an electric conductivity ρ of a filtrate has become a first value or lower.
US09437873B2	Spinel-type lithium manganese-based composite oxide Regarding spinel-type lithium manganese-based composite oxide (LMO) to be used as a positive electrode active substance material for lithium battery, a novel LMO is provided, which is capable of maintaining discharge capacity even if charging and discharging are repeated under high temperatures. An LMO in which the crystallite size is 250 nm to 350 nm, the strain is 0.085 or less and the specific surface area increase rate when placed in water at 25° and pH 7 and ultrasonically dispersed at 40 W ultrasonic intensity for 600 seconds is 10.0% or less, can prevent a decrease in the output that accompanies the repetition of charging and discharging while at a high temperature.
US09437869B2	Positive electrode for nonaqueous electrolyte secondary battery and nonaqueous electrolyte secondary battery using the positive electrode It is an object of the present invention to provide a positive electrode for nonaqueous electrolyte secondary batteries that can suppress decreases in the discharge capacity and discharge voltage even when continuous charging is performed at high temperature and that can also suppress decreases in the discharge voltage and energy density even in the charge and discharge after the continuous charging, and to provide a nonaqueous electrolyte secondary battery that uses the positive electrode. The positive electrode includes a positive electrode active material composed of a mixture containing lithium cobalt oxide 21 having a surface to which an erbium compound 22 is partly adhered and lithium nickel cobalt manganese oxide and a binder. The content of the lithium nickel cobalt manganese oxide is 1% by mass or more and 50% by mass or less relative to the total amount of the positive electrode active material.
US09437867B2	Battery plate grid strip pasting assembly A battery plate grid strip pasting assembly can include an orifice plate, a support structure, and a belt. The orifice plate has an opening through which battery paste material is dispensed out of a hopper. The support structure underlies a battery plate grid strip and supports the battery plate grid strip upstream of the opening. The belt traverses beneath the orifice plate and carries the battery plate grid strip downstream of the opening and downstream of the support structure. The support structure supports the battery plate grid strip above the belt and a gap is provided between a bottom surface of the battery plate grid strip and a top surface of the belt. Battery paste material is dispensed into the gap, through the battery plate grid strip, and overpastes the bottom surface of the battery plate grid strip.
US09437866B2	Process for producing lithium vanadium phosphate-carbon composite A process for producing a lithium vanadium phosphate-carbon composite includes a first step that includes mixing a lithium source, a tetravalent or pentavalent vanadium compound, a phosphorus source, and a conductive carbon material source that produces carbon through pyrolysis, in an aqueous solvent to prepare a raw material mixture, a second step that includes heating the raw material mixture to effect a precipitation reaction to obtain a reaction mixture that includes a precipitate, a third step that includes subjecting the reaction mixture that includes the precipitate to wet grinding using a media mill to obtain a slurry that includes ground particles, a fourth step that includes spray-drying the slurry that includes the ground particles to obtain a reaction precursor, and a fifth step that includes calcining the reaction precursor at 600 to 1300° C. in an inert gas atmosphere or a reducing atmosphere. A lithium vanadium phosphate-carbon composite produced by the process may provide a lithium secondary battery with excellent battery performance (e.g., high discharge capacity) when used as a cathode active material.
US09437865B2	Active material for lithium ion secondary battery, and lithium ion secondary battery To provide an active material having high capacity and excellent cycle characteristics. An active material has a layered crystal structure and is expressed by a compositional formula (1) LiyNiaCobMncMdOx (1), where the element M is at least one kind of element selected from the group consisting of Al, Si, Zr, Ti, Fe, Mg, Nb, Ba, and V; 1.9≦(a+b+c+d+y)≦2.1; 1.05≦y≦1.35; 0
US09437862B2	Container for energy storage device including full penetration welded sealing member and method of producing the same An energy storage device having a container containing an electrolyte includes: a through hole formed in the container, for injecting the electrolyte; a sealing member that covers the through hole; and a full penetration weld portion formed by full penetration welding the sealing member to the container.
US09437860B2	Traction battery assembly having snap-in bus bar module A traction battery includes a cell having a terminal defining a surface with a top and at least one sidewall. The traction battery also includes a busbar having an interior defining a top engaging with the top of the terminal, and at least one side surface engaging with the sidewall. One of the side surface and the sidewall includes a projection and the other of the side surface and the sidewall includes a receptacle for receiving the projection.
US09437857B2	Battery assembly A spacer disposed between first and second unit cells has a corrugated portion. The corrugated portion includes first and second protrusions alternating continuously and repeatedly in a vertical direction. The first protrusions protrude from a center in the thickness direction toward the first unit cell to form clearances that function as cooling passages between the first protrusion and the second unit cell. The second protrusions protrude from the center in the thickness direction toward the second unit cell to form clearances that function as cooling passages between the second protrusions and the first unit cell. The spacer includes a straight portion extending in a direction crossing the cooling passages so as to prevent elongation of the corrugated portion in a direction perpendicular to the cooling passages.
US09437855B2	Lithium accumulator and the method of producing thereof A lithium accumulator includes at least two three-dimensional electrodes separated by a separator and encased together into an accumulator body with an electrolyte that is a non-aqueous solution of a lithium salt in an organic polar solvent. The two electrodes have a minimum thickness of 0.5 mm each. At least one electrode is a homogenous, compressed mixture of an electron conductive component and an active material. The active material is capable of absorbing and extracting lithium in the presence of electrolyte. The porosity of the pressed electrodes is 25 to 90%. The active material has morphology of hollow spheres with a wall thickness of maximum 10 micrometers, or morphology of aggregates or agglomerates of maximum 30 micrometers in size. The separator includes a highly porous electrically insulating ceramic material with open pores and porosity from 30 to 95%.
US09437852B2	Method for manufacturing a battery, battery arrangement and modular system The invention relates to a method for manufacturing a battery (10) in which at least one battery module (12) having a plurality of battery cells (14) is provided. A cooling device (26) is selected depending on whether liquid cooling or cooling by a gaseous medium is intended for the at least one battery module (12). Depending on the selection, at least one first heat sink (26), through which a cooling liquid can flow, or at least one second heat sink, through which a gaseous medium can flow, is arranged on the at least one battery module (12) as the cooling device. The invention further relates to a battery arrangement and a modular system for producing a battery (10).
US09437851B2	Electric storage battery support apparatus An apparatus for supporting a battery comprises a tray including a support surface, a recess having a elevation that is lower than an elevation of the support surface, ribs located in the recess and extending to the elevation of the support surface, thermal insulation supported on the ribs and the upper surface, and a battery contacting the insulation and supported on the ribs and the support surface.
US09437849B2	Battery damage indicator The present disclosure provides systems and methods for indicating battery damage. A battery may comprise an odorant and/or visible indicator material configured to be released in response to battery damage. The battery may be configured to release the odorant and/or visible indicator in response to damage to the battery housing, a cell or cells in the battery, a seal of the battery, or any other specific component of the battery. The odorant and/or visible indicator may be stored in free space in the battery housing, a battery cell, or other battery component. The battery may be configured to emit an audible and/or visible indication of battery damage in addition to releasing the odorant and/or visible indicator.
US09437847B2	Battery pack A battery pack includes a battery group including battery rows consecutively disposed adjacent to each other, with the battery rows including secondary batteries disposed parallel to each other and spaced apart from each other, a frame for surrounding the battery group, and a plurality of first ribs that are each disposed between adjacent battery rows. The first ribs include supporting grooves that are formed in lateral surfaces of the first ribs and accommodate portions of edges of the secondary batteries, and ends of each of the first ribs are coupled to the frame.
US09437845B2	Battery module and battery pack To provide a battery module that may be easily assembled, and is capable of preventing a cell unit from being damaged during assembly, the battery module includes a cell unit provided with at least one unit cell, and first and second cases which enclose and accommodate the cell unit. The first and second cases are respectively provided with a main surface, and a side surface which is bent at one end of the main surface and extends in a direction away from the main surface.
US09437844B2	Display device and method for manufacturing the same A display device includes a substrate, a first electrode on the substrate, a pixel defining layer on the substrate, the pixel defining layer having an opening exposing the first electrode, a metal layer on the pixel defining layer, a light emission layer on the first electrode exposed by the opening, and a second electrode on the light emission layer in the opening. The metal layer contacts the second electrode.
US09437842B2	Light-emitting transistors with improved performance Disclosed are light-emitting transistors having novel structures that can lead to enhanced device brightness, specifically, via incorporation of additional electrically insulating components that can favor charge localization and in turn, carrier recombination and exciton formation.
US09437841B2	OLED display structure and OLED display device Disclosed are an OLED display structure and an OLED display device having the OLED display structure. The OLED display structure comprises: a substrate (10), and an OLED pixel layer (20), an o-light and e-light splitting and converting device (5) and a circular polarizer layer (6) which are formed on the substrate (10) in sequence; the o-light and e-light splitting and converting device (5) is adapted to divide a light beam into o-light and e-light, and to convert the o-light and the e-light into circularly polarized light which has the same polarization state as the circular polarizer layer (6); the circular polarizer layer (6) is adapted to allow passage of the circularly polarized light which has the same polarization state as it. With the display structure, the light transmittance is improved, and the pixel current of the OLED pixel layer (20) is reduced, and thereby energy is saved.
US09437840B2	Organic light emitting display device An organic light emitting display device includes a substrate, a display unit on the substrate, the display unit including a plurality of light-emitting areas in a lattice pattern, and an antireflective film on the display unit, the antireflective film including at least two metal layers and at least two dielectric layers that are alternately stacked, and each of the at least two metal layers including a plurality of islands in a lattice pattern overlapping the light-emitting areas of the display unit.
US09437835B2	Transparent infrared-to-visible up-conversion device Embodiments of the invention are directed to a transparent up-conversion device having two transparent electrodes. In embodiments of the invention, the up-conversion device comprises a stack of layers proceeding from a transparent substrate including an anode, a hole blocking layer, an IR sensitizing layer, a hole transport layer, a light emitting layer, an electron transport layer, a cathode, and an antireflective layer. In an embodiment of the invention, the up-conversion device includes an IR pass visible blocking layer.
US09437831B2	Display device and method for manufacturing the same A first organic resin layer is formed over a first substrate; a first insulating film is formed over the first organic resin layer; a first element layer is formed over the first insulating film; a second organic resin layer is formed over a second substrate; a second insulating film is formed over the second organic resin layer; a second element layer is formed over the second insulating film; the first substrate and the second substrate are bonded; a first separation step in which adhesion between the first organic resin layer and the first substrate is reduced; the first organic resin layer and a first flexible substrate are bonded with a first bonding layer; a second separation step in which adhesion between the second organic resin layer and the second substrate is reduced; and the second organic resin layer and a second flexible substrate are bonded with a second bonding layer.
US09437827B2	Heterocyclic compound and organic light-emitting device including the same A heterocyclic compound represented by Formula 1 below and an organic light-emitting device including the same,
US09437821B2	Method for manufacturing electronic device When a thin film is formed by an application method, damage to a substrate or existing electrodes and functional layers can be reduce. A method for manufacturing an electronic device comprising two or more electrodes, and an organic thin film provided between the two or more electrodes, the method comprising the steps of: forming a coating film by applying a coating liquid that comprises a material having a crosslinking group, and forming the organic thin film by repeating an irradiation of electromagnetic waves to the coating film to cross-link with the crosslinking group.
US09437819B2	Donor substrate and method for forming transfer pattern using the same A donor substrate includes a base layer, a light-to-heat conversion layer disposed on the base layer, a buffer layer disposed on the light-to-heat conversion layer and a transfer layer disposed on the buffer layer. The buffer layer includes a cross-linked polymer, a spacer polymer bonded to the cross-linked polymer, and a perfluoroalkyl alcohol group bonded to the spacer polymer.
US09437818B2	Exposure apparatus, method of controlling the same, and alignment method for exposure An exposure apparatus capable of preventing a reduction in its accuracy due to, for example, the influence of aging or the influence of heat is disclosed. Also disclosed is a method of controlling the same, and an alignment method for exposure. In one aspect, the exposure apparatus includes a main stage for adjusting a position of a substrate, a beam irradiation unit for irradiating a beam onto a mask, and a beam monitoring unit having a position fixed with respect to the main stage, and for recognizing the beam emitted from the beam irradiation unit and passed through one pattern of the mask.
US09437817B2	Insulator material for use in RRAM The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.
US09437816B2	Phase change memory structures and methods A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.
US09437813B2	Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell. A resistance-switching material is then deposited between and above the bottom electrode structures, followed by a top electrode layer. Or, insulation is deposited between and above the bottom electrode structures, followed by planarizing and a wet etch to expose top surfaces of the bottom electrode structures, then deposition of the resistance-switching material and the top electrode layer. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.
US09437806B2	Piezoelectric thin film, method of manufacturing the same, piezoelectric thin film manufacturing apparatus and liquid ejection head A piezoelectric thin film is manufactured by sequentially executing: a step of coating a substrate by applying a coating solution containing an organic solvent and a piezoelectric thin film precursor to form a coating layer; a step of evaporating the organic solvent from the coating layer in a windless environment to obtain a dried coating layer containing the piezoelectric thin film precursor; and a step of heating the dried coating layer to form a piezoelectric thin film from the dried coating layer containing the piezoelectric thin film precursor.
US09437805B2	Piezoelectric thin film element A piezoelectric thin film element that includes a substrate, a lower electrode on the substrate, a piezoelectric film on the lower electrode, and an upper electrode on the piezoelectric film. The piezoelectric film is a potassium sodium niobate film represented, as its main constituent, by the general formula (1−n)(K1-xNax)NbyO3-nM1M2O3 in which M1 is any one of Ca, Sr, and Ba, and M2 is Zr, and x, y, and n respectively are within the ranges of: 0.25≦x≦1.00; 0.85≦y≦1.10; and 0.01≦n≦0.10. Alternatively, M2 is any one of Sn and Hf, and x, y, and n respectively are within the ranges of: 0.25≦x≦1.00; 0.90≦y≦1.05; and 0.01≦n≦0.10.
US09437804B2	Electroactive polymer structures printed with varying compositions of ions An electroactive polymer structure includes a first flexible electrode, a second flexible electrode, and a polymer dielectric layer with ionic liquid on top of the first electrode including at least two regions. Each region of the polymer dielectric layer includes a different ionic liquid concentration. The polymer dielectric layer is in between the first flexible electrode and the second flexible electrode.
US09437803B2	Piezoelectric actuator A piezoelectric actuator, in particular for injectors in internal combustion engines, is provided which includes a piezoelectric module including a ceramic body and two end pieces which clamp the ceramic body axially in place, and an electrical connecting element which is secured on the piezoelectric module and which includes two contact plates leading to the ceramic body. To increase the robustness of the connecting element and to avoid fractures in the contact plates under high vibrational stresses, the contact plates are designed as one-piece metal stampings including at least partially embossed stamped edges.
US09437801B2	Piezoelectric device and method for using same A piezoelectric device, which has bipolar polarization-electric field (Pr-E) hysteresis characteristics of a piezoelectric material asymmetrically biased, when a first and second coercive electric fields respectively having smaller and larger absolute values are defined as Ec1 and Ec2 and a bias ratio of the coercive electric field is defined as [(Ec2+Ec1)/(Ec2−Ec1)]×100[%], includes a piezoelectric element unit including a piezoelectric body film whose bias ratio is 20% or more, the piezoelectric element unit operating with an electric field intensity smaller than that of the first coercive electric field. The piezoelectric device includes a refresh voltage applying circuit configured to apply a voltage to maintain operation performance of the relevant device, the voltage having an electric field intensity larger than the electric field intensity for operating the device and being equal to or less than three times \|Ec1\|, such that a polarized state of the piezoelectric body film is restored.
US09437795B2	Thermoelectric device and method of manufacturing the same Provided are a thermoelectric device and a method of manufacturing the same. The method may include forming nanowires on a substrate, forming a barrier layer on the nanowires, forming a bulk layer on the barrier layer, forming a lower electrode under the substrate, and forming an upper electrode on the bulk layer.
US09437794B2	Method of fabricating a flip chip light emitting diode (FCLED) die having N-conductor layer A method for fabricating a flip chip light emitting diode (FCLED) die includes forming an epitaxial stack on a carrier substrate having an n-type confinement layer, a multiple quantum well (MQW) layer, and a p-type confinement layer, forming a mirror layer on the p-type confinement layer, forming an n-trench in the n-type confinement layer, forming an n-conductor layer in the n-trench on the n-type confinement layer, forming a p-metal layer on the p-type confinement layer, forming a first electrical isolator layer on the n-conductor layer and a second electrical isolator layer on the p-metal layer, forming a p-pad on the first electrical isolator layer, and forming an n-pad the second electrical isolator layer.
US09437793B2	Package support, fabrication method and LED package A package support including: metal frames connected together; one or more dielectric materials disposed in an inner gap of the metal frames; wherein: the package support has a frame region and a function region; wherein the function region has complete upper and lower surfaces configured to prevent leakage if at least one of the entire upper or lower surfaces is covered with an encapsulant material. A fabrication method allows for manufacturing the package support with a high cell density, relatively low price, high reflectivity, good heat dissipation, and high reliability. The LED package using the package support has a smaller size and improved dissipation properties.
US09437788B2	Light emitting diode (LED) component comprising a phosphor with improved excitation properties A light emitting diode (LED) component comprises an LED having a dominant wavelength in a range of from about 425 nm to less than 460 nm and a phosphor in optical communication with the LED. The phosphor includes a host lattice comprising yttrium aluminum garnet (YAG), and may include an activator comprising Ce and a substitutional dopant comprising Ga incorporated in the host lattice. An emission spectrum of the phosphor has a maximum intensity in a wavelength range of from about 540 nm to about 570 nm, and an excitation spectrum of the phosphor comprises an intensity at 440 nm equivalent to at least about 85% of a maximum intensity of the excitation spectrum.
US09437785B2	Light emitting diodes including integrated backside reflector and die attach Light emitting diodes include a silicon carbide substrate having first and second opposing faces, a diode region on the first face, anode and cathode contacts on the diode region opposite the silicon carbide substrate and a hybrid reflector on the silicon carbide substrate opposite the diode region. The hybrid reflector includes a transparent layer having an index of refraction that is lower than the silicon carbide substrate, and a reflective layer on the transparent layer, opposite the substrate. A die attach layer may be provided on the hybrid reflector, opposite the silicon carbide substrate. A barrier layer may be provided between the hybrid reflector and the die attach layer.
US09437784B2	Light emitting device Disclosed is a light emitting device including a light emitting structure comprising a first semiconductor layer, an active layer and a second semiconductor layer, a phosphor plate disposed on the second semiconductor layer, a first electrode portion disposed on the phosphor plate, and a plurality of bonding portions disposed between the light emitting structure and the phosphor plate, the bonding portions bonding the phosphor plate to the light emitting structure, wherein each bonding portion includes at least one first bonding portion electrically connected to the first electrode portion.
US09437781B2	Light emitting device Disclosed is a light emitting device which includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first current blocking layer, a second current blocking layer arranged on the light emitting structure to be separated from each other, a light-transmitting conductive layer arranged on the first current blocking layer, the second current blocking layer and the light emitting structure, first electrode and second electrode electrically coupled to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively, a through hole formed through the light-transmitting conductive layer, the second conductive semiconductor layer and the active layer to a portion of the first conductive semiconductor layer, and a through electrode arranged inside the through hole. Here, the through electrode does not overlap the first current blocking layer in a vertical direction.
US09437772B2	Method of manufacture of advanced heterojunction transistor and transistor laser Methods of manufacture of advanced heterojunction transistors and transistor lasers, and their related structures, are described herein. Other embodiments are also disclosed herein.
US09437770B2	Radiation detector and medical diagnostic system A radiation detector is disclosed, including a plurality of detector elements arranged adjacent to one another in a planar manner. In an embodiment, for the purpose of radiation detection, a semiconductor layer with an upper side and a lower side is present, the semiconductor layer on one of the sides including an electrode embodied so as to extend across a number of detector elements and electrodes subdivided into individual electrodes being arranged on the other side of the semiconductor layer so that by applying voltage between the electrodes of the two sides, an electrical field is generatable and each individual electrode is assigned an effective volume so as to collect charge in the semiconductor layer. In an embodiment, the individual electrodes are alternately connected to at least two different voltage potentials. Furthermore, a medical diagnostic system is disclosed, including at least one such radiation detector.
US09437768B2	Photoelectric conversion device A photoelectric conversion device with low resistance loss and high conversion efficiency is provided. The photoelectric conversion device includes a first silicon semiconductor layer and a second silicon semiconductor layer between a pair of electrodes. The first silicon semiconductor layer is provided over one surface of a crystalline silicon substrate having one conductivity type and has a conductivity type opposite to that of the crystalline silicon substrate, and the second silicon semiconductor layer is provided on the other surface of the crystalline silicon substrate and has a conductivity type which is the same as that of the crystalline silicon substrate. Further, the first silicon semiconductor layer and the second silicon semiconductor layer each have a carrier concentration varying in the film thickness direction.
US09437766B2	Photovoltaic thermal hybrid systems and method of operation thereof A method is disclosed for operating a photovoltaic thermal hybrid system having a hybrid solar receiver with a photovoltaic module, operatively coupled to the system to deliver an electrical output power for a power user, a thermal collector distinct from the photovoltaic module, wherein the photovoltaic module and/or the thermal collector are movably mounted in the system, a collector thermal storage thermally connected to the thermal collector to store heat collected at the thermal collector, and a positioning mechanism adapted to move the photovoltaic module and/or the thermal collector. The method includes instructing the positioning mechanism to move the photovoltaic module and/or the thermal collector to change a ratio of an intensity of radiation received at the photovoltaic module to an intensity of radiation received at the thermal collector.
US09437765B2	Solar cell module and solar cell module manufacturing method A solar cell module includes: a plurality of solar cell elements that have electrodes on surfaces thereof; a tab wire that connects the electrodes of the plurality of solar cell elements; and a resin portion that is provided in a discontinuous manner on the surfaces and that bonds the tab wire and the surfaces to each other. The tab wire extends in a predetermined direction along the electrodes, and the resin portion is discontinuously arranged along the tab wire. A bus bar electrode extends in a non-linear shape. The bus bar electrode is provided such that the bus bar electrode passes a plurality of vertices that are each positioned spaced apart in a short-side direction of the bus bar electrode from a center position of the bus bar electrode in the short-side direction. The resin portion is provided avoiding the vicinity of the vertices.
US09437764B2	Photoelectric conversion device and method for manufacturing photoelectric conversion device An exemplary embodiment is a photoelectric conversion device having a photoelectric conversion portion, and a transfer portion. The transfer portion transfers charges of the photoelectric conversion portion. The photoelectric conversion portion includes first and second semiconductor regions of a first conductivity type. Charges generated by photoelectric conversion are accumulated in the first and second semiconductor regions. According to the structure of the first and second semiconductor regions of the exemplary embodiment or the method for manufacturing them, the transfer efficiency of charges can be improved while improving the sensitivity of the photoelectric conversion portion.
US09437758B2	Photoelectric conversion device A photoelectric conversion device in photoelectric conversion in a light-absorption region in a crystalline silicon substrate is efficiently performed is provided. In the photoelectric conversion device, a light-transmitting conductive film which has a high effect of passivation of defects on a silicon surface and improves the reflectance on a back electrode side is provided between the back electrode and the crystalline silicon substrate, The light-transmitting conductive film includes an organic compound and an inorganic compound. The organic compound includes 4-phenyl-4′-(9-phenylfluoren-9-yl)triphenylamine. The inorganic compound includes an oxide of a metal belonging to any of Groups 4 to 8 of the periodic table.
US09437754B2	Method of manufacturing electrical device A method of manufacturing an electrical device comprising steps of: preparing a substrate; applying a conductive paste onto the substrate, wherein the conductive paste comprises (i) an inorganic powder comprising at least a conductive powder, (ii) an organic polymer, (iii) a solvent and (iv) a gellant selected from the group consisting of a polyalkyleneoxy terminated polyamide (PAOPA), an ester terminated polyamide (ETPA), polyether polyamine (PEPA) and a mixture thereof; and heating the applied conductive paste to form an electrode.
US09437748B2	Method for manufacturing semiconductor device To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
US09437745B2	Semiconductor device and method for manufacturing same The present invention provides a semiconductor device which is provided with an oxide semiconductor TFT that can be reduced in the parasitic capacitance by suppressing process damage to a channel, while reducing the channel length (L). A semiconductor device of the present invention is provided with: a gate electrode (3) that is provided on a substrate (1); a first insulating layer (5) that is formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) that is formed on the first insulating layer (5); a source electrode (11) and a drain electrode (13) that are electrically connected to the oxide semiconductor layer (7); and a protective layer (9) that covers the upper surface of the oxide semiconductor layer (7). The source electrode (11) and/or the drain electrode (13) is arranged on a portion of the side faces of the oxide semiconductor layer (7) and a portion of the side faces of the protective layer (9), but does not cover the upper face of the protective layer (9).
US09437744B2	Semiconductor device and manufacturing method thereof When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity.
US09437738B2	Field effect transistor with heterostructure channel In some embodiments, an FET structure comprises a heterostructure, and a gate structure. The heterostructure comprises a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least portions of source and drain regions, respectively. When the channel region is p type, the barrier section has a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section has a positive conduction band offset with respect to each of the first section and the second section. A gate structure is configured over the channel region.
US09437731B2	Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same A semiconductor device includes a semiconductor substrate having a first conductivity type, a plurality of pillars extending to a direction perpendicular to a surface of the semiconductor substrate, a stress providing layer formed in the semiconductor substrate between pillars and forming a junction with the semiconductor substrate below each pillar to cause lattice deformation in the pillar, a source region having a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate below the pillar, a drain region having the second conductivity type formed in an upper portion of the pillar, a gate insulating layer formed on a lateral surface of the pillar and a surface of the stress providing layer, and a gate electrode formed to surround the lateral surface of the pillar.
US09437730B2	Semiconductor device using three dimensional channel According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.
US09437729B2	High-density power MOSFET with planarized metalization A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical polishing process on the active area to produce a substantially planar surface. A metalization deposition process is then performed on the substantially planar surface and the fabrication of the power MOSFET is subsequently completed.
US09437726B2	Field effect transistor In a field effect transistor, a carbon concentration in a buffer layer at the side closer to a high resistance layer is not less than 0.8×1019/cm3 and not more than 1.0×1021/cm3, a carbon concentration in the high resistance layer at the side closer to the buffer layer is not less than 3.7×1018/cm3 and not more than 1.0×1021/cm3, and a carbon concentration in the high resistance layer at the side closer to the channel layer is not less than 1.4×1019/cm3 and not more than 1.0×1021/cm3.
US09437721B2	Reverse-conducting IGBT with buffer layer and separation layer for reducing snapback In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer surrounds an n-type cathode layer. The n-type buffer layer separates the p-type collector layer and the p-type separation layer from each other. The p-type separation layer separates the n-type cathode layer and the n-type buffer layer from each other. Therefore, the present invention makes it possible to reduce snapback.
US09437720B2	Semiconductor device A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region.
US09437719B2	Method for manufacturing semiconductor device having grooved surface A technology for reducing contact resistance between a semiconductor substrate and an electrode is provided. A provided method for manufacturing a semiconductor device includes: forming an oxide film 62 on a surface 12b of a semiconductor substrate 12 by bringing the surface 12b into contact with ammonia-hydrogen peroxide water mixture; forming a groove 60 on the surface 12b by irradiating light to heat the surface 12b covered with the oxide film 62; removing the oxide film 62 to expose the surface 12b; and forming an electrode 16 on the exposed surface 12b.
US09437717B2	Interface control in a bipolar junction transistor Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
US09437711B2	Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an H-terminated silicon surface, selectively forming a sacrificial material layer within a replacement gate cavity but not on the H-terminated silicon surface, forming a high-k layer of insulating material within the replacement gate cavity above the H-terminated silicon surface and laterally between first spaced-apart portions of the sacrificial material layer, and forming a work-function adjusting material layer in the gate cavity, wherein the work-function adjusting material layer has a substantially planar upper surface that extends between second spaced-apart portions of the sacrificial material layer formed on the sidewall spacers.
US09437709B2	Semiconductor device and fabrication method thereof A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a fin-shaped buffer layer formed on the surface of the substrate. A QW material layer is formed on the surface of the fin-shaped buffer layer. A barrier material layer is formed on the QW material layer. The QW material layer is suitable for forming an electron gas therein. Thereby the short-channel effect is improved, while high mobility of the semiconductor device is guaranteed. In addition, according to the present disclosure, thermal dissipation of the semiconductor device may be improved, and thus performance and stability of the device may be improved.
US09437705B2	Method of manufacturing a spacer for dual gate electronic memory cell and associated electronic memory cell A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at least one of the layers is able to store electric charges, the method including depositing a spacer material layer, at least on the area covered by the stack; ion beam machining the spacer material layer, the ion beam machining being carried out with controlled stopping so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer.
US09437704B2	Semiconductor device having electrode made of high work function material, method and apparatus for manufacturing the same Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation resistance. The semiconductor device includes an insulating film disposed on a substrate; and a metal film disposed on the insulating film. The metal film includes a stacked structure of: a first metal film disposed on the insulating film to directly contact the insulating film; a second metal film disposed on the first metal film to directly contact the first metal film; and the first metal film disposed on the second metal film to directly contact the second metal film, the second metal film having a work function greater than 4.8 eV and being different from the first metal film in material, wherein an oxidation resistance of the first metal film is greater than that of the second metal film.
US09437701B2	Integrated circuit devices with counter-doped conductive gates Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.
US09437700B2	Semiconductor device A semiconductor device is provided with a silicon layer, an upper surface side aluminum layer containing silicon and an insulation film. The upper surface side aluminum layer contacts and is layered on a part of a surface of the silicon layer. The insulation film contacts and is layered on another part of the surface of the silicon layer. The insulation film is adjacent to and contacts the upper surface side aluminum layer. The insulation film includes an insulation film body and a plurality of first nodule segregated portions projecting from the insulation film body toward the upper surface side aluminum layer as seen along a vertical direction relative to the surface of the silicon layer. A corner is formed by a side surface of the insulation film body and a side surface of each of the first nodule segregated portions as seen along the vertical direction.
US09437698B2	Semiconductor device including a gate structure wrapped around a fin structure Methods and structure for a semiconductor device is disclosed, which provides a semiconductor device that includes an integral semiconductor fin structure having a middle section defining a channel region of the semiconductor device. The middle section includes an embedded root portion protruding from an insulating surface on a substrate and a suspended overhead portion arranged above the root portion, which is separated from the overhead portion by a predetermined distance. The root portion and the overhead portion respectively define a substantially identical channel direction. The device further includes a gate structure disposed over the fin structure at the middle section. The gate structure wraps around a cross-section of the overhead portion and caps over the protruded portion of the root portion.
US09437696B2	Semiconductor device and method for fabricating the same A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on both ends of the gate electrode, wherein a pin is formed under the gate electrode between the active regions.
US09437695B2	Semiconductor device and method of manufacturing the same According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of the recess is reflected on a surface of a metal film which is also provided on the back surface of the semiconductor substrate.
US09437693B2	Device having a shield plate dopant region and method of manufacturing same A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.
US09437684B2	Method of producing microstructure of nitride semiconductor and photonic crystal prepared according to the method The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor.
US09437681B2	Dual channel FinFET CMOS device with common strain-relaxed buffer and method for manufacturing thereof A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.
US09437680B1	Silicon-on-insulator substrates having selectively formed strained and relaxed device regions A method of forming a semiconductor device substrate includes forming a donor wafer having a surface comprising regions of relaxed silicon and regions of relaxed silicon germanium (SiGe); epitaxially growing a silicon device layer on the surface of the donor wafer, wherein the silicon device layer comprises tensile strained silicon on the regions of relaxed silicon germanium of the donor wafer, and wherein the silicon device layer comprises relaxed silicon on the regions of relaxed silicon of the donor wafer; and transferring the silicon device layer from the donor wafer to a handle wafer comprising a bulk substrate and an insulator layer, so as to form a silicon-on-insulator (SOI) substrate with the silicon device layer maintaining regions of tensile strained silicon and regions of relaxed silicon.
US09437679B2	Semi-conductor device with epitaxial source/drain facetting provided at the gate edge A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region.
US09437678B2	Fabrication method of semiconductor device, evaluation method of semiconductor device, and semiconductor device A fabrication method of a semiconductor device that includes trench gate structures each having a gate electrode extending in a depth-direction of an element, where first trench gate structures contribute to controlling the element and second trench gate structures do not contribute. The fabrication method includes forming the trench gate structures on a front face of a semiconductor substrate; forming on the front face, an electrode pad connected to the gate electrode of at least one trench gate structure; executing screening by applying a predetermined voltage between the electrode pad and an electrode portion having a potential other than a gate potential, to apply the predetermined voltage to gate insulator films in contact with each gate electrode connected to the electrode pad; and forming the second trench gate structures having the gate electrodes connected to the electrode pad, by short-circuiting the electrode portion to the electrode pad after executing screening.
US09437669B2	Semiconductor device A semiconductor resistor circuit has resistor elements of a polycrystalline silicon thin film formed on an insulating film deposited on a semiconductor substrate. A high stress insulating film is formed on and covers the resistor elements and the insulating film exposed between the resistor elements. Metal wirings cover upper portions of the resistor elements. The high stress insulating film has a membrane stress that is higher than that of the metal wirings.
US09437668B1	High resistivity soft magnetic material for miniaturized power converter An on-chip magnetic structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.
US09437666B2	OLED display device that prevents shorting of interconnections during manufacture thereof An organic light emitting diode (OLED) display device, including a first substrate and a second substrate facing each other, a sealant arranged between the first and second substrates to adhere the first and second substrates together, a plurality of interconnections arranged on one of the first and second substrates and a plurality of cladding parts covering at least a portion of each of the plurality of interconnections at a location that corresponds to the sealant, each of the cladding parts including a material having a higher melting point than that of the interconnections. By including the cladding parts, a short circuit between the interconnections caused by heat applied to the sealant can be prevented, and safety and reliability of the OLED display device can be improved.
US09437665B2	Organic light-emitting display apparatus Disclosed is an organic light-emitting display apparatus. The organic light-emitting display apparatus includes a pixel electrode that is connected to at least one thin film transistor, an opposite electrode that is disposed to face the pixel electrode, an organic light emitting layer that is disposed between the pixel electrode and the opposite electrode, and a pad electrode that includes a first pad layer, a second pad layer disposed on the first pad layer, and a third pad layer which is disposed between the first pad layer and the second pad layer and contains a material having a reducibility that is lower than a reducibility of a material contained in the second pad layer.
US09437664B2	Display device and manufacturing method thereof A display device may include a display area for displaying an image. The display device may further include a peripheral area that surrounds the display area. The display device may further include a pixel disposed in the display area. The display device may further include a bus line disposed in the peripheral area and configured to transmit a signal. The display device may further include a connection conductor set electrically connected to the bus line. The display device may further include a branch line electrically connected to the connection conductor set, configured to receive the signal from the bus line, and configured to transmit the signal to the pixel, wherein a portion of the branch line is disposed in the display area.
US09437655B2	Magnetic tunnel junction with superlattice barriers A magnetic tunnel junction is provided. The magnetic tunnel junction can enhance the tunnel magnetoresistance ratio and a device including the magnetic tunnel junction. The magnetic tunnel junction includes: a pinned layer; a free layer; and a superlattice barrier, the barrier configured between the pinned layer and the free layer. The magnetic tunnel junction may be a series or parallel connection of the above-mentioned basic form. The device including a magnetic tunnel junction may be a magnetic random access memory bit cell, a magnetic tunnel junction transistor device, a magnetic field sensor, etc.
US09437653B2	Stress sensing devices and methods Embodiments relate to stress sensors and methods of sensing stress. In an embodiment, a stress sensor comprises a vertical resistor. The vertical resistor can comprise, for example, an n-type resistor and can have various operating modes. The various operating modes can depend on a coupling configuration of terminals of the resistor and can provide varying piezo-coefficients with very similar temperature coefficients of resistances. Comparisons of resistances and piezo-coefficients in differing operating modes can provide a measure of mechanical stresses acting on the device.
US09437650B2	Image device and methods of forming the same A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.
US09437648B2	Solid-state image pickup device A solid-state image pickup device includes a plurality of pixels each including a photoelectric conversion section that generates an electric charge in accordance with incident light and a junction field-effect transistor that outputs an image signal in accordance with the electric charge generated by the photoelectric conversion section. The solid-state image pickup device includes a first element isolation region using an insulator and a second element isolation region using a pn junction, the first element isolation region and the second element isolation region being arranged in a region in which the plurality of pixels are arranged.
US09437646B2	Detecting device, detector, and imaging apparatus using the same A detecting device which detects electromagnetic waves includes an antennal configured to receive electromagnetic waves, and a plurality of semiconductor rectifying devices serially connected to the antenna, and connected in parallel to each other such that the polarity is aligned, so as to receive electromagnetic waves propagated from the antenna, wherein the plurality of semiconductor rectifying devices are each disposed at positions where the phase of electromagnetic waves propagated from the antenna is substantially the same phase.
US09437639B2	Semiconductor device and manufacturing method thereof Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.
US09437636B2	Solid-state imaging element, manufacturing method, and electronic device A solid-state imaging element includes a semiconductor substrate where a plurality of photodiodes are arranged in a plane, and a separation section which separates the photodiodes, in which the separation section has a photoelectric conversion section formed by filling a material which has a high light absorption coefficient and a high quantum efficiency in trenches which are formed in the semiconductor substrate.
US09437633B2	Depth sensing pixel, composite pixel image sensor and method of making the composite pixel image sensor A depth sensing pixel includes a photodiode; a first photo storage device; and a first transistor configured to selectively couple the photodiode to the first photo storage device. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node.
US09437632B2	Image sensor and manufacturing method thereof An image sensor and a manufacturing method thereof are provided. The image sensor includes: a photo diode; a first-conductive-type isolating layer; a second-conductive-type lightly-doped region formed in the first-conductive-type semiconductor substrate; a first-conductive-type lightly-doped region formed under the second-conductive-type lightly-doped region, where the second-conductive-type lightly-doped region is isolated from the second-conductive-type region by the first-conductive-type lightly-doped region; a gate structure of a transfer transistor; and a floating diffusion region which is second-conductive-type heavily-doped. In the image sensor, the second-conductive-type lightly-doped region is formed to be connected with the floating diffusion region, thus, a distance between the floating diffusion region and the photo diode may be reduced which may enable photo-induced carriers to be transmitted from the photo diode to the floating diffusion region more rapidly, and further increase the transmission efficiency of the photo-induced carriers.
US09437631B2	Solid-state imaging device, manufacturing method of the same, and electronic apparatus A solid-state imaging device includes plural photodiodes which are formed in a photodiode area of a unit pixel with no element separating area interposed therebetween and in which impurity concentrations of pn junction areas are different from each other.
US09437628B1	Biodegradable microwave electronic devices Substantially biodegradable microwave integrated circuits and method for making the microwave integrated circuits are provided. The integrated circuits, which have applications in high performance flexible microwave and digital electronics, utilize biobased, biodegradable cellulose nanofibril films as a substrate and comprise only very small amounts of potentially toxic inorganic materials.
US09437625B2	Display panel and method of manufacturing the same A display panel includes a first pixel electrode electrically connected to a first switching electrode, and includes a plurality of first branches forming micro slits, a second pixel electrode electrically connected to a second switching electrode, and including a plurality of second branches forming micro slits, and a third pixel electrode electrically connected to a third switching electrode, and including a plurality of third branches forming micro slits. The first branches are spaced apart from each other by a first space, and have a first width. The second branches are spaced apart from each other by a second space, and have a second width. The third branches are spaced apart from each other by a third space, and have a third width. At least one of the first width, the second width and the third width is different from the other widths.
US09437622B2	Thin film transistor and method for manufacturing the same, array substrate and display device A thin film transistor and a method for manufacturing the same, an array substrate and a display device that can prevent the semiconductor layer in a channel region from damage. The thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer, an insulator layer, and source/drain electrodes, the insulator layer is provided on the semiconductor layer, covers channel regions of the source/drain electrodes, and is formed of a metal oxide insulator. In this thin film transistor, when water vapor from the air penetrates, the insulator layer formed of the metal oxide insulator will firstly reacts with the water vapor to prevent the metal oxide semiconductor in the channel region from damage.
US09437618B2	Pixel structure and method of fabricating the same A pixel structure includes a thin film transistor device. The thin film transistor device includes a first connection electrode, a second connection electrode, an oxide semiconductor channel layer, a gate insulation layer, a gate electrode, a dielectric layer, a source electrode and a drain electrode. The oxide semiconductor channel layer at least partially covers a top surface of the first connection electrode and a top surface of the second connection electrode. The gate electrode is disposed on the gate insulation layer. The dielectric layer is disposed on the gate electrode and the gate insulation layer. The gate insulation layer and the dielectric layer have a first contact hole at least partially exposing the top surface of the first connection electrode and a second contact hole at least partially exposing the top surface of the second connection electrode. The source electrode is electrically connected to the first connection electrode via the first contact hole, and the drain electrode is electrically connected to the second connection electrode via the second contact hole.
US09437615B2	High intensity discharge lamps with dosing aid A ceramic metal halide lamp according to various embodiments can include a discharge vessel and an ionizable fill. The ionizable fill is sealed within the discharge vessel. The ionizable fill includes an oxygen dispenser to introduce oxygen in a form of a pellet into the discharge vessel in a controlled manner to facilitate a tungsten halogen wall cleaning cycle. The pellet comprises aluminum-oxide and molybdenum-oxide.
US09437614B1	Dual-semiconductor complementary metal-oxide-semiconductor device A method of forming an active device on a semiconductor wafer includes the steps of: forming a plurality of semiconductor fins on at least a portion of a semiconductor substrate; forming a dielectric layer on at least a portion of the semiconductor substrate, the dielectric layer filling gaps between adjacent fins; forming a plurality of gate structures on an upper surface of the dielectric layer; forming a channel region on the dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material; forming source and drain epitaxy regions on an upper surface of the dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another; and replacing the channel region with a second crystalline semiconductor material after high-temperature processing used in fabricating the active device has been completed.
US09437611B1	Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.
US09437608B2	Vertical memory cell string with dielectric in a portion of the body Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.
US09437606B2	Method of making a three-dimensional memory array with etch stop A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.
US09437601B1	Semiconductor device A semiconductor device according to an embodiment includes a stacked body, and a semiconductor pillar. The stacked body includes first insulating layers and conductive layers. The conductive layer includes silicon. At least one of the conductive layers includes a first portion, a second portion, and a third portion. The first portion includes a first element selected from at least one of boron and phosphorus. The second portion includes the first element. The third portion is provided between the first portion and the second portion in a stacking direction of the conductive layers and the first insulating layers. The third portion includes a second element. The second element is selected from at least one of carbon, nitrogen, oxygen, and germanium. The semiconductor pillar pierces through the stacked body. The semiconductor pillar extends in the stacking direction.
US09437600B2	Flash memory structure and method of making the same A method of making a flash memory includes providing a substrate. Then, a first insulating layer, a first conductive layer and a second insulating layer are formed to cover the substrate. Later, a first trench is formed in the first conductive layer and the second insulating layer. After that, a second conductive layer and a mask layer are formed to cover the second insulating layer, and the second conductive layer fills up the first trench. Then, the mask layer are patterned to form patterned mask layers. Subsequently, a spacer is formed on the sidewall of the patterned mask layer. Then, an etching process is carried out by using the patterned mask layers and the spacer as a mask so as to form a first gate structure and a second gate structure.
US09437595B2	Barrier trench structure and methods of manufacture A structure includes at least one shallow trench isolation structure formed in a substrate to isolate adjacent different type devices. The structure further includes a barrier trench structure formed in the substrate to isolate diffusions of adjacent same type devices. The structure further includes a material spanning the barrier trench structure to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.
US09437590B2	Electrostatic discharge protection device and electrostatic discharge protection system An ESD device disposed on a substrate is provided. The ESD device includes a first well, a second well, a first poly-silicon region, a second poly-silicon region and a first protection layer. The first well has a first conductive type and is disposed on the substrate. The second well has a second conductive type, is disposed on the substrate and is adjacent to the first well. The first poly-silicon region is disposed on the first well. The second poly-silicon region is disposed on the second well. The first protection layer covers portions of the first well, the second well, the first poly-silicon region and the second poly-silicon region. There is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.
US09437589B2	Protection devices In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle and a protection device disposed over the die paddle. The protection device includes a first heat generating zone disposed in a substrate. The first heat generating zone is disposed at a first side facing the die paddle. A solder layer at the first heat generating zone joins the protection device with the die paddle.
US09437587B2	Flip chip semiconductor device A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.
US09437585B2	Photoelectric device and method of manufacturing the same A photoelectric device includes an electrode structure, an LED (light emitting diode) element, a zener diode and a reflective cup. The LED element, the zener diode and the reflective cup are arranged on the electrode structure. The LED element and the zener diode are electrically connected in anti-parallel with each other. The reflective cup comprises an inner surface defined thereof and a nick defined in an outside of the reflective cup. The LED element is surrounded by the inner surface of the reflective cup and the zener diode is arranged in the nick.
US09437583B1	Package-on-package assembly and method for manufacturing the same A package-on-package (PoP) assembly includes a bottom die package and a top die package. The bottom die package includes an interposer having a first side and a second side, an active chip mounted on the first side within a chip mounting area through first bumps, and a dummy chip mounted on the first side within a peripheral area. The dummy chip is directly mounted on a passivation layer of the interposer. A dielectric layer covers the active chip and the dummy chip. At least one TSV connecter penetrates through the dielectric layer and the dummy chip. A molding compound is disposed on the first side. The molding compound covers the active chip and the TSV chip. Solder bumps are mounted on the second side.
US09437578B2	Stacked IC control through the use of homogenous region A package includes a semiconductor chip. The semiconductor chip includes a substrate, a plurality of dielectric layers underlying the substrate, a dielectric region penetrating through the plurality of dielectric layers, and a metal pad overlapped by the dielectric region. A conductive plug penetrates through the substrate, the dielectric region, and the metal pad.
US09437577B2	Package on package structure with pillar bump pins and related method thereof A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second package has a plurality of pads connected to the pillar bump pins, respectively. A method of forming a package on package (POP) structure includes at least the following steps: providing a first package with a plurality of pillar bump pins; providing a second package with a plurality of pads; and forming the POP structure by connecting the pillar bump pins to the pads.
US09437572B2	Conductive pad structure for hybrid bonding and methods of forming same A method embodiment includes patterning an opening through a layer at a surface of a device die. The method further includes forming a liner on sidewalls of the opening, patterning the device die to extend the opening further into the device die. After patterning the device die, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
US09437569B2	High density substrate routing in BBUL package Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
US09437568B2	Method for manufacturing semiconductor device having a multilayer interconnection Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.
US09437564B2	Interconnect structure and method of fabricating same A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer.
US09437561B2	Semiconductor chip with redundant thru-silicon-vias A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.
US09437557B2	High density three-dimensional integrated capacitors A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.
US09437556B2	Semiconductor device The reliability of a semiconductor device is improved. Further, miniaturization of the semiconductor device is attained. A sealring is formed in a wiring structure provided over a semiconductor substrate. The sealring has a structure in which sealring wirings respectively formed in a plurality of wiring layers included in the wiring structure are laminated. The position of a side surface on the inner peripheral side of a sealring wiring formed in the wiring layer at the uppermost layer in the wiring layers is located more outside than the position of a side surface on the inner peripheral side of a sealring wiring formed in the wiring layer located one layer lower than the wiring layer at the uppermost layer. The width of the sealring wiring at the uppermost layer is smaller than the width of the sealring wiring located one layer lower than the wiring layer at the uppermost layer.
US09437555B2	Semiconductor device having features to prevent reverse engineering It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
US09437553B2	Electronic device An electronic device includes a first substrate including a first electrode formed on a surface of the first substrate, an electronic component mounted on another surface of the first substrate, a second substrate placed on the first substrate via the electronic component, and a shield disposed between the first substrate and the second substrate.
US09437551B2	Concentric bump design for the alignment in die stacking An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.
US09437547B2	Through silicon vias A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
US09437546B2	Method of forming stacked trench contacts and structures formed thereby Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
US09437541B2	Patterning approach to reduce via to via minimum spacing A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches.
US09437538B2	Semiconductor device including RDL along sloped side surface of semiconductor die for Z-direction interconnect A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.
US09437537B2	Semiconductor device and method of manufacturing the same A semiconductor device including conductive lines configured to include first lines extending generally in parallel in a first direction and second lines extending generally in parallel in a second direction to intersect the first direction from the respective ends of the first lines and each second line having a width wider than the first line, and dummy patterns formed between the second lines.
US09437521B2	Thermally conductive sheet A thermally conductive sheet, comprising a curable resin composition, thermally conductive fibers, and thermally conductive particles, wherein the thermally conductive sheet has a compressibility of 40% or more.
US09437520B2	Semiconductor device including a semiconductor element and a fixed member to which the semiconductor element is fixed A semiconductor device includes a semiconductor element having a rectangular shape in a plan view, and a fixed member to which the semiconductor element is fixed. The semiconductor element is disposed so that a rectangular face of the semiconductor element is faced toward a surface of the fixed member. A part of the rectangular face of the semiconductor element is fixed to the surface of the fixed member. At least corner parts of the rectangular face of the semiconductor element are not fixed to the surface of the fixed member.
US09437510B2	Opto-electrical device and method for manufacturing thereof An opto-electrical device is provided that comprises a cover (10), a barrier structure (20), an opto-electrical structure (30) and a plurality of transverse electrical conductors (40). Therein—the cover (10) includes a metal foil (12) and a patterned electrically conductive layer (14) carried by and electrically insulated from the metal foil,—the opto-electrical structure (30) is sandwiched between the cover (10) and the barrier structure (20), wherein the opto-electrical structure (30) comprises at least an opto-electrical layer (32) and a transparent electrically conductive layer (34), the opto-electrical structure having a first main surface (31) facing towards the cover (10),—the plurality of transverse electrical conductors (40) extend from the metal foil (12) or the patterned electrically conductive layer (14) of the cover (10) through the at least one opto-electrical layer (32) to said transparent electrically conductive layer (34),—the cover (10) extends beyond said first main surface (31) of the opto-electrical structure (30).
US09437506B2	Semiconductor defect characterization The defect-containing die identified from an inspection layer analysis subsequent to a manufacturing step for a wafer including a plurality of die and as well as the faulty die identified from a fault testing of the wafer are processed to identify a subset of the die that both contain a defect and are faulty. A probability analysis is performed to determine a confidence level of whether the die in the subset are faulty due to their defects.
US09437504B2	Method for the formation of fin structures for FinFET devices On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.
US09437501B1	Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.
US09437500B1	Method of forming supra low threshold devices A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device includes a non-volatile memory cell having a gate dielectric and formed in a non-volatile memory well region; a first transistor type formed using a first gate oxide and formed in a first transistor well region; a second transistor type formed using a second gate oxide and formed in a second transistor well region; and a third transistor type formed using a third gate oxide and formed in a third transistor well region. The gate dielectric and the first and second gate oxides are formed from the same oxide stack. The first, second, and third transistor types include extension implants formed using a first implant dopant, and the non-volatile memory cell includes extension implants formed using a second implant dopant, where the first and second implant dopants are different.
US09437499B2	Semiconductor device including merged-unmerged work function metal and variable fin pitch A method of varying a threshold voltage of a semiconductor device includes forming plural first semiconductor fins atop a substrate and which are separated from one another according to a first fin pitch to define first fin trenches having a first width. At least one second semiconductor fin is formed atop the substrate and is separated from the plural first semiconductor fins by a second fin pitch to define second fin trenches having a second width. The method further includes forming a work function metal layer in the first and second fin trenches. The second trenches have a first cavity formed therein such that at least one second semiconductor fin has a different concentration of work function metal layer with respect to the first plural semiconductor fins so as to vary the threshold voltage of the at least one second semiconductor fin with respect to the first plural semiconductor fins.
US09437498B2	Method for the formation of different gate metal regions of MOS transistors A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.
US09437492B2	Substrate for alternative semiconductor die configurations A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.
US09437491B2	Method of forming chip with through silicon via electrode The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.
US09437487B2	Array substrate and fabrication method thereof, and display device Embodiments of the disclosure disclose an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate comprises: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer.
US09437485B2	Method for line stress reduction through dummy shoulder structures Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.
US09437480B2	Methods of forming semiconductor structures including tight pitch contacts and lines Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
US09437477B1	Pattern forming method In one embodiment, a pattern forming method includes forming a first film on a substrate that includes a convex portion and a concave portion so as to expose an upper end of the convex portion. The method further includes forming a photosensitive second film on the first film so as to cover the upper end of the convex portion. The method further includes exposing the second film to light. The method further includes developing the second film with a development liquid to form a second pattern of the second film. The method further includes dissolving and removing the first film exposed from the second pattern with a liquid to form a first pattern of the first film.
US09437476B2	Method of manufacturing semiconductor device including air gap between patterns In one embodiment, a method of manufacturing a semiconductor device includes forming a pattern portion and a flat portion on a substrate, the pattern portion including plural patterns, and the flat portion having a flat surface at a position lower than upper surfaces of the patterns. The method further includes transferring a first film on the substrate to continuously form the first film on the upper surfaces of the patterns and on the flat surface of the flat portion and to form a first air gap between the patterns.
US09437470B2	Self-aligned trench isolation in integrated circuits A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.
US09437469B2	Inertial wafer centering end effector and transport apparatus A substrate transport apparatus for a processing tool. The apparatus has a drive section, a movable arm, and an end effector. The arm is operably connected to the drive section. The end effector is connected to the movable arm for holding and transporting the substrate in the processing tool. The apparatus has a substrate inertial capture edge grip connected to the end effector and arranged so that the grip effects capture and centering of the substrate onto the end effector from substrate inertia.
US09437467B2	Substrate handler A loadport for handling film frames is disclosed. The loadport is modular and substantially compatible with applicable standards regarding modular equipment. In particular, the load port is substantially interchangeable with loadports not adapted for handling film frames. The loadport has a compact shuttle for moving film frames and flexible alignment mechanisms for aligning film frames and cassettes of different configurations.
US09437466B2	Storage container, shutter opening/closing unit of storage container, and wafer stocker using storage container and shutter opening/closing unit Provided is a wafer stocker that can prevent the inflow of an external atmosphere, maintain a wafer storage space at a desired atmosphere with a relatively small amount of gas, and prevent dust from being attached to a wafer surface. A shutter portion, including multiple shield plates having the same height as an interval between shelf plates disposed in a storage container, is disposed with a slight space from a body portion, and by supplying clean gas into the storage container, a clean atmosphere of a higher pressure than an external environment is maintained, and a shutter portion is opened and closed by moving up and down the shield plate independently from the shelf plate that supports a wafer.
US09437465B2	Substrate processing apparatus and method of manufacturing semiconductor device When a step is delayed, an operator can be rapidly informed of the delay. A substrate processing apparatus comprises a process system configured to process a substrate; a control unit configured to control the process system for performing a plurality of steps; and a manipulation unit configured to monitor a progress of each of the plurality of steps, wherein when a time elapsed after the control unit goes into a hold state exceeds an allowable time previously allocated to the one of the plurality of steps while waiting for a completion of the one of the plurality of steps started by the process system, the control unit transmits an alarm message to the manipulation unit so as to inform the manipulation unit that the allowable time is exceeded, terminates the hold state, and performs a recovery action.
US09437464B2	Substrate treating method for treating substrates with treating liquids A method for treating substrates with treating liquids, using a treating tank for storing the treating liquids, a holding mechanism for holding the substrates and placing the substrates in a treating position inside the treating tank, a first and a second treating liquid supply device, a temperature control device, and a control device. A first treating liquid is supplied into the treating tank, then a second treating liquid of lower surface tension and higher boiling point than the first treating liquid, is supplied into the treating tank, and placed in a temperature range above the boiling point of the first treating liquid and below the boiling point of the second treating liquid, and then controlling the second treating liquid supply device to replace the first treating liquid stored in the treating tank with the second treating liquid, and controlling the temperature control device to maintain the second treating liquid in the same said temperature range.
US09437463B2	Heating device A heating apparatus includes a susceptor having a heating face of heating a semiconductor and a supporting part joined with a back face of the susceptor. The susceptor comprises a ceramic material comprising magnesium, aluminum, oxygen and nitrogen as main components. The material comprises a main phase comprising magnesium-aluminum oxynitride phase exhibiting an XRD peak at least in 2θ=47 to 50° by CuKα X-ray.
US09437459B2	Aluminum clad copper structure of an electronic component package and a method of making an electronic component package with an aluminum clad copper structure An electronic component package that includes a package substrate having an aluminum bond pad formed from an aluminum clad copper structure. The aluminum clad copper structure is attached to a dielectric layer. An electronic component is attached to the substrate and includes a conductive structure electrically coupled to the aluminum bond pad. The aluminum bond pad, the electronic component, and at least a portion of the substrate are encapsulated with an encapsulant.
US09437457B2	Chip package having a patterned conducting plate and method for forming the same According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.
US09437456B2	Heat treatment apparatus emitting flash of light Flash lamps connected to short-pulse circuits and flash lamps connected to long-pulse circuits are alternately arranged in a line. The duration of light emission from the flash lamps connected to the long-pulse circuits is longer than the duration of light emission from the flash lamps connected to the short-pulse circuits. A superimposing of a flash of light with a high peak intensity from the flash lamps that emit light for a short time and a flash of light with a gentle peak from the flash lamps that emit light for a long time can increase the temperature of even a deep portion of a substrate to an activation temperature or more without heating a shallow portion near the substrate surface more than necessary. This achieves the activation of deep junctions without causing substrate warpage or cracking.
US09437455B2	Manufacturing method for semiconductor device A manufacturing method for a semiconductor device includes introducing an impurity into a SiC substrate, forming a mixed material layer, which is made from a resin and a fibrous carbon material, on a surface of the SiC material into which the impurity is introduced, performing heat treatment of the SiC substrate in which the mixed material layer is formed on the surface of the SiC substrate, and removing the mixed material layer after the heat treatment.
US09437450B2	Plasma etching method In a plasma etching method, with respect to a substrate to be processed, which has a base layer, a silicon oxide film, and an etching mask formed in this order, the etching mask having an etching pattern formed thereon and being formed of polysilicon, a silicon-containing deposit is deposited on a surface of the etching mask using a plasma generated from a processing gas, while applying a negative direct current voltage to an upper electrode formed of silicon. Furthermore, in the plasma etching method, the silicon oxide film is etched using plasma generated from a first CF-based gas using, as a mask, the etching mask having the silicon-containing deposit deposited thereon.
US09437447B2	Method for patterning a substrate for planarization Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A conformal spacer is applied on a bi-layer or tri-layer mandrel (multi-layer) or other relief feature. The conformal spacer thus wraps around the mandrels and is also deposited on an underlying layer. A fill material is deposited to fill gaps or spaces between sidewall spacers. A CMP planarization step then removes substrate stack material down to a material interface of the bi-layer or tri-layer mandrel, with a middle or lower material of the mandrel being a CMP-stop material. This technique essentially cuts off or removes rounded features such as upper portions of sidewall spacers, thereby providing a spacer material with a planar top surface that can be uniformly etched and transferred to underlying layers.
US09437441B2	Methods for etching substrate and semiconductor devices A method of etching a substrate using a metal-assisted chemical etching process is provided. The method may include forming a metal catalytic layer to a predetermined thickness on a substrate and reacting the metal catalytic layer with the etching solution to form a porous surface in the metal catalytic layer and etch the substrate. When the metal catalytic layer is reacted with an etching solution, a porous surface may be formed on the metal catalytic layer.
US09437436B2	Replacement metal gate FinFET A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
US09437435B2	LTPS TFT having dual gate structure and method for forming LTPS TFT The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.
US09437432B1	Self-compensating oxide layer A method of conformally doping a device on a semiconductor workpiece is disclosed. An oxide layer is applied to all surfaces of the device. Further, the thickness of the oxide layer on each surface is proportional to the energy that ions impact that particular surface. For example, ions strike the horizontal surfaces at nearly a normal angle and penetrate more deeply into the workpiece than ions striking the vertical surfaces. After creating an oxide layer that has a variable thickness, a subsequent dopant implant is performed. While ions strike the horizontal surfaces with more energy, these ions pass through a thicker oxide layer to penetrate the workpiece. In contrast, ions strike the vertical surfaces with less energy, but traverse a much thinner oxide layer to penetrate the workpiece. The result is a conformally doped device.
US09437431B2	Electronic device manufacture New methods are provided for manufacturing a semiconductor device. Preferred methods of the invention include depositing a photoresist on a semiconductor substrate surface followed by imaging and development of resist coating layer; applying a curable organic or inorganic composition over the resist relief image; etching to provide a relief image of the resist encased by the curable composition; and removing the resist material whereby the curable organic or inorganic composition remains in a relief image of increased pitch relative to the previously developed resist image.
US09437424B2	High mobility power metal-oxide semiconductor field-effect transistors High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on”resistance of the device.
US09437423B2	Method for fabricating an inter dielectric layer in semiconductor device In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.
US09437422B2	Method of manufacturing semiconductor device and substrate processing method A method of manufacturing a semiconductor device is provided. The method includes: forming a film containing a predetermined element, oxygen, carbon and nitrogen on a substrate by repeating a cycle. The cycle includes: (a) supplying a source gas containing the predetermined element and a halogen element to the substrate; (b) supplying a first reactive gas containing three elements including carbon, nitrogen and hydrogen to the substrate; (c) supplying a nitriding gas as a second reactive gas to the substrate; (d) supplying an oxidizing gas as a third reactive gas to the substrate; and (e) supplying an hydrogen-containing gas as a fourth reactive gas to the substrate, wherein (a) through (e) are non-simultanelously performed.
US09437421B2	Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium A substrate processing apparatus includes a process chamber in which a substrate is accommodated; a source gas supply system configured to supply a source gas onto the substrate; first and second reactive gas supply systems configured to supply a reactive gas onto the substrate via first and second interconnected reactive gas supply pipes, wherein a gas storage unit is installed at the second reactive gas supply pipe to store the reactive gas and the reactive gas is supplied onto the substrate via the gas storage unit; and a control unit configured to control the source gas supply system to supply the source gas onto the substrate and to control the first and second reactive gas supply systems to supply the reactive gas onto the substrate via the first and second reactive gas supply pipes.
US09437420B2	Capacitors including amorphous dielectric layers and methods of forming the same A capacitor can include a crystallized metal oxide dielectric layer having a first dielectric constant and an amorphous metal oxide dielectric layer, on the crystallized metal oxide dielectric layer, where the amorphous metal oxide dielectric layer has a second dielectric constant that is less than the first dielectric constant and is greater than a dielectric constant of aluminum oxide.
US09437419B2	Method of forming a layer using a trialkylsilane silicon precursor compound A trialkylsilane-based silicon precursor compound may be expressed by Si(Ri)X, i=1-3, where each of “R1”, “R2”, and “R3” is a hydrogen or an alkyl having 1-5 carbon(s), all of “R1”, “R2”, and “R3” are not hydrogen, “X” is one of hydrogen, a hydroxyl group, an amide group, an alkoxide group, a halide group, or Si(R)3, and “R” is a hydrogen or an alkyl group having 1˜5 carbon(s).
US09437410B2	System and method for applying curtain gas flow in a mass spectrometer A system of mass spectrometry is disclosed having an ion source for generating ions at substantially atmospheric pressure. The system has a sampling member with an orifice disposed therein. The sampling member forms a vacuum chamber with a mass spectrometer. The system also has a curtain plate between the ion source and the sampling member. The curtain plate has an aperture therein, having a cross-section and being spaced from the sampling member to define a flow passage between the curtain plate and the sampling member, and to define an annular gap between the orifice and the aperture. The area of the annular gap is less than the cross-sectional area of the aperture. The system also has a power supply for applying a voltage to the curtain plate, and a curtain gas flow mechanism for directing a curtain gas into the flow passage and the annular gap.
US09437407B2	Mass spectrometry for multiplexed quantitation using multiple frequency notches A method of performing a mass spectrometry analysis includes labeling each of a plurality of samples with a corresponding chemical tag; forming a first plurality of ions from molecules in the samples; selecting a subset of the first plurality of ions, the subset being selected by isolating ions of the first plurality of ions in a plurality of ranges of mass-to-charge; forming a second plurality of ions by fragmenting ions in the subset; and measuring information indicative of a quantity of each of the plurality of chemical tags present in each of the plurality of samples.
US09437405B2	Hot rolled plate made of copper alloy used for a sputtering target and sputtering target Disclosed is a hot rolled plate produced by hot rolling an ingot cast by continuous casting, in which the plate is made of a copper alloy containing 0.5 to 10.0 at % of Ca and the balance consisting of Cu and inevitable impurities and the average grain size of Cu-α phase crystal grains is 5 to 60 μm in a Cu matrix.
US09437399B2	Plasma equipment There is provided plasma equipment including a power supply that supplies a RF power; a chamber in which plasma is generated, and a processing target to processed by the plasma is provided; an antenna coil that is provided on a top surface of the chamber, and is connected to the power supply to receive the RF power; and a resonance coil that is provided to be electrically insulated or cut off from the antenna coil. The resonance coil receives electromagnetic energy applied from the antenna coil to allow a current to flow, and the plasma is generated within the chamber. It is possible to increase the degree of freedom for an installation position of the resonance coil, and it is possible to increase plasma density.
US09437395B2	Method and compound system for inspecting and reviewing defects The present invention provides an improved electron-optical apparatus for the inspection and review of the specimen, and for the defect inspection, an inspection mode of operation is performed to generate inspection data, wherein the large beam current is formed by a magnetic immersion lens to scan the specimen, and preferably the objective lens system, a swing objective retarding immersion lens, focuses the beam current and generates the large scanning field, and for the defect review, the review mode of operation is performed to analyze the defects, wherein the large beam current is abandoned and the small beam current is adopted to examine the specimen without a large scanning field, and in order to properly select and detect signal charged particles excited from the specimen, a first Wien filter is utilized to select the acquired signal particles and a second Wien filter is used to compensate the aberrations induced when the signal particles pass through the first Wien filter.
US09437391B2	Carbon nanotube based micro-tip structure and method for making the same A carbon nanotube micro-tip structure includes an insulating substrate and a patterned carbon nanotube film structure. The insulating substrate includes a surface. The surface includes an edge. The patterned carbon nanotube film structure is partially arranged on the surface of the insulating substrate. The patterned carbon nanotube film structure includes two strip-shaped arms joined at one end to form a tip portion protruded from the edge of the surface of the insulating substrate and suspended. Each of the two strip-shaped arms includes a plurality of carbon nanotubes parallel to the surface of the insulating substrate.
US09437390B2	X-ray tube device An X-ray tube device according to the present invention includes a cathode generating an electron beam, an anode generating an X-ray by collision of the electron beam from the cathode, an envelope internally housing the cathode and the anode, a magnetic field generator including a magnetic pole arranged to be opposed to the envelope, generating a magnetic field for focusing and deflecting the electron beam from the cathode to the anode, and an electric field relaxing electrode arranged between the magnetic pole and the envelope, having an outer surface having a rounded shape. Thus, the magnetic field generator can be placed closer to the envelope while a tip end of the magnetic field generator is suppressed from being a discharge start point, and hence the effect of being capable of downsizing the X-ray tube device is achieved.
US09437388B2	Method and system for dynamic in-situ phosphor mixing and jetting A system and method for depositing a phosphor composition onto a light emitting device improves manufacturing yield, simplifies conventional processes, and decreases costs. For example, a method of dispensing a phosphor composition onto a light emitting device includes dispensing a portion of the phosphor composition onto the light emitting device utilizing a plurality of colored phosphor dispensers each for dispensing a respective type of phosphor. Power is applied to the light emitting device to emit light, and a characteristic the light emitted by the light emitting device is detected. Phosphor mixing and phosphor dispensing are dynamically controlled. Therefore the color characteristics of phosphor dispensed on LEDs are consistent. The system and method may also reduce the difference between detected characteristic of the light and a desired characteristic of the light.
US09437386B2	Protective wiring device The present is directed to a protective device that includes a separator portion disposed between a back body member and a front cover portion. The separator portion includes a reset pin aperture accessible via a first major surface facing the front cover and a reset pin guide portion disposed on an opposite second major surface facing the back body member. The device further includes a latch block assembly having a central latch block portion configured to accommodate a reset pin and a latching element. The central latch block portion includes an open side configured to accommodate the reset pin guide portion. The reset pin is substantially prevented from exiting the central latch block portion via the open side by the reset pin guide portion.
US09437383B2	Auxiliary contact mechanism of electromagnetic contactor The present invention relates to an auxiliary contact mechanism of an electromagnetic contactor, and more particularly, to an auxiliary contact mechanism of an electromagnetic contactor capable of maximizing a time duration for which power is supplied to a magnetic coil for switching a main contact until the main contact is closed. The auxiliary contact mechanism of an electromagnetic contactor, includes: a case formed to have a box shape; an auxiliary sliding member installed above the case, and moving up and down by receiving a pressure from a main contact sliding member; an elastic member accommodated in an insertion groove formed in the auxiliary sliding member; a pressing member insertion-installed below the auxiliary sliding member, and moving up and down by an elastic force of the elastic member; and a micro switch turned on/off by the pressing member.
US09437382B2	Electromagnet device and electromagnetic relay using the same An electromagnet device has a spool having a guard portion at at least one end thereof, a coil wound around a body portion of the spool, and a coil terminal press-fitted in the guard portion. A lead wire of the coil is tied up to a tying-up portion of the coil terminal projected from the guard portion. The tying-up portion is folded toward the guard portion of the spool after the lead wire of the coil is tied up to the tying-up portion of the coil terminal extending in a direction receding from the spool.
US09437381B2	Electric vehicle support equipment having a smart plug with a relay control circuit A smart plug for coupling an electric vehicle to a power supply includes a relay including contacts, the relay configured to operate in a closed state to enable power to be supplied to the electric vehicle and an open state to prohibit power from being supplied to the electric vehicle. The smart plug also includes a microcontroller (MCU) coupled to the relay, the microcontroller outputting a control signal to operate the relay in the closed state. The smart plug further includes a zero crossing detector (ZCD) coupled to the relay, the ZCD outputting a close signal to the relay when a voltage of the power is substantially zero and outputting an open signal to the relay when a current of the power is substantially zero.
US09437378B2	Keyswitch device A keyswitch device includes a pair of links for supporting a key top, each provided on the support sheet and including a first arm and a second arm, and a frame for supporting the links, provided on the support sheet. Each link includes a rotation shaft provided at a first end and a slide shaft provided at a second end of each of the first arm and the second arm. The rotation shaft is rotatably placed on one of the frame and the key top. The slide shaft is slidably placed in a corresponding one of guide grooves provided on the other of the frame and the key top. A connecting groove is provided in the first arm of at least one of the links. A connecting shaft is provided on the second arm of the other of the links, and is movably placed in the connecting groove.
US09437375B2	Electromagnetic relay assembly having a switch control unit An electromagnetic relay assembly includes a switching unit to push a sliding member and to place a locking portion of a locking member to lock the sliding member at a first position where the switching unit switches a first conductive plate and a second conductive plate to an electrically disconnected state. When a coil is energized, the sliding member is moved to a second position, and the locking portion of the locking member is placed to lock the sliding member in the second position where the switching unit is actuated by the sliding member to switch the first and second conductive plates to an electrically connected state.
US09437371B2	Nitrile-substituted silanes and electrolyte compositions and electrochemical devices containing them Described herein are liquid, organosilicon compounds that including a substituent that is a cyano (—CN), cyanate (—OCN), isocyanate (—NCO), thiocyanate (—SCN) or isothiocyanate (—NCS). The organosilicon compounds are useful in electrolyte compositions and can be used in any electrochemical device where electrolytes are conventionally used.
US09437370B2	Lithium-ion cell having a high-capacity anode and a high-capacity cathode A lithium-ion cell comprising: (A) a cathode comprising graphene as the cathode active material having a surface area to capture and store lithium thereon and wherein said graphene cathode is meso-porous having a specific surface area greater than 100 m2/g; (B) an anode comprising an anode active material for inserting and extracting lithium, wherein the anode active material is mixed with a conductive additive and/or a resin binder to form a porous electrode structure, or coated onto a current collector in a coating or thin film form; (C) a porous separator disposed between the anode and the cathode; (D) a lithium-containing electrolyte in physical contact with the two electrodes; and (E) a lithium source disposed in at least one of the two electrodes when the cell is made. This new Li-ion cell exhibits an unprecedentedly high energy density.
US09437361B2	Three-phase high frequency transformer A three-phase high frequency transformer has: a ferrite core formed from three solid-cylindrical cores and a ceiling plate and a bottom plate; and three sets of coils having primary coils of a predetermined inner diameter that are formed by bending flat wires plural times in width directions of the flat wires, and secondary coils that are formed such that an inner diameter is the same as the inner diameter of the primary coils by bending flat wires, that have a width that is different than a width of the flat wires of the primary coils, in width directions of the flat wires, and the flat wires that structure the secondary coils are interposed within intervals of the flat wires that structure the primary coils, and the three sets of coils are structured such that inner peripheries of the primary coils and the secondary coils coincide, and are disposed such that the respective solid-cylindrical cores are inserted in respective inner portions, and the primary coils and the secondary coils are Δ-connected or Y-connected.
US09437360B2	Structure of transformer An improved structure of a transformer includes a bobbin covering at least a portion of a magnetic core set which has a magnetic loop passing through the bobbin, wherein winding grooves and at least one connecting portion extending sideways are provided on the outer peripheral side of the bobbin, and a plurality of notches with lateral openings are provided on the connecting portion. Coils are wound in the winding grooves of the bobbin. The coils have at least a plurality of line ends, each line end passing through a different notch. One positioning pin is embedded in each of the winding grooves near the lateral opening. The positioning pins hold the respective line ends in place by pressing against them. A casing is fitted on the outer peripheral side of the coils to create separation between the coils and the magnetic core set. The casing is provided with a hollow opening such that the outer peripheral side of the coils facing the airflow is exposed to improve the overall heat dissipating efficiency.
US09437359B2	Reinforcement-free tank for an electromagnetic apparatus A reinforcement-free tank for an electromagnetic apparatus, as may be immersed in a fluid is provided. The tank may include a pair of mutually-opposite side walls. Each side wall may have at least one curved segment defining a vertically-curving profile between a top edge and a bottom edge of a side wall. A pair of mutually-opposite end walls. Each end wall may have a substantially vertically-extending semi-cylindrical shape defining a vertically-straight profile between a top edge and a bottom edge of an end wall. A plurality of vertically-extending joining members. Each joining member may be configured to provide a transition between the vertically-curving profile of a side wall and the vertically-straight profile of a corresponding end wall. The walls can withstand vacuum and overpressure conditions which can develop in the tank, without a reinforcing member connected to the walls.
US09437354B2	Voltage surge protector having a pressure release mechanism A voltage surge protector consisting of a plurality of varistors connected in a column, an upper electrode connected to the upper edge of the column of varistors, a lower electrode connected to the lower edge of the column of varistors, an insulating housing that surrounds the column of varistors, a fiberglass cover that surrounds the insulating housing and a weatherproof protective cover provided with barriers mounted on the fiberglass cover. The protector has a mechanism to release pressure during a voltage surge, which consists of a hole in a transversal direction for each varistor of the column of varistors inside the insulating housing, the holes being helicoidally distributed along the length of the housing of insulating material and of a depth less than the thickness of the insulating housing.
US09437353B2	Resistor, particularly a low-resistance current-measuring resistor The invention relates to a resistor, in particular a low-resistance current-measuring resistor, comprising a first connection part (1) that consists of a conductor material for introducing an electrical current (I), a second connection part (2) that consists of a conductor material for discharging said electrical current (I), and a resistor element (3) that consists of a resistor material and is arranged between the two connection parts (1, 2) in the direction of the current, also comprising a resistor coating (7) that consists of a metallic material for the purpose of achieving protection from corrosion, and/or improving solderability. According to the invention, the metallic coating (7) is applied directly to the entire free surface of the resistor element (3) without any insulation layer.
US09437351B2	Shield wire for wiring harness and method of making the same Disclosed is a shield wire for a wiring harness improving workability for wiring, and a method of the shield wire for a wiring harness. Forming of a shield part by winding a strip-like shield member outside of an electric wire allows work for inserting the electric wire into the shield part to be omitted, which improves workability for wiring. Forming of overlap portion where the shield part overlaps with each other in a radial direction allows the electric wire not to be exposed even if the shield electric wire for a wiring harness is bent, which prevents leak or penetration of electromagnetic wave.
US09437347B2	Method for manufacturing an electrostatic discharge device The invention is achieved by applying a layer of the mixture that contains polymer and conductive particles over a first surface, when the mixture has a first viscosity that allows the conductive particles to rearrange within the layer. An electric field is applied over the layer, so that a number of the conductive particles are aligned with the field and thereafter the viscosity of the layer is changed to a second, higher viscosity, in order to mechanically stabilize the layer. This leads to a stable layer with enhanced and anisotropic conductivity that can be used in the manufacture of ESD devices.
US09437341B2	Method and apparatus for generating high current negative hydrogen ion beam An apparatus to generate negative hydrogen ions includes an ion source operative to generate positive hydrogen ions, a first component to adjust positive molecular hydrogen ion species in the ion source, a second component to adjust extraction voltage for extraction of the positive molecular hydrogen ions from the ion source, and a charge exchange cell comprising charge exchange species to convert the extracted positive molecular hydrogen ions to negative hydrogen ions. The adjusted extraction voltage is effective to generate an ion energy to maximize negative ion current yield in the charge exchange cell based upon a product of extraction efficiency of the positive molecular hydrogen ions and a peak in charge exchange efficiency for converting a species of the positive molecular hydrogen ions to negative hydrogen ions through charge exchange between the extracted hydrogen ions and charge exchange species.
US09437340B2	Leaf module for a multi-leaf collimator and multi-leaf collimator The invention relates to a leaf module (102) for a multi-leaf collimator (132), comprising a leaf unit (104) and a leaf drive unit (106), wherein the leaf unit (104) comprises a leaf (108) for shielding beams from a selected area, and the leaf unit (104) is mounted displaceably in an adjusting direction (110), wherein the leaf drive unit (106) is designed to displace the leaf unit (104) linearly in the adjusting direction (110), and wherein the leaf drive unit (106) comprises at least one drive mechanism (112), being designed in such a way that the drive mechanism (112) operates based on pneumatic actuation. Furthermore, the invention relates to a multi-leaf collimator (132) comprising a plurality of leaf modules (102) according to the invention. The invention is based on the objective of designing a leaf module (102) and a multi-leaf collimator (132) as compactly as possible, while achieving a simple, reliable and variable adjustability of the leaf unit (104). The invention is regarded to be particularly suitable for implementation in Cobalt-60 or mid- to low-end linac radiotherapy apparatuses.
US09437338B2	Solidification method of radioactive waste A solidification method of radioactive waste is provided, including kneading a binder and an inorganic adsorbent to obtain a kneaded object, the in organic adsorbent included radionuclides; extruding the kneaded object to obtain an extruded material object; cutting the extruded material object to obtain at least one extruded material block; and firing the at least one extruded material block to solidify the at least one extruded material block.
US09437336B2	Isotope-specific separation and vitrification using ion-specific media Apparatuses, processes and methods for the separation, isolation, or removal of specific radioactive isotopes from liquid radioactive waste, these processes and methods employing isotope-specific media (ISM). In some embodiments, the processes and methods further include the vitrification of the separated isotopes, generally with the ISM; this isotope-specific vitrification (ISV) is often a step in a larger scheme of preparing the radioactive isotopes for long-term storage or other disposition. A variety of ISM are disclosed.
US09437331B2	Inherently safe passive gas monitoring system Generally, the present disclosure is directed to gas monitoring systems that use inductive power transfer to safely power an electrically passive device included within a nuclear material storage container. In particular, the electrically passive device can include an inductive power receiver for receiving inductive power transfer through a wall of the nuclear material storage container. The power received by the inductive power receiver can be used to power one or more sensors included in the device. Thus, the device is not required to include active power generation components such as, for example, a battery, that increase the risk of a spark igniting flammable gases within the container.
US09437328B2	Apparatus and method for applying at-speed functional test with lower-speed tester A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.
US09437327B2	Combined rank and linear address incrementing utility for computer memory test operations Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.
US09437323B2	Shift register circuit for preventing malfunction due to clock skew and memory device including the same A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.
US09437321B2	Error detection method Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect.
US09437320B1	Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference A system including a receiving module to receive data from cells of memory, each cell storing multiple bits, each bit corresponding to a different type of page of the memory, the bits stored in a cell denoting a state of the cell, and the data including bits from a page of the memory or states of cells along a word line of the memory. A processor generates a reliability indication for a first portion of the data corresponding to a first cell based on the first portion of the data and one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell. A decoder decodes the first portion of the data based on the first portion of the data and the reliability indication for the first portion of the data.
US09437318B2	Adaptive program pulse duration based on temperature Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state.
US09437314B2	Precharge control signal generator and semiconductor memory device therewith A precharge control signal generator and a semiconductor memory device include a precharge control signal generating circuit which generates a precharge control signal and applies the precharge control signal to a sensing circuit, and a sensing circuit configured to precharge a bit line connected to a memory cell according to the precharge control signal and read data stored in the memory cell. The precharge control signal controls the sensing circuit so that a precharge time is adjusted according to operating temperature.
US09437308B2	Nonvolatile semiconductor memory device which performs improved erase operation According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
US09437305B2	Programming memory with reduced short-term charge loss Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.
US09437302B2	State-dependent lockout in non-volatile memory A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
US09437301B2	Non-volatile semiconductor memory device According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region.
US09437299B2	Systems and methods for order scope transitions using cam A data processing system includes a content addressable memory (CAM). Each entry of the CAM corresponds to a task and is configured to store a current scope of each task. A random access memory (RAM) is configured to shadow information of the CAM. Transition position storage circuitry is configured to store transition age positions for tasks. Control circuitry is configured to, in response to a command to transition a selected task to a destination scope, access the RAM to determine the current scope for the selected task, use the current scope to perform a match determination with the CAM to determine if any entries corresponding to tasks other than the selected task match the current scope; and for any matching entries, updating a transition age position in the transition position storage circuitry for the corresponding task within the current scope.
US09437296B2	Three-dimensional resistive memory device with adjustable voltage biasing A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.
US09437292B1	Circuits and methods for limiting current in random access memory cells Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.
US09437290B2	Resistive memory device and operation A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.
US09437286B2	Memory system, method of programming the memory system, and method of testing the memory system A method of programming a memory system includes repetitively performing N program loops for a selected memory cell (where N is a natural number equal to or greater than two). Each of the N program loops includes a program operation and a program verify operation. At least one of the N program loops includes performing the program operation on the selected memory cell and on at least one additionally selected memory cell by applying a program voltage to at least one word line to which the selected memory cell and at least one additionally selected memory cell are connected, and performing the program verify operation on the selected memory cell by applying a program verify voltage to a selected word line to which the selected memory cell is connected.
US09437284B1	Memory devices and control methods thereof A memory device is provided. The memory device includes a memory device, a plurality of word lines and bit lines, first and second decoders, and a control circuit. The memory array includes memory cells on rows and columns. Each word line is coupled to the memory cells in one row. Each bit line is coupled to the memory cells in one column. The first decoder selects one word line according to an address signal and a first control signal. The control circuit respectively generates the first control signal and the second control signal according to a first clock signal and a second clock signal. In the period during which the first decoder selects the one word line, the second decoder selects at least two bit lines according to the address signal and a second control signal. The memory device performs a read/write operation on the selected bit lines.
US09437280B2	DRAM sense amplifier that supports low memory-cell capacitance The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.
US09437277B1	Mechanism for data generation in data processing systems An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.
US09437276B2	Maintenance operations in a DRAM A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
US09437275B2	Memory system and method for operating the same A memory system may include a memory including a cell array having a plurality of word lines and an address storage unit that stores an address in response to a capture command, wherein the memory sequentially refreshes the word lines in response to a refresh command at a set cycle, and refreshes a word line corresponding to the stored address in response to the refresh command when the address is stored in the address storage unit; and a memory controller transmitting the refresh command to the memory at the set cycle when a word line satisfying one or more of conditions that the number of activation times is equal to or more than a reference number and an activation frequency is equal to or more than a reference frequency is detected, and transmitting the capture command and an address of the detected word line to the memory.
US09437273B2	Semiconductor device To provide a semiconductor device that has a novel structure and achieves a higher degree of convenience, the semiconductor device is configured to include a memory cell that stores binary data or multilevel data, and a reading circuit that reads the data stored in the memory cell and transfers the data to the outside. The reading circuit includes a first reading circuit for reading binary data and a second reading circuit for reading multilevel data.
US09437271B2	Electronic devices having semiconductor magnetic memory units An electronic device comprising a semiconductor memory unit that includes a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input terminal.
US09437270B2	Nonvolatile memory apparatus for controlling a voltage level of enabling a local switch A nonvolatile memory apparatus includes: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; and a local switch block configured to apply a write voltage, a read voltage, and a source line voltage to the bit line and the source line in response to a local switch select signal. In a write or read operation of the nonvolatile memory apparatus, the word line has a first voltage level, and the local switch select signal has a second voltage level higher than the first voltage level.
US09437265B2	Semiconductor device having shallow trench isolation and gate groove Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that extends within the first and second regions. First and second active regions are disposed in respective first and second regions, with a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench. A cap insulating film is disposed in an upper portion of the gate groove covering an upper surface of the gate electrode. First and second transistors are within respective first and second active regions and share the gate electrode.
US09437262B2	Memory controller and associated signal generating method A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.
US09437255B2	Semiconductor device controlling refresh operation for preventing wordline disturbance A semiconductor device may include a storage unit configured to store a number of times a first command has been provided to a memory cell array, a control unit configured to generate a second command operable to activate at least one word line in the memory cell array based on a comparison of the number stored at the storage unit with a threshold value, when the first command is received, and a selection unit configured to select one of the first command and the second command based on a result of the comparison and transmit the selected command to the memory cell array.
US09437252B2	Stack bank type semiconductor memory apparatus capable of improving alignment margin A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.
US09437248B2	Apparatus and method for transmitting video data from mobile communication terminal An apparatus and method for transmitting video data to a receiving terminal is disclosed. The apparatus comprises an event processing unit for outputting a signal to store a selected portion of the video data that is currently being reproduced, a video data reproduction unit for receiving the signal from the event processing unit and storing the selected portion of the video data that is currently being reproduced in response to the outputted signal while reproducing the video data. A message transmission unit is further provided for attaching the stored selected portion of the video data that is currently being reproduced to a message and transmitting the message to the receiving terminal. A data storage unit stores the video data and the selected portion of the video data.
US09437247B2	Preview display for multi-camera media clips Some embodiments provide a graphical user interface (GUI) of a media-editing application. The GUI includes a composite display area for displaying a set of media clips that define a composite presentation. The set of media clips includes a particular media clip which includes several different groups of ordered clips that are selectable for use in the composite presentation. The GUI includes a preview display area for simultaneously displaying video images from several of the different groups corresponding to a time in the composite presentation. The displayed video images in the preview display area are selectable to determine which of the groups is for use in the composite presentation.
US09437245B2	Video recording apparatus and external terminal An external terminal having a communication unit capable of communicating with a video recording apparatus, the external terminal includes an input unit operable to input additional information from a user, an input start detecting unit operable to detect start of the input of the additional information to the input unit, and a recording state inquiring unit operable to inquire of the video recording apparatus and acquire information representing a recording position in video data currently being recorded by the video recording apparatus via the communication unit, when the input start detecting unit detects the start of the input of the additional information.
US09437244B2	Image processing apparatus, image processing method, and recording medium The present invention comprises an input part for inputting image data, a receiving part for receiving production information relating to production transmitted from another apparatus, a recording part for recording the production information received by the receiving part and image data input by the input part, a detection part for detecting a recording position on a recording medium at an editing point of image data recorded by the recording part, and a transmission part for transmitting information of the recording position detected by the detection part, whereby identification information for identifying image data and voice data is recorded in a recording medium or a recording device, this relieving a burden on a photographer and an editor and facilitating extraction of image data and voice data.
US09437236B2	Encoding data Data can be encoded in physical medium and represented by shapes having many various physical attributes. In various examples, data points are encoded and represented by the physical shape, color, size, and/or structure of objects. In one embodiment, holes in memory surface substrates represent data. Various attributes of such holes, including depth, profile size, profile shape, and/or angle can represent data.
US09437235B2	Glass substrate for information recording medium and method for manufacturing the same The present invention relates to a method for manufacturing a glass substrate for an information recording medium having a high level of cleanness and superior smoothness. The manufacturing method includes a step for washing a disk-shaped glass plate with an acid washing liquid, a step for removing at least part of a surface layer, which is formed on the surface of the glass plate, by performing grinding with diamond abrasion grains, and a step for washing the surface with a neutral or alkaline washing liquid.
US09437234B1	Head-medium contact detection using high frequency heater oscillation An apparatus comprises a read/write head having a heater, wherein a low- or non-modulation interface is defined between the head and a magnetic recording medium. A microactuator is coupled to the head. A main actuator is coupled to the microactuator and the head. A controller is coupled to the main actuator, the microactuator, and the head. The controller is configured to control movement of the main actuator and the microactuator in response to a position error signal. The controller is further configured to induce an oscillation in the heater at a predetermined frequency. A detector is coupled to the controller. The detector is configured to sense a disturbance in the PES supplied to the microactuator resulting from the induced heater oscillation, and detect contact between the head and the medium using the PES disturbance.
US09437230B2	And method of operation of micro-milliactuators and micro-microactuators A micro-milliactuator, a micro-microactuator, an actuator arm assembly, a hard disk drive and a method for operation of the hard disk are provided. In accordance with one aspect, the actuator arm assembly includes an arm, a slider for reading and writing information to disk media in response to read/write signals, and an actuator selected from the group comprising a micro-milliactuator and a micro-microactuator. The actuator has the slider mounted thereon and supports it above the disk media. The actuator includes one or more piezoelectric actuators for horizontally shifting the slider in response to actuator control signals. The actuator further includes one or more sensors physically coupled thereto for vibration sensing, compensation and suppression, the one or more sensors generating sensor signals in response to sensed vibrations during operation, wherein the actuator control signals are generated at least partially in response to the sensor signals.
US09437223B2	Magnetoresistive element, method of manufacturing magnetoresistive element, magnetic head, and magnetic recording and reading apparatus A magnetoresistive element according to an embodiment includes: a multilayer element including a first magnetic layer, a magnetization direction of the first magnetic layer being pinned, a nonmagnetic layer disposed on the first magnetic layer, a second magnetic layer disposed in a first region on the nonmagnetic layer, a magnetization direction of the second magnetic layer being pinned and antiparallel to the magnetization direction of the first magnetic layer, and a third magnetic layer disposed in a second region that is different from the first region on the nonmagnetic layer near one of two opposite end faces of the nonmagnetic layer, a magnetization direction of the third magnetic layer being changeable by an external magnetic field, a lower face of the nonmagnetic layer being in contact with an upper face of the first magnetic layer.
US09437220B2	Varying data writer side shield gap distal the ABS A data writing element may be configured at least with a write pole positioned adjacent a first shield along a first axis and adjacent a second shield along a second axis. The second shield may be separated from the write pole by a first gap distance on an air bearing surface (ABS) and by a second gap distance distal the ABS with the first and second gap distances meeting at a transition surface oriented parallel to the ABS.
US09437215B2	Predictive video analytics system and methods The methods and systems described herein predict user behavior based on analysis of a user video communication. The methods include receiving a user video communication, extracting video facial analysis data from the video communication, extracting voice analysis data from the video communication, associating the video facial analysis data with the voice analysis data to determine an emotional state of a user, collecting biographical profile information specific to the user, applying a linguistic-based psychological behavioral model to the spoken words to determine personality type of the user, and inputting the collected biographical profile information, emotional state, and personality type into a predictive model to determine a likelihood of an outcome of the video communication.
US09437214B2	Distributed audience measurement systems and methods Systems and methods are disclosed for customizing, distributing and processing audio fingerprint data. An example method includes receiving, at a first device, an activation signal and a first audio fingerprint via first wireless communications between the first device and a communications network, the receiving occurring while the first device is not recording audio via a microphone of the first device; based on the activation signal, recording audio using the microphone during a first time period; generating a second audio fingerprint representative of the recorded audio; determining whether the second audio fingerprint matches the first audio fingerprint; and sending an indication of whether the second audio fingerprint matches the first audio fingerprint to an audience measurement entity via second wireless communications between the first device and the communications network.
US09437212B1	Systems and methods for suppressing noise in an audio signal for subbands in a frequency domain based on a closed-form solution Systems and methods for reducing noise from an input signal are provided. An input signal is received. The input signal is transformed from a time domain to a plurality of subbands in a frequency domain, where each subband of the plurality of subbands includes a speech component and a noise component. For each of the subbands, an amplitude of the speech component is estimated based on an amplitude of the subband and an estimate of at least one signal-to-noise ratio (SNR) of the subband. The estimating of the amplitude of the speech component is based on a closed-form solution. The plurality of subbands in the frequency domain are filtered based on the amplitudes of the speech components.
US09437203B2	Error concealment for speech decoder Provided is a system, method, and computer program product for improving the quality of speech reproduction in wireless applications where the received speech frames are subject to transmission and packet losses. The speech decoding process is dynamically delayed by at least one frame period in order to perform additional error correction and concealment techniques during times when the wireless link quality if below a predetermined threshold. The wireless link is monitored and if the link quality falls below a predetermined threshold, the decoding process is delayed by at least one frame period so that one or more error correcting techniques can be performed to increase the quality of the reconstructed speech.
US09437197B2	Encoding device, encoding method, and program This technology relates to an encoding device, an encoding method, and a program capable of improving audio quality and more efficiently encoding audio. A first high-frequency encoding circuit encodes a high-frequency range based on a low-frequency subband signal and a high-frequency subband signal and obtains a high-frequency code amount. A low-frequency encoding circuit encodes a low-frequency signal with a code amount determined by the high-frequency code amount and a low-frequency decoding circuit decodes the encoded low-frequency signal. A subband dividing circuit divides a decoded low-frequency signal obtained by decoding into decoded low-frequency subband signals of a plurality of subbands and a second high-frequency encoding circuit generates a high-frequency code string such that a code amount of the high-frequency code string for obtaining a high-frequency component is not larger than the high-frequency code amount based on the decoded low-frequency subband signals and the high-frequency subband signals. The present invention is applicable to the encoding device.
US09437193B2	Environment adjusted speaker identification Computerized estimation of an identity of a user of a computing system. The system estimates environment-specific alterations of a received user sound that is received at the computing system. The system estimates whether the received user sounds is from a particular user by use of a corresponding user-dependent audio model. The user-dependent audio model may be stored in a multi-system store accessible such that the method may be performed for a given user across multiple systems and on a system that the user has never before trained to recognize the user. This reduces or even eliminates the need for a user to train a system to recognize the voice of a user, and allows multiple systems to take advantage of previous training performed by the user.
US09437192B2	Method and device of matching speech input to text A method and device for matching speech to text are disclosed, the method including: receiving a speech input, the mentioned speech input carrying input speech information; obtaining initial text corresponding to the input speech information, and respective pinyin of the initial text; generating at least one approximate pinyin for the initial text based on predetermined pronunciation similarity information; and from a preset mapping relationship table, obtaining additional text corresponding to the respective pinyin of the initial text or to the at least one approximate pinyin of the initial text, wherein the preset mapping relationship table includes a respective record for each word in a word database, including respective pinyin and at least one respective approximate pinyin for said each word, and a respective mapping relation between said respective pinyin, said at least one respective approximate pinyin, and said each word.
US09437187B2	Voice search device, voice search method, and non-transitory recording medium A search string acquiring unit acquires a search string. A converting unit converts the search string into a phoneme sequence. A time length deriving unit derives the spoken time length of the voice corresponding to the search string. A zone designating unit designates a likelihood acquisition zone in a target voice signal. A likelihood acquiring device acquires a likelihood indicating how likely the likelihood acquisition interval is an interval in which voice corresponding to the search string is spoken. A repeating unit changes the likelihood acquisition zone designated by the zone designating unit, and repeats the process of the zone designating unit and the likelihood acquiring device. An identifying unit identifies, from the target voice signal, estimated intervals for which the voice corresponding to the search string is estimated to be spoken, on the basis of the likelihoods acquired for each of the likelihood acquisition zones.
US09437186B1	Enhanced endpoint detection for speech recognition Determining the end of an utterance for purposes of automatic speech recognition (ASR) may be improved with a system that provides early results and/or incorporates semantic tagging. Early ASR results of an incoming utterance may be prepared based at least in part on an estimated endpoint and processed by a natural language understanding (NLU) process while final results, based at least in part on a final endpoint, are determined. If the early results match the final results, the early NLU results are already prepared for early execution. The endpoint may also be determined based at least in part on the content of the utterance, as represented by semantic tagging output from ASR processing. If the tagging indicate completion of a logical statement, an endpoint may be declared, or a threshold for silent frames prior to declaring an endpoint may be adjusted.
US09437184B1	Elemental artificial cell for acoustic lens A cell for manipulating an acoustic wave includes a plurality of spokes radiating from a hub and a plurality of concentrically arranged leaves. Each leaf is supported by at least one spoke and is formed by a plurality of circumferentially distributed fingers. Each finger is connected to at least one spoke.
US09437183B2	Metamaterial based acoustic lenses for structural health monitoring An embedded acoustic metamaterial lenses allows for ultrasonic beam-forming and high resolution identification of acoustic sources for structural health monitoring. The lenses design provides an alternative to conventional phased-array technology enabling the formation of steerable and collimated (or focused) ultrasonic beams by exploiting a single transducer. The ultrasonic beam can be steered by simply tuning the frequency of the excitation. Also, the embedded lens can be designed to achieve sub-wavelength resolution to clustered acoustic sources which is a typical scenario encountered in incipient structural damage.
US09437180B2	Adaptive noise reduction using level cues A system utilizing two pairs of microphones for noise suppression. Primary and secondary microphones may be positioned closely spaced to each other to provide acoustic signals used to achieve noise cancellation/suppression. An additional, tertiary microphone may be spaced with respect to either the primary microphone or the secondary microphone in a spread-microphone configuration for deriving level cues from audio signals provided by the tertiary and the primary or secondary microphone. The level cues are expressed via a level difference used to determine one or more cluster tracking control signal(s). The level difference-based cluster tracking signals are used to control adaptation of noise suppression. A noise cancelled primary acoustic signal and level difference-based cluster tracking control signals are used during post filtering to adaptively generate a mask to be applied to a speech estimate signal.
US09437179B2	Reverberation suppression device A reverberation suppression device comprises: an echo canceller that removes an echo component included in an input signal; a howling suppressor that detects occurrence of howling based on a frequency characteristic of the input signal from which the echo component has been removed and attenuates a frequency level of a component of the detected howling; and an initial sound suppressor that detects a sound section of the input signal in which the frequency level of the howling component has been attenuated and suppresses a signal value at a sound start portion of the detected sound section.
US09437171B2	Local tone mapping for high dynamic range images A method of local tone mapping of a high dynamic range (HDR) image is provided that includes dividing a luminance image of the HDR image into overlapping blocks and computing a local tone curve for each block, computing a tone mapped value for each pixel of the luminance image as a weighted sum of values computed by applying local tone curves of neighboring blocks to the pixel value, computing a gain for each pixel as a ratio of the tone mapped value to the value of the pixel, and applying the gains to corresponding pixels in the HDR image. A weight for each value is computed based on distance from the pixel to the center point of the block having the local tone curve applied to compute the value and the intensity difference between the value of the pixel and the block mean pixel value.
US09437170B1	Systems and methods for augmented reality display Systems and methods for generating Augmented Reality displays including obtaining a location and an orientation of an electronic device. Geolocation responsive to the location and the orientation of the electronic device and a distance may be obtained. Physical phenomena information of the geolocation may be obtained. The physical phenomena information may be displayed overlaying a view of a physical environment on a display of the electronic device.
US09437163B2	Methods and apparatuses for increasing the apparent brightness of a display to synchronize at least two monitors Methods and apparatuses to varying the apparent brightness of a display are described. The change in apparent brightness is accompanied by unchanged in relative contrast, rendering a display with higher or lower brightness while maintaining contrast fidelity. In exemplary embodiments, the signals for the middle tone levels are adjusted to increase or decrease the brightness intensity, while keeping constant the gamma correction. This maintains the relative contrast of images while rendering them at a different brightness. Implementations of the present process include an adjusted gamma correction lookup table, incorporated in the video card to modify the video signal before reaching the display. The present invention can be used for matching the brightness of two or more displays or to provide compensation for variations in display characteristics to ensure consistency in display brightness within a data processing model.
US09437160B2	System and method for automatic color matching in a multi display system using sensor feedback control A system for automatic color matching of multiple displays in a multi-display system. A sensor observes the output energy of each of the displays in a multi-display system and measures the difference in the color responses for a given input color. This difference is used to derive a modification function that is applied to each display. The displays are modified accordingly, and then the color is displayed again. This process is repeated until the measured values from each of the displays are within a minimum measurement error tolerance, so that the differences in displayed colors observed among the displays are minimized.
US09437157B2	Image processing apparatus and image processing method A display system including a communication unit to receive streamed data from a mobile terminal located within the vehicle; a first display unit operatively connected to the communication unit and installed in a first location in the vehicle, the first display unit to display the streamed data; and a second display unit operatively connected to the communication unit and installed in a second location in the vehicle different than the first location, the second display unit to display the streamed data. Further, the first display unit interrupts the display of the streamed data by the first display unit while the mobile terminal processes an incoming or outgoing call, and the second display unit continues to display the streamed data while the mobile terminal processes the incoming or outgoing call.
US09437153B2	Liquid crystal display device According to one embodiment, a liquid crystal display device includes pixel electrodes arranged in matrix, gate lines, source lines, pixel switches, gate drivers allocated at both ends of a display region, a source driver, image signal transmit lines arranged along the columns in which the pixel electrodes are arranged, each image signal transmit line supplying an image signal to each source line, switches arranged along the row direction, each switch configured to switch a connection between the source line and the image signal transmit line, and control lines configured to output source control signals to switch the switches, each control line outputting a source control signal to switch a plurality of the switches at the same time, wherein each source control signal is input to each control line at a position substantially the center of the gate line in the row direction.
US09437150B2	Liquid crystal display (LCD) device A LCD device includes pixels formed of column data lines and row scanning lines. The pixel includes a display element; a first switching unit that performs sampling on each frame data of an input video signal; a first holding unit that configures an SRAM, and holds sub frame data; a second switching unit that causes the sub frame data held in the first holding unit; and a second holding unit that configures a DRAM, and applies output data to the pixel electrode, a pixel control unit that performs an operation of repeating writing the sub frame data in the first holding unit, turning on the second switching units, and rewriting memory content of the second holding units; and a timing control unit. A delay of a certain period of time is sequentially given to a timing at which the pixel control unit turns on the second switching unit.
US09437145B2	Gamma reference voltage generating circuit, method for measuring voltage-transmission curve and display device The present disclosure provides a gamma reference voltage generating circuit including a center voltage generation unit, a gamma reference voltage generation unit configured to generate positive and negative gamma reference voltages and control the positive gamma reference voltage and the negative gamma reference voltage to be symmetrical with respect to the center voltage; a first voltage divider unit including a first terminal for receiving the positive gamma reference voltage and a second terminal for receiving the center voltage; and a second voltage divider unit including a first terminal coupled with the second terminal of the first voltage divider unit and a second terminal for receiving the negative gamma reference voltage.
US09437142B2	Pixel circuit and display apparatus A pixel circuit, comprises two sub-pixel circuits (P1, P2) and a sixth switch unit (T6); a first terminal of the sixth switch unit (T6) is connected to an operating voltage line (Vdd), and a control terminal of the sixth switch unit is connected to a first scan signal line (Em); each of the sub-pixel circuits (P1, P2) comprises five switch units (T1, T2, T3, T4, T5), a driving unit (DT), a energy storage unit (C) and an electroluminescent unit (L), a first switch unit (T1) and a fourth switch unit (T4) in a first sub-pixel circuit (P1) share a scan signal line (Scan[3]) with a first switch unit (T1′) and a fourth switch unit (T4′) in a second sub-pixel circuit (P2), and a third switch unit (T3) in the first sub-pixel circuit (P1) share a scan signal line (Scan[2]) with a third switch unit (T3′) in the second sub-pixel circuit (P2). The pixel circuit completely solves the problem of non-uniformity in the display brightness due to drifting of the threshold voltage of the driving transistor. Meanwhile, one compensation circuit is used to drive two pixels, and two adjacent pixels share multiple signal lines, which can reduce the number of signal lines for the pixel circuit in a display apparatus, lower the cost of the integration circuit, decrease the pixel pitch, and increase the pixel density.
US09437141B2	Scan driver, light emitting driver, and driving method thereof A scan driver includes: a plurality of scan driving blocks including an output terminal outputting a scan signal to a scan line; a first transistor transmitting a voltage of a power source to the output terminal; a second transistor transmitting a clock signal to the output terminal; and a third transistor including a gate electrode connected to a node formed with a gate-on voltage turning on the second transistor, one terminal connected to the power source, and the other terminal connected to the gate electrode of the first transistor. The scan driver may reduce the influence of a leakage current even though application of the scan signal is increased, and a scan signal of a uniform voltage level may be output.
US09437138B2	Display device The rate of reading from a memory for storing display irregularity correction data is lowered. At the time of display, calculation is carried out in a correction calculation section using an input signal and correction data in one or more memory units, and brightness inconsistency correction is carried out. The way in which correction calculation is carried out in the correction calculation section is changed for every frame.
US09437136B2	Light-emitting display apparatus and driving method thereof A pixel includes five transistors and a capacitor. A first transistor controls current to be supplied to a light-emitting element. A second transistor is connected between a gate electrode of the first transistor and a first power supply. A third transistor is connected between the gate electrode of the first transistor and a second terminal of the first transistor. The capacitor is coupled between the third transistor and the second terminal of the first transistor. The fourth transistor is connected between the second terminal of the first transistor and a second power supply. The fifth transistor is connected between the second terminal of the third transistor and a signal line. The capacitor may be the only capacitor in the pixel, and the signal line may receive an initialization voltage and a gray scale data voltage.
US09437132B2	Devices and methods for providing access to internal component Systems, methods, and devices are disclosed for applying concealment of components of an electronic device. In one embodiment, an electronic device may include a component that is disposed behind a display (e.g., a transparent organic light-emitting diode (OLED) display) that is configured to selectively become transparent at certain transparency regions. Additionally, the electronic device includes data processing circuitry configured to determine when an event requesting that the component be exposed occurs. The data processing circuitry may control portions of the display to become transparent, to expose the component upon the occurrence of the event requesting that the component be exposed.
US09437126B2	Test apparatus of display, method and computer readable medium A test apparatus for a display includes an interface transmitting characteristic information including a resolution of the display unit and each equivalent model of a plurality of pixels, a reference voltage model including a plurality of reference voltages respectively corresponding to a plurality of pixels included in a unit region of the display unit, and pixel information including a position of a plurality of pixels to be tested among a plurality of pixels, a pixel model generator that schematizes a plurality of pixels into a plurality of test pixels and at least one equivalent load pixel according to the characteristic information and the pixel information to generate a pixel model, and a voltage mapper that maps the reference voltage model to the pixel model to calculate test voltages respectively corresponding to a plurality of test pixels and the equivalent load pixel.
US09437124B1	Flying decoration A flying decoration includes a drive unit, at least one object mount, a transport line and an idler pulley device. The drive unit includes a drive motor, a system controller and a speed sensor. The drive unit is retained above the ground in one location and the idler pulley device is retained above the ground in another location. A drive pulley is mounted to a drive shaft of the drive motor. The system controller controls the rotation of the drive shaft. Both ends of the transport line are secured to the object mount to form a transport loop. The system controller includes an automatic travel distance calibration program. The object mount includes a line tensioning device for reducing slack in the transport loop. One end of the transport loop is retained on the drive pulley and the other end is retained on an idler pulley of the idler pulley device.
US09437122B2	Paper, labels made therefrom and methods of making paper and labels Paper is disclosed for use in making repositionable or removable adhesive labels. The adhesive can be applied in patches or discrete areas to the paper or to a layer of material that cleans rollers in the manufacturing line and/or in printers. The adhesive can be applied in single or multiple layers. The paper is light weight paper and preferably thermal paper for use in POS printers.
US09437117B2	Birthing simulation devices, systems, and methods Devices, systems, and methods appropriate for use in medical training are disclosed. In some instances, a patient simulator system is provided that includes a maternal patient simulator and a fetal patient simulator. The maternal patient simulator includes an internal chamber sized to receive the fetal patient simulator and a birthing mechanism disposed within the internal chamber configured to translate and rotate the fetal patient simulator with respect to the maternal patient simulator to simulate a birth. In some instances, the fetal patient simulator an internal support structure that includes a head, spinal components, left arm components, right arm components, left leg components, and right leg components with a continuous silicon skin layer covering the internal support structure.
US09437112B1	Depiction of relative motion of air traffic via an air traffic display Techniques are described that allow an air traffic display of an aircraft to display the relative motion of air traffic proximate to the aircraft. The air traffic display may be switched between a first display mode in which absolute motion of air traffic is displayed (e.g., motion of air traffic targets relative to a fixed point on the earth's surface or relative to an apparently fixed celestial point is displayed) and a second display mode in which motion of air traffic targets is displayed relative to the aircraft. The techniques further facilitate the selection of individual traffic targets from a displayed traffic depiction to activate a third display mode in which additional information about the relative motion of the selected target, such as its estimated closest point of approach (CPA) to the aircraft and the estimated time it will take the selected target to reach the CPA are shown.
US09437106B2	Techniques for controlling appliances Remote control systems utilize touch-sensitive user-input devices and/or displays which may be integral with the touch-sensitive user-input devices. Gestures input into a touch-sensitive user-input device result in signals transmitted to one or more appliances for the purpose of controlling the one or more appliances. A display provides intuitive visual feedback regarding input into the remote control system, through a touch-sensitive user-input device and/or other user-input devices. The remote control systems may be configured and dynamically updated based on user activity in connection with the remote control systems.
US09437105B2	System and method for optimized appliance control A device receives a request from a controlling device, such as a remote control, smart phone, or the like, where the request is intended to have one or more target devices perform one or more functional operations. The device responds to the request by applying the optimum methodology to propagate one or more commands to each intended target appliance to cause each intended target appliance to perform the intended one or more functional operations.
US09437104B2	System and method for configuring the remote control functionality of a portable device A server device receives identity data retrieved from an appliance through use of a physical and logical interconnection referenced to a standard. The identity data is used at the server device to identify within a database having a plurality of appliance records, each of which is cross-referenced to an appliance, an appliance record having data in one or more record fields which matches the identity data retrieved from the appliance. A codeset identifier associated with the identified appliance record is then used to select from a plurality of codesets a codeset for use in configuring the portable device to command functional operations of the appliance.
US09437103B2	Dispenser and contaminant sensor A fluid dispenser including a contaminant sensor and methods of use of such a fluid dispenser to monitor contaminants either alone or in an array of similar dispensers within a facility.
US09437102B2	System and method for configuring the remote control functionality of a portable device A system and method used to configure a smart device to command functional operations of a target appliance. The smart device retrieves from a controllable appliance, such as a settop box, data indicative of a codeset identity of the target appliance wherein the codeset identity was determined during a process used to configure a conventional universal remote control to command functional operations of the target appliance and wherein the process used to configure the conventional universal remote control is performed in cooperation with the controllable appliance. A remote control application resident on the smart device then uses the data indicative of the codeset identity retrieved from the controllable appliance to also configure the smart device to command functional operations of the target appliance.
US09437101B2	System, transmitting device, receiving device, and method for the wireless control of an RC model A system for the wireless control of an RC model, comprising a transmitting device separate from the RC model, a multifunctional device in the RC model, and a receiver model in the RC model. The transmitting device comprises a first transmitter for transmitting information via digital radio communication to the RC model, and a second receiver adapted to receive second information via digital radio communication from the RC model. The multifunctional device comprises or is connected to one or more electronic accessory modules. The receiver module is connected to or integrated with the multifunctional device, and comprises a first receiver configured to receive the first information and a second transmitter configured to transmit the second information. A method for using the system, a transmitting device suitable for use with the system, and a receiving device suitable for use with the system are also claimed.
US09437100B2	Supervising alarm notification devices In an example implementation, a system includes a control module, one or more electric circuits, each electric circuit including a resistor and one or more notification devices in parallel, and a supervisor module electrically coupled to the control module and the electric circuits. The supervisor module is configured to receive input electric power, the input electric power having a voltage in a range of 12 to 16 VDC, and apply, to each electric circuit, first electric power having a first polarity and a voltage of approximately 12 VDC. The supervisor module is also configured to determine, based on electric power returning from each electric circuit, an operational state of each respective electric circuit, and receive, from the control module, a trigger signal indicative of an alarm event. The supervisor module is also configured to, responsive to receiving the trigger signal, apply, to at least one electric circuit, second electric power having a second polarity opposite the first polarity and a voltage of approximately 12 VDC.
US09437099B2	Detecting presence using a presence sensor network Concepts and technologies are disclosed herein for detecting presence using a presence sensor network. In some embodiments, a computer executing a presence service generates a user interface for display at a user device. The user interface can include a control that, when selected, generates room data defining a monitored location. The computer can obtain sensor identifier data that identifies a presence sensor located at the monitored location and a location of the presence sensor at the monitored location. The computer can provide the user interface to the user device to obtain the room data and obtain the room data. The computer also can store the room data and the sensor identifier data.
US09437097B2	Systems and methods for using robots to monitor environmental conditions in an environment Methods and devices are disclosed for monitoring environmental conditions in one or more environments. In one embodiment, the method includes maintaining a plurality of environmental-condition thresholds, each of which corresponds to an environmental condition and is predetermined based on data corresponding to the environmental condition that is received from a plurality of robots. The method further includes receiving from a first robot first data corresponding to a first environmental condition in a first environment. The method may still further include making a first comparison of the first data and a first environmental-condition threshold corresponding to the first environmental condition and, based on the first comparison, triggering a notification. Triggering the notification may comprise transmitting to the robot instructions to transmit the notification to at least one of a call center and a remote device.
US09437093B2	Differential current measurements to determine ION current in the presence of leakage current An ion chamber provides a current representative of its characteristics as affected by external conditions, e.g., clean air or smoke. A direct current (DC) voltage is applied to the ion chamber at a first polarity and the resulting current through the ion chamber and parasitic leakage current is measured at the first polarity, then the DC voltage is applied to the ion chamber at a second polarity opposite the first polarity, and the resulting current through the ion chamber and parasitic leakage current is measured at the second polarity. Since substantially no current flows through the ion chamber at the second polarity, the common mode parasitic leakage current contribution may be removed from the total current measurement by subtracting the current measured at the second polarity from the current measured at the first polarity, resulting in just the current through the ion chamber.
US09437091B2	Smart alarm object proximity system using motion detection signal adjustment An object proximity alert system using motion detection having a smart alarm component for receiving a proximity signal from an associated object monitor component. The object monitor includes within its housing a motion detector that monitors the state of motion of the object monitor, and at least one operating instruction that adjusts a property of the transmitted proximity signal in response to a change in the object monitor's motion state. The smart alarm sets off a perceptible alarm through one or more sensory alert mechanisms when the separation distance between the smart charm and object monitor is determined to exceed a threshold alert criterion.
US09437089B2	Monitoring camera and monitoring camera control method An image signal processing DSP subjects an image captured by an imaging element having a zoom lens to image processing for identifying a tracking target. In accordance with zoom information generated by the image signal processing DSP, the main CPU controls the zoom lens and controls a turn table that moves the imaging element in panning and tilting directions in accordance with pan and tilt information, to track the tracking target. During tracking of the tracking target, a determination is made, from information about movements of the tracking target generated by the image signal processing DSP, as to whether or not the target to be tracked has intruded the inside of the area from the outside. In a case where the target has intruded the inside of a preset area from the outside, an alarm command is produced when the target continually remains in the area for; e.g., one second.
US09437087B2	Method and system for haptic data encoding and streaming using a multiplexed data stream A method includes receiving digital content data including audio data and/or video data, generating haptic data using at least some of the received digital content data, encoding the haptic data for efficient transmission over a communication network, multiplexing the encoded haptic data with the received digital content data, embedding information for decoding the encoded haptic data in metadata of the multiplexed data stream, and sending the multiplexed data stream over the communication network. The method may include analyzing the haptic data to determine at least one characteristic of the haptic data, and the encoding the haptic data may include encoding, based on the determined characteristic, the haptic data to meet a pre-defined criteria.
US09437085B1	In-basket digital donation system An integrated electronic donation acceptance device and money collection basket. The money collection basket is portable. The electronic donation acceptance device includes a housing and circuitry that is capable of receiving electronic payments. At least a portion of the housing of the electronic donation acceptance device is releasably couplable to the money collection basket.
US09437084B2	Gaming system and method for providing a cascading symbol game including a plurality of independent reels which provide a stacked symbol functionality A gaming system displays a plurality of independent reels, wherein each independent reel generates a symbol from a plurality of symbol positions of that independent reel in accordance with a plurality of probabilities. At least two adjacent independent reels generate symbols according to relatively high probabilities of generating a designated symbol. For a play of the game, the gaming system generates and displays a symbol for each independent reel and provides an award for any displayed winning symbol combinations. In one embodiment, for at least one symbol position of at least one winning symbol combination, the gaming system re-generates a symbol for one or more independent, such as by displaying a symbol from an adjacent symbol position of that independent reel. The gaming system provides an award for any winning symbol combinations and repeats until no winning symbol combinations are displayed.
US09437083B2	Computer gaming device and method for computer gaming A system for computer gaming includes a processor configured to provide a first table of a first group of players grouped together to play a first hand and provide to each of the first group of players one or more cards for the first hand. The system includes an interface couple to the processor and configured to receive from a first player of the first group of players a request to fold the one or more cards of the first player. The processor is also configured to automatically move the first player to a second table of a second group of players grouped together to play a second hand.
US09437079B2	Rotor-based gaming device having a secondary award system A game system including a plurality of symbols, a rotor and an award amount. The plurality of symbols include at least one secondary award group of the symbols. A wager is placeable on the secondary award group. The rotor displays the symbols and a plurality of ball landings adjacent to the symbols. A plurality of the symbols are indicatable after multiple spins of the rotor. The game system is operable to provide a secondary award based on the indication of one or more symbols within the secondary award group.
US09437071B2	Wide screen gaming apparatus A gaming apparatus includes a display unit and has a display support structure that extends substantially vertically from a horizontal support base. The display unit includes a flat-panel display screen having a width (W) and a height (H) wherein W/His at least 16/10. The display unit is rotatable about a horizontal axis located in a plane substantially parallel to the display screen wherein, a player's angle of viewing the display unit may be adjusted by vertical translation of the display unit on the display support structure, over a vertical range of motion, and by rotation of the display unit about the horizontal axis. A front face of the display structure presents, in a region proximate to the vertical range of motion, a concave side of a curved surface.
US09437060B2	Initiating remote control using near field communications A system in which a portable electronic device communicates with a keypad including a near field communication (NFC) tag in order to establish remote control of a controllable residential device over a home automation network. Upon placing the portable electronic device near the keypad, a control application running on the portable electronic device is launched and a graphical representation of the keypad is displayed on the portable electronic device. The portable electronic device then provides remote control of the controllable residential device over the home automation network. The portable electronic device may additionally provide expanded control options for the controllable residential device.
US09437054B2	Method for predicting an auxiliary power unit fault A method of predicting an auxiliary power unit fault in an aircraft having an auxiliary power unit and multiple sensors related to the auxiliary power unit, components thereof, and systems related thereto, including receiving a sensor signal from at least one of the multiple sensors to define a sensor output, comparing the sensor output to a reference value and predicting a fault in the auxiliary power unit based on the comparison.
US09437049B2	Ticket dispenser A ticket dispenser comprising a housing body, a lockable housing door configured to close an opening in the housing body, a ticket dispensing aperture, a lockable security cover configured to prevent the removal of tickets through the aperture, and a lock assembly, wherein the lock assembly is configured to lock the housing door and security cover when in a first orientation, wherein the lock assembly is configured to lock the housing door and not to lock the security cover when in a second orientation, and wherein the lock assembly is configured not to lock the housing door or the security cover when in a third orientation.
US09437048B2	Searching method for plane area of 3D model A method for searching plane area on a 3D model comprises following steps of: obtaining an outline of the 3D model; setting a lowest point of the outline based on a datum axis to be a locate point; extending from the locate point along another two axes to search all coordinate points within the outline at a substantially height on the datum axis with the locate point; reserving of the information of the continual coordinate points which can constitute a plane area; recording the plane area; amending value on the datum axis to add fixed variable of the locate point; executing above steps repeatedly until the locate point is amended to be the highest point of the outline based on datum axis. The present disclosure can actually search for all plane area on the outline of the 3D model, so as to help the combination with other 3D models.
US09437047B2	Method, electronic apparatus, and computer-readable medium for retrieving map The invention discloses a method, an electronic apparatus, and a computer readable medium for retrieving a map. The method includes the following steps. Firstly, a picture of a printed map is obtained. A block area surrounded by a road outline in the picture is defined. A map service is queried to find an electronic map having a map area corresponding to the block area according to contents of the printed map. A plurality of 3-D models of a plurality of buildings located in the map area is retrieved. The 3-D models are mapped on the picture.
US09437046B2	Anchors for location-based navigation and augmented reality applications A method for encoding information includes specifying a digital value and providing a symbol (28, 70, 80, 90, 100) comprising a plurality of polygons (72, 82, 92, 94, 102) meeting at a common vertex (74, 84, 96, 98, 104) and having different, respective colors selected so as to encode the specified digital value.
US09437045B2	Real-time mobile capture and application of photographic images as textures in three-dimensional models A computer-implemented method for obtaining texture data for a three-dimensional model is disclosed. The method is performed at a portable electronic device including a camera, one or more processors, and memory storing one or more programs. The method includes obtaining an image of one or more objects with the camera. The method also includes concurrently displaying at least a portion of the image with one or more objects in the three-dimensional model. The one or more objects in the three-dimensional model at least partially overlay the one or more objects in the image. The method furthermore includes storing at least one or more portions of the image as texture data for one or more of the one or more objects in the image.
US09437041B2	3D laser ablation tomography A laser ablation tomography system includes a specimen stage for supporting a specimen. A specimen axis is defined such that a specimen disposed generally on the axis may be imaged. A laser system is operable to produce a laser sheet in a plane intersecting the specimen axis and generally perpendicular thereto. An imaging system is operable to image the area where the laser sheet intersects the specimen axis.
US09437038B1	Simulating three-dimensional views using depth relationships among planes of content Approaches enable image content (e.g., still or video content) to be displayed in such a way that the image content will appear, to a viewer, to include portions with different locations in physical space, with the relative positioning of those portions being determined at least in part upon a current relative position and/or orientation of the viewer with respect to the device, as well as changes in that relative position and/or orientation. For example, relationship pairs for image content capable of being displayed on a display screen can be determined. Based on the relationship pairs, a node hierarchy that includes position information for planes of content that include the image content can be determined. The position information can be to render a view of the image content based on the relative position, direction, and/or orientation between the viewer and device to provide a two- or three-dimensional representation of that image content that is appropriate for that viewing angle, giving the impression of a three-dimensional view or display even when the display is in two dimensions.
US09437037B2	Image display device, method and program In the present invention, when a 3D medical image is displayed on a 3D display, the position of accompanying information displayed at the same time is appropriately controlled. The position of the accompanying information in the coordinate system of a 3D signal value that is an item to be drawn is computed, and said position is saved in a storage unit. By integrating a 3D data area and an accompanying information area, a drawing process unit generates an output image to be displayed in a display unit, said 3D data area being drawn for an area specified by mask information that specifies an area to be drawn among an array of the 3D signal value that is the item to be drawn, and being drawn on the basis of information that specifies a drawing method for a 2D image based on the 3D signal value array, and said accompanying information area being drawn for the accompanying information, which is associated with the item to be drawn, and being drawn on the basis of position information for the accompanying information determined by a drawing control unit. The display unit displays the drawn output image.
US09437035B2	Light source detection from synthesized objects Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining a location relative to an object and a type of a light source that illuminated the object when the image was captured, are described. A method performed by a process executing on a computer system includes identifying an object of interest in a digital image. The method further includes projecting at least a portion of the digital image corresponding to the object of interest onto a three dimensional (3D) model that includes a polygon-mesh corresponding to the object's shape. The method further includes determining one or more properties of a light source that illuminated the object in the digital image at an instant that the image was captured based at least in part on a characteristic of one or more polygons in the 3D model onto which the digital image portion was projected.
US09437033B2	Generating 3D building models with ground level and orthogonal images A system and method is provided for generating textured 3D building models from ground-level and orthogonal imagery. Ground-level images for the sides of building objects are collected to form a 3D dense point cloud for identification of key architectural features, corresponding key façade geometry planes, and generation of a 3D building façade geometry. Orthogonal images are correlated to the 3D building model providing a properly geo-positioned, scaled and textured 3D building model.
US09437032B1	Server computing system for and method of providing cross-platform remote access to 3D graphics applications A server computing system in a client-server computing environment includes a virtual display driver that marshals and transmits graphics application programming interface (API) functions to a client via a network. The server may receive capability information from the client, allowing the virtual display driver to resolve differences between the APIs supported on the server and the client.
US09437021B2	Dynamic visualization for optimization processes Embodiments of the present invention include a method, computer program product, and system for generating a visualization of an optimized project. The computer receives a project and a period of interest associated with the project. The computer determines a constraint status for each constraint associated with the project. The computer generates a graphical element that illustrates the constraint status. The computer generates a visualization of the project during the period of interest, wherein the visualization includes concentric geometric structures and the graphical element.
US09437018B2	Method and apparatus for reducing artifacts in computed tomography image reconstruction The present invention provides a method and apparatus for reducing artifacts in CT image reconstruction. The method comprises obtaining an original reconstructed image and an original sinogram and determining a proportion of metal pixels in the original reconstructed image. If the proportion is greater than a first threshold value, then generating an expanded metal template based on the original reconstructed image, generating a metal-free, metal artifact reduced (MAR) image based on the expanded metal template and the original sinogram, and generating a final image based on the expanded metal template and the metal-free, MAR image. However, if the proportion of metal pixels is less than a second threshold value, then generating an expanded metal template based on the original reconstructed image, generating a metal-free, metal artifact reduced image based on a treatment, and generating a final image based on the expanded metal template and the metal-free, MAR image.
US09437012B2	Multiple-object tracking and team identification for game strategy analysis A method for automatically tracking multiple objects from a sequence of video images that may extract raw data about participating elements in a sporting, or other event, in a way that does not interfere with the actual participating elements in the event. The raw data may include the position and velocity of the players, the referees, and the puck, as well as the team affiliation of the players. These data may be collected in real time and may include accounting for players moving fast and unpredictably, colliding with and occluding each other, and getting in and out of the playing field. The video sequence, captured by a suitable sensor, may be processed by a suitably programmed general purpose computing device.
US09437006B2	Method and system for object reconstruction A system and method are presented for use in the object reconstruction. The system comprises an illuminating unit, and an imaging unit (see FIG. 1). The illuminating unit comprises a coherent light source and a generator of a random speckle pattern accommodated in the optical path of illuminating light propagating from the light source towards an object, thereby projecting onto the object a coherent random speckle pattern. The imaging unit is configured for detecting a light response of an illuminated region and generating image data. The image data is indicative of the object with the projected speckles pattern and thus indicative of a shift of the pattern in the image of the object relative to a reference image of said pattern. This enables real-time reconstruction of a three-dimensional map of the object.
US09437004B2	Surfacing notable changes occurring at locations over time An exemplary method for surfacing feature changes occurring over time at a location is provided. The method includes identifying sets of images captured at a location over a period of time. The sets of images depict objects at the location. Visual changes at the location over the period of time are determined for a given physical feature of the objects depicted in images from the sets of images based on at least a comparison of features in corresponding areas of a first and a second 3D geometry of the location associated with the images. The first and second 3D geometries depict physical features of objects at the location at different times. The sets of images may be ranked based on the determined visual changes for each set. A given set of images from the sets of images may be selected for display on a user interface based on the ranking.
US09437000B2	Odometry feature matching Methods and systems for determining features of interest for following within various frames of data received from multiple sensors of a device are disclosed. An example method may include receiving data from a plurality of sensors of a device. The method may also include determining, based on the data, motion data that is indicative of a movement of the device in an environment. The method may also include as the device moves in the environment, receiving image data from a camera of the device. The method may additionally include selecting, based at least in part on the motion data, features in the image data for feature-following. The method may further include estimating one or more of a position of the device or a velocity of the device in the environment as supported by the data from the plurality of sensors and feature-following of the selected features in the images.
US09436993B1	System and method for fused image based navigation with late marker placement Systems and methods for image guidance, which may include an image processing unit, cameras, and handheld real-time imaging components or handheld displays, wherein the cameras observe visual features on patients, tools, or other components, and wherein said features allow camera or object positions to be determined relative to secondary image data or a reference position, and wherein the image processing unit is configured to dynamically register observations with secondary image data, and to compute enhanced images based on combinations of one or more of secondary image data, positioning data, and real-time imaging data.
US09436992B2	Method of reconstituting cellular spectra useful for detecting cellular disorders Embodiments of the present disclosure provides improved methods for determining the presence of abnormalities in exfoliated cells. In one embodiment, the present disclosure provides methods for reconstructing cellular spectrum of a cell sample by creating a spectral map of the cellular sample, generating a binary mask of the spectral map, removing edge artifacts from each cell, and co-adding spectral data of each pixel corresponding to the cell to reconstruct the spectrum of each cell.
US09436990B2	Defect observation method and device therefor The present invention is detection of a defect signal which is small enough to be buried in a background noise, by a method that includes detecting a defect on a specimen which is detected by another inspection device by using a detection device equipped with an optical microscope, amending positional information of the defect, observing the defect by using an SEM, wherein the detecting the defect is carried out such that forming stationary waves on the specimen by irradiating the specimen with two illumination lights having the same wavelength from the opposite directions on the same incidence plane at the same incidence angle and cause the two illuminating light to interfere; removing scattered components generated by minute irregularities on the specimen surface by a spatial filter, detecting an image formed by the scattered light not removed by the spatial filter; and processing the detected image to detect the defect.
US09436989B2	System and method for rapid quantitative dynamic molecular imaging scans Methods and systems for controlled administration of a tracer and quantification of uptake of the tracer by a target organ are described. The method includes administering a tracer to a patient and imaging at least two regions of the patient's body that cannot be imaged simultaneously. An input function for the tracer can be determined by imaging a first region of the patient's body during selected times, and using an injector to administer the tracer in a manner that accurately estimates the input function when this first region is not being imaged. One or more additional regions of the body may then be imaged to create data that may be used to estimate the input function. One or more parameters may then be estimated from each additional region of the body based on the input function and the imaging data gathered from each region.
US09436983B2	Systems and methods for non-linear processing of image frames Embodiments of the present disclosure include systems and methods for image processing for enhancing, e.g., photos, videos, and graphics representations. Particularly, some embodiments perform a histogram-based SMQT decomposition of various attributes in an original image. The SMQT decomposition of these attributes may then be used to create a look-up-table indicating how to modify pixel attributes in the same or a subsequent image so as to enhance the same or subsequent image. The results of the SMQT decomposition for each attribute may be interpolated based, e.g., on user preferences, to achieve a more optimal enhancement.
US09436982B1	Scalable rank filter A scalable rank filter and method for performing rank filtering are disclosed. In one embodiment, the rank filter comprises a W staged pipeline with W stages to receive N input data samples and operable to generate an output based on the N input data samples as a result of the W stages completing execution, where W is a bit length of the inputs and W and N are integers greater than two; and output logic coupled to the W staged pipeline to determine the output prior to all W stages completing execution and to output the median.
US09436981B2	Dictionary creation device, image processing device, image processing system, dictionary creation method, image processing method, and program A dictionary creation device including a blurred image generation unit which outputs a blurred image generated by performing a blurring process to a learning image together with a blur parameter indicating a blurring state of the blurred image, a patch pair generation unit which generates a restoration patch and a blurred patch as a patch pair that is composed of the patches located at the corresponding positions of the learning image and the blurred image, and a registration unit which associates the patch pair with a blur parameter corresponding to the blurred patch in the patch pair and registers them in a dictionary.
US09436975B2	Method and apparatus for performing interpolation based on transform and inverse transform Provided are a method and apparatus for interpolating an image. The method includes: selecting a first filter, from among a plurality of different filters, for interpolating between pixel values of integer pixel units, according to an interpolation location; and generating at least one pixel value of at least one fractional pixel unit by interpolating between the pixel values of the integer pixel units by using the selected first filter.
US09436974B2	Method and apparatus to recover scene data using re-sampling compressive sensing Methods, computer program products, and computer systems for recovering data of scene are provided. The techniques include: obtaining, by at least one processor, data of a scene; re-sampling, by the at least one processor, the data of the scene to obtain re-sampled sensing data of the scene and a corresponding sensing matrix; and constructing, by the at least one processor, recovered data of the scene using the re-sampled sensing data of the scene and the corresponding sensing matrix. In one embodiment, the method includes enhancing occluded data of the scene to construct the recovered data of the scene, where the recovered data of the scene facilitates identification of the scene. In another embodiment, the method includes compressing original data of a scene, the compressing including sampling the original data of the scene to select the data of the scene.
US09436967B2	System for providing extensible location-based services A system for providing location-based services to a mobile device regularly determines the location of the mobile device. Using the location of the device, the system queries a database of virtual geographic regions to determine if the location of the mobile device falls within one or more of the virtual geographic regions. The virtual geographic regions correspond to service entities that have purchased, rented, leased, or otherwise acquired the virtual geographic regions. The virtual geographic regions cover a certain area of a map. If the mobile device is within a virtual geographic region, the system notifies the mobile device. A location-based services application installed on the mobile device launches an applet for the entity that acquired the virtual geographic region within which the mobile device is located. When the mobile device is located within multiple overlapping virtual geographic regions, the system generates a prioritization scheme that defines which of the corresponding service entities should be displayed on the mobile device, and in what order the service entities should be displayed.
US09436966B2	Universal social messaging A method and system for universal social messaging is disclosed where an event is detecting on a host device by the electronic social messaging platform, an option associated with the event is selected by the electronic social messaging platform, and the option associated with the event is provided to the user of the host device by the electronic social messaging platform.
US09436962B2	Internet radio and broadcast method personalized by genre Data streams are generally selected according to user preferences and transmitted to the user in general alignment with expressed preferences of the user. Such data streams may be music, including music videos. Users may indicate their general or specific preferences with regards to song, artists, or albums. Any other aspects or factors that might affect the user's preferences can be taken into account. A playlist is created that combines all of these factors. The playlist then serves as the basis for feeding the data streams to the user. Each user is able to express his or her own preferences and receive music corresponding to those preferences on an on-going basis.
US09436959B2	Individual product identification system, individual product identification method, and device and program used by same The present invention is an individual product identification method, comprising: previously storing epidermal pattern images in a predetermined scope with a predetermined location of a registered product taken as a reference; imaging the epidermal pattern in the predetermined scope with the predetermined location of the product, being a target of individual product identification, taken as a reference; correcting the imaged epidermal pattern image of the product, being a target of individual product identification to an image for collation with the registered product with the predetermined location of the product taken as a reference: and collating an image characteristic of the epidermal pattern image of the registered product with the image characteristic of the corrected epidermal pattern image, and identifying whether the product, being a target of individual product identification, is one of the registered products.
US09436954B2	Modified queue list generation A queuing method and system. The method includes retrieving by a computer processor of a stationary computing system or a computing device, queue data placing an individual onto an initial queue list for receiving a service and ID data identifying the individual. The computer processor presents a status of the individual with respect to the queue list. The computer processor receives a request associated with the service and in response presents options for the individual. The computer processor receives a selection for an option and generates a modified queue list.
US09436949B1	Evaluating geographically grouped data sets Geographically grouped data sets may be evaluated in order to determine an ROI for different assets. The ROI of an asset may be determined based on one or more accounting items, or on an expense percentage for the asset. The value for each accounting item and the value for the expense percentage may vary depending on the geographic location of the asset. The geographically grouped data sets may be received from a variety of sources, including proprietary databases, user inputs, and third party resources. Results from evaluating the geographically grouped data sets may be used to supplement and/or refine the existing data stored in the proprietary database. A subset of the available data may be used to generate an initial ROI for one or more assets. Initial ROIs may be used to filter and identify assets for more in depth, refined, or resource-intensive analysis.
US09436948B2	Power aggregation system for distributed electric resources Systems and methods are described for a power aggregation system. In one implementation, a method includes establishing a communication connection with each of multiple electric resources connected to a power grid, receiving an energy generation signal from a power grid operator, and controlling a number of the electric resources being charged by the power grid as a function of the energy generation signal.
US09436942B2	Flexible mobile gift cards Devices, systems and methods are disclosed which relate to allowing a recipient of a closed-loop gift card to select one of a number of merchants toward which to apply the value. A consumer buys a variable gift card from a service provider for a set amount, pays the service provider that amount, and the service provider holds that amount in escrow. The consumer sends the gift card to a recipient with a predetermined merchant. The recipient receives the gift card and decides to switch the gift card from the predetermined merchant to a desired merchant. The recipient requests the service provider to change the merchant, and the service provider delivers the amount from escrow to the desired merchant. If the recipient does desire to use the predetermined merchant, the recipient contacts the service provider for activation and the service provider transfers the amount to the predetermined merchant.
US09436938B1	Transaction payment processing by multiple data centers A payment service is configured to support purchase transactions generated by merchant point-of-sale (POS) devices, wherein each purchase transaction may comprise multiple transaction requests such as authorization requests and capture requests. Each transaction request may be sent to a different one of multiple data centers of the payment service. Upon successfully receiving an acknowledgement from one of the data centers for a transaction request, the POS device designates that data center as the primary data center. Subsequently, all transaction requests for that transaction identify the primary data center, even when the transaction requests are sent to other data centers. At the payment service, the data centers synchronize requests such that the primary data center is informed of all authorizations and is made responsible for performing the capture of the transaction. This allows the primary data center to detect duplicate authorizations and to prevent duplicate captures.
US09436937B1	Highlight-based bill processing Document processing utilizing extraneous highlight added to the document. Sections or fields of a document including data utilized for document processing are marked or highlighted for processing. For example, a paper or printed document may be manually highlighted by a highlighter pen, or the highlight may be computer generated. An image of the highlighted bill is acquired. Highlighted sections within the image are identified, and bill data within the highlighted fields is extracted and utilized for bill processing.
US09436934B2	Techniques for visual integration of meeting space in calendar systems Techniques for visual integration of meeting spaces within a calendar system are presented. A meeting room can be viewed via a map and selected for scheduling a meeting. The map depicts the location of the meeting room within a facility of an enterprise. A meeting scheduler visually sees the meeting room within the map and can select the meeting room and acquire details about the meeting room.
US09436931B2	Remote prompting infrastructure The invention relates to a method and apparatus for sending and receiving prompts to end-users inside and outside the home. A prompt, for example, a message, image, or sound is presented to the end user in order to notify them of a health event, serve as a simple reminder, helps them through their daily activities. The invention includes, for example, the following components: a remote prompting client which runs on the end-user's home network and is typically associated with a physical display device. This entity has the ability to receive a prompt request from a remote prompting host, and display the prompt to the end-user; and a remote prompting host which runs on the end-user's home network and has the ability to scan the network and discover all existing remote prompting clients.
US09436929B2	Collaborative event playlist systems and methods Exemplary collaborative event playlist systems and methods are disclosed herein. An exemplary system includes a moderator device located at an event premises, connected to a local area network at the event premises, and hosting a collaborative event playlist for playback at an event at the event premises. The system further includes a participant device located at the event premises, connected to the local area network at the event premises, and configured to communicate with the moderator device by way of the local area network to participate in populating the collaborative event playlist with a song to which the participant device has access rights. Corresponding methods and systems are also disclosed.
US09436926B2	Entryway based authentication system A system can include at least one robot configured to autonomously navigate from a first location to a destination zone, the at least one robot having a generally cylindrical shape and including a storage container for storing at least one item for delivery, a plurality of image based depth sensor mounted proximate a top end of the robot, and a controller configured to navigate to the destination zone and to authenticate a delivery target for the item.
US09436925B2	Inventory management A device includes a code that is interpretable to identify a three-dimensional (3D) design specification by which a replacement for the device can be printed on a 3D printer.
US09436920B2	Method and apparatus for tracking and reporting social impact of food products Various embodiments of the present disclosure include methods and apparatus for tracking and reporting the social impact of food products. In an example embodiment, an apparatus comprises a hand-held device including a display and one or more input devices to sense product identification indicia associated with a food product that is grown or raised in an agricultural operation. The hand-held device includes at least one processor to determine a machine-readable identification code from the product identification indicia; send the identification code to at least one remote server; receive, from the at least one remote server, information that is associated with the product, the information including social impact information that is associated with the production of the food product; and display at least some of the received social impact information on the display in human readable form.
US09436916B2	Method for determining a correction characteristic curve A method for determining a correction characteristic curve for adapting a characteristic curve of an injection system, in which the correction characteristic curve includes at least one deviation of a measured characteristic curve from a setpoint characteristic curve, the at least one deviation including a sum tolerance of at least two components of the injection system, which have an effect on the characteristic curve.
US09436915B2	Medical decision making support apparatus and control method for the same A medical decision making support apparatus performs the inference processing of obtaining an inference result by performing inference processing associated with medical diagnosis based on a plurality of pieces of input medical information, and the calculation processing of calculating the degree of denial or affirmation of the inference result in association with each of a plurality of partial sets including each medical information extracted from the plurality of pieces of medical information as an element. The medical decision making support apparatus presents a user an inference result obtained by the inference processing and negative information indicating medical information included in a partial set, of the plurality of partial sets, for which the degree of denial is calculated by the calculation processing.
US09436913B2	Adaptive probabilistic computer-controlled method and system An adaptive probabilistic computer-controlled method and system determines computer-controlled actions that are expected to reduce uncertainties that are embodied as probabilities and then updates the probabilities in accordance with the results of the computer-controlled actions. The updated probabilities inform the determination of subsequent computer-controlled actions. Expected values of information may also be applied in determining the subsequent computer-controlled actions. The computer-controlled actions may comprise analysis of content and generating recommendations that are delivered to users, and inferences from the analysis of content and usage behaviors may inform the updating of the probabilities. Statistical learning functions and/or neural networks may be applied in determining the computer-controlled actions.
US09436910B2	Method, device and database for reconstructing intended activities from neural signals using frequencies of representations There is provided a method for reconstructing intended activities from a first representation of neural signals which is indicative of an intended activity to a second representation, wherein for second representations, a degree of agreement between the first representation and each second representation from a plurality of predetermined second representations that are indicative of intended activities is determined on the basis of a predetermined agreement criterion, and a second representation of neural signals is selected from the plurality of second representations on the basis of the degree of agreement, which selected second representation is the reconstructed intended activity.
US09436909B2	Increased dynamic range artificial neuron network apparatus and methods Apparatus and methods for processing inputs by one or more neurons of a network. The neuron(s) may generate spikes based on receipt of multiple inputs. Latency of spike generation may be determined based on an input magnitude. Inputs may be scaled using for example a non-linear concave transform. Scaling may increase neuron sensitivity to lower magnitude inputs, thereby improving latency encoding of small amplitude inputs. The transformation function may be configured compatible with existing non-scaling neuron processes and used as a plug-in to existing neuron models. Use of input scaling may allow for an improved network operation and reduce task simulation time.
US09436900B2	RFID switch tag Various embodiments of RFID switch devices are disclosed herein. Such RFID switch devices advantageously enable manual activation/deactivation of the RF module. The RFID switch device may include a RF module with an integrated circuit adapted to ohmically connect to a substantially coplanar conductive trace pattern, as well as booster antenna for extending the operational range of the RFID device. The operational range of the RFID switch device may be extended when a region of the booster antenna overlaps a region of the conductive trace pattern on the RF module via inductive or capacitive coupling. In some embodiments, all or a portion of the booster antenna may at least partially shield the RF module when the RFID switch device is in an inactive state. The RFID switch device may further include a visual indicator displaying a first color if the RFID switch device is in an active state and/or a second color if the RFID switch device is in an inactive state.
US09436896B2	Chip card holder and portable electronic device with same A chip card holder includes a tray and a protecting member. The tray includes a receiving portion and a handle portion. The receiving portion is configured to receive a chip card. The handle portion is positioned at a side of the receiving portion. The protecting member is sleeved on the receiving portion and resists the handle portion. The protecting member is made of elastic material so as to prevent outside contamination from entering the chip card holder.
US09436891B2	Discriminating synonymous expressions using images A method for identifying synonymous expressions includes determining synonymous expression candidates for a target expression. A plurality of target images related to the target expression and a plurality of candidate images related to each of the synonymous expression candidates are identified. Features extracted from the plurality of target images are compared with features extracted from the plurality of candidate images using a processor to identify a synonymous expression of the target expression.
US09436888B2	Method and system for determining a boundary surface network A method is disclosed for determining a boundary surface network of a tubular object. An ordered series of contours is first supplied on the basis of image data in a source space. A transformation function is created for at least two consecutive contours in the series, and a unit space segment object is created in the unit space on the basis of the consecutive contours. A local signed distance function is determined in the unit space. In addition, a relative positional information of a query point is determined in the source space from a surface of a segment object in the source space, the segment object being based on the consecutive contours, on the basis of the local signed distance function in the unit space and using the transformation function. Finally, the boundary surface network is created on the basis of the relative positional information that has been determined.
US09436887B2	Apparatus and method for automatic action selection based on image context Devices and a method are provided for providing context-related feedback to a user. In one implementation, the method comprises capturing real time image data from an environment of the user. The method further comprises identifying in the image data a hand-related trigger. Multiple context-based alternative actions are associated with the hand-related trigger. Further, the method comprises identifying in the image data an object associated with the hand-related trigger. The object is further associated with a particular context. Also, the method comprises selecting one of the multiple alternative actions based on the particular context. The method further comprises outputting the context-related feedback based on a result of the executed alternative action.
US09436885B2	Determining a computer's position and system for manufacturing a tag A system and method for accurately positioning a computer position, and identifying the specific rack position where the computer is without manual intervention. A camera is installed on the computer to read the contents of a tag on the rack, so as to identify the position information of the computer. Specifically, the computer is provided with a self-positioning function, wherein: a camera is installed on the computer, and the camera is configured to read the contents of a tag attached on a side of a rack to house the computer to identify the rack position where the computer is.
US09436882B2	Automated redaction In embodiments, one or more computer-readable media may have instructions stored thereon which, when executed by a processor of a computing device provide the computing device with a redaction module. The redaction module may be configured to receive a request to redact a selection of text from a document and identify instances of the text occurring within the document through an analysis of word coordinate information of an image of the document. The redaction module may further be configured to generate redaction information, including redaction coordinates, the redaction coordinates may be based on the word coordinate information associated with respective instances of the text occurring within the document. The redactions, when applied to the image in accordance with the redaction coordinates, may redact the respective instances of the text. Other embodiments may be described and/or claimed.
US09436880B2	Vehicle vision system A vision system for a vehicle includes an imaging sensor having a forward field of view in a forward direction of travel of the vehicle. The imaging sensor includes an array of photosensing elements that has groupings of photosensing elements, each grouping having at least three neighboring photosensing elements. At least one photosensing element of each grouping is a red light sensitive photosensing element and at least one other photosensing element of each grouping is a white light sensitive photosensing element. A control may process image data captured by the imaging sensor to determine a taillight of a leading vehicle present in the forward field of view and traveling ahead of and in the same direction as that of the equipped vehicle. The control may process captured image data to determine rate of approach of the equipped vehicle relative to the leading vehicle.
US09436877B2	Pedestrian right of way monitoring and reporting system and method A system and method for monitoring vehicle traffic and collecting data indicative of pedestrian right of way violations by vehicles is provided. The system comprises memory and logic for monitoring traffic intersections and recording evidence indicating that vehicles have violated pedestrian right of way. Two sensor modalities collecting video data and radar data of the intersection under observation are employed in one embodiment of the system. The violation evidence can be accessed remotely by a traffic official for issuing of traffic citations.
US09436870B1	Automatic camera selection for head tracking using exposure control The subject technology provides embodiments for tracking a user's face/head (or another object) using one or more cameras provided by a computing device. Embodiments implement exposure sweeping based on an average intensity of a current scene to a target intensity for a given image. If a face is not detected, an exposure duration and/or gain may be adjusted and the face detection is performed again. Once the face is detected, an average intensity of a virtual bounding box surrounding the detected face is determined and exposure sweeping may be performed solely within the virtual bounding box to reach a target intensity. When the average intensity is within a predetermined threshold of the target intensity, the detected face may be at an optimal exposure. Embodiments also provide for switching to another camera(s) of the computing device when not detecting a face in the image upon performing a full exposure sweep.
US09436869B2	Method and apparatus for acquiring nerve fiber structure information of object by using MRI system A method of obtaining fiber structure information of a nerve fiber in an object by using an MRI system includes: obtaining image information of voxels of the object; setting a tracking start area including at least one voxel of the object; setting at least one voxel adjacent to the tracking start area as a tracking processing area; determining a similarity between image information of a voxel included in the set tracking processing area and a voxel included in the tracking start area; and obtaining the fiber structure information according to the determined similarity.
US09436864B2	Electronic device performing finger biometric pre-matching and related methods An electronic device may include a finger biometric sensor to sense a user's finger adjacent thereto, and a memory for storing finger matching biometric data and a subset of finger matching biometric data. The electronic device may include a processor coupled to the finger biometric sensor to acquire finger matching biometric data from the finger biometric sensor, and perform a finger pre-matching between a subset of the acquired finger matching biometric data and the subset of stored finger matching biometric data and based upon context data to generate pre-match data. The processor may also perform a finger matching between the acquired finger biometric data and the stored finger matching biometric data based upon the pre-match data.
US09436863B2	Reconstructing a biometric image A biometric sensing device is operatively connected to a processing channel. The processing channel can include one or more variable gain amplifiers and/or one or more variable offset circuits. The signal levels associated with a section of a biometric image can be reconstructed using a digitized section of the biometric image and a particular gain and/or a particular offset value used in the processing channel to process the digitized section of the biometric image. The reconstructed sections of the biometric image can be combined to form a reconstructed biometric image. Additional processing operations can be performed on the reconstructed biometric image.
US09436859B2	Ad hoc localization using a movable reader and movable id tags Embodiments are directed to a method of identifying an identification (ID) tag. The method includes using a movable reader to determine a presence of an ID tag, an absence of the ID tag and that the ID tag has moved. The method further includes using the movable reader to determine a localization probability score of the ID tag, and, based on the localization probability score, adjust the movable reader's determination of the presence of the ID tag.
US09436855B2	Card reader for mobile device A card reader for use with a mobile device includes a foot and/or a housing for a jack on the bottom of the card reader prevents the card reader from accidently turning off the mobile device during use.
US09436851B1	Geometric encrypted coded image A method, system and computer program for defining a geometric code is provided. The method for generating a geometric code includes the steps of defining a first geometric shape, defining a size of a second geometric shape as a change in size from the first geometric shape, defining a position of the second geometric shape as a change in position from the first geometric shape, and displaying the first geometric shape and the second geometric shape. A system for imaging the defined geometric code includes a processor performing the steps of segmenting the imaged code, partitioning the segmented imaged code, determining a gray level of each portion of the partitioned segmented imaged code, and determining a code represented by each segmented portion of the partitioned segmented imaged code.
US09436844B2	Access enablement security circuit A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.
US09436841B2	Enhanced system security Methods and systems for maintaining the confidentiality of data provided by an organization for storage on a third party database system are provided. The data can be encrypted on an internal network of the organization and sent to the third party database system for storage. The third party database system can associate metadata with the encrypted data and can store the encrypted data. Accordingly, when a request for the encrypted data is received from a computing device communicating with an internal network of the organization, the encrypted data and associated metadata can be sent to the computing device. A key that is stored on an internal network of the organization can be called through an applet, which utilizes information within the metadata to locate the key on the internal network of the organization.
US09436839B2	Tokenization using multiple reversible transformations Technologies for tokenizing data including a computing device to extract plaintext data from an input file to be tokenized. The computing device performs data domain-specific format-preserving encryption on the extracted plaintext data based on a first cryptographic key to generate encrypted data and replaces one or more portions of the encrypted data with corresponding portions of alternative data based on a mapping table that maps encrypted data to alternative data. The computing device further performs data domain-specific format-preserving encryption on the alternative data based on a second cryptographic key to generate a token and stores the token in an output file.
US09436836B2	Tamperproof regulation of a process, production, and actuating installation A method for regulating process, production, and/or actuating installation includes recording observation data records at installation components of the installation by respective recording units of the installation. The method also includes transmitting the observation data records to a central control apparatus of the installation via a field bus. The method further includes forming, at the control apparatus, associated actuating data record based on the transmitted observation data records. The method also includes transmitting the actuating data records to actuating units of the installation via filed buses. The method also includes adjusting the installation components from the actuating units based on the transmitted actuating data records. The observation data records are encrypted at the respective recording units before transmitted to the control apparatus The actuating data records are formed from the encrypted observation data records without decrypting the encrypted observation data records during the process of forming the actuating data records.
US09436834B1	Techniques using an encryption tier property in a multi-tiered storage environment Techniques are described for storing data. A plurality of storage tiers are provided including a first set and a second set of storage tiers of physical devices. Data stored on any physical device in the first set is stored in an encrypted form. Data stored on any physical device in the second set is not stored in an encrypted form. A first value is specified for a first setting that is any of a tiering preference and tiering requirement indicating that at least one data portion of a logical device is to be stored on physical device(s) of a storage tier storing data in an encrypted form. Responsive to specifying the first value as the first setting, the at least one data portion of the logical device currently stored on physical device(s) of the second set are relocated to physical device(s) of the first set.
US09436827B2	Attesting a component of a system during a boot process A method for attesting a component of a system during a boot process. The method includes steps of: verifying that the system is in a trusted state; in response to verifying that the system is in a trusted state, requesting an enrollment of the system wherein the requesting step further comprises the step of: retrieving enrollment data associated with the system; retrieving current input data associated with the component of the system; comparing the current input data against the enrollment data in order to determine whether the system can retain its trusted state; wherein in response to the comparing step, if the current input data matches the enrollment data, the system retains its trusted state; and accepting the trusted state until receipt of a notification, from the system having a retained trusted state, of an update to the system.
US09436825B2	System and method for integrity assurance of partial data A system is disclosed for assuring the integrity of file segments. A first server has an associated file repository storing a plurality of files and transfers a file segment on an output upon request. A second server also has an associated file repository and receives and stores the file segment in the associated file repository. The second server identifies if there are additional segments of the same file in the associated file repository and processes the received file segment together with the additional identified file segments to identify the presence of malware. Finally, the second server transfers the received file segment on an output as a scanned file segment only if no malware is identified. A third server has an associated file repository and is configured to receive and store the scanned file segments in the associated file repository and to transfer a received scanned file segment to a client.
US09436823B1	System and method for detecting malicious code A method and apparatus are provided to detect malicious code in a computing system, where the malicious code is obscured by manipulation of an input/output memory management unit. A peripheral component interconnect express (PCIe) device requests a translation of a bus address for a given device in the system and determines whether the requested translation was received. If the requested translation was received, the PCIe device further determines whether the bus address for the given device corresponds to a physical address for the given device. If the bus address for the given device does not correspond to the physical address for the given device, the PCIe device sends a notification that the computing system is potentially compromised.
US09436822B2	Virtual browsing environment An embodiment for providing a secure virtual browsing environment includes creating a virtual browsing environment with a virtualized operating system sharing an operating system kernel of a supporting operating system and executing the browser application within the virtual browsing environment. Another embodiment includes receiving a website selection within a browser application, determining if the website selection corresponds to a secure bookmark, and creating a second virtual browsing environment and executing the browser application within the second virtual browsing environment to access the website selection when the website selection corresponds to a website specified as a secure bookmark. Yet another embodiment includes monitoring operation of the operating system within the at least one virtual browsing environment, determining when the operation of the operating system includes potential malicious activity, and terminating the virtual browsing environment when the operation includes potential malicious activity.
US09436811B2	Systems and methods for licensing non-destructive testing content A non-transitory computer readable medium may include executable instructions which, when executed by a processor, cause the processor provide for a repository of digital content and to create a first license based on the digital content. The instructions further cause the processor to transmit the first license and the digital content to a non-destructive testing (NDT) device, and wherein the digital content is configured to be executed by, used by, or displayed by the NDT device, or a combination thereof, based on the first license.
US09436804B2	Establishing a unique session key using a hardware functionality scan Systems and methods for independently generating a unique private session key at one or more hardware devices within a computing system using a subset of the functionality implemented in a hardware functionality scan combined with the use of a one-way mathematical function.
US09436800B2	Method and system for collecting and disseminating data produced by medical devices, particularly those used in intensive care units The invention relates to a method and a system for collecting medical data produced by medical devices (1) situated, for example, in intensive care units and for disseminating said information to the health professionals using computer equipment (5).The process and the system include the following software modules: (I) one service module (DS) (21), (II) a data storage module (DDS) (25), (III) control modules (DAC) (26) accessible from any point of said computer communications network and controlling the distribution of said data D, (IV) a device interface module (DDI) (23), configured as a function of the specifications of said transmitter devices (1), (V) a communications interface module (DCI) (22), (VI) a configuration interface module (DCP) (28), (VII) a data portal module (DDP).
US09436798B2	Method of retrieving data from a medical image data set The present invention discloses a method of retrieving a plurality of data slices from a medical image data set (5), the method comprising the steps of: a) displaying an indicator (10, 20) associated with the plurality of data slices; b) selecting the indicator (10, 20) based on a user input; and c) retrieving the plurality of data slices (1, 2) associated with the indicator when said indicator is selected; wherein the association between the indicator and the plurality of slices is based on segmentation of the medical image data set, the indicator representing an object obtained in the segmentation of the medical image data set, the plurality of data slices comprising the object data. The method of the invention reduces the amount of data transfer because it allows for retrieving only those data slices which comprise relevant data relating to the object of interest.
US09436797B2	Bioinformatics platform for high-throughput identification and quantification of N—glycopeptide The present invention relates to a more efficient and accurate method for the identification and quantification of comparatively low abundant glycopeptides, compared with general peptides, using mass spectrum obtained by using high resolution mass spectrometer. Therefore, the method of the present invention can be effectively used for the techniques for identification of biotherapeutics and diagnosis of cancer or disease by screening glycopeptide, the disease marker (Biomarker), from various samples.
US09436793B2	Tier based layer promotion and demotion Among other things, one or more systems and techniques for tier based layer modification, such as promotion or demotion, for a design layout are provided herein. A metal scheme describes one or more metal layers of the design layout, which are grouped into a set of tiers based upon resistivity similarity between the metal layers. Wire segments of the design layout are evaluated for promotion to tiers providing improved performance, for demotion to tiers providing decreased performance so that relatively faster routing resources are freed up for other wire segments, or for modification such as widening of wire segments. Via count penalties corresponding to timing delays of additional vias used to reassign wire segments are taken into account during promotion. Routing resource gains associated with reassigning wire segments are taken into account during demotion. In this way, wire segments of the design layout are promoted, demoted, or modified.
US09436789B2	Structure, method and system for complementary strain fill for integrated circuit chips A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
US09436785B1	Hierarchical preset and rule based configuration of a system-on-chip Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.
US09436782B2	Transmission device and temperature control method There is provided a transmission device including an associative memory in which, when data is specified, contents of the memory are searched for the data and an address of a location in which the data has been found is read out; a detector configured to detect an access rate to the associative memory; an estimation unit configured to estimate a temperature of the associative memory, based on the access rate to the associative memory; a prediction unit configured to predict a time period until the temperature of the associative memory reaches a specified temperature, based on the temperature estimated by the estimation unit; and an access controller configured to control an access to the associative memory, based on the time period predicted by the prediction unit.
US09436769B2	Automatic device upload configuration Various embodiments of the present technology involve the configuration of a wireless-enabled memory card. For example, a client application associated with a content management system (CMS) can obtain a computing device's current wireless configuration information, request a temporary authentication token from the CMS, encode this information in a visual code, and display this visual code on a display screen of the computing device. A user can capture an image of the visual code with a camera, thereby, causing the memory card to extract the wireless configuration information and token from the image, and connect to the specified wireless network. Once connected, the temporary authentication token is exchanged for an access token allowing the memory card to automatically send images captured by the camera to an account with the CMS for storage.

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