| Document | Document Title |
|---|---|
| US09432002B2 |
High-speed voltage level shifter circuit
A level shifter includes a latch having first and second branches, first and second outputs, first and second control switches in series between the respective branches and outputs, and a controller receiving first and second output signals and outputting first and second control signals to the first and second control switches for controlling activation thereof. In an initial state, the first output signal is in the first state, the first control switch is activated, the second output signal is in the second state, and the second control switch is deactivated. In a final state, the first output signal is in the second state, the first control switch is deactivated, the second output signal is in the first state, and the second control switch is activated. The controller changes the first and second control signals only after the first and second output signals reach the respective second and first states. |
| US09431999B1 |
Intelligent mechanical balancing apparatus for slide screw tuners
An intelligent, independent and universal mechanical balancing apparatus for automatic microwave multi-probe slide screw tuners allows stable on-wafer testing of sub-micrometric devices. Low loss rigid airlines (bend-lines) used to connect the multi-probe tuner with the chips, in order to improve the tuning range at the DUT reference plane, causes mechanical movements of the wafer probes attached to the rigid bend-lines, when the tuner mobile carriages move horizontally. Stabilizing the center of gravity (balancing) of the tuner by means of exactly controlled counter-weights, driven by the same firmware which controls the tuner motors, allows for synchronized compensation of the probe movement and safe on wafer load pull operation. |
| US09431988B2 |
Stacked chip device
The present disclosure relates to a stacked chip device including a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions, a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns, and a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns, wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets. |
| US09431986B2 |
Sound processing apparatus and sound processing method
A sound processing apparatus includes an information acquisition unit which acquires control information including at least one of mode information for designating a reproduction mode of the sound processing apparatus and attribute information for designating an attribute of an audio content represented by a sound signal, a frequency band expansion unit which performs frequency band expansion processing for adding an expanded component generated from the sound signal to the sound signal, and a control unit which changes parameters to be applied to the frequency band expansion processing in accordance with the control information acquired by the information acquisition unit. |
| US09431985B2 |
Dynamic adjustment of master and individual volume controls
Techniques for controlling the volumes of multiple audio output devices using a collective (master) volume control and an individual volume control for each audio output device. In one set of embodiments, each individual volume control can be configured to indicate the current absolute volume level of its corresponding audio output device. When the master volume control is manually adjusted, the individual volume controls can be automatically adjusted in a manner proportional to the manual adjustment of the master volume control. In addition, when an individual volume control is manually adjusted to a setting or value that exceeds the master volume control, the master volume control can be automatically adjusted to be equal to, or greater than, the manually adjusted setting for the individual volume control. In this scenario, the other individual volume controls can remain unchanged. |
| US09431984B2 |
Acoustic apparatus
An acoustic apparatus includes a signal processor configured to generate an analog audio signal based on a digital audio signal. The digital audio signal includes a first silent part and a sound part subsequent to the first silent part. The signal processor starts an operation in a period during which the first silent part is input. |
| US09431982B1 |
Loudness learning and balancing system
A loudness learning and balancing system for one or more audio channels. The system learns user volume preferences from manual interventions, providing effective and robust loudness learning to provide a consistent and balanced sonic experience. The system also reduces and/or eliminates incorrect attenuation or over-amplification of quiet interludes in the audio material, thereby eliminating artifacts such as noise pumping or breathing. In addition, the system reduces low level noise in the audio signals while preserving a wide dynamic range at most listening levels. |
| US09431980B2 |
Apparatus, systems and methods for adjusting output audio volume based on user location
Systems and methods are operable to adjust an output audio volume level of presented audio content that is output as sound from one or more speakers in a media presentation environment. An exemplary embodiment detects movement of a user who is listening to the audio content; increases the output audio volume level when the detected user movement is away from a predefined location in the media presentation environment; and decreases the output audio volume level when the detected user movement is closer to the predefined location in the media presentation environment. |
| US09431979B2 |
Method and apparatus for emulating sound
A method of emulating a sound of an audio apparatus by using a sound emulation apparatus includes obtaining k past samples (where k is a natural number that is equal to or greater than 1) by delaying a current sample of an audio signal; applying a plurality of characteristic functions indicating an input/output relationship of the audio apparatus to the current sample and the k past samples, respectively; and adding the current sample and the k past samples, to which the plurality of characteristic functions have been applied, respectively, to generate an emulation sound of the audio apparatus. |
| US09431973B2 |
Pulse-width modulation generator
The present application relates to a pulse-width modulation generator for generating a pulse-width modulated signal, the PWM generator comprising: a PWM modulator; and a loop filter, wherein the loop filter is configured to receive an input signal and to output a filtered signal to the PWM modulator, and the PWM modulator is configured to receive the filtered signal from the loop filter and to output a pulse-width modulated signal, the PWM generator further comprising: a feedback loop coupling an output of the PWM modulator to an input of the loop filter, wherein the feedback loop includes a comb filter. |
| US09431971B2 |
Reduced-power dissipation for circuits handling differential pseudo-differential signals
In an example, a differential amplifier is disclosed that is configured to realize low noise with decreased overall system current. The differential amplifier may include a first amplifier stage and a second amplifier stage arranged in series, wherein a pull-up current iH flowing as a single bias current iB=iH flows into the first stage. A single pull-down current iT sources to ground from the second stage, wherein iH=iT=iB substantially. In certain embodiments, the transconductance of the second stage may be increased by providing two transconductors coupled at their base nodes. |
| US09431969B2 |
Doherty power amplifier with tunable impedance load
Radio frequency (RF) amplification devices are disclosed that include Doherty amplification circuits and control circuits along with methods of operating the same. In one embodiment, the Doherty amplification circuit includes a quadrature coupler having an isolation port and a tunable impedance load coupled to the isolation port and configured to provide a tunable impedance. The control circuit is configured to tune the tunable impedance of the tunable impedance load at the isolation port dynamically as a function of the RF power of the Doherty amplification circuit. In this manner, the control circuit can provide dynamic load modulation, thereby increasing the power efficiency of the Doherty amplification circuit, particularly at backed-off power levels. The load modulation provided by the control circuit also allows the Doherty amplification circuit to provide broadband amplification in various RF communication bands. |
| US09431967B2 |
Dynamic amplifier supply
A method of providing a power supply of an amplifier of a wireless transmission system comprising, determining the power at an antenna when transmitting a signal to be transmitted by the amplifier, determining the modulation scheme for transmitting the signal, determining the frequency allocation of the signal to be transmitted, determining a transmit channel characteristic, and adjusting a parameter of the power supply of the amplifier based on the determining steps to maintain amplifier linearity. |
| US09431966B2 |
High efficiency and high linearity adaptive power amplifier for signals with high papr
One embodiment of the present invention provides a system for controlling operations of a power amplifier in a wireless transmitter. During operation, the system receives a baseband signal to be transmitted, and dynamically switches an operation mode of the power amplifier between a high power back-off mode having a first power back-off factor and a normal mode having a second power back-off factor based on a level of the baseband signal. |
| US09431964B2 |
Operational amplifier and method of operating the operational amplifier
An operational amplifier comprises a first input pair, a second input pair, a switch and a first current mirror. The first input pair comprises a different type of MOS transistor from the second input pair. The switch determines which one of the first or the second input pair is functioning and the operating input pair is configured to output voltage. The switch is further connected to the first input pair and the first current mirror. The first current mirror is further connected to the second input pair, and is configured to copy a current passing through the switch to the second input pair. Therefore an increase of transconductance of the first input pair is compensated by a decrease of transconductance of the second input pair, and the operational amplifier has a substantially constant transconductance no matter which of the first input pair and the second input pair is functioning. |
| US09431960B2 |
Solution testing equipment
There is provided solution testing equipment which can detect an output variation of a THz oscillation device using a THz wave (hν) by contacting a liquid or cells on an RTD oscillation device, and can reduce the size and weight thereof. The solution testing equipment includes: a THz oscillation device configured to radiate the THz wave Is; a THz detection device configured to receive the THz wave Is; and a solution as a test object disposed on the THz oscillation device, in which the solution is tested on the basis of output characteristics of the terahertz wave varying in response to a relative permittivity of the solution. |
| US09431953B2 |
Height adjustment bracket for roof applications
A roof mount for mounting at least one solar panel to a roof surface including a base. The roof mount includes a clamp connected to the base and a first recess sized to support a first solar panel. The first recess has a first height extending between a first top flange and a first bottom flange. The clamp also includes a second recess sized to support one of a second solar panel and a skirt flange. The second recess has a second height extending between a second top flange and a second bottom flange. The roof mount further includes a fastener connected to the clamp. The second fastener is operable to adjust the first and second heights, such that upon tightening of the second fastener, the first height increases and the second height decreases, and upon loosening of the second fastener, the first height decreases and the second height increases. |
| US09431951B2 |
Direct torque control motor controller with transient current limiter
An AC motor controller is provided that utilizes a direct torque controller and primary and secondary control loops. The primary control loop operates in a relatively conventional manner, determining a voltage vector that sets the inverter switching variables for the motor's power inverter, where the voltage vector is based on the motor's torque and flux as estimated from the measured voltage and current of the motor. Application of the voltage vector determined by the primary loop is delayed until initiation of the next primary control loop cycle. The secondary loop, utilizing a faster sampling rate than that of the primary loop, compares the measured phase current to a preset current limit. If the secondary loop determines that the measured phase current has exceeded the preset current limit, it sets a null voltage vector, thereby limiting transient over currents. |
| US09431947B2 |
Input vector set for position detection of PM motors
A method of determining angular position (A) of a rotor of an N-phase permanent magnet motor (PMM). A processor having an associated stored angular position determination (APD) algorithm is programmed to implement the algorithm to cause an associated motor controller to execute steps including forcing one vector at a time a phase vector set of current or voltage vectors to stator terminals of windings for the N-phases a positive and negative magnitude vector, wherein the vector magnitude is sufficiently small to not move the rotor, and a time duration for the forcing current or voltage vectors is essentially constant. The resulting stator current or voltage levels are measured for each current or voltage vector. An N-dimension current vector or voltage vector is generated from superposition of the resulting stator current levels or resulting stator voltage levels. The N-dimension current vector or voltage vector is used to determine angular position. |
| US09431943B2 |
Assembly operating in a variable regime
The invention relates to electromechanical assemblies comprising an alternator, especially of high power, typically greater than or equal to IMW, and a converter, the alternator comprising a rotor driven in rotation, by a wind turbine for example, and more particularly to wound rotor synchronous alternators. The drive can also take place by means of a tide-driven, hydraulic or marine-current-driven generator. An alternator comprises in a manner known per se a field winding, generally at the rotor, supplied with DC current either by split rings and brushes, or by an exciter, so as to generate in an armature winding, generally at the stator, an AC voltage. |
| US09431941B1 |
Method and apparatus for detecting alternator rectifier diode short fault
Methods for detecting a short fault of an alternator rectifier electronic component include sampling a field winding voltage or current signal of an alternator, during operation of the alternator, and determining a fault ripple period at which the alternator field winding signal exceeds a fault threshold. A short fault of an electronic component of a rectifier coupled to the alternator is detected in the event that the fault ripple period closely matches an alternator armature period. Alternatively or additionally, the sampled field winding signal is band pass filtered, and a short fault is detected in the event that an amplitude of the band pass filtered field winding signal exceeds a fault threshold. The methods can be implemented, for example, by an apparatus that includes a hysteresis frequency counter, a frequency comparator, and a countdown timer. |
| US09431934B2 |
Motor controller with drive-signal conditioning
An embodiment of a motor controller includes a motor driver and a signal conditioner. The motor driver is operable to generate a motor-coil drive signal having a first component at a first frequency, and the signal conditioner is coupled to the motor driver and is operable to alter the first component. For example, if the first component of the motor-coil drive signal causes the motor to audibly vibrate (e.g., “whine”), then the signal conditioner may alter the amplitude or phase of the first component to reduce the vibration noise to below a threshold level. |
| US09431932B2 |
Converter unit for an asynchronous machine
A converter unit having at least one output. The at least one output is configured to be connected to a coil of an asynchronous machine. The converter unit is configured to provide several voltage levels at the at least one output. |
| US09431931B2 |
Controller for a brushless motor
A controller for a brushless motor that includes a PWM module configured in half-bridge or full-bridge mode. The PWM module outputs control signals for controlling the excitation of a winding of the motor, and one of the duty cycle and the period of the PWM module defines a time at which the winding is commutated. |
| US09431927B2 |
System for harvesting energy from door or door hardware movement
An electrical generation system for a doorway including a door includes a lock mechanism movable between an engaged position and a disengaged position to allow the door to move between a closed position and an open position and a cam coupled to the door. A piezo-electric generator is coupled to the cam. The cam is rotatable with respect to the piezo-electric generator. The piezo-electric generator is operable to produce an electrical current in response to rotation of the cam with respect to the piezo-electric generator, and the electrical current has a frequency that is greater than the number of revolutions made by the cam with respect to the piezo-electric generator. |
| US09431925B2 |
Half bridge circuit, full bridge circuit constructed with half bridge circuit, and three-phase inverter circuit constructed with half bridge circuit
In a half bridge circuit according to one aspect of the present disclosure, when a voltage between a first terminal and a third terminal or a voltage between the first terminal and the second terminal is greater than or equal to a threshold voltage, a current is passed from the second terminal to the third terminal or from the third terminal to the second terminal according to a polarity of the voltage between the second terminal and the third terminal. When the current is passed from the third terminal to the second terminal, the voltage between the second terminal and the third terminal changes with respect to the voltage applied between the first terminal and the third terminal within a range where the voltage between the first terminal and the third terminal is less than or equal to the threshold voltage. |
| US09431923B2 |
Power converter
An operation area of a motor is increased without increasing the capacity of a switching element. A current limiter which limits a current flowing in switching elements to prevent the current from exceeding a predetermined current limit value is provided. A current limit value controller which decreases the current limit value if a loss generated in the switching elements increases at a same current value, and increases the current limit value if the loss decreases at a same current value, is provided. |
| US09431920B2 |
Non-isolated DC/DC converter with 2 inductors and zero voltage switching
Zero-voltage switching of a switching element (Q2) is achieved by turning off a switching element (Q1) and then turning on switching element (Q2) while the parasitic diode (DQ2) of switching element (Q2) is turned on. Subsequently, switching element (Q2) is turned off when the current flowing through switching element (Q2) changes from negative to positive (in a direction from the drain towards the source) and the current reaches a prescribed threshold value. Then, zero-voltage switching of switching element (Q1) is achieved by turning on switching element (Q1) while the parasitic diode (DQ1) of switching element (Q1) is turned on. |
| US09431912B2 |
Control device for rectifiers of switching converters
A control device controls a rectifier of a switching converter that is supplied with an input voltage and provides an output current. The rectifier is configured to rectify the output current of the converter and has at least one transistor. The control device, when the at least one transistor is turned off, provides a slow discharge path to ground in a normal operation condition and provides a fast discharge path to ground for discharging the control terminal of the at least one transistor in response to detecting a zero cross event of the current flowing through said at least one transistor. |
| US09431910B1 |
Energy recycling system and recycling method thereof
An energy recycling system and an energy recycling method are disclosed. The energy recycling system includes several working circuits and a first energy recycling circuit. The working circuits include at least one first working circuit and at least one second working circuit. The first energy recycling circuit is coupled between the first working circuits and the second working circuits. The first alternating-current-type (AC-type) voltage source is supplied to the first working circuits and the second working circuits. The energy loss of the first AC-type voltage source is replenished by a direct-current-type (DC-type) voltage source. The first energy recycling circuit includes an inductor and pairs of switches, and the pairs of switches are configured for conducting in different time sequences and transferring the energy of the first AC-type voltage source between the first working circuits, the inductor and the second working circuits. |
| US09431901B2 |
Charge pump stage and a charge pump
A charge pump cell, comprising: an input node; an output node; Q channels, where Q is an integer greater than one, and where at least two of the channels comprise: a capacitor; a unidirectional current flow device; an output diode; and a channel drive signal node; and wherein a first current flow node of the unidirectional current flow device is connected to a first node of the capacitor at a channel node, a second node of the capacitor is connected to the channel drive signal node, a second current flow node of the unidirectional current flow device is connected to the input node, and the output diode is connected between the channel node and the output node. |
| US09431898B2 |
Bidirectional DC-to-DC converter
A bidirectional DC-to-DC converter is configured to convert electrical energy from a first and second DC source. The bidirectional converter includes an output capacitor providing an output voltage and a first and second inductor. The first inductor is arranged between a positive connection of the second DC source and a first contact of a first switch. The second inductor is arranged between a negative connection of the first DC source and a second contact of the first switch. A buffer capacitor is arranged between a negative output of the first DC source and a positive output of the second DC source. A second and third switch are arranged in series with the first switch. The second switch is arranged between the first contact of the first switch and the positive DC output. The third switch is arranged between the second contact of the first switch and the negative DC output. |
| US09431897B2 |
Electric device
Provided is an electric device, including: a secondary battery; and a power supply circuit for dropping an input voltage which is input from the secondary battery to an output voltage and outputting the output voltage to a load, in which the output voltage is stepwise dropped in accordance with the drop of the input voltage. |
| US09431887B2 |
Lens positioning system
An actuator includes an inner element coupled to an outer element by a linear-motion bearing that provides a single degree of translational movement of the inner element with respect to the outer element along a longitudinal axis. The inner element includes a permanent magnet and the outer element includes a conductive winding with a first coil wound in first direction around a first pole of the permanent magnet and a second coil wound in a second direction around a second pole of the permanent magnet. |
| US09431886B2 |
Method of manufacturing a magnet plate for a linear motor
A method for producing a magnet plate for a linear motor is provided. The magnet plate comprises a base plate and a plurality of magnets juxtaposed to one another on a surface of the base plate. The method comprises providing the plurality of magnets on a surface of the base plate at a certain interval, placing the base plate into a mold, supplying a resin material into the mold, so as to form a resin molding covering the plurality of magnets on the surface of the base plate by means of injection molding, and magnetizing the plurality of magnets. |
| US09431878B2 |
Electric machine with enclosed, autonomous cooling medium circuit
An electric machine has a base body with a stator, a rotor shaft mounted in the base body, and a heat exchanger. Cooling ducts for a liquid cooling medium are arranged in the base body. The rotor shaft is embodied as a hollow shaft through which the liquid cooling medium can flow. The heat exchanger dissipates heat contained in the liquid cooling medium to the surroundings of the electric machine. The heat exchanger, the rotor shaft and the cooling ducts are fluidically connected in series, producing a closed circuit for the liquid medium. A feed element is arranged to co-rotate with the rotor shaft. The feed element is inserted in the closed circuit for the liquid cooling medium to forcibly circulate the liquid cooling medium in the closed circuit as the rotor shaft for the liquid cooling medium rotates. |
| US09431874B2 |
Meter unit including step motor and braking spring
A meter unit includes a step motor, a gear, a braking spring and a case. The gear has a gear body and a rotation shaft. The braking spring urges the gear in a direction of an axis of rotation of the gear. The case accommodates the step motor, the gear body, a part of the rotation shaft, and the braking spring therein. The braking spring has a shape through which the first part of the rotation shaft passes. A first face of the gear body is formed with a recessed portion which accommodates the braking spring. A first part of the case supports a second face of the gear body. A second part of the case is configured to press the braking spring so that entire part of the braking spring is accommodated in the recessed portion. |
| US09431867B2 |
Rotating electrical machine
A rotating electrical machine includes a stator, a rotor, a case, a seal member, and a terminal board. The stator has a conductor line wound thereon. The rotor is disposed inside the stator. The terminal board is to make an electrical connection between the conductor line and an external power line connected to a power supply. The terminal board is contained in the case and includes a relay conductor and a storage chamber containing the relay conductor. The relay conductor is to make a connection between the conductor line and the external power line. The storage chamber is hermetically closed by the seal member with respect to an outside of the case. The storage chamber has a discharge hole that allows communication between the storage chamber and the outside. |
| US09431865B2 |
Standby generator with removable panel
A standby generator includes a base and a number of walls extending from the base including a wall having a removable panel. A cover is coupled to the wall having the removable panel and is moveable between a closed position and an open position. When the cover in the open position, the removable panel may be removed from the standby generator. |
| US09431863B2 |
Insulation component for an electric machine and method of assembly
An electric machine includes a core with a plurality of teeth that extends between end faces of the core. Slots are defined in the core between adjacent teeth of the plurality of teeth. The slots each have a radial opening formed between end portions of the adjacent teeth. An insulation sheet is positioned on the core to obstruct the radial openings to the slots. The insulation has at least two spaced circumferential members that respectively overlap the end faces of the core. The insulation sheet also has a plurality of spaced axial members connected to the circumferential members. The axial members are positioned within the slots to obstruct the radial openings to the slots. |
| US09431862B2 |
Motor
A winding structure which is disposed over an armature and a commutator includes an equalizer. The equalizer includes a going portion and a return portion which are wound across one group of teeth through a slot and connected between two identical segments. In a case where an integer number is an expansion value among values which are integer multiples of a value which is acquired by dividing the total number of the slots by the total number of pole pairs, when one group of the teeth having the same total number as the expansion value is given as an element teeth group, the going portion and the return portion are wound across the element teeth group through the slots positioned at both sides of the element teeth group. |
| US09431861B2 |
Fixing permanent magnets to a rotor
A rotor for an electrical machine includes a base body, a plurality of permanent magnets which are arranged axially in rows on an outer surface of the base body. At least two of the permanent magnet rows are arranged so as to be mutually offset in an axial direction. First and second locking plates are respectively arranged at axial end faces of the base body to secure the rows of permanent magnets in the axial direction, with the first and second locking plates each having a surface which rests on respective axial ends of the permanent magnet rows. A bandage is wound around the base body to fix the permanent magnets to the outer surface of the base body. |
| US09431860B2 |
Rotor and method of manufacturing rotor
A rotor that can reduce the used amount of resin for securing a permanent magnet is provided. The rotor includes a rotor core provided fixedly to a rotation shaft and having a magnet insertion hole extending in an axial direction formed therein, a permanent magnet embedded in the magnet insertion hole and extending in the axial direction and extending in a direction inclined relative to a radial direction of the rotor core, and a resin layer that secures the permanent magnet to the rotor core. The resin layer covers a surface of the permanent magnet and is in contact with an inner surface of the magnet insertion hole. A hollow space extending in the axial direction is left in the magnet insertion hole at an inner side in the radial direction relative to the permanent magnet. Part of the inner surface of the magnet insertion hole is exposed to the hollow space. |
| US09431856B2 |
Power transmission
An improved device and system for power transmission. A power transmission device comprises a primary winding magnetically coupled to a resonant secondary which comprises a plurality of magnetic resonators, each magnetic resonator comprising a magnetic winding. The magnetic resonators are connected in series and arranged so that the magnetic axis of each magnetic resonator is coupled to the primary winding. In operation, a power source supplies alternating current at an operating frequency to the primary of a power transmission device used as a transmitter. A load is coupled to the primary of a power transmission device used as a receiver. Collectors may be coupled to either or both of the transmit or receive device. A return line may be coupled to either or both of the transmit or receive device. |
| US09431854B2 |
Multiple UPS system having multi-way power tie system and intelligent power sharing control
A multiple UPS system includes a plurality of multi-module UPS subsystems coupled to a power tie cabinet, each multi-module UPS subsystem having a plurality of UPS modules. The power tie cabinet includes one or more controllers, collectively referred to as PTC (power tie cabinet) controls. The PTC controls periodically determine a power error message for each of the multi-module UPS subsystems and pass it to the respective multi-module UPS subsystem. A controller of the multi-module UPS subsystem uses the power error message to determine error data that is provided to a power average control loop used in control of power sharing among the UPS modules of the multi-module UPS subsystem. |
| US09431852B2 |
Power supply device
A power supply device includes an input terminal to which an electric power is supplied from a commercial power source; an output terminal connected to an electric load; a power storage device to be charged by the electric power supplied from the input terminal and supplying the electric power to the output terminal; a primary battery; and a controller supplying an output of the primary battery to the output terminal, when monitoring a voltage of the commercial power source, which is applied to the input terminal, and a charged state of the power storage device, and detecting that the voltage of the commercial power source falls to a specified voltage value or less and the charged state of the power storage device indicates a specified value or less. |
| US09431849B2 |
Method for controlling the temperature of at least one battery element, battery and motor vehicle with such a battery
A method for controlling the temperature of at least one battery element, a battery, and a motor vehicle that has the battery includes specifying a temperature value, and determining the cool-down behavior of the at least one battery element beginning at a first temperature. A first point in time, at which the battery temperature will have reached or fallen below the temperature value, is determined by evaluating the cool-down behavior. Subsequently, a second point in time for a beginning of the charging or discharging of the at least one battery element is determined. If tmin |
| US09431848B2 |
Method and apparatus for protecting wireless power receiver from excessive charging temperature
An apparatus and a method for protecting a wireless power receiver from excessive temperature caused by charging are provided. The wireless power receiver includes a power receiver for receiving wireless power in an Alternate Current (AC) form from a wireless power transmitter; a regulator for regulating the wireless power; a power management unit for controlling charging by providing the regulated wireless power to a battery; a temperature measurement unit for measuring a temperature of a point in the wireless power receiver during reception of the wireless power; and a controller configured to provide a control signal for the wireless power receiver to be charged with a regulated charging power if a temperature measured by the temperature measurement unit exceeds a preset temperature. |
| US09431846B2 |
Systems and methods for controlling battery charging
Systems and methods for controlling battery charging are disclosed. According to one embodiment of the disclosure, a method can include receiving battery state information; determining, based on the battery state information, whether to adjust battery models; and, if so, adjusting the battery models. |
| US09431844B2 |
System and method for wireless power control communication using bluetooth low energy
This disclosure provides systems, methods, and apparatus for connecting with a charging device via a wireless communications network. In one aspect, a wireless charger comprises a transmitter configured to transmit a power signal. The wireless charger further comprises a device scanner configured to scan for one or more connection solicitations transmitted by devices. The wireless charger further comprises a receiver configured to receive a connection solicitation via the wireless communications network from the charging device in response to the transmitted power signal. The transmitter may be configured to transmit a connection request to establish a connection with the charging device in response to the received connection solicitation. |
| US09431842B1 |
Regulate the charging of a mobile device
Various embodiments of the invention provide methods, systems, and computer-program products for charging a battery of a first mobile device from a battery of a second mobile device. In particular embodiments, a request is received identifying an amount of charge to provide from the battery of the second device to the battery of the first device. Accordingly, a determination is made as to whether the amount of charge requested is likely to result in a battery charge of the second device dropping below a threshold value before the battery of the device is recharged based on historical battery charge usage data of the device over a past period of time. If the amount of charge is not likely to result in the battery charge dropping below the threshold value, then the battery of the first device is charged with the amount of charge from the battery of the second device. |
| US09431839B2 |
Method, apparatus, and computer program product for optimized device-to-device charging
Method, apparatus, and computer program product example embodiments provide device-to-device charging. According to an example embodiment of the invention, a method comprises receiving, by a first device, a user's selection of a charging criterion for balancing stored charges in the first device's own battery and in a second device's rechargeable battery; determining, by the first device, that recharging of the second device's rechargeable battery is required; computing, by the first device, an amount of charging required for the second device's rechargeable battery, in order to satisfy the user's selected charging criterion; and transmitting, by the first device, power provided by the first device's own battery, to the second device, for charging the second device's rechargeable battery until the present level of stored battery charge in the second device's rechargeable battery reaches the computed amount of charging required. |
| US09431835B2 |
Street light mounted network-controlled charge transfer device for electric vehicles
A network-controlled charge transfer device for transferring charge between a local power grid and an electric vehicle is mounted to a street light. The charge transfer device includes the following: an electrical receptacle to receive an electrical connector for connection to the electric vehicle; an electric power line that couples the power grid to the electrical receptacle through a wiring box; a control device to switch the receptacle on and off; a current measuring device to measure current flowing through the electric power line; and a controller to operate the control device and to monitor output from the current measuring device. |
| US09431828B2 |
Multi-source, multi-load systems with a power extractor
Apparatuses and systems enable power transfer from one or more energy sources to one or more loads. The input power from the energy sources may be unregulated, and the output power to the loads is managed. The power transfer is based on a dynamic implementation of Jacobi's Law (also known as the Maximum Power Theorem). In some embodiments, the energy sources are selectively coupled and decoupled from the power transfer circuitry. In some embodiments, the loads are selectively coupled and decoupled from the power transfer circuitry. Power transfer to the loads is dynamically controlled. |
| US09431826B2 |
Determining the power supply and receive relationships among a plurality of devices based upon power consumptions of each of the devices
An information processing system includes an obtaining unit, a specifying unit, and an output unit. The obtaining unit obtains information indicating a state of the use of each of plural electrical apparatuses. The specifying unit specifies a power supply-and-receive relationship between the plural electrical apparatuses, on the basis of a change in power associated with the obtained information concerning each of the plural electrical apparatuses. The output unit outputs information indicating the power supply-and-receive relationship. |
| US09431825B2 |
Systems and methods to reduce the number and cost of management units of distributed power generators
Apparatuses and methods for configuring and managing solar panels to form strings of photovoltaic energy generators with improved performance and reduced cost. The photovoltaic energy generators are connected via one or more combined local management units (CLMUs), each having a plurality of direct current converters connected to and configured to receive direct current power from a respective solar panel. A controller unit shared by the CLMU's direct current converters is utilized to separately control the operation of each converter such that the power extracted from the solar panels is maximized. A communications unit coupled with the controller unit is utilized to facilitate communications between the controller unit and a system unit remote from the CLMU to report measurements and receive control signals. |
| US09431824B2 |
DC-DC converter comprising DC power sources to be connected in parallel or in series
The power supply system includes a first DC power source, a second DC power source, and a power converter having a plurality of switching elements and reactors. The power converter is configured to be switchable, by the control of the plurality of switching elements, between a parallel connection mode in which DC voltage conversion is executed with the DC power sources connected in parallel with a power line and a series connection mode in which DC voltage conversion is executed with the DC power sources connected in series with the power line. Each of the switching elements is arranged to be included both in a power conversion path between the first DC power source and the power line PL and a power conversion path between the second DC power source and the power line. |
| US09431820B2 |
Vehicle or environment-controlled unit having a multiphase alternator with a protected high-voltage bus
A mobile environment-controlled unit, such as an over-the-road compartment trailer, having an environmental-control system, such as a refrigeration unit, powered by an alternator and having a high-voltage alternating current (AC) bus. The unit incorporates a high resistance ground scheme and can incorporate a solid-state input module to detect phase-chassis faults. This combination provides an improvement in protection for mobile applications that cannot have a voltage reference (or neutral point) solidly connected to earth ground. |
| US09431818B2 |
Protection circuits and methods for electrical machines
An assembly includes an electrical machine connected to a power converter by a three-phase circuit having three conductors, e.g. cables Each conductor is associated with a switching device such as a contactor or the like that connects the conductor to a common conductor or terminal. In the event of a fault current being developed in the circuit or the power converter the switching devices are operated to close the fault current and connect together the conductors of the three-phase circuit to provide a full three-phase short circuit. |
| US09431815B1 |
Cable fitting with grip assembly
An adjustable cable fitting with a removable grip assembly secures and retains a cable passing therethrough. The grip assembly has a flexible tightening member and a resilient grommet inserted in the tightening member. The grip assembly is further disposed between a connector and a compression cap, such that the tightening member assists the grommet in creating and maintaining a watertight seal with the cable when tightening the compression cap to the connector. The tightening member also assists the grommet in securing and retaining the cable by preventing it from being pulled out of the fitting. The tightening member has a plurality of spaced apart retaining arms. Each arm has a retaining flange at one end that overhangs past an end of the grommet and which has gripper elements formed thereon for directly gripping the cable. |
| US09431813B2 |
Redundant wired pipe-in-pipe telemetry system
A system and method for providing redundant wired pipe-in-pipe telemetry is described. The redundant wired pip-in-pipe telemetry system includes an outer pipe and an inner pipe disposed within the outer pipe. Within the outer pipe, two or more conductive elements may be provided as well as a wired path controller that may selectably switch between available conductive paths. The wired path controller may identify conductive paths with good electrical characteristics and select those paths for transmission. If a conductive path develops a fault, the wired path controller may select one of the alternative redundant conductive paths for transmission to avoid the fault. The wireless controller may further transmit information about the location of faults to a drill operator at the surface. |
| US09431812B1 |
Dynamic capacitors for tuning of circuits
A circuit includes a signal line formed of at least one conductive element and a shield at least partially encompassing the signal line. The circuit further includes a first dynamic capacitor located between the shield and the signal line. The first dynamic capacitor is configured to provide a first variable amount of capacitance. |
| US09431808B1 |
Electrical connector
An electrical connector for connecting an electrical conduit to a wall of a junction box having an opening therein and having edges surrounding the opening. The connector includes a connector body defining a conduit-supporting passageway having a conduit central axis, a proximal end, a distal end, and a sidewall extending between the proximal and distal ends, the distal end formed with a locating collar substantially encircling the connector body, the locating collar functioning to engage the edges of the opening in the junction box. The connector further includes a pressure lock mechanism for selectively and removably securing the connector body to the opening in the junction box. |
| US09431807B2 |
Booster cable holding structure
In a booster cable holding structure, a resin terminal supporting portion includes a tooth-edge surrounding wall on a pressed surface thereof to be pressed by a plurality of teeth arranged in a width direction of a pressing surface of a clip in a state the clip clamps a clamping connection portion, a wall inner surface of the tooth-edge surrounding wall closely surrounds each edge of at least two of the teeth of the clip or closely surrounds the edges of the at least two teeth together. |
| US09431804B2 |
Cable clamp and harness
A cable clamp is configured to fix an electric cable including an electric wire section and an outer layer section covering the electric wire section to a fixed member. The cable clamp includes a first cylindrical portion for the electric wire section to be inserted therein, and a second cylindrical portion formed around outside the first cylindrical portion to surround the first cylindrical portion. The second cylindrical portion includes a receiving portion formed between it and the first cylindrical portion to receive the outer layer section. The second cylindrical portion is swaged with the electric wire section inserted in the first cylindrical portion and with the outer layer section received in the receiving portion, so that the outer layer section is gripped by the first cylindrical portion and the second cylindrical portion. |
| US09431802B2 |
Cable protector
A cable protector including a conduit having a top channel having at least one engaging edge and a bottom channel having at least one engaging edge adapted to be removably coupled to the engaging edge of the top channel. The pair of removably coupled engaging edges includes an outer portion having a profile including a projection extending from a step to a tip and an inner portion having a profile including a locking step. When urged against the inner portion, the outer portion is slidingly coupled to the inner portion until the step becomes locked in the locking step to form a cavity within the conduit to accommodate the cables. When pulled from the inner portion, the outer portion is slidingly decoupled from the inner portion after the step becomes dislodged from the locking step to provide access to cables disposed within the cavity. |
| US09431799B2 |
Structure of three-phase integrated bus in gas insulated switchgear
The present disclosure relates to a gas insulated switchgear (GIS), and more particularly, a structure of a bus in a GIS. A structure of a three-phase integrated bus in a GIS, in a bus of a gas insulated switchgear comprising an enclosure, three phase conductors inserted in the enclosure, and spacers coupled to both sides of the enclosure to fix the three phase conductors, is characterized in that the three phase conductors are arranged in a shape of inverted triangle, wherein a conductor located at a lower side, of the three phase conductors, is formed in a shape of straight pipe, and has a branch bus upwardly extending from its middle portion, and wherein each of two conductors located at an upper end of the inverted triangle, of the three phase conductors, has both side portions formed in a shape of straight pipe and a middle portion outwardly curved. |
| US09431798B2 |
Various methods and apparatuses for a low profile integrated power distribution platform
A method, apparatus, and system are described for a monolithic, pre-wired, pre-engineered, and pre-assembled integrated platform for a critical power supply and electrical distribution system that is scalable and modular. The skeletal framework of the integrated platform acts as an equipment support structure and includes an upper superstructure and a lower superstructure. Two or more cabinet enclosures are mounted onto the lower superstructure where their weight is supported by the skeletal framework. One or more National Electric Code approved (NEC-approved) electrical cable routing support systems are mounted onto the upper superstructure. The skeletal framework also includes one or more vertical columns that are connected between the upper superstructure and the lower superstructure. The skeletal framework and the cabinet enclosures are fabricated in place as a monolithic, pre-wired, pre-engineered, and pre-assembled integrated platform prior to being installed. |
| US09431797B2 |
Spark plug electrode gap setting tool
A spark plug electrode gap setting pliers is provided. The pliers include a first jaw portion coupled to a first shim and a second jaw portion coupled to a second shim. Upon actuation of the pliers, the first and second jaw portions close in parallel to bend respective electrode supports of a pair of electrodes or to bend the pair of electrodes to provide a parallel gap between the pair of electrodes. |
| US09431795B2 |
Laser beam-combining optical device
A laser beam-combining optical device according to the present invention includes a plurality of semiconductor laser arrays, and a reflective element that reflects a laser light beam emitted from at least one semiconductor laser array of the plurality of semiconductor laser arrays. When laser light beams emitted from respective ones of the plurality of semiconductor laser arrays are focused on a single focus point, the laser light beam emitted from the at least one semiconductor laser array is reflected by the reflective element, and is then focused on the focus point. |
| US09431794B2 |
Optoelectronic device containing at least one active device layer having a wurtzite crystal structure, and methods of making same
Optoelectronic devices, such as light-emitting diodes, laser diodes, image sensors, optical detectors, etc., made by depositing (growing) one or more epitaxial semiconductor layers on a monocrystalline lamellar/layered substrate so that each layer has a wurtzite crystal structure. In some embodiments, the layers are deposited and then one or more lamellas of the starting substrate are removed from the rest of the substrate. In one subset of such embodiments, the removed lamella(s) is/are partially or entirely removed. In other embodiments, one or more lamellas of the starting substrate are removed prior to depositing the one or more wurtzite-crystal-structure-containing layer(s). |
| US09431791B1 |
Multi-section heterogeneous semiconductor optical amplifier
Described herein are methods, systems, and apparatuses to utilize a semiconductor optical amplifier (SOA) comprising a silicon layer including a silicon waveguide, a non-silicon layer disposed on the silicon layer and including a non-silicon waveguide, first and second mode transition region comprising tapers in the silicon waveguide and/or the non-silicon waveguide for exchanging light between the waveguide, and a plurality of regions disposed between the first and second mode transition regions comprising different cross-sectional areas of the silicon waveguide and the non-silicon waveguide such that confinement factors for the non-silicon waveguide in each of the plurality of regions differ. |
| US09431789B2 |
Method and apparatus for fabrication of controlled chirp gratings
In some aspects of the present application, an apparatus for producing an interference pattern on a photosensitive portion formed on a surface of a sample is disclosed. The apparatus can include an optical system for providing interference between two coherent spherical wavefronts impinging on a thin-film photosensitive material formed on a surface of a sample, wherein a plane of the surface normal of the sample is arranged at an angle with respect to a plane defined by center propagation vectors of the two coherent spherical wavefronts; and one or more actuating elements operable to actuate one or more optical elements in the optical system, the sample, or both the one or more optical elements and the sample in one or more degrees of freedom to control a relative magnitude of a longitudinal and a transverse chirp of the interference pattern. |
| US09431785B2 |
High power ultra-short laser device
Disclosed is a high power ultra-short pulsed laser device increasing pulse energy by using resonators. A pulsed laser device may comprise a first resonator making a pump beam resonate primarily and passing the pump beam which resonated through a first output mirror; and a second resonator comprising a first multiple reflection mirror and a second multiple reflection mirror. Also, the first multiple reflection mirror includes at least one first small area mirror, and the second multiple reflection mirror includes at least one second small area mirror, and the second resonator makes the laser beam delivered from the first resonator resonate by reflecting the laser beam repetitively. Therefore, the pulsed laser device may increase pulse energy without using a multi-stage amplifier so that a high power ultra-short pulsed laser beam can be generated. |
| US09431782B2 |
Current carrying systems and methods of assembling the same
A current carrying system for use in transporting electrical current between a plurality of electrical devices is provided. The current carrying system includes a busbar having a first axial end, a second axial end, an electrically conductive shaft extending from the first axial end to the second axial end, and at least one cooling feature defined in at least a portion of the electrically conductive shaft. The current carrying system also includes a casing that defines a busbar channel configured to receive the busbar such that the casing at least partially circumscribes the busbar. The current carrying system also includes an air vent defined by the at least one cooling feature and the casing, wherein the air vent is in flow communication with ambient air, and the cooling feature is configured to facilitate a flow of air from the ambient air through the air vent. |
| US09431779B1 |
Extension cord light source
An extension cord light source provides a source of light without additional cords or light units. A light source is attached or attachable to the end of an extension cord. The light source may be a light bulb-shaped source having multiple LEDs therein. Clear plastic encloses the devices therein and allows for multi-directional light beams. The LEDs may connected to a switch with multiple positions for controlling the amount of light. The extension cord lines pass through the bulb and into an outlet being a female plug. This combination thus eliminates the need for a drop light. A removable shade may be also attached to the bulb to prevent unnecessary light. A pilot lamp is included in the bulb to indicate that the power is present. The bulb may have a male plug therein that will accept the female plug of a conventional extension cord. |
| US09431777B2 |
Connector
A detector (60) configured to be pressed and moved by a second housing (40) in the process of connecting first and second housings (10, 40) and separate the second housing 40 from the first housing (10) when a connecting operation of the first and second housings is stopped halfway is mounted on the first housing (10). The detector (60) integrally includes a resilient arm (61) configured to apply a separation force to the second housing (40) in a direction to separate the second housing (40) from the first housing (10) by sliding on a guiding surface (27) in one of the first and second housings (10, 40) to be deflected and deformed in a direction intersecting a connecting direction of the first and second housings (10, 40) in the process of connecting the first and second housings (10, 40). |
| US09431776B2 |
Connector
A connector for being attached to a power-supply unit including a switching element includes a connecting terminal including an end portion connected to an output terminal in a casing of the power-supply unit, a housing fixed to the casing and enclosing at least a portion of the connecting terminal, a current sensor to detect a magnetic field generated by an electric current flowing through the connecting terminal, and a signal line for transmitting an output signal of the current sensor. The signal line includes an extension region with a predetermined length from one end on a side of the current sensor. The extension region extends in a direction orthogonal to a direction of electric current flowing through the connecting terminal. |
| US09431775B2 |
Connector with built-in electronic circuit board and method of manufacturing same
A connector with built-in electronic circuit board includes an electronic circuit board for a sensor, the electronic circuit board including a first connection terminal, an inner case housing the electronic circuit board, and an outer case having a chamber housing the inner case. The connector further includes a second connection terminal extending from inside the chamber to outside the outer case, a third connection terminal disposed in the chamber, and a cable connected to the sensor at one end thereof at outside the outer case and connected to the third connection terminal at the other end thereof. The inner case is sealed by resin in a state of the first connection terminal being exposed. The first connection terminal is connected to the second and third connection terminals. The chamber is closed by a lid. |
| US09431770B2 |
Shielded communication connectors and systems comprising shielded communication connectors
Embodiments of the present invention are directed to various designs of shielded connectors, systems using such connectors, and methods of improving connector connectivity. For example, in one embodiment, the present invention is a communication plug having plug sides, the communication plug comprising a plug housing and a plug shield. The plug housing and the plug shield forming a seam on the plug sides, wherein the seam has an oblique angle relative to a vertical axis of the communication plug. This feature may aid plug removal from a jack by helping to prevent the snagging of a jack tab by a plug seam. |
| US09431753B2 |
Connector with convenient installation
A cable end connector includes an insulative body, a number of terminals received in the insulative body, a spacer mounted behind the insulative body, and an insulative housing molded to enclose the inuslative body and the spacer. The spacer includes an intermediate chamfer at a mounting end thereof to prevent interference during mounting of the spacer to the insulative body. A stopping wall is disposed at two opposite sides of the chamfer to prevent molten plastics from flowing into the insulative body during molding the insulative housing. |
| US09431751B2 |
Connector having a pin guide for use with a printed circuit board
A connector having a pin guide and method are disclosed. The connector includes a housing, terminals and a pin guide. The terminals include securing sections and substrate mating ends. The securing sections are positioned to maintain the terminals in the terminal receiving recesses. The substrate mating ends extend from the housing. The pin guide is removably attached to the housing, the pin guide having terminal receiving cavities for receiving the substrate mating ends of the terminals therein. The method of assembly and installing a connector includes: inserting terminals into housing; bending a portion of the terminals which extend outward from the housing; and positioning a pin guide over the bent ends of the terminals, whereby the bent ends are retained in cavities of the pin guide. |
| US09431740B2 |
Method of assembling an electrical terminal assembly
A method of assembling an electrical terminal having a base and a spring member. The base is provided with a plurality of base beams. The spring member is provided with a plurality of spring beams. The spring member defines an axis such that the plurality of spring beams is spaced radially apart from the axis. The spring beams deflected radially outwardly. The base is inserted in the spring member to position the base beams adjacent to the spring beams. The spring beams are released such that the spring beams retract radially inwardly against the base beams. |
| US09431739B2 |
Conductive terminal with insulating leading-end
A terminal includes an insulating leading-end insulation portion (8) that is fixed to a conductive terminal main body (7) and that protrudes in front of a leading end of a terminal contact portion (72). The terminal contact portion (72) is formed in a cylindrical shape including a rod through-hole (71) penetrating in an axial direction, and the leading-end insulation portion (8) is formed as a part of an insulation member (82) including a penetrating rod portion (81) penetrating through the rod through-hole (71) and protruding to a back end side of the rod through-hole (71); and the leading-end insulation portion (8) and the back end side of the penetrating rod portion (81) are respectively engaged with respect to the terminal main body (7) in a removal direction to thereby fix the insulation member (82) into the terminal main body (7). |
| US09431732B1 |
Electrical plug connector
An electrical plug connector including a body having a cavity, an electrical connection portion on the body, a wire locking mechanism in the cavity, and a current transmitter electrically connecting the electrical connection portion and the wire locking mechanism. The body may include a cover pivotable from an open position to a closed position. |
| US09431728B2 |
Coaxial connector splice
A coaxial cable connector splice including a central conductor extending between opposed ends and an insulating structure interposed between the central conductor and an outer body. |
| US09431727B2 |
Terminal connection structure for electric wire
A terminal connection structure for an electric wire, the electric wire including an internal conductor which is covered with a first insulating cover (21) and an external conductor which is provided coaxially with the internal conductor to surround an outer circumference of the first insulating cover and covered with a second insulating cover, the terminal connection structure including: a first terminal which is connected to a part where the internal conductor is exposed; a second terminal which is connected to a part where the external conductor is exposed; and an insulating portion which is interposed between the first insulating cover and the second terminal. |
| US09431720B2 |
Connecting structure and connecting method of flat circuit body and terminal
A portion of a conductor of a flat circuit body is exposed from an insulating layer covering at least one of surfaces of the conductor. A terminal includes a bottom plate on which the exposed portion of the conductor is provided, and crimp claws which are raised at two side edges of the bottom plate so that the exposed portion of the conductor is disposed therebetween. A protective plate is provided on the exposed portion of the conductor, and has a strength so as not to be penetrated by the crimp claws when the crimp claws are crimped onto the protective member. The crimp claws are crimped onto the protective plate so that the terminal is crimped to the conductor in a state where the exposed portion of the conductor is in surface contact with the bottom plate. |
| US09431719B2 |
Contact pin
The invention relates to a contact pin, comprising an angular end section, which is in particular designed for connecting to a wire or plug, wherein the angular end section has an angular cross-section. According to the invention, the contact pin has a round end section that is opposite the angular end section and that is designed for soldering to a circuit board. The round end section has a cross-section that is round at least in some sections of the circumference. |
| US09431712B2 |
Electrically-small, low-profile, ultra-wideband antenna
An ultra-wideband, low profile antenna is provided. The antenna includes a ground plane substrate, a feed conductor, a top hat conductor, a shorting arm, and a ring slot. The feed conductor includes a first end and a second end. The first end is configured for electrical coupling to a feed network through a feed element extending from the ground plane substrate. The top hat conductor includes a generally planar sheet mounted to the second end of the feed conductor in a first plane approximately parallel to a second plane defined by the ground plane substrate. The shorting arm includes a third end and a fourth end. The third end is mounted to the top hat conductor, and the fourth end is mounted to the ground plane substrate. The ring slot is formed in the ground plane substrate around the feed element. |
| US09431710B2 |
Printed wide band monopole antenna module
A printed wide band monopole antenna module is provided. The module comprises: a substrate having a first surface, a ground terminal part formed on the first surface, and an antenna body disposed on the first surface opposite to the ground terminal part. The antenna body comprises: a first extending part having a first length, a second extending part having a second length, and a third extending part having a first width. The width of the second extending part is the first width plus a second width. The second extending part forms a connection with the first and the third extending part. The ratio of the first length to the second length is less than a first value. The ratio of the first length to the sum of the first and the second width is less than a second value. |
| US09431709B2 |
Artificial magnetic conductor antennas with shielded feedlines
An antenna system is described which is comprised of an artificial magnetic conductor (AMC), an antenna element, and a feed network comprised of shielded feedlines whose outer conductor, or shield, is routed through the substrate of the AMC. The feedline outer conductor is connected to both the substantially continuous conductive surface and the array of capacitive patches forming the AMC. The shielded feedline suppresses the excitation of undesired TM modes within the AMC substrate, results in a stable return loss over a frequency range associated with the AMC's high surface impedance and surface wave bandgap. |
| US09431707B2 |
Apparatus and method for wireless power transmission including a source resonator having a substantially uniform megnetic field
A source resonator for wirelessly transmitting power to a target device may include a magnetic field distribution adjusting unit that is configured to adjust the magnetic field generated by the source resonator. In one or more embodiments, the magnetic field distribution adjusting unit may adjust the magnetic field to be substantially uniform in a predetermined vicinity of the source resonator. For example, the magnetic field distribution adjusting unit may adjust the intensity of the magnetic field near the center of the source resonator to be substantially the same as the intensity of the magnetic field near an edge area of the source resonator. |
| US09431705B2 |
Antenna arrangement and device
An antenna arrangement of an electronic device and a device is disclosed. The antenna arrangement includes two radiator elements. The first radiator element of the two radiator elements is connected to a feed element. A second radiator element of the two radiator elements is a passive element and connected to a ground plane. The first radiator element is arranged to feed the second radiator element by radiating energy. |
| US09431703B1 |
Differential phase shifter assembly
A differential phase shifter assembly with n striplines positioned concentrically with one another, on the opposite stripline ends of which connecting points for connecting lines leading to radiators are provided, where n is a natural integer greater than or equal to 2. A feeding and/or tapping device is pivotable about a central and/or pivot axis, and is therefore pivotable over the plurality of striplines while establishing a primary capacitive coupling. A central feed serves to feed the feeding and/or tapping device. At least one to n−1 secondary capacitive couplings are additionally provided. The one or more secondary capacitive couplings are provided on the side of the feeding and/or tapping assembly facing the primary capacitive coupling. For the at least one additional secondary capacitive coupling, at least one additional branched feeding and/or tapping device is provided, which together with the feeding and/or tapping device is pivotable about the central and/or pivot axis. |
| US09431701B1 |
Dual antenna transfer switch system, method and apparatus
A system, methods, and apparatus for dual antenna transfer switching are disclosed. In an example embodiment, a dual antenna system includes antennas, antenna control units, a transfer switch, and a modem. For example, the transfer switch may transfer a connection between antennas based on changing satellite visibility, upon entering a preprogrammed blockage zone or an unexpected loss of satellite visibility. The transfer switch may receive GPS data from an external GPS unit and/or the antenna control units and buffer the GPS data to a modem. The transfer switch may provide a modem receive-lock signal to retarget a line of sight. The transfer switch may transfer the connection between the antennas based on satellite visibility including signal reception quality and/or a modem receive-lock status. The transfer switch may, based on a difference in antenna uplink transmission power, attenuate a higher power antenna to be balanced with a lower power antenna. |
| US09431700B2 |
Modal antenna-integrated battery assembly
A modal antenna is formed within a battery assembly for use with a portable electronic device. In certain embodiments, the antenna is printed on an exterior surface of a battery enclosure using a conductive ink. In other embodiments, the antenna is attached, or etched, on a substrate; the substrate may at least partially include a battery housing. The antenna can include an Isolated Magnetic Dipole (IMD) antenna, or other radiating structure. Active components, such as active tuning components, are optionally included in the antenna-integrated battery assembly for the purpose of tuning the antenna. |
| US09431697B2 |
USB cable antenna
There is provided a USB cable antenna which also uses a USB cable as an antenna that receives a high-frequency signal in a desired band, by connecting a metal shield of the USB cable to an ID terminal of a USB connector connected to the USB cable of a predetermined length connected to an information terminal device, connecting a high-frequency cutoff element having a high impedance for the high-frequency signal in the desired band to both ends of a power supply line and a ground line of the USB cable, and connecting a common mode choke having the high impedance for the high-frequency signal in the desired band to both ends of a transmission line of a differential signal of the USB cable. |
| US09431685B2 |
Battery arrangement for use in a motor vehicle
A battery arrangement for a motor vehicle has a battery housing (4) with battery cells (6, 8) arranged by a holding apparatus (14). The battery cells (6, 8) are connected electrically to one another via a cell connecting element (14). A cooling arrangement (20, 22, 24, 26) cools the battery cells (6, 8) with a cooling medium. The cooling arrangement has a first one flow space (20), a conveying device and a heat exchanger for the cooling medium. Cell poles (10, 12) of the battery cells (6, 8) are arranged on the cell connecting element (14) and a printed circuit board (18) is parallel to the cell connecting element (14). A second flow space (22) is formed between the printed circuit board (18) and the cell connecting element (14) and has openings (24) in the region of the battery cells (6, 8) arranged on the cell connecting element (14). |
| US09431682B2 |
Degradation protection of solid alkali ion conductive electrolyte membrane
The present invention provides an electrochemical cell having an negative electrode compartment and a positive electrode compartment. A solid alkali ion conductive electrolyte membrane is positioned between the negative electrode compartment and the positive electrode compartment. A catholyte solution in the positive electrode compartment includes a halide ion or pseudohalide ion concentration greater than 3M, which provides degradation protection to the alkali ion conductive electrolyte membrane. The halide ion or pseudohalide ion is selected from chloride, bromide, iodide, azide, thiocyanate, and cyanide. In some embodiments, the electrochemical cell is a molten sodium rechargeable cell which functions at an operating temperature between about 100° C. and about 150° C. |
| US09431681B2 |
High temperature sodium battery with high energy efficiency
A molten sodium secondary cell charges at a high temperature and discharges at a relatively lower temperature. The cell includes a sodium anode and a cathode. A sodium ion conductive solid membrane separates the cathode from the sodium anode and selectively transports sodium ions. A solar energy source includes a photovoltaic system to provide an electric charging potential to the sodium anode and the cathode and a solar thermal concentrator to provide heat to the cathode and catholyte composition to cause the molten sodium secondary cell to charge at a temperature in the range from about 300 to 800° C. The cell has a charge temperature and a charge voltage and a discharge temperature and a discharge voltage. The charge temperature is substantially higher than the discharge temperature, and the charge voltage is lower than the discharge voltage. |
| US09431680B2 |
Electric storage device, electric storage system, and manufacturing method thereof
An electric storage device includes: a rolled electrode assembly 10 formed by winding a positive electrode, a negative electrode, and a separator so as to have curved portions and linear portions; current collectors 7; and an electrolyte solution 3. A positive electrode substrate has at one end 10A an unformed portion 11E formed without a positive electrode mixture layer, and a negative electrode substrate has at the other end 10B an unformed portion 13E formed without a negative electrode mixture layer. The current collectors 7 are connected respectively to at least part of the linear portions in the unformed portion of the positive electrode at the one end 10A and that of the negative electrode at the other end 10B. The one end 10A in the positive electrode has a length greater than the winding length, and/or the other end 10B in the negative electrode has such a length. |
| US09431676B2 |
Electrode, method for manufacturing electrode, biplate assembly and bipolar battery
An electrode for a biplate assembly includes an active material made from a compressed powder 11, and a non-metal carrier 10. A biplate assembly 20 includes electrodes 27, 28 each having a non-metal carrier 10. A method is disclosed for manufacturing an electrode 13 having a non-metal carrier 10. An apparatus 30 is disclosed for manufacturing such an electrode 13. A bipolar battery includes at least one such an electrode 13. The non-metal carrier 10 is preferably a non-conductive carrier. |
| US09431671B2 |
Microbial fuel cell comprising a microprobe array
Provided is a microbial fuel cell (MFC). The MFC includes a microfluidic element having an inlet portion and an outlet portion for intake and discharge of a culture fluid containing cells and a microchannel portion for capturing the cells and interconnecting the inlet portion and the outlet portion, a microprobe-array element having microprobes as anodes for extracting electrons produced during a metabolic process of the cells, and delivering the extracted electrons to an external circuit outside the cells, and a cathode for delivering the electrons used in the external circuit to an electron acceptor outside the cells. The microprobes penetrate the microfluidic element and are inserted into a plurality of single cells captured by the microchannel portion when the microfluidic element and the microprobe-array element are coupled together. The microprobes are separated from the single cells when the microfluidic element and the microprobe-array element are separated from each other. |
| US09431670B2 |
High durability fuel cell components with cerium salt additives
A fuel cell membrane electrode assembly is provided comprising a polymer electrolyte membrane which comprises a polymer that comprises bound anionic functional groups, wherein the polymer electrolyte membrane additionally comprises cerium cations. In another aspect, a fuel cell membrane electrode assembly is provided comprising a polymer electrolyte membrane which comprises a polymer that comprises bound anionic functional groups, wherein at least a portion of the anionic functional groups are in acid form and at least a portion of the anionic functional groups are neutralized by cerium cations. In another aspect, a polymer electrolyte membrane is provided which comprises a polymer that comprises bound anionic functional groups, wherein the polymer electrolyte membrane additionally comprises cerium cations, and wherein the amount of cerium cations present is between 0.001 and 0.5 charge equivalents based on the molar amount of acid functional groups present in the polymer electrolyte, more typically between 0.005 and 0.2, more typically between 0.01 and 0.1, and more typically between 0.02 and 0.05. |
| US09431667B2 |
Cathode channel shutoff in a fuel cell
In at least one embodiment, a fuel cell comprising a cathode flow field and a strip is provided. The cathode flow field plate defines a plurality of cathode channels for receiving a first fluid from a cathode source when the fuel cell is in an operational state. The strip includes a flexible first portion positioned about the plurality of cathode channels, the flexible first portion for moving toward the plurality of cathode channels to prevent a flow of the first fluid therein when the fuel cell is in an inoperative state. |
| US09431665B2 |
Selectively coated bipolar plates for water management and freeze start in PEM fuel cells
A flow field plate for fuel cell applications includes an electrically conductive plate having a first surface defining a plurality of channels. An active area section and an inactive area section characterize the flow field channels. A hydrophobic layer is disposed over at least a portion of the inactive area section while a hydrophilic layer is disposed over at least a portion of the active area section. |
| US09431662B2 |
Fuel cell electrodes using high density support material
Methods of preparing fuel cells and fuel cell electrodes having catalyst with high density catalyst support are provided. One method of fabricating a fuel cell electrode comprises adjusting the gravimetric ratio of ionomer to catalyst support based on the density of the support material to optimize ionomer performance. |
| US09431660B2 |
Lithium battery with charging redox couple
In accordance with one embodiment, an electrochemical cell includes a negative electrode including a form of lithium, a positive electrode spaced apart from the negative electrode and including an electron conducting matrix, a separator positioned between the negative electrode and the positive electrode, an electrolyte including a salt, and a charging redox couple located within the positive electrode, wherein the electrochemical cell is characterized by the transfer of electrons from a discharge product located in the positive electrode to the electron conducting matrix by the charging redox couple during a charge cycle. |
| US09431656B2 |
Hybrid molten/solid sodium anode for room/intermediate temperature electric vehicle battery
A hybrid battery with a sodium anode is designed for use at a range of temperatures where the sodium is solid and where the sodium is molten. When the battery is at colder temperatures or when the vehicle is idle and needs to be “started,” the anode will be solid sodium metal. At the same time, the battery is designed such that, once the electric vehicle has been “started” and operated for a short period of time, heat is directed to the battery to melt the solid sodium anode into a molten form. In other words, the hybrid battery operates under temperature conditions where the sodium is solid and under temperature conditions where the sodium is molten. |
| US09431655B2 |
Antiomony and layered carbon network battery anode
A method is provided for fabricating an antimony anode. The method disperses antimony (Sb) particles in a layered carbon network using a process such as mechanical mixing, ball milling, stirring, or ultrasound sonication, forming a Sb/carbon composite. The Sb/carbon composite is mixed with a binder, forming a mixture, and the mixture is deposited on a current collector. Advantageously, the binder may be an aqueous (water soluble) binder. In one aspect, prior to dispersing the Sb particles in the layered carbon network, the Sb particles are coated with carbon. For example, the Sb particles may be dispersed in a solution including a polymer, where the solution may be an aqueous or organic. Alternatively, the Sb particles may be dispersed in a solution including a monomer. The monomer solution is polymerized to form polymer sheathed Sb core-shell structures, and then carbonized. Associated Sb anodes and Sb anode batteries are also provided. |
| US09431653B2 |
Structurally stable active material for battery electrodes
A process of producing active material for an electrode of an electrochemical cell includes providing lithium-intercalating carbon particles having an average particle size of 1 μm to 100 μm as component 1, providing silicon particles having an average particle size of 5 nm to 500 nm as component 2, providing a polymer or polymer precursor which can be pyrolyzed to form amorphous carbon and is selected from the group consisting of epoxy resin, polyurethane resin and polyester resin, as component 3, mixing components 1 to 3 in to a mixture and heat treating the mixture substantially in the absence of atmospheric oxygen at a temperature at which the pyrolyzable polymer or the pyrolyzable polymer precursor decomposes to form amorphous carbon. |
| US09431651B2 |
Composite material for a lithium ion battery anode and a method of producing the same
A composite material for a lithium ion battery anode and a method of producing the same is disclosed, wherein the composite material comprises a porous electrode composite material. Pores with carbon-based material forming at the pore wall are created in situ. The porous electrode composite material provide space to accommodate volumetric changes during battery charging and discharging while the carbon-based material improved the conductivity of the electrode composite material. The method creates pores to have a denser carbon content inside the pores and a wider mouth of the pores to enhance lithium ion distribution. |
| US09431650B2 |
Method of manufacturing anode active material with oxide coating on active particles
An anode active material including anode active material particles including silicon, tin, or both and at least partially coated with an oxide-containing film including an oxide of silicon, germanium, tin, or a combination of them formed by a liquid-phase method such as a liquid-phase deposition method. A region of the particles in contact with the electrolytic solution is covered with the oxide-containing film, to thereby improve the chemical stability of the anode and the charge-discharge efficiency. The thickness of the oxide-containing film is preferably within a range from 0.1 nm to 500 nm both inclusive. |
| US09431647B2 |
Secondary battery having a safety device
A high voltage battery for vehicles includes an electrode tab that is divided into a first part placed near a battery cell and a second part placed near a terminal. A pouch packages the battery cell therein. A housing is packaged in an interior of the pouch together with the battery cell and has an opening. A first part extension and a second part extension extend from the first part and the second part, respectively, that are inserted into the housing through the opening, and that come into contact with each other in the housing. A cushion is inserted in the housing and compresses the first part extension and the second part extension such that the first part extension and the second part extension come into close contact with each other. |
| US09431637B2 |
Method for preparing a solid-state battery by sintering under pulsating current
The present invention relates to a method for preparing a completely solid Li-ion battery having a solid state body wherein the battery is assembled in a single step by stacking at least one layer of a powder mix including a positive electrode active material and a solid electrolyte, at least one intermediate layer of a solid electrolyte and at least one layer of a powder mix including a negative electrode active material and a solid electrolyte, and simultaneous sintering of the three layers at a pressure of at least 20 MPa, under pulsating current. The invention also relates to the Li-ion battery obtained by such a method. |
| US09431635B2 |
Light-emitting component and method for producing a light-emitting component
A light-emitting component may include: an electrically active region, including: a first electrode; a second electrode; and an organic functional layer structure between the first electrode and the second electrode; and a thermotropic layer, which is arranged outside the electrically active region. |
| US09431634B2 |
Organic light emitting display device having improved light emitting efficiency
In an organic light emitting display device according to an embodiment of the present disclosure, a light extraction reduction preventing layer is disposed between a display unit disposed on a substrate and an encapsulation layer for protecting the display unit, and as a result, light emission efficiency may be improved by reducing an amount of light dissipating while light generated from an emission layer of the display unit is extracted to the outside. |
| US09431633B2 |
Organic light emitting diode display device
Disclosed is an organic light emitting diode display device having improved light extraction efficiency and display quality. The organic light emitting diode display device includes a plurality of sub-pixels including organic light emitting cells arranged in an inner side of a substrate, a groove formed between neighboring sub-pixels, and a light extraction pattern formed over an outer surface of the substrate. |
| US09431625B2 |
Organic light-emitting diode
An organic light-emitting diode (OLED). |
| US09431621B2 |
Metal oxide charge transport material doped with organic molecules
Doping metal oxide charge transport material with an organic molecule lowers electrical resistance while maintaining transparency and thus is optimal for use as charge transport materials in various organic optoelectronic devices such as organic photovoltaic devices and organic light emitting devices. |
| US09431619B2 |
Composition for insulator, insulator, and thin film transistor
An insulating composition includes a nanoparticle-polyorganosiloxane composite, a cross-linking agent, and a solvent, an insulator includes the insulating composition, and an electronic device includes the insulator. |
| US09431617B2 |
Phosphorescent compound and organic light emitting diode device using the same
The present invention provides a phosphorescent compound of following formula: wherein each of X1 and X2 is independently selected from substituted or non-substituted carboline, dibenzofuran, dibenzothiophene and fluorene. |
| US09431616B2 |
Phosphaphenanthrene-carbazole-based organic light-emitting compound, and organic light-emitting device comprising same
Provided are a phosphaphenanthrene-carbazole-based organic light-emitting compound having superior light emitting properties, and an organic light-emitting device including the same. |
| US09431609B2 |
Oxide film scheme for RRAM structure
The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode. |
| US09431608B2 |
Hybrid non-volatile memory device and method for manufacturing such a device
A method for manufacturing a hybrid non-volatile memory device includes forming first conductive pads; depositing a first conductive layer on a second area of the substrate; etching the first conductive layer to obtain second conductive pads, the second conductive pads having a section at their base smaller than at their top; protecting the upper face of the second conductive pads; oxidizing the substrate so that an insulating material layer covers the upper face of the first conductive pads and sides of the second conductive pads; depositing an oxide layer at the tops of the first conductive pads, resulting in memory elements of a first type supported by the first conductive pads; and forming memory elements of a second type at the tops of the second conductive pads. Each memory element of the second type is supported by one of the second conductive pads. |
| US09431602B2 |
Top electrode coupling in a magnetoresistive device using an etch stop layer
A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack. |
| US09431601B2 |
Magnetoresistive element with oxygen getting layer having enhanced exchange bias and thermal stability for spintronic devices
Magnetic element including a first magnetic layer having a first magnetization; a second magnetic layer having a second magnetization; a tunnel barrier layer between the first and the second magnetic layers; and an antiferromagnetic layer exchanged coupling the second magnetic layer such that the second magnetization is pinned below a critical temperature of the antiferromagnetic layer, and can be freely varied when the antiferromagnetic layer is heated above that critical temperature. The magnetic element also includes an oxygen gettering layer between the second magnetic layer and the antiferromagnetic layer, or within the second magnetic layer. The magnetic element has reduced insertion of oxygen atoms in the antiferromagnetic layer and possibly reduced diffusion of manganese in the second magnetic layer resulting in an enhanced exchange bias and/or enhanced resistance to temperature cycles and improved life-time. |
| US09431599B2 |
Non-volatile logic device
A non-volatile logic device, comprising: a first input element magnetizable along a first direction to impart or change a chirality of a domain wall traversing the first input element a second input element configured to transport the domain wall, a magnetization of the second input element along a second direction representing a second logical input; a bifurcated output section comprising a pair of output elements for receiving the domain wall from the second input element, a magnetization of at least part of the output elements being changeable by propagation of the domain wall along the output elements; and a non-magnetic conductive element; wherein the magnetization in an output element after propagation of the domain wall represents a value of a logical function selectable by passing an electrical current through the non-magnetic conductive element to induce a magnetic field of a desired magnitude and direction in the second input element. |
| US09431597B2 |
Piezoelectric laminate, surface acoustic wave device, thin-film piezoelectric resonator, and piezoelectric actuator
A piezoelectric laminate including a base and a first piezoelectric layer formed above the base and including potassium sodium niobate. The first piezoelectric layer is shown by a compositional formula (KaNa1-a)xNbO3, “a” and “x” in the compositional formula being respectively 0.1 |
| US09431594B2 |
Extremely low resistance compositions and methods for creating same
The invention pertains to creating new extremely low resistance (“ELR”) materials, which may include high temperature superconducting (“HTS”) materials. In some implementations of the invention, an ELR material may be modified by depositing a layer of modifying material unto the ELR material to form a modified ELR material. The modified ELR material has improved operational characteristics over the ELR material alone. Such operational characteristics may include operating at increased temperatures or carrying additional electrical charge or other operational characteristics. In some implementations of the invention, the ELR material is a cuprate-perovskite, such as, but not limited to BSCCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium. |
| US09431592B2 |
Submount with cavities and through vias for LED packaging
A wafer having a plurality of light-emitting diode (LED) submounts and a method for fabricating an LED submount are provided. Each of the plurality of LED submounts of the wafer includes: a substrate (201), including through vias (203a); an LED die (208) mounted in a cavity (204) on a first side of the substrate (201) and connected to the through vias (203a); a redistribution layer (205a) attached to a second side of the substrate (201) connected to the LED die (208) through the through vias (203a). The method includes providing a wafer as a substrate (201); providing a cavity (204) in the substrate (201) on a first side of the substrate (201); providing through vias (203a) in the substrate (201), providing a redistribution layer (205a) on the second side of the substrate (201), and mounting an LED (208) in the cavity (204), wherein the LED die (208) is connected to the redistribution layer (205a) through the through vias (203a). |
| US09431590B2 |
Ceramic based light emitting diode (LED) devices and methods
Light emitter devices, such as light emitting diode (LED) devices and related methods are disclosed. A light emitter device includes a ceramic based substrate, at least one LED chip disposed on the substrate, and a filling material. The ceramic substrate can include one or more surface features. The filling material can be disposed over and/or within a portion of the one or more surface features. Surface features can include one or more pedestals, trenches, holes, indentions, depressions, waves, and/or convexly or concavely curved surfaces. Surface features can improve optics of the LED device, for example, improving brightness, reflection, and/or light extraction associated with the device. Related methods are disclosed. |
| US09431589B2 |
Textured encapsulant surface in LED packages
A packaged LED device having a textured encapsulant that is conformal with a mount surface on which at least one LED chip is disposed. The textured encapsulant, which can be textured using an additive or subtractive process, is applied to the LED either prior to or during packaging. The encapsulant includes at least one textured surface from which light is emitted. The textured surface helps to reduce total internal reflection within the encapsulant, improving the extraction efficiency and the color temperature uniformity of the output profile. Several chips can be mounted beneath a single textured encapsulant. A mold having irregular surfaces can be used to form multiple encapsulants over many LEDs simultaneously. |
| US09431586B2 |
Ceramic conversion element, optoelectronic semiconductor element, and method for producing a ceramic conversion element
A ceramic conversion element includes a first ceramic layer having a first luminescent material, which transforms electromagnetic radiation of a first wavelength range into electromagnetic radiation of a second wavelength range. A second ceramic layer includes a second luminescent material, which transforms electromagnetic radiation of the first wavelength range into electromagnetic radiation of a third wavelength range. The first luminescent material and the second luminescent material are based on at least one inorganic compound containing oxygen and are different from one another. An optoelectronic component with a ceramic conversion element and a method for producing a ceramic conversion element are also specified. |
| US09431584B2 |
Light converting and emitting device with suppressed dark-line defects
Light emitting systems are described. Particularly, light emitting systems and light converting components utilized within these systems are described. The light emitting system and components are formed such that dark-line defects do not interfere with the light emitting system efficiency. |
| US09431583B2 |
Semiconductor light emitting device
A light emitting device is provide comprising a light emitting diode (LED) chip having a first main surface and a second main surface opposing the first main surface, and one or more side surfaces extending between the first main surface and second main surface. A plurality of electrodes is disposed on the first main surface. A wavelength conversion film is disposed on the second main surface. A mark is formed in the wavelength conversion film. The mark contains orientation information of the light emitting device, thereby enabling the light emitting device to be properly oriented on a receiving substrate. |
| US09431578B2 |
Semiconductor light emitting devices
In one example embodiment, a semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. The second conductivity-type semiconductor layer and the active layer having at least one contact hole exposing a region of the first conductivity-type semiconductor layer. The semiconductor light emitting device further includes at least one columnar structure disposed in the exposed region of the first conductivity-type semiconductor layer within the at least one contact hole. The semiconductor light emitting device further includes a first electrode disposed on the exposed region of the first conductivity-type semiconductor layer in which the at least one columnar structure is disposed, the first electrode being connected to the first conductivity-type semiconductor layer. The semiconductor light emitting device further includes a second electrode connected to the second conductivity-type semiconductor layer. |
| US09431573B2 |
Method and system for generating a photo-response from MoS2 schottky junctions
Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively. |
| US09431567B2 |
Semiconductor photo-detection device and radiation detection apparatus
On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other. The high-concentration n-type region is formed by diffusing an n-type impurity from the front side of the substrate so as to surround the p-type region as seen from the front side. The p-type region is formed by diffusing a p-type impurity from the front side of the substrate so as to surround the p-type region and high-concentration n-type region as seen from the front side. Formed on the front side of the n-type semiconductor substrate are an electrode electrically connected to the p-type region and an electrode electrically connected to the high-concentration n-type region and the p-type region. |
| US09431561B1 |
Method and system for providing a wind load resistant, tracking photovoltaic (PV) array
A wind load resistant, tracking photovoltaic solar array system may include a pivot support; at least one solar cell coupled to the pivot support; and a pivot arm coupled to the solar cell for providing transverse movement of the solar cell relative to a longitudinal axis of the pivot support. A transverse drive motor may be coupled to the pivot arm for rotating the pivot arm in response to control signals. A tube for housing the solar cell, pivot arm, and the transverse drive motor may also be included. A support structure may be coupled to the tube and for mounting the tube against another structure, such as a building rooftop. A longitudinal axis drive motor may be coupled to the tube and the support structure. The longitudinal axis drive motor may rotate the tube around a geometrical longitudinal axis of the tube in response to control signals. |
| US09431558B2 |
CIGS type compound solar cell
A CIGS type compound solar cell excellent in both productivity and conversion efficiency is provided. The CIGS type solar cell includes a CIGS light absorbing layer, a buffer layer and a transparent electrode layer provided in this order on a substrate. The buffer layer is made of a mixed crystal compound containing ZnO, MgO and ZnS being present at specific ranges respectively. |
| US09431551B2 |
Circuit arrangement and method of forming a circuit arrangement
A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate. The first doped region of the first conductivity type may extend from the first surface into the semiconductor substrate to form an electrically conductive connection with the first electrode. |
| US09431550B2 |
Trench polysilicon diode
Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench. |
| US09431544B2 |
Polysilicon thin-film transistor array substrate and method for preparing the same, and display device
The present invention provides a polysilicon thin-film transistor array substrate and a method for preparing the same, and a display device, wherein the method comprises a step of forming a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode of the polysilicon thin-film transistor, and a first electrode and a second electrode of a storage capacitor, and a gate line and a data line, wherein, the semiconductor layer and the first electrode of the storage capacitor are formed via a one-time patterning process, and the gate electrode, the gate line and the second electrode of the storage capacitor are formed via a one-time patterning process. By the solution of the invention, the number of mask plates used can be lowered, so that the process can be simplified, and the production cost can be lowered. |
| US09431539B2 |
Dual-strained nanowire and FinFET devices with dielectric isolation
A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions. |
| US09431533B2 |
Method to enable higher carbon co-implants to improve device mismatch without degrading leakage
An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least one of the angled carbon co-implant is greater than the implant energy of the boron halo implant. A total carbon dose of the angled carbon co-implants is at least 5 times a total boron dose of the boron halo implants. The NMOS transistor has a carbon concentration in the halo regions which is at least 5 times greater than the boron concentration in the halo regions. The co-implanted carbon extends under the gate of the NMOS transistor. |
| US09431530B2 |
Super-high density trench MOSFET
A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches. |
| US09431529B2 |
Confined semi-metal field effect transistor
Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal. |
| US09431527B1 |
Enhancement mode high electron mobility transistor
An enhancement mode HEMT, including: a substrate layer; a buffer layer; barrier layers; drain electrodes; reverse polarization semiconductor layers; source electrodes; an insulated gate dielectric; and a metal gate electrode The buffer layer is disposed on the substrate layer, and the barrier layers are disposed on the buffer layer. Interfaces between the buffer layer and the barrier layers are provided with first heterojunctions having a two-dimensional electron gas (2DEG) channel. The drain electrodes are disposed at one end of the upper surfaces of the barrier layers and form Ohmic contact with the barrier layers. The reverse polarization semiconductor layers are disposed on the upper surfaces of the barrier layers and are able to produce inversed polarization with the barrier layers. The interfaces between reverse polarization semiconductor layers and barrier layers are provided with second heterojunctions having two-dimensional hole gas (2DHG). |
| US09431526B2 |
Heterostructure with carrier concentration enhanced by single crystal REO induced strains
A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction. |
| US09431525B2 |
IGBT with bidirectional conduction
An IGBT device includes a drift region, a collector contact, an injector region, a pair of junction implants, a gate contact, and an emitter contact. The injector region includes a first surface in contact with the collector contact, a second surface opposite the first surface and in contact with the drift region, and at least one bypass region running between the first surface and the second surface. Notably, the at least one bypass region has a charge carrier that is different from that of the injector region. The pair of junction implants is in the drift region along a surface of the drift region opposite the injector region. The gate contact and the emitter contact are on the surface of the drift region opposite the injector region. |
| US09431524B2 |
Method of manufacturing IC comprising a bipolar transistor and IC
Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate (10) comprising a pair of first isolation regions (12) separated from each other by an active region (11) comprising a collector impurity said bipolar transistor; forming a base layer stack (14, 14′) over said substrate; forming a further stack of a migration layer (15) having a first migration temperature and an etch stop layer (20) over said base layer stack (14); forming a base contact layer (16) having a second migration temperature over the further stack, the second migration temperature being higher than the first migration temperature; etching an emitter window (28) in the base contact layer over the active region, said etching step terminating at the etch stop layer; at least partially removing the etch stop layer, thereby forming cavities (29) extending from the emitter window in between the base contact layer and the redistribution layer; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. An IC comprising such a bipolar transistor is also disclosed. |
| US09431521B1 |
Stress memorization technique for strain coupling enhancement in bulk finFET device
A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins. |
| US09431520B2 |
Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates
Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. |
| US09431519B2 |
Method of producing a III-V fin structure
A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate. |
| US09431517B2 |
Semiconductor device and method
Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices. |
| US09431514B2 |
FinFET device having a high germanium content fin structure and method of making same
A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate. |
| US09431513B2 |
Dummy gate structure and methods thereof
A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness. |
| US09431512B2 |
Methods of forming nanowire devices with spacers and the resulting devices
A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers. |
| US09431508B2 |
Simplified gate-first HKMG manufacturing flow
When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed. |
| US09431505B2 |
Method of making a gate structure
A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material. |
| US09431502B2 |
Display panel and display apparatus having the same
A display panel includes a substrate, an active layer, a gate insulating layer, a gate electrode structure, an insulating interlayer, a switching element, and a planarization insulating layer. The active layer includes a source region and a drain region, and is disposed on the substrate. The gate insulating layer is disposed on the active layer. The gate electrode structure includes a plurality of gate electrode layer which are at least partially overlapped with each other. The gate electrode structure is disposed on the gate insulating layer. The insulating interlayer covers the gate electrode structure. The switching element includes a source electrode and a drain electrode, and the source electrode and the drain electrode are in contact with the source region and the drain region, respectively. The planarization insulating layer covers the switching element. |
| US09431500B2 |
Integrated circuit device having defined gate spacing and method of designing and fabricating thereof
A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm2). |
| US09431499B2 |
Method of manufacturing a stress-controlled HEMT
A method of manufacturing a semiconductor device includes providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions, and forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material. |
| US09431498B2 |
Semiconductor device including first and second MISFETs
In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film. |
| US09431495B2 |
Method of forming SGT MOSFETs with improved termination breakdown voltage
A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the termination trench and performing a second etching to increase the depth of the active trench to a desired depth wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller than a depth difference between the initial depth of the active trench and the desired depth of the termination trench. |
| US09431490B2 |
Power semiconductor device and method
A power semiconductor device includes a semiconductor body having a first side, a second side opposite the first side and an outer rim. The semiconductor body includes an active region, an edge termination region arranged between the active region and the outer rim, a first doping region in the active region and connected to a first electrode arranged on the first side, a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side, a drift region between the first doping region and the second doping region, the drift region including a first portion adjacent to the first side and a second portion arranged between the first portion and the second doping region, and an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region. |
| US09431485B2 |
Formation of finFET junction
A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction. |
| US09431484B2 |
Vertical transistor with improved robustness
A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface. |
| US09431483B1 |
Nanowire and method of fabricating the same
A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire. |
| US09431481B2 |
Superjunction structures for power devices and methods of manufacture
In a general aspect, a power device can include an epitaxial layer of a first conductivity type, an active region, a termination region surrounding the active region, a plurality of trenches disposed in the epitaxial layer, and silicon material of a second conductivity type disposed in the plurality of trenches. The silicon material of the second conductivity type and a plurality of mesas defined in the epitaxial layer by the trenches, can define a plurality of concentric octagon-shaped pillars of alternating conductivity type, a first portion of the pillars being disposed in the active region and a second portion of the pillars being disposed in the termination region. Sidewalls of the plurality of trenches can define a first four legs and a second four legs of each of the pillars. The sidewalls can have a same crystallographic plane direction. |
| US09431480B1 |
Diluted drift layer with variable stripe widths for power transistors
A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions. |
| US09431479B2 |
High breakdown voltage semiconductor device having a resurf layer
In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part. |
| US09431478B2 |
Semiconductor device and method of fabricating the same
A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer. |
| US09431476B2 |
Semiconductor devices including capacitors and methods of manufacturing the same
A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern. |
| US09431473B2 |
Hybrid transformer structure on semiconductor devices
Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer. |
| US09431470B2 |
Display device
A display device has a plurality of pixels which are arranged on a substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter have a second color are provided. The second color is different from the first color. |
| US09431469B2 |
Organic light-emitting diode display
An organic light emitting diode (OLED) display includes: a first electrode around a center point of a virtual square; second electrodes around a first vertex and a second vertex diagonal to the first vertex of the virtual square, the second electrodes being separated from each other and with the center point of the virtual square interposed therebetween; third electrodes around a third vertex and a fourth vertex of the virtual square, the third electrodes being separated from each other and with the center point of the virtual square interposed therebetween; a pixel defining layer partially on the first electrode, the second electrodes, and the third electrodes, and partially exposing the first electrode, the second electrodes, and the third electrodes; and four spacers disposed as islands on the pixel defining layer and corresponding to four sides of the virtual square. |
| US09431463B2 |
Display apparatus
Provided are a display apparatus and a method of manufacturing the display apparatus. A color filter layer including at least a red color filter, a green color filter, and a blue color filter is disposed on a first substrate. A black matrix is disposed on the color filter layer. A color filter overlapped unit where the red, green and blue color filters are overlapped is disposed in a black matrix area corresponding to the black matrix. The color filter overlapped unit has a lower reflectivity with respect to an external light than the other color filters. The color filter overlapped unit is formed in the black matrix area, and the color filter overlapped unit is formed by overlapping the blue, red and green color filters in order, and, thus, can prevent mixing of colors and reduce reflection with respect to an external light. |
| US09431461B2 |
Transistor having a vertical channel
A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function. |
| US09431460B2 |
Embedded non-volatile memory
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation. |
| US09431455B2 |
Back-end processing using low-moisture content oxide cap layer
A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) is formed over at least one ILD layer. The cap layer serves as an etch-stop for the subsequently-formed metal layer of a next metallization layer by isolating the underlying ILD material from the plasma environment during aluminum over-etch, which significantly reduces the production and migration of hydrogen into front-end structures. |
| US09431454B1 |
Imaging apparatus
An imaging device includes a light source which irradiates an infrared light including one or more wavelength to a subject; a lens which forms an image of the infrared light transmitting the subject or being reflected from the subject; an infrared detection device including a plurality of pixels which are sensitive to the wavelength; and a filter array which is provided in proximity to the infrared detection device between the lens and the infrared detection device and including a plurality of wavelength filters having different transmission wavelengths. |
| US09431453B2 |
Fill factor opto-sensitive device
An opto-sensitive device, a pixel configured for use in an opto-sensitive device, and a method of operating an opto-sensitive device are disclosed. The opto-sensitive device illustratively includes a capacitor stacked on top of a photodetector, thereby improving the fill factor of the opto-sensitive device. Transparent properties of the capacitor for a wavelength of interest ensure that the incident light is completely or mostly absorbed only within the photodetector and not within the capacitor. |
| US09431448B2 |
Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus
A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer. |
| US09431439B2 |
Light detector
There is provided a light detector having a light-receiving unit including a light-receiving element of a photon-counting type that receives incident light and outputs a binary pulse indicating presence or absence of photon incidence, and an integrating unit that calculates an output value in which a total of pulse widths of pulses is integrated over a measurement period. |
| US09431437B2 |
Display panel and method of manufacturing the same
A display panel includes a gate electrode and a gate line on a substrate, a gate insulating layer and an active layer sequentially on the gate electrode and the gate line, a planarization layer which is on the substrate and compensates for a step difference between the substrate, and the gate electrode and the gate line, respectively, source and drain electrodes on the active layer overlapping the gate electrode and spaced apart from each other, a data line on the active layer and crossing the gate line, a protective layer which covers the planarization layer, the source and drain electrodes, and the data line, a contact hole defined in the planarization layer and partially exposing the drain electrode, and a pixel electrode on the protective layer and electrically connected to the drain electrode through the contact hole. |
| US09431430B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device having high electric characteristics and in which a capacitor is efficiently formed even if the semiconductor device has a miniaturized structure. In a top-gate (also referred to as staggered) transistor using an oxide semiconductor film as its active layer, a source electrode and a drain electrode has a two-layer structure (a first electrode film and a second electrode film). Then, a capacitor is formed using a film formed using a material and a step similar to those of the first electrode film, a gate insulating film, and a gate electrode. Accordingly, the transistor and the capacitor can be formed through the same process efficiently. Further, the second electrode is connected onto the oxide semiconductor film between a first electrode and a channel formation region of the transistor. Accordingly, resistance between source and drain electrodes can be reduced; therefore, electric characteristics of the semiconductor device can be improved. |
| US09431428B2 |
Display device
A display device capable of operating at high speed and with low power consumption is provided. A miniaturized display device occupying a small area is also provided. The display device includes a support; a display portion which includes a pixel; a light-blocking unit which is in the support and includes a light-blocking layer having a first opening overlapping with at least part of the pixel, and a movable light-blocking layer blocking light passing through the first opening; a transistor which is electrically connected to the light-blocking unit and includes an oxide semiconductor film; and a capacitor electrically connected to the transistor. |
| US09431427B2 |
Semiconductor device comprising oxide semiconductor layer
An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX. |
| US09431423B2 |
Semiconductor integrated circuit
Disclosed herein is a semiconductor integrated circuit including: a cell layout region including circuit cells subject to power control the supply and interruption of power to which is controlled by a power switch, and always-on circuit cell groups which are always powered after the activation; a main line laid out in the cell layout region and applied with a source or reference voltage; and first and second branch lines which branch from the main line in the cell layout region. |
| US09431421B2 |
Data line arrangement and pillar arrangement in apparatuses
Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD). |
| US09431417B1 |
Semiconductor structure and method for manufacturing the same
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of connecting portions. The stacks are disposed on the substrate. Each of the stacks comprises alternately-stacked conductive layers and insulating layers. The memory layers are disposed on sidewalls of the stacks, respectively. The channel layers are disposed on the memory layers, respectively, wherein each of the channel layers comprises a surface being exposed. The connecting portions connect the surface of each of the channel layers to the substrate, respectively. |
| US09431416B2 |
Vertical-type nonvolatile memory device and method of manufacturing the same
A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer. |
| US09431412B1 |
Semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a first array extending in a first direction, a second array extending in the first direction, and a second electrode film. The second array is arranged with the first array in a second direction crossing the first direction. The second electrode film provided between the first array and the second array. The second electrode film extends in the first direction. Each of the first array and the second array include a first structure, a second structure arranged in the first direction, a fourth insulating film provided between the first structure and the second structure, and a third insulating film provided between the first structure and the second electrode film, provided also between the first structure and the fourth insulating film. |
| US09431411B1 |
Efficient process for 3D NAND memory with socketed floating gate cells
A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory layer each has a series of socket components aligned to embed respective floating gates of a group memory cells. This structure allows reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. The memory is fabricated by using odd and even subarrays of vertical shafts on a multi-layer slab to create at different times odd and even socket components that overlap to form continuous word lines with socket components. In particular, with only three masks, the even memory cells are fabricated to have their word line socket component enlarged to overlap with those of the odd memory cells in order to form continuous word lines in the row direction. |
| US09431408B2 |
Methods for fabricating integrated circuits with a high-voltage MOSFET
Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process. |
| US09431406B1 |
Semiconductor device and method of forming the same
A semiconductor device and a method of forming the same are provided. At least two separated stacked structures and at least two hard mask patterns respectively on the stacked structures are formed on a substrate. A patterned mask layer is formed on the substrate. The patterned mask layer has an opening which exposes a portion of top surfaces of the hard mask patterns and a portion of the substrate between the stacked structures. The exposed portion of the substrate is removed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a trench in the substrate. An ion implantation process is performed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a doped region in the substrate around the trench. |
| US09431405B2 |
Method for forming flash memory devices
A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate; and forming a first polysilicon layer. The method also includes forming a hard mask layer; and forming a plurality of first openings exposing the first polysilicon layer in the hard mask layer and the first polysilicon layer. Further, the method includes forming a plurality of grooves by etching the semiconductor substrate along the first openings; and forming liner oxide layers by oxidizing the first polysilicon layer. Further, the method also includes forming shallow trench isolation structures by filling the first openings; and forming second openings by removing the hard mask layer and the non-oxidized first polysilicon layer. Further, the method also includes forming a tunnel oxide layer on a bottom of the second opening; and forming a floating gate on each of the tunnel oxide layers. |
| US09431403B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device provided with a capacitor that includes a plurality of cylindrical or columnar storage electrodes provided periodically on a semiconductor substrate, capacitor insulation films that cover the wall surfaces of the storage electrodes, and first conductive films provided on the capacitor insulation film and facing the storage electrodes, wherein the first conductive films of the capacitors adjacent in a first direction in which the storage electrodes are arranged are in contact with each other, and the first conductive films of capacitors adjacent in remaining other directions in which the storage electrodes are arranged are separated from each other. |
| US09431399B1 |
Method for forming merged contact for semiconductor device
A method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a protective layer on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a source/drain region on the second fin. |
| US09431398B2 |
Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering
According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip. |
| US09431393B2 |
Semiconductor device
A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a Schottky barrier diode formed in the first well; and a PN junction diode formed in the second well, with an impurity concentration of the PN junction thereof set higher than an impurity concentration of the Schottky junction of the Schottky barrier diode, and being connected antiparallel with the Schottky barrier diode. |
| US09431391B2 |
Gallium nitride hemt device with a mosfet in series coupled to diodes for protection of high-voltage
A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound semiconductor, a second element which is connected to the first element in series and is a transistor having withstand voltage between a source and a drain lower than withstand voltage of the first element, a first diode which is connected between a gate of the first element or a gate of the second element and a drain of the first element so that a cathode of the first diode is connected at the drain's side and has predetermined avalanche withstand voltage, and a first resistance connected to the gate to which the first diode is connected. The avalanche withstand voltage of the first diode is lower than breakdown voltage of the first element. |
| US09431388B1 |
Series-connected nanowire structures
Series-connected nanowire structures and methods of manufacture are disclosed. The structure includes a plurality of vertically stacked nanowires extending through a gate structure. The structure further includes a plurality of conductively doped contacts connecting to the stacked nanowires in a series configuration. |
| US09431387B2 |
Electrostatic discharge protection
A device comprising an electrostatic discharge protection structure, an ion sensitive field effect transistor (ISFET) having a floating gate, and a sensing layer located above the floating gate. The device is configured such that the electrical impedance from the sensing layer to the electrostatic discharge protection structure is less than the electrical impedance from the sensing layer to the floating gate. The device can be fabricated in a standard CMOS process. |
| US09431386B2 |
Current sensing of emitter sense insulated-gate bipolar transistor (IGBT)
A control circuit and method are disclosed for controlling a current sense Insulated-Gate Bipolar Transistor (IGBT). In particular, the current sense IGBT creates voltage spikes in a sense voltage as a result of normal switching operations. The control circuit creates a blank period so that the voltage spikes are ignored and false detections of short-circuit events are avoided. |
| US09431374B2 |
Semiconductor package
A semiconductor device includes a substrate having a first part and a second part, the first and second parts being continuous with each other and at different height levels, a first semiconductor chip overlapping the first and second parts of the substrate, an electrical interconnection structure connecting the first part of the substrate and the first semiconductor chip, a distance between the first part of the substrate and the first semiconductor chip being shorter than a distance between the second part of the substrate and the first semiconductor chip, and at least one electronic component in a space between the second part of the substrate and the first semiconductor chip. |
| US09431373B2 |
Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure, and corresponding three-dimensional integrated structure
A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations. |
| US09431370B2 |
Compliant dielectric layer for semiconductor device
Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used. |
| US09431367B2 |
Method of forming a semiconductor package
A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure. |
| US09431366B2 |
Selective area heating for 3D chip stack
A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively. |
| US09431356B2 |
Semiconductor device and method of forming the same
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material. |
| US09431355B2 |
Semiconductor structure and method for forming the same
Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer. |
| US09431353B2 |
Method for manufacturing a digital circuit and digital circuit
A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input has a predetermined defined logic state. |
| US09431351B2 |
Semiconductor package and manufacturing method of the same
The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer. |
| US09431343B1 |
Stacked damascene structures for microelectronic devices
A microelectronic device includes a dual-damascene interconnect structure and a single-damascene line structure directly on the dual-damascene interconnect structure. The dual-damascene interconnect structure and the single-damascene line structure may each include multiple line segments that are arranged in a brick wall pattern. The brick wall pattern may also be used with two or more single-damascene line structures. Various microelectronic devices and related fabrication methods are described. |
| US09431339B2 |
Wiring structure for trench fuse component with methods of fabrication
The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged. |
| US09431335B2 |
Molding compound supported RDL for IC package
A cylindrical molding compound supported RDL for IC package is disclosed wherein a central cavity is formed in the center of the molding compound. A plurality of metal pillar is embedded in the molding compound, a redistribution layer is configured on bottom of the plurality of metal pillar; at least one passive element such as a capacitor can be mounted in the central cavity. The bottom of the package is adaptive for at least one chip to mount so that the passive element is close to the chip and therefore simultaneous switching noise (SSN) can be reduced to a minimum at the initial first stage when a power is turned on. |
| US09431325B2 |
Semiconductor packaging structure
A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals. |
| US09431321B2 |
Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer
According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate. |
| US09431320B2 |
Methods and structures to facilitate through-silicon vias
In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad is such that the openings are laterally offset and substantially do not directly overlie or underlie one another. As seen in a top-down view, the through-silicon via etch may “see” a metal etch stop that extends continuously across the width of the via, although different portions of the etch stop may be distributed on different vertical levels due to the presence of openings in the metal pads. The openings in the metal pads facilitate integrated circuit fabrication their respective levels and the aggregate structure formed by the metal pads provides an effective etch stop for the through-silicon via etch. |
| US09431319B2 |
Exposed, solderable heat spreader for integrated circuit packages
An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the integrated circuit package. |
| US09431318B2 |
Electronic device
In an electronic device, a one-side heat radiation element and a two-side heat radiation element are disposed on a surface of a substrate adjacent to a heat sink. The one-side heat radiation element has a rear-side covered conductive portion and a rear-surface molded portion on the rear-side covered conductive portion adjacent to the heat sink, and radiates heat to the substrate. A surface of a rear-side exposed conductive portion of the two-side heat radiation element adjacent to the heat sink is exposed and the two-side heat radiation element radiates heat to the substrate and the heat sink. The rear-surface molded portion controls a limit position of the one-side heat radiation element toward the heat sink due to deformation of the substrate. A heat radiation gel is filled in between the rear-side exposed conductive portion and the heat sink to radiate heat from the two-side heat radiation element toward the heat sink. |
| US09431317B2 |
Power doubler amplifier module with improved solder coverage between a heat sink and a thermal pad of a circuit package
In one embodiment, an apparatus includes a printed circuit board, and a circuit package mounted to the printed circuit board. The circuit package has a thermal pad. A first heat sink structure of the module is associated with the printed circuit board and has a wall defining a contact surface that contacts and thermally couples with the thermal pad. The wall includes at least one aperture there-through. Solder paste is provided between the contact surface and the thermal pad to bond the contact surface to the thermal pad, with the at least one aperture being constructed and arranged to aid in outgassing of the solder paste. |
| US09431307B2 |
Semiconductor wafer evaluation method, semiconductor wafer evaluation device, and probe for semiconductor evaluation device
Provided is a semiconductor wafer evaluation method of performing an evaluation of electrical characteristics of a semiconductor wafer by bringing mercury into contact with a surface of the semiconductor wafer, the method including using a probe constituted of a fixed electrode having a tip end portion and a transparent covering portion that covers a portion other than the tip end portion of the fixed electrode, the fixed electrode being made of a metal having stronger wettability with respect to the mercury than the semiconductor wafer and the covering portion, and measuring the electrical characteristics by attaching the mercury to the tip end portion of the fixed electrode and then bringing the mercury into contact with the surface of the semiconductor wafer. |
| US09431306B2 |
Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process
A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region. |
| US09431305B1 |
Vertical transistor fabrication and devices
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains. |
| US09431304B2 |
Method and structure for metal gates
A semiconductor device having metal gates and methods of forming the same are disclosed. The method includes receiving a substrate, a dummy gate stack formed over the substrate, and a structure surrounding the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a trench in the structure. The method further includes forming a gate dielectric layer in the trench; forming a barrier layer over the gate dielectric layer; forming an oxide layer over the barrier layer; and forming a work function metal layer over the oxide layer. In embodiments, the method further includes removing the work function metal layer by an etchant containing phosphoric acid, wherein the oxide layer prevents the etchant from etching the barrier layer. |
| US09431303B2 |
Contact liners for integrated circuits and fabrication methods thereof
Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a first transistor having at least one of a p-type source region or a p-type drain region and a second transistor having at least one of an n-type source region or an n-type drain region, and the fabricating including: forming a contact liner at least partially over both the first transistor and the second transistor, the contact liner including a first contact liner material and a second contact liner material, wherein the first contact liner material is selected to facilitate electrical connection to the at least one p-type source region or p-type drain region of the first transistor, and the second contact liner material is selected to facilitate electrical connection to the at least one n-type source region or n-type drain region of the second transistor. |
| US09431300B1 |
MOL architecture enabling ultra-regular cross couple
A method of forming an ultra-regular layout with unidirectional M1 metal line and the resulting device are disclosed. Embodiments include forming first and second vertical gate lines, spaced from and parallel to each other; forming a M1 metal line parallel to and between the first and second gate lines; forming first, second, and third M0 metal segments perpendicular to the M1 metal line; connecting the first M0 metal segment to the M1 metal line and the second gate line; connecting the second M0 metal segment to the first gate line and the second gate line; connecting the third M0 metal segment to the first gate line and the M1 metal line; forming a first gate cut on the first gate line between the second and third M0 metal segments; and forming a second gate cut on the second gate line between the first and second M0 segments. |
| US09431298B2 |
Integrated circuit chip customization using backside access
An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements. |
| US09431292B1 |
Alternate dual damascene method for forming interconnects
After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial material portion is deposited in the at least one opening as a place holder for an interconnect structure later formed. Next, the sacrificial metal template layer is removed and a second dielectric material layer is formed to fill voids that were previously occupied by the sacrificial metal template layer. After removing the sacrificial material portion from the at least one opening, an interconnect structure is formed within the at least one opening. |
| US09431291B2 |
Method of making openings in a semiconductor device with reduced residue by transferring layers
According to an embodiment, a method for manufacturing a semiconductor device includes transferring a continuous second layer, forming a third layer, and removing the second layer. The second layer is transferred onto a first layer. The first layer has a first opening. The second layer covers the first opening to form a first air gap. The third layer is formed on the first layer. The third layer has a second opening. The second opening is positioned on the first air gap. The second layer is removed through the second opening. |
| US09431289B2 |
Method and structure to reduce FET threshold voltage shift due to oxygen diffusion
Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials. |
| US09431278B2 |
Backside rapid thermal processing of patterned wafers
Apparatus and methods of thermally treating a wafer or other substrate, such as rapid thermal processing (RTP) apparatus and methods are disclosed. An array of radiant lamps directs radiation to the back side of a wafer to heat the wafer. In one or more embodiments, the front side of the wafer on which the patterned integrated circuits are being formed faces a radiant reflector. In one or more embodiments, the wafer is thermally monitored for temperature and reflectivity from the side of the reflector. |
| US09431273B2 |
Method for manufacturing a resin-encapsulated semiconductor device
A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires for connecting together electrodes of the semiconductor element and the lead portions. Those members are partially encapsulated by a resin. A bottom surface part of the die pad portion and a lead bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulation resin. After a cutout part devoid of the encapsulation resin is formed above a lead upper end part, a plating layer is formed on the lead bottom surface part and the lead upper end part. |
| US09431269B2 |
Dual chamber plasma etcher with ion accelerator
The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber. The etching gas and ions react with the surface of the substrate to etch the substrate as desired. |
| US09431266B2 |
Double patterning method
Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate. |
| US09431265B2 |
Fin cut for tight fin pitch by two different sit hard mask materials on fin
Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of paired SIT spacers composed of different materials, portions of the first set of the paired SIT spacers can be selectively removed without adversely affecting the second set of the paired SIT spacers, even portions of both sets of the paired SIT spacers are exposed by the cut mask due to the different etching characteristics of the different materials. |
| US09431264B2 |
Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space. |
| US09431262B2 |
Method for polishing work and work polishing apparatus
The method of the present invention is capable of polishing a high hardness work at high polishing efficiency. The method comprises the steps of: pressing a surface of the work onto a polishing part of a rotating polishing plate; and supplying slurry while performing the pressing step. The method is characterized in that an activated gas, which has been activated by gas discharge, is turned into bubbles and mixed into the slurry. |
| US09431261B2 |
Removal of defects by in-situ etching during chemical-mechanical polishing processing
Technologies for a process used to reduce the height of a raised profile of a device. One or more raised profiles on one or more layers of a device are removed using a combined chemical-mechanical polishing/etching process. In some implementations, a protective layer is applied to a top layer of a device grown on a substrate. A combined chemical-mechanical polishing/etching process may commence whereby one or more raised profiles of the protective layer are removed through a planarization process, exposing at least a portion of a raised profile of a layer below the protective layer. Material may be removed using an etchant to reduce the height of the raised profile. |
| US09431254B2 |
One-time programmable memory and method for making the same
A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology. |
| US09431253B1 |
Fabrication flow based on metal gate process for making low cost flash memory
An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate. |
| US09431250B2 |
Deep well implant using blocking mask
Various methods include: forming an opening in a resist layer to expose a portion of an underlying blocking layer; performing an etch on the exposed portion of the blocking layer to expose a portion of an etch stop layer, wherein the etch stop layer resists etching during the etch of the exposed portion of the blocking layer; etching the exposed portion of the etch stop layer to expose a portion of a substrate below the exposed portion of the etch stop layer and leave a remaining portion of the etch stop layer; and ion implanting the exposed portion of the substrate, wherein the blocking layer prevents ion implanting of the substrate outside of the exposed portion. |
| US09431249B2 |
Edge termination for super junction MOSFET devices
In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N− type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure. |
| US09431248B2 |
High tilt angle plus twist drain extension implant for CHC lifetime improvement
An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor. |
| US09431246B2 |
Semiconductor device with low contact resistance SIC region
According to one embodiment, a semiconductor device includes a first semiconductor part and a conductive electrode. The first semiconductor part is made of SiC. The SiC contains a first element as an n-type or p-type impurity. The first semiconductor part has a first interface part. The first interface part is configured to have maximum area density of the first element. The c conductive electrode is electrically connected to the first interface part. |
| US09431245B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is equal to or less than a resolution of a lithography process, the patterns are apportioned among a plurality of masks such that in each of the masks the space between adjacent ones of the patterns is greater than the resolution, and a dual pattern is added to one of the masks. A semiconductor pattern is formed on a substrate using the mask(s) and the mask to which the dual pattern has been added. Patterns having a pitch equal to or less than the resolution may be formed on the semiconductor device. |
| US09431243B2 |
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures. |
| US09431242B2 |
PBNZT ferroelectric film, sol-gel solution, film forming method and method for producing ferroelectric film
To provide a PBNZT ferroelectric film capable of preventing sufficiently oxygen ion deficiency. The PBNZT ferroelectric film according to an embodiment of the present invention is a ferroelectric film including a perovskite-structured ferroelectric substance represented by ABO3, wherein the perovskite-structured ferroelectric substance is a PZT-based ferroelectric substance containing Pb2+ as A-site ions and containing Zr4+ and Ti4+ as B-site ions, and the A-site contains Bi3+ as A-site compensation ions and the B-site contains Nb5+ as B-site compensation ions. |
| US09431238B2 |
Reactive curing process for semiconductor substrates
In some embodiments, a reactive curing process may be performed by exposing a semiconductor substrate in a process chamber to an ambient containing hydrogen peroxide, with the pressure in the process chamber at about 300 Torr or less. In some embodiments, the residence time of hydrogen peroxide molecules in the process chamber is about five minutes or less. The curing process temperature may be set at about 500° C. or less. The curing process may be applied to cure flowable dielectric materials and may provide highly uniform curing results, such as across a batch of semiconductor substrates cured in a batch process chamber. |
| US09431235B1 |
Multilayer dielectric structures with graded composition for nano-scale semiconductor devices
Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure. |
| US09431234B1 |
Curable polymeric materials and their use for fabricating electronic devices
Disclosed are curable linear polymers that can be used as active and/or passive organic materials in various electronic, optical, and optoelectronic devices. In some embodiments, the device can include an organic semiconductor layer and a dielectric layer prepared from such curable linear polymers. In some embodiments, the device can include a passivation layer prepared from the linear polymers described herein. The present linear polymers can be solution-processed, then cured thermally (particularly, at relatively low temperatures) and/or photochemically into various thin film materials with desirable properties. |
| US09431233B2 |
Plasma lighting system with a metallic material in the bulb
A plasma lighting system includes a magnetron configured to generate microwaves, and a bulb in which a dose for generation of light using the microwaves and at least one metallic material for generation of thermal electrons are received. The metallic material reduces an electric field intensity required for electric discharge by discharging thermal electrons. In this way, the plasma lighting system reduces the time it takes to turn the light back on after the light is turned off. |
| US09431232B2 |
Short arc discharge lamp
A cathode for a discharge lamp in which an electron emitting section containing an easily electron emitting material at its end is provided that has simplified yet non-breakable structure and can reduce the manufacturing cost. A short arc discharge lamp includes an arc tube in which a cathode and an anode face each other and a xenon gas is enclosed. The cathode has an electron emitting section made from tungsten to which thorium is added as an easily electron emitting substance. The cathode also has an electrode body section made from tungsten to which no thorium is added. The electrode body section has a recess at a front end side. The electron emitting section has a circular truncated conical shape, a rear end side of the electron emitting section is received in the recess, and a front end side portion protrudes from the recess. |
| US09431230B2 |
Method of extracting ions with a low M/Z ratio from an ion trap
In a mass spectrometer, a method for trapping ions includes providing at least first and second multipole rod sets positioned in tandem, introducing a plurality of ions into the first rod set, applying an RF potential to at least one of said rod sets to generate a radial trapping potential within said rod sets, applying a radial DC potential to said first rod set so as to modulate said radial trapping potential set as a function of m/z of said ions, and applying a DC potential between said two rod sets to provide an axial bias potential between said two rod sets. The method can further comprise selecting an axial barrier potential to selectively extract ions having an m/z ratio less than a threshold from said first rod set into said second rod set. |
| US09431224B2 |
Chromatograph mass spectrometer
When performing an automatic MS2 analysis on a specimen containing components that include elements whose abundance ratio of stable isotopes is close, to prevent the same component that includes isotopes of differing masses to be successively selected as a precursor ion and allow the MS2 analysis of various components whose retention time to elution is close. As precursor selection conditions, the user is allowed to set in advance the time period for automatic exclusion and a m/z range (−p, q) with respect to any m/z. When the analysis is performed, a precursor selection unit selects a precursor according to a predetermined selection condition for the MS spectrum that was obtained and repeats the MS2 analysis on the precursor ion (m/z=M) for the number of times that is set. Thereafter, for a specified automatic exclusion period, ions falling in a m/z range of M−p to M+q are excluded from selection as a precursor. Since ions that are derived from a component whose difference from the original component from which the ion whose m/z=M is derived is the isotopes will fall in the excluded m/z range, such ions are not used as a precursor ion. |
| US09431220B1 |
Substrate processing apparatus and substrate processing system
A substrate processing apparatus may include a process chamber configured to accommodate a substrate having a metal film polished on a first insulating film and a second insulating film polished on the metal film; a process gas supply part configured to supply a process gas to the substrate; an activation part configured to activate the process gas; a computation part configured to compute processing data for adjusting a film thickness distribution of a stacked insulating film having the polished second insulating film and a third insulating film by adjusting a film thickness distribution of the third insulating film based on the film thickness distribution data of the polished second insulating film; and a control part configured to control the process gas supply part and the activation part to adjust the film thickness distribution of the stacked insulating film based on the processing data. |
| US09431217B2 |
Microwave plasma generating device and method for operating same
A microwave plasma generating device has a plasma chamber. A microwave generating device is provided outside of the plasma chamber, and the microwaves are coupled into the plasma chamber via a microwave in-coupling device. The microwave in-coupling device has an inner conductor which leads into the plasma chamber through a chamber wall of the plasma chamber, an insulating tube which encloses the inner conductor and separates the inner conductor from an interior of the plasma chamber, and an outer conductor which leads into the plasma chamber through the chamber wall and which is coaxial to the inner conductor. The outer conductor has an outer conductor end in the plasma chamber. The inner and outer conductors form a microwave line, an outlet of microwaves out of the microwave line is provided in the plasma chamber to generate microwave plasma in the interior of the plasma chamber. |
| US09431215B2 |
Chip packaging structures and treatment methods thereof
A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer. |
| US09431214B2 |
Ion implantation apparatus
An ion implantation apparatus includes a scanning unit, the scanning unit including a scanning electrode device that allows a deflecting electric field to act on an ion beam incident along a reference trajectory and scans the ion beam in a horizontal direction, and an upstream electrode device provided upstream of the scanning electrode device. The scanning electrode device includes a pair of scanning electrodes provided to face each other in the horizontal direction with the reference trajectory interposed therebetween and a pair of beam transport correction electrodes provided to face each other in a vertical direction perpendicular to the horizontal direction with the reference trajectory interposed therebetween. Each of the pair of beam transport correction electrode includes a beam transport correction inlet electrode body protruding toward the reference trajectory in the vertical direction in the vicinity of an inlet of the scanning electrode device. |
| US09431213B2 |
Scanning electron microscope, an interface and a method for observing an object within a non-vacuum environment
An interface, a scanning electron microscope and a method for observing an object that is positioned in a non-vacuum environment. The method includes: generating an electron beam in the vacuum environment; scanning a region of the object with the electron beam while the object is located below an object holder; wherein the scanning comprises allowing the electron beam to pass through an aperture of an aperture array, pass through an ultra thin membrane that seals the aperture, and pass through the object holder; wherein the ultra thin membrane withstands a pressure difference between the vacuum environment and the non-vacuum environment; and detecting particles generated in response to an interaction between the electron beam and the object. |
| US09431211B2 |
Hybrid electron microscope
A hybrid electron microscope includes: an electron source to emit an electron beam; a parabolic mirror including: a reflective surface; and an aperture to communicate the electron beam through the parabolic mirror; and a sample holder interposed between the electron source and the parabolic mirror such that the reflective surface of the parabolic mirror faces the electron source and the sample holder. A process for acquiring hybrid electron microscopy data includes: disposing a parabolic mirror in a chamber, the parabolic mirror including: a reflective surface; and an aperture to communicate an electron beam through the parabolic mirror; disposing a sample on a sample holder; interposing a sample holder between an electron source and the parabolic mirror such that the reflective surface of the parabolic mirror faces the electron source and the sample holder; producing the electron beam from the electron source; subjecting the sample to the electron beam; communicating the electron beam through the sample and the aperture of the parabolic mirror; and collecting imaging data of the sample in response to the subjecting the sample to the electron beam to acquire the hybrid electron microscopy data. |
| US09431210B2 |
Charged particle beam device with dynamic focus and method of operating thereof
A retarding field scanning electron microscope for imaging a specimen is described. The microscope includes a scanning deflection assembly configured for scanning an electron beam over the specimen, one or more controllers in communication with the scanning deflection assembly for controlling a scanning pattern of the electron beam, and a combined magnetic-electrostatic objection lens configured for focusing the electron beam, wherein the objective lens includes a magnetic lens portion and an electrostatic lens portion. The electrostatic lens portion includes an first electrode configured to be biased to a high potential, and a second electrode disposed between the first electrode and the specimen plane, the second electrode being configured to be biased to a potential lower than the first electrode, wherein the second electrode is configured for providing a retarding field of the retarding field scanning electron microscope. The retarding field scanning electron microscope further includes a voltage supply being connected to the second electrode for biasing the second electrode to a potential and being in communication with the one or more controllers, wherein the one or more controllers synchronize a variation of the potential of the second electrode with the scanning pattern of the electron beam. |
| US09431207B2 |
Rotating-anode X-ray tube assembly and rotating-anode X-ray tube apparatus
According to one embodiment, a rotating-anode X-ray tube assembly includes an X-ray tube, a stator coil, a housing, an X-ray radiation window, and a coolant. The housing includes a first divisional part which includes an X-ray radiation port and to which the X-ray tube is directly or indirectly fixed, and a second divisional part located on a side opposite to an anode target with respect to an anode target rotating mechanism and coupled to the first divisional part. A coupling surface between the first divisional part and the second divisional part is located on one plane, and is inclined to an axis, with exclusion of a direction perpendicular to the axis. |
| US09431205B1 |
Fold over emitter and collector field emission transistor
A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned. |
| US09431201B2 |
Micromechanical resonant switches and charge pumps
A circuit of N micromechanical resonant switches (resoswitches) is presented, which mimics a Dickson charge pump to amplify an input voltage to an output voltage of N plus 1 times the input voltage, while avoiding the diode voltage drop and breakdown voltage limitations of CMOS-based conventional charge pumps. Important aspects of successful charge pumping are: 1) the long cycle lifetime of resonant micromechanical switches, which has been shown to operate 173.9×1012 cycles, is orders of magnitude higher than non-resonant switches; 2) the use of gated-sinusoid drive excitation to allow a charging period independent of resoswitch resonance frequency; and 3) the use of resonance operation to lower required drive and DC-bias voltages to below the supply voltage. This mechanical charge pump obviates the need for custom high voltage CMOS for applications where large voltages are needed such as MEMS-based timing references, thereby allowing the use of virtually any CMOS process. |
| US09431193B2 |
Low current switch
A low current switch has a flexible movable contact that can be deflected by an actuator. In some implementations the switch may permit a low current switch to be manufactured using elements of a high current switch without requiring large amounts of precious metal. The flexible movable contact may be arranged as one or more cantilevers that are deflected using a rocking actuator. The actuator interacts with the movable contact in such a way as to provide tactile feedback to an operator comparable to a high current switch having a rigid movable contact. Also described are a set of low and high current switches, components of a low current switch, and a method of manufacturing a low current switch. |
| US09431186B2 |
Clutch device of gear transmission system of circuit breaker spring operating mechanism
A clutch device of a gear transmission system of a circuit-breaker spring operating mechanism includes an energy storage shaft, a large gear, and a small gear. At an energy storage holding position of the large gear, a toothless and special teeth area is arranged corresponding to the small gear. A clutch cam is provided in a cavity in the large gear at the area and a backward extended part and may be reset by a resetting spring. In the area, the large gear includes a first special tooth, a second special tooth, and a space between the first and second special teeth. When energy storage is completed, the small gear pushes the first special tooth to push the large gear and energy storage shaft to the energy storage holding position that is away from a friction dead zone, and the small gear is automatically disengaged from the large gear. |
| US09431185B2 |
Spring operation device for switchgear
A spring operation device for use in a switchgear includes an interlock bar, attached at its one end to a lock plate and includes a switch-on electromagnet that has a plunger provided with a flange portion. The lock plate is pushed by a lock member that is attached to a four-joint link and the position of the lock plate is changed by being rotated. During an opening operation of a switching contact, the other end of the interlock bar is arranged above the flange portion to stop the forward movement of the plunger of the switch-on electromagnet so as to prevent a switch-on trigger from rotating. During a closing operation of the switching contact, the other end of the interlock bar is arranged at a position that does not stop the plunger of the switch-on electromagnet from moving forward so that the switch-on trigger is allowed to rotate. |
| US09431177B2 |
Interface for communication between voltage domains
In one or more embodiments, circuitry is provided for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The capacitive coupling is provided by one or more capacitive structures having a breakdown voltage that is defined by way of the various components and their spacing. The capacitive structures each include three capacitive plates arranged to have two plates located in an upper layer and one plate located in a lower layer. A communication signal can be transmitted via the capacitive coupling created between the lower plate and each of the upper plates, respectively. |
| US09431176B2 |
Multilayer ceramic capacitor having multi-layered active layers and board having the same
A multilayer ceramic electronic component including: a ceramic body having a plurality of dielectric layers stacked therein; active layers including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body with the dielectric layers interposed therebetween; and first and second external electrodes formed on the both end surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. The active layers may include a first active layer including a ferroelectric layer and a second active layer including a paraelectric layer, the first and second active layers being alternately stacked. |
| US09431169B2 |
Primary power supply tuning network for two coil device and method of operation
This disclosure provides systems, methods and apparatus for connecting and operating an AC source to a load. In one aspect a power supply topology is provided which may be of particular use in the area of wireless power transfer. The topology allows for a single source to energize one or more conductive structures configured to generate a field, improving power transfer to a power receiver. |
| US09431167B2 |
Single-phase electric furnace transformer
A single-phase electric furnace transformer is provided according to the basic principle of the invention, comprising: a single magnetic core, said magnetic core comprising two side columns and at least one main column; a main transformer, comprising a first primary side winding and a first secondary side winding which are disposed on said at least one main column, wherein said first primary side winding consists of a first winding and a second winding which are connected in series with each other; and a voltage regulating autotransformer, which is disposed on one of two side columns of said magnetic core, and which comprises a second primary side winding and a second secondary side winding, wherein said second secondary side winding is an adjustable winding having on-load tap switch, and said adjustable winding is connected in series between the first winding and the second winding of said main transformer. The direct effect on the regulating winding and the regulating switch by the over-voltage of the grid can be avoided in the single-phase electric furnace transformer of the invention, and the voltage between two terminals of the primary winding of the main transformer can be reduced. Furthermore, the winding of the voltage regulating transformer is disposed on the side column of the main transformer in the invention, so that the material and the transformer loss can be reduced, and the installation space of the transformer can be decreased. |
| US09431166B2 |
Inductor and method of manufacturing the same
According to an embodiment, there is an inductor, including: a magnetic core; a winding formed around the magnetic core; a first resin provided between turns of the winding; and a second resin covering the winding and the first resin, wherein the second resin has higher filler content than the first resin. |
| US09431153B2 |
Armoured cable for transporting alternate current with reduced armour loss
An armored cable for transporting an alternate current at a maximum allowable working conductor temperature includes: at least two cores stranded together according to a core stranding lay and a core stranding pitch A; and an armor surrounding the at least two cores, the armor including one layer of a plurality of metal wires wound around the cores according to a helical armor winding lay and an armor winding pitch B, the helical armor winding lay having the same direction as the core stranding lay, the armor winding pitch B being from 0.4A to 2.5A and differing from the core stranding pitch A by at least 10%. |
| US09431152B2 |
Method of manufacturing electrical cable, and resulting product, with reduced required installation pulling force
Disclosed is type THHN cable having a reduced surface coefficient of friction, and the method of manufacture thereof, in which the central conductor core and insulating layer are surrounded by a nylon sheath. A high viscosity, high molecular weight silicone based pulling lubricant for THHN cable, or alternatively, erucamide or stearyl erucamide for small THHN gauge wire, is incorporated, by alternate methods, with the nylon material from which the outer sheath is extruded, and is effective to reduce the required pulling force on the cable during installation. |
| US09431150B2 |
Particle loaded, fiber-reinforced composite materials
A composite material includes a plurality of fibers embedded in a metal matrix. The composite material further includes a plurality of particles disposed in the metal matrix. At least 25% of the fibers contact or are spaced less than 0.2 micrometers from an adjacent fiber within the metal matrix. |
| US09431149B2 |
Device for reducing the corona effect
A device in connection with the corona effect, which is applicable in particular to connection nodes between conductor tubes of a power substation, and which includes an electrically conductive primary filamentous element wound onto itself forming an enveloping figure. |
| US09431148B2 |
Thick film resistive heater compositions comprising Ag and RuO2, and methods of making same
Thick film resistor paste compositions, and methods for making the thick film compositions are disclosed. The compositions include a resistor composition dispersed in an organic vehicle. The resistor composition has 3 to 60% by weight RuO2 conductive material, 5 to 75% by weight Ag conductive material, 15 to 60% by weight glass frit and optionally up to 10% by weight copper oxide or precursor thereof, and up to 20% by weight bismuth oxide or precursor thereof. Optionally the glass is (by weight) 25-45% SiO2, 2-15% Al2O3, 0-3% ZrO2, 0-8% B2O3, 5-15% CuO, 0-8% BaO, 0-3% P2O5, and 20-50% Bi2O3. The resistor composition when printed to a dry thickness and fired at a temperature between 750° C. and 950° C. achieves a sheet resistivity between 10 and 10,000 milliohms/square and a hot temperature coefficient of resistivity of 1000 ppm/C or higher. The fired resistor composition may achieve a resistance thickness ratio (Rtr) value between 0.75 and 1.50. |
| US09431147B2 |
Thermoformable polymer thick film transparent conductor and its use in capacitive switch circuits
This invention is directed to a polymer thick film transparent conductor composition that may be used in applications where thermoforming of the base substrate occurs, e.g., as in capacitive switches. Polycarbonate substrates are often used as the substrate and the polymer thick film conductive composition may be used without any barrier layer. Depending on the specific design, the thermoformable transparent conductor may be below or on top of a thermoformable silver conductor. Thermoformable electric circuits benefit from the presence of an encapsulant layer over the dried polymer thick film transparent conductor composition. The electrical circuit may be subsequently subjected to an injection molding process. |
| US09431146B2 |
Battery electrodes and methods of manufacture
This disclosure relates to compositions and methods of manufacture of electrodes for batteries, including rechargeable lithium batteries, wherein at least one electrode comprises an electroactive material and a malleable metal. The electrode may be substantially free of other conductive additives and organic binders. Manufacture of the electrode may be performed without solvent or sintering. |
| US09431145B2 |
Transistors and methods for making them
A semiconductor composition which comprises a soluble polyacene semiconductor and a polymeric semiconducting binder the binder having a permittivity greater than 3.4 at 000 Hz. The charge mobility of the semiconducting binder when measured in a pure state is greater than 10−7 cm2/Vs and more preferably greater than 10−6 cm2/Vs. Organic thin film transistors in which the source and drain electrodes are bridged by the semiconductor composition have desirable properties of reproducibility and charge mobility. The organic semiconducting composition can be applied by solution coating. |
| US09431144B2 |
Indium-containing oxide film and preparing method thereof
The present invention relates to an indium oxide film formed by chemical vapor deposition or atomic layer deposition, or to an oxide film containing indium, and to a method for forming same. By chemical vapor deposition or atomic layer deposition, wherein an indium material that is a liquid at room temperature is used, an oxide film containing indium can be formed on a substrate having a large area, and particularly a substrate for manufacturing a display device. |
| US09431141B1 |
Reconfigurable liquid attenuated collimator
A reconfigurable radiographic aperture mask collimator apparatus includes a body portion configured to receive an attenuating liquid having a first attenuation value per unit volume. The apparatus further includes a grid portion mated to a face of the body portion and a plurality of passageways each having a cross sectional area and a length. The plurality of passageways is disposed within the grid portion. A plurality of plugs is slidably disposed within the plurality of passageways, and each of the plurality of plugs has a second attenuation value per unit volume less than the first attenuation value. One of the plurality of passageways is filled with a column of attenuating liquid that is coincident with an end of the one of a plurality of plugs contained therein, and wherein the column substantially conforms to the cross sectional area. |
| US09431140B2 |
Optimized multi-pinhole collimator for dual-purpose clinical and preclinical imaging
A multi-pinhole collimator is formed by calculating a projection size (D) for different pinhole numbers (n) for a predetermined field-of-view (FOV) (d) by arranging a plurality of projections into a pattern. A pattern is selected which utilizes a whole detector with maximized packing density, minimum truncation to provide a projection overlap below a predetermined limit. The number of pinholes is modified to calculate a collimator length, a corresponding acceptance angle and aperture size. Sensitivities for individual pinholes are added to obtain a total sensitivity for a given pinhole number, and an optimized multi-pinhole configuration is obtained by maximizing the total sensitivity for a predetermined target resolution (Rt) and field-of-view (FOV) (d). |
| US09431139B2 |
Method of utilizing nuclear reactions of neutrons to produce primarily lanthanides and/or platinum metals
The method according to the invention is accomplished via neutrons produced in a nuclear reactor and moderated to thermal energy level in such a way that a target to be irradiated can also be arranged outside of the reactor shell, within a cassette and/or a container suitable for this purpose. This solution can remarkably increase the production capacity, but can be applied for irradiation channels as well. The disclosure teaches the production of lanthanides and platinum metals, however, other species, e.g. Re, can also be produced. In the technological process the target (mother element) is commercially less valuable than the product (daughter element) prepared therefrom via (n, γ) nuclear reaction. The product—practically the alloy of the mother element and daughter element(s)—can be fully separated into its constituents, element by element, by means of prior art techniques, and can be processed. The thus obtained product, after retention (that is, after normalizing the radiation level), can be made use of. The exemplified daughter elements are Pm, Eu, Tm, Lu; and Rh, Os; and Re. When Os is produced, Re takes the role of the mother element. In certain products other daughter elements also form, such as e.g. Tc, as it is discussed in the specification. |
| US09431134B1 |
Structure of top nozzle for nuclear fuel assembly
Disclosed herein is a joint structure between a top nozzle and a guide thimble. The joint structure includes an outer guide post, an inner-extension tube head, an inner-extension tube body, a wedge and the guide thimble. The outer guide post is provided with an external thread formed on a lower end thereof. The inner-extension tube head includes an annular retaining part formed on an upper end thereof. An internal thread is formed on a medial portion of the inner-extension tube head. An external thread is formed on each of upper and lower ends of the inner-extension tube body. A stop protrusion is provided under a lower end of the wedge. The wedge is welded to the inner-extension tube body after the top nozzle has been joined with the guide thimble. A stop protrusion receiving depression is formed in the guide thimble. |
| US09431132B2 |
Data managing method, memory control circuit unit and memory storage apparatus
A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command. |
| US09431131B2 |
Timing-drift calibration
The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device. |
| US09431126B2 |
Non-volatile memory program algorithm device and method
A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold. |
| US09431125B2 |
Method and system for adaptive setting of verify levels in flash memory
A system and method for computing MLC flash memory cell programming parameters to dynamically adjust verify voltage levels is provided. The method may use an iterative guess and check process that will result in a distribution of states, specifically a cell voltage distribution (CVD) that minimizes the cell error rate in cells encoded in interleaved error correction code (ECC) mode, and that balances the bit error rate between pages in cells encoded in non-interleaved ECC mode. |
| US09431121B2 |
Read voltage adjustment
The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can include a memory array and a controller coupled to the memory array. The controller is configured to adjust a read voltage used to access a portion of the memory array based on a length of time since a last WRITE operation to the portion. |
| US09431119B2 |
Adjustable read time for memory
Apparatuses, systems, methods, and computer program products are disclosed for controlling a read time of an electronic memory device. A method includes reading data from an integrated circuit of storage using a read time for the integrated circuit of storage. A method includes adjusting a read time for an integrated circuit of storage. A method includes reading data from a same integrated circuit of storage using an adjusted read time for the integrated circuit of storage. |
| US09431117B2 |
Memory system and read reclaim method thereof
A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation. The read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area. |
| US09431113B2 |
Data storage system with dynamic erase block grouping mechanism and method of operation thereof
Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block. |
| US09431112B2 |
Semiconductor memory device including strings including memory cell transistors
A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong. |
| US09431111B2 |
One time programming memory cell, array structure and operating method thereof
A one time programming memory cell includes a transistor, a first varactor, and a second varactor. The transistor has a gate terminal, a source terminal and a drain terminal. The gate terminal of the transistor is connected with a word line. The source terminal of the transistor is connected with a bit line. A first end of the first varactor is connected with the drain terminal of the transistor. A second end of the first varactor is connected with a first program line. A first end of the second varactor is connected with the drain terminal of the transistor. A second end of the second varactor is connected with a second program line. |
| US09431110B2 |
Column address decoding
Methods, memories and systems to access a memory may include generating an address during a first time period, decoding the address during the first time period, and selecting one or more cells of a buffer coupled to a memory array based, at least in part, on the decoded address, during a second time period. |
| US09431109B2 |
Parallel bitline nonvolatile memory employing channel-based processing technology
Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node and a drain node. The gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory. A channel-based processing component programs the memory cell and inhibits programming of a second memory cell on the wordline of the memory. The channel-based processing component also grounds the local source line and the local data line in conjunction with programming the memory cell, and floats a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell. |
| US09431106B1 |
Ternary content addressable memory (TCAM) with magnetic tunnel junction (MTJ) devices
A ternary content addressable memory (TCAM) cell is coupled to a first word line and a first match line and includes a first data storage portion coupled to a first search line, a second data storage portion coupled to a complement of the first search line, and a resistor divider portion including two resistive elements coupled in series with the first and second data storage portions of the first TCAM cell. The first and second data storage portions of the first TCAM cell are coupled to a first supply voltage and include two resistive elements coupled in parallel. |
| US09431101B2 |
Resistive devices and methods of operation thereof
In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period. |
| US09431098B1 |
Structure for reducing pre-charge voltage for static random-access memory arrays
A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level. |
| US09431097B2 |
Volatile/non-volatile SRAM device
A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. |
| US09431096B1 |
Hierarchical negative bitline boost write assist for SRAM memory devices
A memory device having a plurality of banks of memory cells may be provided. Each memory cells may be interconnected via a local write bit-line and a complementary local write bit-line to a local write bit-line buffer circuit. The local write bit-line buffer circuit may be connected via a global write bit-line and a complementary one to a negative bias write assist circuit. The memory device may also comprise an address decoder separately connected to the local write bit-line buffer circuits. The address decoder may comprise a generating unit for enabling exactly one local write enable signal for a respective one of said local write bit-line buffer circuits. The local write bit-line buffer circuit may be adapted for generating local write data on said local write bit-line in response to receiving global write data on said global write bit-line when its local write enable signal is enabled. |
| US09431090B2 |
Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift. |
| US09431089B2 |
Optimizing power in a memory device
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. |
| US09431088B1 |
Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture
A plurality of semiconductor memory devices on a multi-chip package is disclosed. Each semiconductor device may include a plurality of through vias and a plurality of capacitance enhanced through vias. The through vias may provide an electrical connection for signals that may transition between logic states. The capacitance enhanced through vias may provide an electrical connection from a first side to a second side of the respective semiconductor device for transmission signals that remain substantially stable such as reference voltages, power supply voltages or the like. In this way, noise may be reduced and a reservoir of charge for circuits that provide a load for reference voltages and/or power supply voltages may be provided. |
| US09431081B2 |
Memory device
A memory device includes a plurality of normal word lines arranged at a first distance from each other, a redundant word line arranged at a second distance, which is greater than the first distance from a normal word line adjacent to the redundant word line, among the normal word lines, and a word line control unit suitable for selectively activating the normal word lines, and replacing a frequently activated word line with the redundant word line when the frequently activated word line is detected. |
| US09431078B2 |
Semiconductor storage device and control method thereof
According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal. |
| US09431077B2 |
Dual host embedded shared device controller
Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data. |
| US09431069B2 |
Management method for nonvolatile memory system following power-off
A management method for a memory system executes a first memory system management sequence upon determining that the memory system was normally powered off, and a second sequence upon determining that the memory system was abnormally powered off. The first sequence allows immediate execution of a program operation at a valid data page location extracted from stored metadata, while the second sequence allows execution of a program operation only after programming dummy data to at least one erroneous page. |
| US09431066B1 |
Circuit having a non-symmetrical layout
A circuit comprises a first voltage line, a second voltage line parallel to the first voltage line, and a bit line between the first voltage line and the second voltage line. The bit line is separated from the first voltage line by a minimum distance allowed by a design rule. The bit line is closer to the first voltage line than to the second voltage line. A first capacitance value between the bit line and the first voltage line is different than a second capacitance value between the bit line and the second voltage line. |
| US09431065B2 |
Semiconductor integrated circuit
A semiconductor integrated circuit that exhibits an enhanced surge withstand voltage of a nonvolatile memory and has a reduced chip area, having a nonvolatile memory and a Zener diode connected in parallel between a write terminal and a ground terminal. The nonvolatile memory is connected to the write terminal by a write terminal line and to a common connection point by a first ground line. The cathode of the Zener diode is connected to the write terminal line. The anode of the Zener diode is connected to the specified connection point by a second ground line. The first ground line and the second ground line are connected to the specified connection point. |
| US09431064B2 |
Memory circuit and cache circuit configuration
A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals. |
| US09431060B2 |
Mobile terminal and controlling method thereof
A mobile terminal and controlling method thereof are disclosed, which facilitates a terminal to be used in further consideration of user's convenience. The present invention includes a touchscreen, a memory, and a controller outputting a play screen of a video to the touchscreen, the controller, if receiving a touch drag input to the outputted plays screen of the video, activating a memo function of saving a touch path of the touch drag input as a writing memo, the controller recording the outputted play screen of the video while the memo function is activated. Accordingly, while a mobile terminal plays a video, a user interface for enabling a user to input a memo more quickly and conveniently can be provided advantageously. |
| US09431051B1 |
Systems and methods for acquisition phase gain modification
Systems and methods relating generally to data processing, and more particularly to adjusting gain parameters in relation to data processing. |
| US09431049B2 |
Load balancing and space efficient big data tape management
A tool for space efficient tape management. The tool retrieves one or more tapes from one or more tape library frames in a first tape library. The tool inserts the one or more tapes into the one or more tape library frames in the first tape library. The tool transfers the one or more tapes from the one or more tape library frames in the first tape library to one or more tape library frames in a second tape library. |
| US09431048B2 |
Detection of data in burst cutting area of optical disk
An apparatus generates outgoing data to be provided on an optical disk in a burst cutting area. The burst cutting area further comprises markings which cause a marking frequency spectrum when reading out the burst cutting area. The apparatus comprises a channel coder which receives processed data and supplies the outgoing data having an outgoing data frequency spectrum with suppressed DC-content. The apparatus further comprises a data processing device which generates the processed data to obtain an outgoing frequency spectrum wherein a frequency component causing interference with a low frequent component of the markings is suppressed or not present. |
| US09431045B1 |
Magnetic seed layer used with an unbalanced soft underlayer
A magnetic media is described including a substrate, an unbalanced soft under layer (SUL), a magnetic seed layer, which may consist of one or more of NiWxCoy, NiWxCoyAlz, NiVaCob, NiVaCobAlc, NiWxVaCob, and NiWxVaFeb, and a magnetic recording layer. |
| US09431044B1 |
Slider having shock and particle resistance
A slider for a hard disk includes a leading structure having a first air bearing surface portion, a trailing structure having a second air bearing surface portion, and a cavity between the leading structure and the trailing structure. The leading structure has one or more interior walls defining a pit therein. A hard disk drive includes a rotatable magnetic recording disk and the slider. |
| US09431041B1 |
Comb structure for a disk drive suspension piezoelectric microactuator operating in the D33 mode, and method of manufacturing the same
A microactuator assembly is formed by depositing PZT material over electrode gaps, the electrode gaps being defined by the spaces between interleaved fingers of metal that define alternating plus and minus electrodes. The PZT material is hardened and poled. The PZT material may be deposited and poled either as isolated islands of PZT material across respective electrode gaps, or as a continuous sheet of PZT material with localized areas of that material being poled and then activated. The individual PZT elements are arranged such that successive PZT elements extend in the same direction as across the electrode gaps. The resulting microactuator assembly acts in the d33 direction of the PZT elements. The electrodes have raised or recessed features such as ribs or castellations, with the PZT material mating with those features, thus anchoring the PZT material to the electrodes. |
| US09431039B1 |
Multiple sensor array usable in two-dimensional magnetic recording
A method and system provide a magnetic transducer including a first shield, a plurality of read sensors, and a second shield. The read sensors are between the first shield and the second shield. The read sensors have a plurality of widths in a track width direction and are separated by at least one distance in a down track direction. The down track direction is perpendicular to the track width direction. |
| US09431036B2 |
Heat-sinks for optical near-field transducers
Thermal energy is generated within an optical NFT when in operation within a HAMR head. A heat-sink assembly within the HAMR head extracts thermal energy from the optical NFT and transmits the thermal energy via convection to air surrounding the HAMR head, radiation to surfaces adjacent to the HAMR head, and/or conduction to other parts of the HAMR head. The thermal energy generated within the optical NFT is conducted to the heat-sink. An air-bearing surface of the heat-sink convectively transfers at least some of the thermal energy to air passing between the air-bearing surface and a surface of an adjacent magnetic medium. Further, some of the thermal energy may also radiatively transfer from the air-bearing surface to the magnetic medium. |
| US09431034B1 |
Corrosion resistance in air bearing surfaces
A method includes identifying a microelectronic device located at an air bearing surface. The method further includes identifying a resistive heating element electrically isolated the said microelectronic device; applying a bias current through the resistive heating element to generate localized heat to heat the microelectronic device; identifying a predetermined humidity threshold and a separation distance between the microelectronic device and the resistive heating element in at least one dimension; measuring an ambient temperature at the air bearing surface; measuring an ambient relative humidity at the air bearing surface; determining an effective temperature; and adjusting the bias current to heat the microelectronic device to the effective temperature. The resistive heating element is one of a plurality, and at least two of the plurality of resistive heating elements are powered from a common source such that at least two of the resistive heating elements are commonly controllable via a common source. |
| US09431033B1 |
Corrosion resistance in air bearing surfaces
A structure includes an air bearing surface including a plurality of material layers arranged in at least one dimension on the air bearing surface. The structure further includes a microelectronic device and a resistive heating element, which each include at least one of the plurality of material layers. The resistive heating element is electrically isolated from the microelectronic device. The microelectronic device is heated by said resistive heating element. Optionally, a structure includes a tape reader or a tape writer, located at an air bearing surface. A resistive heating element is electrically isolated from the tape reader or writer and heats the tape reader or the tape writer. Optionally, a method includes identifying a microelectronic device located at an air bearing surface, identifying a resistive heating element, which is electrically isolated from the microelectronic device, applying a bias current through the resistive heating element to heat the microelectronic device. |
| US09431023B2 |
Monaural noise suppression based on computational auditory scene analysis
The present technology provides a robust noise suppression system that may concurrently reduce noise and echo components in an acoustic signal while limiting the level of speech distortion. A time-domain acoustic signal may be received and be transformed to frequency-domain sub-band signals. Features, such as pitch, may be identified and tracked within the sub-band signals. Initial speech and noise models may be then be estimated at least in part from a probability analysis based on the tracked pitch sources. Speech and noise models may be resolved from the initial speech and noise models and noise reduction may be performed on the sub-band signals. An acoustic signal may be reconstructed from the noise-reduced sub-band signals. |
| US09431015B2 |
Electronic device and method for managing voice entered text using gesturing
An electronic device for managing voice entered text using gesturing comprises a housing, display, power source, speech recognition module, gesture recognition module, and processor. A first speech input is detected, and textual words are displayed. One or more swipe gestures are detected, and a direction of the swipe gesture(s) is determined. Each textual word is highlighted one-by-one along a path of the direction of the swipe gesture(s) highlighting for each swipe gesture. For one embodiment, a second speech input may be detected and a highlighted textual word may be substituted with a second textual word. For another embodiment, a type of the swipe gesture(s) may be determined. A textual word adjacent to a currently highlighted word may be highlighted next for the first type, and a textual word non-adjacent to the currently highlighted word may be highlighted next for the second type. |
| US09431014B2 |
Intelligent placement of appliance response to voice command
Systems and methods for intelligent placement of appliance response to a voice command are provided. An exemplary system includes a plurality of appliances. An exemplary method includes connecting each of the plurality of appliances over a local area network and generating a location map providing a location of each of the plurality of appliances. The method includes receiving the human voice signal at a plurality of microphones respectively included in the plurality of appliances and determining an originating location of the human voice signal based at least in part on the location map. The method includes selecting one of the plurality of appliances to respond to the human voice signal based at least in part on the location map and the originating location. |
| US09431011B2 |
System and method for pronunciation modeling
Systems, computer-implemented methods, and tangible computer-readable media for generating a pronunciation model. The method includes identifying a generic model of speech composed of phonemes, identifying a family of interchangeable phonemic alternatives for a phoneme in the generic model of speech, labeling the family of interchangeable phonemic alternatives as referring to the same phoneme, and generating a pronunciation model which substitutes each family for each respective phoneme. In one aspect, the generic model of speech is a vocal tract length normalized acoustic model. Interchangeable phonemic alternatives can represent a same phoneme for different dialectal classes. An interchangeable phonemic alternative can include a string of phonemes. |
| US09431007B2 |
Voice search device, voice search method, and non-transitory recording medium
In a voice search device, a processor acquires a search word, converts the search word into a phoneme sequence, acquires, for each frame, an output probability of a feature quantity of a target voice signal being output from each phoneme included in the phoneme sequence, and executes relative calculation of the output probability acquired from each phoneme, based on an output probability acquired from another phoneme included in the phoneme sequence. In addition, the processor successively designates likelihood acquisition zones, acquires a likelihood indicating how likely a designated likelihood acquisition zone is a zone in which voice corresponding to the search word is spoken, and identifies from the target voice signal an estimated zone for which the voice corresponding to the search word is estimated to be spoken, based on the acquired likelihood. |
| US09431004B2 |
Variable-depth audio presentation of textual information
A respective sequence of tracks of Internet content of common subject matter is queued to each of a plurality of stations, where each of the tracks of Internet content resides on a respective Internet resource in textual form. In response to receiving a sample input, snippets of each of multiple tracks queued to a selected station among the plurality of stations is transmitted for audible presentation as synthesized human speech, where each of the snippets includes only a subset of a corresponding track. Thereafter, one or more complete tracks among the multiple tracks for which snippets were previously transmitted are transmitted for audio presentation as synthesized human speech. |
| US09431002B2 |
Real time popularity based audible content aquisition
A personalized news service provides personalized news programs for its users by generating personalized combinations of audible versions of news stories derived from text-based based versions of the news stories. The audible versions may be generated from the text-based version by a text-to-speech system, or may by recording a person reading aloud the text-based version. To acquire recordings, the personalized news service can make a determination that a particular news story has a threshold extent of popularity. The news service can then transmit a request to a remote recording station for a recording of a verbal reading of the particular news story. The news service can then receive the requested recording from the remote recording station. |
| US09431001B2 |
Device, system and method of noise control
Some demonstrative embodiments include devices, systems and methods of noise control. For example, a device may include a controller to control noise within a predefined noise-control zone, the controller is to receive a plurality of noise inputs representing acoustic noise at a plurality of predefined noise sensing locations, which are defined with respect to the predefined noise-control zone, to receive a plurality of residual-noise inputs representing acoustic residual-noise at a plurality of predefined residual-noise sensing locations, which are located within the predefined noise-control zone, to determine a noise control pattern, based on the plurality of noise inputs and the plurality of residual-noise inputs, and to output the noise control pattern to at least one acoustic transducer. |
| US09430999B2 |
Noise cancellation
A noise cancellation signal is generated by generating an ambient noise signal, representing ambient noise, and generating a noise cancellation signal, by applying the ambient noise signal to an feedforward filter, where the feedforward filter comprises a high-pass filter having an adjustable cut-off frequency, and by applying a controllable gain. The noise cancellation signal is then applied to a loudspeaker, to generate a sound to at least partially cancel the ambient noise. An error signal is generated, representing unwanted sound in the region of the loudspeaker. The phase of the ambient noise signal is compared to a phase of the error signal, and the gain is controlled on the basis of a result of the comparison, taking account of a phase shift introduced by the high-pass filter when performing the comparison. |
| US09430998B2 |
Radio apparatus comprising an agglomeration of acoustically adsorbing members
An apparatus includes an acoustic chamber, an agglomeration of acoustically adsorbing members in the acoustic chamber and suitably located substantially on or in a non-conductive support that comprises a substantially acoustically transparent material, and a transducer configured to generate acoustic waves which enter the acoustic chamber. Each acoustically adsorbing member is separated from neighboring members. |
| US09430995B1 |
Harmonica automatic positioner and method
A harmonica automatic positioner, comprising: a shoulder yoke configured to be worn over the shoulders of a user, the shoulder yoke having a first end and a second end configured for resting on opposite sides of the chest of the user; a harmonica support frame, rotatably attached to the first end and second end, the harmonica support frame having a first member and a second member configured to rotatably attach to the first end and the second end of the shoulder yoke, where the harmonica support frame is adapted to be wearable on a chest of a user and comprises a plurality of fasteners configured to hold a harmonica; a clutch mechanism that rotatably joins the first end and the first member, and rotatably joins the second end and the second member, where the clutch mechanism is configured to hold the harmonica automatic positioner in alternatively an at rest position and an at ready position, where in the at rest position the harmonica is out of the way of the user's mouth, and where at the at ready position the harmonica is near the mouth of the user such that the user can play the harmonica; an actuator in operable communication with the clutch mechanism, and configured to actuate the clutch mechanism from the at rest position to the at ready position, and further configured to actuate the clutch mechanism from the at ready position to the at rest position; and a switch mechanism in communication with the actuator and configured to actuate the actuator. The disclosed invention also relates to A method of using a harmonica, the method comprising: actuating a harmonica automatic positioner to move a harmonica from a rest position to a ready position; playing the harmonica; and actuating the harmonica automatic positioner to move a harmonica from the ready position to the rest position. |
| US09430986B2 |
Color signal processing device
A color signal processing device for generating image data to be displayed on a display device which represents a color by using at least four primary colors, includes an obtainer that obtains a color signal regarding three primary colors for image data composed of a plurality of pixels, a changer that changes a value of the obtained color signal regarding the three primary colors, and a converter that converts the changed color signal regarding the three primary colors into a color signal regarding four primary colors. When a predetermined region contains a color saturated pixel, the changer makes the value of the color signal of at least one color of the three primary colors smaller, for pixels contained in the predetermined region. |
| US09430980B2 |
Liquid crystal display panel and liquid crystal display device
The present invention provides an liquid crystal display panel and an liquid crystal display device. The liquid crystal display panel comprises a second substrate. The second substrate comprises a plurality of pixel units. The pixel unit comprises a brightness adjustment pixel which is employed for changing the display brightness of itself to adjust the brightness of the liquid crystal display panel. The contrast ratio and the brightness of the liquid crystal display panel can be raised at outdoor or in a strong ambient light environment and the power consumption can be decreased. |
| US09430979B2 |
Liquid crystal display panel, method for driving the same and display device
Embodiments of the invention disclose a liquid crystal display panel, a method for driving the same, and a display device, to improve the transmissivity and the image display quality of the LCD panel. The LCD panel comprises a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer positioned between the first substrate and the second substrate; a first electrode and a second electrode insulated from and disposed on the first electrode are disposed on a side of the first substrate which is close to the liquid crystal layer; one of the first electrode and the second electrode is a common electrode, the other is a pixel electrode; a third electrode and a fourth electrode are disposed on a side of the second substrate which is close to the liquid crystal layer, one of the third electrode and the fourth electrode is a common electrode, and the other is a pixel electrode. |
| US09430972B2 |
Electrowetting display device driving method
An electrowetting display device has at least one display element. The method of driving the display device comprises receiving data representing a display effect for display by the element. A driving scheme is selected for the display element in dependence on a characteristic of the data. The driving scheme is selected from at least an analog driving scheme and a pulse width modulation driving scheme. |
| US09430970B2 |
3D image display device
A 3D image display device includes a backlight unit for generating an original light, a display panel, a light modulating unit, and a controller connected to the display panel and the light modulating unit. According to a first signal, the original light passes through the display panel generates a first light, the first light passes through the light modulating unit, and has a first position on an objective plane parallel to the display panel. According to a second signal, the original light passes through the display panel to generate a second light, the second light passes through the light modulating unit and has a second position on the objective plane, wherein the first position is different from the second position. |
| US09430966B2 |
Organic light emitting display device and method of driving the same
A method of driving an organic light emitting display device includes: dividing one frame into one blank frame and sub-frames; determining whether a data signal to be applied to a pixel circuit of the organic light emitting display device is a data signal of a high gray-level region or a data signal of a low gray-level region based on a predetermined reference gray-level; applying the data signal to the pixel circuit in all of the sub-frames when the data signal is the data signal of the high gray-level region; and applying a first setting data signal corresponding to a gray-level higher than the reference gray-level to the pixel circuit in some of the sub-frames, and applying a second setting data signal corresponding to a zeroth gray-level to the pixel circuit in other sub-frames among the sub-frames when the data signal is the data signal of the low gray-level region. |
| US09430965B2 |
Organic light emitting display device and driving method thereof
An organic light emitting display device includes a display panel including a plurality of pixels each having an organic light emitting element that emits light according to a current corresponding to a data voltage, and a panel driver configured to divide the display panel into first to Mth blocks, calculate an average picture level of each block from data to be displayed in each of the plurality of pixels of each block, convert the data to be displayed by each of the plurality of pixels of each block into the data voltage, and supply the data voltage to each of the plurality of pixels of each block, where the panel driver controls the data voltage to be supplied to an ith block on the basis of the average picture levels of M number of blocks previous to the ith block, where i is a natural number from 1 to M. |
| US09430957B2 |
Virtual load board and test system and test method for liquid crystal display control board
A virtual load board includes a connection port, a conversion circuit, and an indication unit, wherein the connection port comprises at least one terminal. The terminal receives an output voltage from the liquid crystal display control board. The conversion circuit converts the output voltage into an operating voltage for the indication unit and supplies the operating voltage to the indication unit. A test system and a test method for liquid crystal display control board are also provided. With the above-discussed arrangement, the virtual load board replaces a liquid crystal display panel to carry out a reliability test of the liquid crystal display control board, and has the advantages of small volume and low cost and can be accommodated, together with the liquid crystal display control board, in reliability test equipment in order to carry out a reliability test of the liquid crystal display control board in a specific environment. |
| US09430956B2 |
Seam allowance guide aide label
A seam allowance guide aide label, Sewing with Color Label, to be applied to the surface of a sewing machine plate, as a stick-on label. The label has imprinted vertical and horizontal lines with colors; the first vertical line is the guideline to align the label to the default needle position for applying the label to the sewing machine's plate. The use of colors is a system to represent a standard measurement, known and accepted in today's sewing industry. The color system defines and establishes immediate differences between measurements, to achieve accuracy in positioning the edge of a textile to be sewn in a specific seam line without trouble of not recognizing numerical representations or seam grading lines in the actual plate of a sewing machine, either in imperial or metric system. |
| US09430955B2 |
Breastfeeding training system
This invention relates generally to breastfeeding training and more specifically to devices comprised of a doll and chest piece used for breastfeeding training. |
| US09430953B2 |
Simulation device with motion stabilization
A simulation device imparts a force corresponding to a simulated event on a user. The simulation device includes a motion base mounted to a moveable surface and a capsule mounted to the motion base. The user is positioned within the capsule during the simulated event, and the motion base is configured to move the capsule relative to the moveable surface. The simulation device further includes a sensor that senses movement of the moveable surface. A controller is operably coupled to both the sensor and the motion base. The controller receives a signal from the sensor and controls the motion base to move the capsule according to the simulated event and the signal received from the sensor. |
| US09430948B2 |
Landing alerts for preventing runway excursions
A landing alert system and method for preventing runway excursions may include determining, during an approach of an aircraft to landing on a runway, a target touchdown point on the runway, determining a boundary descent path configured to permit safe approach and touchdown of the aircraft on the runway at or before the target touchdown point, and, in response to the aircraft crossing within a selected margin of the boundary path, alerting an operator of the aircraft. |
| US09430947B2 |
Maritime autonomous station keeping (MASK)
Technology for determining a point-to-point separation between a first ship (e.g., guide ship) and a second ship (e.g., following ship) is disclosed. One approach can include maritime autonomous station keeping (MASK) interactive device comprising a communication module and a processor. The communication module can be configured to receive a following ship reference point (SRP) generated by at least one differential global positioning system (DGPS) receiver on a following ship relative to a guide SRP generated by at least one DGPS receiver on a guide ship. The processor can be configured to generate a plurality of fixed following reference edge points (REPs) relative to the following SRP representing a following ship hull, generate a plurality of fixed guide REPs relative to the guide SRP representing a guide ship hull, and monitor a plurality of distances between the plurality of following REPs and the plurality of guide REPs. |
| US09430946B2 |
Obstacle determination device
An obstacle determination device that determines whether a solid object present in a travelling direction of a subject vehicle is an obstacle that the vehicle should avoid, and determines the solid object is an obstacle by comparing the height of the solid object to a reference height. The reference height is set based on a relative positional relation between a separation line detected by a separation line detection unit and the solid object. And, when the separation line is present between the solid object and the subject vehicle, the reference height is set such that the solid object is more likely to be determined as an obstacle, as compared to when the separation line is not present between the solid object and the subject vehicle. |
| US09430937B2 |
Contextual, two way remote control
Methods and systems for allowing interaction between devices are described. At a first device, an application is executed. The application operates interactively with a remote control application executing on a second device. One or more information items are transmitted to the second device for display as one or more selectable display items. Each respective information item is associated with an action definition. The action definition includes a command to be sent by the second device to the first device in response to a user selection of the respective information item. A command is received from the second device in response to a selection of a first one of the selectable display items by the user. A predefined action is performed in response to receiving the command. |
| US09430936B2 |
Systems and methods for monitoring and controlling remote devices
Systems and methods for monitoring and controlling remote devices are provided. In an embodiment, a system can comprise one or more remotely controlled sensors and actuators. The remote sensors/actuators can interface with uniquely identified remote transceivers that transmit and/or receive data. The embodiment can also comprise a plurality of transceivers each having a unique address, and a controller adapted to communicate with at least one of the transceivers in a preformatted message. A sensor can be associated with at least one transceiver to detect a condition and output a data signal to the transceiver, and an actuator can be associated with a transceiver to receive a control signal and activate a device. Other embodiments are also claimed and described. |
| US09430935B2 |
Emergency event message
A gateway can be configured to receive an emergency event message in a predefined format via a network. The emergency event message can characterize a location and a nature of an emergency event. The gateway can also be configured to identify a particular Public Safety Answering Point (PSAP) customer premise equipment (CPE) to service the emergency event. The gateway can further be configured determine a format of messages employable by the particular PSAP. The gateway can still further be configured to provide the particular PSAP CPE with an output message in the format employable by the particular PSAP CPE. The output message can characterize the nature and the location of the emergency event. |
| US09430934B2 |
Wireless communication device and locator system
There is provided a locator system that facilitates registration of a calling apparatus to be added and a locator. Portable unit communicates with base unit with a DECT protocol. Moreover, portable unit serves as a calling apparatus that transmits a call signal to locator to be attached to an item with a locator protocol. Portable unit transmits registration information to base unit by wireless communication as being triggered by registration with locator in one-to-one correspondence being ended. In a case where a request is received from portable unit as a calling apparatus to be added, base unit transmits stored registration information received from portable unit to portable unit. Portable unit stores the registration information received from base unit. |
| US09430932B2 |
Hand luggage reminder for vehicle passenger
The present invention discloses a hand luggage reminder comprising a mainbody (1) operationally connected with a first and a second electric switch boxes (21, 22), a small permanent magnetic rod set (33), and a strong permanent magnet (43); and the mainbody further comprises a main electric switch box (5) operationally connected with a battery box (11), a sound generator box (12), and a permanent magnetic push-to-break switch (16) for easy controlling the sound for reminding a passenger on a vehicle to take out personal belongings while leaving the vehicle. After depressing a button (161) of the push-to-break switch (16) to stop the reminding sound, it needs no another button pressing to restore the reminding function because the reminder cannot be switched off by pressing the button (161). Closing the car door can also stop the reminding sound. The present invention is waterproof, low in cost, easy in installation and operation. |
| US09430924B2 |
AC-coupled RFID system
An AC-coupled RFID system is disclosed. Embodiments of the invention statistically correlate the transmit data from a baseband transmit signal and the receive data in a receive signal after the signal has passed through a baseband receive filter. By using a receive bandpass or high-pass filter at baseband, the receiver can be AC-coupled in the baseband. This AC coupling significantly reduces cost and complexity by eliminating high-power reflected signals at and near DC. The high-pass corner frequency of the receive filter passes enough of the receive signal to still be measurable. The correlation is used to estimate the reflected carrier, which in turn enables cancellation of the carrier, improving RFID reader sensitivity. |
| US09430923B2 |
Moving object detection, tracking, and displaying systems
Moving object detecting, tracking, and displaying systems are provided. Systems illustratively include a graphical user interface and a processing unit. The processing unit is a functional part of the system that executes computer readable instructions to generate the graphical user interface. The graphical user interface may include an alert and tracking window that has a first dimension that corresponds to a temporal domain and a second dimension that corresponds to a spatial domain. In some embodiments, alert and tracking windows include target tracking markers. Target tracking markers optionally provide information about moving objects such as, but not limited to, information about past locations of moving objects and information about sizes of moving objects. Certain embodiments may also include other features such as zoom windows, playback controls, and graphical imagery added to a display to highlight moving objects. |
| US09430920B2 |
Treadmill belt wear notification system
Belt wear of a treadmill is determined. Samples of electric current draw of a treadmill at different speeds of the treadmill belt of the treadmill are received. A value of each sample is differently weighted based on a speed of the treadmill belt at which the value of each sample was obtained. A belt wear notification is output based on the different weighted values of the samples. |
| US09430919B2 |
Communication using coupled devices
A first device presents first information that is associated with a first mode of operation. The first device receives a communication from a second device that is communicably coupled to the first device. The communication instructs the first device to perform an operation corresponding to an event associated with the second device. In response to receiving the communication from the second device, the first device presents second information that is associated with a second mode of operation corresponding to the event associated with the second device. The second information is presented by the first device concurrent with a processing associated with the event that is performed by the second device. |
| US09430918B2 |
Receipt generation service
A method includes receiving, by a server via a network, transaction information descriptive of a money transfer transaction initiated at a point of entry device. The transaction information includes information that identifies a location of the point of entry device. The method includes determining, by the server, receipt information to be included in a receipt for the money transfer transaction. The receipt information may be determined based, at least in part, on the transaction information, and at least a portion of the receipt information included in the receipt satisfies regulatory requirements associated with the location of the point of entry device. The method includes generating, by the server, the receipt that includes the receipt information, and transmitting the receipt from the server to the point of entry device via the network. |
| US09430917B2 |
Dynamically mapping wagering game content
A wagering game system (“system”) and its operations are described herein. In some examples, the operations include electronically determining, via an electronic communication interface of the system, display coordinates associated with first content of a first wagering game application (“first application”) for presentation on an electronic display device associated with the system. The first application is independent from a second wagering game application (“second application”). The operations can further include automatically mapping, via an electronic processing unit of the system, second content for the second application to the display coordinates. The operations can further include, based on the mapping, electronically presenting, via the electronic display device, the second content affixed relative to the first content during concurrent game play of the first application and the second application. The first content indicates a first game outcome independent from a second game outcome indicated by the second content. |
| US09430914B2 |
Gaming machine and methods of allowing a player to play gaming machines having selectable reel strips
A method of allowing a player to play a gaming machine is described herein. The method includes displaying a game including at least one reel and a plurality of reel strips for display with the at least one reel. Each reel strip includes a plurality of normal symbol positions and a plurality of special symbol positions. The plurality of reel strips includes a first reel strip having a first number of special symbol positions and a second reel strip having a second number of special symbol positions that is different than the first number of special symbol positions. The method also includes randomly generating an outcome of the game and displaying the game outcome on the display device. One of the first reel strip and the second reel strip is randomly selected for display with the at least one reel. |
| US09430905B2 |
Method and system for gaming revenue
A method and system comprises integrating a contest framework into a game. The contest framework at least comprises means for communicating with a transactional server, a plurality of listeners being configured to monitor interactions during a play of the game for communication to the transactional server, and means for displaying notifications from the transactional server. The transactional server is at least configured for processing received interactions in conjunction with a progressive jackpot contest associated with the game and communicating notifications regarding the processing to the contest framework. A communicating with the transactional server at least comprises associating the game with a progressive jackpot contest and setting parameters for the progressive jackpot contest. |
| US09430904B2 |
Self configuring progressive jackpot award controller
A self configuring progressive jackpot award system includes a plurality of electronic gaming machines (EGMs). The plurality of EGMs respectively include a plurality of EGM configuration options, and operate in accordance with the EGM configuration options. A subset of the plurality of EGM configuration options relates to participating in a progressive jackpot award game. A progressive controller is coupled to the plurality of EGMs and controls the operation of a progressive jackpot award game. The progressive controller includes a plurality of progressive jackpot award game configuration options. A subset of these progressive jackpot award game configuration options correspond to the subset of EGM configuration options related to participating in the progressive jackpot award game. The progressive controller automatically sends data representing this subset of progressive jackpot award game configuration options to the plurality of EGMs. The plurality of EGMs receives the progressive jackpot award game configuration option representative data from the progressive controller, stores the subset of EGM configuration options related to participating in the progressive jackpot award game represented by the data, and participates in the progressive jackpot award game in accordance with the EGM progressive jackpot award game configuration award game options. |
| US09430900B2 |
Gaming system and method for providing a symbol matrix with a moveable symbol display window
In various embodiments, the present disclosure generally relates to gaming systems and methods which utilize a symbol matrix or symbol field in conjunction with a movable symbol display window to randomly select different subsets of symbols from the symbol matrix and provide different awards to players based on such selected symbol subsets. |
| US09430898B2 |
Gaming device with personality
Embodiments of the present invention are directed to gaming devices that provide audio-visual animated characters in response to game play. The character has a personality that may be encouraging, taunting or another quality. A plurality of expressions of the personality is presented, between one extreme and another, dependant upon the history of game outcomes. |
| US09430896B2 |
Bill handling apparatus
A bill handling apparatus includes a first squeezing unit that performs a first squeezing of a bill in receiving the bill, and a second squeezing unit that performs a second squeezing of the bill after the first squeezing, wherein the first squeezing unit comprises a pair of conveying belts that convey the bill in a predetermined conveying direction in receiving the bill, a distance between both the conveying belts being gradually reduced in a direction of thickness of the bill in the predetermined conveying direction, and the second squeezing unit comprises a pair of rollers disposed at an end part of the first squeezing unit in the predetermined conveying direction. |
| US09430893B1 |
Systems, methods and devices for managing rejected coins during coin processing
Currency processing systems, coin processing machines, computer-readable storage media, and methods of managing processed coins are presented herein. A method is presented for managing coins processed by a currency processing system. The method includes: receiving a batch of coins by the currency processing system; feeding the coins into a coin processing unit which includes one or more coin discriminating sensors; sorting the batch of coins into genuine fit target coins and reject coins; sorting the reject coins into a plurality of reject groups, each of which corresponds to a respective category of rejected coins; analyzing at least one of the reject groups to determine if any genuine target coins were mischaracterized and erroneously sorted into that reject group; and, crediting a user of the currency processing system for any genuine target coins in the reject group determined to have been mischaracterized and erroneously sorted. |
| US09430888B2 |
Access control in location tracking system
A method for controlling access in a location tracking system is provided. In response to detection of the presence of a mobile tag of the location tracking system in an area having at least one access control device, a location tracking device of the location tracking system activates the access control device to initiate establishment of a communication connection with the mobile tag so as to negotiate access rights of the mobile tag. |
| US09430886B2 |
Driving diagnosis device, driving diagnosis system and driving diagnosis method
A driving diagnosis device includes storage device which stores plural pieces of advice and a processor. The processor makes a diagnosis on driving by a driver according to vehicle information indicating at least one of behavior of a certain vehicle and an operation of the driver while the driver is driving the certain vehicle. The processor judges a degree of influence, on the diagnosis, of a driving experience of the driver before the driver drives the certain vehicle according to history information as for a history of the driver driving one or more different vehicles including the certain vehicle. And the processor determines to present to the driver a piece of advice stored in the storage device, from among plural pieces of advice, in association with a combination of a result of the diagnosis and the judged degree of influence. |
| US09430884B2 |
Vehicle communication and cable tester system
A device includes a processor in communication with a first port, a second port and a third port. The first port is configured to communicate via a diagnostic cable with an electronic control unit of a vehicle. The diagnostic able cable has a first end configured to connect to a vehicle port and a second end configured to connect to the first port. The processor is configured to selectively test the communication capability of the diagnostic cable when the first end of the diagnostic cable is connected to the third port and the second end of the diagnostic cable is connected to the first port. |
| US09430877B2 |
Electronic device and method for selecting augmented content using the same
Disclosed are an electronic device and a method for selecting augmented content that selectively augment various types of content with respect to a real object using a marker. The electronic device providing augmented reality, comprising: a memory storing at least one content group, wherein each of the at least one content group includes a plurality of virtual objects; a display; and a controller configured to: capture, via the camera, an image including a real object and a marker, obtain identification information on the real object based on the image, obtain angle information reflecting an orientation of the marker with respect to the real object using the image, determine a specific content group from the at least one content group based on the identification information, select a specific virtual object among the virtual objects include in the specific content group based on the angle information, and augment, via the display, the specific virtual object. |
| US09430875B1 |
Updating damaged-enhanced 3D polygon meshes
A method and computer system for updating damaged-enhanced polygon meshes in a computer simulation associated to a storage module accessible to at least a first and a second decentralized simulation stations and a centralized processing unit thereof. At the first station, during the computer simulation, determining coordinates of a virtual impact on a 3D polygon mesh, computing newly formed 3D polygon mesh(es) from the virtual impact without updating the storage module and rendering damaged-enhanced image(s) of the newly formed 3D polygon mesh(es) for display from a first field of view of the first station. At the second station, receiving the coordinates of the virtual impact. At the centralized processing unit, receiving the coordinates of the virtual impact, computing the newly formed 3D polygon mesh(es) from the received coordinates independently from the first station, in non-real-time priority processing and persistently updating the storage module with newly formed 3D polygon mesh(es). |
| US09430874B2 |
Estimation of object properties in 3D world
Objects within two-dimensional video data are modeled by three-dimensional models as a function of object type and motion through manually calibrating a two-dimensional image to the three spatial dimensions of a three-dimensional modeling cube. Calibrated three-dimensional locations of an object in motion in the two-dimensional image field of view of a video data input are determined and used to determine a heading direction of the object as a function of the camera calibration and determined movement between the determined three-dimensional locations. The two-dimensional object image is replaced in the video data input with an object-type three-dimensional polygonal model having a projected bounding box that best matches a bounding box of an image blob, the model oriented in the determined heading direction. The bounding box of the replacing model is then scaled to fit the object image blob bounding box, and rendered with extracted image features. |
| US09430872B2 |
Performance prediction for generation of point clouds from passive imagery
A system and method of generating point clouds from passive images. Image clusters are formed, wherein each image cluster includes two or more passive images selected from a set of passive images. Quality of the point cloud that could be generated from each image cluster is predicted for each image cluster based on a performance prediction score for each image cluster. A subset of image clusters is selected for further processing based on their performance prediction scores. A mission-specific quality score is determined for each point cloud generated and the point cloud with the highest quality score is selected for storage. |
| US09430871B2 |
Method of generating three-dimensional (3D) models using ground based oblique imagery
Embodiments of the invention relate to the visualization of geographical information and the combination of image information to generate geographical information. Specifically, embodiments of the invention relate to a process and system for correlating oblique images data and terrain data without extrinsic information about the oblique imagery. Embodiments include a visualization tool to allow simultaneous and coordinated viewing of the correlated imagery. The visualization tool may also provide distance and measuring, three-dimensional lens, structure identification, path finding, visibility and similar tools to allow a user to determine distance between imaged objects. |
| US09430869B1 |
Reducing data stored in a deep-framebuffer
The subject matter of this specification can be embodied in, among other things, a method that includes generating intermediate values from an evaluation of one or more static expressions within shader programming code that is configured to modify an appearance of an image, compressing the intermediate values based on a determination of which intermediate values are duplicative, and storing the compressed intermediate values in a buffer accessible to an image rendering application. |
| US09430868B2 |
Pseudo 3-D rendering of mobile device based slot machine
The invention relates to a system and method for applying one or more visual effects such as three-dimensional effects and holographic effects to one or more two-dimensional images that represent all or a portion of a virtual slot machine that is depicted in a virtual slot machine game rendered by a computing device. The computing device may determine the visual effects to be applied based on sensor information that indicates an orientation of the computing device. The visual effects may simulate various real-world visual changes (e.g., shadow changes, reflection changes, etc.) that occur as the user's point of view changes, thereby providing a more realistic user experience in relation to the virtual slot machine game. |
| US09430862B2 |
Raster image three-dimensionalization processing device, raster image three-dimensionalization method, and raster image three-dimensionalization program
The computer main body includes a mesh size matching unit, a shading map generator, a red three-dimensional image generator, a raster image reader, a gradient reader, a floating-sinking degree reader, a first HSV converter, a mesh designator, a shading data reader, a second HSV converter, a hue reader, a first synthesis unit, a second synthesis unit, a third synthesis unit, an image output unit, a register, a color adjuster and the like, and causes the raster image RSGi having an elevation value to be viewed three-dimensionally. |
| US09430861B2 |
System and method for integrating multiple virtual rendering systems to provide an augmented reality
There is provided a system and method for integrating multiple virtual rendering systems to provide an augmented reality. There is provided a method for integrating multiple virtual rendering systems for outputting a composite render to a display, comprising obtaining a first environment data from a first virtual rendering system using a first camera view, obtaining a second environment data from a second virtual rendering system using a second camera view, rendering the composite render by processing the first environment and the second environment, and outputting the composite render to the display. Additionally, the first environment data and second environment data may depend on synchronized or corresponding inputs, and display priority algorithms or masking algorithms may be used to determine virtual and real object display priority. |
| US09430859B2 |
Image processing apparatus, image relaying apparatus, method for processing image, and method for relaying image
A method of relaying an image. The method includes receiving a plurality of images which are photographed by a plurality of image processing apparatuses, determining orientation modes of the plurality of images, combining the plurality of images to generate a combined image in which the plurality of combined images are orientated in the same way, and transmitting the combined image to the plurality of image processing apparatuses. |
| US09430856B2 |
System comprising providing means for providing data to a user
The present invention relates to a system comprising providing means for providing data to a user, comprising display means for displaying said provided data and comprising assessment means for assessing at least one characteristic of at least one of said displayed data, wherein the system further comprises at least one means for providing a color in at least one part of the area displayed by said display means, wherein the color or at least one characteristic of the color is dependend on said characteristic of said data. |
| US09430854B2 |
System and method for model consistency constrained medical image reconstruction
A method for reconstructing an image of a subject with a medical imaging system, such as a magnetic resonance imaging system, is provided. Medical image data is acquired from the subject with the medical imaging system, and one or more images of the subject are reconstructed from the medical image data while constraining the one or more images to be consistent with a signal model that relates image intensity values in the image to a free parameter that is associated with a physical property of the subject. The signal model may be an analytical signal model or an approximate signal model learned from acquired medical image data. The model consistency condition may be enforced using an operator that projects an image estimate onto the space of all functions satisfying the signal model. |
| US09430852B2 |
Digital check image shifting in a carousel display
Apparatus and methods are provided for viewing a check image and selecting a check service to be applied to a check. Check services may include a pay/return decision. The check images may be presented in a carousel view without pop-up windows. The user may import pre-selected check services such as stop payments. Check images may be marked with a status indicator. The status indicator may correspond to a check service applied to the check or a reconciliation error associated with the check. A user may receive notifications of pending expiration of an applied check service. The user may select and apply a check service at any time during a clearing process of the check. User may search for checks and check images based on the check service applied to the check. Search results may include check images and may be transmitted to a requested location such as via e-mail. |
| US09430846B2 |
Method of tracking objects using hyperspectral imagery
A method of tracking motion of at least one object of a group of moving objects using hyperspectral imaging includes, among other things, obtaining a series of hyperspectral image frames; comparing each frame in the series to a template to determine changes in the image between frames; identifying a group of pixels in each frame associated with the changes; identifying changes as motion of the moving objects; correlating the pixel groups frame to frame to spatially determine at least one parameter of the motion of the objects; and correlating the pixel groups with a spectral reflectance profile associated with the at least one object wherein the track of the at least one object is distinguishable from the tracks of other moving objects. |
| US09430843B2 |
Edge detection in images
An edge detection engine operates to scan an image to identify edges within the image. An annular aperture is used to locate the edges in the image. An output image is generated by the edge detection engine that identifies the locations of the edges found in the image. |
| US09430841B2 |
Defect inspection method
There is provided a defect inspection method capable of detecting a crack with high accuracy. The defect inspection method includes the steps of: obtaining a shot image comprising pixels; and scanning the shot image in predetermined directions, and assigning a high evaluation value to a pixel M for each scanning direction when the luminance of the pixel M is lower than the luminances of first adjacent pixels K, O, located on both sides of the pixel M in the scanning direction and, in addition, the luminance of each of second adjacent pixels C, W, located on both sides of the pixel M in a direction perpendicular to the scanning direction, is lower than the luminances of third adjacent pixels A, E or U, Y located on both sides of the second adjacent pixel in the scanning direction. The method also includes the steps of selecting selection pixels based on the evaluation values of the pixels for each scanning direction; connecting the selection pixels for each scanning direction; and synthesizing the selection pixels of the predetermined scanning directions, and removing those pixels which do not meet the requirement for a predetermined shape from the selection pixels. |
| US09430840B1 |
Method and system for segmenting an image based on motion vanishing points
A method segments an image acquired by a sensor of a scene by first obtaining motion vectors corresponding to the image and generating a motion vanishing point image, wherein each pixel in the motion vanishing point image represents a number of intersections of pairs of motion vectors at the pixel. In the motion vanishing point image, a representation point for each motion vector is generated and distances between the motion vectors are determined based on the representation points. Then, a motion graph is constructed wherein each node represents a motion vector, and each edge represents a weight based on the distance between the nodes. Graph spectral clustering is performed on the motion graph to produce segments of the image. |
| US09430839B2 |
Unsupervised framework to monitor lake dynamics
A method of reducing processing time when assigning geographic areas to land cover labels using satellite sensor values includes a processor receiving a feature value for each pixel in a time series of frames of satellite sensor values, each frame containing multiple pixels and each frame covering a same geographic location. For each sub-area of the geographic location, the sub-area is assigned to one of at least three land cover labels. The processor determines a fraction function for a first sub-area assigned to a first land cover label. The sub-areas that were assigned to the first land cover label are reassigned to one of the second land cover label and the third land cover label based on the fraction functions of the sub-areas. |
| US09430837B2 |
Position and orientation measurement apparatus, position and orientation measurement method, and program
A position and orientation measurement apparatus for measuring the position and orientation of a target object includes a first search unit which searches a geometric model for a lost model region corresponding to a lost image region in a range image, a determination unit which determines whether or not a point on a geometric model corresponding to a pixel on the range image of the target object falls within the lost model region, a correction unit which corrects combinations of pixels on the range image and corresponding points which are determined to fall within the lost model region, and a calculation unit which calculates the position and orientation of the target object based on the corrected combinations of the pixels on the range image and points on the geometric model. |
| US09430830B2 |
Spatially aware cell cluster (SPACCL) graphs
Methods, apparatus, and other embodiments associated with objectively predicting disease aggressiveness using Spatially Aware Cell Cluster (SpACCl) graphs. One example apparatus includes a set of logics that acquires an image of a region of tissue, partitions the image into a stromal compartment and an epithelial compartment, identifies cluster nodes within the compartments, constructs a spatially aware stromal sub-graph and a spatially aware epithelial sub-graph based on the cluster nodes and a probabilistic decaying function of the distance between cluster nodes, extracts local features from the sub-graphs, and predicts the aggressiveness of a disease in the region of tissue based on the sub-graphs and the extracted features. Example methods and apparatus may employ a Support Vector Machine classifier to classify super-pixels within the image as stromal super-pixels or epithelial super-pixels. |
| US09430829B2 |
Automatic detection of mitosis using handcrafted and convolutional neural network features
One example apparatus associated with detecting mitosis in breast cancer pathology images by combining handcrafted (HC) and convolutional neural network (CNN) features in a cascaded architecture includes a set of logics that acquires an image of a region of tissue, partitions the image into candidate patches, generates a first probability that the patch is mitotic using an HC feature set and a second probability that the patch is mitotic using a CNN-learned feature set, and classifies the patch based on the first probability and the second probability. If the first and second probabilities do not agree, the apparatus trains a cascaded classifier on the CNN-learned feature set and the HC feature set, generates a third probability that the patch is mitotic, and classifies the patch based on a weighted average of the first probability, the second probability, and the third probability. |
| US09430828B2 |
Cloud-based medical image processing system with tracking capability
A cloud server receives a request for accessing medical image data from a client device, where the cloud server provides image processing services to users in image processing steps, resulting in image views. User privileges of a user are determined for accessing the medical image data. In response to receiving a command having a selection of an image view from the client device, the cloud server provides the medical image data based on the selected one or more image views. The user interactions of the user with the medical image data via the selected image views are tracked, including tracking how much time the user takes to complete a particular medical image processing step. The tracked user interactions are stored in a persistent storage, and an analysis is performed on the tracked user interactions stored in the persistent storage to determine an overall usage trend of the image views. |
| US09430824B2 |
Machine learning method and apparatus for inspecting reticles
Apparatus and methods for inspecting a photolithographic reticle are disclosed. A reticle inspection tool is used at one or more operating modes to obtain images of a plurality of training regions of a reticle, and the training regions are identified as defect-free. Three or more basis training images are derived from the images of the training regions. A classifier is formed based on the three or more basis training images. The inspection system is used at the one or more operating modes to obtain images of a plurality of test regions of a reticle. Three or more basis test images are derived from to the test regions. The classifier is applied to the three or more basis test images to find defects in the test regions. |
| US09430823B1 |
Determining camera sensor isolation
Approaches discussed herein enable a computing device to be tested to determine whether light from an emitter is bleeding through the device, which can be indicative of an assembly failure. A light blocking member can be placed over a camera in order to prevent a camera from capturing light coming from outside the device. At least one light source of the device then can be caused to emit light, and the camera can capture at least one image to determine whether any of the light is bleeding through the device and being detected by the camera. If so, the device can be determined to fail the test, and can be sent for reassembly or another remedial action. In some cases, a type of failure might be able to be determined, and information for the failure can be logged for purposes such as quality assurance and failure rate monitoring. |
| US09430820B2 |
Pixel clustering
A technique is described for combining several image sources into a single output image or video sequence. For a given pixel of the output image, pixel values are received from the image sources, and a matrix of distance measures between the pixel values (e.g. based on their colors) is computed. Clusters of pixel values are formed using the distance measures, and a score determined for each. One of the clusters is selected according to the scores, and used to derive an output pixel value. In an example, the clusters are formed using an iterative process where the closest pairs of pixel values or clusters are merged to form new clusters up to a size threshold. Examples are described for scoring the clusters based on model-based weighting or cluster size. Examples are also described for a rule-based cluster selection system. A composite image generator implementing the technique is also described. |
| US09430816B2 |
Image processing method, image processing system, image processing device, and image processing program capable of removing noises over different frequency bands, respectively
Disclosed is an image processing method including: generating an initial denoised image with a reduced noise while preserving an edge in an input image; controlling an iterative operation performed based on energy defined in advance based on an initial residual component calculated from the input image and the initial denoised image; and separating the initial denoised image to a skeleton component and a residual component by the controlled iterative operation to generate the skeleton component as an output image. |
| US09430812B2 |
Image processing method, image output processing method, and image reception processing method
The present invention discloses an image processing method comprising: using an image output device to generate a scale-down image; using the image output device to generate a plurality of divided images according to the scale-down image; using the image output device to encode the plurality of divided images to thereby generate a plurality of encoded images; having the image output device output the plurality of encoded images into an image reception device through a transmission interface; using the image reception device to decode the plurality of encoded images to thereby recover the plurality of divided images; using the image reception device to generate a combined image according to the plurality of divided images; and using the image reception device to generate a display image according to the combined image, in which the size of the display image is larger than the size of the combined image. |
| US09430811B2 |
Graphics processor with non-blocking concurrent architecture
In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations. |
| US09430810B2 |
Drawing method, apparatus, and terminal
A drawing method, apparatus, and terminal, where: a drawing command set of a current frame is received; a CPU drawing time and a GPU drawing time of the current frame are determined according to the drawing command set of the current frame; and if the CPU drawing time is less than the GPU drawing time, the CPU is used to draw the current frame, and if the CPU drawing time is longer than the GPU drawing time, the GPU is used to draw the current frame. In this way, which drawing manner is adopted is dynamically determined according to the drawing time corresponding to the CPU/GPU, so as to shorten a drawing time of each frame to some extent, thereby increasing a display speed of a system and improving display performance. |
| US09430807B2 |
Execution model for heterogeneous computing
The techniques are generally related to implementing a pipeline topology of a data processing algorithm on a graphics processing unit (GPU). A developer may define the pipeline topology in a platform-independent manner. A processor may receive an indication of the pipeline topology and generate instructions that define the platform-dependent manner in which the pipeline topology is to be implemented on the GPU. |
| US09430806B2 |
Electronic device and method of operating the same
A method and apparatus for image processing includes receiving images, detecting non-stationary objects in the images, displaying a first image that includes a non-stationary object, selecting a frame region including the non-stationary object in the first image, selecting a second image based on a low similarity with the first image, and replacing image data in the frame region of the first image with image data represented in the frame region of the second image. |
| US09430802B2 |
Method and process for collaboratively built content filtering
A method and system for collaborative content filtering on a communications network includes monitoring social networking communications of a plurality of users on a communications network using a program. The method and system further include selecting a filter parameter by a user. The content of the social networking communications is filtered based on the filter parameter including parsing input from the users, using the program. The filtered content is identified to at least one user. |
| US09430801B2 |
Methods systems and computer program products for generating financial statement complying with accounting standard
Requirements, principles or guidelines of an accounting standard such as Generally Accepted Accounting Principles (GAAP) are transformed or codified into rules that specify how form, content and/or style of a certain portion of a financial statement, such as a header, should be configured while complying with the accounting standard. A rule engine compares attributes related to a financial statement and rules to determine which rule applies, and a selected rule specifies a header configuration. Relevant data received or retrieved from a source is used to generate or populate the header such that the header is automatically generated while complying with the accounting standard. |
| US09430797B2 |
Digital downloading jukebox system with user-tailored music management, communications, and other tools
A digital downloading jukebox system including a mechanism for delivering custom services to a recognized user, including services for creating playlists, communicating with others, accessing other features, etc. is provided. In some exemplary embodiments, after a user is recognized, the jukebox system allows users to access a special front-end via the Internet or on an actual jukebox. Then, the user may, for example, create playlists, share songs with friends, send messages to friends, and access other value-added content. Other exemplary embodiments allow users to become certified, charging them for services without requiring constant inputting of coinage or credit card information. Such a system preferably learns about networks of friends, and enables managers to send similar messages to regular customers and/or others known to the system. |
| US09430796B1 |
Direct purchase from user-received advertisement
An advertised product is associated with an option to directly purchase the advertised product. A payment processing system receives an input from a user device of a selection on the user device of the option to directly purchase the advertised product. In response to receiving the input from the user device to directly purchase the advertised product, a time-out period for modifying the selection of the option to directly purchase the advertised product is provided. When the payment processing system determines that the time-out period for modifying the selection to directly purchase the advertised product has expired, the payment processing system automatically completes a purchase of the advertised product on behalf of the user. If, however, the payment processing system receives a modification input from the user before the time-out period expires, the payment processing system ceases the automatic purchase transaction and processes the received modification input. |
| US09430791B1 |
Virtual goods having nested content and system and method for distributing the same
Virtual goods having nested content are distributed. The virtual goods can be branded or not branded. The nested content can be virtual goods, digital media (music files, video files, pictures and/or other digital media), promotional content (e.g., coupons, incentives, advertisements and/or other promotional content) and/or other nested content. The nested content can include one or more units or combinations of units. |
| US09430788B2 |
Retail location robotic wall system
A robotic retail wall is presented allowing for the dispensing of merchandise within a retail location. The robotic wall includes commodity products and robotics that pick and deliver products to consumers in response to input at a kiosk. The robotics and products are separated from a retail space by a transparent barrier, allowing consumers in the retail space to view the actions of the robotics in retrieving a product. Behind the robotic wall is a product stocking area, where commodity products can be added to the robotic wall with assistance from the robotics. |
| US09430780B2 |
Communication service method and communication apparatus thereof
A communication service method wherein a user ID is registered at server. Video data from the user's terminal is transmitted to the server. The user selects the setting of whether image data is used with that video data; and the user's selected setting is stored at the server with the user ID. When the stored setting indicates that image data is used, the video data and the image data are transmitted from the server to one or more other terminals. |
| US09430776B2 |
Customized E-books
An e-book management system receives a request for an e-book from a user client operated by a user. The e-book management system accesses a user profile associated with the user and an e-book profile associated with the e-book. The e-book profile contains content sections referencing portions of the e-book, and containing information describing the characteristics of those portions. Based on the user profile, display settings for the e-book are generated. The display settings contain instructions describing how to transform the e-book based on the content sections. The display settings may be used by the e-book management system to transform the e-book, which can then be sent to the user client. Alternatively, the display settings may be sent to the user client, where they may be used to transform the e-book prior to display. |
| US09430775B2 |
System and method for analyzing and tuning a marketing program
A method for permitting a program to be analyzed and tuned includes the steps of receiving a program which itself includes a plurality of stages, where execution of the program follows a plurality of distinct paths, each of the distinct paths including one or more of the stages. The method further includes determining unique paths of the program and determining execution boundaries of the program. In addition, the method includes persisting the unique paths and the execution boundaries in a database, and changing an execution of the program based on the persisted unique paths and execution boundaries. |
| US09430768B2 |
Mobile checkout systems and methods
A mobile checkout system and method for completing a purchase transaction to purchase items from an internet merchant. A user browses and selects items for purchase from the merchant through a shopping application or browser. During the processing of the transaction, a checkout application installed on a mobile communication device is launched. The checkout application receives a checkout token created by a checkout server that identifies the purchase transaction. The checkout application uses this token and communicates with the checkout server to cause the checkout server to complete the purchase transaction, in which payment data is securely transmitted using a cryptogram. |
| US09430767B2 |
Tokenization in mobile environments
Data can be protected in mobile and payment environments through various tokenization operations. A mobile device can tokenize communication data based on device information and session information associated with the mobile device. A payment terminal can tokenize payment information received at the payment terminal during a transaction based on transaction information associated with the transaction. Payment data tokenized first a first set of token tables and according to a first set of tokenization parameters by a first payment entity can be detokenized or re-tokenized with a second set of token tables and according to a second set of tokenization parameters. Payment information can be tokenized and sent to a mobile device as a token card based on one or more selected use rules, and a user can request a transaction based on the token card. The transaction can be authorized if the transaction satisfies the selected use rules. |
| US09430766B1 |
Gift card recognition using a camera
Various embodiments describe systems and methods enable a computing device of a user to capture an image of a gift card, or other such monetary device containing a code, with a camera or otherwise receive an image of that gift card. The computing device can be configured to recognize codes, such as digit claim codes, of the gift card by using one or more image processing, computer vision, and/or machine learning algorithms. After a successful detection and verification of a claim code, money or funds deposited in, or otherwise available from, an account associated with the gift card can be utilized, such as applied to a purchase or deposited into the user's account. In many instances, a user interface (UI) can be provided on the computing device for the user to use to capture an image of a gift card and redeem the funds from the corresponding card. |
| US09430764B2 |
Financial server, IC card terminal, and financial information processing method
A system capable of charging up electronic money cards using a credit card is provided. A PIN is authenticated between a card terminal and the credit card. The card terminal transmits to a credit company server an authentication result, amount information indicating an amount with which to charge up, and a credit card number of the credit card. After billing, the credit company server transmits the amount information and the credit card number to an electronic money server. The electronic money server identifies an electronic money card based on the credit card number. The electronic money server generates amount change information for adding the amount with which to charge up to “VALUE”, and transmits the amount change information to the card terminal. The electronic money card updates the amount of “VALUE” stored therein to an amount specified by the amount change information. |
| US09430763B2 |
Wearable payment processing device
Various embodiments each include at least one of devices, systems, methods, and software of or including a wearable payment processing device. A wearable payment processing device is a wearable device that allows for conducting point-of-sale transactions. One embodiment includes a mounting base having opposing sides. A first opposing side is adapted to attach to a fixed base and a second opposing side is adapted to attach to a payment processing device. The payment processing device includes a payment card reader, an imaging device, and a display device electrically interconnected by a mainboard. The mainboard of such includes at least one processor, at least one memory device, and a network interface device. The at least one memory device stores instructions executable by the at least one processor to perform product purchase transactions for products identified via the imaging device and with payment data received via the payment card reader. |
| US09430762B2 |
Fee management system, transmission system, and fee management method
A disclosed fee management system is for managing attending fees that are charged when transmission terminals attend a conversation in a transmission management system, which manages transmission of information associated with the conversation between the transmission terminals. The fee management system includes an acquisition unit configured to acquire attending hours information and conversation quality information, the attending hours information indicating attending hours for which the respective transmission terminals have attended the conversation, the conversation quality information indicating conversation communication service quality provided during the conversation; an attending hours computing unit configured to compute total attending hours based on the attending hours information, the total attending hours indicating hours for which the terminal has attended the conversation; and an attending fee computing unit configured to compute an attending fee for each of the terminals based on the corresponding total attending hours and the conversation quality information. |
| US09430758B2 |
User interface component with a radial clock and integrated schedule
Techniques are provided to obtain event scheduling information for one or more events occurring within a time period and to obtain a reference time. A composite display widget is generated comprising a radial time indicator for the reference time and a radial event indicator for a first event of the one or more events based on the scheduling information. The composite display widget is displayed. The composite display widget can be used to display time integrated with events scheduled from a plurality of scheduling applications to provide a small icon-based scheduling package that can be viewed at a glance by a user. |
| US09430757B2 |
Rich personalized communication context
A method for displaying context information on a user device, the method includes: identifying a triggering event associated with a contact; identifying a user associated with the user device; identifying a personalized configuration profile is based on at least one of an attribute of the contact attribute or an attribute of the user; identifying the context information associated with the personalized configuration profile; and retrieving the context information for displaying on the user device. |
| US09430756B2 |
Patent claims analysis system and method
A system and method for facilitating patent grant and patent application claims examination; including the functions of automated importing of patent claims, automated parsing of the claims into their hierarchy, and compression/expansion of the parsed claims to/from the independent claim level. |
| US09430751B2 |
Method, system and apparatus for generation of lot codes and expiry dates
According to embodiments described in the specification, a method, system and apparatus for code and expiry date generation are provided. The method comprises receiving a request to generate a code at the processor; automatically selecting one of a plurality of code generation rules from the memory based on an item identifier derived from the request, the selected rule including one or more code fragment definitions; retrieving data from at least one reference table stored in the memory, based on the code fragment definitions; generating the one or more code fragments according to the selected rule using the retrieved data; and concatenating the generated code fragments to generate the code. |
| US09430750B2 |
Predictive approach to environment provisioning
Embodiments of the present invention provide methods, systems, and computer program products for building an environment. Embodiments of the present invention can be used to allocate resources and build an environment such that the environment is built when a user is prepared to test one or more portions of code in the environment. Embodiments of the present invention can be used to reduce the “lag time” developers experience between waiting for the code to be built and for resources to be provisioned, and can also provide a less costly alternative to maintaining and operating dedicated environments. |
| US09430749B2 |
Architectural planning system and process therefor
An architectural planning system, that includes software and the process thereof, which actively tracks the relationship of organizational groups as well as the required connections therebetween, which information can be actively taken into account during an architectural planning phase. Generally, this provides an improved software tool and process for planning the physical locations of organizational groups within the building space. Further, changes in organizational needs can be readily modified and adapted through direct and dynamic collaboration between these parties. |
| US09430745B2 |
Pre-executing workflow preparation activities based on activity probabilities and system load and capacity threshold requirements
In a Workflow Management System with a workflow having a sequence of activities of an underlying business process, logical wait situations occur when a given activity depends upon completion of a prerequisite preparation activity. A method for decreasing the resulting run-time delays includes: identifying a primary activity and an associated preparation activity required to be done before executing the primary activity; navigating through the process template of the underlying workflow and calculating the probability at a node of the process template that the primary activity will be reached for a current process instance; and pre-executing the preparation activity in parallel to the activity sequence if the probability exceeds a predetermined threshold. |
| US09430739B2 |
Determining general causation from processing scientific articles
Examples of the disclosure are directed toward generating a causation score with respect to an agent and an outcome, and projecting a future causation score distribution. For example, a causation score may be determined with respect to a hypothesis that a given agent causes a given outcome, and the score may indicate the acceptance of that hypothesis in the scientific community, as described by scientific literature. A future causation score distribution, then, may indicate a probability distribution over possible future causation scores, thereby predicting the scientific acceptance of the hypothesis at some specific date in the future. A future causation score distribution can be projected by first generating one or more future publication datasets, and then determining causation scores for each of the one or more future publication datasets. |
| US09430737B2 |
Spiking model to learn arbitrary multiple transformations for a self-realizing network
A neural network, wherein a portion of the neural network comprises: a first array having a first number of neurons, wherein the dendrite of each neuron of the first array is provided for receiving an input signal indicating that a measured parameter gets closer to a predetermined value assigned to said neuron; and a second array having a second number of neurons, wherein the second number is smaller than the first number, the dendrite of each neuron of the second array forming an excitatory STDP synapse with the axon of a plurality of neurons of the first array; the dendrite of each neuron of the second array forming an excitatory STDP synapse with the axon of neighboring neurons of the second array. |
| US09430735B1 |
Neural network in a memory device
Devices, systems and methods for operating a memory device facilitating a neural network in a memory device are disclosed. In at least one embodiment, the memory device is operated having a feed-ward neural network operating scheme. In at least one other embodiment, memory cells are operated to emulate a number of neural models to facilitate one or more neural network operating characteristics in the memory device. |
| US09430732B2 |
Three-dimension RFID tag with opening through structure
In embodiments of the present invention improved capabilities are described for a three-dimensional Radio Frequency Identification (RFID) tag structure with an opening though the structure. |
| US09430730B2 |
Anti-skimming payment card
A payment card may include a read sensor configured to detect a reading of the payment card by a card reader. In particular, the payment card may include a controller or a processor configured to count a number of times the payment card is read by other card readers. The payment card may implement card security measures based on the number of reads detected by the read sensor. The payment card may further include a magnetic stripe emulator configured to emulate signal patterns of a magnetic stripe when the magnetic stripe is read by a card reader. The controller may disable the magnetic stripe emulator when the number of reads detected by the read sensor exceeds a predetermined number. |
| US09430723B1 |
Printing device software management and common interface
The present disclosure is directed to a method for managing printing device software. The method includes receiving, at a computing device, a request to print a document file. The method also includes receiving a selection of a particular printing device with which to print the document file. The method further includes performing a search operation to determine whether a printer driver for the particular printing device is stored on the first computing device. Additionally, the method includes causing a data transfer of the printer driver from a server onto the first computing device over a wide area network upon determining that the printer driver is not stored on the computing device. Further, the method includes converting, using the printer driver, the document file into a print job. The method also includes transmitting, to the particular printing device, instructions to execute the print job. |
| US09430718B1 |
Efficient local feature descriptor filtering
The present disclosure generally relates to methods and computer program products for searching for a similar image among a plurality of stored images, and in particular to a method and computer program product used in a content based image retrieval system where roughly similar images are clustered and feature vectors for the clustered images are filtered based on a matching frequency for the feature vectors among the images in the cluster. |
| US09430716B2 |
Image processing method and image processing system
An example is an image processing method including a step of acquiring data containing an image, an extraction step of extracting a first image region from the acquired data based on the type of software for generating the acquired data, an extraction step of extracting a second image region the same as or similar to each of images held in a storage unit from the acquired data by comparing the acquired data and each of the images, an extraction step of extracting a third image region the same as or similar to each of the images from the acquired data by comparing the image feature amount of the acquired data and the image feature amount of each of the images, and a step of identifying an image in the acquired data to be stored in the storage unit based on the image regions and reliabilities of the extraction steps. |
| US09430715B1 |
Identifying and modifying cast shadows in an image
Methods and systems for detection and removal of cast shadows from an image. In particular, one or more embodiments compute correspondences between image patches in the image using a grid-based patch-matching algorithm. One or more embodiments then train a regression model to detect shadows from the computed patch correspondences. One or more embodiments then segment the detected shadows into shadow regions and identify cast shadows from the shadow regions. Once the cast shadows are identified, one or more embodiments use patch-based synthesis of pixels guided by a direct inversion of the image. Optionally, one or more methods can use pixels from the synthesized image and the naïve inversion of the image, based on a synthesis confidence of each pixel, to produce a combined result. |
| US09430706B1 |
System and method for detection of in-vivo pathology sequences
An in-vivo imaging system and method to automatically detect a pathology frame sequence in an image stream captured in vivo. An image stream comprising a plurality of image frames captured in vivo may be received, and a pathology score for at least a portion of the image frames is received. A seed frame which includes at least one pathology candidate may be selected, and the position of the pathology candidate in the seed frame may be determined. A sequence of frames adjacent to the seed frame is defined comprising frames that depict the pathology candidate, and a pathology sequence score is calculated based on the sequence, the pathology sequence score correlating to the probability that the sequence of frames adjacent to the seed frame includes a pathology. If the pathology sequence score is within a range, a display method may be adapted, or the pathology score may be changed based. |
| US09430705B2 |
Information processing apparatus, information processing method, information processing system, and program
There is provided an information processing apparatus including a face image acquisition section which acquires face images extracted from images which are classified into an identical time cluster by performing time clustering, and a person information generation section which classifies the face images for each time cluster, and generates person information in which persons regarded as an identical person are identified based on the face images which are classified. |
| US09430698B2 |
Information input apparatus, information input method, and computer program
An information input apparatus includes an observation unit that observes an environment including a user and one or more apparatuses to be controlled and includes a sensor; a learning unit that separates a foreground including the user and the one or more apparatuses to be controlled and a background including the environment except for the foreground from observation data obtained by the observation unit and learns three-dimensional models of the foreground and the background; a state estimation unit that estimates positions and postures of already modeled foregrounds in the environment; a user recognition unit that identifies fingers of the user from the foreground and recognizes a shape, position, and posture of the fingers; and an apparatus control unit that outputs a control command to the one or more apparatuses to be controlled on the basis of the recognized shape, position, and posture of the fingers. |
| US09430697B1 |
Method and system for face recognition using deep collaborative representation-based classification
The present invention provides a face recognition method. The method includes obtaining a plurality of training face images which belongs to a plurality of face classes and obtaining a plurality of training dictionaries corresponding to the training face images. A face class includes one or more training face images. The training dictionaries include a plurality of deep feature matrices. The method further includes obtaining an input face image. The input face image is partitioned into a plurality of blocks, whose corresponding deep feature vectors are extracted using a deep learning network. A collaborative representation model is applied to represent the deep feature vectors with the training dictionaries and representation vectors. A summation of errors for all blocks corresponding to a face class is computed as a residual error for the face class. The input face image is classified by selecting the face class that yields a minimum residual error. |
| US09430695B2 |
Determining which participant is speaking in a videoconference
Aspects herein describe methods and systems of receiving, by one or more cameras, images in which the images comprise facial images of individuals. Aspects of the disclosure describe extracting the facial images from the images received, sorting the extracted facial images into separate groups wherein each group corresponds to the facial images of each individual, and selecting, for each individual, a preferred facial image from each group. The preferred facial images selected are transmitted to a client for display. Aspects of the disclosure also describe selecting either a facial recognition algorithm or an audio triangulation algorithm to use to determine which individual is speaking wherein the selection is based on whether lip movement of one or more of the individuals is visible in the images received from the cameras. |
| US09430693B2 |
Biometric authentication apparatus and biometric authentication method
A biometric authentication apparatus includes: a storage unit which stores identification information and authentication information of a plurality of registrants; a deletion process unit which registers, when receiving a request to delete the authentication information of any of the plurality of registrants, the identification information of the registrant to a deletion list, and deletes, from the storage unit, the authentication information of the registrant corresponding to the identification information registered on the deletion list at predetermined time; and an authentication process unit which matches the biometric information of the plurality of registrants with biometric information of a user based on the authentication information of each registrant and authentication information extracted from biometric data representing the biometric information of the user to determine whether or not to authenticate the user as any of the plurality of registrants other than the registrants corresponding to the identification information registered on the deletion list. |
| US09430690B2 |
Optical information reading device
Provided is an optical information reading device that displays, as an image, information that can be conveniently checked in setting work and in maintenance work. A decoding unit decodes image data acquired by an imaging element, and an arithmetic operation unit arithmetically operates a matching level indicating easiness of the decoding of a code, stability of the decoding, a margin of the decoding or pixel-per-cell in the decoding unit. Furthermore, a UI management unit and an image display device display, as an image, at least one of the matching level, the image data acquired by the imaging element, and an average success rate (reading success rate) of the decoding obtained by decoding a plurality of pieces of image data obtained by capturing an image of the code a plurality of times. |
| US09430688B1 |
Overlapping multi-signal classification
A system and method for multi-signal classification that classifies a signal or a variable utilizing topological data analysis (TDA) specifically, via the theory of persistent homology; and encode the persistent homology of a data set in the form of a parameterized version of a Betti number by way of a topology data function which is more generally referred to as a persistence diagram or barcode. |
| US09430679B2 |
Display device and method aiming to protect access to audiovisual documents recorded in storage means
A display device and method aiming to protect access to audiovisual documents recorded in a memory. The display device includes a setting device for setting a masking threshold of the documents. The display device further includes a masking device for masking recorded documents the seniority of which in the memory is greater than the masking threshold. |
| US09430676B1 |
Processor related noise encryptor
An apparatus for encrypting processor related noise is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a frequency selection module that selects frequencies for a first noise output. The frequencies are within a range of frequencies of a second noise output. The second noise output is produced by one or more first voltage regulating modules providing power to a processor. The apparatus includes an amplitude selection module that selects an amplitude for each frequency of the first noise output. The apparatus includes a noise scrambling module that produces the first noise output based on one or both of the frequency selection module and the amplitude selection module. The first noise output combines with the second noise output to produce a third noise output such that coherence between the third noise output and operations of the processor is below a threshold. |
| US09430675B2 |
Encrypting pin pad
The present invention provides a method and apparatus for protecting an Encrypting PIN Pad (EPP) against tampering. The apparatus provides an EPP comprising a first layer comprising at least two spaced apart electrode elements, and a second layer comprising at least one bridge element for electrically bridging a space between the at least two electrode elements when the first layer and the second layer are urged together. |
| US09430672B2 |
Stack fusion architecture including distributed software clusters to enable software communication services
A stack fusion architecture enables a cloud provider to provide Software-as-a-Service (SaaS) offerings to multiple organizations. Each organization operates a Infrastructure-as-a-Service (IaaS) platform and is associated with an organization domain. A cluster of software/communication services is deployed to each platform. Users registered to an organization domain have access limited to the cluster uniquely associated with that domain. The architecture includes a globally accessible domain-to-cluster map used to map each cluster to the associated domain. A locally accessible user-to-cluster map is stored in each cluster to map that cluster to each user registered to the domain uniquely associated with that cluster. The architecture enables communication between users provisioned on different clusters and registered to different domains without exposing private information to the cloud provider. |
| US09430665B2 |
Dynamic authorization to features and data in JAVA-based enterprise applications
Systems and methods are presented for dynamically controlling role-based access to enterprise applications. The access includes both a user's ability to access a requested functionality (hereinafter referred to as “features”) in an enterprise applications, as well as the user's ability to access the specific data (and request filtering of the data) within the enterprise applications. The systems and methods provide dynamic control by utilizing a number of separate tables for identifying each element (user, role and feature), with join-tables used to define, on an active/customized basis, the association of each user with respect to a particular role (user_role join-table) and association of each feature with the listing of roles (feature_role join-table). The join-tables and specific element tables may be modified during runtime to modify any of the associations or listings. |
| US09430662B2 |
Provisioning authorization claims using attribute-based access-control policies
Disclosed are methods and devices for provisioning authorization claims, which are enforced to control access of users to objects (resources) in a computer system, and which are to be equivalent to an attribute-based access control (ABAC) policy. A policy converter according to the invention includes a policy processor processing the policy by partial evaluation against attribute values of the users, objects or permission levels in the system and outputting simplified policies, which are subject to reverse evaluation in a reverse policy evaluator, whereby users, objects and permission levels to be associated by way of a single authorization claim are obtained. Responsible for the defining of the authorization claim and its distribution in the computer system are an authorization claim generator and an authorization claim distribution interface. The invention may be so configured as to return a single authorization claim for each combination of an object and a permission level. |
| US09430660B2 |
Managing access in one or more computing systems
Embodiments pertaining to managing access in one or more computing systems can include an operations controller in communication with the one or more computing systems for managing commercial transactions of the one or more computing systems and an access management controller in communication with the operations controller. The access management controller can receive an input including user roles and actions associated with the one or more computing systems. The access management controller can provide the input to the operations controller for implementation of access rules in accordance with relationships between the user roles and the actions. The access management controller can attempt to access in the one or more computing systems at least a portion of the user roles and the actions after the operations controller has implemented the access rules. The access management controller can compare the attempted access with the relationships to determine access discrepancies. |
| US09430659B2 |
Locating cryptographic keys stored in a cache
Example embodiments provide various techniques for locating cryptographic keys stored in a cache. The cryptographic keys are temporarily stored in the cache until retrieved for use in a cryptographic operation. The cryptographic key may be located or found through reference to its cryptographic key identifier. In an example, a particular cryptographic key may be needed for a cryptographic operation. The cache is first searched to locate this cryptographic key. To locate the cryptographic key, the cryptographic key identifier that is associated with this cryptographic key is provided. In turn, the cryptographic key identifier may be used as an address into the cache. The address identifies a location of the cryptographic key within the cache. The cryptographic key may then be retrieved from the cache at the identified address and then used in the cryptographic operation. |
| US09430658B2 |
Systems and methods for secure provisioning of production electronic circuits
To securely configure an electronic circuit and provision a product that includes the electronic circuit, a first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the circuit. A second entity (e.g., an OEM): 1) derives a trust anchor from a code signing public key; 2) embeds the trust anchor in a first circuit copy; 3) causes the first circuit copy to generate a secret key derived from the trust anchor and the embedded secret value(s); 4) signs provisioning code using a code signing private key; and 5) sends the code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second circuit copy and causes it to: 1) generate the secret key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code. The OEM can authenticate the second circuit copy using the first circuit copy and a challenge/response protocol. |
| US09430651B2 |
Digital rights management license archiving
An arrangement is provided where a media server temporarily stores a DRM license that is associated with downloaded media content prior to copying the DRM license to a physical archival medium such as an optical disc. When the media server confirms that the DRM license is successfully copied to the physical archival medium, it destroys the temporarily stored DRM license. |
| US09430649B2 |
Automatic strong identity generation for cluster nodes
Aspects of the subject matter described herein relate to clusters. In aspects, an image is created to install software onto nodes of the cluster. A root secret of the cluster is injected into the image. After installing the software of the image onto a node of the cluster, the node may boot into a secure mode, detect that individualization is needed for the node to join a cluster, create an identity for authenticating with other nodes of the cluster, chain the identity via the root secret, and then securely erase the root secret from the node prior to assuming node duties. Among other things, this allows a single image to be used for installing software on all nodes of a cluster without the compromise of a single node compromising the entire cluster. |
| US09430648B2 |
Method and apparatus for near field communication
A method of updating firmware of a near field communication (NFC) device includes copying metadata, which is included in a firmware image file, from an application processor to the NFC device. One of a certification success signal and a certification fail signal is provided from the NFC device to the application processor after the NFC device verifies an integrity of the metadata. Firmware data, which is included in the firmware image file, is copied from the application processor to the NFC device when the application processor receives the certification success signal from the NFC device. |
| US09430644B2 |
Systems, methods, and apparatus to enhance the integrity assessment when using power fingerprinting systems for computer-based systems
A power fingerprinting system is adopted for assessing integrity of a target computer-based system. In one implementation, the power fingerprinting system may receive, at a first module, side-channel information of a first target component of a system, the first module being collocated with the first target component; obtain a power fingerprint for the first target component based on the side-channel information for the first target component, the power fingerprint for the first target component representing a plurality of execution statuses of the first target component; receive, at a second module, side-channel information of a second target component of the system, the second module being collocated with the second target component, the power fingerprint for the second target component representing a plurality of execution statuses of the second target component; and obtain a power fingerprint for the second target component based on the side-channel information for the second target component. |
| US09430643B2 |
Detecting malicious computer code in an executing program module
A computer program includes a plurality of different types of computer program instructions. Prior to execution of the computer program, the computer the computer program instructions of each of the types. At a time during execution of the computer program, the computer counts the computer program instructions of each of the types. The computer, in response to determining that the count for one of the instruction types determined prior to execution of the computer program differs by at least an associated threshold value from the count for the same instruction type determined during execution, makes a record that the computer program has an indicia of maliciousness. |
| US09430642B2 |
Providing virtual secure mode with different virtual trust levels each having separate memory access protections, interrupt subsystems and private processor states
A virtual machine manager (e.g., hypervisor) implements a virtual secure mode that makes multiple different virtual trust levels available to virtual processors of a virtual machine. Different memory access protections (such as the ability to read, write, and/or execute memory) can be associated with different portions of memory (e.g., memory pages) for each virtual trust level. The virtual trust levels are organized as a hierarchy with a higher level virtual trust level being more privileged than a lower virtual trust level, and programs running in the higher virtual trust level being able to change memory access protections of a lower virtual trust level. The number of virtual trust levels can vary, and can vary for different virtual machines as well as for different virtual processors in the same virtual machine. |
| US09430632B2 |
Function performing apparatus and storage medium
A function performing apparatus includes a function performing unit, an operation unit, a processor and memory. The function performing apparatus receives a first instruction from a portable device, determines whether first authentication information is to be registered in an authentication memory, registers the first authentication information in authentication the memory, transmits the first authentication information, receives a second instruction including the first authentication information from the portable device, changes a state of the function performing apparatus from a non-permission state to a permission state if the second instruction is received while the first authentication information is registered in the authentication memory and changes the state from the non-permission state to the permission state if second authentication information is input to the function performing apparatus by the operation unit while the second authentication information is registered in the authentication memory. |
| US09430631B2 |
Connection control device establishing connection between portable type mobile terminal and information processing device by wireless communication
A connection control device acquires information on a position in which a user performs manipulation input to information processing device and information on a travel distance of a portable type mobile terminal. The connection control device compares the acquired pieces of information to determine whether the manipulation input performed by the user corresponds to a travel of the portable type mobile terminal. The connection control device establishes a wireless connection between the information processing device and the portable type mobile terminal according to a determination result. |
| US09430624B1 |
Efficient logon
Methods and systems for efficiently logging in or onto a computer system or other restricted system are described. An enterprise device may detect that a user device is within a detectable range of the user device. A user profile associated with the user device may be identified. The user and/or the user device may provide authentication information to the enterprise device, and the user may be granted access when the authentication information has been verified. |
| US09430617B2 |
Content suggestion engine
Systems and methods for content selection and processing in an information system are described herein. In one example, a content suggestion engine operates to select, suggest, or recommend content to human users. The selection of content may be suited to a goal or set of goals set by a human user (for example, content recommendations used to assist the human user with achieving a personal health goal). The content suggestion engine may evaluate information to help determine the appropriateness of the content suggestions, considering factors such as a psychological profile, medical conditions, lifestyle, demographics, and goals. The content may be further filtered and weighted to select a subset of content and suggested actions most relevant to the human user. |
| US09430610B2 |
Re-sequencing pathogen microarray
The present invention relates to pathogen detection and identification by use of DNA resequencing microarrays. The present invention also provides resequencing microarray chips for differential diagnosis and serotyping of pathogens present in a biological sample. The present invention further provides methods of detecting the presence and identity of pathogens present in a biological sample. |
| US09430609B2 |
Electronic device and method for analyzing adjoining parts of a product
A scanner obtains point-cloud data of adjoining parts of a product. A computing device reads two point-clouds from the point-cloud data, fits two or more lines according to the two point-clouds, selects two lines that have the same ascending direction from the two or more lines, and creates a two-dimensional coordinates system base on the two selected lines. The computing device determines a highest point in each of the two point-clouds based on distances from each point in either of the point-clouds to a corresponding selected line, and determines two nearest points in the two point-clouds. A difference between Y coordinates of the two highest points is determined as a gap-height of two adjoining parts of the product, and a difference between X coordinates of the two nearest points is determined as a gap-width between two adjoining parts. |
| US09430607B2 |
Electron beam drawing apparatus, electron beam drawing method, and storage medium
An electron beam drawing apparatus includes: an accepting unit that accepts input graphic information, which is information representing at least one graphic; a graphic width acquiring unit that acquires a width of each of the at least one graphic represented by the input graphic information; a generating unit that generates approximate graphic information representing at least one approximate graphic, which is a graphic configured by at least one rectangle matching the width of the graphic, and is a graphic that approximates each of the at least one graphic represented by the input graphic information; and a drawing unit that draws the at least one approximate graphic represented by the approximate graphic information generated by the generating unit. |
| US09430598B2 |
Dual mode logic circuits
A method for designing a dual-mode logic circuit which is selectably operational in static and dynamic modes is performed as follows. A basis library with a DML inverter and dual-mode logic (DML) bicells is provided. Each DML bicell includes a type-A DML logic gate with a clock input and a type-B DML logic gate with an inverted clock input. A pseudo-static library is formed from the basis library by modifying each bicell of the basis library and specifying at least one dynamic timing parameter. A dynamic library is formed from the basis library by specifying dynamic timing parameters for the basis library DML inverter and bicells. Logic behavior of the required logic circuit is defined. An initial logic circuit design synthesized from the pseudo-static library and the defined logic behavior. Finally, a dynamic circuit design is formed by replacing modified bicells with corresponding bicells from the dynamic library. |
| US09430597B2 |
Method for estimating patterns to be printed on a plate or mask by means of electron-beam lithography and corresponding printing device
This method for estimating patterns (M′PF,D′PF) to be printed by means of electron-beam lithography, comprises the following steps: printing (100), in a resin, a set of calibration patterns (MCF, DCF); measuring (120) characteristic dimensions (CD) of this set; supplying an estimation (140) of the point spread function (PSF) based on the characteristic dimensions (CD) measured; estimating (160) the patterns (M′PF,D′PF) to be printed by convoluting the point spread function (PSF) supplied with an initial value of the patterns (MPF,DPF).Furthermore, each calibration pattern printed includes a central zone exposed to the electron beam and a plurality of surrounding concentric zones with rotational symmetry. The characteristic dimensions measured are characteristic dimensions (CD) of the central zones of the patterns. The estimation of the point spread function (PSF) is calculated by inverting analytical modelling of the effect, on these characteristic dimensions, of applying the first point spread function portion (PSFBE) characterising electrons back-scattered by the substrate to the set of calibration patterns (MCF, DCF). |
| US09430596B2 |
System, method and apparatus for a scalable parallel processor
A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit. |
| US09430593B2 |
System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed. |
| US09430592B2 |
Method for simulating the electrical behaviour of an integrated diode and corresponding computerized system
A method for simulating, in an electrical device simulator, electrical behavior of an integrated diode is described. The diode is modelled using a compact model in the electrical device simulator to determine the electrical behavior of the diode in a given situation. The modelling includes modelling a series resistance relating to the active regions and to the connections, modelling a PN junction of the diode, and modelling a well resistance for positive values of a current passing through the diode involving a conductivity modulation model. The method further includes modelling of the well resistance for negative values of the current by a curve which increases steeply from an initial resistance value corresponding to a zero value of current up to a plateau. |
| US09430587B2 |
Techniques for managing media content
Various media management techniques are described. A mobile computing device may comprise a metadata information database to store metadata, a media object database to store media objects, and a media content manager to couple to the metadata information database and the media object database. The media content manager may comprise a metadata manager to retrieve and associate metadata from the metadata information database with different media objects. The media content manager may further comprise a media object classifier to classify the media objects into hierarchical categories based on the metadata. The media content manager may still further comprise an album generator to generate a media album representing a hierarchical category. Other embodiments may be described and claimed. |
| US09430586B2 |
Reference resolution
Methods, computer systems, and computer-storage media are provided for reference resolution. The present invention seeks to resolve entities in conversational search. To enable a more natural conversational search interaction, referential expressions such as pronouns are handled in queries. A component keeps track of previous queries and performs reference resolution based on an entity in the previous query and reformulates the query using an identifier for the referenced entity. Reference resolution may be performed for pronouns, plural pronouns, partial names, across domains, and on any device or platform. |
| US09430583B1 |
Extracting a portion of a document, such as a web page
A portion data structure representing a portion extracted from a formatted source document is described. A portion data structure contains a first subtree of nodes that is modeled after a second subtree of a complete hierarchical representation of the formatted source document. Explicit formatting attribute values are specified for nodes of the first subtree only where a value calculated for the formatting attribute in a node of the first subtree differs from a value calculated for the formatting attribute in the corresponding node in the second subtree at a time when the node of the first subtree descends from a reset node specifying standardized formatting attribute values. The contents of the portion data structure are usable to display the portion extracted from the formatted source document in a context other than the formatted source document. |
| US09430580B2 |
Information processing apparatus, information processing method, and program for displaying switching information
There is provided an information processing apparatus including a page switching unit for switching a display screen from a first Web page screen displayed on a display unit to a second Web page screen, and a switching information notification unit for notifying a page switching information on a notification screen before the second Web page screen is displayed while switching between the pages by the page switching unit, the page switching information is based on information included in at least the second Web page of the first and second Web pages, and the notification screen is a different screen from the first Web page. |
| US09430573B2 |
Coherent question answering in search results
Systems, methods, and computer-readable storage media for providing query-completion suggestions that include answers to the complete queries suggested while the user is formulating a search query. At least a portion of a search query is received by the search engine. As the portion of the search query is received, query-completion suggestions are identified and answers to the plausible search query completions are identified for inclusion in the search input area. Upon selection of a query-completion suggestion, the search engine results page is presented, wherein the search engine results page includes the answers in the snippets generated for the results that contain the answers to the completed queries suggested to the user. |
| US09430569B2 |
System and method for aggregating and ranking data from a plurality of web sites
System and method for collecting information from a plurality of related sites, analyzing the information and storing the relevant information in a data base for future use. According to one embodiment of the present invention, the system uses the provided list of sites, whether obtained automatically or separately, queries them and analyzes the result retrieved from each site. The information may also optionally and preferably be ranked. |
| US09430565B2 |
Providing relevant content
For providing relevant content, a search module indexes each content identifier for content received in a search result to content data. The content comprises related content identifiers. The search module further iteratively retrieves content for the indexed content identifiers and indexes the related content identifiers for the retrieved content until all related content identifiers for all the indexed content identifiers are indexed. A relevance module identifies relevant content and provides the relevant content. |
| US09430564B2 |
System and method for providing data protection workflows in a network environment
A method is provided in one example and includes receiving first sets of metadata elements representing an inventory of objects in a data storage location of a network environment and presenting an inventory view of the objects to a user. The inventory view includes a first summary of the inventory objects. The method further includes receiving a request from the user to manipulate the inventory view based on a first selected dimension group and presenting to the user a manipulated inventory view that includes a second summary of a first subset of the inventory objects. In more specific embodiments, the method includes receiving a request from the user to perform a protection task on objects of the first subset and initiating the protection task. The protection task includes one of applying a remediation policy to the objects of the first subset and registering the objects of the first subset. |
| US09430554B2 |
Object-relational mapping based on virtual columns
A server system allows object relational mapping. Objects of an object type are stored as records in a table corresponding to the object type. The server system allows new attributes to be added to an object type without altering the corresponding table. The object type comprises a set of mapped attributes that correspond to distinct columns of the associated table. The object type further comprises unmapped attributes that fail to map to distinct columns of the table. The table is associated with a virtual column for storing the unmapped attributes. The unmapped attributes of an object of the object type are encoded into a value and stored in the virtual column. The virtual column may be a column of the same table or a column of an auxiliary table. The unmapped attributes may also be stored as name value pairs in an auxiliary table associated with the table. |
| US09430550B2 |
Clustering a table in a relational database management system
Techniques are provided that address the problems associated with prior approaches for clustering a fact table in a relational database management system. According to one aspect of the invention, a database server clusters a fact table in a database based on one or more dimension tables. More specifically, rows are stored in the fact table in a sorted order and the order in which the rows are sorted is based on values in one or more columns of one or more of the dimension tables. A user specifies the columns of the dimension tables on which the sorted order is based in “clustering criteria”. The database server uses the clustering criteria to automatically store the rows in the fact table in the sorted order in response to certain user-initiated database operations on the fact-table. |
| US09430545B2 |
Mechanism for communication in a distributed database
In a method for providing communication integrity within a distributed database computer system, a first node of a plurality of nodes transmits a change notification to a second node of the plurality of nodes. The second node is a neighbor of the first node. The first node receives at least one change confirmation from the second node. The change confirmation confirms acknowledgment of the change notification by the second node and by a third node of the plurality of nodes. The third node is not a neighbor of the first node. Responsive to receiving the at least one change confirmation, the first node determines that all the plurality of nodes have acknowledged the change notification. |
| US09430542B2 |
User initiated replication in a synchronized object replication system
A snapshot of selected objects in a source repository is created in response to the user-initiated replication. The snapshot is designated as a snapshot replication job. The snapshot replication job is added to the end of a replication queue to await execution for the synchronized object replication. Unsynchronized objects in a target destination are detected by comparing a state of the selected objects in the snapshot with a current state of the target destination at the time of execution of the snapshot replication job. The unsynchronized objects in the target destination are synchronized based upon the comparison of the state of the selected objects in the snapshot with the current state of the target destination at the time of execution of the snapshot replication job. |
| US09430541B1 |
Data updates in distributed system with data coherency
Updating data in a distributed system, in which a data coordinator receives a proposed change to a data element, locks the data element, and sends an invalidation command to nodes in the distributed system. If all nodes acknowledge the invalidation command, the data coordinator updates the data element locally and unlocks the data element. If not all nodes acknowledge the invalidation command, the data coordinator terminates the proposed change and unlocks the data element. Each node that invalidated the data element requests the data element. The data coordinator returns its current value. If the value is changed, all nodes request and receive the update. If a node did not invalidate, it will not request an update, but the value will not have changed so all requesting nodes receive the previous value. Thus, all nodes have the same value for the data element and consistency is maintained throughout the system. |
| US09430540B2 |
Metal fatigue analytics and alert systems
The disclosure is directed to metal fatigue analytics and alert systems. A system in accordance with an embodiment includes: a first database on a vehicle, the database storing a list of at least one metal part in the vehicle and corresponding metal batch information for each metal part in the list; a second database on a server remote from the first database, the second database storing metal batch information for at least one batch of metal from which faulty metal parts have been constructed; a comparing system for comparing the metal batch information stored in the first database with the metal batch information stored in the second database; and a messaging system for generating a failure alert message when the comparing system finds a match between the metal batch information stored in the first database and the metal batch information stored in the second database. |
| US09430539B2 |
Universal data storage system that maintains data across one or more specialized data stores
In an embodiment, a method comprises receiving an input defining organization of one or more universal data elements; generating a universal schema that defines organization of the one or more universal data elements based on the input; associating the universal schema with a specialized plug-in, wherein the specialized plug-in maps the one or more universal data elements with data elements in one or more specialized databases maintained by a specialized data store; receiving, from a computer, a request to receive data stored in the specialized data store and comprising parameters based on the universal schema; transforming the request using the specialized plug-in to produce a specialized query; sending the specialized query to the specialized data store to execute the specialized query; receiving a specialized result set from the specialized data store; sending, to the computer, a result set based on specialized result set. |
| US09430533B2 |
Machine-assisted search preference evaluation
Various technologies described herein pertain to evaluating search preferences. A search query, a first search result list returned by a first ranker system responsive to the search query, and a second search result list returned by a second ranker system responsive to the search query are received. A classifier is employed to predict (e.g., based upon values of features of the search query, the first search result list, and the second search result list) whether a search preference judgment (e.g., a side-by-side search preference judgment, etc.) indicates a quality difference between the first search result list and the second search result list. The search query, the first search result list, and the second search result list are excluded from a set of search queries and search result list pairs to be manually judged for search preference judgments when predicted to lack the quality difference. |
| US09430529B2 |
Techniques for incrementally updating aggregation of states
Methods, systems, and computer program products are provided for generating and updating an aggregation of data states. The aggregation of data states is selectively updated by updating an affected slice of the aggregation of data states. The aggregation of data states is replaced by a new aggregation of data states created from a selective subset of detailed data state data, by adding new aggregations and deleting existing aggregations. |
| US09430527B2 |
Keyword-based content management
A method, implementable in a system coupled to a network, includes accessing a first portion of a memory device coupled to the network. The first portion has stored thereon information characterizing an entity. An information set of a predetermined information type is gathered from the first portion. First and second information subsets of the information set are organized into first and second keywords. A second portion of a memory device coupled to the network is accessed. The second portion has stored thereon a plurality of data sets. First and second subsets of the data sets are identified. Each data set of the first data-set subset includes the first keyword, and each data set of the second data-set subset includes the second keyword. The first data-set subset is stored in a third portion of a memory device coupled to the network. |
| US09430525B2 |
Access plan for a database query
A system and method of creating an access plan for a database query is disclosed. The system and method include identifying a first portion of a column of a table of a database. The first portion of the column may be in a select statement of the database query. The system and method include estimating a first statistical value for the column. The estimating may occur by analyzing a second portion of the column. The system and method include generating the access plan to predict a characteristic of a set of results for the database query. In generating the access plan, the first statistical value for the column may be used. |
| US09430522B2 |
Navigating performance data from different subsystems
Performance data can be collected from different runtime environment subsystems of a computer system while the computer system is running a program in the runtime environment. A visualization model can be displayed, and a visual query of the integrated data can be received at the visualization model. Queried data can be compiled and displayed in response to the visual query. The queried data can be drilled into in response to user input. In response to a navigation request, navigation can lead to a programming element related to a portion of the queried data. |
| US09430520B2 |
Semantic reflection storage and automatic reconciliation of hierarchical messages
Database storage of hierarchically structured messages is facilitated based on structural semantic reflection of the message and automatic reconciliation of the messages. The structural semantics of an incoming message may be assessed and database storage provisioned based on the structural semantic reflection of the message. The system may auto-adapt over time as incoming messages from a known source change and automatically generate code which applies the sequential logic to a stream of messages in order to represent the latest state for a given context. Furthermore, the hierarchical semantics of messaging formats may be applied to a flexible set of database structures that represent the raw contents of the messages. |
| US09430515B2 |
Data validation using schema definition
A system includes a first processor configured to intake a schema definition file. The schema definition file defines a set of rules that a data document must follow. The processor extracts one or more data adherence rules from the schema definition file and stores the extracted data adherence rules. Accordingly, subsequent data generation, configuration and/or validation of one or more system data objects may occur without requiring the creation of the data document. |
| US09430510B2 |
Computer implemented methods and systems for multi-level geographic query
According to one aspect of the present disclosure, a computer-implemented method is provided for processing a query for points of interest (POIs) using a hierarchical grid structure representing a geographic area. The method includes receiving a query for POIs; defining a query footprint for the query based on a location corresponding to the query, wherein the query footprint comprises query spatial identifiers for a plurality of levels of the hierarchical grid structure; matching the query spatial identifiers with one or more POI spatial identifiers organized into a plurality of indexes, wherein each one of the plurality of indexes comprises an index of the POI spatial identifiers for one of the plurality of levels; and providing an output specifying one or more POIs corresponding to the matched POI spatial identifiers. |
| US09430502B1 |
Method and apparatus for collecting and storing statistics data from network elements using scalable architecture
A method and apparatus for collecting statistics data over a communications network using scalable stateless processes are disclosed. A process capable of obtaining statistics data, in one embodiment, detects a delay associated with the availability of statistics data in accordance with predefined lag duration, and subsequently, adds one or more stateless processes to a pool of stateless processes to increase capacity of collecting statistics data. Upon enabling a stateless process to collect statistics data from network element (“NE”) in response to a statistics collecting tasks, the statistics data is stored in a database. |
| US09430500B2 |
Method and device for operating image in electronic device
Disclosed are a method and device for providing a user-based interactive image by inserting various pieces of image processing information corresponding to a user input into an image in an electronic device. The method includes: displaying an image, identifying image processing information of the image in response to a user input for the image, and outputting feedback through image processing responding to the user input based on the image processing information. The present disclosure can be applied to various other embodiments based on the aforementioned embodiment. |
| US09430498B2 |
Methods and systems for generating a digital celebrity map tour guide
Systems and methods of creating a tour on a digital celebrity map are disclosed, including steps to receive a user geolocation; determine a map area around the user geolocation; retrieve, from a data repository, celebrity geolocations within the map area, wherein each celebrity geolocation is associated with at least one named celebrity, and wherein each of the celebrity geolocations is associated with a celebrity geolocation type selected from the group consisting of celebrity real estate property, celebrity sighting location, and celebrity hotspot; transmit the celebrity geolocations to the computing appliance, for display on the digital celebrity map; receive a request to generate a tour to the celebrity geolocations, wherein the tour starts from the user geolocation; and in response to the user request, generate for display on the digital celebrity map, the tour to the celebrity geolocations. |
| US09430496B2 |
Range of focus in an augmented reality application
A computer-implemented augmented reality method includes receiving one or more indications, entered on a mobile computing device by a user of the mobile computing device, of a distance range for determining items to display with an augmented reality application, the distance range representing geographic distance from a base point where the mobile computing device is located. The method also includes selecting, from items in a computer database, one or more items that are located within the distance range from the mobile computing device entered by the user, and providing data for representing labels for the selected one or more items on a visual display of the mobile computing device, the labels corresponding to the selected items, and the items corresponding to geographical features that are within the distance range as measure from the mobile computing device. |
| US09430493B2 |
Extension of write anywhere file layout write allocation
A write allocation technique extends a conventional write allocation procedure employed by a write anywhere file system of a storage system. A write allocator of the file system implements the extended write allocation technique in response to an event in the file system. The extended write allocation technique efficiently allocates blocks, and frees blocks, to and from a virtual volume (vvol) of an aggregate. The aggregate is a physical volume comprising one or more groups of disks, such as RAID groups, underlying one or more vvols of the storage system. The aggregate has its own physical volume block number (pvbn) space and maintains metadata, such as block allocation structures, within that pvbn space. Each vvol also has its own virtual volume block number (vvbn) space and maintains metadata, such as block allocation structures, within that vvbn space. The inventive technique extends input/output efficiencies of the conventional write allocation procedure to comport with an extended file system layout of the storage system. |