Document Document Title
US09425419B2 Organic light-emitting display apparatus and method of manufacturing the same
Provided is an organic light-emitting display apparatus including a substrate; and a plurality of pixels on the substrate, wherein each of the pixels comprise: an organic light-emitting device comprising a first electrode, a second electrode, and an intermediate layer between the first electrode and the second electrode, wherein the intermediate layer comprises an organic emission layer; a driving transistor configured to drive the organic light-emitting device; and a switching transistor electrically coupled to the driving transistor, wherein the gate electrode of the driving transistor comprises a first conductive layer, and a second conductive layer between the first conductive layer and the active layer of the driving transistor and has a smaller size than the first conductive layer, and the gate electrode of the switching transistor comprises a same material as the first conductive layer.
US09425418B2 Flexible display device with bend stress reduction member and manufacturing method for the same
There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
US09425416B2 Condensed cyclic compound and organic light-emitting device including the same
A condensed cyclic compound of Formula 1 is provided. An organic light-emitting device includes the same.
US09425414B2 Organometallic complexes, and organic electroluminescence device and display using the same
Disclosed are an organometallic complex, and an organic electroluminescence device and a display device including the same. The organometallic complex is represented by the following Chemical Formula 1. The definition of the above Chemical Formula 1 is the same as described in the detailed description.
US09425413B2 Conjugated side-strapped phthalocyanines and methods for producing and using the same
The present invention provides conjugated side-strapped phthalocyanines and methods for producing and using the same. In one particular embodiment, the conjugated side-strapped phthalocyanine is of the formula: where each of the substituents are defined herein.
US09425411B2 Organic electroluminescent element
To provide an organic electroluminescent element that can attain efficiency improvement by forming an electron injection layer by a film that is stable and excellent in uniformity, and forming a charge generation layer capable of effectively exhibiting the function. In an organic electroluminescent element provided with at least one organic layer between a pair of electrodes, an electron injection layer comprising a ZnO-containing layer, and a charge generation layer containing an electron acceptor-containing film in contact with the cathode side thereof and an electron donor-containing film adjacent thereto are formed.
US09425409B2 Materials for electronic devices
The present invention relates to compounds of the to the use of the compounds in electronic devices, to processes for the preparation of the compounds, and to electronic devices comprising the compounds, preferably as electron-transport materials, as hole-blocking materials, as matrix materials and/or as emitter materials.
US09425408B2 Organic light emitting host materials
Disclosed herein are compounds represented by formula: where HT, ET, and R1-R6 are described herein. Compositions of said compounds along with organic light-emitting diode (OLED) devices related thereto are also disclosed.
US09425403B2 Light-emitting organic compound and EL display device utilizing the same
By repeating a purification process of a light-emitting organic compound several times, a thin film made of the light-emitting organic compound to be used in an EL display device contains ionic impurities at the concentration of 0.1 ppm or lower and has a volume resistivity in the range of 3×1010 Ωcm or larger. By using such a thin film as a light-emitting layer in the EL device, a current caused by reasons other than the carrier recombination can be prevented from flowing through the thin film, and deterioration caused by unnecessary heat generation can be suppressed. Accordingly, it is possible to obtain an EL display device with high reliability.
US09425401B2 9,9′-spirobixanthene derivatives for electroluminescent devices
The present invention relates to compounds suitable for use in electronic devices, and to electronic devices, especially organic electroluminescent devices, comprising these compounds.
US09425400B2 Apparatus and method for coating organic film
An apparatus and method for coating an organic film are disclosed. The apparatus comprises an evaporation device, an electron emission device and a spray device; wherein the evaporation device comprises an evaporation container, the evaporation container is a linear evaporation container, in which a uniform organic gas is generated; the electron emission device is horizontally arranged over the evaporation container such that the organic gas evaporated in the evaporation container is uniformly charged and becomes charged organic gas; the spray device is provided with an electric field, under which the charged organic gas is moved toward a substrate so as to deposit the organic film on the substrate.
US09425398B2 Complex compounds having anionic ligands containing two P donors and the use thereof in the opto-electronic field
The invention describes electronic devices comprising a metal complex compound having at least one anionic ligand containing two P donors, having the formula (I), in which R1 to R4 are, independently of one another, an atom or radical from the group comprising hydrogen, a halogen, R, RO—, RS—, RCO—, RCOO—, RNH—, R2N—, RCONR— and —Si(R)X(OR)3-X, where R=a C1-C40-hydrocarbon and X=1, 2 or 3, and E is a bridge atom from the group with carbon or boron, where an atom or radical from the group with hydrogen, halogen, —CN, R, RO—, RS—, RCO—, RCOO—, RNH—, R2N—, RCONR— and —Si(R)X(OR)3-X, where R=the C1-C40-hydrocarbon and X=1, 2 or 3, is optionally bonded to the carbon, and two radicals from the group with halogen, R, RO—, RS—, RCO—, RCOO—, RNH—, R2N—, RCONR— and —Si(R)X(OR)3-X, where R=the C1-C40-hydrocarbon and X=1, 2 or 3, are optionally bonded to the boron. The invention furthermore describes a process for the production of an electronic device of this type and processes for the generation of light or blue emission using a metal complex compound of this type.
US09425395B2 Method of fabricating a variable resistance memory device
A method of fabricating a variable resistance memory device includes preparing a substrate having a lower electrode, forming a mold layer on the substrate, patterning the mold layer to form an opening, forming a variable resistance layer having a first portion in the opening and a second portion disposed on a top surface of the mold layer, and separating the second portion of the variable resistance layer from the first portion by irradiating the variable resistance layer to form a variable resistance element in the opening.
US09425392B2 RRAM cell structure with laterally offset BEVA/TEVA
The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.
US09425388B2 Magnetic element and method of manufacturing the same
A magnetic element includes a first magnetic layer, a first non-magnetic layer on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer, the third magnetic layer having a side wall layer including a material which is included in the second non-magnetic layer; wherein the material is one of Ru and Pt as a common material to the side wall layer and the second non-magnetic layer.
US09425387B1 Magnetic element with perpendicular magnetic anisotropy for high coercivity after high temperature annealing
A magnetic tunnel junction (MTJ) is disclosed wherein a free layer has an interface with a tunnel barrier and a second interface with a metal oxide layer to promote perpendicular magnetic anisotropy (PMA) therein. A diffusion barrier is formed on a side of the metal oxide layer opposite the second interface to prevent non-magnetic metals in a hard mask or electrode from migrating to the second interface and degrading free layer PMA. A second diffusion barrier may be formed between a second electrode and a reference layer. The diffusion barrier may be a single layer of SiN, TiN, TaN, Mo, or CoFeX where X is Zr, P, B, or Ta, or is a multilayer such as CoFeX/Mo wherein CoFeX contacts the metal oxide layer and Mo adjoins a hard mask. As a result, coercivity is maintained or increased in the MTJ after annealing at 400° C. for 30 minutes.
US09425383B2 Method of manufacturing electroactive polymer transducers for sensory feedback applications
A method for fabricating electroactive polymer transducers, the includes providing an electroactive polymer film comprising an elastomeric dielectric polymer, forming an array of electrodes on the film, and sandwiching the electrode array between a top and bottom array of frame components to form an array of electroactive polymer transducers.
US09425378B2 Actuator, actuator system and actuation of an actuator
The invention relates to an actuator (1) having stacked piezoelements (16), first and second inner electrodes (5, 3) disposed alternatingly between the piezoelements (16), a first outer electrode (4) which is electrically conductively connected to the first inner electrode (5), a second outer electrode (2) which is electrically conductively connected to the second inner electrode (3), characterized in that the actuator (1) comprises a plurality of actuator segments (81, 82, 83, 84, 85) and that the second outer electrode (2) comprises separate electrode segments (21, 22, 23, 24, 25) each of which are electrically conductively connected to the second inner electrodes (3) in one of the actuator segments (81, 82, 83, 84, 85).
US09425375B2 Method for making high-temperature superconducting film
A method for making a high-temperature superconducting film includes loading a SrTiO3 substrate in an ultra-high vacuum system. A single crystalline FeSe layer is grown on a surface of the SrTiO3 substrate by molecular beam epitaxy. A protective layer with a layered crystal structure is grown by molecular beam epitaxy and covering the single crystalline FeSe layer.
US09425374B2 Electronic apparatus and protective cover of mobile device
An electronic apparatus and a protective cover for a mobile device are disclosed. The protective cover is removably attached on an outer surface of a mobile device. The protective cover comprises an outer protective layer, a thermo-conductive layer and a thermoelectric material layer. The thermo-conductive layer is attached on the outer surface of the mobile device. The thermoelectric material layer has a first side adjacent to the thermo-conductive layer and a second side adjacent to the outer protective layer. The thermoelectric material layer generates a current according to a temperature difference between the first side and the second side.
US09425373B2 Light emitting module
A light emitting module includes: a first substrate including a resin having insulation properties, and a copper component embedded in the resin; a second substrate placed above the copper component of the first substrate, and soldered to the copper component; a mounting electrode formed above the second substrate; and an LED placed above the second substrate, and gold-tin soldered to the mounting electrode.
US09425372B2 LED device, method of manufacturing the same, and light-emitting apparatus
The LED device (27) has a LED bare chip (25) mounted directly on a metal contact (28), and supplies power to the bare chip and conducts heat from the bare chip via the metal contact.
US09425371B2 Light-emitting device and electronic device
An object is to provide a light-emitting device having a structure in which an external connection portion can easily be connected and a method for manufacturing the light-emitting device. A light-emitting device includes a lower support 110, a base insulating film 112 over the lower support 110 which has a through-hole 130, a light-emitting element 127 over the base insulating film 112, and an upper support 122 over the light-emitting element 127. An electrode 131 is provided in the through-hole 130, and the external connection terminal 132 electrically connected to the electrode 131 is provided below the base insulating film 112. The external connection terminal 132 is electrically connected to the external connection portion 133 and functions as a terminal that inputs a signal or a power supply into the light-emitting device. This light-emitting device has a structure in which an external connection portion can easily be connected.
US09425368B2 Engineered-phosphor LED packages and related methods
In accordance with certain embodiments, regions of spatially varying wavelength-conversion particle concentration are formed over light-emitting dies.
US09425367B2 Light emitting device having opening for extracting light and method for manufacturing light emitting device having opening for extracting light
A light emitting device includes a flip-chip mounted type light emitting element, a phosphor-containing member, and a first reflecting member. The flip-chip mounted type light emitting element has a pair of electrodes disposed on a bottom surface side. The phosphor-containing member is provided at least above the light emitting element and separated from the light emitting element. The first reflecting member is configured to cover the phosphor-containing member. An opening is in at least one of side faces of the light emitting device, the opening extracting light emitted from the light emitting element and light whose wavelength is converted by the phosphor-containing member.
US09425366B2 Light emitting device including resin member surrounding sides of light emitting element
A light emitting device includes a substrate member, a light emitting element, a resin member, an insulating layer and a fluorescent material layer. The light emitting element is arranged on the substrate member. The resin member surrounds sides of the light emitting element, and has a top portion located higher than a light emission surface of the light emitting element. The insulating layer covers the light emission surface of the light emitting element and an outer wall surface and an inner wall surface of the top portion of the resin member. The fluorescent material layer covers a surface of the insulating layer.
US09425364B2 Method for the production of white LEDs and white LED light source
For the production of a white LED having a predetermined color temperature, a blue LED (2a-2d) or a UV LED is coated with a conversion layer (5) which absorbs the blue light or UV light and emits light of greater wavelength. In accordance with the invention, the exact wavelength of the LED (2a-2d) is determined and the color conversion agent (5) is applied over this LED (2a-2d) in a quantity dependent upon the determined wavelength. Through this, the tolerance of the color temperature can be significantly reduced. The color conversion agent may be applied by means of dispenser or stamp, and the quantity and/or concentration selected in dependence upon the determined wavelength. Inkjet printing, deposition from the gas phase or selective removal by means of a laser is, however, also possible. The invention also relates to light sources produced in accordance with this method.
US09425360B2 Light emitting device package
A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.
US09425359B2 Light emitting diode
A light emitting diode includes a semiconductor stacked structure, a substrate, a first electrode, a second electrode and a third electrode. The semiconductor stacked structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. An undoped semiconductor layer over the first semiconductor layer may be not removed or not completely removed to increase the strength of the semiconductor stacked structure and improve the reliability of the LED and the production yields of manufacturing process. A roughened structure (or a photonic crystal) can be formed on the undoped semiconductor layer when the semiconductor stacked structure to improve the light emitting efficiency of the LED.
US09425358B2 Optoelectronic semiconductor chip and method for production thereof
An optoelectronic semiconductor chip includes a semiconductor body and a carrier, on which the semiconductor body is arranged. The semiconductor body has a semiconductor layer sequence with an active region provided for generating or receiving radiation, a first semiconductor layer and a second semiconductor layer. The active region is arranged between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is arranged on the side of the active region facing away from the carrier. A trench structure extends through the second semiconductor layer and the active region into the first semiconductor layer. An electrical contact structure with a plurality of contact strips is formed between the carrier and the semiconductor body. The contact strips in the trench structure are connected in an electrically conductive manner to the first semiconductor layer.
US09425357B2 Diode for a printable composition
An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between about 2.5 to 7 microns; a first terminal coupled to the light emitting region on a first side, the first terminal having a height between about 1 to 6 microns; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height between about 1 to 6 microns.
US09425356B2 Light emitting device
A light emitting device includes a light emitting structure having a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer; a first electrode disposed on the light emitting structure, configured as a plurality of dots and electrically connected to the first conductive semiconductor layer; an electrode pad electrically connected to the first electrode; and a second electrode electrically connected to the second conductive semiconductor layer.
US09425355B2 Semiconductor light emitting device
A semiconductor light emitting device including a first conductive semiconductor base layer on a substrate; an insulating layer on the first conductive semiconductor base layer, the insulating layer including a plurality of openings through which the first conductive semiconductor base layer is exposed; and a plurality of nanoscale light emitting structures on the first conductive semiconductor base layer, the nanoscale light emitting structures respectively including a first conductive semiconductor core on an exposed region of the first conductive semiconductor base layer, and an active layer, and a second conductive semiconductor layer sequentially disposed on a surface of the first conductive semiconductor core, wherein a lower edge of a side portion of each nanoscale light emitting structure is on an inner side wall of the opening in the insulating layer.
US09425354B2 Epitaxy base, semiconductor light emitting device and manufacturing methods thereof
An epitaxy base including a substrate and a nucleating layer disposed on the substrate. The nucleating layer is an AlN layer with a single crystal structure. A diffraction pattern of the nucleating layer includes a plurality of dot patterns. Each of the dot patterns is substantially circular, and a ratio between lengths of any two diameters perpendicular to each other on each of the dot patterns ranges from approximately 0.9 to approximately 1.1. A semiconductor light emitting device, a manufacturing method of the epitaxy base, and a manufacturing method of the light emitting semiconductor device are further provided.
US09425351B2 Hybrid heterostructure light emitting devices
Light-emitting devices having a multiple quantum well (MQW) pin diode structure and methods of making and using the devices are provided. The devices are composed of multilayered semiconductor heterostructures. The devices include one or more interfacial layers of a material that allows current tunneling through lattice mismatched heterogeneous junctions at the interfaces between the intrinsic active region and the p-type and/or n-type doped charge injection layers.
US09425350B2 Photocoupler and light emitting element
According to one embodiment, a photocoupler includes: an input terminal; a light emitting unit; a light receiving unit and an output terminal. An input electrical signal having a prescribed voltage is input into an input terminal. The light emitting unit is connected to the input terminal, includes a light emitting element configured to emit emission light, and is configured to drive the light emitting element under a constant voltage of the input electrical signal. The light receiving unit includes a light receiving element configured to receive the emission light and convert the emission light into an electrical signal. The output terminal is insulated from the input terminal and configured to output the electrical signal in accordance with the input electrical signal.
US09425347B2 Semiconductor substrate, semiconductor device, and manufacturing methods thereof
A method of manufacturing a semiconductor substrate includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a first portion of a second semiconductor layer on the first semiconductor layer and the metallic material layer, removing the metallic material layer under the first portion of the second semiconductor layer by dipping the substrate in a solution, forming a second portion of the second semiconductor layer on the first portion of the second semiconductor layer, and forming a cavity in a portion of the first semiconductor layer located under where the metallic material layer was removed.
US09425344B2 Formulation of colloidal titanium-oxide solutions composition for coating and printing methods, and improvement of the output and lifespan of organic P-I-N/N-I-P photovoltaic cells
The invention relates to a method for preparing a colloidal nanoparticle solution, including: (a) dissolving a titanium-oxide precursor, referred to as a precursor, in one or more solvents, referred to as precursor solvents; and (b) chemically converting, preferably by means of hydrolysis, said titanium-oxide precursor and said precursor solvent into a colloidal-solution solvent so as to form titanium-oxide nanoparticles that are dispersed in the colloidal-solution solvent, said colloidal solution having a dynamic viscosity of between 4 and 54 cP at 20° C. and 101,325 Pa.The invention also relates to a colloidal titanium-oxide nanoparticle solution containing a dispersion of titanium-oxide nanoparticles in a solvent or system of solvents, the viscosity of which is between 4 and 54 cP, said solution being particularly obtainable according to the method of the invention, as well as to the uses thereof, in particular for preparing photovoltaic cells. The invention also relates to a method for generating power using a semiconductor prepared from said solution.
US09425343B2 Mechanisms for forming image sensor device
Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and one photodetector formed in the semiconductor substrate. The image sensor device also includes one gate stack formed over the semiconductor substrate. The gate stack includes multiple polysilicon layers.
US09425341B2 P-I-N photodiode with dopant diffusion barrier layer
According to one aspect of the invention, there is provided a pin photodetector comprising a dopant diffusion barrier layer disposed within an active light absorbing region of the pin photodetector.
US09425335B2 Optical detector
Disclosed is an optical detector. The optical detector includes: a first dielectric layer; a graphene optical transmission line formed on the first dielectric layer; a graphene optical detector formed on the first dielectric layer and configured to detect light transmitted along the graphene optical transmission line; electric wires formed on the graphene optical detector; metal pads positioned at both ends of the graphene optical detector and connected with the electric wires; and a second dielectric layer formed on the graphene optical transmission line, in which the graphene optical detector detects an intensity of light incident in a horizontal direction with respect to a surface of the graphene optical transmission line.
US09425332B2 Photosensor having emitter and receiver leads protruding from circuit-encapsulating portion to connect to light emitter and light receiver, respectively
A photosensor includes a sensor module in which emitter and receiver leads protrude from a circuit-encapsulating portion in a direction intersecting with a direction in which an external connecting terminal extends. The photosensor includes a light emitter, a light receiver, a circuit-encapsulating portion, a connecting terminal, first and second emitter leads, and first and second receiver leads. When the connecting terminal extends in a first direction, and a first plane is parallel to the first direction, the first and second emitter leads protrude from the circuit-encapsulating portion in a direction parallel to the first plane and intersecting with the first direction, and extend opposite to the first direction. The first and second receiver leads protrude from the circuit-encapsulating portion in the direction parallel to the first plane and intersecting with the first direction and opposite to a direction in which the first and second emitter leads protrude, and extend opposite to the first direction. The first and second emitter leads and the first and second receiver leads are deformed to allow the light receiver and the light emitter to face each other.
US09425331B2 Solar cell wafer connecting system
A method and apparatus for forming a solar cell structure. A first wafer and a second wafer are positioned relative to each other such that first nanotubes on the first wafer are opposite to second nanotubes on the second wafer. The first nanotubes are connected to the second nanotubes. The first wafer is connected to the second wafer to form the solar cell structure.
US09425329B2 Rectifying device and method for manufacturing the same
Disclosed herein are a rectifying device and a method of fabricating the same. The rectifying device includes a first electrode formed in a flat shape, an insulating layer deposited on the first electrode and a second electrode formed on a preset region of the insulating layer in a nanaopillar shape in a longitudinal direction to be asymmetrical to the first electrode, thereby increasing current flow.
US09425324B2 Semiconductor device and channel structure thereof
A semiconductor device having a composite structure is disclosed, which includes a channel structure having an inner core strut that extends substantially along a channel direction of the semiconductor device and an outer sleeve layer disposed on the inner core strut. The inner core strut mechanically supports the sleeve member across a channel length of the semiconductor device.
US09425321B2 Thin-film transistor and process for manufacture of the thin-film transistor
A thin-film transistor includes an oxidic semiconductor channel, a metallic or oxidic gate, drain and source contacts and at least one barrier layer positioned between the oxidic semiconductor channel and the drain and source contacts to inhibit an exchange of oxygen between the oxidic semiconductor channel and the drain and source contacts.
US09425317B1 Fin field effect transistor (FinFET) device structure with Ge-doped inter-layer dielectric (ILD) structure
A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending above the substrate. The FinFET device structure includes an isolation structure, and the fin structure is embedded in the isolation structure. The FinFET device structure also includes a gate structure formed on a middle portion of the fin structure. The gate structure has a top portion and bottom portion, and the bottom portion is wider than the top portion. The FinFET device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.
US09425316B2 Source/drain contacts for non-planar transistors
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
US09425314B2 Passivated III-V or Ge fin-shaped field effect transistor
A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.
US09425313B1 Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.
US09425306B2 Super junction trench power MOSFET devices
In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.
US09425301B2 Sidewall passivation for HEMT devices
Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
US09425299B1 Three-dimensional memory device having a heterostructure quantum well channel
A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.
US09425297B2 Semiconductor devices
Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and doped with a p-type dopant, a drain region adjacent to a second side surface of the semiconductor region, a gate electrode on the semiconductor region, a source gate electrode on the source region, and a drain gate electrode on the drain region. The second side surface is a reverse side of the first side surface. The drain region is doped with a p-type dopant.
US09425291B1 Stacked nanosheets by aspect ratio trapping
A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material.
US09425290B2 Formation of high quality fin in 3D structure by way of two-step implantation
The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed.
US09425289B2 Methods of forming alternative channel materials on FinFET semiconductor devices
One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.
US09425288B2 Method of manufacturing semiconductor device
A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
US09425284B2 Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
US09425279B1 Semiconductor device including high-K metal gate having reduced threshold voltage variation
A semiconductor device having a reduced variation in threshold voltage includes a semiconductor substrate with a high dielectric-constant (high-k) layer deposited in a gate trench and on a semiconductor portion of the substrate. At least one workfunction layer has an arrangement of first and second workfunction granular portions on an upper surface of the high-k layer to define a workfunction of the semiconductor device. The arrangement of first and second workfunction granular portions define a granularity of the at least one workfunction layer. A gate contact material fills the gate trench, wherein the high-k layer has a concentration of oxygen vacancies based on the granularity of the at least one work function metal layer so as to reduce the variation in the threshold voltage.
US09425270B2 Array substrate structure and contact structure
A contact structure is provided, including a substrate, an active layer, an inter-layer dielectric (ILD) layer, a contact opening, and a conductive layer. The active layer is disposed over the substrate, and the insulating layer is disposed over the active layer; an inter-layer dielectric (ILD) layer over the insulating layer. The contact opening penetrates a portion of the ILD layer and the insulating layer to expose a portion of the active layer, wherein the contact opening includes a first recess portion, and the first recess portion is defined by a bottom surface of the ILD layer, a sidewall of the insulating layer and a top surface of the active layer. The conductive layer is in the contact opening and is electrically connected to the active layer.
US09425269B1 Replacement emitter for reduced contact resistance
Device structures for a bipolar junction transistor and methods for fabricating such device structures. An emitter structure is formed that has a semiconductor layer with a top surface defining a recess and a sacrificial layer comprised of a disposable material in the recess. A contact opening is formed that extends through one or more first dielectric layers to the sacrificial layer. After the contact opening is formed, the sacrificial layer is removed from the recess. Alternatively, the layer in the recess may be comprised of a non-disposable material that may occupy the recess at the time that a contact is formed in the contact opening.
US09425268B2 Compound semiconductor device and method of manufacturing the same
A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film.
US09425261B2 Silicon-carbide semiconductor device and method for manufacturing the same
A silicon carbide semiconductor device that reduces an influence of an off-angle of a silicon carbide substrate on characteristics of the semiconductor device and achieves improved operational stability and reduced resistance. In a trench-gate silicon carbide MOSFET semiconductor device, a high-concentration well region is formed in a well region, and a distance from a first sidewall surface of a trench of the silicon carbide semiconductor to the high-concentration well region is smaller than a distance from a second sidewall surface of the trench to the high-concentration well region, the second sidewall surface facing the first sidewall surface of the trench through the gate electrode.
US09425260B2 Application of super lattice films on insulator to lateral bipolar transistors
A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.
US09425251B2 Thin film transistor substrate and organic light-emitting diode (OLED) display having the same
A thin film transistor substrate and an organic light-emitting diode (OLED) display are disclosed. In one aspect, the OLED includes a thin film transistor substrate. The thin film transistor substrate includes a substrate, a source electrode formed over the substrate, a drain electrode formed over the substrate and spaced apart from the source electrode, an oxide semiconductor layer, and a gate electrode. The oxide semiconductor layer includes a source area at least partially overlapping the source electrode, a drain area at least partially overlapping the drain electrode, and a channel area formed between the source area and the drain area. The gate electrode, which is insulated from the oxide semiconductor layer, has a first width at a first end thereof, a second width at a second end opposite to the first end thereof and the first width is different from the second width.
US09425250B2 Transistor with wurtzite channel
A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [−2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.
US09425249B2 Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers
A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.
US09425245B2 Array substrate and method for manufacturing the same, display device
Embodiments of the present invention disclose an array substrate comprising a plurality of pixel units disposed on a base substrate, the pixel units comprising: a thin film transistor structure formed on the base substrate; and an OLED driven by the thin film transistor structure, the OLED disposed in a pixel region of the pixel units, the OLED comprising sequentially in a direction away from the base substrate a first electrode which is transparent, a light-emitting layer and a second electrode which reflects light; a transflective layer disposed between the OLED and the thin film transistor structure; a color filter disposed between the second electrode of the OLED and the transflective layer; the second electrode of the OLED and the transflective layer constitute a microcavity structure.
US09425244B2 Display device
A display device is provided including a display region arranged with a plurality of the pixels in a matrix, the plurality of pixels including a light emitting region, a first light shielding layer, and a second light shielding layer, wherein the first light shielding layer includes a plurality of first apertures opening the light emitting region, and a plurality of second apertures opening a non-light emitting region between the plurality of the pixels, and the second light shielding layer is arranged below the first light shielding layer and includes a plurality of third apertures opening the light emitting region, the second light shielding layer being arranged with a light shielding region below the second apertures.
US09425243B2 Organic light emitting display panel
An organic light emitting display panel includes: a pixel defined by an intersection of one of a plurality of data lines and one of a plurality of gate lines, the pixel including: a transistor, a storage capacitor including: a first electrode, and a second electrode, and a semiconductor layer, a first plate partially overlapping the semiconductor layer in the pixel, the first plate including: a gate portion of the transistor, and a capacitor-forming portion including the first electrode of the storage capacitor, and a second plate on the first plate in the pixel, the second plate including the second electrode of the storage capacitor, the second plate not overlapping the semiconductor layer.
US09425235B2 Light emitting device including resin package having differently curved parts
A light emitting device, having: a first light emitting element and a second light emitting element; and a resin package equipped with an opening having a reflective wall that widens toward the upper face, the opening comprises at least first and second curved parts having different radiuses at the resin package upper face, and the radius of the first curved part disposed near the first light emitting element is greater than the radius of the second curved part disposed near the second light emitting element.
US09425228B2 Image sensor with reduced optical path
Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler gird portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler gird portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.
US09425225B2 Solid-state imaging device
Unit pixel cells each includes: a photoelectric conversion film; a transparent electrode; a pixel electrode; an amplification transistor; a reset transistor; and an element isolation STI and a leakage suppression region for electrically isolating the amplification transistor and the reset transistor, the first isolation region being in a silicon substrate, between the amplification transistor and the reset transistor, the reset transistor including: a gate electrode; and a drain region which is connected to the pixel electrode, and is in the silicon substrate, between the gate electrode and element isolation STI and the leakage suppression region, in which a depletion layer formed by a first PN junction between the drain region and its surrounding region and in contact with a surface of the silicon substrate is narrower than a depletion layer formed by a second PN junction between the drain region and its surrounding region and formed in the silicon substrate.
US09425224B2 Light detection device
A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche photodiodes operating in Geiger mode, quenching resistors connected in series to the respective avalanche photodiodes, and signal lines to which the quenching resistors are connected in parallel. A mounting substrate is configured so that a plurality of electrodes corresponding to the respective channels are arranged on a third principal surface side and so that a signal processing unit for processing output signals from the respective channels is arranged on a fourth principal surface side. In a semiconductor substrate, through-hole electrodes electrically connected to the signal lines are formed for the respective channels. The through-hole electrodes and the electrodes are electrically connected through bump electrodes.
US09425223B1 Manufacture method of TFT substrate and sturcture thereof
The present invention provides a manufacture method of a TFT substrate, and the method comprises steps of: 1, deposing a first metal layer (2) on a substrate (1); 2, coating a first photoresistor layer (3) and implementing gray scal exposure; 3, removing a part of the first metal layer (2) to form a gate (21) and a source/a drain (23); 4, implementing ashing process to the first photoresistor layer (3); 5, deposing an isolation layer (4); 6, removing a part of the first photoresistor area (3) and a part of the isolation layer (4); 7, forming an oxide semiconductor layer (5); 8, deposing a protecting layer (6); 9, coating a second photoresistor layer (7) and implementing gray scal exposure; 10, removing a part of the protecting layer (6); 11, implementing ashing process to the second photoresistor layer (7); 12, deposing a transparent conducting thin film (8); 13, removing a part of second photoresistor layer (7) and a part of the transparent conducting thin film (8); 14, forming a pixel definition layer (9); 15, forming photo spacers (10).
US09425222B2 Display device and method of manufacturing the same
A display device includes pixels. At least one of the pixels includes a pixel area, a first non-pixel area disposed adjacent to the pixel area and extending in a first direction, and a second non-pixel area extending in a second direction substantially perpendicular to the first direction. The pixel including a pixel area includes a pixel electrode disposed in the pixel area, a color filter extending in the second direction, and a shielding electrode extending in the second direction and disposed on the color filter in the second non-pixel area. A capping layer is disposed on the color filter. The capping layer covers the shielding electrode in an area except for a crossing area where the first and second non-pixel areas cross each other. A black matrix is disposed on the capping layer and the shielding electrode in the first non-pixel area.
US09425221B2 Circuit-on-wire
A circuit-on-wire (CoW) is provided that is made from a flexible metal wire with an outer surface, and a plurality of discrete electrical control devices formed in series along the metal wire outer surface. Each control device may have an electrical contact accessible through the metal wire. In one aspect, the control device may have a via through the metal wire from the top surface to the bottom surface with a second electrical contact accessible through the via. In addition, the control devices may have a top surface with an accessible third electrical contact. For example, the control device may be a first thin-film transistor (TFT), with a gate electrode accessible through the metal wire, wherein the second electrical contact is a first source/drain (S/D) electrode, and wherein the third electrical contact is a second S/D electrode. Using the above-described CoW, a woven active matrix array can be fabricated.
US09425214B2 Thin film transistor substrate, method of manufacturing the same, and organic light emitting diode display using the same
A thin film transistor substrate includes: a polymer substrate, an oxide transparent electrode layer (TCO) formed on the polymer substrate, a barrier layer formed on the oxide transparent electrode layer, and a semiconductor layer formed on the barrier layer, in which the semiconductor layer is polysilicon. The polysilicon thin film transistor provides an oxide transparent electrode layer (TCO) which absorbs heat energy and light generated during a process of manufacturing the polysilicon thin film transistor to prevent a damage of the substrate using a polymer material.
US09425211B2 Semiconductor memory device and method for manufacturing same
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
US09425209B1 Multilayer 3-D structure with mirror image landing regions
An integrated circuit includes blocks and global lines overlying the blocks. The blocks include a plurality of levels including two dimensional arrays of memory cells having horizontal lines and being intersected by vertical lines coupled to corresponding memory cells. Levels include contact pads communicating with horizontal lines for a given block. The global lines include connectors. Connectors coupled to given global lines are coupled to landing areas on corresponding contact pads of the blocks. The blocks include first and second blocks disposed so that a first set of the contact pads associated with the first block are next to a second set of contact pads associated with the second block. The landing areas of the contact pads of the first and second blocks are mirror image surfaces of one another. The horizontal lines can be bit lines and the vertical lines can be word lines.
US09425206B2 Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology
The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.
US09425205B2 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and a charge storage film. The stacked body includes a plurality of electrode layers crosswise extending in a first direction and second direction crossing the first direction, the plurality of electrode layers separately stacked each other in a third direction crossing the first direction and second direction. The semiconductor body extends in the third direction and provided in the stacked body. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.
US09425195B2 Static discharge system
A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.
US09425194B2 Transistor devices with high-k insulation layers
An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.
US09425193B2 Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material
A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.
US09425191B2 Memory device and manufacturing method of the same
A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.
US09425187B1 Apparatus and methods for modulating current / voltage response using multiple semi-conductive channel regions (SCR) produced from different integrated semiconductor structures
Apparatuses and methods for modulating current/voltage response using multiple semi-conductive channel regions (SCR) produced from different integrated semiconductor structures are provided. In particular, embodiments include systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using combined integrated functions of a lateral double-diffused metal-oxide semiconductor field effect transistor (LDMOSFET) and junction field effect transistor (JFET) disposed in proximity of a LDMOSFET's SCR within a certain orientation forming a second SCR.
US09425186B2 Electrostatic discharge protection circuit
The present invention discloses an electrostatic discharge protection circuit, comprising a diode and a N-type metal-oxide-semiconductor (NMOS) transistor. The diode locating on a N-well comprises an high P-doping concentration region and an nonadjacent high N-doping concentration region. The NMOS transistor, locating on a P-well, comprises a drain, a source and a gate, and the drain and the source are formed by the high N-doping concentration region. Wherein the P-well further comprises a high P-doping concentration region near the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, the gate of the NMOS transistor electrically connected to a trigger point. Accordingly, the electrostatic discharge protection circuit has a low parasitic capacitance, wide operating voltage range and high electrostatic discharge (ESD) capability for resolving the problems about the ESD of the RX pins.
US09425184B2 Electrostatic discharge devices and methods of manufacture
Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.
US09425183B2 Active guard ring structure to improve latch-up immunity
An active guard ring structure is provided, which is applicable to improving latch-up immunity during the latch-up current test (I-test). The proposed active guard ring structure comprises an I/O circuit and an active protection circuit, wherein the I/O circuit receives a trigger current via an input pad and generates a corresponding bulk current since being triggered. The active protection circuit, connected between the I/O circuit and a core circuit, detects whether the trigger current is a positive or negative current pulse. When an intensity of the trigger current is larger than a threshold value, the active protection circuit controls the I/O circuit to provide a sink or compensation current so as to neutralize the bulk current and to reduce the net current flowing into or sourced from the core circuit, thereby increasing the latch-up resistance and immunity of the core circuit.
US09425176B2 Cascode transistor device and manufacturing method thereof
A semiconductor device comprises a substrate, a patterned conductive layer, a first transistor structure and a second transistor structure. The patterned conductive layer is formed on the substrate. The first transistor structure includes a first source, a first gate and a first drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The second transistor structure includes a second source, a second gate and a second drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The first gate is electrically connected to the second source through the patterned conductive layer, and the first source is electrically connected to the second drain through the patterned conductive layer.
US09425174B1 Integrated circuit package with solderless interconnection structure
An integrated circuit package may include an integrated circuit die and a package substrate having a conductive pad. A conductive pillar is formed on a front surface of the integrated circuit die and directly contacts the conductive pad. Prior to contacting the conductive pad directly, the conductive pillar may be positioned adjacent to the conductive pad such that it is aligned to the conductive pad. The integrated circuit package further includes an interconnect structure that is formed in the package substrate. The interconnect structure may include conductive traces that are electrically connected to the conductive pad and the conductive pillar. An additional integrated circuit die may be mounted on the package substrate. The additional integrated circuit die may couple to the integrated circuit die through the interconnect structure.
US09425172B2 Light emitter array
Lamps, luminaries or solid state lighting components are disclosed having multiple discrete light sources whose light combines to provide the desired emission characteristics. The discrete light sources are arranged in an array pursuant to certain guidelines to promote mixing of light from light sources emitting different colors of light. One embodiment solid state lighting component comprises a light emitting diode (LED) component having an array of LED chips having a first group of LED chips and one or more additional groups of LED chips. The array is arranged so that no two LED chips from said first group are directly next to one another in the array, that less than fifty percent (50%) of the LED chips in the first group of LEDs is on the perimeter of the array, and at least three LED chips from the one or more additional groups is adjacent each of the LED chips in the first group.
US09425171B1 Removable substrate for controlling warpage of an integrated circuit package
One embodiment of the present invention sets forth a technique for packaging an integrated circuit die. The technique includes bonding a first surface of the integrated circuit die to a first substrate via a first plurality of solder bump structures and bonding a second substrate to a second surface of the integrated circuit die. The technique further includes bonding the first substrate to a third substrate via a second plurality of solder bump structures and, after bonding the first substrate to the third substrate, removing the second substrate from the second surface of the integrated circuit die. The technique further includes disposing a heat sink on the second surface of the integrated circuit die.
US09425169B2 Flexible stack packages having wing portions
A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the flexible layer, and a contact portion disposed on the chip to penetrate the flexible layer and exposed at a surface of the flexible layer. Each of the first and second packages includes a fixing portion and a wing portion. A first adhesion part is disposed between the fixing portion of the first package and the fixing portion of the second package to combine the first package with the second package. A first stretchable interconnector electrically connects or couples the contact portion of the first package to the contact portion of the second package.
US09425166B2 GOA layout method, array substrate and display device
A GOA layout method, an array substrate and a display device are provided. The array substrate includes a plurality of GOA unit groups, each of which includes two adjacent GOA units. The plurality of GOA unit groups includes a first GOA unit group, two GOA units of the first GOA unit group have an overlapping region with at least one via hole provided therein, and the two GOA units of the first GOA unit group are electrically connected through the at least one via hole. With the array substrate, the density of gate lines can be increased.
US09425164B1 Low alpha tin
A non alpha controlled Tin including Tin and a trace amount of Polonium may be converted to a low alpha emission Tin by concentrating and removing at least some of the Polonium. The non alpha controlled Tin may be a raw material or a solder bump upon a semiconductor wafer, chip, or carrier. The Polonium may be concentrated by oxidizing an exterior portion of the non alpha controlled Tin. If the non alpha controlled Tin is a raw material, the oxidized exterior portion of the non alpha controlled Tin may be stripped. If the non alpha controlled Tin is a solder bump, the oxidized exterior portion of the solder bump may be removed by applying flux to the solder bump, reflowing the solder bump to dissolve the oxidized exterior portion and the concentrated Po into the flux, and cleaning the flux from the solder bump.
US09425163B2 Systems and methods for determining and adjusting a level of parallelism related to bonding of semiconductor elements
A bonding machine for bonding semiconductor elements, the bonding machine including: a support structure configured to support a substrate; a bond head assembly, the bond head assembly including a bonding tool configured to bond a plurality of semiconductor elements to the substrate; and a calibration tool including a contact portion configured to be positioned between the bonding tool and the support structure, the contact portion configured to be contacted by each of the bonding tool and the support structure simultaneously during a calibration operation.
US09425159B2 Wiring board and method for manufacturing the same
A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.
US09425158B2 Rigid-flex module and manufacturing method
Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane (20) and a sacrificial-material piece (16) are attached to an insulator membrane (12) in the location of the flexible zone (13). An insulator layer (1), which encloses within itself a sacrificial-material piece (16) is manufactured on the surface of the conductor membrane (12). The flexible zone (13) is formed in such a way that an opening (9) is made in the insulator layer (1), through which the sacrificial-material piece (16) is removed. The flexible zone comprises at least part of the flexible membrane (20) as well as conductors (22), which are manufactured by patterning the insulator membrane (12) at a suitable stage in the method.
US09425157B2 Substrate and package structure
According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
US09425155B2 Wafer bonding process and structure
A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
US09425146B2 Semiconductor structure and method for making same
One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.
US09425145B2 Oversized contacts and vias in layout defined by linearly constrained topology
A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.
US09425140B2 Capacitors in integrated circuits and methods of fabrication thereof
In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.
US09425138B2 Semiconductor device having through-electrode
A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the semiconductor substrate through an insulating film, a via, passing through the semiconductor substrate from a rear surface thereof up to the front surface to reach the surface electrode, having a wall including a flange portion inwardly projecting on a front surface portion of the semiconductor substrate, a via insulating film formed on the wall of the via, and a through-electrode embedded inside the via insulating film and electrically connected to the surface electrode, while the via insulating film has portions having different thickness compensating for a step between the flange portion and the remaining portion of the wall, to planarize a contact surface with the through-electrode.
US09425133B2 Integrated circuits and methods of forming conductive lines and conductive pads therefor
An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed.
US09425131B2 Package structure
A package structure includes an insulation layer, a first conductive layer, a second conductive layer, at least one electronic component, and at least one thermal conduction structure. At least one first conductive via and at least one second conductive via are formed in the insulation layer. The first conductive layer is disposed on a top surface of the insulation layer and contacted with said at least one first conductive via. The second conductive layer is disposed on a bottom surface of the insulation layer and contacted with the second conductive via. The electronic component is embedded within the insulation layer, and includes plural conducting terminals. The plural conducting terminal is electrically connected with the first conductive layer and the second conductive layer through said at least one first conductive via and said at least one second conductive via. Said at least one thermal conduction structure is embedded within the insulation layer.
US09425129B1 Methods for fabricating conductive vias of circuit structures
Methods and structures for fabricating conductive vias in circuit structures are provided. Methods may include, for example, providing a substrate that includes a dopant and at least one trench formed in the substrate; providing an undoped semiconductor layer over a surface of the substrate within the trench; and providing a conductive material on top of dielectric layer in the trench, the conductive material forming the conductive via. The undoped semiconductor layer, having no dopant, reduces a parasitic capacitance between the conductive via and the substrate. The undoped semiconductor layer may also prevent migration of dopant from the substrate into the undoped semiconductor layer, further reducing capacitance in the circuit structure.
US09425122B2 Electronic component package and method for manufacturing the same
A method for manufacturing an electronic component packages is provided, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. A combination of a formation process of a plurality of metal plating layers and a patterning process of the plurality of metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, and the patterning process being performed by a patterning of at least two of the plurality of metal plating layers.
US09425120B2 Semiconductor device and production method therefor
A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a wiring circuit substrate or a semiconductor device in which connection portions of a plurality of semiconductor chips are electrically connected to each other, the method comprising a step of sealing at least part of the connection portions with an adhesive for a semiconductor comprising a compound having a group represented by the following formula (1): wherein R1 represents an electron-donating group.
US09425119B2 Package structure and fabrication method thereof
A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.
US09425110B1 Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems
A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.
US09425109B2 Planarization method, method for polishing wafer, and CMP system
A planarization method is provided. The planarization method includes providing a wafer, in which the wafer includes a work function layer, a surface layer formed on the work function layer and oxidized from the work function layer, and a planarization layer disposed on or above the surface layer, performing a chemical-mechanical planarization (CMP) process on the planarization layer, providing an incident light to a surface of the wafer under the CMP process, detecting absorption of the incident light by the surface layer; and stopping the CMP process in response to an increase in the detected absorption of the incident light.
US09425108B1 Method to prevent lateral epitaxial growth in semiconductor devices
A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.
US09425103B2 Methods of using a metal protection layer to form replacement gate structures for semiconductor devices
A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.
US09425101B2 FinFET fabrication method using buffer layers between channel and semiconductor substrate
FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions.
US09425096B2 Air gap between tungsten metal lines for interconnects with reduced RC delay
Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.
US09425095B2 Distributed metal routing
A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
US09425094B2 Mechanisms for forming semiconductor device structure with feature opening
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a hard mask layer over the dielectric layer. The method also includes performing a plasma etching process to etch the hard mask layer to form an opening, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The gas mixture has a volumetric concentration of the nitrogen-containing gas in a range from about 20% to about 30%. A volumetric concentration ratio of the carbon-containing gas to the halogen-containing gas in the gas mixture is equal to about 0.3. The method further includes etching the dielectric layer through the opening in the hard mask layer to form a feature opening in the dielectric layer. The method includes forming a conductive material in the feature opening.
US09425092B2 Methods for producing interconnects in semiconductor devices
A method for producing interconnects on a workpiece includes obtaining a workpiece substrate having a feature, depositing a conductive layer in the feature, to partially or fully fill the feature, depositing a copper fill to completely fill the feature if the feature is partially filled by the conductive layer, applying a copper overburden, thermally treating the workpiece, and removing the overburden to expose the substrate and the metalized feature.
US09425086B2 Method of controlling contact hole profile for metal fill-in
A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.
US09425083B2 Handle substrate, composite substrate for semiconductor, and semiconductor circuit board and method for manufacturing the same
It is provided a handle substrate of a composite substrate for a semiconductor. The handle substrate is composed of a translucent polycrystalline alumina. A purity of alumina of the translucent polycrystalline alumina is 99.9% or higher, an average of a total forward light transmittance of the translucent polycrystalline alumina is 60% or higher in a wavelength range of 200 to 400 nm, and an average of a linear light transmittance of the translucent polycrystalline alumina is 15% or lower in a wavelength range of 200 to 400 nm.
US09425077B2 Semiconductor apparatus with transportable edge ring for substrate transport
An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.
US09425075B2 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
The present disclosure suppresses oxidation of a base film on a substrate surface during the formation of an oxide film. A method of manufacturing a semiconductor device according to the present disclosure includes forming an initial layer including a predetermined element and having a thickness of several atomic layers on a substrate in a process chamber by supplying a predetermined-element-containing gas to the substrate, and forming an oxide film including the predetermined element on the initial layer by performing a cycle a predetermined number of times, the cycle including supplying a precursor gas including the predetermined element to the substrate in the process chamber and supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in the process chamber under a pressure lower than an atmospheric pressure.
US09425066B2 Circuit substrate
A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.
US09425056B2 Method for producing silicon wafer
The present invention provides a method for producing a silicon wafer including a step of, after growing the oxide film on one surface of a raw material silicon wafer by chemical-vapor deposition, performing double-side polishing of the raw material silicon wafer in such a manner that a suede polishing pad or a velour polishing pad with an asker-C rubber hardness of 50° or more but less than 90° is used for the oxide-film surface.
US09425051B2 Method for producing a silicon-germanium film with variable germanium content
The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas.
US09425047B1 Self-aligned process using variable-fluidity material
A method of forming a wide line includes forming a portion of variable-fluidity material between opposing inner walls of a pair of adjacent line portions, the portion of variable-fluidity material patterned to have a lateral dimension that is smaller than a distance between the opposing inner walls of the pair of adjacent line portions, and subsequently applying process conditions that increase the fluidity of the portion of variable-fluidity material sufficiently to cause the portion of variable-fluidity material to extend to the opposing inner walls of the pair of adjacent line portions.
US09425045B2 Semiconductor device including oxide semiconductor and manufacturing method thereof
It is an object to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. An oxide semiconductor film serving as a channel formation region of a transistor is formed by a sputtering method at a temperature higher than 200° C., so that the number of water molecules eliminated from the oxide semiconductor film can be 0.5/nm3 or less according to thermal desorption spectroscopy. A substance including a hydrogen atom such as hydrogen, water, a hydroxyl group, or hydride which causes variation in the electric characteristics of a transistor including an oxide semiconductor is prevented from entering the oxide semiconductor film, whereby the oxide semiconductor film can be highly purified and made to be an electrically i-type (intrinsic) semiconductor.
US09425041B2 Isotropic atomic layer etch for silicon oxides using no activation
Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO activation of an oxide surface. Once activated, a fluorine-containing gas or vapor etches the activated surface. Etching is self-limiting as once the activated surface is removed, etching stops since the fluorine species does not spontaneously react with the un-activated oxide surface. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.
US09425040B2 Method of forming laminated film and forming apparatus thereof
A method of forming a laminated film includes forming a silicon oxide film on a plurality of target objects loaded in a reaction chamber, and forming a silicon oxynitride film on the plurality of target objects by supplying a silicon source, an oxidizing agent and a nitride agent to the reaction chamber, wherein forming the silicon oxide film and forming the silicon oxynitride film are repeatedly performed for a predetermined number of times on the plurality of target objects to form a laminated film including the silicon oxynitride film and the silicon oxide film.
US09425038B2 Method and apparatus for forming silicon oxycarbonitride film, silicon oxycarbide film and silicon oxynitride film
A method for forming a silicon oxycarbonitride film includes supplying a gas containing a silicon precursor having an oxygen-containing group onto a process surface of a workpiece, supplying a gas containing a carbon precursor onto the process surface, and supplying a nitriding gas onto the process surface subjected to the supplying a gas containing a silicon precursor and the supplying a gas containing a carbon precursor. The silicon oxycarbonitride film is formed on the process surface by the supplying the gas containing the silicon precursor, the supplying gas containing the carbon precursor and the supplying a nitriding gas without performing an oxidation process.
US09425035B2 Ion trap with spatially extended ion trapping region
A mass or mass to charge ratio selective ion trap is disclosed which directs ions into a small ejection region. A RF voltage acts to confine ions in a first (y) direction within the ion trap. A DC or RF voltage acts to confine ions in a second (x) direction. A quadratic DC potential well acts to confine ions in a third (z) direction within the ion trap. The profile of the quadratic DC potential well progressively varies along the second (x) direction.
US09425033B2 Ion injection device for a time-of-flight mass spectrometer
The invention provides methods and devices to pulse ions from an RF ion storage into the flight tube of a time-of-flight mass spectrometer. The pusher cell comprises essentially two parallel plates, both plates completely slotted into two electrically insulated halves. The four half plates can be supplied with RF voltages to form a two-dimensional quadrupole field in the center between the slits, or with DC voltages to form a homogeneous acceleration field to eject ions. The RF quadrupole field is not ideal, but sufficiently good to store ions, to damp the ions by an additional collision gas, and to form a fine thread of ions in the axis of the quadrupole field. The DC acceleration field is extremely homogeneous; slight distortions near the slits can be corrected by external electrodes. The ideal acceleration field results in a high mass resolution and the device does not show any mass discrimination.
US09425028B2 Plasma processing apparatus
A plasma processing apparatus includes an upper electrode arranged at a processing chamber and including a plurality of gas supplying zones, a branch pipe including a plurality of branch parts, an addition pipe connected to at least one of the branch parts, and a plurality of gas pipes that connect the branch parts to the gas supplying zones. The upper electrode supplies a processing gas including a main gas to the processing chamber via the gas supplying zones. The branch pipe divides the processing gas according to a predetermined flow rate ratio and supplies the divided processing gas to the gas supplying zones. The addition pipe adds an adjustment gas. A gas flow path of the gas pipe connected to the branch part to which the addition pipe is connected includes a bending portion for preventing a gas concentration variation according to an adjustment gas-to-main gas molecular weight ratio.
US09425026B2 Systems and methods for improved radio frequency matching networks
Systems and methods are provided for matching the impedance of a load to an impedance of a power generator. Embodiments include a matching network with a dynamically configurable component assembly array couplable to the variable impedance load and the RF power generator, wherein the component assembly array includes one or more tune and load electrical components. The component assembly array is adapted to be configured for each recipe step, and at least one of the electrical components is a variable impedance component adjustable to reduce RF energy reflected from the variable impedance load for each recipe step. Numerous other aspects are provided.
US09425025B2 Mixed mode pulsing etching in plasma processing systems
A method for processing substrate in a chamber, which has at least one plasma generating source, a reactive gas source for providing reactive gas into the interior region of the chamber, and a non-reactive gas source for providing non-reactive gas into the interior region, is provided. The method includes performing a mixed-mode pulsing (MMP) preparation phase, including flowing reactive gas into the interior region and forming a first plasma to process the substrate that is disposed on a work piece holder. The method further includes performing a MMP reactive phase, including flowing at least non-reactive gas into the interior region, and forming a second plasma to process the substrate, the second plasma is formed with a reactive gas flow during the MMP reactive phase that is less than a reactive gas flow during the MMP preparation phase. Perform the method steps a plurality of times.
US09425021B2 X-ray generation apparatus and X-ray radiographic apparatus
In an X-ray generation apparatus of transmission type including an electron emission source, and a target generating an X-ray with collision of electrons emitted from the electron emission source against the target, the X-ray generation apparatus further includes a secondary X-ray generation portion generating an X-ray with collision of electrons reflected by the target against the secondary X-ray generation portion, and the secondary X-ray generation portion and the target are arranged such that the X-ray generated with the direct collision of the electrons against the target and the X-ray generated with the collision of the electrons reflected by the target against the secondary X-ray generation portion are both radiated to an outside. X-ray generation efficiency is increased by effectively utilizing the electrons reflected by the target.
US09425020B2 Miniaturized all-metal slow-wave structure
A miniaturized all-metal slow-wave structure includes: a circular metal waveguide; and metal electric resonance units provided in the circular metal waveguide; wherein the metal electric resonance unit provided in the circular metal waveguide includes a ring-shaped electric resonance metal plate with an electron beam tunnel provided on a center thereof, and a ring plate body of the ring-shaped electric resonance metal plate has two auricle-shaped through-holes symmetrically aside an axial-section; a main body of the auricle-shaped through-hole is a ring-shaped hole, two column holes extending towards a center of a circle are provided at two ends of the ring-shaped hole; the ring-shaped electric resonance metal plates are perpendicular to an axis and are provided inside the circular metal waveguide with equal intervals therebetween, external surfaces of the ring-shaped electric resonance metal plates are mounted on an internal surface of the circular metal waveguide.
US09425017B2 Method of manufacturing a complex fusible link
A manufacturing method of a complex type fusible link. The manufacturing method includes hollowing out a metal plate into a link-like conductor including a connecting plate and a terminal, cutting out the link-like conductor so as to separate the connecting plate and the terminal, forming, by insert molding, a block base including a cavity after setting the connecting plate and the terminal in a mold, and directly connecting a fusible element to an exposed portion of the connecting plate and an exposed portion of the terminal.
US09425008B1 Contactless switch with shielded vane
A switch includes a switch housing, a button, a circuit board having at least one magnet sensor, and a magnet holder, including at least one magnet, movably mounted to the housing to move responsive to an actuation of the button. A vane interrupter in the switch includes a passage structure positioned proximate to each magnet sensor such that a respective magnet is movable at least partially within a passage defined by the passage structure, and a flange structure having a first flange and a second flange positioned on opposing ends of the passage structure, with the first flange positioned adjacent a portion of the magnet holder holding the magnet and with the second flange positioned adjacent a surface of the circuit board opposite a surface on which the at least one magnet sensor is positioned, such that the circuit board is positioned between the magnet holder and the second flange.
US09424999B2 Dye for photoelectric conversion device and photoelectric conversion device
A photoelectric conversion device that includes a work electrode, an opposed electrode, and an electrolyte-containing layer. In the work electrode, a metal oxide semiconductor layer supporting a dye is provided. The dye contains a cyanine compound that has a methine chain, an indolenine skeleton bonded with both ends of the methine chain, and anchor groups introduced to a nitrogen atom included in the indolenine skeleton. Electron injection efficiency to the metal oxide semiconductor layer is improved, and the dye is hardly exfoliated from the metal oxide semiconductor layer.
US09424993B2 Systems and methods for a thin film capacitor having a composite high-K thin film stack
Systems and methods are provided for fabricating a thin film capacitor involving depositing an electrode layer of conductive material on top of a substrate material, depositing a first layer of ferroelectric material on top of the substrate material using a metal organic deposition or chemical solution deposition process, depositing a second layer of ferroelectric material on top of the first layer using a high temperature sputter process and depositing a metal interconnect layer to provide electric connections to layers of the capacitor.
US09424988B2 Common mode filter and method of manufacturing the same
The present invention relates to a common mode filter and a method of manufacturing the same. In order to implement a common mode filter with low shrinkage, high substrate sintered density, and high strength, the present invention provides a common mode filter including: a lower substrate; an insulating layer having a conductor pattern inside and provided on the lower substrate; an upper substrate provided on the insulating layer; and a ferrite core made of ferrite and provided in the center of the insulating layer, the lower substrate, and the upper substrate by penetrating the insulating layer, the lower substrate, and the upper substrate, and a method of manufacturing the same.
US09424987B2 Three-phase/two-phase rotary transformer including a scott connection
A three-phase/two-phase rotary transformer, includes a first single-phase rotary transformer and a second single-phase rotary transformer, the first transformer including a first body defining a first slot, a first coil in the first slot, a second body defining a second slot, and a second coil in the second slot, the second transformer including a third body defining a third slot, a third coil in the third slot, a fourth body defining a fourth slot, and a fourth coil in the fourth slot, wherein one terminal of the first coil is connected to the midpoint of the third coil, the first body, the first coil, the third body, and the third coil forming a three-phase portion of the transformer, the second body, the second coil, the fourth body, and said fourth coil forming a two-phase portion of the transformer.
US09424986B2 Multi-function wireless power induction mousepad
A multi-function wireless power induction mousepad is composed of a lower soft pad, a foam pad and an upper soft pad, which is flexible and can be rolled for storage. A power module is embedded on the foam pad. The power module includes a power induction coil and a USB socket. The power module supplies power to a mouse having a charging induction coil or a cell phone to be charged. The present invention can cooperate with other peripheral devices, such as a display, a touch-control panel, an LED panel, a writing panel, electronic paper, electronic message board and the like, according to the demand of the user, providing a multi-function effect.
US09424981B2 Inductor element
A multilayer body 12 includes nonmagnetic sheets SH1a and SH1b each having an upper surface provided with a plurality of linear conductors 16, a magnetic sheet SH3 having an upper surface provided with a plurality of linear conductors 18a, and a nonmagnetic sheet SH4 having an upper surface provided with a plurality of linear conductors 18b, which are stacked one on top of another. Via-hole conductors or side-surface conductors are disposed with the multilayer body 12 so as to connect these linear conductors to one another and form an inductor. The plurality of linear conductors have a pattern that is common among at least two sheets adjacent to each other in a stacking direction.
US09424980B2 Electronic component and method of producing same
A laminate in which plural insulator layers are stacked includes an external electrode that is exposed to the exterior of the laminate and includes a plurality of conductive layers stacked in a staking direction and passing through some of the plural insulator layers in the stacking direction. At least one side of the external electrode facing in the stacking direction is overlaid with rest of the plural insulator layers. At least one side surface of the external electrode facing in the stacking direction is uneven with another portion of the side surface.
US09424972B2 Solenoid with variable reluctance plunger
A solenoid for a vehicle starter includes at least one coil with a passage extending through the coil in an axial direction. The solenoid further includes a plunger configured to move in the axial direction within the passage. The plunger includes a cylindrical outer surface with a substantially uniform diameter and a circumferential notch. The cylindrical outer surface includes a first portion with a first diameter on one side of the circumferential notch, and a second portion with the first diameter on an opposite side of the circumferential notch. The circumferential notch includes a portion with a second diameter that is less than the first diameter.
US09424970B2 High-k transformers extending into multiple dielectric layers
A device includes a first plurality of dielectric layers over a substrate and a second plurality of dielectric layers over the first plurality of dielectric layers. A metal inductor includes a first metal portion, a second metal portion, a third metal portion, and a fourth metal portion, wherein each of the first, the second, the third, and the fourth metal portions extends into the first and the second plurality of dielectric layers. A first metal bridge connects the first metal portion to the second metal portion, wherein the first metal bridge extends into the first plurality of dielectric layers and not into the second plurality of dielectric layers. A second metal bridge connects the third metal portion to the fourth metal portion, wherein the second metal bridge extends into the second plurality of dielectric layers and not into the first plurality of dielectric layers.
US09424966B2 Method for forming electrical connection structure part, method for producing aluminum wire with terminal, electrical connection structure part, motor provided with electrical connection structure part, and electrical device provided with motor provided with electrical connection structure part, aluminum wire with terminal, motor provided with aluminum wire with terminal, and electrical device provided with motor provided with aluminum wire with terminal
A method for forming an electrical connection structure part according to the present invention includes a step of covering, with an alloy body, a connection part between a first conductor part and a second conductor part, so as to form the electrical connection structure part. The first conductor part contains aluminum. The second conductor part has a surface covered with an ingredient containing nickel. The alloy body contains tin, silver, and nickel. The method further includes steps of: connecting the first conductor part and the second conductor part to each other to form the connection part; melting the alloy body; and dipping at least the connection part into the molten alloy body.
US09424962B2 Flexible electrical cable with resistance to external chemical agents
A flexible electrical cable that is resistant to external chemical agents includes a sheathing assembly and a core assembly. From interior to exterior, the core assembly has at least two conductors and a two-part filler material with an inner portion and an outer portion. The inner portion has discrete, non-continuous elements, and the outer portion is a solid, continuous material surrounding the inner portion and at least partially embedding the at least two conductors. The outer portion has a circular cross-section. The sheathing assembly has a foamed polymeric material formed around and shaped by the outer portion of the filler material, a metal tape positioned around and shaped by the foamed polymeric material, a polymeric coating surrounding the metal tape, and an outer sheath.
US09424961B2 Insulated wire, and electric/electronic equipments, motor and transformer using the same
An insulated wire having a rectangular shaped cross-section, containing: a conductor having a rectangular shaped cross-section; and an insulating layer coated on the conductor, in which the insulating layer has a foamed layer composed of a thermosetting resin containing bubbles, the cross-section of the insulating layer has a shape composed of a flat portion and a corner portion, and the insulating layer satisfies the relationship represented by the following formula: ∈1<3 and (T2/∈2)>(T1/∈1) wherein T1 [μm] represents a thickness of the flat portion; ∈1 represents a relative dielectric constant of the flat portion; T2 [μm] represents a thickness of the corner portion; and ∈2 represents a relative dielectric constant of the corner portion, and an electric/electronic equipment, a motor, or a transformer, using the insulated wire.
US09424956B2 Submerged or underwater electricity production module
This underwater electricity production module includes an elongated cylindrical box, which includes a reactor compartment and an electricity production unit. The reactor compartment includes a reservoir chamber and a dry chamber. A nuclear reactor is located in the dry chamber. The reservoir chamber forms a safety water storage reservoir. At least a radial wall of the reservoir chamber is in a direct heat exchange relationship with a marine environment that surrounds the cylindrical box. The nuclear reactor includes a nuclear boiler which includes a pressurizer connected through a depressurizing valve to the reservoir chamber.
US09424954B2 Semiconductor package including stacked chips and method of fabricating the same
A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.
US09424952B1 Circuits, methods, and media for detecting and countering aging degradation in memory cells
Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.
US09424941B2 Semiconductor memory device with sense amplifyer groups and method of operation the same
A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.
US09424940B1 Nonvolatile memory device and method of erasing the same
A nonvolatile memory device includes a substrate, a plurality of memory cells stacked in a direction perpendicular to the substrate, word lines connected to the memory cells, a ground select transistor between the memory cells and the substrate, a ground select transistor between the memory cells and the substrate, a ground select line connected to the ground select transistor, a bit line on the memory cells, and a string select transistor between the memory cells and the bit line. In an erase operation, the ground select line is floated at a time when a specific time passes after the erase voltage is provided to the substrate. And the ground select line is floated at different times depending on a temperature.
US09424937B2 Method for programming a flash memory
A method of programming a flash memory is described. The method includes partitioning a flash memory into a first group having a first level of write-protection, a second group having a second level of write-protection, and a third group having a third level of write-protection. The write-protection of the second and third groups is disabled using an installation adapter. The third group is programmed using a Software Installation Device.
US09424936B1 Current leakage reduction in 3D NAND memory
Embodiments of the present disclosure are directed towards techniques and configurations for providing an apparatus comprising a memory array, to which bias voltage may be provided to reduce leakage current. In one embodiment, the apparatus may comprise a three-dimensional (3D) memory array having at least first and second blocks; and circuitry coupled with the 3D memory array to access the 3D memory array. The circuitry may include circuit to deselect the first block and select the second block, and supply a first bias voltage to the deselected first block and a second bias voltage to the selected second block, to reduce leakage current in the 3D memory array. The first bias voltage may be different than the second bias voltage. Other embodiments may be described and/or claimed.
US09424932B2 Nonvolatile memory device and programming method thereof
A programming method is for programming a nonvolatile memory device including a plurality of strings disposed perpendicular to a substrate and connected between bitlines and a common source line. The programming method includes setting up the common source line to a predetermined voltage, floating the setup common source line, performing a program operation on memory cells connected to a selected wordline, and performing a verify operation on the memory cells.
US09424930B2 Apparatus, system, and method for non-volatile storage element programming
Methods, storage controllers, and systems for non-volatile storage element programming are described. One method includes programming user data in pages associated with a set of wordlines of an erase block of a non-volatile, solid-state storage element. The method further includes selecting at least one of the wordlines of the set programmed with the user data and restricting further programming of user data in the pages associated with the selected wordline. In some embodiments, the selected wordline occurs subsequent to the pages associated with the other wordlines of the set in a page programming order for the erase block.
US09424928B2 Nonvolatile memory device including multi-plane
A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.
US09424925B2 Memory cell
The invention relates, inter alia, to a memory cell (10) comprising at least one binary memory area for storing bit information.According to the invention it is provided that the memory area (SB) can optionally store holes or electrons and allows a recombination of holes and electrons, the charge carrier type of the charge carriers stored in the memory area defines the bit information of the memory area, and a charge carrier injection device (PN) is present, by means of which optionally holes or electrons can be injected into the memory area (SB) and the bit information can thus be changed.
US09424923B2 Semiconductor storage device
A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.
US09424922B2 Semiconductor memory device, operating method thereof, and data storage device including the same
A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control logic suitable for loading the setting information stored in the setting information area on a content-addressable memory (CAM) block, a CAM state information storage block suitable for storing information on whether the setting information loaded on the CAM block is changed, wherein when a reloading operation of the setting information stored in the setting information area on the CAM block is requested, the control logic selectively performs the reloading operation based on the information stored in the CAM state information storage block.
US09424919B2 Semiconductor storage device
According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.
US09424918B2 Ionic storage unit and driving method
There is provided a storage unit including: a storage device configured to store a resistance state, the resistance state being changeable between a first state and a second state; and a driving section, when setting the resistance state to the first state, applying a first pulse having a first polarity to the storage device, the driving section, when setting the resistance state to the second state, applying a second pulse having a second polarity to the storage device, then temporarily applying a third pulse having the first polarity, and applying the second pulse again, the first polarity and the second polarity differing from each other.
US09424914B2 Resistive memory apparatus and memory cell thereof
A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.
US09424909B1 Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation
Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.
US09424904B2 Magnetic memory devices including oxide multiferroic material
A magnetic memory device is provided. The magnetic memory device includes a plurality of variable resistance devices connected to a word line, and a plurality of bit lines, each of which provides an electrical pathway between a corresponding one of the variable resistance devices and a read and write circuit. Each of the variable resistance devices includes a free layer and a pinned layer spaced apart from each other and having a tunnel barrier interposed therebetween, an assistant layer spaced apart from the tunnel barrier and having the free layer interposed therebetween, and an exchange coupling layer arranged between the free layer and the assistant layer. The exchange coupling layer has an electric polarization, which results from its ferroelectric property, and having a direction that can be changed by a voltage applied to the corresponding one of the bit lines.
US09424902B2 Memory controller and associated method for generating memory address
A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.
US09424901B1 Semiconductor memory device outputting status signal and operating method thereof
An operating method of a semiconductor memory device may include receiving a command, outputting a status signal as a busy status while accessing a selected area of the memory cell array in response to the command, changing the status signal from the busy status to a ready status and outputting the status signal after the access is completed, and applying a dummy pulse to an unselected area of the memory cell array in response to the status signal being output as the ready status.
US09424900B2 Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (TBL) and/or a clock signal (e.g., GCLKB)) transitions from one voltage level to another voltage level. A process-and-temperature-dependent bias circuit is provided to control the charge-injection pull-up transistor. The bias circuit causes the charge-injection pull-up transistor to adjust the discharge rate or transition rate of the signal line to compensate for timing delays caused by process or temperature variations.
US09424897B2 Equalizer and semiconductor memory device including the same
Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.
US09424892B2 Storage device to which memory device are connectable in multiple stages
A storage device includes a controller device and a memory device. The controller device transmits communication information to which route information is added, the route information indicating a route to a destination of the communication information and including an address of a relay point that the communication information passes through before reaching the destination of the communication information. The memory device receives the communication information, and to transmit the communication information to a next relay point, when the destination of the communication information is not the local memory device, by using the address of the relay point included in the route information of the communication information.
US09424891B2 Methods and devices for temperature sensing of a memory device
Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof. In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.
US09424888B2 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
US09424887B1 Apparatus with vapor-trapping pathway
Various aspects of the present disclosure are directed toward a disc drive apparatus including a disc drive actuator assembly, and a vapor-trapping pathway. The vapor-trapping pathway, in certain embodiments, is formed by an inner surface of an eblock, outer surface of a pivot shaft, and first and second shields. The vapor-trapping pathway being designed to mitigate the flow of vapor into an interior enclosure of the disc drive from within a ball-bearing cartridge.
US09424883B2 Method and apparatus for editing a video and/or audio program
The present invention provides a method and apparatus for editing an audio/video program. The method comprises the steps of acquiring the description information of two program segments of the program, the program segments being in sequence in playing order, the description information comprising the ending description information of the previous program segment and the start point information of the subsequent program segment, generating a guiding information to guide the ending point information to the start point information according to the description information and playing order of the program segments and updating the description information of the program according to the guiding information. With this invention, excessively detailed application editing work and an expense of high buffering cost may be avoided in editing compact disc program.
US09424882B2 System and method for semantic trick play
A semantic based trick play method and system in a media player is provided in which a semantic trick play command is received from a user while the user is experiencing a current content of a media item. Metadata is detected with respect to a current playback position of the media item, and at least one further playback position is determined in the current content of the media item or a related content in another media item. The further playback position is semantically related to the metadata of the current playback position. Playback is then moved to the at least one further playback position, so that the user experiences a media content of the at least one further playback position.
US09424881B2 Selective placement of progress bar
Methods and apparatus are disclosed for selecting the placement of a progress bar that is displayed on top of audiovisual content being presented on a display device when a viewer issues a “trick-play” command to change the rate at which the audiovisual content is being presented, such as rewind, pause, or fast-forward. The placement of the progress bar is selected such that it does not obscure audiovisual content used by the viewer to determine how long to issue the trick-play command.
US09424880B2 Method and apparatus for determining read-head deviation using orthogonal preambles
A storage device includes read circuitry having a read head having a detector that outputs signals representing data from a first track and an adjacent track. The read head is subject to off-track excursions during which the read head detects signals from both the first track and an adjacent track. Data on each track includes a preamble including a repeating pattern. The repeating pattern in any first track is orthogonal to the repeating pattern in any track adjacent to the first track. The read circuitry also includes respective Discrete Fourier Transform circuits to identify components in the signals corresponding to respective frequencies characteristic of the repeating pattern on the first track and the repeating pattern on the second track, and computation circuitry to determine from the components a ratio by which the read head is off-track. Corresponding methods are provided for operating such a storage device and for reading data.
US09424879B1 Data storage device with adaptive data capacity
A data storage device can have one or more data bits that are stored on a data storage medium and accessed with a transducing head. The data bits may be organized on the data storage medium to provide a surface data capacity. A performance degradation can be predicted for the transducing head by a controller connected to the transducing head. In response to the predicted performance degradation, the surface data capacity of the data storage medium is decreased.
US09424875B2 Content-receiving device
A content receiver comprises: an acceptance unit for accepting a designation of a recording medium to which contents are to be output; a license information acquiring unit for acquiring output license information describing the output requirements of the contents; and an output unit for outputting the contents to the designated recording medium. The output license information includes usage time limit information indicating the time limit of using the contents in an output destination. The output unit acquires the usage time limit information from the output license information for the contents, and sets the acquired usage time limit information to a management information storing area in the designated recording medium, thereby managing the time period of using the contents in the recording medium even if the copyright protection of the recording medium, which is an export destination, has a function to manage the time period of using the contents.
US09424872B1 Imprint template for patterned recording media
Provided herein is an apparatus including a rectangular array of rectangular protrusions in a first region corresponding to a data region; and a hexagonal array of circular protrusions in a second region corresponding to a servo region, wherein a first global protrusion density for the first region is greater than a second global protrusion density for the second region. Also provided herein is a method including forming a first template; forming a second template; and cross-imprinting the first template and the second template to form a third template corresponding to the foregoing apparatus.
US09424868B1 Data storage device employing spindle motor driving profile during seek to improve power performance
A data storage device is disclosed comprising a spindle motor configured to rotate a disk, wherein the spindle motor comprises a plurality of windings, and a head actuated over the disk. The windings of the spindle motor are commutated based on a commutation sequence while applying a periodic driving voltage to each winding. During a seek operation to seek the head a seek length, an amplitude of the periodic driving voltage is adjusted according to a driving profile corresponding to the seek length, wherein the driving profile compensates for a power disturbance during the seek operation.
US09424864B2 Data management for a data storage device with zone relocation
Managing data stored on media of a Data Storage Device (DSD) using zone relocation. At least a portion of the media is logically divided into a plurality of zones and zones are identified with access counts greater than or equal to a threshold. The access count for each of the identified zones indicates a number of times data in the zone has been read or written. Data is relocated from at least one zone of the identified zones to at least one destination zone on the media to reduce a data access time between the identified zones.
US09424859B2 System to control audio effect parameters of vocal signals
A vocal effect processing system may include an effect modification module configured to selectively and dynamically apply effects to an input audio signal in accordance with a degree of likelihood that the input audio signal includes a vocal signal and/or based on a proximate location of a source of vocal audio with respect to a vocal microphone. Determination of the degree of likelihood that the input audio signal includes a vocal signal and/or the proximate location may be based on processing of the input audio signal or a plurality of input audio signals. Determination of the proximate location may alternatively, or in addition, be estimated based on a proximity sensor. The effect modification module may dynamically and selectively adjust the effects in response to changes in the degree of likelihood that the vocal signal is included in the input audio signal and/or changes in the estimated proximate location.
US09424857B2 Encoding method and apparatus, and decoding method and apparatus
An encoding method of an encoder is provided. The encoder generates first MDCT coefficients by transforming an input signal, and generates MDCT indices by quantizing the first MDCT coefficients. The encoder generates second MDCT coefficients by dequantizing the MDCT indices, and calculates MDCT residual coefficients using differences between the first MDCT coefficients and the second MDCT coefficients. The encoder generates a residual index by encoding the MDCT residual coefficients, and generates gain indices corresponding to gains from the first MDCT coefficients and the second MDCT coefficients.
US09424856B2 Filling of non-coded sub-vectors in transform coded audio signals
A spectrum filler for filling non-coded residual sub-vectors of a transform coded audio signal includes a sub-vector compressor (42) configured to compress actually coded residual sub-vectors. A sub-vector rejecter (44) is configured to reject compressed residual sub-vectors that do not fulfill a predetermined sparseness criterion. A sub-vector collector (46) is configured to concatenate the remaining compressed residual sub-vectors to form a first virtual codebook (VC1). A coefficient combiner (48) is configured to combine pairs of coefficients of the first virtual codebook (VC1) to form a second virtual codebook (VC2). A sub-vector filler (50) is configured to fill non-coded residual sub-vectors below a predetermined frequency with coefficients from the first virtual codebook (VC1), and to fill non-coded residual sub-vectors above the predetermined frequency with coefficients from the second virtual codebook (VC2).
US09424854B2 Method and apparatus for processing audio data
A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common scalefactor value is determined for representing the quantized audio data in the frame. A line equation common scalefactor value is determined from the first and second common scalefactor values.
US09424853B2 Apparatus and method for synchronizing multichannel extension data with an audio signal and for processing the audio signal
For synchronizing multichannel extension data with an audio signal, wherein the audio signal includes block division information and the multichannel extension data include reference audio signal fingerprint information, the block division information in the audio signal is detected by means of a block detector. Thereupon, block division of the audio signal is performed by a fingerprint calculator according to the block division information in order to obtain a sequence of test audio signal fingerprints. In addition to that, a sequence of reference audio signal fingerprints is extracted from the reference audio signal fingerprint information of the multichannel extension data. Both sequences of fingerprints are correlated in order to obtain a correlation result, by which a compensator is controlled in order to reduce or eliminate a time offset between the multichannel extension data and the audio signal.
US09424852B2 Determining the inter-channel time difference of a multi-channel audio signal
There is provided a method and device for determining an inter-channel time difference of a multi-channel audio signal having at least two channels. A determination is made, at a number of consecutive time instances, of inter-channel correlation based on a cross-correlation function involving at least two different channels of the multi-channel audio signal. Each value of the inter-channel correlation is associated with a corresponding value of the inter-channel time difference. An adaptive inter-channel correlation threshold is adaptively determined based on adaptive smoothing of the inter-channel correlation in time. A current value of the inter-channel correlation is then evaluated in relation to the adaptive inter-channel correlation threshold to determine whether the corresponding current value of the inter-channel time difference is relevant. Based on the result of this evaluation, an updated value of the inter-channel time difference is determined.
US09424851B2 Frame error concealment method and apparatus and decoding method and apparatus using the same
A frame error concealment method and apparatus and a decoding method and apparatus using the same. The frame error concealment method includes setting a concealment method to conceal an error based on one or more signal characteristics of an error frame having the error and concealing the error using the set concealment method.
US09424848B2 Method for secure transactions utilizing physically separated computers
A secure transaction method involves establishing an electronically accessible verification site authorized by the holder of a credit or debit card, and accessing the verification site by a merchant to determine whether a request for goods or services is authorized. The request for goods or services is based upon the use of the credit or debit card, but the card is not physically presented. The verification site is an electronic mail account which may be established by the merchant, card holder or other authorized person or entity. An authorization message is preferably sent from the site to the merchant in response to the step of accessing the verification site by the merchant. The verification site may also be wirelessly accessible, enabling an authorization message to be delivered through a cellular telephone, personal digital assistant, or other mobile device.
US09424843B2 Methods and apparatus for signal sharing to improve speech understanding
Methods and devices are described for allowing users to use portable computer devices such as smart phones to share microphone signals and/or closed captioning text generated by speech recognition processing of the microphone signals. Under user direction, the portable devices exchange messages to form a signal sharing group to facilitate their conversation.
US09424842B2 Speech recognition system including an image capturing device and oral cavity tongue detecting device, speech recognition device, and method for speech recognition
A speech recognition system is to be used on a human subject. The speech recognition system includes an image capturing device, an oral cavity detecting device and a speech recognition device. The image capturing device captures images of lips of the subject during a speech of the subject. The oral cavity detecting device detects contact with a tongue of the subject and distance from the tongue of the subject, and accordingly generates a contact signal and a distance signal. The speech recognition device processes the images of the lips and the contact and distance signals so as to obtain content of the speech of the subject.
US09424835B2 Statistical unit selection language models based on acoustic fingerprinting
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for providing statistical unit selection language modeling based on acoustic fingerprinting. The methods, systems and apparatus include the actions of obtaining a unit database of acoustic units and, for each acoustic unit, linguistic data corresponding to the acoustic unit; obtaining stored data associating each acoustic unit with (i) a corresponding acoustic fingerprint and (ii) a probability of the linguistic data corresponding to the acoustic unit occurring in a text corpus; determining that the unit database of acoustic units has been updated to include one or more new acoustic units; for each new acoustic unit in the updated unit database: generating an acoustic fingerprint for the new acoustic unit; identifying an acoustic unit that (i) has an acoustic fingerprint that is indicated as similar to the fingerprint of the new acoustic unit, and (ii) has a stored associated probability.
US09424834B2 Method and system for reading fluency training
A non-transitory processor-readable medium stores code representing instructions to be executed by a processor. The code causes the processor to receive a request from a user of a client device to initiate a speech recognition engine for a web page displayed at the client device. In response to the request, the code causes the processor to (1) download, from a server associated with a first party, the speech recognition engine into the client device; and then (2) analyze, using the speech recognition engine, content of the web page including text in an identified language to produce analyzed content based on the identified language, where the content of the web page is received from a server associated with a second party. The code further causes the processor to send a signal to cause the client device to present the analyzed content to the user at the client device.
US09424832B1 Method and apparatus for safely and reliably sending and receiving messages while operating a motor vehicle
A system that allows a vehicle operator to record and send a voice message without ever releasing their hands from the wheel and taking their eyes off the road is disclosed. This system also allows incoming notification of messages to be read out loud to the user if they choose. The recipient, if not driving, can choose to see a transcription of the voice message, otherwise the recorded message is played back as recorded by a sending user.
US09424831B2 Voice synthesizing having vocalization according to user manipulation
A voice synthesizing apparatus includes a manipulation determiner configured to determine a manipulation position which is moved according to a manipulation of a user, and a voice synthesizer configured to generate, in response to an instruction to generate a voice in which a second phoneme follows a first phoneme, a voice signal so that vocalization of the first phoneme starts before the manipulation position reaches a reference position and that vocalization from the first phoneme to the second phoneme is made when the manipulation position reaches the reference position.
US09424829B2 Method for manufacturing compound diaphragm
The present disclosure provides diaphragm and a method for manufacturing the same. The diaphragm includes a first macromolecular material layer, a graphene layer, a glue layer and a second macromolecular material layer in sequence. The first macromolecular material layer is directly attached to the graphene layer, and the second macromolecular material layer is attached to the graphene layer via the glue layer. The strength and the stiffness of the diaphragm is enhanced to improve the acoustic performances of the diaphragm.
US09424826B2 Method for representing musical scales and electronic musical device
A method represents musical scales by means of tiles, including pentatonic scales (arbitrary scales with five notes per octave), heptatonic scales (arbitrary scales with seven notes per octave), Major blues and Minor blues scales (specific scales with six notes per octave). An electronic musical device has an interface that uses this representation. The device uses a multi-touch interface with or without strings, which allows the musician to concentrate on the melodic line only, making it easier to improvise and perform music composed in one of the scales. The representation differs from the traditional interfaces on string instruments (such as a guitar) in that only the notes of a given scale (with five, six or seven notes per octave) can be played.
US09424825B2 Keyboard apparatus for an electronic musical instrument
A keyboard apparatus has a plurality of white keys and black keys each of which pivot. The keyboard apparatus also has a plurality of reaction force generation members 21w and 21b provided for the white keys and the black keys, respectively. The reaction force generation members 21w and 21b have dome portions 21w1 and 21b1, respectively, which are thin and shaped like a dome so as to be elastically deformed by depression, and base portions 21w3 and 21b3, respectively, which are thick and are formed integrally with the dome portions 21w1 and 21b1 to support the dome portions 21w1 and 21b1, the base portions 21w3 and 21b3 jutting outward from respective lower end surfaces of the dome portions 21w1 and 21b1. The vertical position of the lower end of the dome portion 21w1 is displaced from the vertical position of the lower end of the dome portion 21b1.
US09424822B2 Musical score display device and accessory therefor
An electronic device adapted to display musical scores. The musical score display device includes a display for displaying a musical score, i.e. sheet music, to a user and a foot actuator accessory operatively connectable to the musical score display device that users can use to manually scroll through the displayed musical score in a hands-free manner. Alternatively, the display device comprises a microphone and is adapted to detect the playing of musical notes and automatically scroll through the displayed musical score without action by the user. Furthermore, the display device indicates to the user as to whether each note was played correctly or incorrectly via an on-screen prompt. The musical score display device is attachable to a variety of different support articles, such as a music stand or an instrument-attachable support.
US09424820B2 Transformable stand with an improved foot operated pitch changing mechanism for stringed instruments
Disclosed are apparatus and related methods for changing the pitch of a stringed instrument, such as an standard, fixed-pitch, resonating or Dobro-type guitar, by attaching the stringed instrument onto a transformable stand comprising a foot pedal assembly and string pitch changing mechanism. In one embodiment, the apparatus and related methods involve affixing the strings from an existing guitar to an improved pitch-changing mechanism, such as disclosed string pitch changer housing, that does not require the deconstruction of the guitar body. Rather, the existing guitar is securely placed on its back on a transformable stand with the use of specially designed plates that hold the instrument with screws, securing the body of the instrument to the stand.
US09424817B2 Fully-adjustable capo for stringed musical instruments
A tuning apparatus for a musical instrument is provided. The apparatus includes a clamp, a plurality of string-contacting members, and a string-contacting member spacing adjustment mechanism. The clamp removably attaches to a desired longitudinal position on the instrument's neck. Each member is rotatably supported by the clamp and rotates thereon independently of the other members. Each member also adjustably impinges upon and urges a given string or course thereof on the instrument toward a user-selectable one of three different longitudinal positions on the neck's front surface, these positions including a home position, a home−1 position, and a home+1 position. The mechanism allows a user to adjust the location of the members as a group on the clamp so as to substantially center the plane of rotation of each member over a different string or course thereof, and to maintain substantially equal spacing between each different adjacent pair of members.
US09424816B2 Electric stringed instrument having a pivotable body
An electric stringed instrument includes: an instrument main body which includes a front surface including a structure configured to hold a string; and a pair of frames which are connected to the instrument body. At least one of the pair of frames is a movable frame rotating toward the other one of the pair of frames with a longitudinal direction of the instrument main body serving as a rotating axis while going around a rear surface side of the instrumental body.
US09424812B2 Method and electronic apparatus for achieving translation of a screen display interface
A method and an electronic apparatus for achieving translation of a screen display interface are provided. The method comprises: sensing a first operation action of a user on a sensing screen; generating a first operation instruction when the first operation action is sensed; determining whether the first operation instructions belongs to a translation instruction that is preset for translating the display interface; if determining the first operation instruction belongs to the translation instruction, translating the screen display interface to a preset region by a preset distance towards a direction of an action region according to the first operation instruction for displaying, where the action region is a position region mapping the first operation action to the sensing screen. In this way, the present disclosure can allow a user to operate the full screen of a large sensing screen with a single bond.
US09424811B2 Digital collage creation kit
A digital collage creation kit is provided. The digital collage creation kit may include a digital photo cutter, a digital stamper, and a digital transforming tool. The digital photo cutter, the digital stamper, and the digital transforming tool may be configured to interact with a touch-screen surface of a computing device executing the digital collage creation kit application. Upon executing the digital collage creation kit application by the computing device, the digital collage creation kit may generate a digital collage creation environment, in which a digital collage may be created based on input received from one or more of the digital photo cutter, the digital stamper, and the digital transforming tool.
US09424809B1 Patterned projection with multi-panel display
A system for displaying a unified image on a multi-panel display includes a projector and a display engine. The projector is configured to project a patterned projection on a bezel region between an array of display panels arranged to be viewed as a multi-panel display. The display engine is coupled to drive the multi-panel display to display image sections. The patterned projection and the image sections combine to form a unified image.
US09424800B2 Driving device of image display medium, image display apparatus, and non-transitory computer readable medium
Provided is a driving device of an image display medium including a voltage application unit that varies a voltage applied to a common electrode provided in one of a pair of substrates, and applies a voltage to a pixel electrode provided in the other substrate through active matrix driving, with respect to the image display medium including plural kinds of particles, and a controller that controls the voltage application unit such that a voltage is applied between the pair of substrates, and controls the voltage application unit such that a deviation time of a scanning timing generated due to the active matrix driving during transition to the steps and a potential difference between the pair of substrates in the deviation time are equal to or less than predefined threshold characteristics of the particles.
US09424796B2 Circuit for eliminating shut down image sticking and array substrate comprising the circuit
The present disclosure relates to a field of display technique, and particularly to a circuit and an array substrate for eliminating shutting-down image sticking, which may eliminate the image sticking generated after a display apparatus is shut down. The circuit comprises a charging module and a discharging module; the discharging module is connected with a first voltage terminal, and is used for storing charges under a control of a first voltage signal input from the first voltage terminal; the discharging module is connected with the charging module and a second voltage terminal, and is used for providing the charges stored by the charging module to gate lines under a control of a second voltage signal input from the second voltage terminal.
US09424795B2 Display device, and driving method
A display device (1) includes: a scan line drive circuit (4) which line-sequentially selects from among a plurality of scan signal lines; at least one signal line drive circuit (3) which has a receiving circuit that receives a data signal, and which sequentially supplies the data signal to pixels linked to a scan signal line (6) selected by the scan line drive circuit (4); a timing controller (10) which defines, in accordance with sync signals received from an outside source, a non-scan period during which none of the scan signal lines is selected, and which transmits, to the at least one signal line drive circuit (3), an operation discriminant signal that causes the receiving circuit to be underrun during at least part of the non-scan period thus defined. The at least one signal line drive circuit (3) and the timing controller (10) are provided as separate entities.
US09424793B2 Displays with intra-frame pause
A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.
US09424792B2 Test method and test device for line defect of display panel
A test method for line defect in a display panel (10) comprises: inputting a first ON signal and a first OFF signal into odd rows of gate scanning lines (GE12) and even rows of gate scanning lines (GS13) of the display panel (10) respectively, to turn on transistors controlled by the odd rows of gate scanning lines (GE12), and turn off transistors controlled by the even rows of gate scanning lines (GS13), thereby obtaining a first test image; inputting a second OFF signal and a second ON signal into the odd rows of gate scanning lines (GE12) and even rows of gate scanning lines (GS13) of the display panel (10) respectively, to turn off the transistors controlled by the odd rows of gate scanning lines (GE12), and turn on the transistors controlled by the even rows of gate scanning lines (GE13), thereby obtaining a second test image; comparing the first test image with the second test image to determine that line display defect appearing in the first test image or the second test image are true display defect. Also is disclosed a test device for line defect in a display panel (10). This method allows the test result to approach the lighting test result under module signal input state and can detect true defect of the display panel (10).
US09424791B2 Reflective display device
A reflective display device includes a pixel array including a plurality of pixels; a data driver connected to each of the plurality of pixels and configured to transmit a target voltage to each of the plurality of pixels; and a scan driver connected to each of the plurality of pixels and configured to transmit a switching signal for determining whether the data driver transmits the target voltage to some of the plurality of pixels, wherein each of the plurality of pixels is configured to receive the target voltage for single data information, receive the target voltage in a first time period when the target voltage transmitted to each of the plurality of pixels is between a first voltage level and a second voltage level, and receive the target voltage in a second time period when the target voltage is between the second voltage level and a third voltage level.
US09424784B2 Array substrate and display device
The present invention discloses a local backlight brightness adjustment method for a direct backlight in a display device, the method comprising the steps of: step 1: performing edge detection on an input image to determine whether a sensitive zone exists, the sensitive zone being a portion in the input image in which a gray level difference between adjacent pixels is greater than a predetermined threshold; and Step 2: if a sensitive zone exists, performing a backlight brightness adjustment with respect to a backlight region corresponding to the sensitive zone and a remaining backlight region other than the backlight region corresponding to the sensitive zone, respectively. According to the above-mentioned technical solution, since the backlight brightness adjustment are performed with respect to the backlight region corresponding to the sensitive zone and the remaining backlight region other than the backlight region corresponding to the sensitive zone, respectively, thus, when there is gray level abruptly-varying portion in the image, the display performance of the displayer can still be ensured.
US09424782B2 Organic light emitting display
An organic light emitting display including a display panel having pixels coupled to data lines and first power voltage lines. Each of the pixels includes an organic light emitting diode; a driving transistor coupled to the organic light emitting diode and the first power voltage lines; a first transistor coupled to the data lines and a gate electrode of the driving transistor; a second transistor configured to supply a reference voltage of the data lines to a source electrode of the driving transistor; and a capacitor coupled to the gate and source electrodes of the driving transistor.
US09424781B2 Organic light emitting display device
An organic light emitting display is disclosed. The organic light emitting display includes a display panel having subpixels; a data driving part for supplying a data signal to the display panel; a compensation circuit part for sensing the subpixels; a power generation part for generating and outputting power to be supplied to the display panel and the data driving part; a voltage line wired between an output terminal of the power generation part and the display panel, the voltage line to transmit a voltage output from the power generation part to the display panel; and a power control part for controlling the voltage line.
US09424780B2 Pixel circuit of active matrix organic light emitting diode, driving method of the same, and display apparatus
A pixel circuit, a driving method, and a display apparatus, wherein the pixel circuit includes: a first switch transistor having a source connected to a data signal terminal, and a gate connected to a first control signal terminal; a first capacitor having a first terminal connected to a drain of the first switch transistor; a second capacitor having a first terminal connected to a second voltage signal terminal, and a second terminal connected to a second terminal of the first capacitor; a third capacitor having a first terminal connected to the first control signal terminal, and a second terminal connected to a gate of a driving transistor; a second switch transistor having a source connected to the gate of the driving transistor, a drain connected to a drain of the driving transistor, and a gate connected to the first control signal terminal; and a third, fourth, fifth and sixth switch transistors.
US09424776B2 Pixel circuit, display panel, and display device
A pixel driving circuit includes a signal loading component, a storage capacitor, a compensation component, a mirror component, and a drive transistor. In a data transmission stage, the signal loading component transmits a received image data signal to the gate of a drive transistor, which is stored in a storage capacitor; and in a threshold voltage compensation stage, the compensation component connects the gate of the drive transistor to the source of the drive transistor so as to generate a drive signal dependent upon the threshold voltage of the drive transistor from the signal stored in the storage capacitor and to drive an organic light emitting diode to emit light, thus eliminating an influence of the threshold voltage of the drive transistor on the current through the organic light emitting diode and preventing the brightness of the organic light emitting diode from varying over its operating period of time.
US09424773B2 Display panel, method of driving the same, and electronic apparatus
A display panel includes: a display section including a plurality of unit pixels; and a display drive section configured to generate first pixel packets and supply the first pixel packets to the display section, the first pixel packets each including luminance data of a digital signal, the pieces of luminance data determining respective luminances of respective predetermined number of unit pixels of the plurality of unit pixels, and the first pixel packets being equal in number to the predetermined number of unit pixels.
US09424768B2 System and method for universal 3D viewing device
A signal format definition data appropriate for a rendering device used to present alternate-frame sequencing based 3D material is identified and the identified signal format definition data is thereafter used to decode received synchronization signals associated with the rendering device. A shutter of a universal viewing device may thus be controlled as a function of the decoded synchronization signals associated with the rendering device to thereby allow for viewing of the alternate-frame sequencing based 3D material.
US09424765B2 Image processing apparatus, image processing method, and program
An information processing apparatus that includes a memory that stores a plurality of images, and a controller that obtains a template having attributes applied to each of a plurality of display areas, selects images matching the attributes of the respective display areas from among the plurality of images stored in the memory, disposes the selected images matching the attributes of the respective display areas in the respective display areas, and controls a display to display the template including the selected images disposed in the respective display areas.
US09424763B2 Messaging sign having a reversible fastening system for moveable display articles
A messaging sign apparatus is provided. The messaging signs includes a frame, and a moveable article. The frame includes an article receiving section along an inner body thereof and an article receiving opening on an outer surface and leading into the article receiving section. The moveable article is positioned in the article receiving section and moveable through the article receiving opening. The moveable article includes a first position notch positioned between a distal end and a leading end of the moveable article to engage the frame and secure one end of the moveable article within the frame and an opposite end positioned outside the frame.
US09424762B2 Cling print system
A label assembly including a label having a top surface and a bottom surface opposite the top surface, where the top surface includes indicia printed thereupon, and a layer of a first adhesive is coated on the bottom surface. The label assembly also includes a dome cover coupled to the label, the dome cover being formed of a substantially transparent material and having an underside, where a layer of a second adhesive is coated on the underside, the second adhesive having a greater holding capability than the first adhesive.
US09424755B2 Flight analogous and projection system
Systems and methods for processing aircraft flight information and flight plan information are described. Specific techniques are described for managing flight data in real time, sharing flight data between a plurality of systems, dynamically managing flight information, generating flight plan information, providing flight plan information to a user, and closing flight plan discontinuities.
US09424751B2 Systems and methods for performing driver and vehicle analysis and alerting
Systems and methods are disclosed for collecting vehicle data from a vehicle engine computer of a vehicle and a plurality of sensors disposed about the vehicle and generating feedbacks for a driver of the vehicle using at least the vehicle data. The systems and methods additionally provide for receiving user inputs from the driver responding to the feedbacks so that the user inputs are associated with corresponding rule violations that triggered the feedbacks.
US09424744B2 Method and apparatus for traffic management
A method for determining travel time of a vehicle on a road, wherein the vehicle is operable within a mobile communication network, comprising: collecting historical communication events of a mobile user in order to obtain travel samples, wherein the historical communication events indicate when the mobile user travelled along a monitored road; determining a cell handover sequence from the historical communication events; determining from the cell handover sequence, one of more road segments of the monitored road; determining the travel time of the one or more road segments according to the travel time samples; selecting, for an undetermined road segment of the monitored road for which the real-time travel time is not determined from the collected historical communication events, a candidate mobile user that is most likely to appear on the undetermined road segment; actively positioning the candidate mobile user to obtain positioning information; and returning to the step of collecting communication events of a mobile user currently on a monitored road with the active positioning as one communication event for the candidate mobile user, to determine the real-time travel time of the undetermined road segment.
US09424743B2 Real-time traffic detection
Systems and methods for real-time traffic detection are described. In one embodiment, the method comprises capturing ambient sounds as an audio sample in a user device, and segmenting the audio sample into a plurality of audio frames. Further, the method comprises identifying periodic frames amongst the plurality of audio frames. Spectral features of the identified periodic frames are extracted, and horn sounds are identified based on the spectral features. The identified horn sounds are then used for real-time traffic detection.
US09424741B2 Combined sense signal generation and detection
In an exemplary implementation, a detection circuit for regulating a power converter is configured to receive a combined sense signal comprising a first sense signal from the power converter superimposed with a second sense signal from the power converter. The detection circuit is further configured to generate a first detect signal from the combined sense signal and generate a second detect signal from the combined sense signal. The first detect signal can correspond to the first sense signal and the second detect signal can correspond to the second sense signal. The detection circuit can generate a filtered signal corresponding to the first sense signal from the combined sense signal to generate the first detect signal from the combined sense signal. Also, the detection circuit can generate an offset signal based on the combined sense signal to generate the second detect signal from the combined sense signal.
US09424733B2 Protection device
The invention relates to a device for securing objects against unauthorized removal. To this aim, the device (26) comprises an alarm electronics unit (1) having a motion sensor (3), an environmental brightness sensor (4), and an alarm signal transmitter (5). The alarm electronics unit (1) is designed so that the ambient brightness sensor (4) is activated by the detection of a movement. However, alarm release occurs only if the ambient brightness measured at the ambient brightness sensor (4) exceeds a predetermined brightness threshold, and the movement last continuously for a predetermined time span. The alarm activation occurs only if the ambient brightness falls below a predetermined darkness threshold and the movement continues to persist.
US09424730B2 Device for providing directional guidance while swimming
The present invention is generally directed to a device that provides haptic, auditory and/or visual indications representing a swimmer's deviation from an intended path. Visual indications can be displayed on one or more lenses of the swimmer's goggles. In this way, the swimmer can receive continuous guidance to swim in a desired direction without lifting his head to sight. The device can be configured as a base unit that can be worn on the head and an eyepiece that is attached to a lens of the swimmer's goggles. The eyepiece can include one or more LEDs for displaying the visual indications based on information received from the base unit.
US09424729B2 Security system tracking of remote items using reduced power
A mobile tracking unit includes a controller having a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions are executable by the processor to communicate with a control unit of an automation and security system, determine a position of the mobile tracking unit relative to a base station using a low power location module, and communicate the position of the mobile tracking unit to at least one of the base station and a control unit of the automation and security system. When the mobile tracking unit is outside a specified range from the mobile tracking unit, the controller continues tracking the position of the mobile tracking unit with the low power location module. When the mobile tracking unit is inside the specified range, the controller determines the position of the mobile tracking unit using a high power location module.
US09424727B2 Baby sleeping position reminder
A device and method to remind parents to regularly alternate the head position of a sleeping baby in order to prevent or minimize positional plagiocephaly. The device comprises a display area displaying a plurality of suggested head positions and at least one user-selectable indicator for selecting a first one of said plurality of suggested head positions. The user-selectable indicator is coupled with a source of illumination for maintaining visual indication of said first head position until the user manually selects a second head position or the device is turned off. The device further comprises a processor coupled with memory configured to store the user-selected head position which is visually indicated upon deactivation of said source illumination. The processor can then be configured to cause said source of illumination to blink indicating the user-selected head position stored in said memory upon the device being powered on.
US09424722B2 Smart memory material lock devices
Tracking device embodiments, comprising: portable housing with a locking mechanism; band latched about a wrist; tampering detection device to detect tampering with the band, comprising: power source; latch configured to latch one end of the band within the housing; a shape memory material component connected to the latch; an electrical circuit for controlling the power source to heat the shape memory material component to cause the shape memory material component to change from a first length/shape to a second length/shape during supply of power to perform a locking function; a timer; two-way network communication device; a tracking element; tampering signal generation circuit. In embodiments, a tamper resistant container cap, comprises: cap housing releasably lockable to an open end of a container and a locking mechanism using a shape memory material component.
US09424720B2 Gaming machine and methods of allowing a player to play gaming machines having modifiable reel features
A gaming machine is described herein. The gaming machine includes a display device for displaying a game and a controller connected to the display device. The game includes a plurality of reels, each reel having a reel strip including a plurality of symbol positions and a plurality of game symbols displayed in each of the symbol positions in a predetermined order. The controller is configured to determine an outcome of the primary game, responsively spin and stop the reels to display the outcome of the primary game, and provide a first award to the player based on the primary game outcome. The controller detects if a triggering graphic is being displayed with the primary game outcome and is associated with at least one reel, modifies a reel feature of a reel strip associated with the reel, and generates an outcome of a secondary game including the modified reel strip.
US09424718B2 Symbol match apparatus and method for game
A method and apparatus of aggregating a randomly distributed number of symbol images to a population of consumers using mobile communication devices to scan consumer products or promotional messages. The virtual game card puzzles on the communication devices are populated by the symbols in an order to complete a card and earn a prize or an entry for a drawing to win a prize.
US09424712B2 Authenticating components in wagering game systems
In some embodiments, a processor includes a plurality of local stores configured to store wagering game assets and at least part of a wagering game controller, and to store authentication keys for use in authenticating the wagering game controller and the wagering game assets; a plurality of processing elements, wherein each processing element is coupled to one of the local stores, each processing element configured to present wagering games by executing the wagering game controller; at least one authentication controller including hardware configured to authenticate, using the authentication keys, the wagering game controller and wagering game assets; a storage device in communication with the processor, the storage device configured to store the wagering game controller and wagering game assets, wherein the wagering game assets include audio and video content for use in presenting the wagering games.
US09424707B2 Actuated castellation plate for a currency acceptor
An actuated castellation plate can be arranged across a length of a currency passageway of a currency acceptor assembly and configured in an open state. Pressure from an attempted string fraud, such as pulling in reverse a bill across the castellation plate, can actuate the castellation plate to a closed state, obstructing the currency passageway so that the bait bill cannot be retrieved. Embodiments can include a currency acceptor including a currency passageway, mounting assembly, currency storage assembly having an entrance, the currency passageway being arranged to guide a currency denomination to the entrance of the currency storage assembly, and an actuated castellation plate including an array of teeth coupled to a baseplate including a receptacle and two opposing mounting ends, the castellation plate being configured at the entrance of the cashbox assembly to transfer between an open and closed state. Related apparatus, systems, techniques, and articles are also described.
US09424706B2 Controlled coin portal
A controlled coin inlet or portal is described that allows for improved alignment of a coin with the coin entry slot of a coin acceptor mechanism. A coin entry slot having at least an upper or lower edge is dimensioned to allow entry of a coin of a desired maximum width in a substantially on-edge orientation. The coin portal may include at least one outwardly extending coin guide slot of substantially corresponding maximum width as the coin entry slot and positioned adjacent to the upper or lower edge of the coin entry slot.
US09424705B1 Money handling apparatus
A money handling apparatus is constituted by a mechanical processing unit configured to mechanically process money, and a manually-handled money storage unit for storing money by a manual handling. The mechanical processing unit includes an inlet for receiving money, a recognition and counting unit configured to recognize and count the money that has been received in the inlet, a mechanically-processed money storage unit configured to store the money, an outlet to which the money fed from the mechanically-processed money storage unit is discharged, and a money transport unit configured to connect these units and portions. The manually-handled money storage unit is not connected to the money transport unit of the mechanical processing unit, and has a structure in which money to be manually managed can be directly stored therein by hand and the stored money can be directly taken out therefrom by hand.
US09424701B2 Electronic lock and key assembly
A locking device comprises a key that comprises a key power coil and a key data coil and an electronically-actuatable lock comprising a lock power coil and a lock data coil. The key power coil and the lock power coil are coaxial and at least partially overlapping one another when the key engages the lock. The key data coil lies in a first plane and the lock data coil lies in a second plane. The first plane and the second plane are substantially parallel to one another.
US09424700B2 Electronic lock having usage and wear leveling of a touch surface through randomized code entry
An electronic lock that requires the user complete a wear leveling action prior to entering in the passcode. The wear leveling action causes the user to touch one or more portions of the touch interface that may not be associated with the passcode to distribute wear of the touch interface. These area(s) of the touch interface selected for the wear leveling actions could be determined based on a pseudorandom number generator and/or by tracking usage of the touch interface to identify less used areas.
US09424699B2 Electronic access control and location tracking system
A method and system that allows authorized individuals access into controlled access locations and the ability to grant temporary and limited access to guests into these locations. The method and system allows for navigational services to be provided to members and guests, and real-time tracking and confirmation to members and administrators that guests have arrived at their destination and did not enter any unauthorized areas. The method preferably can work through a system of wireless radio, sound and/or light-based beacons communicating with member and guest's electronic devices. Members and administrators can send one or more temporary electronic access keys to a guest's smartphone or other electronic device. Wireless radio, sound and/or light-based beacons provide an access control and location tracking system with real-time data about the member and guest whereabouts, allowing for the confirmation and tracking.
US09424697B2 Apparatus, method and article for a power storage device compartment
A network of collection, charging and distribution machines collect, charge and distribute portable electrical energy storage devices (e.g., batteries, supercapacitors or ultracapacitors). To allow easy and convenient access to empty portable electrical energy storage device compartments within the vehicles, if the vehicle comes within the vicinity of a collection, charging and distribution machine or other authorized external device such as a key fob or other wireless device of a user, an empty portable electrical energy storage device compartment that is closed or locked, is unlocked, unlatched or opened automatically. Also, if the portable electrical energy storage device compartment is in another desired state to have the compartment unlocked, such as having a portable electrical energy storage device in the compartment that has a charge level below a particular threshold, the compartment will likewise be unlocked, unlatched or opened automatically.
US09424694B2 Assessing performance of a system
A method of generating probability data for use in assessing performance of a system and a mission involving the system. The method includes receiving (302) a combined model describing a system diagnosis model describing symptoms, failures and link strengths (conditionals) of components/subsystems of the system, and a mission impact model, the mission impact model describing effects of the system on an ability to perform the mission. Observation data regarding a state of the system is also received (306) The observation data is used (308) in combination with the combined model to generate probability data for use in assessing performance of the system and the mission.
US09424692B2 Systems and methods for transit industry vehicle hardware-agnostic communication
Systems and methods for hardware-agnostic communication between one or more mobile data terminals and one or more vehicle logic units, where a vehicle logic unit can communicate with one or more inputs from a transit industry vehicle and create an abstraction interface capable of being processed by multiple mobile data terminal hardware platforms—meaning that each vehicle logic unit can communicate with multiple mobile data terminals, and each mobile data terminal can communicate with multiple vehicle logic units.
US09424690B2 Method for translating the location, orientation and movement of a predefined object into computer generated data
A method, comprising: obtaining an image data of a physical object; the physical object comprises a plurality of markers positioned on the outer surface of the physical object; analyzing, using a computer, the data, to identify visual markers information indicative of at least some of a plurality of markers; determining an orientation and a location of the physical object in response to predefined attributes of the plurality of markers and to the visual markers information.
US09424687B2 Method, apparatus and computer program product for modelling the non-linear structural response of a component
A method, apparatus and computer program product for modeling the non-linear structural response of a component. The non-linear structural response is modeled using a two-step global-local finite element analysis method, which employs a linear global analysis step, a linear intermediate analysis step and a non-linear local analysis step. The boundary conditions applied in the intermediate step are derived in part from the linear global analysis and the boundary conditions applied in the local analysis are derived in part from the global and intermediate analyses.
US09424685B2 Unified rasterization and ray tracing rendering environments
A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.
US09424683B2 Transposing apparatus, transposing method, and computer product
A transposing apparatus is configured by a computer controlling a computing device having computing elements arranged into a matrix and memory devices connected to the computing elements. The computing device executes an electromagnetic field analysis process on latticed three-dimensional analysis subject data present in a three-dimensional coordinate system. The computer is configured to detect the number of lined-up lattices in a direction of a first axis, in a direction of a second axis, and in a direction of a third axis of the coordinate system, through detection on the three-dimensional analysis subject data; transpose a group of lattices of the three-dimensional analysis subject data, based on the detected numbers of lined-up lattices and on the number of lined-up computing elements in a row direction and in a column direction; and output to the computing device, the three-dimensional analysis subject data transposed.
US09424661B2 Method and an apparatus for facilitating efficient information coding
A method and an apparatus for producing a coded graphic representation. The method includes providing a graphic array and processing at least a portion of the graphic array. A graphic array can be provided such that an array of graphic indications which includes a plurality of graphic indication pairs can be provided. Each of the plurality of graphic indication pair can have at least a first graphic element and a second graphic element. The first and second graphic element can be spaced apart such that each of the plurality of graphic indication pairs can be associated with an element pitch. The element pitches of the plurality of graphic indication pairs can be substantially similar. At least a portion of the graphic array can be processed by displacing at least one graphic indication pair in the plurality of graphic indication pairs such that at least one element pitch is deviated.
US09424656B2 Computer vision based method and system for evaluating and grading surgical procedures
To increase the timeliness, objectivity, and efficiency in evaluating surgical procedures such as those performed by ophthalmology residents' learning of cataract surgery, an automatic analysis system for surgeries such as cataract surgery is provided to assess performance, particularly in the capsulorrhexis step on the Kitaro simulator. Computer vision technologies are employed to measure performance of this critical step including duration, centrality, circularity, size, as well as motion stability during the capsulorrhexis procedure. Consequently, a grading mechanism is established based on either linear regression or non-linear classification via Support Vector Machine (SVM) of those computed measures. Comparisons of expert graders to the computer vision based approach have demonstrated the accuracy and consistency of the computerized technique.
US09424655B2 Image processing apparatus, method, and storage medium for analyzing changes in video
An image processing apparatus includes an acquisition unit configured to acquire a video, a superimposition unit configured to superimpose an image onto the video acquired by the acquisition unit, and a detection unit configured to detect the emergence of an object in a video in a detection area set on the video acquired by the acquisition unit, wherein the superimposition unit superimposes an image corresponding to the size of the object to be detected when emerging by the detection unit onto the video in the detection area, and outputs the resultant video to the detection unit.
US09424651B2 Method of tracking marker and electronic device thereof
Disclosed are a method and an apparatus for tracking a marker. The method of tracking a marker by an electronic device includes: detecting a position of a marker in a first frame; tracking a position of the marker in a second frame based on the position of the marker detected in the first frame; and estimating a 3D position based on the tracked position of the marker. Further, the method of tracking a marker is implemented through various embodiments.
US09424648B2 Method and system for device detection in 2D medical images
A method and system for device detection in a 2D medical image. In order to account for shape variation of a 3D object in a 2D imaging plane, a hierarchical tree-structured array of trained classifiers is used to detect a 3D object, such as a pigtail catheter in a 2D medical image, such as a fluoroscopic image. The hierarchical tree-structured array of trained classifiers increases a dimensionality of the search space with each hierarchical level, and as the search space is increased, the classification is split into object sub-classes using trained classifiers independently trained for each sub-class.
US09424642B2 Extraction of myocardial contour points
One of the preferred embodiments includes: (a) creating a summed 3D nuclear medicine imaging data by summing a plurality of 3D nuclear medicine imaging data pixel by pixel; (b) determining pixels corresponding to myocardial regions in the summed 3D nuclear medicine imaging data; (c) defining a plurality of tracing directions based on the summed 3D nuclear medicine imaging data, and determining a reference myocardial center base point, a reference inner myocardial wall base point and a reference outer myocardial wall base point for each of the tracing directions; (d) determining a phase-specific myocardial center base point for each of the tracing directions for each of the phases; and (e) seeking a difference between the reference myocardial center base point and the phase-specific myocardial center base point, and determining a phase-specific inner myocardial wall base point and a phase-specific outer myocardial wall base point.
US09424641B2 Visual suppression of selective tissue in image data
A method image data processor (318) includes a shape likelihood determiner (402) that processes voxels of image data and determines a likelihood that a voxel represents predetermined tissue of interest for a plurality of the voxels based on a shape of a tissue represented by the voxel, an opacity determiner (406) that determines an opacity suppression for each of the plurality of voxels based on the likelihood, a re-formatter (410) that re-formats the image data based on the determined opacity suppression, generating opacity suppressed re-formatted data, and a rendering engine (412) that visually presents the opacity suppressed re-formatted data.
US09424640B2 Pathological diagnosis support apparatus and pathological diagnosis support method
A pathological diagnosis support apparatus outputs a diagnostic region that is to be used as a target for diagnosis in a specimen image representing a specimen that is a target for pathological diagnosis, and includes: a target obtainment unit which obtains the specimen image and specimen information related to a scheme for preparing the specimen; a criterion obtainment unit which obtains a criterion corresponding to the specimen information from a database associating, for each of a plurality of specimens, specimen information related to a scheme for preparing each of the plurality of specimens with a criterion indicating a condition of a positive rate which is to be satisfied by the diagnostic region in a specimen image; and an output unit which outputs, as the diagnostic region, each of one or more regions in the specimen image having the positive rate determined to satisfy a condition indicated by the criterion obtained by the criterion obtainment unit.
US09424634B2 Machine vision system for identifying and sorting projectiles and other objects
A machine vision system for automatically identifying and inspecting objects is disclosed, including composable vision-based recognition modules and a decision algorithm to perform the final determination on object type and quality. This vision system has been used to develop a Projectile Identification System and an Automated Tactical Ammunition Classification System. The technology can be used to create numerous other inspection and automated identification systems.
US09424633B2 Image processing apparatus, and non-transitory computer readable medium for generating a feature-reflected image and for changing a degree of reflection of a feature in the feature-reflected image
Provided is an image processing apparatus including an acquisition section that acquires an object image which is an editing object, a feature quantity acquisition section that acquires a feature quantity of a reference image which is referred to when the object image is edited, a feature-reflected image generation section that reflects a feature of the reference image on the object image by using the feature quantity acquired by the feature quantity acquisition section, and generates a feature-reflected image which is the object image on which the feature is reflected, and a reflection degree changing section that changes a degree of reflection of the feature in the feature-reflected image by using an adjustment value which is input by a user.
US09424630B2 Method and apparatus for detecting and removing false contour, method and apparatus for verifying whether pixel is included in contour, and method and apparatus for calculating simplicity
A method and an apparatus for detecting and removing a false contour, a method and an apparatus for verifying whether a pixel is included in a contour, and a method and an apparatus for calculating simplicity are provided. The method for detecting and removing the false contour includes: verifying whether a pixel of an input video is included in a contour; calculating simplicity of the pixel; determining whether the pixel is included in a false contour based on the simplicity and based on whether the pixel is included in the contour; and removing the false contour from the input video via smoothing with respect to the false contour.
US09424622B2 Methods and apparatus for processing graphics data using multiple processing circuits
Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.
US09424615B2 In-game football strategy system and method
A system and method are disclosed for determining and recommending a coaching decision during a football game, where the recommended coaching decision corresponds with the highest probability of winning the football game.
US09424610B1 Method and apparatus for performing transaction item identification
System and methods for determining items purchased in a transaction are described. Transaction information, such as a transaction amount, transaction location, and merchant ID may be used to generate a pre-tax transaction amount. A website affiliated with a transacted merchant may be parsed to determine whether one or more single items, or combinations of items, have prices that alone or when summed equal the pre-tax transaction amount. The items may be assigned probability values based on clustering and consumer profiling and an item ID may be stored for each item having the highest probability value.
US09424609B2 Interactive account management system and method
Embodiments of the invention are directed to a computer-implemented interactive account management system operated in cooperation with a financial institution on behalf of multiple account holders. The interactive account management system may include a financial networking engine implemented by a processor for defining a financial network for each account holder and for identifying each member of an account holder financial network based on stored account information and account holder input. The system may additionally include interactive processing components for processing information to provide collaborative interaction between the members of the account holder financial network defined by the financial networking engine and user interface presentation tools for displaying financial guidance and collaborative interaction interfaces and inviting active participation from the financial network members.
US09424608B2 Generating and delivering a wrap package of cards including custom content and/or services in response to a vehicle diagnostic system triggered event
Delivery of a wrap package “on the fly” in reply to a vehicle onboard diagnostic (OBD) system triggered event. When a notice of the event is received, a wrap package, including custom content presented within a plurality of cards arranged in one or more linear sequences, is automatically authored. The custom content encompasses, but is not limited to, one or more media types, application functionality and/or e-commerce related services. In one embodiment, the custom content pertains to a specific code generated by the OBD system that corresponds to the event. In another embodiment, the triggered event is an accident.
US09424604B2 Internet radio and broadcast method personalized by ratings feedback
Data streams are generally selected according to user preferences and transmitted to the user in general alignment with expressed preferences of the user. Such data streams may be music, including music videos. Users may indicate their general or specific preferences with regards to song, artists, or albums. Any other aspects or factors that might affect the user's preferences can be taken into account. A playlist is created that combines all of these factors. The playlist then serves as the basis for feeding the data streams to the user. Each user is able to express his or her own preferences and receive music corresponding to those preferences on an on-going basis.
US09424595B2 Customized content delivery based on geographic area
Methods and systems are disclosed for providing customized content to users based on their location. In one embodiment, for each of one or more content providers, a customized content delivery function receives information from the content provider defining a number of geographic shapes selecting corresponding geographic areas. Preferably, each of the geographic shapes overlaps at least one other of the geographic shapes and is assigned an importance level. For each geographic shape, the content provider defines one or more tags for the geographic shape and assigns a weight to each of the one or more tags. Thereafter, when a request is received from a requestor, one or more content items are selected for delivery to the requestor based on the geographic shapes, the tags and corresponding weights for the geographic shapes, and the location of the requestor.
US09424594B2 System for targeting location-based communications
Embodiments of the invention are directed to systems, methods and computer program products for providing targeted location-based communications. An exemplary apparatus is configured to receive an encoded signal, decode the encoded signal such that embedded data is retrieved, send the embedded data a remote server; and receive a message based at least partially on sending the embedded data. Another exemplary apparatus is configured to provide the encoded signal by receiving data input, receiving a host signal, embedding the data input within the host signal such that an encoded signal is generated, and transmitting the encoded signal. A third exemplary apparatus is configured to provide the targeted communications by storing one or more messages associated with an entity, receiving data, selecting at least one of the one or more messages based at least partially on the data received, and sending the at least one of the one or more messages selected.
US09424593B2 Secured identities collaboration system and method
An identities collaboration system that comprises a Personal Service Provider (PSP) system for supplying specific user related personal service(s); means for assigning two different data files to each user opting-in to the PSP system, wherein one data file contains data representing the user identity at the PSP system and it assigned on a first domain, and the other data file(s) contains data representing the information regarding whether the user is opted-in, or another identity number that is related to the user identity at the PSP, and is assigned on a second domain. The data files are stored within the terminal of each of the opting-in users; The system also comprises a third party server for providing personal service or tailored content to the opting-in user; and a utilities package, located within each of the third party servers, for identifying or re-tagging the user as a PSP user by using the data files, whenever such data file exists, or existed in the past, and is currently missing from the terminal of the user.
US09424590B2 Method and system for real time targeted advertising in a retail environment
A method and a system for real time targeted advertising using purchase transaction data and payment card holder activity and location information in a retail environment. The system includes a radio frequency identification (RFID) reader situated in a retail environment. The RFID reader communicates with an RFID tag that is situated on a payment card of a payment card holder to track the payment card holder as the payment card holder walks around in the retail environment. The system also includes a processor configured to select a predictive behavioral model based on payment activities attributable to the payment card holder and payment card holder activity and location in a retail environment, associate the predictive behavioral model with merchant advertising information, and convey the associated information to a merchant to enable the merchant to make a targeted offer to the payment card holder.
US09424589B2 Systems and methods for enabling and managing ordering information within a network
Systems, methods, and computer-readable mediums, consistent with principles of some embodiments of the present invention provide for remote ordering of goods within a shopping establishment including enabling selection between a plurality of counter services, receiving information relating to the selected counter service, enabling customization of the order for the selected counter service, transmitting the selection information, customization information and order identifying information to one of a plurality of remote devices to be fulfilled, and receiving completion data from the one of the plurality of remotes devices when the order is fulfilled.
US09424586B1 Remote sensor management
Technologies are described herein for remote management of sensors and other functionalities in a digital signage device through a remote management server. In particular, a Digital Signage Control System (“DSCS”) facilitates delivery of sensor command parameters to particular signage devices or a network of signage devices as specified in a Sensor Command Deployment Plan. After receiving various sensor commands from a user at a user interface, a Sensor Command Deployment Module generates a Sensor Command Deployment Plan (“SCDP”), which specifies which sensors or controls should be adjusted on signage device(s) and when the adjustments should be made. Subsequently, a Signage Communication Module (“SCM”) waits for a request for sensor instructions from a signage device specified in the plan. Once the request is received, the SCM deploys specific instructions or commands (parameters) to a particular signage device wherein the command is executed at the signage device.
US09424583B2 Differential trials in augmented reality
Techniques for displaying virtual objects on devices in differential situations are provided. Augmented reality authoring ensures that users have a consistent experience with virtual objects, including augmented reality images, by delivering the same versions of the virtual objects to devices that are close in terms, for instance, of at least distance and/or time. Devices that are not sufficiently close may receive different versions of the virtual object, thus ensuring that the users of devices that are sufficiently near each other do not experience different versions of the virtual object.
US09424582B2 System and method for managing customer address information in electronic commerce using the internet
A system and method for managing customer address information in electronic commerce using the Internet are provided. Customers' detailed address information is received from customer terminals connected over the Internet, a unique address number corresponding to the detailed address information is produced, and the produced unique address number and the corresponding detailed address information are separately stored and managed in separate database (DBs), thereby effectively preventing leakage of the customers' detailed address information due to hacking or a malicious program.
US09424580B2 Table for storing parameterized product/services information using variable field columns
Computer implemented systems store descriptions of multiple different types of marketplace items as a collection of parameter-value pairs, using a table having a plurality of rows and columns, wherein values for at least two of the items are stored in cells of first and second ones of the rows, respectively; keys that provide information that can be used to decipher differential mappings of a plurality of the columns to a plurality of parameters in different ones of the rows; and one or more interfaces that collectively display previously stored parameters and values to a human end-user.
US09424577B2 Systems and methods for processing payment transactions at fuel dispensing stations
The methods and systems described herein provide for processing electronic payments at a retail location. Secure payment information for use in processing future payment transactions initiated by a mobile device may be stored at a secure location remote from retail locations. A mobile device of a user may be detected and location determined based at least in part on the strength of a signal via a wireless antennas at the retail location. A determination is made that the mobile device is associated with a user who previously provided payment information for use in processing payment transactions. The mobile device may receive incentives based at least in part on the determined location. A user may complete a payment transaction at the retail location without providing the secure payment information at the retail location.
US09424567B2 Authentication method and system
A method and system capable of authenticating transactions involving at least one service provider and one or more users who are each in electronic communication. This electronic communication can be, for example, SMS, MMS, e-mail or online account messaging. Certain embodiments provide for the transaction to be an authentication and/or verification of an entity. Examples of such entities are products, actions and users.
US09424560B2 Time indicators for calendars
In a multiday view of a calendar, a time indicator is shown adjacent to a graphical element for the current day. In the multiday view, such a time indicator accurately indicates the current time on the current day, but not on other days of the week. If the current day is not viewable, the time indicator is not shown. By being adjacent to the graphical element for the current day, the time indicator does not obscure information, such as events, for the current day.
US09424559B2 Annotation of communications
A calendar event that is addressed to a plurality of recipients is generated. At least one of the plurality of recipients is designated as a first annotation recipient. A first annotation is associated with the calendar event, the first annotation addressed to the first annotation recipient.
US09424555B2 Virtual conferencing system
The present invention provides a virtual conferencing system including a wearable information device to be worn by a user; an environmental information capturing device that captures environmental information; a virtual simulation device that receives the environmental information captured by the environmental information capturing device, calculates simulation conferencing scenes by an intelligence algorithm, and transmits the simulation conferencing scenes to the wearable information device as the user's feedbacks.
US09424550B2 Charging for operator-assisted sessions in IMS networks
IMS networks and methods are disclosed for charging for operator-assisted sessions. To perform the charging, an operator assistance application server (AS) acts as an interface between an operator system (legacy or IMS) and charging systems for the IMS network. When an operator-assisted session is initiated in the IMS network, the operator assistance AS receives a session initiation message in SIP, and transmits the session initiation message to the operator system to allow the operator system to collect charging information from an end user. The operator assistance AS then receives a service request message from the operator system that includes the collected charging information, and detects a charging event. The operator assistance AS generates a Diameter charging request message, maps the charging information from the service request message to the Diameter charging request message, and transmits the Diameter charging request message to a charging system to charge for the operator-assisted session.
US09424549B2 System and method for facilitating user-generated content relating to social networks
A system and method for facilitating user-generated content relating to social networks are provided. The system provides an online environment which poses questions to users, and which allows the users to answer such questions by identifying appropriate contacts of the user. The system automatically identifies the user's contacts by consulting one or more electronic accounts of the user on one or more social networking sites/services, and/or one or more e-mail accounts. The user can respond to questions posed by clicking on appropriate contacts, dragging them, and dropping them in an answer area in the online environment. The user can manage his/her contacts by creating one or more groups and/or tags associated with each contact. The grouped/tagged contacts can be imported into a contact management system, and can be used by researchers to conduct social network visualizations or to achieve other research objectives.
US09424546B2 Prioritising event processing based on system workload
Event processing is prioritized based on system workload. A time constraint attribute is defined in an event rule. The event rule uses one or more events. An event processing system is monitored to determine when the system is under a predefined level of stress. If the system is determined to be under the predefined level of stress, the time constraint attribute in the event rule is used to establish when the processing of a received event used in an event rule must be carried out.
US09424540B2 Identifying service oriented architecture shared service opportunities
An approach that identifies a service oriented architecture (SOA) shared service opportunity is provided. In one embodiment, there is an opportunity tool, including an identification component configured to identify a plurality of projects from each of a plurality of lines of business; a selection component configured to select a set of projects common to more than one line of business from the plurality of lines of business; and an evaluation component configured to evaluate the set of projects common to more than one line of business from the plurality of lines of business to identify a SOA shared service opportunity.
US09424533B1 Method and system for predicting an outcome of an event
Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, OCR (text), background, relationship, position, pattern, and object), large number of images (“Big Data”) analytics, machine learning, training schemes, crowd-sourcing (using experts or humans), feature space, clustering, classification, similarity measures, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, Natural Language Processing (NLP), Computing-with-Words (CWW), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability (e.g., using Z-number (e.g., “About 45 minutes; Very sure”)), rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, and data compression.
US09424527B2 Information processing system, network structure learning device, link strength prediction device, link strength prediction method and program
An information processing system separately generates sample sequences from a posterior distribution of each random variable in a probability model representing the structure of a template network that serves as a template for a plurality of networks whose network structures are to be learned, and from a posterior distribution of each random variable in a probability model representing the structures of the plurality of networks, using learning data and hyperparameters relating to the plurality of networks. Next, the information processing system derives a predictive value of the strength of a link specified by an external variable based on the external variable and on the sample sequences.
US09424526B2 Quantum processor based systems and methods that minimize a continuous variable objective function
Computational techniques for mapping a continuous variable objective function into a discrete variable objective function problem that facilitate determining a solution of the problem via a quantum processor are described. The modified objective function is solved by minimizing the cost of the mapping via an iterative search algorithm.
US09424525B1 Forecasting future states of a multi-active cloud system
An embodiment of the invention may include a method, computer program product and computer system for forecasting future states of a multi-active cloud. The method, computer program product and computer system may include a computing device that determines the operating state of the passive server. The operating state of the passive server is one or more of a deploying state and a smoke testing state. The computing device may determine the probability of the operating state successfully completing. The computing device may delay the second asynchronous workflow until the operating state successfully completes based on the probability of the operating state successfully completing exceeding a predetermined value.
US09424523B2 Providing computable guidance to relevant evidence in question-answering systems
A computer-based system includes a computer-processable definition of a region in a data set. The system identifies a region of the data set based on the definition of the region. The system provides output to a user representing a question and the identified region of the data set. The system may also automatically generate an answer to the question based on the question and the data set, and provide output to the user representing the answer. The system may generate the answer based on a subset of the data set, and provide output to the user representing the subset of the data set. The user may provide feedback on the first answer to the system, which the system may use to improve subsequent answers to the same and other questions, and to disable the system's automatic question-answering function in response to disagreement between the user and the system.
US09424520B1 Semantic database driven form validation
Embodiments of the present invention provide a means for validating electronic forms using one or more semantic databases. The invention includes processing an electronic form into individual elements and generating entities for the individual elements. The closest matching ontology is found for each entity and the pairings are grouped into a general formal ontology tree. The entities in the general formal ontology tree are traversed using generated rules. This analysis yields validation results that are combined with the original form to create an annotated form.
US09424519B1 Cost-effective remote monitoring, diagnostic and system health prediction system and method for vapor compression and heat pump units based on compressor discharge line temperature sampling
A diagnostic monitoring system and method is employed for one or more vapor compression systems such as air conditioners and heat pumps having a compressor, an indoor air handler fan coil and an outdoor condensor. Temperature, voltage and current sensors are provided at the outdoor condensor to determine that at least one vapor compression system is operating properly. Data obtained from the sensors is wirelessly transmitted to a receiving-device for use by the systems' custodian or repair service provider and includes information concerning an occurrence of periods when one or more of the vapor compression systems are operating at an abnormal state.
US09424514B2 Synapse maintenance in the developmental networks
The developmental neural network is trained using a synaptic maintenance process. Synaptogenic trimming is first performed on the neuron inputs using a synaptogenic factor for each neuron based on standard deviation of a measured match between the input and synaptic weight value. A top-k competition among all neurons then selects a subset of said neurons as winning neurons. Neuronal learning is applied only to these winning neurons, updating their synaptic weights and updating their synaptogenic factors.
US09424513B2 Methods and apparatus for neural component memory transfer of a referenced pattern by including neurons to output a pattern substantially the same as the referenced pattern
Aspects of the present disclosure support techniques for neural component memory transfer. A pattern in a plurality of afferent neuron outputs can be first referenced with one or more referencing neurons. One or more first relational aspects can be matched, with one or more first relational aspect neurons, between the referenced pattern and an output of the one or more referencing neurons. The referenced pattern can be transferred to one or more transferee neurons by inducing the plurality of afferent neurons to output a pattern substantially the same as the referenced pattern by the one or more referencing neurons.
US09424512B2 Directed behavior in hierarchical temporal memory based system
A hierarchy of computing modules is configured to learn a cause of input data sensed over space and time, and is further configured to determine a cause of novel sensed input data dependent on the learned cause. At least one of the computing modules has a sequence learner module configured to associate sequences of input data received by the computing module to a set of causes previously learned in the hierarchy.
US09424511B2 Methods and apparatus for unsupervised neural component replay by referencing a pattern in neuron outputs
Aspects of the present disclosure support techniques for unsupervised neural component replay. A pattern in a plurality of afferent neuron outputs can be first referenced with one or more referencing neurons. One or more relational aspects can be matched, with one or more relational aspect neurons, between the pattern and an output of the one or more referencing neurons. One or more of the plurality of afferent neurons can be induced to output a pattern that is substantially the same as the referenced pattern by the one or more referencing neurons.
US09424509B2 System for application personalization for a mobile device
A system for controlling applications of a wireless mobile device includes a server for receiving data related to an adaptive user profile and for controlling operations of applications within the wireless mobile device. An adaptive neural/fuzzy logic control application implemented within the network server generates the adaptive user profile responsive to the received data. The adaptive user profile controls operations of the applications within the wireless mobile device and changes in real time responsive to the received data.
US09424507B2 Dual interface IC card components and method for manufacturing the dual-interface IC card components
Dual-interface Integrated Circuit (IC) card components and methods for manufacturing the dual-interface IC card components are described. In an embodiment, a dual-interface IC card component includes a single-sided contact base structure, which includes a substrate with an electrical contact layer. On the single-sided contact base structure, one or more antenna contact leads are attached to the single-sided contact base structure to form a dual-interface contact structure, which is a component of a dual-interface IC card. Other embodiments are also described.
US09424498B2 Information processing apparatus, information processing method, and recording medium for conversion of vendor-specific print data
An information processing apparatus for generating drawing data by using a print job including print data and setting information, includes a description detection unit detecting a characteristic description included in the print data; a conversion unit converting the print data, the characteristic description, and the setting information into an instruction group; and one or more drawing data generation units generating the drawing data by executing the instruction group.
US09424496B2 Image forming apparatus with image deformation correction using user input length information of test image line drawing
An image forming apparatus for easily setting a parameter for avoiding an occurrence of defective image by the sector deformation is provided. The image forming apparatus forms a test image. The test image having a first line drawing and a second line drawing, each of which is extending in a first direction, and the first line drawing and the second line drawing are provided at different positions in a second direction which is perpendicular to the first direction. Further, the image forming apparatus obtains the length information of the first and the second line drawings. Based on the length information of the first and the second line drawings, a correction condition is set. Then, the image forming apparatus corrects the image data based on the correction condition according to a position of the second direction.
US09424495B1 Digital food imaging analysis: system and method to analyze food consumption
A method for identifying and analyzing amounts and nutritional values of food consumption, utilizing digital image processing and linked nutritional information. A recipe generator is utilized to provide a component analysis of food preparations based on identification of subcomponents.
US09424494B1 Pure convolutional neural network localization
An approach is provided in which a knowledge manager processes an image using a convolutional neural network. The knowledge manager generates a pixel-level heat map of the image that includes multiple decision points corresponding to multiple pixels of the image. The knowledge manager analyzes the pixel-level heat map and detects sets of decision points that correspond to target objects. In turn, the knowledge manager marks regions of the heat map corresponding to the detected sets of per-pixel decision points, each of the regions indicating a location of the target objects.
US09424493B2 Generic object detection in images
Neural networks for object detection in images are used with a spatial pyramid pooling (SPP) layer. Using the SPP network structure, a fixed-length representation is generated regardless of image size and scale. The feature maps are computed from the entire image once, and the features are pooled in arbitrary regions (sub-images) to generate fixed-length representations for training the detectors. Thus, repeated computation of the convolutional features is avoided while accuracy is enhanced.
US09424490B2 System and method for classifying pixels
Embodiments are disclosed that relate to processing image pixels. For example, one disclosed embodiment provides a system for classifying pixels comprising retrieval logic; a pixel storage allocation including a plurality of pixel slots, each pixel slot being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel; and scheduling logic configured to control dispatches from the pixel slots to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence.
US09424489B2 Automated feature analysis, comparison, and anomaly detection
Novel methods and systems for automated data analysis are disclosed. Data can be automatically analyzed to determine features in different applications, such as visual field analysis and comparisons. Anomalies between groups of objects may be detected through clustering of objects.
US09424487B2 Image matching method and image processing system
A processor of executes the following processes on one or more second feature point pairs for a first feature point pair from among created first pair candidates. A first vector is a vector that connects a first feature point of the first feature point pair and a first feature point of the second feature point pair. A second vector is a vector that connects a second feature point of the first feature point pair and a second feature point of the second feature point pair. The processor determines that a first feature point pair has been deleted from the first pair candidates, on the basis of a comparison result between a predetermined angle and an angle between the first vector and the second vector. The processor performs matching between the first image and the second image on the basis of feature point.
US09424484B2 Feature interpolation
Feature interpolation techniques are described. In a training stage, features are extracted from a collection of training images and quantized into visual words. Spatial configurations of the visual words in the training images are determined and stored in a spatial configuration database. In an object detection stage, a portion of features of an image are extracted from the image and quantized into visual words. Then, a remaining portion of the features of the image are interpolated using the visual words and the spatial configurations of visual words stored in the spatial configuration database.
US09424483B2 Method and device for measuring the verticality of a container
A method of measuring lean on a container driven in rotation comprises: taking at least one image of the container to obtain images of the left and right edges of the ring, the matrix images of the left and right edges of the heel, of the shoulder, and/or of the base of the neck; analyzing the images of the left and right edges of the ring to determine the real position of the ring; and the matrix images of the left and right edges to determine a left positioning point Tg and right positioning point Td; and determining the theoretical position of the ring on a perpendicular to the straight line segment passing through the left and right positioning points; and based on variations in the differences between the real position and the theoretical position of the ring, deducing a measurement of the lean of the container.
US09424481B2 Screenshot database for application verification
Methods, systems, and computer-readable mediums are presented that process and store images efficiently in a memory system. When a new image is received, it is compared to a plurality of reference images. The most similar reference image is located, and a delta image is generated representing a difference between the reference image and the new image. Instead of storing the entirety of the new image, the delta image can be stored along with a reference to the corresponding reference image, such that the new image can be restored from the delta image and the reference image. The total number of reference images and delta images can be dynamically balanced such that predetermined ratios of image numbers or image sizes can be maintained.
US09424476B2 Method for detecting a vehicle sunvisor's state
A method for detecting a vehicle sunvisor's state includes obtaining a detected image; conducting a gray-scale preprocessing on the detected image, to obtain a gray-level image; conducting a main connected region extraction on the gray-level image, and calculating a geometric feature and a rectangle similarity of each main connected region; conducting a horizontal long edge extraction on the gray-level image, and conducting feature matching operation between horizontal long edges and main connected regions to obtain a region edge matching relationship; determining the sunvisor's state based on the region edge matching relationship, the geometric feature of main connected regions and rectangle similarity of main connected regions. The present invention can be widely applied in the field of image process.
US09424473B2 Identifying scene boundaries using group sparsity analysis
A method for identifying a set of key video frames from a video sequence comprising extracting feature vectors for each video frame and applying a group sparsity algorithm to represent the feature vector for a particular video frame as a group sparse combination of the feature vectors for the other video frames. Weighting coefficients associated with the group sparse combination are analyzed to determine video frame clusters of temporally-contiguous, similar video frames. The video sequence is segmented into scenes by identifying scene boundaries based on the determined video frame clusters.
US09424470B1 Systems and methods for scale invariant 3D object detection leveraging processor architecture
An example method includes receiving a plurality of templates of a plurality of objects, where a template comprises feature values sampled at corresponding points of a two-dimensional grid of points positioned over a particular view of an object and scaled based on a depth of the object at the particular view. The method may further include receiving an image of an environment and determining a matrix representative of the image, where a row of the matrix comprises feature values sampled at a particular point of the two-dimensional grid positioned over one or more locations within the image and scaled based on depths of the one or more locations. The method may additionally include determining at least one similarity vector corresponding to at least one template and using the at least one similarity vector to identify at least one matching template for at least one object located within the image.
US09424468B2 Moving object prediction device, hypothetical movable object prediction device, program, moving object prediction method and hypothetical movable object prediction method
A position, behavior state and movement state of a moving object are detected, together with plural categories of track segment region and stationary object regions, using an environment detection section. A presence probability is applied to the detected track segment regions and stationary object regions and a presence probability map is generated, using a map generation section. A moving object position distribution and movement state distribution are generated by a moving object generation section based on the detected moving object position, behavior state and movement state, and recorded on the presence probability map. The moving object position distribution is moved by a position update section based on the moving object movement state distribution. The moved position distribution is changed by a distribution change section based on the presence probabilities of the presence probability map, and a future position distribution of the moving object is predicted on the presence probability map. Consequently, the future position of the moving object can be predicted with good precision under various conditions.
US09424466B2 Shoe image retrieval apparatus and method using matching pair
Provided are a shoe image retrieval apparatus and method using a matching pair, which can accurately retrieve image information corresponding to an inputted image from the database and provide the retrieved image information, by normalizing a correspondence relation in consideration of geometric image transformation about the matching pair and allowing a similar image to be retrieved by applying the normalized correspondence relation. It is possible to detect optimum geometric image transformation from a matching pair between the inputted shoe image and the image stored in the database and simultaneously retrieve a plurality of objects in the inputted shoe image based on the detected geometric image transformation, thereby providing an efficient shoe retrieval service.
US09424460B2 Tumor plus adjacent benign signature (TABS) for quantitative histomorphometry
Methods, apparatus, and other embodiments associated with predicting prostate cancer (CaP) progression using tumor cell morphology features and benign region graph features are described. One example apparatus includes a set of logics that acquires an image of a region of tissue, detects and segments cells in the image, extracts a set of morphological features from cells in a first region in the image, constructs a graph of a localized cellular network in a second region of the image, extracts a set of graph features from the graph, generates a set of tumor plus adjacent features signature (TABS) features from the sets of graph features and the set of morphological features, and calculates the probability that the image is a progressor or non-progressor based, at least in part, on the set of TABS features. The first region may concern cancerous cells and the second region may concern benign cells.
US09424459B1 Computerized methods for cell-based pattern recognition
Systems and methods relating to a cell-based pattern recognition tool for microscopy images from tissue sections are described, wherein cell features are extracted and a classifier is built in accordance with a particular application using an interactive training tied to a computerized platform, the result is an application-specific classifier that further processes images in accordance with the specific application, thereby tuning an automated process for cell based pattern recognition.
US09424458B1 Systems and methods for performing fingerprint based user authentication using imagery captured using mobile devices
Technologies are presented herein in support of a system and method for performing fingerprint recognition. Embodiments of the present invention concern a system and method for capturing a user's biometric features and generating an identifier characterizing the user's biometric features using a mobile device such as a smartphone. The biometric identifier is generated using imagery captured of a plurality of fingers of a user for the purposes of authenticating/identifying the user according to the captured biometrics and determining the user's liveness. The present disclosure also describes additional techniques for preventing erroneous authentication caused by spoofing. In some examples, the anti-spoofing techniques may include capturing one or more images of a user's fingers and analyzing the captured images for indications of liveness.
US09424456B1 Ultrasonic fingerprint authentication based on beam forming
An ultrasonic finger print authentication system that generates a three-dimensional representation of a fingerprint. High frequency sound waves are used as a medium for imaging finer details of the patterns on a fingertip, including the ridge and valley formations. Multiple frequencies and beam-forming are used to quickly map the ridges. Acoustic resonance is used to determine the depths of the intervening valleys.
US09424451B2 Low-energy radio frequency tag for performing a vehicle function
A low-energy transceiver tag is described, as well as methods of using the low-energy transceiver tag to enable secure communication with a vehicle. The low-energy transceiver tag includes a substrate, and electronic circuitry carried by the substrate having a transceiver circuit coupled to a power circuit. The transceiver circuit may be configured to transmit a preconfigured answer signal in response to receiving a query signal. In addition, the preconfigured answer signal may be a low-energy response associated with a remotely-located trust anchor.
US09424446B2 Point of sale inductive systems and methods
Systems and methods for the identification, powering and control of products and product packaging. The systems can include a point of sale display having a contactless power supply. The contactless power supply can provide a source of wireless power for products and product packaging. The products and product packaging can include light emitting diodes, e-ink displays and printed speaker circuits that activate as the operating frequency of the contactless power supply varies. Other embodiments include product level sensors, inductive reader networks, printed temperature sensors, product alignment systems, passive identification circuits and methods for controlling operation of the same.
US09424442B2 Nonvolatile memory and electronic device
The embodiments of the present invention disclose a nonvolatile memory and an electronic device, where each time the nonvolatile memory is powered on, an exchanger is used to implement a random exchange of at least one address subsignal and its inverted signal in a bank decoder and/or a row decoder in a bank and/or a column decoder in a bank, which causes that data stored before the nonvolatile memory is powered off is interrupted when the nonvolatile memory is powered off and then powered on and that data stored in the nonvolatile memory cannot be read sequentially from original storage addresses to achieve an encrypting effect and increase security of the data stored in the nonvolatile memory.
US09424441B2 Multiprocessor fabric having configurable communication that is selectively disabled for secure processing
Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
US09424435B2 Filesystem access for web applications and native code modules
One embodiment provides a system that facilitates the execution of a web application. During operation, the system allocates a storage space on one or more storage devices for use by the web application. Next, the system creates, for the web application, a private filesystem comprising a private root directory within the storage space. Finally, the system enables access to the private filesystem for the web application through the private root directory in a manner that does not allow access to a host filesystem associated with the one or more storage devices from the web application.
US09424434B2 Personal electronic device and data theft prevention system and method thereof
Data theft prevention technology for a personal electronic device is provided. When an internet-communication address of the personal electronic device is detected by a server through the internet and the server determines that the detected internet-communication address has been listed in a lost list, a processing unit of the personal electronic device operates in accordance with anti-theft software to execute the codes contained in a BIOS memory of the personal electronic device to set a medium password for a user-data storage medium of the personal electronic device and to prohibit the use of the personal electronic device.
US09424429B1 Account management services for load balancers
A configurable load balancer can be utilized in a multi-tenant environment, where the load balancer can incorporate, or utilize, an account management service operable to perform security tasks such as authentication, authorization, and session management. Customers can utilize the load balancer to control access that users have to resources associated with those customers, without having to build and maintain a dedicated user management system. By implementing security functionality at the load balancer level, traffic can be managed before reaching the resources, which can help to reduce traffic and load on the resources, and can also help to prevent attacks and secure sensitive information. Visibility into the traffic through the load balancer also allows for behavior and usage monitoring, which is helpful for tasks such as billing and usage limit enforcement.
US09424426B2 Detection of malicious code insertion in trusted environments
Methods and computer program products which facilitate detection of malicious code insertion by an insider during the software development lifecycle are disclosed Aspects focus on behavioral characteristics associated with the introduction of malcode during the software development process. Injection of malcode by an insider threat, and the malcode itself, may leave behind behavioral signatures in the source code repository and source code that can be detected by a multi-dimensional combination of sensors. By detecting the behavioral signatures of malcode within artifacts generated by the software development process, instances of malcode can be isolated and prevented before release.
US09424425B2 Protecting anti-malware processes
Anti-malware process protection techniques are described. In one or more implementations, an anti-malware process is launched. The anti-malware process is verified based at least in part on an anti-malware driver that contains certificates which contain an identity that is signed with the trusted certificate from a verified source. After the anti-malware process is verified, the anti-malware process may be assigned a protection level, and an administrative user may be prevented from altering the anti-malware process.
US09424424B2 Client based local malware detection method
A method for detecting malware in a user terminal device that has been infected by malware via a browser running on the user terminal device, according to which upon detecting a predetermined a triggering event on the user terminal, a security application installed on the terminal automatically activates a transparent browser to navigate to one or more predetermined URLs. Then the security application checks the code of an inspected webpage that has been received immediately after it is opened by the transparent browser and rechecks the code after being at least partially processed by the transparent browser. If a change the code is detected, an alert is issued, indicating that the terminal has been infected by malware.
US09424421B2 Security engine for a secure operating environment
The presenting invention relates to techniques for implementing a secure operating environment for the execution of applications on a computing devices (e.g., a mobile phone). In The secure operating environment may provide a trusted environment with dedicated computing resources to manage security and integrity of processing and data for the applications. The applications may be provided with a variety of security services and/or functions to meet different levels of security demanded by an application. The secure operating environment may include a security engine that enumerates and/or determines the security capabilities of the secure operating environment and the computing device, e.g., the hardware, the software, and/or the firmware of the computing device. The security engine may provide security services desired by applications by choosing from the security capabilities that are supported by the secure operating environment and the computing device.
US09424419B1 Automatic rotation and storage of security credentials
A system and method for a credentials agent that automatically rotates and stores security credentials usable at least in part to authenticate calling applications with a computing resource service provider. Upon determining that a first set of credentials are due to be rotated, the credentials agent may obtain a second set of credentials and store the second set of credentials in a data store. The credentials agent may give notice to a calling application that the first set of credentials is due to be rotated, whereupon the calling application may obtain the second set of credentials and be authenticated to access a resource of the computing resource service provider at least in part by providing the second set of credentials. The authorization system provides visualizations and alerts to administrators of unexpected states that may be caused by misconfigured applications or malicious users.
US09424416B1 Accessing applications from secured states
A computing device can enable a user to navigate to an application or other digital object directly from a lock screen of the device. A user can specify a credential, such as a short code, that is associated with a specific application. If the credential is recognized, the device can be unlocked and the corresponding application displayed. The user can then be granted full or partial access to functionality and/or data of the device, as may depend at least in part upon the type of credential or a level of access specified for the credential. The credential can be based at least in part upon, or independent of, a general unlock credential for the device. In some embodiments, the user can be able to specify the amount and/or type of access to be granted under a credential, such as access only to utilize the corresponding application.
US09424410B2 Methods and systems for leveraging transaction data to dynamically authenticate a user
A system and method for authenticating a candidate user accessing a host computing device as an authentic user is provided. The host computing device is in communication with an authenticating computing device. The method includes receiving, by the authenticating computing device, a request to authenticate the candidate user as an authentic user. The authentication request includes a user identifier. The method also includes retrieving, by the authenticating computing device, transaction data including payment transactions performed by the authentic user based on the user identifier. The method also includes generating, by the authenticating computing device, a challenge question and a correct answer based on the transaction data associated with the authentic user, and transmitting the challenge question for display on a candidate user computing device used by the candidate user.
US09424405B2 Using receipts to control assignments of items of content to users
The described embodiments comprise an electronic device that executes an application, the electronic device including a processing subsystem. In these embodiments, the processing subsystem is configured to acquire a receipt associated with the application, wherein the application was purchased by a purchasing entity and installed on the electronic device after being assigned to a user of the electronic device by the purchasing entity. The processing subsystem is further configured to determine, using the receipt, if the application has expired. When the application has not expired, The processing subsystem is configured to execute the application with predetermined functions of the application enabled. When the application has expired, The processing subsystem is configured to execute the application with the predetermined functions of the application disabled.
US09424403B2 Obtaining software asset insight by analyzing collected metrics using analytic services
A plurality of software instances deployed in a monitored environment are discovered by a software asset management tool operated by a software asset administrator who is responsible for monitoring software license compliance within the monitored environment. The software asset management tool then collects metrics associated with the plurality of software instances. The collected metrics are then provided to a first analytic service adapted to generate analytic information about the plurality of software instances. Using at least the collected metrics, the analytic service generates analytic information. The analytic information is then obtained from the analytic service. By reviewing the analytic information, the software asset administrator is able to obtain additional insight into the monitored environment that would not otherwise be available to him.
US09424392B2 System and method for cleaning noisy genetic data from target individuals using genetic data from genetically related individuals
A system and method for determining the genetic data for one or a small set of cells, or from fragmentary DNA, where a limited quantity of genetic data is available, are disclosed. Genetic data for the target individual is acquired and amplified using known methods, and poorly measured base pairs, missing alleles and missing regions are reconstructed using expected similarities between the target genome and the genome of genetically related subjects. In accordance with one embodiment of the invention, incomplete genetic data is acquired from embryonic cells, fetal cells, or cell-free fetal DNA isolated from the mother's blood, and the incomplete genetic data is reconstructed using the more complete genetic data from a larger sample diploid cells from one or both parents, with or without genetic data from haploid cells from one or both parents, and/or genetic data taken from other related individuals.
US09424391B2 Installation optimisation
A computer-implemented method for determining a configuration of a plurality of components in a systems installation which satisfies one or more constraints.
US09424388B2 Dividing lithography exposure fields to improve semiconductor fabrication
In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, a computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines the one or more exposure areas in the reticle field, and at least one lithography process parameter for each exposure area of the one or more exposure areas in the reticle field based, at least in part, on the data received from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.
US09424385B1 SRAM cell layout structure and devices therefrom
A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.
US09424384B2 Method of density-controlled floorplan design for integrated circuits and integrated circuits
A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.
US09424383B2 Design, layout, and manufacturing techniques for multivariant integrated circuits
An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.
US09424382B1 Method and apparatus for providing fault tolerance through compilation diversity
A method for designing a system on a target device includes synthesizing a logic representation of a processing channel from a description of the processing channel in hardware description language (HDL) according to a first set of constraints. A logic representation for a redundant processing channel is synthesized from the description of the processing channel in HDL according to a second set of constraints. The processing channel and the redundant processing channel are placed and routed.
US09424379B2 Simulation system and method for testing a simulation of a device against one or more violation rules
A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation. The simulation system further comprises a reporting unit for preparing a report of the rule scores associated with the one or more violation rules and for reporting the report to a user. A method of testing a simulation of a device against one or more violation rules is described.
US09424373B2 Site modeling using image data fusion
Site modeling using image data fusion. Geometric shapes are generated to represent portions of one or more structures based on digital height data and a two-dimensional segmentation of portions of the one or more structures is generated based on three-dimensional line segments and digital height data. A labeled segmentation of the one or more structures is generated based on the geometric shapes and the two-dimensional segmentation. A three-dimensional model of the one or more structures is generated based on the labeled segmentation.
US09424370B2 System and method for spatial partitioning of CAD models
A method and related CAD system and computer readable medium. A method includes loading an object model in a CAD system, the object model including a plurality of parts each of which may contain one or more shapes which in turn are composed of multiple polygons. The method includes adding the shapes to a spatial tree, the shapes each corresponding to at least one cell, each cell corresponding to a spatial region of the object model. The method also includes, for each cell that is too complex to process within a memory space of the CAD system, subdividing the cell into a plurality of subcells using a first subdivision process. The method also includes subdividing each cell into a plurality of subcells using a multi-threaded subdivision process, and combining the subcells into the spatial tree.
US09424365B2 XPath-based creation of relational indexes and constraints over XML data stored in relational tables
Techniques and approaches are provided for creating indexes and column constraints on structured XML data that is stored in a relational database. Data Definition Language (DDL) Create Index and Create Constraint commands have extended syntax that allows the specification of a path-based expression instead of requiring a column and table name. A mapping created by the system when an XML Schema is registered stores the correspondence of XML data elements to automatically-created database tables and columns that are given names only useful for the internal system. When a user provides a path-based expression in a DDL when creating an index or constraint, the path-based expression is translated to the underlying database constructs using the mapping. Issues are addressed for handling path-based expressions that evaluate to more than one element. Additional index optimization is described using data type information available in the XML schema to select the optimal index type.
US09424364B2 Integrated context-driven information search and interaction
A method and a device are disclosed including an integrated connection between a Social Business Network (SBN) and a webpage configured to provide context-based relevant information about content and/or metadata associated with the webpage. A SBN provides business-oriented information in a social networking environment. In some embodiments, SBN connection automatically provides information about the webpage's owner, or is used used or to start a conversation with another user. In still other embodiments, the SBN connection may retrieve information from external sources such as Facebook®, web, and databases associated with the SBN, including prior relevant conversations, project information, participant information, articles, historical data, and the like. In various embodiments, the SBN connection is in the form of a browser plugin component, which may be enhanced by custom software cartridges developed by customers of SBN to dynamically alter the behavior or add functionality to the SBN plugin component.
US09424356B2 Updating a search index using reported browser history data
Methods, systems, and computer-readable media are provided for updating a search index with new uniform resource locators (URLs) and spiking URLs with increased user interest. History data, provided from browser applications residing on users' computers that indicate URLs accessed by the users, is parsed to identify new/previously unknown URLs. The history data also indicates URLs in which there is increased interest based on a number of recent hits as compared to an average number of hits determined over time. Author postings of new URLs to social networking sites and a quality rating of the authors may also be used to identify and filter new URLs. Search indexes are updated with the new and spiking URL data. As such, lag time between posting of new URLs and spiking of URL interest and inclusion of this data in a search index is greatly decreased.
US09424353B2 Related entities
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for receiving a first search query from a user device; receiving search results for the first search query provided by a search engine, wherein each of the search results identifies a respective resource; determining from the search results that the first search query relates to a first entity of a first entity type; determining that one or more entities of a second entity type have a predetermined relationship with the first entity; and transmitting information identifying the one or more entities of the second type to the user device as part of a response to the first search query.
US09424352B2 View item related searches
A system and method of providing related search queries are disclosed. A new item listing is identified based on a determination that the new item listing lacks a predetermined minimum amount of clickstream data. Similar item listings for the new item listing is determined from a plurality of old item listings based on at least one item feature of the new item listing and the plurality of old item listings. The plurality of old item listings comprises live item listings and completed item listings. Each old item listing has at least the predetermined minimum amount of clickstream data. Related search queries of the similar item listings are associated with the new item listing. The related search queries for the new item listing are provided along with the new item listing to a user on a client device.
US09424351B2 Hybrid-distribution model for search engine indexes
Methods and systems are provided for using a hybrid-distribution system to identify relevant documents based on a search query. A group of documents is assigned to a particular segment. The group of documents is indexed both by atom and by document to form a reverse index and a forward index. Both indexes are divided amongst each node in that segment so that each node is responsible for storing and accessing a different portion of both the reverse and forward indexes. The reverse index portion is accessed on each of a first set of nodes to identify a first set of documents that is relevant to a particular search query. Document identifications associated with the first set of documents are used to identify a second set of nodes that access their forward index portions to limit the number of relevant documents to a second set of documents.
US09424346B2 Web query classification
A query phrase may be automatically classified to one or more topics of interest (e.g., categories) to assist in routing the query phrase to one or more appropriate backend databases. A selectional preference query classification technique may be used to classify the query phrase based on a comparison between the query phrase and patterns of query phrases. Additionally, or alternatively, a combination of query classification techniques may be used to classify the query phrase. Topical classification of a query phrase also may be used to assist a search system in delivering auxiliary information to a user who entered the query phrase. Advertisements, for instance, may be tailored based on classification rather than query keywords.
US09424340B1 Detection of proxy pad sites
A system may identify a set of first documents associated with an organization, and identify clusters to which the first documents belong. Each of a number of the identified clusters may include a group of documents that includes one of the first documents and one or more second documents associated with one or more different organizations. The system may determine a quality score for each of the documents in each of the identified clusters, and determine, for each of the number of the identified clusters, whether the quality score of the one of the first documents in the identified cluster is higher than the quality score of the one or more second documents in the identified cluster. The system may generate a proxy pad score based on the determinations, and store the proxy pad score.
US09424338B2 Clustering queries for image search
Aspects of the subject matter described herein relate to functions used for retrieving image results based on search queries. More specifically, image search queries can be pre-grouped or classified based on visual and semantic similarity. For example, a pairwise image similarity value for a pair of queries can be computed based on one or more of the sum of all of the overlapping the image results, the sum of the image distances between all of the pairs of images in the image results, and the rank of each of the images in the image results. The pairwise image similarity values can then be used to generate image query clusters. Each image query clusters can include a set of queries with high pairwise image similarity values. In some examples, a distance function can be determined for each image query cluster. This data can be used to provide image results.
US09424336B2 Facilitating distributed data processing for dynamic and efficient generation of search results in an on-demand services environment
In accordance with embodiments, there are provided mechanisms and methods for facilitating distributed data processing for dynamic and efficient generation of search results in a multi-tenant environment according to one embodiment. In one embodiment and by way of example, a method includes receiving, at a data processing platform, extracted data occurrences from a database coupled to a server computing device, where each data occurrence may be assigned a classification according to a category. The method may further include mapping values to the data occurrences based on classifications of the data occurrences, mapping prefixes to the data occurrences based on identifying names of the data occurrences, and generating search data based on the mapped values and mapped prefixes, where the search data may represent autosuggestions.
US09424324B2 Method, computer-readable medium, and system for storing, allocating and retrieving medical image data in a distributed computerized system of a clinical facility
In a method for storing and providing medical image data in a distributed, computer-based system of a clinical facility comprising multiple satellites, wherein a satellite has at least one modality, an image administration server and at least one local database, and wherein the clinical facility also has a central database for the administration of the stored image data and a central long-term storage for long-term storage, the image data are acquired at the modality, the image data include metadata and pixel data, partial metadata in the metadata of the acquired image data are marked, at least the metadata of the image data acquired are locally stored at the respective satellites, the image data of the image data acquired at the respective satellites are centrally stored in the central long-term storage, all metadata stored in the local database in the central database are completely, centrally replicated, and the marked partial metadata of the image data from the central database are partially, automatically replicated at respective local databases of one, multiple or all satellites in order to be able to provide these image data at the satellites.
US09424322B2 Digital sticky note
An apparatus includes at least one computer readable storage medium that bears instructions executable by a processor to configure the processor for accessing one or more electronically stored calendars of events pertaining to at least one user to obtain first calendar information from the one or more electronically stored calendars. The instructions also configure the processor for accessing at least one social network service for which the user has an account to obtain second calendar information from the site, consolidating the first and second calendar information to render consolidated information, presenting at least some of the consolidated information on a user device associated with the user, and presenting a recommendation for action pertaining to the event along with at least one event in die consolidated information.
US09424317B2 Ranking algorithm for search queries
In various embodiments, a method of prioritizing search results in an electronic environment is disclosed. The method includes selecting a plurality of equivalent keywords responsive to a search query from an end-user, determining a rank of each of the plurality of equivalent keywords, selecting a plurality of most highly ranked keywords from the plurality of equivalent keywords, and preparing a response including the plurality of most highly ranked keywords.
US09424310B2 System and method for executing queries
There is provided a computer-implemented method of executing a query plan against a database. An exemplary method comprises accessing a first subset of rows of a database table using a direct access method for an index. The query plan may comprise the direct access method. The exemplary method also comprises determining a processing cost of accessing the first subset of rows. The exemplary method further comprises modifying the direct access method for the index in response to determining that the processing cost exceeds a specified threshold. Additionally, the exemplary method comprises accessing a second subset of rows of the database table using the modified direct access method.
US09424309B2 Method for optimizing performance of database/web-service backed applications by automatically prefetching query results
The present disclosure proposes the method for optimizing the performance of data base/web-service backed applications by automatically prefetching query results. The proposed system and methods automatically insert prefetch instructions at the earliest possible points across procedure calls in application source code, in presence of conditional branching and loops. A data flow analysis technique called anticipable expressions analysis is extended, to analyze anticipability of queries. The benefit of prefetching is limited due to the presence of assignment statements and conditional branches that precede the query execution statement. Enhancements such as code motion, chaining and rewriting prefetch requests are devised to increase benefits of prefetching. These techniques perform equivalence preserving program and query transformations.
US09424305B1 Multi-faceted search
A facility for representing a set of items each potentially having a value for each of a group of attributes is described. The items are represented in a database made up of two or more discrete components. Each component corresponds to a proper subset of group of attributes, and represents for every item of the set the values of its proper subset of attributes. Every component is organized such that data items are represented within it in the same order.
US09424304B2 Maintenance of active database queries
An aspect includes a method for maintaining active queries. The method includes executing a query based on data items in at least two relations in a database. The executing includes outputting a query result and control information associated with the query. The query result and the control information are recorded. A notification that at least one of the data items has been updated subsequent to the executing is received. The query result is modified, responsive to the control information, to reflect the data items that were updated subsequent to the executing.
US09424302B2 Sorting information by relevance to individuals with passive data collection and real-time injection
In one aspect, data, such as information articles, is sorted and prioritized based on a plurality of factors, such as user interest and popularity of data with respect to other users. The data is sorted by initial personal (i.e., user) data, sorted by the most relevant to the user, while passive interaction data is used to continually reorder the articles in real-time, while new stories are being injected into the stream in real time, all while other articles are increasing/decreasing in stature based on popularity with regard to other users and time decay. As such, the system provides that the information is fed to users in an efficient manner, in a manner based on time relevance, assumed interest with regard to that given user based on past actions by that user or information otherwise known about that user, as well as interest in the articles demonstrated by other users.
US09424301B2 System and method for negotiated takeover of storage objects
A system and method of negotiated takeover of storage objects includes one or more processors, a storage controller, and memory coupled to the one or more processors. The memory stores a data structure that includes information about a plurality of storage objects manageable by the storage controller. The storage controller is configured to assume, one by one, current ownership of a first subset of the storage objects and assume, concurrently, current ownership of a second subset of the storage objects. The first subset of storage objects and the second subset of storage objects are currently owned by a second storage server coupled to the storage server. In some embodiments, current ownership of the first subset of storage objects is transferred by iteratively detecting a particular storage object from the first subset of the storage objects whose current ownership can be assumed and bringing the particular storage object online.
US09424300B2 Data allocation containers in a partitioned table of a computer database system for holding data based on usage
An apparatus and method utilize partitioned database tables divided into data allocation containers (DACs) where data is placed into the DACs based on usage of the data in past queries. Records that are used most often are placed together and records that are used less often are placed together to improve database performance. In preferred embodiments, a database manager determines where to place data into the DACs based on how often the data is selected by a database query using a DAC selection ratio (DSR). The database manager may determine when to perform table maintenance to move rows of data to the appropriate DACs based on a timestamp or last check date (LCD) stored in the database.
US09424299B2 Method for preserving conceptual distance within unstructured documents
A method, system and computer-usable medium are disclosed for preserving conceptual distance within unstructured documents by characterizing conceptual relationships. Natural language processing is applied to content in a plurality of documents to identify topics and subjects. Analytic analysis is then applied to the identified topics and subjects to identify concepts. The content in each of the plurality of documents is partitioned into a first structured hierarchy, preserving at least one structure in each document inherent in the each document. Access is then provided to the content through a first index based upon utilizing the first structured hierarchy and through a second index utilizing a second structured hierarchy. The conceptual relationship criteria are based upon a directed graph with weights based upon a similarity and a distance based upon concepts.
US09424298B2 Preserving conceptual distance within unstructured documents
A method, system and computer-usable medium are disclosed for preserving conceptual distance within unstructured documents by characterizing conceptual relationships. Natural language processing is applied to content in a plurality of documents to identify topics and subjects. Analytic analysis is then applied to the identified topics and subjects to identify concepts. The content in each of the plurality of documents is partitioned into a first structured hierarchy, preserving at least one structure in each document inherent in the each document. Access is then provided to the content through a first index based upon utilizing the first structured hierarchy and through a second index utilizing a second structured hierarchy. The conceptual relationship criteria are based upon a directed graph with weights based upon a similarity and a distance based upon concepts.
US09424297B2 Index building concurrent with table modifications and supporting long values
Disclosed herein are system, method, and computer program product embodiments for constructing an index for a database table. An index that comprises a data structure may be created. The index can then be populated with data from the database table. When a request to modify the database table is received, the method may determine that the request to modify the database table relates to a portion of the database table corresponding to a portion of the index that has yet to be populated. An entry indicating the requested modification can be inserted into the portion of the index that has yet to be populated.
US09424294B2 Method for facet searching and search suggestions
Methods for faceted searching within clustered in-memory databases are disclosed. Faceted searching may be used to generate search suggestions. The faceted search engine may be able to use non-literal key algorithms for a partial prefix fuzzy matching and may include a feature disambiguation module. The disclosed search engine may be capable of processing large amounts of unstructured data in real time to generate search suggestions.
US09424292B2 Method of ranking and displaying certified content
A method of displaying and ranking certified and user-generated content from an individual user against content from other users. The user is prompted to input user-generated information and various related information and at least one visual recording is received and associated to create a user single trophy entry in a remote database. The user single trophy entry is ranked relative to other trophy entries in the remote database, and is displayed with a determined rank. Overlay data may be automatically received and associated based on the user-generated information and the related information. To create certified user single trophy entries a list of certification partners may be displayed and used.
US09424290B2 System and method for data validation
Systems and methods for validating data in a communication network environment include receiving a data transformation specification from a user. The data transformation specification is analyzed to determine data transformation rules which are indicative of a relationship between corresponding fields of the source repository and the target repository. Test cases and test scripts are generated based on the data transformation rules and the test cases and the test scripts are executed on the source repository and the target repository to validate the relationship between the corresponding fields of the source repository and the target repository. Thereafter, a log file, indicative of the outcome of the execution of the test cases and the test scripts, is generated.
US09424285B1 Content-based sampling for deduplication estimation
The techniques introduced herein provide for systems and methods for estimating the effectiveness of utilizing a data deduplication process. More specifically, a content-based sampling approach for data deduplication estimation is described in which a subset of the scanned fingerprints of a dataset are included in a content-based sample that is used to determine an accurate deduplication estimate for a dataset (or volume).
US09424283B2 Social files
Disclosed are systems, apparatus, methods, and computer readable media for creating and sharing social files in a feed system. In one embodiment, a request is received to perform an action related to a social file. The social file may provide access to a first document file within a social networking system. The first document file may be capable of being displayed on a display device. A determination may be made as to whether the requested action complies with a permission configuration record associated with the social file. The permission configuration record may identify one or more user accounts permitted to access the social file.
US09424279B2 Presenting image search results
A system and computer-implemented method is provided for organizing multiple user submitted results responsive to an image query. A plurality of content submissions may be received from a variety of submitting users, each content submission including an image and an associated label. An image query may provide an image of an object as a request to identify the object. In response to receiving the image query, one or more results of the plurality of content submissions may be identified. A similarity between the labels for each of the one or more results may be determined and used to group the one or more results. Grouped results may be ranked and sorted for accurate and concise presentation to a querying user.
US09424276B2 Efficient state change support for hierarchical data models in a virtualized system
Methods, systems and computer readable media for efficient state change support for hierarchical data models in a virtualized system are described. In some implementations, the method can include determining a system status including a system-level bit masked word having a plurality of bits, each bit corresponding to a status of a different hierarchical level of the system, and receiving a change notification. The method can also include querying an entity at a lower hierarchy level if a cascaded state change is identified for that entity. The method can further include continuing to query one or more entities in successively lower hierarchy levels so long as a cascaded state change is identified for a corresponding entity in a lower hierarchy level. The method can also include determining the current status for one or more entities having a changed status. Identifying a cascaded state change can include performing a logical exclusive OR operation on a previous status bit masked word and a current status bit masked word of an entity.
US09424274B2 Management of intermediate data spills during the shuffle phase of a map-reduce job
A system and a method for spill management during the shuffle phase of a map-reduce job performed in a distributed computer system on distributed files. A spilling protocol is provided for handling the spilling of intermediate data based on at least one popularity attribute of key-value pairs of the input data on which the map-reduce job is performed. The spilling protocol includes an assignment order to storage resources belonging to the computer system based on the at least one popularity attribute. The protocol can be deployed in computer systems with heterogeneous storage resources. Additionally, pointers or tags can be assigned to improve shuffle phase performance. The distributed file systems that are most suitable are ones usable by Hadoop, e.g., Hadoop Distributed File System (HDFS).
US09424270B1 System and method for managing media files
Systems and methods are presented which allow a user's device to accept media from a variety of sources, process those media items based on their characteristics, and deliver the captured media to a pre-established variety of diverse locations with minimal or no user interaction. These systems and methods can also make media items available to a plurality of internet web sites without actually creating and delivering copies of files. In one embodiment, the diverse locations can each have individual delivery protocols (for example, login and formats) and when a number of media are available at the user's device for delivery to storage locations the media can be delivered to pre-established locations with a single user command without regard to the individual location delivery requirements. In another embodiment, processing, delivery, and access to new media items is handled automatically based on pre-established criteria and analysis of the data and metadata of the media items themselves. While unobtrusive user feedback is displayed during media processing, no user attention or intervention is required as long as no changes to the default settings are desired.
US09424269B1 Systems and methods for deduplicating archive objects
A computer-implemented method for deduplicating archive objects may include (1) tagging, using an archiving service, archive objects to indicate data related to the archive objects, (2) assigning an archive object and an additional archive object to be processed by a deduplication engine, (3) determining a degree of overlap between the archive object and the additional archive object based on tags assigned to the archive object and the additional archive object by the archiving service, and (4) adjusting, using the deduplication engine, deduplication between the archive object and the additional archive object using the degree of overlap determined to exist between the archive object and the additional archive object based on the tags assigned by the archiving service. Various other methods, systems, and computer-readable media are also disclosed.
US09424266B2 Efficient file hash identifier computation
Described is maintaining cached hash values for files in association with state data for each file that represents the state of that file's contents at the time of hashing. For example, in a journaling file system, the state data may comprise the update sequence number of the file in the journal and a journal identifier for that journal instance. A request for a hash value for a file is processed by determining whether a cached hash value is maintained for that file. If so, and the associated maintained state data matches current state data for the file, the file contents are unchanged since the last hash computation, whereby the cached hash value is returned in response to the request. Otherwise, a new hash value is computed for the file and returned, and cached for future use. Multiple types of hashes may be cached for a given file.
US09424262B2 Computing system and data management method thereof
A data management method of a computing system includes dividing a storage device into a first area and a second area, storing data and nodes related to the data in the second area, and storing a node address table in the first area. The node address table includes node identifiers corresponding to the nodes and physical addresses corresponding to the node identifiers.
US09424261B2 Techniques to take clean database file snapshot in an online database
Techniques are described herein for making a clean file snapshot of a target file. The techniques may be applied to a single target file, to a set of target files, or to an entire database The techniques involve transitioning the target file through a series of states. During each state, particular actions are performed and/or prevented. In the final state of each approach, a clean file snapshot of the target file exists. Transitioning through the states, only one of which does not allow new changes to be made to the target file, allows the database to remain online and available to a greater extent than is possible with an approach that prevents database changes for the duration of the clean file snapshot creation operation.
US09424255B2 Server-assisted object recognition and tracking for mobile devices
Exemplary embodiments for performing server-assisted object recognition and tracking are disclosed herein. For example, in certain embodiments of the disclosed technology, one or more objects are efficiently recognized and tracked on a mobile device by using a remote server that can provide high capacity computing and storage resources. With the benefit of high-speed image processing on a remote server and high-bandwidth communication networks connecting the mobile device and the remote server, it is possible to identify an object and to track changes in the object's characteristics or location, so that a user experiences seamless, real-time tracking.
US09424249B1 Encoding text units
Disclosed are various embodiments for a text module that receives, in at least one computing device, an encoded text block, the encoded text block comprising user generated text. A set of signals is identified in the encoded text block, each signal specifying a respective text unit, each text unit corresponding to a respective series of characters in the user generated text. The text module may render the user generated text and each series of characters in the user generated text. A text selection of a subset of one of the series of characters is initially prevented. The text module receives a selection of the text unit corresponding to the one of the series of characters, the selection of the text unit triggering a text selection of one of the series of characters.
US09424248B2 Preventing frustration in online chat communication
Monitoring an internet chat in which a text transcript is generated by at least two chat participants, by: (i) performing a simple check on the text transcript for existence of a potential frustration precondition; and (ii) on condition that a frustration precondition is found, performing text analytics type analysis on the text transcript to determine whether potential frustration is evidenced by the text transcript. If it is determined that potential frustration is evidenced by the chat transcript then responsive action is taken to prevent and/or stem the frustration.
US09424246B2 System and method for inputting text into electronic devices
Systems comprising a user interface configured to receive text input by a user and a text prediction engine configured to receive the input text and generate text predictions. The text prediction engine may comprise a general language model and a context-specific language model. The text prediction engine is configured to generate text predictions from the general language model and the context-specific language model and combine the text predictions. The text prediction engine may comprise first and second language models and a first context-specific weighting factor associated with the first language model. The text prediction engine is configured to generate text predictions using the first and second language models, generate weighted probabilities of the text predictions from the first language model using the first context-specific weighting factor; and generate final text predictions from the weighted predictions generated from the first language model and the predictions generated by the second language model.
US09424237B2 Flexible analytics-driven webpage design and optimization
In an approach for selecting a version of a webpage to present to a user, a processor receives a request to access a webpage from a device, wherein the webpage includes a plurality of versions of the webpage. A processor receives information about the device. A processor determines a version of the webpage to present, based on the information about the device and a predefined goal associated with the webpage. A processor causes the version of the webpage to be presented.
US09424233B2 Method of and system for inferring user intent in search input in a conversational interaction system
A method of inferring user intent in search input in a conversational interaction system is disclosed. A method of inferring user intent in a search input includes providing a user preference signature that describes preferences of the user, receiving search input from the user intended by the user to identify at least one desired item, and determining that a portion of the search input contains an ambiguous identifier. The ambiguous identifier is intended by the user to identify, at least in part, a desired item. The method further includes inferring a meaning for the ambiguous identifier based on matching portions of the search input to the preferences of the user described by the user preference signature and selecting items from a set of content items based on comparing the search input and the inferred meaning of the ambiguous identifier with metadata associated with the content items.
US09424231B2 Image reconstruction method and system
A method and system for producing a scalar image from a derivative field and a vector image is disclosed. A function class c is selected, where all members of the class c are functions which map each vector of the vector image to a unique scalar value. A function f is selected from the class c which maps the vector image to a scalar image, the derivative of which is closest to the derivative field. The scalar image is generated from the vector image by using f to calculate each scalar value in the scalar image from a corresponding vector in the vector image.
US09424229B2 Parallel torus network interconnect
A system and method for optimizing a flow of data traffic are provided. A plurality of tori are connected in a parallel tori interconnect. Each torus includes a plurality of nodes. The nodes in the torus are interconnected using links. A host in the network is connected to a subset of nodes where nodes in the subset are associated with different tori. The host transmits the packets to the parallel tori interconnect by selecting a node the subset of nodes. The packets are transmitted using links between from the node to the plurality of nodes in the torus, but not between the plurality of tori.
US09424227B2 Providing byte enables for peer-to-peer data transfer within a computing environment
Non-contiguous or tiled payload data are efficiently transferred between peers over a fabric. Specifically, a client transfers a byte enable message to a peer device via a mailbox mechanism, where the byte enable message specifies which bytes of the payload data being transferred via the data packet are to be written to the frame buffer on the peer device and which bytes are not to be written. The client transfers the non-contiguous or tiled payload payload data to the peer device. Upon receiving the payload data, the peer device writes bytes from the payload data into the target frame buffer for only those bytes enabled via the byte enable message. One advantage of the present invention is that non-contiguous or tiled data are transferred over a fabric with improved efficiency.
US09424226B1 Method and system for signal equalization in communication between computing devices
Method and system for performing an equalization process between a remote PCI (Peripheral Component Interface)-Express device and a local PCI-Express device are provided. The use of a forced coefficient in a third phase of the equalization process is enabled. When the remote PCI-Express has made a preset request, then the local PCI-Express device sends the preset request back to the remote PCI-Express device with the forced coefficient.
US09424220B2 Method and apparatus for setting working mode of multi-processor system
A method for setting a working mode of a multi-processor system includes: detecting, after a current board is inserted into a slot of the backplane, whether an associated board exists on the backplane; detecting, if the associated board exists, whether the associated board is in an independent working state; powering on the current board according to a slave working mode if the associated board is not in an independent working state, so as to work coordinately with the associated board; detecting, within a predetermined detection time if the associated board does not exist, whether a board is inserted into another slot of the backplane except the slot of the master board; and powering on the current board according to a master working mode if it is detected that the board is inserted, so as to work coordinately with the board in the other slot.
US09424216B2 Ascertaining configuration of a virtual adapter in a computing environment
A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The virtual adapter is for use by a guest of the host system in performing data input and output. The activating activates the virtual adapter absent involvement of the guest. Based on activating the virtual adapter, the control component obtains configuration information of the activated virtual adapter from the physical adapter, the configuration information generated based on the activating. The control component ascertains a configuration of the activated virtual adapter based on the obtained configuration information.
US09424212B2 Operating system-managed interrupt steering in multiprocessor systems
An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. On a regular basis, these assignments can be changed given current operating conditions of the system.
US09424211B2 Providing multiple virtual device controllers by redirecting an interrupt from a physical device controller
Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.
US09424205B2 System and method for SATA virtualization and domain protection
A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual guest devices or virtual machines (VMs). The lightweight SATA virtualization handler can also perform the scheduling or queuing of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the coprocessor and has commands from one or more VMs. Guest devices or guest operating systems can build associated AHCI data structures in memory, which may be on-chip memory or DDR memory.
US09424203B2 Storing look-up table indexes in a return stack buffer
A return stack buffers (RSB) is modified to store index values instead of addresses. When a function is called, the address following the function call is stored in a look-up table and the index at which the address is stored is pushed to the RSB. When a function returns, an index is popped from the RSB and used to identify an address in the look-up table. In another embodiment, the RSB is modified such that each entry comprises two or more address slots. When a function is called, the address following the function call is pushed to the RSB and stored in a selected one of the address slots in a top entry in the RSB. One or more pointer bits within the entry are set to indicate which slot the address was stored in.
US09424202B2 Database search facility
A database cache manager for controlling a composition of a plurality of cache entries in a data cache is described. Each cache entry is a result of a query carried out on a database of data records, the cache manager being arranged to remove cache entries from the cache based on a cost of removal factor which is comprised of a time cost, the time cost being calculated from the amount of time taken to obtain a query result to which that cache entry is related.
US09424198B2 Method, system and apparatus including logic to manage multiple memories as a unified exclusive memory
A processor includes at least one execution unit, a near memory, and memory management logic to manage the near memory and a far memory external to the processor as a unified exclusive memory. Each of a plurality of data blocks may be exclusively stored in either the far memory or the near memory. The unified exclusive memory space may be divided into a plurality of sets and a plurality of ways. In response to a request for a first block stored in the far memory, the memory management logic may move the first block from the far memory to the near memory, and may move a second block from the near memory to the far memory. A tag buffer may store tags associated with blocks being moved between the near memory and the far memory. Fill and drain buffers may also be used. Other implementations are described and claimed.
US09424193B2 Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
US09424192B1 Private memory table for reduced memory coherence traffic
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.
US09424191B2 Scalable coherence for multi-core processors
An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.
US09424182B2 Adaptive memory system for enhancing the performance of an external computing device
An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.
US09424181B2 Address mapping for solid state devices
Technologies are generally described for systems, devices and methods relating to swapping bits in memory addresses in solid state devices. In some examples, a bit swap module may receive a first memory address. The first memory address may include a first bit value at a first position of the first memory address and/or a second bit value at a second position of the first memory address. The bit swap module may swap the first bit value with the second bit value to produce a second memory address. The second memory address may be sent to a memory controller. In some examples, the first memory address may relate to a first package of memory and the second memory address may relate to a second package of memory.
US09424178B2 Optimized flash memory without dedicated parity area and with reduced array size
A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.
US09424170B2 Second failure data capture in co-operating multi-image systems
A method captures diagnostic trace information in a computer system having a plurality of software images. Information is received that is associated with a first failure in a first one of the plurality of software images. The received information is distributed to others of the plurality of software images. Further information is captured that is associated with a second failure in another one of the plurality of software images. The information associated with a first failure in a first one of said plurality of software images is combined with the information associated with a second failure in another of said plurality of software images, and the combined information is analyzed in order to determine a cause of the first failure.
US09424169B1 Method of integrating heterogeneous test automation frameworks
Techniques for testing heterogeneous software components are described herein. In response to a test procedure, a main test framework (MTF) identifies one or more test cases associated the sequence of testing operations. The MTF delegates at least one testing operation to a first subordinated test framework (STF) by invoking an MTF-to-STF (MTF/STF) adaptor, where the first STF corresponds to a test operation of a specific functionality. The MTF/STF adaptor launches the first STF by passing a first set of parameters received from the MTF to a first format compatible with the first STF, where the first STF is configured to perform a first sequence of testing operations for a first functionality. In response to a first test result from the first STF, the MTF/STF adaptor converts the first test result in second format compatible with the MTF and returns the converted first test result back to the MTF.
US09424168B2 System and method for automatic generation of software test
Disclosed herein is a system and method for automatically generating a test for a design process. The present system and method compares a keyword list associated with a design process and keyword lists associated with kernels and/or algorithms, temporarily associating matching kernels and/or algorithms with the design process, testing the kernels and/or algorithms with an input and designates the best output as the expected output.
US09424165B2 Debugging processor hang situations using an external pin
Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.
US09424163B2 Exception and debugging behaviors for JavaScript debugging using just my code
Just My Code debugging allows developers to work on problems within their own code without noise from libraries, plugins and other unrelated code. Typical debugger behaviors may be modified based upon the identification or characterization of JavaScript code as “My Code,” “Library Code,” or “Unrelated Code.” The debugger behaviors that may be modified depending upon the code's characterization include, for example, first-chance exception handling, unhandled exception handling, the behavior of the debugger at explicit user breakpoints, the behavior when a user directs the debugger to break upon the next statement, and the behavior of the debugger when the user executes a stepping gesture. The debugger's visualizes core elements of the program state, such as the call stack, depending upon the identification or characterization of the code.
US09424161B2 Trace capture device with common structure and related trace capture method
A trace capture device includes a processing system, a trace capture control unit and a bus unit. The processing system includes at least one function block arranged to generate first data, second data, and correlation information corresponding to the first data. The trace capture control unit is arranged to receive the first data and correlation information corresponding to the first data from the processing system, and generate third data according to the first data and the correlation information. The bus unit is coupled to the processing system, the trace capture control unit and a data link interface. The bus unit is arranged to use the data link interface to transmit information derived from the second data in a first mode, and reuse the first data link interface to transmit information derived from the third data in a second mode.
US09424159B2 Performance measurement of hardware accelerators
Performance measurement of hardware accelerators, where one or more computer processors are operably coupled to at least one hardware accelerator, and a computer memory is operatively coupled to the one or more computer processors, including operating by the one or more processors the accelerator at saturation, submitting data processing tasks by the processors to the accelerator at a rate that saturates the data processing resources of the accelerator, causing the accelerator to decline at least some of the submitted tasks; and while the accelerator is operating at saturation, measuring by the processors accelerator performance according to a period of time during which the accelerator accepts a plurality of submitted tasks.
US09424156B2 Identifying a potential failure event for a data storage device
A storage access request is received. A data storage device is identified as being targeted by the storage access request. The data storage device is located in an enclosure that includes two or more data storage devices, including the data storage device. An access operation is performed in accordance with the storage access request on the data storage device. A record of a fault sensor assigned to the data storage device is updated based at least partly on monitoring the performing of the access operation.
US09424151B2 Disk failure recovery for virtual disk with policies
An administrator provisions a virtual disk in a remote storage platform and defines policies for that virtual disk. A virtual machine writes to and reads from the storage platform using any storage protocol. Virtual disk data within a failed storage pool is migrated to different storage pools while still respecting the policies of each virtual disk. Snapshot and revert commands are given for a virtual disk at a particular point in time and overhead is minimal. A virtual disk is cloned utilizing snapshot information and no data need be copied. Any number of Zookeeper clusters are executing in a coordinated fashion within the storage platform, thus increasing overall throughput. A timestamp is generated that guarantees a monotonically increasing counter, even upon a crash of a virtual machine. Any virtual disk has a “hybrid cloud aware” policy in which one replica of the virtual disk is stored in a public cloud.
US09424148B2 Automatic failover in modular chassis systems
Systems and methods for automatic failover in modular chassis systems. In some embodiments, a modular chassis includes a chassis management controller and a plurality of server blades. A first of the plurality of server blades may be configured to detect an internal fault to and to transmit a corresponding alert message to the chassis management controller via a midplane connection. Moreover, the chassis management controller may be configured to initiate a migration procedure to transfer one or more workloads from the first server blade to a second of the plurality of server blades.
US09424147B2 System and method for supporting memory allocation control with push-back in a distributed data grid
A system and method can support memory allocation control in a distributed data grid. The system can designate a process, such as a logical process, to handle a request that is received from a client for storing data in a data storage using an elastic data structure with one or more journal files. Then, a resource manager associated with the data storage can suspend the process when the elastic data structure appears to be logically full. Furthermore, the resource manager can resume the suspended process associated with the client, after the resource manager has reclaimed sufficient memory from the elastic data structure.
US09424145B2 Ensuring the same completion status for transactions after recovery in a synchronous replication environment
Disclosed in some examples is a method, the method including detecting that an RDMS is recovering from a failure; sending a request for a last committed transaction on a replication component to the replication component; receiving, from the replication component, the last committed transaction which identifies a transaction that was the last committed transaction at a replication component at a time of RDMS failure; determining that a transaction log on the RDMS includes a transaction that had not yet been replicated at the time of RDMS failure which was committed on the transaction log subsequent to the last committed transaction received from the replication component; and based on that determination rolling back the transaction that had not yet been replicated at the time of RDMS failure.
US09424144B2 Virtual machine migration to minimize packet loss in virtualized network
Methods and apparatus are provided for controlling live migration of a virtual machine from a first host to a second host in a data center. A virtual machine manager may distribute to at least one host in a virtual network an updated mapping policy that maps a customer address of the virtual machine to a provider address of the migrated virtual machine. The updated mapping policy enables hosts in the virtual network to communicate with the migrated virtual machine. The updated mapping policy can be a shadow policy. The shadow policy is transmitted to hosts in the virtual network by the virtual machine manager before live migration of the virtual machine completes and is maintained by recipient hosts in an inactive state until triggered. The virtual machine manager notifies hosts in the virtual network to activate the shadow policy when live migration completes.
US09424140B1 Providing data volume recovery access in a distributed data store to multiple recovery agents
A distributed data store may provide volume recovery access to multiple recovery agents. A data volume may be maintained for a storage client at the distributed data store. Write access to the data volume may be granted according to a single writer consistency scheme. When a recovery event is detected for the data volume, the data volume may be made available to multiple recovery agents that may perform respective recovery operations. Upon first completion of a recovery operation for the data volume, granting access to the data volume according to the single writer consistency scheme may be resumed. In some embodiments, the distributed data store may be a log-structured data store.
US09424138B2 Checkpointing a computer hardware architecture state using a stack or queue
Various embodiments relating to saving and recovering a hardware architecture state are provided. In one embodiment, during a first mode of operation, entries in a first portion of a random-access memory (RAM) are manipulated. A current version of less than all of the entries of the first portion is saved to a checkpointed version in response to a checkpoint event that triggers operation in a second mode of operation. During the second mode of operation, entries in a second portion of the RAM are manipulated. The checkpointed version of less than all of the entries of the first portion is recovered as the current version in response to a restore event that triggers resumption of operation in the first mode.
US09424136B1 Systems and methods for creating optimized synthetic backup images
A computer-implemented method for creating optimized synthetic backup images may include (1) transferring a backup image that represents a virtual machine at a specific point in time to a server that stores the backup image, (2) identifying a subsequent backup image that represents at least a portion of the virtual machine at a subsequent point in time, (3) creating a data stream that includes (i) at least one changed data block captured in the subsequent backup image and (ii) at least one reference that identifies where at least one unchanged data block is located within the backup image stored on the server, and then (4) transferring the data stream to the server to enable the server to create an optimized synthetic backup image of the virtual machine. Various other methods, systems, and computer-readable media are also disclosed.
US09424133B2 Providing an eventually-consistent snapshot of nodes in a storage network
Systems and methods which provide for obtaining snapshots of one or more nodes, while having minimal impact on performance and throughput of the storage network are provided. Embodiments may involve a method of obtaining snapshots of individual node data within a clustered storage network having a plurality of nodes without requiring quiescing of every node. The snapshots may be obtained in a rolling fashion, e.g., moving across the individual nodes of a cluster either sequentially or non-sequentially. In other embodiments snapshots may be obtained in an asynchronous manner. The obtained snapshots then collectively define an eventually consistent view of the entire system. Such a view may be utilized to provide for mirroring functionality, e.g. to provide for DR and/or HA capabilities.
US09424127B2 Charger detection and optimization prior to host control
Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.
US09424126B2 Memory controller
According to one embodiment, a memory controller according to the embodiments includes an encoder that sequentially calculates parity based on data; a parity buffer that stores completed parity and intermediate parity based on data less than a predetermined size; a write processing unit that writes data and completed parity on a non-volatile memory; a decoder; and a controller that performs a decoding process based on the data read from the non-volatile memory and the intermediate parity in the parity buffer, when receiving a read request to inputted data in a stage in which the a number of inputted data to the encoder is less than the predetermined size.
US09424122B2 Digital information transfer system including fault protection
A digital information transfer system includes an electronic driver unit in electrical communication with a power supply to receive an input voltage. The driver converts the input data into output data based on a digital information transfer system protocol. An electronic fault detection is configured to determine a fault condition of the at least one output transmission line based on a comparison between a voltage level of the at least one output transmission line and the input voltage. An electronic fault protection module is in electrical communication with each of the driver unit, the at least one output transmission line and the fault detection module. The electronic fault protection module is configured to selectively disconnect the driver unit from the at least one output transmission line in response to detecting the fault condition.
US09424116B2 Program development in a distributed server environment
According to one embodiment of the present invention, a system for processing a computer program for a distributed server environment executes the computer program in the distributed server environment in accordance with a configuration for the computer program. The computer program is generated within a development environment. The configuration indicates a type of server environment and is associated with one or more data sets for processing by the computer program. The system monitors execution of the computer program within the distributed server environment and provides a program status to the development environment. The system displays results produced by the computer program within the distributed server environment via the development environment. Embodiments of the present invention further include a method and computer program product for processing a computer program in substantially the same manners described above.
US09424114B2 Input/output (I/O) processing via a page fault doorbell mechanism
Systems and methods are disclosed for processing an input/output (I/O) operation. An example system includes a kernel interface that receives a notification of a page fault. The page fault is responsive to an application attempting to perform an operation on a memory region that is set to a first access mode. When the memory region is set to the first access mode, the application does not have permission to perform the operation on the memory region. The system also includes a handler that responsive to the notification (i) sets the memory region to a second access mode and (ii) spawns a kernel thread to drain data from the memory region. When the memory region is set to the second access mode, the application has permission to perform the operation on the memory region. The system further includes an I/O module that stores the data in the memory region for processing.
US09424112B1 Execution plan generator and execution engine for interfacing with application programming interfaces
Embodiments for a method of interfacing with a remote application programming interface (API) by defining an execution plan using an interface definition language and a dependency configuration file to generate a constrained directed graph of hierarchically dependent functions of the API, and executing the execution plan using an executing engine that traverses the graph to call the API functions in a defined order and convert data output by a parent function call to input required by a child function call until a terminal vertex is reached that results in directing the resulting in an action such as data to persist and/or affecting the state of a system.
US09424107B1 Content enhancement techniques
Techniques for enhancing content being rendered on an electronic device are described herein. In some instances, the techniques include monitoring interactions between a user and a content item that the user consumes on an electronic device. The content items may include electronic books, songs, videos, documents, or the like. In response to detecting an interaction between the user and the content item, the techniques may publish an event indicative of the interaction to an application platform that hosts one or more applications. The applications may be designed to enhance the content that the user consumes in one or more specified ways.
US09424103B2 Adaptive lock for a computing system having multiple runtime environments and multiple processing units
A method for operating a lock in a computing system having plural processing units and running under multiple runtime environments is provided. When a requester thread attempts to acquire the lock while the lock is held by a holder thread, determine whether the holder thread is suspendable or non-suspendable. If the holder thread is non-suspendable, put the requester thread in a spin state regardless of whether the requester thread is suspendable or non-suspendable; otherwise determines whether the requester thread is suspendable or non-suspendable unless the requester thread quits acquiring the lock. If the requester thread is non-suspendable, arrange the requester thread to attempt acquiring the lock again; otherwise add the requester thread to a wait queue as an additional suspended thread. Suspended threads stored in the wait queue are allowable to be resumed later for lock acquisition. The method is applicable for the computing system with a multicore processor.
US09424101B2 Method and apparatus for synchronous processing based on multi-core system
Embodiments of the present invention relate to the field of communications network technologies and provide a method and an apparatus for synchronization processing based on a multi-core system, which can improve efficiency in system scheduling and consume fewer resources. According to the solutions provided in the present invention, an initialization setting is sent by any processing device in a first group of processing devices that synchronously process a same current task and initialization is performed; then a notification message sent by any processing device in the first group of processing devices is received and 1 is subtracted from a value of a counting semaphore; and when the value of the counting semaphore is 0, a control message is sent to a second group of processing devices through a message sending interface. The solutions provided in the present invention are applicable to processing synchronization and communication between multiple modules.
US09424100B2 Monitoring and validating the coordinated execution of sequenced tasks by an electronic card with two processors synchronized to different clocks
A method for monitoring the coordinated execution of sequenced tasks by an electronic device including a main electronic card including at least one main processor synchronized to a main clock and at least one auxiliary electronic card including at least one auxiliary processor synchronized to an auxiliary clock, includes emitting by the main processor of a coordination marker to the auxiliary processor at the start of each main time period; emitting by the auxiliary processor of a response word formed on the basis of the last coordination marker received to the main processor at the end of each auxiliary time period; validating by the main processor of the response word received with respect to the first coordination marker emitted; and signaling by the main processor if the response word received is not valid so as to signal a defect of coordination of the auxiliary processor.
US09424099B2 Method and system for synchronization of workitems with divergent control flow
Disclosed methods, systems, and computer program products embodiments include synchronizing a group of workitems on a processor by storing a respective program counter associated with each of the workitems, selecting at least one first workitem from the group for execution, and executing the selected at least one first workitem on the processor. The selecting is based upon the respective stored program counter associated with the at least one first workitem.
US09424097B1 Dynamically managing workload placements in virtualized environments based on current user globalization customization requests
Multiple workloads from multiple users requesting access to at least one virtualized application are received, wherein each of the workloads is specified with one or more separate globalization characteristics from among multiple globalization characteristics. To dynamically manage workload placement, each of the workloads is dynamically categorized separately for placement in one or more particular virtualized environments from among multiple virtualized environments based on the one or more separate globalization characteristics of each of the workloads, wherein each virtualized environment comprises the at least one virtualized application configured for a separate selection of globalization services from among multiple globalization services for handling a separate selection of the one or more separate globalization characteristics.
US09424096B2 Task allocation in a computer network
Server computers send requests over a network for an allocation of server tasks and processing tasks, the processing task requests having an associated expiration time. The plurality of server computers process received server tasks provided to the server computers in response to the requests, and process processing tasks within the expiration time in response to the requests for processing tasks. The server computers perform the allocated processing tasks only if there are no pending server tasks.
US09424095B2 Method and system for controlling the processing of requests for web resources
A system, method and computer program product for controlling the processing of requests for web page resources from a web server are provided. The method comprises monitoring a run level of the web server; receiving requests for one or more web page resources; determining a priority of received requests based on a run level value associated with a requested resource and the run level of the web server; and processing the requests by the web server according to the determined priority. In dependence on the current load on the web server, requests for low priority resources can be given a low processing priority, with processing capability focussed on requests for higher priority web resources.
US09424092B2 Heterogeneous thread scheduling
Heterogeneous thread scheduling techniques are described in which a processing workload is distributed to heterogeneous processing cores of a processing system. The heterogeneous thread scheduling may be implemented based upon a combination of periodic assessments of system-wide power management considerations used to control states of the processing cores and higher frequency thread-by-thread placement decisions that are made in accordance with thread specific policies. In one or more implementations, a system workload context is periodically analyzed for a processing system having heterogeneous cores including power efficient cores and performance oriented cores. Based on the periodic analysis, cores states are set for some of the heterogeneous cores to control activation of the power efficient cores and performance oriented cores for thread scheduling. Then, individual threads are scheduled in dependence upon the core states to allocate the individual threads between active cores of the heterogeneous cores on a per-thread basis.
US09424089B2 Hardware acceleration of web applications
In a first embodiment of the present invention, a method for enabling hardware acceleration of web applications is provided, comprising: parsing a web page using a scripting engine, wherein the web page necessitates running a web application; accessing one or more Application Program Interfaces (APIs) that provide parallelization, and distribute tasks of the web application among multiple cores of a multi-core central processing unit (CPU) or graphical processing unit (GPU), wherein the accessing uses a compute context class that, when instantiated, creates a compute context object that acts as a bridge between the scripting engine and the one or more APIs; and creating one or more kernels to operate on the multiple cores.
US09424082B2 Application startup page fault management in a hardware multithreading environment
A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks to a hardware thread 0 across plural processing cores in a simultaneous multithreading environment to provide more rapid processing of processor bound page faults. I/O bound page faults are flagged to associated with predetermined cache locations to improve data and text first reference page-in I/O response.
US09424081B2 Managing callback operations in emulated environments
Examples of the disclosure enable callback operations, such as interrupts, Asynchronous Procedure Calls (APCs), and Deferred Procedure Calls (DPCs), to be efficiently managed. In some examples, an emulated thread includes a request for a callback operation. When the request is detected, the emulated thread and/or a cooperating thread associated with the callback operation is executed based on an execution mode associated with the callback operation. Examples of the disclosure manage callback operations while efficiently managing system resources, including processor load, by providing at least one cooperating thread that consumes little or no processing power until the callback operation is ready to be executed.
US09424080B2 Systems and methods for utilizing futures for constructing scalable shared data structures
A multithreaded application that includes operations on a shared data structure may exploit futures to improve performance. For each operation that targets the shared data structure, a thread of the application may create a future and store it in a thread-local list of futures (under weak or medium futures linearizability policies) or in a shared queue of futures (under strong futures linearizability policies). Prior to a thread evaluating a future, type-specific optimizations may be performed on the list or queue of pending futures. For example, futures may be sorted temporally or by key, or multiple operations indicated in the futures may be combined or eliminated. During an evaluation of a future, a thread may compute the results of the operations indicated in one or more other futures. The order in which operations take effect and the optimization operations performed may be dependent on the futures linearizability policy.
US09424079B2 Iteration support in a heterogeneous dataflow engine
Various embodiments provide techniques and constructs to improve execution speed of distributed iterative computation using heterogeneous specialized resources including, for example, processors and accelerators. Iteration over an arbitrary sub-graph without loop unrolling including for algorithms with data-dependent loop termination and large iteration counts, including as a result of nested iteration, are supported in a resource-efficient manner without adding vertices to a dataflow graph to represent iteration constructs. Instead, some or all of the existing vertices within the sub-graph that is to be iterated upon based on having additional and/or modified ports and channels associated with them.
US09424078B2 Managing high performance computing resources using job preemption
The preemption of running jobs by other running or queued jobs in a system that has processing resources. The system has running jobs, and queued jobs that are awaiting processing by the system. In a scheduling operation, preemptor jobs are identified, the preemptor jobs being jobs that are candidates for preempting one or more of the running jobs. The preemptor jobs include queued jobs, as well as running jobs that are capable of using more processing resource of the system. One of the other running jobs is preempted to free processing resources for the running job that was identified as a preemptor job. Accordingly, not only may queued jobs preempt running jobs, but currently running jobs may preempt other currently running jobs.
US09424073B1 Transaction handling between soft logic and hard logic components of a memory controller
Techniques and mechanisms handle transactions between various components of a memory controller. For example, a memory controller may include a component implemented in configurable logic and another component implemented in hard logic.
US09424069B2 Communication terminal and communication control method
A communication terminal has communication circuit, a processor and a storing module operable to store a plurality of application programs. The terminal includes comprising: a table that a plurality of timer times are registered, a notifying module operable to notify expiration when reaching at a timer time that is registered in the table, an executing module operable to execute at least two or more application programs when the expiration is notified by the notifying module, and an enabling module operable to enable the communication circuit when executing the application program by the executing module. Communication is performed by the at least two or more application programs while the communication circuit is being enabled.
US09424068B2 Automatic batching of GUI-based tasks
Described herein are techniques for automatically batching GUI-based (Graphical User Interface) tasks. The described techniques include automatically determining whether a user is performing batchable tasks in a GUI-based environment. Once detected, the described techniques include predicting the next tasks of a batch based upon those detected batchable tasks. With the described techniques, the user may be asked to verify and/or correct the predicted next tasks. Furthermore, the described techniques may include performing a batch and doing so without user interaction.
US09424067B2 Managing virtual machine instances utilizing an offload device
Generally described, the present application relates to systems and methods for the managing virtual machines instances using a physical computing device and an offload device. The offload device can be a separate computing device that includes computing resources (e.g., processor and memory) separate from the computing resources of the physical computing device. The offload device can be connected to the physical computing device via a interconnect interface. The interconnect interface can be a high speed, high throughput, low latency interface such as a Peripheral Component Interconnect Express (PCIe) interface. The offload device can be used to offload virtualization and processing of virtual components from the physical computing device, thereby increasing the computing resources available to the virtual machine instances.
US09424065B2 Methods and apparatus to scale application deployments in cloud computing environments using virtual machine pools
Methods and apparatus are disclosed to scale application deployments in cloud computing environments using virtual machine pools. An example method disclosed herein includes displaying a user-selectable control to specify whether the application is to be scaled in accordance with a scaling policy, based on selection of the user-selectable control, storing, in a blueprint of the application, an indication of whether the application is to be scaled in accordance with the scaling policy, based on the indication in the blueprint, preparing a virtual machine pool in the computing environment, the virtual machine pool including a virtual machine provisioned for use in a scaling operation, in response to a request to scale the application deployed in a deployment environment, determining whether configuration information satisfies a scaling requirement, and based on the determination, performing the scaling operation in accordance with the request to scale by transferring the virtual machine to the deployment environment.
US09424061B2 Bandwidth-efficient virtual machine image delivery
A mechanism is provided for bandwidth-efficient virtual machine image delivery. Responsive to a request to generate a virtual machine (VM) in a node using an existing virtual machine image (VMI) file, a set of file chunks that constitute the VMI file is identified. The set of file chunks are retrieved from within a set of distributed nodes by establishing an optimized plan for retrieving the set of file chunks in a bandwidth-efficient manner. Responsive to retrieving the set of file chunks from within the distributed nodes, the set of file chunks are reassembled into the VMI file for generation of the VM.
US09424060B2 Tiered eviction of instances of executing processes
In one example embodiment, an instance of a virtual machine to evict may be identified. A determination may be made within a predetermined range of probabilities, that processing on the identified instance of the virtual machine will resume within a predetermined range of time. Thus, the identified instance of the virtual machine may be softly evicted by allocating processing resources away from the identified instance of the virtual machine, receiving an instruction to resume the processing on the identified instance of the virtual machine, and restoring the processing on the identified instance of the virtual machine.
US09424059B1 System and methods for implementing quality of service in a networked virtualization environment for storage management
A method for implementing quality of service (QoS) for network communications sharing a network in a networked virtualization environment for storage management, includes receiving a network communication from a controller VM, identifying whether the network communication is a data communication type issued by a user VM or a control communication type issued by the controller VM, applying a set of rules to the network communication based on its communication type, and placing the network communication in a prioritization class queue based on a result of applying the set of rules to the network communication.
US09424055B2 Multi-function instruction that determines whether functions are installed on a system
A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.
US09424054B2 Driver file conversion system
A method for creating an offline script format driver file from an INF file includes replacing variables with associated value data. Version data and a unique identifier are captured and stored. Disk identification data is retrieved and combined with data that references the disk identification data in order to create and store a list of disk names and files within those disk names. A list is created of all possible models sections from value data included in a manufacturer value name to determine which models sections support which operating systems. Information that describes which models section is compatible with which operation system is created and stored. For DDInstall sections that include device driver installation details, sections directives that include registry actions or file actions are processed. The method provides an offline script format driver file that is operable to provide for offline driver installation in an information handling system (IHS).
US09424050B2 Parallelization and instrumentation in a producer graph oriented programming framework
Embodiments of parallelization and/or instrumentation in a producer graph oriented programming framework have been presented. In one embodiment, a request to run an application program is received, wherein object-oriented source code of the application program includes methods and producer dependency declarations, wherein the producer dependency declaration for a given method identifies a set of zero or more producers with outputs that are an input to the given method, wherein a producer is at least an instance and a method associated with that instance. Further, execution of the application program may be parallelized based on dependency between producers of the application program using the runtime. In some embodiments, the application program is instrumented using the runtime.
US09424049B2 Data protection for opaque data structures
Methods, media and systems that use an encoded opaque pointer in an API between a client process and a library process. An encoded opaque pointer, in one embodiment, can be received by the library process from the client process, and the library process can decode the opaque pointer to obtain an address in memory containing a data structure pointed to by the opaque pointer. The library process can operate on the data structure to create a revised or processed data structure, stored in the same or different address in heap memory or stack memory, and the library process can encode and return a new opaque pointer, for the processed data structure, to the client process.
US09424043B1 Forward-flow selection
Systems and methods for enhancing performance of programs implemented on an integrated circuit (IC) are provided. A forward-flow selector may determine a common branch for adding a data set to and removing a data set from. By selecting a common branch for adding and removing a data set, there will be a pipeline stage for data flowing into the branch. Accordingly, the embodiments described herein enhance throughput by increasing the number of datasets that may enter a branched pipeline without stalling.
US09424042B2 System, apparatus and method for translating vector instructions
Vector translation instructions are used to demarcate the beginning and the end of a code region to be translated. The code region includes a first set of vector instructions defined in an instruction set of a source processor. A processor receives the vector translation instructions and the demarcated code region, and translates the code region into translated code. The translated code includes a second set of vector instructions defined in an instruction set of a target processor. The translated code is executed by the target processor to produce a result value, the result value being the same as an original result value produced by the source processor executing the code region. The target processor stores the result value at a location that is not a vector register, the location being the same as an original location used by the source processor to store the original result value.
US09424041B2 Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions
A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a source of the nested dependent instruction expire and a producer instruction speculatively waking up the dependent instruction is canceled.
US09424040B2 LSI and LSI manufacturing method
An LSI includes an address decoder in which combinations of IP cores and control registers simultaneously accessed according to an operation mode signal are set in advance, so that the plurality of control registers can be accessed with a single system address signal. Therefore, it is unnecessary that the CPU is provided with selection signals whose number is equal to that of the combinations of the control registers. This reduces coding work for operating CPU, reducing work in developing a program of the CPU.
US09424037B2 Instructions and functions for evaluating program defined conditions
A compare instruction of an instruction set architecture (ISA), when executed tests one or more operands for an instruction defined condition. The result of the test is stored as an operand, with leading zeros, in a general register of the ISA. The general register is identified (explicitly or implicitly) by the compare instruction. Thus, the result of the test can be manipulated by standard register operations of the computer system. In a superscalar processor, no special “condition code” renaming is required, as the standard register renaming takes care of out-of-order processing of the conditions.
US09424034B2 Multiple register memory access instructions, processors, methods, and systems
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
US09424032B2 List vector processing apparatus, list vector processing method, storage medium, compiler, and information processing apparatus
Disclosed is a list vector processing apparatus (LVPA) or the like which can process the indirect reference at a high speed.The LVPA includes: a gather processing unit processing a first gather instruction to store a value of a storage area accessed by only a self information processing apparatus (SelfIPA) in a plurality of information processing apparatuses according to a list vector storing an address representing a storage area read from a storage apparatus into a register, and a process of generating reference access information indicating whether being a storage area accessed by both of the SelfIPA and another information processing apparatus; a communication unit for related information; an access information operating unit to calculate an area accessed by the information processing apparatus; and a scatter processing unit processing a first scatter instruction to store a value stored in the register into the storage area accessed by only the SelfIPA.
US09424027B2 Message management system for information transfer within a multitasking system
This invention bridges the gap between bare-block messaging for I/O and exchange messaging for inter-task communication by providing a message make service to make exchange messages from bare-block messages during input and a message unmake service to do the opposite during output. This invention also introduces new capabilities for message broadcasting by using broadcast message exchanges and message multicasting and distributed message assembly by using proxy messages.
US09424026B2 Visualizations of inter-entity calls
The disclosure generally describes computer-implemented methods, software, and systems, including methods for generating visualizations. On a client side, a user request is received for an inter-entity call visualization. Code analysis data is accessed. A visualization model is built. The visualization is shown. User inputs are received for interacting with the visualization. The visualization is updated based on the received user inputs. On a server side, a request is received for code analysis data. The requested data collected, including running analyzers for any available data. The requested data is sent. The code analysis data can be used for other purposes than visualizations.
US09424022B2 Method for updating firmware of an electronic device within a computer
A method for updating firmware of a hard disk drive (HDD) within a computer. In order to use the firmware that has been updated without rebooting the computer, the old identification information of the old firmware is loaded into a random-access memory (RAM) of the HDD. The new firmware containing new identification information is written in the non-volatile memory of the HDD during a power-on state of the computer. The new firmware containing new identification information is loaded into the RAM, and the new identification information is rewritten with the old identification information. The old identification information at the RAM of the HDD is sent back in response to a request of identification information from the operating system prior to cold boot.
US09424021B2 Capturing updates to applications and operating systems
An enterprise network management system is described for automatically updating program layers. A program is installed on a reference machine designated for the program and the reference machine is subsequently suspended. When the system detects a newer version of the program on a client device on the network, the reference machine is resumed, the program is allowed to update to the newer version, an updated program layer for the newer version is captured and stored, and the reference machine is suspended. Thereby, when a program layer for the updated application is required for IT operations, the layer will be available. The process can repeat when subsequent versions of the program are detected on client devices.
US09424020B2 Remote flashing during infusion
A medical device controller operating in conjunction with a medical device determines one or more current versions of executable code associated with one or more processors in a medical device. Medical devices may include infusion pumps, other patient treatment devices as well as vital signs monitors. The medical device controller determines one or more current versions of executable code and configuration information associated with the one or more processors in the medical device. The medical device controller further determines which of the processors in the medical device require updated executable code, and which of the processors in the medical device require updated configuration information. The medical device controller distributes to the medical device as required at least one of the updated executable code and the updated configuration information. The medical device deploys the distributed updates, and activates the updates at a clinically appropriate time.
US09424018B2 Filtering and promoting application store applications
Techniques for filtering and promoting application store applications are described that can be employed to provide filtered application information and/or application promotions to client devices. The filtering and promoting can be based at least in part upon system information that describes configurations and capabilities of the client devices. In one or more embodiments, various system information for a client device is detected. The detected system information for the client device is used to filter application data in an application catalog. Page information to be provided to the client device for interaction with the application catalog is then ascertained using the filtered application data. The page information is sufficient to enable the client device to render targeted application store pages having filtered application information and/or promotions that are selected based on the detected system information.
US09424014B2 Strength reduction compiler optimizations for operations with unknown strides
An optimizing compiler includes a strength reduction mechanism that optimizes a computer program that includes operations that have an unknown stride by analyzing the instructions in the computer program in a single pass, determining whether instruction substitution is profitable for original instructions in the code, and performing instruction substitution for one or more original instructions for which instruction substitution is deemed profitable, including operations with unknown strides. The substituted instructions result in strength reduction in the computer program.
US09424012B1 Programmable code fingerprint
A method, computer program product, and system performing a method that includes a processor compiling a description including information to be utilized by programmable logic to recognize a code fingerprint in a program executing in the runtime environment. The method also includes the processor configuring the programmable logic, by loading the description into the programmable logic at a predefined time and obtaining, during runtime of the program, an alert that the programmable logic recognized the code fingerprint in the program.
US09424011B2 Recursive expression simplification
A computer-implemented method, carried out by one or more processors, for recursive expression reduction. In an embodiment, the method comprises the steps of identifying a candidate loop, where the candidate loop includes at least one or more reduction variables and reduction operations; altering grouping of loop invariants and loop variants within the candidate loop; and performing recursive expression simplification for an inner loop, wherein the inner loop is located within the candidate loop.
US09424008B2 API descriptions
API description techniques are described for consumption by dynamically-typed languages. In one or more implementations, machine-readable data is parsed to locate descriptions of one or more application programming interfaces (APIs). The descriptions of the one or more application programming interfaces are projected into an alternate form that is different than a form of the machine-readable data.
US09424006B2 Execution optimization of mobile applications
According to an aspect of some embodiments of the present invention there is provided a method for changing a program code to decrease execution time. The method comprises an action of receiving a program code, comprising function calls, with an entry and a target function. The method comprises analyzing the function calls between the entry function and the target function. A first program code is generated, comprising some of the function calls executed before the target function. A second program code is generated, comprising some of the function calls executed after the target function. The function calls executed before the target function are replaced with the first program code. The function calls executed after the target function are removed. The second program code is added to the program code to execute after the target function as a background process.
US09424003B1 Schema-less system output object parser and code generator
A schema-less system output object parser and code generation process analyzes an instance of a response object from a system, such as a storage array, having components of multiple different types, formats and communications protocols, and automatically generates middleware Java source code to translate and communicate requests and responses between the different components and client applications. Output response objects responding to application requests are annotated and parsed, and data structures are created and initialized with keys and key value variables to generate source code to handle live data.
US09424002B2 Meta-application framework
The present disclosure describes a meta-application framework that enables data to be associated with a class of applications called a meta-application. A meta-application entity may store attributes in common across multiple platforms. A platform entity may store attributes in common across multiple devices and/or operating systems. A device entity may be comprised by a particular set of hardware features and an operating system entity may be comprised of a particular set of software feature. Data associated with the meta-application framework may be accessed directly via data manipulation operations or alternatively by application operations via an application programming interface or via the aforementioned data manipulation operations. Applications may then identify application specific behavior at the appropriate level of detail.
US09423998B2 System and method for playback of media content with audio spinner functionality
A system and method for playback of media content, for example music, video, or other media content. A media device having a media playback application and including a touch-sensitive user interface can be adapted to display a visual array of media options, for example as a grid or list of card elements. Each media option can be associated with one or more media content items that can be streamed to and/or played on the device. The system can determine a selected card element, or media options that are proximate to a selected point or region of the visual array, and play or crossfade media content as appropriate. In accordance with various embodiments, additional features can be provided that improve user interaction, for example the use of audible notifications, media caching, or touch menus.
US09423995B2 Method and apparatus for re-sizing an active area of a flexible display
A method (400) for resizing an active area of a flexible display or reconfigurable device (100) can include a screen (104 or 210) and a controller (202) coupled to the screen. The controller can initiate (402) a re-sizing program upon detection of an altered shape for the display or device and control (411) the active area of the display based upon the altered shape. The controller can further resize (414) fonts or graphic elements or both in correspondence to the dimensions of the active area. The controller can initiate the resizing program by altering the flexible display away from a flat position to a non-flat position for example. The flexible display can further include a switch (106) that detects the mating of a first end (111) of the flexible display with a second end (112) which initiates the resizing program.
US09423991B2 Information processing apparatus, information processing system, and information processing method
An information processing apparatus includes a process control unit that executes one or more process units with respect to input data in an order defined by definition information, an output unit that causes information to be output in a form changeable by a user when a first process unit of the process units is stopped, and an accepting unit that accepts changed information corresponding to the information output by the output unit that is changed by the user. The information output by the output unit includes output information of a process unit executed before the first process unit and/or input information set up in the definition information with respect to a process unit to be executed after the first process unit. The process control unit controls execution of the process unit to be executed after the first process unit based on the changed information accepted by the accepting unit.
US09423989B2 System and method for dynamically reconfiguring one or more autonomous cells in a print shop environment
A method and system for processing jobs in a print shop is provided. The print shop includes at least two autonomous cells, and each autonomous cell includes a resource for performing an operation relative to at least one of the jobs. In one approach, the number of jobs requiring an operation at each one of the two autonomous cells is monitored. When the number of jobs requiring at least one operation at each one of the two autonomous cells exceeds a selected number, a reconfiguration mode is simulated for at least one of the two autonomous cells to obtain a reconfiguration desirability value. The at least one of the two autonomous cells is reconfigured when the reconfiguration desirability value differs from a selected reference value.
US09423988B2 Print control apparatus, print control method, image forming apparatus, image forming method and computer-readable recording medium
A print control apparatus connectable to an image forming apparatus, an image forming apparatus, a print control method, an image forming method, and a non-transitory computer-readable medium are provided. The print control apparatus includes a manipulation inputter configured to receive a command to print a document, a controller configured to calculate a toner amount for each of a plurality of print saving modes applicable to the document, and determine a print saving mode to be applied to the document based on the calculated toner amount, a printer driver configured to generate print data on the document according to the determined print saving mode, and a communication interface configured to transmit the generated print data to the image forming apparatus.
US09423977B2 Lock-free communication storage request reordering
Lock-free communication storage request reordering enables reduced latency and/or increased bandwidth in some usage scenarios, such as a multi-threaded driver context operating with a device, such as a storage device (e.g. a Solid-State Disk (SSD)) enabled to respond to a multiplicity of outstanding requests.
US09423969B2 Sensing operations in a memory device
Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.
US09423967B2 Scheduling of I/O writes in a storage environment
A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.
US09423962B1 Intelligent snapshot point-in-time management in object storage
Various embodiments for managing data objects stored in a tiered data object storage environment, by a processor device, are provided. In one embodiment, a method comprises using an application to provide directives to the tiered data object storage environment for manipulating and managing stored data objects such that data objects with a pending management operation are refrained from being migrated from a higher storage tier to a lower storage tier.
US09423961B2 Method to enhance programming performance in multilevel NVM devices
An apparatus includes an interface and a processor. The interface is configured to communicate with a memory device. The processor is configured to send to the memory device, via the interface, a sequence of write commands that program multiple types of memory pages that incur respective different programming durations in the memory device, while inserting in the sequence suspension periods for permitting execution of storage commands that are not part of the sequence, such that at least some of the suspension periods are followed by write commands of types that do not have a shortest programming duration among the programming durations.
US09423959B2 Method and apparatus for store durability and ordering in a persistent memory architecture
An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.
US09423955B2 Previewing and playing video in separate display window on mobile terminal using gestures
A method and device for reproducing contents of a mobile terminal having a touch screen, including: displaying on the touch screen a list of items corresponding to a plurality of contents stored in the mobile terminal; detecting a touch input to an item displayed in the list; displaying on the touch screen a reproduction screen display having a location and a size corresponding to a determined touch input location; and one of reproducing an entirety of a content corresponding to the touched item and reproducing only a portion of the content corresponding to the touched item in the reproduction screen display according to a detected touch type.
US09423954B2 Graphical user interface methods, systems, and computer program products
Methods, computer software, apparatuses, and systems are described in connection with a mobile device including at least one processor operatively coupled to a touchscreen and memory. The memory stores a first application and a second application. The mobile device is configured for: presenting, utilizing the touchscreen, at least one menu including a plurality of interface elements including a first application interface element associated with the first application and a second application interface element associated with the second application; detecting, utilizing the touchscreen, a first user input in connection with the first application interface element associated with the first application; in response to the first user input, presenting, utilizing the touchscreen, a first visual component for presenting first data associated with the first application; detecting, utilizing the touchscreen, a second user input in connection with the second application interface element associated with the second application; in response to the second user input, presenting, utilizing the touchscreen, a second visual component for presenting second data associated with the second application, such that a first border of the first visual component corresponds to a second border of the second visual component; detecting, utilizing the touchscreen, a third user input; and in response to the third user input, automatically changing, utilizing the at least one processor and the touchscreen, the presentation of the first visual component and the second visual component, such that the first border of the first visual component corresponds to the second border of the second visual component.
US09423948B2 Information processing device, control method for information processing device, program, and information storage medium for determining collision between objects on a display screen
To provide an information processing device capable of ensuring not to execute processing not intended by a user in a case of stopping the ongoing operation after selecting an object (for example, in selecting again an object other than the object already selected, or the like). In a case where one of a user's designated position is included in a determination area based on the position of one of the plurality of objects displayed in a screen, an object moving unit (56) moves the one object based on the one designated position. In a case where the object moving unit (56) moves first and second objects, a collision determination unit (58) determines whether or not the first and second objects have collided. A processing executing unit (60) executes processing relevant to the first and second objects based on a result of determination by the collision determination unit (58).
US09423947B2 Mobile electronic device, control method, and storage medium storing control program
According to an aspect, a mobile electronic device includes: a display unit, an operating unit, and a control unit. The display unit for displays a character input screen including a part of a plurality of soft key objects each associated with a process in a line. The operating unit receives input of an operation. Upon detecting a changing operation through the operating unit, the control unit changes arrangement of the soft key objects such that at least one of the soft key objects that has been displayed is not displayed and at least one of the soft key objects that has not been displayed is displayed.
US09423943B2 Automatic variable zooming system for a project plan timeline
A system is provided that performs automatic variable zooming. The system displays a project plan timeline within a user interface, where a project plan timeline includes one or more tasks and a timeline includes one or more time units. The system further receives an instruction to invoke automatic variable zooming on the displayed project plan timeline. The system further receives a criteria. The system further calculates one or more scores for the one or more time units of the project plan timeline based on the criteria. The system further adjusts a zoom level for one or more portions of the project plan timeline based on the one or more calculated scores.
US09423942B2 Scrolling apparatus, scrolling method, and computer-readable medium
A scrolling apparatus includes: a display unit which displays a content on a screen; a contact detection unit which detects contact of a finger to the screen; a proximity detection unit which detects proximity of a finger to the screen; a scrolling control unit which scrolls the content displayed on the screen in response to a contact manipulation of the finger on the screen; and a display control unit which displays, on the screen, the scrolled content. The scrolling control unit decelerates a scroll speed to a given speed if proximity of the finger to the screen is detected at or after a start of the scrolling.
US09423937B2 Vehicle displays systems and methods for shifting content between displays
Methods and systems are provided, for automatically causing content items to shift to or from screens of a vehicle. One example includes a system in a vehicle that includes an on-board computer. The system includes a first display screen of the vehicle and a second display screen of the vehicle. Also provided is a processor of the on-board computer for processing instructions to enable rendering of a graphical user interface (GUI) items on each of the first and second display screens. A first GUI item is displayed on the first display screen and a second GUI item is displayed on the second display screen. The instructions processed by the processor automatically causing the first GUI item to shift from being displayed on the first display screen to being displayed on the second display screen. Wherein the shifting occurs in response to processing a safe driving condition.
US09423935B2 Terminal apparatus and GUI screen generation method
A terminal apparatus operates according to manipulation by a user on a Graphical User Interface (GUI) screen. The terminal apparatus includes: a generator that generates the GUI screen, the GUI screen including an object selectable in the manipulation and a pointer for selecting the object; and a blur calculator that calculates a vertical blur amount and a horizontal blur amount of a position at which the pointer is displayed on the GUI screen. The generator changes the GUI screen in a vertical direction depending on the vertical blur amount, and changes the GUI screen in a horizontal direction depending on the horizontal blur amount.
US09423934B2 Method for displaying background screen in mobile device and mobile device adapted thereto
A method for displaying a background screen in a mobile terminal is provided. The method includes resizing at least one of a plurality of background screens according to a first input, displaying at least one of the at least one resized background screen, detecting a second input, and transitioning among the resized background screens based on the detected second input, wherein the background screens respectively include an icon that may represent a grouping of a first icon and a second icon respectively displayed on one of the plurality of background screens.