最新美国发明专利第2016-05-17期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09343697B2	Adhesive film and sealing method for organic electronic device using same Provided are an adhesive film, an organic electronic device (OED) encapsulation product using the same, and a method of encapsulating the organic electronic device, and more particularly, an adhesive film for encapsulating an organic electronic element including a first adhesive layer having a loss coefficient (tan δ) at 60 to 100° C. of 1 to 5, and a second adhesive layer formed on the first adhesive layer, and a method of encapsulating an organic electronic device using the same.
US09343696B2	Adhesive film An adhesive film, a method for preparing an adhesive film, and an organic electronic device are provided. According to the adhesive film in exemplary embodiments of the present invention, fluidity of an adhesive can be controlled in the case of applying the adhesive between objects to be subsequently adhered to each other and then thermal-compressing by including an adhesive layer with cured side faces contacting with the outside. The adhesive film is used, for example for assembling a panel and the like, and thereby a defect rate at the time of assembling a panel and the like can be reduced and excellent work characteristics can be provided. In addition, before being applied to a panel or the like, a moisture absorbent included inside an adhesive layer of an adhesive film can be protected from external moisture or the like, thereby being easily stored, and also when it is applied to a product, reliability of life span, and the like can be secured.
US09343691B2	Light-emitting element, light-emitting device, electronic device, and lighting device A novel light-emitting device is provided. A novel light-emitting device with high emission efficiency, low power consumption, and small viewing angle dependence of chromaticity is provided. The light-emitting device includes at least one light-emitting element and one optical element. A spectrum of light emitted from the light-emitting element through the optical element in a range of greater than 0° and less than or equal to 70° with respect to a normal vector of the light-emitting element has a first local maximum value in a wavelength range of greater than or equal to 400 nm and less than 480 nm and a second local maximum value located on a longer wavelength side than the first local maximum value. The intensity ratio of the second local maximum value to the first local maximum value is less than or equal to 15%.
US09343690B2	Method for producing organic electroluminescence element, and organic electroluminescence element A method for producing a luminescent organic film, the method including: coating a solution containing a π-electron conjugated compound precursor A-(B)m and at least one kind of a luminescent dye, where the π-electron conjugated compound precursor A-(B)m contains a leaving substituent; and applying external stimulus to the π-electron conjugated compound precursor A-(B)m to eliminate the leaving substituent thereof, so that the π-electron conjugated compound precursor A-(B)m is converted to a π-electron conjugated compound A-(C)m and an eliminated compound X—Y as in the following reaction formula (I):
US09343689B2	Light-emitting element, light-emitting device, electronic device, and lighting device An object is to provide a light-emitting element capable of emitting light with a high luminance even at a low voltage, and having a long lifetime. The light-emitting element includes n EL layers between an anode and a cathode (n is a natural number of two or more), and also includes, between m-th EL layer from the anode and (m+1)-th EL layer (m is a natural number, 1≦m≦n−1), a first layer including a first donor material in contact with the m-th EL layer, a second layer including an electron-transport material and a second donor material in contact with the first layer, and a third layer including a hole-transport material and an acceptor material in contact with the second layer and the (m+1)-th EL layer.
US09343681B2	Light-emitting element, light-emitting device, electronic device, lighting device, and pyrene-based compound A highly efficient light-emitting element capable of providing a plurality of emission colors is provided, which does not easily deteriorate and can minimize a decrease in external quantum efficiency even when a light-emitting layer has a stacked structure. A light-emitting device, an electronic device, and a lighting device which have low power consumption and long lifetime are provided. A light-emitting element includes a plurality of light-emitting layers stacked between a pair of electrodes. The light-emitting layers each contain a host material and a guest material. The guest materials of the light-emitting layers are substances which have different HOMO levels but have substantially the same LUMO levels and emit light of different colors. A light-emitting device, an electronic device, and a lighting device are fabricated using the light-emitting element.
US09343677B2	GCIB-treated resistive device The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
US09343675B2	Multistate nonvolatile memory elements Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.
US09343674B2	Cross-point memory utilizing Ru/Si diode Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface of ruthenium or ruthenium silicide between the silicon material and the ruthenium material.
US09343672B2	Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.
US09343671B2	Memory cells having heaters with angled sidewalls Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.
US09343670B2	Memory arrays and methods of forming same Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.
US09343667B1	Circuits having programmable impedance elements and vertical access devices A memory device can include at least one programmable impedance cell having at least one programmable layer formed between a first terminal and a second terminal, the programmable layer being programmable between at least two impedance states by application of electric fields; and at least a first access bipolar junction transistor (BJT) coupled to the programmable impedance cell having at least a portion formed by a semiconductor material; wherein a base region and a first emitter region or collector region of the first access BJT are vertically aligned with one another.
US09343666B2	Damascene metal-insulator-metal (MIM) device with improved scaleability A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
US09343664B2	Pattern fortification for HDD bit patterned media pattern transfer A method and apparatus for forming a magnetic layer having a pattern of magnetic properties on a substrate is described. The method includes using a metal nitride hardmask layer to pattern the magnetic layer by plasma exposure. The metal nitride layer is patterned using a nanoimprint patterning process with a silicon oxide pattern negative material. The pattern is developed in the metal nitride using a halogen and oxygen containing remote plasma, and is removed after plasma exposure using a caustic wet strip process. All processing is done at low temperatures to avoid thermal damage to magnetic materials.
US09343659B1	Embedded magnetoresistive random access memory (MRAM) integration with top contacts A magnetoresistive random access memory (MRAM) device includes a top electrode or top contact above a metal hard mask which has a limited height due to process limitations in advanced nodes. The metal hard mask is provided on a magnetic tunnel junction (MTJ). The top contact for the MTJ is formed within a dielectric layer, such as a low dielectric constant (low-k) or extremely low-k layer. An additional dielectric layer is provided above the top contact for additional connections for additional circuitry to form a three-dimensional integrated circuit (3D IC).
US09343654B2	Method of manufacturing implantable wireless acoustic stimulators with high energy conversion efficiencies Receiver-stimulator with folded or rolled up assembly of piezoelectric components, causing the receiver-stimulator to operate with a high degree of isotropy are disclosed. The receiver-stimulator comprises piezoelectric components, rectifier circuitry, and at least two stimulation electrodes. Isotropy allows the receiver-stimulator to be implanted with less concern regarding the orientation relative the transmitted acoustic field from an acoustic energy source.
US09343649B1	Method for producing smooth inner surfaces The invention provides a method for preparing superconducting cavities, the method comprising causing polishing media to tumble by centrifugal barrel polishing within the cavities for a time sufficient to attain a surface smoothness of less than 15 nm root mean square roughness over approximately a 1 mm2 scan area. The method also provides for a method for preparing superconducting cavities, the method comprising causing polishing media bound to a carrier to tumble within the cavities. The method also provides for a method for preparing superconducting cavities, the method comprising causing polishing media in a slurry to tumble within the cavities.
US09343646B2	Thermo-electric power harvesting bearing configuration A power generating bearing assembly (100) comprises a bearing subassembly (120) retained by a bearing housing (110). During operation, friction and other factors increase a temperature of the bearing assembly (100). The housing (110) can optionally include a bearing cooling passage system comprising at least one liquid cooling passage (134) formed internally therein. The liquid cooling passage (134) would be routed proximate the bearing subassembly (120) to remove heat therefrom. A thermal energy transfer media (204) is inserted into a thermal transfer conduit (180), wherein the thermal transfer conduit (180) passes across a heated section of the housing (110). The transfer media (204) conveys the thermal energy to a Thermo-Electric Generator (TEG) (200) located in a thermoelectric generator housing (250) attached to the bearing housing (110). The Thermo-Electric Generator (TEG) (200) utilizes a temperature difference between the transfer media (204) and the ambient air to generated electric power. The power can be used to operate electrically powered devices, such as condition sensors (150), communication devices, and the like.
US09343643B2	Light emitting device A light emitting device has: a first lead which is mounted a light emitting element, a second lead separated by an interval from the first lead, an insulating member configured to fix the first lead and the second lead, a wavelength conversion portion configured to cover the light emitting element, and a lens portion configured to cover the wavelength conversion portion, a thickness of the insulating member is equal to the thickness of the first lead and the second lead, a groove or a recessed portion is provided to retain the wavelength conversion portion in a specific region is formed in the first lead, and a lower surface of the first lead that forms an opposite side of a region formed on the wavelength conversion portion is not covered by the insulating member and is exposed to the outside.
US09343637B2	Optoelectronic semiconductor chip and method for producing optoelectronic semiconductor chips An optoelectronic semiconductor chip has a semiconductor body and a substrate on which the semiconductor body is disposed. The semiconductor body has an active region disposed between a first semiconductor layer of a first conductor type and a second semiconductor layer of a second conductor type. The first semiconductor layer is disposed on the side of the active region facing the substrate. The first semiconductor layer is electrically conductively connected to a first termination layer that is disposed between the substrate and the semiconductor body. An encapsulation layer is disposed between the first termination layer and the substrate and, in plan view of the semiconductor chip, projects at least in some regions over a side face which delimits the semiconductor body.
US09343636B2	Wavelength conversion element, light-emitting semiconductor device and display apparatus therewith, and method for producing a wavelength conversion element A wavelength conversion element including at least two ceramic conversion segments each including a ceramic wavelength conversion substance and connected together in a matrix by a non-transparent connecting material, wherein each conversion segment emits light by absorbing primary radiation and re-emitting secondary radiation different from the primary radiation, and the light comprises the secondary radiation and a proportion of the primary radiation is less than or equal to 5%.
US09343631B2	Light emitting diode chip having distributed bragg reflector and method of fabricating the same A light-emitting diode chip configured to emit light of a first wavelength range and light of a second wavelength range, including a substrate, a light-emitting structure disposed on a first surface of the substrate, the light-emitting structure including an active layer disposed between a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, and configured to emit light of the first wavelength range, and first and second distributed Bragg reflectors (DBRs) disposed on a second surface of the substrate. The first DBR is disposed closer to the substrate than the second DBR, the first wavelength range comprises a blue wavelength range, the first DBR comprises a higher reflectivity for light of the second wavelength range than for light of the first wavelength range, and the second DBR comprises a higher reflectivity for light of the first wavelength range than for light of the second wavelength range.
US09343627B2	Electronic device comprising semiconductor memory having ohmic-contact structure separated from current distributing layer Disclosed are an LED and an LED module. The LED includes: a first conductivity type semiconductor layer; a mesa disposed over the first conductivity type semiconductor layer and including an active layer and a second conductivity type semiconductor layer; a first ohmic-contact structure in contact with the first conductivity type semiconductor layer; a second ohmic-contact structure in contact with the second conductivity type semiconductor layer; a lower insulating layer at least partially covering the mesa and the first conductivity type semiconductor layer and disposed to form a first opening part at least partially exposing the first ohmic-contact structure and a second opening part at least partially exposing the second ohmic-contact structure; and a current distributing layer connected to the first ohmic-contact structure at least partially exposed by the first opening part and disposed to form a third opening part at least partially exposing the second opening part.
US09343623B2	Horizontal power LED device and method for manufacturing same The present invention relates to a horizontal LED device and a method of manufacturing the same. More particularly, the present invention relates to a high-power and high-efficiency horizontal LED device manufactured using the advantages of conventional horizontal and vertical LEDs, and a method of manufacturing the same.
US09343622B2	Nitride semiconductor light emitting device and fabrication method thereof Provided is a nitride semiconductor light emitting device including: a substrate; a first buffer layer formed above the substrate; an indium-containing second buffer layer formed above the first buffer layer; an indium-containing third buffer layer formed above the second buffer layer; a first nitride semiconductor layer formed above the third buffer layer; an active layer formed above the first nitride semiconductor layer; and a second nitride semiconductor layer formed above the active layer. According to the present invention, the crystal defects are further suppressed, so that the crystallinity of the active layer is enhanced, and the optical power and the operation reliability are enhanced.
US09343620B2	Method for fabricating a light emitting diode (LED) die having protective substrate A method for fabricating a light emitting diode die includes the steps of providing a carrier substrate and forming an epitaxial structure on the carrier substrate including a first type semiconductor layer, a multiple quantum well (MQW) layer on the first type semiconductor layer configured to emit light, and a second type semiconductor layer on the multiple quantum well (MQW) layer. The method also includes the steps of forming a plurality of trenches through the epitaxial structure, forming a reflector layer on the second type semiconductor layer, forming a seed layer on the reflector layer and in the trenches, and forming a substrate on the seed layer having an area configured to protect the epitaxial structure.
US09343614B2	Superluminescent diode, method of manufacturing the same, and wavelength-tunable external cavity laser including the same Provided are a high-speed superluminescent diode, a method of manufacturing the same, and a wavelength-tunable external cavity laser including the same. The superluminescent diode includes a substrate having an active region and an optical mode size conversion region, waveguides including an ridge waveguide in the active region and a deep ridge waveguide in the optical mode size conversion region connected to the active waveguide, an electrode disposed on the ridge waveguide; planarizing layers disposed on sides of the ridge waveguide and the deep ridge waveguide on the substrate, and a pad electrically connected to the electrode, the pad being disposed on the planarizing layers outside the active waveguide.
US09343613B2	Phosphor in inorganic binder for LED applications A method for fabricating an LED/phosphor structure is described where an array of blue light emitting diode (LED) dies are mounted on a submount wafer. A phosphor powder is mixed with an organic polymer binder, such as an acrylate or nitrocellulose. The liquid or paste mixture is then deposited over the LED dies or other substrate as a substantially uniform layer. The organic binder is then removed by being burned away in air, or being subject to an O2 plasma process, or dissolved, leaving a porous layer of phosphor grains sintered together. The porous phosphor layer is impregnated with a sol-gel (e.g., a sol-gel of TEOS or MTMS) or liquid glass (e.g., sodium silicate or potassium silicate), also known as water glass, which saturates the porous structure. The structure is then heated to cure the inorganic glass binder, leaving a robust glass binder that resists yellowing, among other desirable properties.
US09343604B2	Process for monolithic series connection of the photovoltaic cells of a solar module and a photovoltaic module implementing this process A method for manufacturing two series-connected photovoltaic cells includes: forming an insulating substrate; forming a stack including; a first conductive layer formed on the substrate; a semiconductor layer comprising a first absorption layer and a second semiconductor layer forming a junction with the first absorption layer; and a second transparent conductive layer, formed on the absorption layer; forming an area dividing the stack into two cells series-connected by an electric path. The forming of said path comprises: forming a first trench all the way to the substrate; forming a second trench all the way to the first conductive layer; and depositing a conductive solution on the first trench and at last a portion of the second trench, so that the solution does not penetrate into the first trench all the way to the first conductive layer and penetrates into the second trench all the way to the first conductive layer.
US09343603B2	Method for manufacturing solar cell module and laminator By increasing a pressure in a chamber flange (10) at a predetermined rate, the number of gas molecules that carry inner thermal energy is increased, which results in a uniform temperature distribution. Thus, non-melting residues of, air bubbles in, and insufficient expansion of the sealing resin (43) are reduced. After removal of the air bubbles (45), a pressure is applied between a substrate (41) and a sealing substrate (44), thereby the substrate (41), a solar cell (42), the sealing resin (43) and the sealing substrate (44) are adhered to each other.
US09343601B2	Photodetector Provided is a photodetector including a graphene p-n homogeneous vertical-junction diode by evaluating photodetection characteristics of the manufactured graphene p-n vertical junction according to the amount of doping. The photodetector comprises a substrate and graphene having a p-n homogeneous vertical junction as a photodetection layer formed on the substrate, wherein the photodetection layer has a detectability of 10E11 (Jones) or higher within the range of 350 nm to 1100 nm, and first and second electrodes are formed on the photodetection layer.
US09343598B2	Solar cell A solar cell includes a back electrode, a silicon substrate, a doped silicon layer and an upper electrode arranged in that order. The silicon substrate comprises a number of three-dimensional nano-structures aligned side by side adjacent to the upper electrode. The doped silicon layer is located on a surface of the three-dimensional nano-structures. A cross section of each three-dimensional nano-structure is M-shaped.
US09343595B2	Photovoltaic devices with electroplated metal grids One embodiment of the present invention provides a solar cell. The solar cell includes a photovoltaic structure and a front-side metal grid situated above the photovoltaic structure. The front-side metal grid also includes one or more electroplated metal layers. The front-side metal grid includes one or more finger lines, and each end of a respective finger line is coupled to a corresponding end of an adjacent finger line via an additional metal line, thus ensuring that the respective finger line has no open end.
US09343593B2	Printable composition of a liquid or gel suspension of diodes An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. In other exemplary embodiments a second solvent is also included, and the composition has a viscosity substantially between about 100 cps and about 25,000 cps at about 25° C. In an exemplary embodiment, a composition comprises: a plurality of diodes or other two-terminal integrated circuits; one or more solvents comprising about 15% to 99.9% of any of N-propanol, isopropanol, dipropylene glycol, diethylene glycol, propylene glycol, 1-methoxy-2-propanol, N-octanol, ethanol, tetrahydrofurfuryl alcohol, cyclohexanol, and mixtures thereof; a viscosity modifier comprising about 0.10% to 2.5% methoxy propyl methylcellulose resin or hydroxy propyl methylcellulose resin or mixtures thereof; and about 0.01% to 2.5% of a plurality of substantially optically transparent and chemically inert particles having a range of sizes between about 10 to about 50 microns.
US09343590B2	Planar semiconductor ESD device and method of making same An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.
US09343588B2	Normally-off semiconductor switches and normally-off JFETs A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided.
US09343587B2	Field effect transistor with self-adjusting threshold voltage Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer.
US09343582B2	Manufacturing method of thin film transistor substrate An embodiment of the invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a photo-sensitive protective layer which is above the gate electrode and has a first recess and a second recess; etching the active material layer by using the photo-sensitive protective layer as a mask to form an active layer; removing a portion of the photo-sensitive protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion.
US09343580B2	Semiconductor device A semiconductor device (100a) with a thin-film transistor (10a) includes: a gate electrode (62) formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode; an oxide semiconductor layer (68) formed on the gate insulating layer; source and drain electrodes (70s, 70d) electrically connected to the oxide semiconductor layer; a protective layer (72) formed on the oxide semiconductor layer and the source and drain electrodes; an oxygen supplying layer (74) formed on the protective layer; an anti-diffusion layer (78) formed on the oxygen supplying layer; and a transparent electrode (81) formed on the anti-diffusion layer and made of an amorphous transparent oxide.
US09343577B2	Thin film transistor, display apparatus including the thin film transistor, and method of manufacturing the thin film transistor A thin film transistor includes: a substrate, a semiconductor layer disposed on the substrate, a first gate electrode and a second gate electrode disposed on the semiconductor layer, a gate insulating layer disposed between the semiconductor layer and the first and second gate electrodes and having a first through hole between the first and second gate electrodes and a capping layer covering the first gate electrode and contacting the semiconductor layer via the first through hole. The capping layer includes a conductive material.
US09343576B2	Thin film forming method, semiconductor substrate and electronic device produced by employing same The present invention provides a thin film forming method. The method includes the steps of: providing a first substrate, of which a surface is covered with a thin film; forming a plurality of openings through the thin film; forming a hollow portion between the first substrate and the thin film by etching the first substrate through the openings; bringing the thin film into contact with a second substrate with a liquid interposed between the thin film and the second substrate; and heating the first substrate and/or the second substrate. In the step of heating, the liquid interposed between the thin film and the second substrate evaporates off, which results in that the thin film is separated from the first substrate and transferred onto the second substrate.
US09343575B1	FinFET and method of manufacturing the same A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.
US09343573B2	Method of fabrication transistor with non-uniform stress layer with stress concentrated regions A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.
US09343568B2	Semiconductor device having high-resistance conductor structure, method of manufacturing the same and method of operating the same Provided is a semiconductor device including a metal oxide semiconductor transistor, a Zener diode, and a resistor. The metal oxide semiconductor transistor includes a gate, a source and a drain. The resistor has one end electrically connected to the drain, wherein the resistor includes a high resistance which is sufficient for flowing most of current to pass the metal oxide semiconductor transistor. The Zener diode includes a cathode and an anode, in which the cathode is electrically connected the gate and another end of the resistor, and the anode is electrically connected to a gate body.
US09343567B2	Semiconductor device A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.
US09343566B2	Semiconductor device A semiconductor device including a gate insulating film; a gate electrode; a source region of a first conductivity; a drain region of the first conductivity type; a drift region of the first conductivity type formed between the channel region and the drain region; a first semiconductor region of a second conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region; and a first shield wiring that encloses a portion of the source region in a plan view in conjunction with the gate electrode, the portion being not covered by the gate electrode, and is connected to the first semiconductor region, or that covers the portion and is connected to the first semiconductor region and the source region.
US09343565B2	Semiconductor device having a dense trench transistor cell array One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3<1.5×w1. The semiconductor device further includes semiconductor diodes. At least one of the semiconductor diodes is arranged between first and second parts of the plurality of transistor cells and includes a diode mesa region adjoining opposing walls of second trenches. A depth d1 of the first trench and a depth d2 of the second trenches differ by at least 20%.
US09343564B2	Semiconductor device including a gate electrode on a protruding group III-V material layer and method of manufacturing the semiconductor device A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.
US09343561B2	Semiconductor device with self-aligned ohmic contacts A method of fabricating a semiconductor device includes providing one or more semiconductor layers, providing a gate contact on a first surface of the one or more semiconductor layers, then using the gate contact as a mask to deposit a source contact and a drain contact on the first surface of the one or more semiconductor layers, such that the source contact and the drain contact include an interior edge that is laterally aligned with a different lateral edge of the gate contact.
US09343558B1	Silicon controlled rectifier A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a fourth doped region. The well is disposed on the substrate and underneath a cell region. The deep doped region is disposed in the well. The first doped region has a first conductivity type, and is disposed in the well. The second doped region and third doped region have the first conductivity type and are disposed on the deep doped region. The fourth doped region has a second conductivity type, and is disposed between the second doped region and the third doped region. The fourth doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region, the second doped region, and the third doped region.
US09343555B2	Methods and apparatus for ESD structures Methods and apparatus are disclosed for ESD protection circuits. An ESD protection circuit may comprise a first region of an n type material, a second region of a p type material adjacent to the first region, a third region of an n type material within the second region and separated from the first region, and a fourth region of a p type material within the third region. There may be multiple parts within the first region and the second region, made of different n type or p type materials. An ESD protection circuit may further comprise a fifth region of a p type material, contained within the first region.
US09343554B2	Semiconductor device and manufacturing method of the same A semiconductor device including a bipolar transistor in which a polysilicon film is used for an emitter electrode. The bipolar transistor includes a collector region formed in an Si substrate, a base layer formed on the collector region, an emitter region formed in an upper part spaced apart from the collector region of the base layers, and a silicon oxide film formed on the base layer and covering a joint portion of the base layer and the emitter region. The density of fluorine existent at an interface between the joint portion and the silicon oxide film is equal to or higher than 1×1020 cm−3.
US09343552B2	FinFET with embedded MOS varactor and method of making same Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.
US09343547B2	Method for fabricating a recessed channel access transistor device A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.
US09343545B2	Electrical coupling of memory cell access devices to a word line A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.
US09343544B2	Multi-finger large periphery AlInN/AlN/GaN metal-oxide-semiconductor heterostructure field effect transistors on sapphire substrate MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes.
US09343542B2	Method for fabricating enhancement mode transistor A method for making an enhancement-mode transistor is described. The method includes forming a first III-V compound layer on a substrate and forming a second III-V compound layer on the first III-V compound layer. The second III-V compound layer is different from the first III-V compound layer. A gate stack is formed thereon. The forming of the gate stack further includes forming a diode having a pair of a n-type doped III-V compound layer and a p-type doped III-V compound layer. Source and drain features are formed on the second III-V compound layer and interposed by the gate stack.
US09343541B2	Method of fabricating GaN high voltage HFET with passivation plus gate dielectric multilayer structure A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
US09343536B2	Semiconductor device A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode.
US09343534B2	Semiconductor materials, transistors including the same, and electronic devices including transistors According to example embodiments, a semiconductor material may include zinc, nitrogen, and fluorine. The semiconductor material may further include oxygen. The semiconductor material may include a compound. For example, the semiconductor material may include zinc fluorooxynitride. The semiconductor material may include zinc oxynitride containing fluorine. The semiconductor material may include zinc fluoronitride. The semiconductor material may be applied as a channel material of a thin film transistor (TFT).
US09343530B2	Method for manufacturing fin structure of finFET The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate (200); forming a first dielectric layer (210); forming a second dielectric layer (220), the material of the portion where the second dielectric layer is adjacent to the first dielectric layer being different from that of the first dielectric layer (210); forming an opening (230) through the second dielectric layer (220) and the first dielectric layer (2100, the opening portion exposing the substrate; filling a semiconductor material in the opening (230); and removing the second dielectric layer (220) to form a fin structure. In the present invention, the height of the fin structure in the FinFET is controlled by the thickness of the dielectric layer. The etching stop can be controlled well by using the etching selectivity between different materials, which can achieve etching uniformity better compared to time control.
US09343524B2	Etchstop layers and capacitors Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.
US09343522B2	Ceramic powder, semiconductor ceramic capacitor, and method for manufacturing same A ceramic powder for use in a grain boundary insulated semiconductor ceramic that has an excellent ESD withstanding voltage, a semiconductor ceramic capacitor using the ceramic powder, and a manufacturing method therefor. The ceramic powder for use in a SrTiO3 based grain boundary insulated semiconductor ceramic has a specific surface area of 4.0 m2/g or more and 8.0 m2/g or less, and a cumulative 90% grain size D90 of 1.2 μm or less.
US09343518B2	Organic light-emitting display apparatus including discontinuous insulating layer An organic light-emitting display apparatus includes a substrate including a display area, a peripheral area surrounding the display area, and an outermost area surrounding the peripheral area, a first insulating layer on the substrate across the display area, the peripheral area, and the outermost area, the first insulating layer being discontinuous in the peripheral area, a second insulating layer on the substrate across the display area and the peripheral area, is the second insulating layer being positioned on the first insulating layer in the display area and on a layer under the first insulating layer in a discontinuous portion of the first insulating layer in the peripheral area, and a pixel electrode on the second insulating layer in the display area.
US09343516B2	Display unit and electronic apparatus A display unit includes a light emitting layer including a light emitting device (10R, 10G, 10B); a color filter layer including a color filter (23R, 23G, 23B) corresponding to the light emitting device; and a light blocking layer (22) including a light blocking member (22B) arranged to overlap an end of the color filter, a center position of the light blocking member being offset from the end of the color filter.
US09343515B2	Display device, manufacturing method thereof, and electronic device A display device that includes a reflective electrode; a transparent electrode; a partition; an EL layer formed over the partition and the transparent electrode; a semi-transmissive electrode formed over the EL layer; and a coloring layer over the semi-transmissive electrode. A light-emitting region is formed to overlap with the transparent electrode, the EL layer, the semi-transmissive electrode, and the coloring layer. A non-light-emitting region is formed to overlap with the transparent electrode, the partition, the EL layer, and the coloring layer. The non-light-emitting region is formed to surround the light-emitting region. The sum of the optical length of the transparent electrode and the optical length of the EL layer is adjusted to fulfill a condition of a microcavity intensifying light of the color of the coloring layer. The optical length of the partition in the non-light-emitting region is adjusted to weaken external light incident through the coloring layer.
US09343510B2	Organic light emitting display device An OLED device according to one example includes a substrate defined into a plurality of sub-pixel regions which includes red, green and blue sub-pixel regions; a first electrode formed on the substrate; an organic emission layer formed on the first electrode; a second electrode formed on the organic emission layer; and a capping layer formed on the second electrode. The capping layer is formed to contain an optical adjustment material which rises in proportion to a wavelength of incident light.
US09343507B2	Dual channel vertical field effect transistor including an embedded electrode A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source. Each field effect transistor may include a first channel and a second channel, each including a second conductivity type
US09343506B2	Memory arrays with polygonal memory cells having specific sidewall orientations Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.
US09343495B2	Solid-state imaging device and method of manufacturing the same A solid-state imaging device includes a semiconductor layer, a reflector, and a plurality of element separating regions. In the semiconductor layer, a plurality of photoelectric conversion elements is arranged in a two-dimensional array. The reflector covers a surface of the semiconductor layer on a side opposite to a surface of the semiconductor layer on which alight is incident, and reflects the light. The element separating regions are formed in the semiconductor layer to physically and electrically separate the plurality of photoelectric conversion elements. Each of the element separating regions extend from the surface of the semiconductor layer on which the light is incident to the reflector and has a reflection surface for reflecting light.
US09343494B2	Light guided pixel configured for emissions detection and comprising a guide layer with a wavelength selective filter material and a light detector layer A light guided pixel having a guide layer and a light detector layer. The guide layer has a light guide. The light detector layer has a light detecting element that receives light channeled by the light guide. The light guide may include a filter for channeling emissions to the light detecting element.
US09343493B1	Image sensor An image sensor is provided. The image sensor includes a semiconductor substrate having a sensing region and a non-sensing region; a passivation layer formed on the semiconductor substrate; a first planar layer formed on the passivation layer; a color filter layer formed on the first planar layer with respect to the sensing region and a shielding layer formed on the first planar layer with respect to the non-sensing region; a plurality of micro-lens layers formed on the color filter layer and on the shielding layer; and a plurality of cap oxide layers formed on the micro-lens layer.
US09343492B2	CMOS image sensor based on thin-film on asic and operating method thereof Provided are a complementary metal-oxide semiconductor (CMOS) image sensor based on a thin-film-on-application specific integrated circuit (TFA), and a method of operating the same. The CMOS image sensor may include at least one floating diffusion region formed in a semiconductor substrate, and a thin film type light sensor disposed to correspond to a plurality of pixels. The CMOS image sensor may also include at least one via electrically connected between the light sensor and the at least one floating diffusion region. The CMOS image sensor may also include a first micro lens disposed to correspond to at least two pixels of the plurality of pixels.
US09343488B2	TFT array substrate manufacturing method thereof and display device According to embodiments of the invention, there are provided a TFT array substrate, a manufacturing method thereof and a liquid crystal display. The manufacturing method comprises manufacturing a pattern including a gate electrode, a gate insulating layer pattern with a via hole, a pattern including an active layer, a pattern including source and drain electrodes and a pattern including a first electrode on a substrate. The formation of the gate insulating layer pattern with the via hole and the pattern including the active layer are completed through one patterning process, the pattern including the gate electrode at least includes the gate electrode and a gate leading wire, the via hole of the gate insulating layer is located over the gate leading wire, and the active layer is located over the gate electrode.
US09343487B2	Thin film transistor substrate and manufacturing method thereof A TFT substrate includes a TFT including a source electrode having a lower source electrode and an upper source electrode, which are electrically connected to each other, and a drain electrode having a lower drain electrode and an upper drain electrode, which are electrically connected to each other. The lower source electrode and the lower drain electrode are in contact with a lower surface of the semiconductor film, and the upper source electrode and the upper drain electrode are in contact with an upper surface of the semiconductor film.
US09343481B2	TFT array substrate and manufacturing method thereof and liquid crystal display device The present invention discloses a TFT array substrate and a manufacturing method thereof and a liquid crystal display device, which is aiming at lowering the resistance value of a common electrode and not diminishing the aperture ratio of pixels on the premise that the manufacturing cost is not additionally increased. The TFT array substrate includes: a substrate, a common electrode layer arranged on the substrate, a first insulating layer arranged on the common electrode layer and a plurality of pixel electrodes arranged in an array on the first insulating layer, wherein via holes penetrating through the first insulating layer are formed between adjacent pixels in some of a plurality of pixels, and common electrode lines are grown between rows and/or columns of pixels in some of the plurality of pixels, and in parallel with the common electrode layer below the first insulating layer through the via holes.
US09343479B2	Three-dimensional devices having reduced contact length Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. Peripheral circuitry is formed on an elevated portion that is adjacent to the memory array and has an uppermost portion substantially coplanar with an uppermost surface of the memory array. Additional apparatuses and methods are described.
US09343476B2	Semiconductor devices and methods of fabricating the same The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.
US09343474B2	Method of manufacturing a semiconductor device having a stacked structure A semiconductor device that includes a plurality of first conductive patterns stacked over a substrate, dummy patterns formed in the first conductive patterns, respectively, first barrier patterns each surrounding the respective first conductive patterns and partially interposed between the respective first conductive patterns and the respective dummy patterns, second barrier patterns each surrounding the respective first barrier patterns and the respective dummy patterns, a second conductive pattern located over or under the first conductive patterns, and a third barrier pattern surrounding the second conductive pattern, wherein the second conductive pattern has a greater thickness than the first conductive patterns.
US09343473B2	Structure and method for manufacture of memory device with thin silicon body Described herein is a structure and method of manufacturing for a memory device with a thin silicon body. The memory device may be a semiconductor comprising: a first dielectric of a first width; a second dielectric of a second width, the second width less than the first width; and a thin film polycrystalline silicon (poly-Si) on sidewalls of the second dielectric.
US09343472B2	Memory cell with decoupled channels A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.
US09343468B1	Feed-forward bidirectional implanted split-gate flash memory cell A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.
US09343466B1	Methods for fabricating flash memory cells and integrated circuits having flash memory cells embedded with logic Methods for fabricating memory cells, methods for fabricating integrated circuits having memory cells, and integrated circuits having memory cells are provided. In one example, a method for fabricating a memory cell includes depositing a first tunnel dielectric layer over a semiconductor substrate. The method includes depositing a floating gate material over the first tunnel dielectric layer. The method forms two control gate stacks over the floating gate material, defines a source line area between the two control gate stacks, and defines select gate areas adjacent the two control gate stacks. The method includes depositing a second tunnel dielectric layer over the select gate areas of the semiconductor substrate. Further, the method includes forming select gates over the second tunnel dielectric layer over the select gate areas of the semiconductor substrate. The second tunnel dielectric layer forms a gate dielectric layer for each select gate.
US09343465B2	Integrated circuit for high-voltage device protection Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.
US09343463B2	Method of high density memory fabrication The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.
US09343461B2	Semiconductor device including a local wiring connecting diffusion regions A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.
US09343459B2	Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.
US09343458B2	Isolation structure for ESD device Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth.
US09343455B2	Apparatus and method for high voltage I/O electro-static discharge protection An electronics chip includes a charge pump and at least one high voltage (HV) electro-static discharge (ESD) module. The charge pump is configured to provide a predetermined voltage across a microphone. The devices described herein are implemented in a standard low voltage CMOS process and has a circuit topology that provides an inherent ESD protection level (when it is powered down), which is higher than the operational (predetermined) DC level. At least one high voltage (HV) electro-static discharge (ESD) module is coupled to the output of the charge pump. The HV ESD module is configured to provide ESD protection for the charge pump and a microelectromechanical system (MEMS) microphone that is coupled to the chip. The at least one HV ESD module includes a plurality of PMOS or NMOS transistors having at least one high voltage NWELL/DNWELL region formed within selected ones of the PMOS or NMOS transistors. The at least one high voltage NWELL/DNWELL region has a breakdown voltage sufficient to allow a low voltage process to be used to construct the chip and still allow the HV ESD module to provide ESD protection for the chip.
US09343448B2	Active matrix emissive micro LED display A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.
US09343445B2	Photoelectric conversion device A photoelectric conversion device includes a circuit board, a light emitting module, a light receiving module, and an optical coupling lens. Two protrusions apart from each other extend from the circuit board. The light emitting module and the light receiving module are mounted on the circuit board and apart from each other. The optical coupling lens includes an oblique reflection surface and a recess having a bottom surface parallel to the circuit board. Two distanced posts perpendicularly extend from the bottom surface and engage with the centers of the protrusions upon assembly to ensure automatic and alignment of the light emitting module with the first converging lens, and alignment of the light receiving module with the second converging lens.
US09343443B2	Light-emitting dies incorporating wavelength-conversion materials and related methods In accordance with certain embodiments, electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g., a light-emitting or a light-detecting element) suspended in the binder and within the aperture of the frame.
US09343439B2	Stack packages and methods of manufacturing the same A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.
US09343436B2	Stacked package and method of manufacturing the same A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.
US09343432B2	Semiconductor chip stack having improved encapsulation A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.
US09343430B2	Stacked wafer-level package device Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device includes one or more micro-solder bumps. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When the semiconductor package device is positioned over the semiconductor device, each micro-solder bump is connected to a respective electrical interconnection that is formed in the semiconductor device.
US09343426B1	Use of device assembly for a generalization of three-dimensional metal interconnect technologies An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.
US09343424B2	Structure of circuit board with voids A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.
US09343422B2	Structure for aluminum pad metal under ball bond A semiconductor structure is disclosed, wherein for a certain percentage of a plurality of bonding pads, the bonding pad metal may include a plurality of grains, wherein the plurality of grains may include a bonding grain. The bonding grain may have a width substantially the same as the width of the wire bonded to the bonding pad such that no grain boundaries are present below the wire bond.
US09343421B2	Semiconductor package and fabrication method thereof A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
US09343420B2	Universal solder joints for 3D packaging Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.
US09343419B2	Bump structures for semiconductor package A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The lateral dimension of the first metal pillar is greater than the lateral dimension of the second metal pillar.
US09343418B2	Solder bump arrangements for large area analog circuitry An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.
US09343416B2	Semiconductor device employing wafer level chip size package technology A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; a connection pad made of a metal having solder wettability, formed on a part facing the opening of the internal pad and provided with a protruding portion protruding on the stress relaxation layer; a metal flange made of a metal having solder wettability, encompassing the periphery of the protruding portion and formed with a smaller thickness than a protruding amount of the protruding portion onto the stress relaxation layer; and a solder terminal for electrical connection with outside formed on the protruding portion and the metal flange.
US09343414B2	Microelectronic packages having radio frequency stand-off layers Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts.
US09343409B2	Semiconductor devices having staggered air gaps A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
US09343407B2	Method to fabricate copper wiring structures and structures formed thereby Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.
US09343404B2	Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved.
US09343393B2	Semiconductor substrate assembly with embedded resistance element A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface. The first isolation layer is located on the first surface of the semiconductor material layer. The second isolation layer is located on the second surface of the semiconductor material layer. The first conductive pillar, supplied with a first voltage, penetrates the semiconductor material layer, the first isolation layer, and the second isolation layer. The second conductive pillar is supplied with to a second voltage, and a part of the second conductive pillar is formed in the second isolation layer, the second conductive pillar penetrates the second isolation layer and touches the second surface of the semiconductor material layer.
US09343390B2	TSV formation processes using TSV-last approach A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.
US09343388B2	Power semiconductor device A power semiconductor device is provided with a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate; semiconductor elements for electric power which are affixed to the surface of the front-surface electrode pattern; a partition wall which is provided on the front-surface electrode pattern so as to enclose the semiconductor elements for electric power; a first sealing resin member which is filled inside the partition wall; a second sealing resin member which covers the first sealing resin member and a part of the semiconductor-element substrate which is exposed from the partition wall, wherein an electrode for a relay terminal is provided on a surface of the partition wall, and a wiring from inside of the partition wall to outside of the partition wall is led out via the electrode for a relay terminal.
US09343387B2	Package on package structure and fabrication method thereof A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.
US09343385B2	Semiconductor device comprising a chip substrate, a mold, and a buffer layer A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.
US09343383B2	High voltage semiconductor devices including electric arc suppression material and methods of forming the same A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess.
US09343379B2	Method to delineate crystal related defects This invention generally relates to a process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.
US09343375B2	Method for manufacturing a transistor in which the strain applied to the channel is increased Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphization of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphization of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallization of the source and drain blocks such that the second semiconducting material imposes its lattice parameter on the source and drain zones.
US09343363B2	Through-silicon vias and interposers formed by metal-catalyzed wet etching Provided are methods for making a through-silicon via feature in a silicon substrate and related systems, such as by forming a noble metal structure on a silicon substrate support surface to generate silicon substrate contact regions that are in contact with or proximate to the noble metal structure; exposing at least a portion of the silicon substrate support surface and noble metal structure to an etchant to preferentially etch the silicon substrate contact regions compared to silicon substrate non-contact regions until the etch front reaches the silicon substrate bottom surface.
US09343360B2	Bump-equipped electronic component and method for manufacturing bump-equipped electronic component A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.
US09343358B1	Three-dimensional memory device with stress compensation layer within a word line stack A first stack of alternating layers including first insulating layers and first sacrificial material layers is formed on a substrate. Dielectric oxide layers applying compressive stress are formed on the top surface of the first stack and on the bottom surface of the substrate. A second stack of alternating layers including second insulating layers and second sacrificial material layers is formed over the top dielectric oxide layer. After formation of lateral recesses by removal of the first and second sacrificial material layers, a bottom dielectric oxide layer is removed. A conductive material applying a tensile stress is deposited into the backside recesses to form electrically conductive layers. The compressive stress applied by the top dielectric oxide layer partially cancels the tensile stress applied by the electrically conductive layers, and reduces the curvature of the substrate that has a concave bottom surface.
US09343357B2	Selective conductive barrier layer formation A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.
US09343356B2	Back end of the line (BEOL) interconnect scheme The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.
US09343352B2	Integrated circuit using deep trench through silicon (DTS) An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.
US09343349B2	Substrate holding apparatus and substrate holding method In accordance with some embodiments of the present disclosure, a substrate holding apparatus is provided. The substrate holding apparatus includes a first holding part, a second holding part and a controller. The first holding part adsorbs and holds a first region including a central portion of a substrate. The second holding part adsorbs and holds a second region located outside the first region of the substrate. The second holding part adsorbs and holds the second region of the substrate after the first holding part adsorbs and holds the first region of the substrate.
US09343346B2	Electrostatic chuck apparatus An electrostatic chuck apparatus including: an electrostatic chuck section having one main surface that is a mounting surface on which a plate specimen is mounted, and being equipped with an electrostatic adsorbing internal electrode; and a temperature adjusting base section that adjusts the electrostatic chuck section to a desired temperature, wherein a heating member is bonded to a main surface of the electrostatic chuck section, which is opposite to the mounting surface, via an adhesive material, the whole or a part of the main surface of the temperature adjusting base section, which is on the side of the electrostatic chuck section, is covered with a sheet or film of insulating material, and the electrostatic chuck section bonded with the heating member and the temperature adjusting base section covered with the insulating material are bonded and integrated via an insulating organic adhesive layer formed by curing a liquid adhesive.
US09343343B2	Method for reducing particle generation at bevel portion of substrate A method for transporting a substrate using an end effector which mechanically clamps a periphery of the substrate includes: before transporting the substrate, depositing a compressive film only on, at, or in a bevel portion of the substrate; and transporting the substrate whose bevel portion is covered by the compressive film as the outermost film, using an end effector while mechanically clamping the periphery of the substrate.
US09343342B2	Handler for testing semiconductor device with detecting sensors A handler for testing a semiconductor device which is used when testing the fabricated semiconductor device. The handler for testing a semiconductor device includes a stacker to supply and accommodate a customer tray and a position selecting device to move the stacker and select a position of the stacker. By efficiently operating the stacker, the handler is able to continuously handle a large amount of semiconductor devices in a same testing process or continuously handle semiconductor devices in different lots, and equipment is prevented from becoming larger or having more complex designs so that required space, production costs and manpower are reduced and operating rates are improved.
US09343339B2	Coating method and coating apparatus A coating head is constructed of a solvent feed mechanism connected to a forward side in a direction of movement of a coating solution feed mechanism, and a gas jet mechanism connected to a rearward side in the direction of movement. While moving the coating head relative to a substrate, a solvent is supplied onto the substrate from the solvent feed mechanism, then a coating solution is supplied onto a film of the solvent from the coating solution feed mechanism, and finally a gas is jetted to an uneven surface of the coating solution from the gas jet mechanism to smooth a thin film surface of the coating solution.
US09343330B2	Compositions for polishing aluminum/copper and titanium in damascene structures The invention provides a chemical-mechanical polishing composition for polishing a substrate. The polishing composition comprises an oxidizing agent, calcium ion, an organic carboxylic acid, and water, wherein the polishing composition has a pH of about 1.5 to about 7. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition.
US09343327B2	Methods for etch of sin films A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.
US09343326B2	CMP slurry composition for polishing an organic layer and method of forming a semiconductor device using the same A chemical mechanical polishing (CMP) slurry composition for polishing an organic layer and a method of forming a semiconductor device using the same are disclosed. The CMP slurry composition may include from 0.001% to 5% by weight of oxide-polishing particles; from 0.1% to 5% by weight of an oxidant; from 0% to 5% by weight of a polishing regulator; from 0% to 3% by weight of a surfactant; from 0% to 3% by weight of a pH regulator; and from 79% to 99.889% by weight of deionized water. The use of the CMP slurry composition makes it possible to allow a silicon-free organic layer to be polished with a selectivity higher than 6:1 with respect to an oxide layer.
US09343325B2	Trilayer SIT process with transfer layer for FINFET patterning Improved sidewall image transfer (SIT) techniques are provided. In one aspect, a SIT method includes the following steps. An oxide layer is formed on a substrate. A transfer layer is formed on a side of the oxide layer opposite the substrate. A mandrel layer is formed on a side of the transfer layer opposite the oxide layer. The mandrel layer is patterned to form at least one mandrel. Sidewall spacers are formed on opposite sides of the at least one mandrel. The at least one mandrel is removed, wherein the transfer layer covers and protects the substrate during removal of the at least one mandrel. The transfer layer is etched using the sidewall spacers as a hardmask to form a patterned transfer layer. The oxide layer and the sidewall spacers are removed from the substrate. The substrate is etched using the patterned transfer layer as a hardmask.
US09343323B2	Method of producing aperture member In one embodiment, an aperture member producing method includes applying a charged particle beam to a plurality of chip areas on a first substrate while changing a writing condition to write a first pattern corresponding to an aperture opening, processing the first substrate based on the written first pattern to form a second pattern, cutting out a chip area provided with the second pattern having desired accuracy from the first substrate to produce a template, allowing the template to come into contact with a resist overlying a front surface of a second substrate, separating the template from the hardened resist to pattern the resist with a transfer pattern, processing the second substrate using the transfer pattern as a mask to form a first recess, and etching a rear surface of the second substrate to form a second recess communicating with the first recess.
US09343321B2	Chemical mechanical planarization using nanodiamond A method for chemical mechanical polishing of a substrate includes polishing the substrate at a stock removal rate of greater than about 2.5 Å/min to achieve a Ra of not greater than about 5.0 Å. The substrate can be a III-V substrate or a SiC substrate. The polishing utilizes a chemical mechanical polishing slurry comprising ultra-dispersed diamonds and at least 80 wt % water.
US09343319B2	Inspection method and method of manufacturing semiconductor device First, a product to be inspected is prepared. The product to be inspected includes a substrate and a first film formed on the substrate. TDS is performed while the temperature of the product to be inspected is raised to 1,000° C. or higher, and the quality of the product to be inspected is determined by checking for the presence or absence of a peak at 1,000° C. or higher. Meanwhile, the substrate is, for example, a semiconductor substrate such as a silicon substrate. In addition, the rate of temperature rise is, for example, equal to or higher than 40° C./min and equal to or lower than 80° C./min. The upper limit of the temperature of TDS is, for example, 1,300° C.
US09343317B2	Methods of forming silicon-containing dielectric materials and semiconductor device structures A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
US09343316B2	Methods of forming memory cells with air gaps and other low dielectric constant materials Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a substrate. A conductive material is formed between the first dielectric material and the second dielectric material. An opening is formed through the first dielectric material, the second dielectric material, and the conductive material. The conductive material is recessed laterally from the opening to form a recessed control gate and to expose portions of the first dielectric material and the second dielectric material. Portions of a third dielectric material are formed over the exposed portions of the first dielectric material and the second dielectric material and a charge storage element is formed between the portions of the third dielectric material and adjacent to the recessed control gate. Portions of the third dielectric material are substantially removed. Additional methods, as well as apparatuses, are disclosed.
US09343311B2	Substrate treatment method A substrate having a native oxide film formed on its surface is heated in a hydrogen atmosphere to reduce silicon dioxide to hydrogen. Additionally, silicon near an interface between the native oxide film and the substrate is hydrogen-terminated. A hydrogen-introduced layer containing silicon bonded with hydrogen is accordingly formed on the substrate surface. A dopant solution is supplied to the substrate surface having the hydrogen-introduced layer formed thereon, and hydrogen in the hydrogen-introduced layer is replaced with a dopant, thereby introducing the dopant into the substrate surface. A relatively large thickness of the hydrogen-introduced layer formed through the reduction of the native oxide film allows the dopant to be uniformly introduced into the substrate surface for a required depth. A flashing light is emitted to the substrate surface containing the introduced dopant, activating the dopant.
US09343310B1	Methods of forming conductors and semiconductors on a substrate An apparatus and a method are disclosed for forming electrical conductors and/or semiconductors on a glass substrate. The electrical conductors and/or semiconductors are formed by applying a conducting material or a semiconductor material to a surface of the glass substrate and irradiating the interface with a focused laser beam transmitted through the glass. An electrical conductor may be formed on a glass substrate or a semiconductor substrate to provide an electrical antenna for radio frequency communication.
US09343309B1	Lateral oxidation process flows Methods of laterally oxidizing features of a patterned substrate are described. A capping layer may be disposed above lateral features to laterally confine the oxidation. The oxidizable features may be material patterned near the optical resolution of a photolithography system using a high-resolution photomask. The oxidizable features may be wider than the spaces between the oxidizable features and may be about three times the width of the spaces. Oxidized portions may be formed on either side of repeated oxidizable features. The unoxidized portions may then be removed as part of a self-aligned double patterning (SADP) process. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features.
US09343297B1	Method for forming multi-element thin film constituted by at least five elements by PEALD A single-phase multi-element film constituted by at least four elements is formed on a substrate by plasma-enhanced atomic layer deposition (PEALD) conducting one or more process cycles. Each process cycle includes: (i) forming an integrated multi-element layer constituted by at least three elements on a substrate by PEALD using at least one precursor; and (ii) treating a surface of the integrated multi-element layer with a reactive oxygen, nitrogen, and/or carbon in the absence of a precursor for film formation so as to incorporate at least one new additional element selected from oxygen, nitrogen, and carbon into the integrated multi-element layer.
US09343296B2	Apparatuses and methods for depositing SiC/SiCN films via cross-metathesis reactions with organometallic co-reactants Disclosed herein are methods of forming SiC/SiCN film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer. The reaction results in the forming of the film layer. In some embodiments, a byproduct is also formed which contains substantially all of the metal of the organometallic ligand transfer reagent, and the methods may further include removing the byproduct from the processing chamber. Also disclosed herein are semiconductor processing apparatuses for forming SiC/SiCN film layers.
US09343293B2	Flowable silicon—carbon—oxygen layers for semiconductor processing Methods are described for forming a dielectric layer on a patterned substrate. The methods may include combining a silicon-and-carbon-containing precursor and a radical oxygen precursor in a plasma free substrate processing region within a chemical vapor deposition chamber. The silicon-and-carbon-containing precursor and the radical oxygen precursor react to deposit a flowable silicon-carbon-oxygen layer on the patterned substrate. The resulting film possesses a low wet etch rate ratio relative to thermal silicon oxide and other standard dielectrics.
US09343291B2	Method for forming an interfacial layer on a semiconductor using hydrogen plasma Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system. Such a plasma treatment can be executed with substrate temperatures less than 380 degrees Celsius, and even down to about 200 degrees Celsius or below.
US09343289B2	Chemistry compatible coating material for advanced device on-wafer particle performance To manufacture a coating for an article for a semiconductor processing chamber, the article including a body of at least one of Al, Al2O3, or SiC, and a ceramic coating on the body. The ceramic coating includes a compound comprising Y2O3 in a range from about 50 mol % to about 75 mol %, ZrO2 in a range from about 10 mol % to about 30 mol %, and Al2O3 in a range from about 10 mol % to about 30 mol %, wherein the number of nodules per inch is in a range from about 30 nodules to about 45 nodules and the porosity is in a range from about 2.5% to about 3.2%.
US09343282B2	Systems and methods for using interleaving window widths in tandem mass spectrometry Systems and methods are provided for analyzing a sample using overlapping measured mass selection window widths. A mass range of a sample is divided into two or more target mass selection window widths using a processor. The two or more target widths can have the same width or variable widths. A tandem mass spectrometer is instructed to perform two or more fragmentation scans across the mass range using the processor. Each fragmentation scan of the two or more fragmentation scans includes a measured mass selection window width. The two or more measured widths of the two or more fragmentation scans can have the same width or variable widths. At least two of the two or more measured mass selection window widths overlap. The overlap in measured mass selection window widths corresponds to at least one target mass selection window width.
US09343280B2	Multi-pressure stage mass spectrometer and methods A mass spectrometer includes a plurality of guide stages for guiding ions between an ion source and an ion detector along a guide axis. Each of the guide stages is contained within one of a plurality of adjacent chambers. Pressure in each of the plurality of chambers is reduced downstream along the guide axis to guide ions along the axis. Each guide stage may further include a plurality of guide rods for producing a containment filed for containing ions about the guide axis, as they are guided to the detector.
US09343278B2	Data independent acquisition of product ion spectra and reference spectra library matching Systems and methods are disclosed for quantitating detectable compounds of a sample. Sample product ion spectra are received for each mass selection window for each time step. The received sample product ion spectra are searched for the presence of known compounds of interest with known product ion spectra by retrieving the known product ion spectra from a library, retrieving the sample product ion spectra corresponding to the precursor mass selection window expected to contain a precursor ion corresponding to the known product ion spectra, generating product ion traces in time for the sample product ion spectra for the known product ion spectra, calculating a score for the product ion traces and product ion spectra that represents how well known product ions and sample product ions match, and calculating a quantitative value for the known compound from the product ion traces when the score exceeds a threshold value.
US09343277B2	Parsing events during MS3 experiments Systems and methods are provided for reducing the time period of a CID event of an MS3 experiment and making the overall fragmentation event more generic. A CID event of an MS3 experiment performed on a sample by a mass spectrometer is divided into two time periods using a processor. At the beginning of a first time period of the CID event, the mass spectrometer is instructed to both open a pulse valve in order to pulse a collision gas and apply a first CID voltage. At the beginning of a second time period of the CID event, the mass spectrometer is instructed to both close the pulse valve and apply a second CID voltage. The mass spectrometer is pumped down during the second time period. The overlap in time of the pump down and CID reduces the overall time period of the CID event.
US09343274B2	Process kit shield for plasma enhanced processing chamber Apparatus for processing substrates is disclosed herein. In some embodiments, an apparatus includes a first shield having a first end, a second end, and one or more first sidewalls disposed between the first and second ends, wherein the first end is configured to interface with a first support member of a process chamber to support the first shield in a position such that the one or more first sidewalls surround a first volume of the process chamber; and a second shield having a first end, a second end, and one or more second sidewalls disposed between the first and second ends of the second shield and about the first shield, wherein the first end of the second shield is configured to interface with a second support member of the process chamber to support the second shield such that the second shield contacts the first shield to form a seal therebetween.
US09343273B2	Substrate holders for uniform reactive sputtering A substrate holder for a substrate including a frame body having an opening for the placement of the substrate. The frame body also includes a hollow portion therein. The substrate holder may be used in a sputtering apparatus for sputtering material onto the substrate. The substrate holder is particularly advantageous in the manufacturing of magnetic recording medium.
US09343272B1	Self-aligned process Methods of forming self-aligned structures on patterned substrates are described. The methods may be used to form metal lines or vias without the use of a separate photolithography pattern definition operation. Self-aligned contacts may be produced regardless of the presence of spacer elements. The methods include directionally ion-implanting a gapfill portion of a gapfill silicon oxide layer to implant into the gapfill portion without substantially ion-implanting the remainder of the gapfill silicon oxide layer (the sidewalls). Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that the gapfill portions of silicon oxide are selectively etched relative to other exposed portions exposed parallel to the ion implantation direction. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.
US09343270B2	Plasma processing apparatus A plasma processing apparatus includes a processing chamber configured to partition a processing space and a microwave generator configured to generate microwaves for plasma excitation. Further, the plasma processing apparatus includes a dielectric member mounted in the processing chamber so as to seal the processing space, and configured to introduce the microwaves generated by the microwave generator into the processing space. Further, the plasma processing apparatus includes an injector mounted in the dielectric member, and configured to supply the processing gas made in a plasma state due to the microwaves to the processing space through a through-hole formed in the dielectric member. Further, the plasma processing apparatus includes a waveguide plate made of a dielectric material mounted in the injector so as to surround the through-hole of the dielectric member, and configured to guide the microwaves propagated into the dielectric member toward the through-hole to an inside of the injector.
US09343269B2	Plasma processing apparatus A plasma processing apparatus has a long chamber having an opening portion, a gas supply apparatus that supplies gas into the chamber, a spiral coil having a long shape in parallel with the longitudinal direction of the chamber, a high-frequency electric power supply connected to the spiral coil, a base material mounting table which is disposed opposite to the opening portion and holds a base material and a moving mechanism which is disposed in parallel with the longitudinal direction of the chamber and the longitudinal direction of the opening portion, and enables the chamber and the base material mounting table to relatively move perpendicularly with respect to the longitudinal direction of the opening portion.
US09343268B2	Multi charged particle beam writing apparatus and multi charged particle beam writing method In accordance with one aspect of this invention, a multi charged particle beam writing apparatus includes an aperture member, in which a plurality of openings are formed, configured to form multi-beams by making portions of the charged particle beam pass through the plurality of openings; a plurality of blankers configured to perform blanking-deflect regarding beams corresponding to the multi-beams; a writing processing control unit configured to control writing processing with a plurality of beams having passed through different openings among the plurality of openings being irradiated on the target object at a predetermined control grid interval; and a dose controlling unit configured to variably control a dose of a beam associated with deviation according to a deviation amount when an interval between the plurality of beams irradiated is deviated from the control grid interval.
US09343267B2	Method and system for dimensional uniformity using charged particle beam lithography A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.
US09343265B2	Charged particle beam irradiation apparatus The purpose of the present invention is to provide a charged particle beam irradiation apparatus of a relatively simple structure which performs cooling on a sample or a sample stage. An aspect of the present invention comprises: a charged particle source; a sample stage; and a driving mechanism that comprises a transmission mechanism which transmits a driving force to move the sample stage. The charged particle beam irradiation apparatus comprises a container capable of accommodating an ionic liquid (12), wherein the container is disposed in a vacuum chamber. When the ionic liquid (12) is accommodated in the container, at least a portion of the transmission mechanism is provided at a position submerged in the ionic liquid (12).
US09343262B2	Ion implantation apparatus, beam parallelizing apparatus, and ion implantation method An ion implantation apparatus includes a beam parallelizing unit and a third power supply unit. The beam parallelizing unit includes an acceleration lens, and a deceleration lens disposed adjacent to the acceleration lens in an ion beam transportation direction. The third power supply unit operates the beam parallelizing unit under one of a plurality of energy settings. The plurality of energy settings includes a first energy setting suitable for transport of a low energy ion, and a second energy setting suitable for transport of a high energy ion beam. The third power supply unit is configured to generate a potential difference in at least the acceleration lens under the second energy setting, and generate a potential difference in at least the deceleration lens under the first energy setting. A curvature of the deceleration lens is smaller than a curvature of the acceleration lens.
US09343261B2	Desktop electron microscope and combined round-multipole magnetic lens thereof A combined round-multipole magnetic lens comprises a coil bracket, a first pole piece and a second pole piece. At least a first pole shoe of the first pole piece on the coil support and at least a second pole shoe of the second pole piece under the coil support respectively extend towards the central axis. The first pole shoe and the second pole shoe are symmetric according to the central axis, or the first pole shoes and the second pole shoes are respectively symmetrically arranged, and the angle difference between the first pole shoe and the adjacent second pole shoes is 360/2N degrees. A magnetic circuit gap is formed between the first pole shoe and the adjacent second pole shoe, for generating a magnetic field distribution of multi-poles and reducing the volume and the number of power supplies.
US09343259B2	GCIB nozzle assembly A nozzle assembly used for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the nozzle assembly includes two or more conical nozzles that are aligned such that they are both used to generate the same GCIB. The first conical nozzle may include the throat that initially forms the GCIB and the second nozzle may form a larger conical cavity that may be appended to the first conical nozzle. A transition region may be disposed between the two conical nozzles that may substantially cylindrical and slightly larger than the largest diameter of the first conical nozzle.
US09343258B2	Magnetic actuator for a circuit breaker arrangement An exemplary magnetic actuator for a circuit breaker arrangement includes a coil, a core with a groove for accommodating a section of the coil, and a movable plate configured to be attracted by the core. When a magnetic field is generated by the coil, the movable plate actuates the circuit breaker arrangement based on the attraction to the core. The magnetic actuator also includes a position locker for locking the coil in the groove. The position locker having a locking part protruding away from the core and over a section of the coil not accommodated in the groove.
US09343256B1	Electrical switching apparatus, and indication assembly and trip cam therefor A trip cam is for an indication assembly of an electrical switching apparatus. The electrical switching apparatus includes a housing and a number of poles. Each of the number of poles includes a pair of separable contacts and an operating mechanism structured to open and close the separable contacts. The indication assembly includes a cradle member. The trip cam includes: a mounting portion; a transfer leg extending from the mounting portion, the transfer leg being structured to cooperate with each of the number of poles; a driving leg extending from the mounting portion in a first direction, the driving leg being structured to be driven by the cradle member; and a trip indicator leg including a base portion. The base portion extends from the mounting portion in a second direction generally opposite the first direction.
US09343253B2	Method of placing a thermal fuse on a panel A reflowable thermal fuse includes a positive-temperature-coefficient (PTC) device that defines a first end and a second end, a conduction element that defines a first end and a second end in electrical communication with the second end of the PTC device, and a restraining element that defines a first end in electrical communication with the first end of the PTC device and a second end, in electrical communication with a second end of the conduction element. The restraining element is adapted to prevent the conduction element from coming out of electrical communication with the PTC device in an installation state of the thermal fuse. During a fault condition, heat applied to the thermal fuse diverts current flowing between the first end of the PTC device and the second end of the conduction element to the restraining element, causing the restraining element to release the conduction element and activate the fuse.
US09343252B2	Arc extinguishing contact assembly for a circuit breaker assembly An arc extinguishing contact assembly for a circuit breaker assembly is provided. The arc extinguishing contact assembly includes a fixed contact assembly, a movable contact assembly and an arc extinguishing assembly. The fixed contact assembly includes a fixed arc contact assembly, a fixed main contact assembly, and a number of movable, intermediate arc contact assemblies. The movable contact assembly includes a movable arc contact assembly and a movable main contact assembly. The arc extinguishing assembly is structured to extinguish an arc generated as the movable contact assembly moves between an open, first position and a closed, second position.
US09343251B2	Bi-directional direct current electrical switching apparatus including small permanent magnets on ferromagnetic side members and one set of arc splitter plates An electrical switching apparatus for bi-directional direct current switching and interruption includes separable contacts, an operating mechanism to open and close the contacts, and an arc chute. The arc chute includes two ferromagnetic side members each having a first side and an opposite second side, the first side of a second ferromagnetic side member facing the first side of a first ferromagnetic side member, a first permanent magnet disposed on the first side of the first side member, a second permanent magnet disposed on the first side of the second side member, and a single set of a plurality of arc splitter plates disposed between the permanent magnets. The permanent magnets are substantially smaller in size than each of the side members. The arc chute is divided into two arc chambers each of which is for a corresponding direction of DC flow through the contacts.
US09343250B2	Compact bus bar assembly, switching device and power distribution system A contact bus bar assembly for supplying power to a load, and further pertains to a switching device which can be connected to such a compact bus bar assembly, and to a power distribution system. The bus bar assembly includes at least two electrically conductive tracks which are at least partly covered by an electrically insulating cover. An outer surface of said insulating cover is provided with a plurality of ribs arranged in a region connecting pin terminals. The switching device may additionally comprise a separating element provided with a plurality of second ribs.
US09343245B2	Molded case circuit breaker A molded case circuit breaker, includes: a case; a power side terminal portion and a load side terminal portion formed at two sides of the case; a mounter installed at the terminal portion with a structure to enclose a terminal connector connected to the terminal portion, wherein the mounter includes: a mounting surface for mounting the terminal connector; insulation surfaces extending from two side edges of the mounting surface, and spaced from each other; and a cover surface having an opening, and formed on outer side surfaces of the insulation surfaces so as to cross the insulation surfaces and the mounting surface. Under such configuration, a regulated insulation distance can be obtained, and the terminal connector can be supported more stably.
US09343240B2	Polarizable ion-conducting material A polarizable ion-conducting material. The material contains mobile ions and a matrix formed of a polymer having ionic groups of a charge opposite to that of the mobile ions, wherein the material has a polarization of at least 0.2 mC/g, a capacitance of at least 0.1 mF/g, and a polarization retention time of at least 5 seconds. Also disclosed is a device containing such a polarizable ion-conducting material.
US09343239B2	Solid electrolytic capacitor and improved method for manufacturing a solid electrolytic capacitor An improved process for forming a capacitor, and improved capacitor formed thereby is described. The process includes: providing an anode comprising a dielectric thereon; applying a first layer of an intrinsically conducting polymer on the dielectric to form a capacitor precursor; applying at least one subsequent layer of an intrinsically conducting polymer on the first layer from a dispersion; and treating the capacitor precursor at a temperature of at least 50° C. no more than 200° C. at a relative humidity of at least 25% up to 100%, or fusing the layered structure by swelling the layered structure with a liquid and at least partially removing the liquid.
US09343238B2	Capacitor for multiple replacement applications A capacitor provides a plurality of selectable capacitance values, by selective connection of six concentrically wound capacitor sections of a capacitive element each having a capacitance value. The capacitor sections each have a respective section element terminal at a first end of the capacitive element and the capacitor sections have a common element terminal at a second end of the capacitive element. A pressure interrupter cover assembly is sealingly secured to the open end a case for the element and has a deformable cover with a centrally mounted common cover terminal and a plurality of section cover terminals mounted at spaced apart locations. A conductor frangibly connects the common element terminal of the capacitive element to the common cover terminal and conductors respectively frangibly connect the capacitor section terminals to the section cover terminals.
US09343237B2	Vertical metal insulator metal capacitor A capacitor structure includes at least two capacitors. A first electrode includes a bottom conductive plane and first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The bottom conductive plane has a first area and a first shape. At least two second electrodes include top conductive planes and second vertical conductive structures. A combined area of the top conductive planes and a gap area between adjacent top conductive planes has a second area and a second shape. The first area and the second area are about the same and the first shape and the second shape are about the same. An insulating structure is disposed between the first electrode and the second electrodes. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other. The capacitors share the bottom conductive plane and have separate top conductive planes.
US09343236B2	Multilayer ceramic capacitor and board having the same mounted thereon A multilayer ceramic capacitor may include: a ceramic body; a first internal electrode is spaced apart from first and second end surfaces by a predetermined distance and includes first and second lead portions which are spaced apart from each other and exposed to a first main surface; and a second internal electrode is spaced apart from the first and second end surfaces by a predetermined distance and includes a third lead portion positioned between the first and second lead portions and exposed to the first main surface. The ceramic body may further include first and second dummy electrodes, a first dummy electrode being disposed on a dielectric layer on which the first internal electrode is disposed, and a second dummy electrode being disposed on a dielectric layer on which the second internal electrode is disposed.
US09343234B2	Monolithic ceramic electronic component A monolithic ceramic electronic component includes an outer electrode including a first plating layer formed directly on a component body by electroless plating so as to cover an exposed portion distribution region including exposed portions of a plurality of inner electrodes and a second plating layer formed by electrolytic plating so as to cover the first plating layer. An amount of extension of the first plating E1 and an amount of extension of the second plating E2 satisfy the relationship E1/(E1+E2)≦20%, where E1 represents a distance from an edge of the exposed portion distribution region to an edge of the first plating layer, and E2 represents a distance from the edge of the first plating layer to an edge of the second plating layer.
US09343231B2	Methods for manufacture a capacitor with three-dimensional high surface area electrodes A capacitor, and methods of its manufacture, having improved capacitance efficiency which results from increasing the effective area of an electrode surface are disclosed. An improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer.
US09343229B2	Multilayer ceramic capacitor and board having the same mounted thereon A multilayer ceramic capacitor may include: a ceramic body in which dielectric layers having an average thickness of 0.2 μm to 2.0 μm are stacked; an active layer configured to form capacitance by including first and second internal electrodes alternately exposed to both end surfaces of the ceramic body, having at least one of the dielectric layers interposed therebetween; an upper cover layer formed on the active layer; a lower cover layer formed below the active layer and being thicker than the upper cover layer; and first and second external electrodes covering the end surfaces of the ceramic body. At least one edge of the ceramic body in length, width, and thickness directions may be rounded. When a radius of curvature of the edge is defined as R and a thickness of the upper cover layer is defined as D, R/D may be in a range of 0.1 to 0.7.
US09343228B2	Laminated inductor and manufacturing method thereof A laminated inductor may include a body having a plurality of ceramic layers stacked therein, a plurality of conductive patterns formed on the ceramic layers, and via electrodes disposed between the ceramic layers and connecting the conductive patterns disposed in a vertical direction to form a coil. Each of the conductive patterns may include a plurality of unit patterns disposed in parallel to be spaced apart from each other on each of the ceramic layers.
US09343224B2	Coplanar energy transfer An external transmitter inductive coil can be provided in, on, or with a belt designed to be placed externally around a part of a body of a patient. An implantable device (such as a VAD or other medical device) that is implanted within the patient's body has associated with a receiver inductive coil that gets implanted within that part of the patient's body along with the device. The externally-located transmitter inductive coil inductively transfers electromagnetic power into that part of the body and thus to the receiver inductive coil. The implanted receiver inductive coil thus wirelessly receives the inductively-transferred electromagnetic power, and operates the implant.
US09343218B2	Electromagnetic actuators and monitoring thereof An assembly includes an electromagnetic actuator (80) and a voltage response arrangement (26) to enable the position of the armature (1) within the actuator to be monitored. The actuator includes two coils (4) joined together in series, the armature being switchable between at least two magnetically latched stable rest positions by passing a current pulse through the coils, and an output contact (82) electrically coupled to the junction (24) between the coils to facilitate monitoring of the voltage at the junction. The voltage response arrangement (26) is electrically coupled to the output contact (82) so as to provide an output signal giving an indication of the position of the armature (1) in response to the voltage generated on the output contact when a current pulse is passed through the coils (4). A method of monitoring the armature position is also provided.
US09343214B2	Magnetic article holder A magnetic article holder includes a first flexible panel, a second flexible panel, a plurality of pockets, a plurality of magnets, and a plate. The first flexible panel has a first outer surface and a first inner surface opposite to the first outer surface. The second flexible panel has a second outer surface and a second inner surface opposite to the second outer surface. The pockets are defined between the first inner surface and the second outer surface. The pockets are at least partially isolated from one another. The magnets are each respectively positioned in one of the plurality of pockets. The plate is spaced from the first outer surface. The plate is magnetically engaged with each of the first plurality of magnets.
US09343212B2	Reactor A reactor includes: a bobbin including flanges at ends of a winding range of a winding, at least one of the flanges being provided with a slit or a hole; a coil formed in a shape in which the winding having a lead portion is wound around the bobbin, the coil being molded by resin, and the lead portion penetrating through the slit or the hole; and a plate through which the lead portion of the coil penetrates, the plate contacting with a circumferential edge of the slit or the hole of the flange so as to close the slit or the hole.
US09343209B2	Open-celled, porous shaped body for heat exchangers An open-cell porous shaped body for heat exchangers, and process for making same, comprising a thermomagnetic material selected from, for example, a compound of the general formula (I): (AyB1−y)2+δCwDxEz (I) where A is Mn or Co; B is Fe, Cr or Ni; at least two of C, D and E are different, have a non-vanishing concentration and are selected from P, B, Se, Ge, Ga, Si, Sn, N, As and Sb, where at least one of C, D and E is Ge or Si; δ is a number from −0.1 to 0.1; and w, x, y, z are each a number from 0 to 1, where w+x+z=1.
US09343206B2	Electrically-driven phase transitions in functional oxide heterostructures A tunable resistance system includes a layer of a first functional material deposited on a component of the system. The first functional material undergoes a phase transition at a first critical voltage. An insulating layer is deposited upon the layer of first functional material. A layer of a second functional material deposited on the insulating layer. The second functional material undergoes a phase transition at a second critical voltage. The insulating layer is configured to induce a stress on the layer so as to change the first critical voltage. In this way, the resistance of the system is tunable, allowing the system to undergo multi-stage electrical switching of resistive states.
US09343203B2	Method and apparatus for forming oriented nanowire material and method for forming conductive structure The present invention provides a method and an apparatus for forming an oriented nanowire material as well as a method for forming a conductive structure, which can be used to solve the problem of imperfect process for forming oriented nanowire material in prior art. The method for forming an oriented nanowire material of the present invention comprises: forming a liquid film in a closed frame by a dispersion containing nanowires; expanding the closed frame in a first direction so that the liquid film expands in the first direction along with the closed frame; contracting the closed frame in the first direction so that the liquid film contracts in the first direction along with the closed frame; transferring the contracted liquid film to a substrate; and curing the liquid film to form an oriented nanowire material on the substrate.
US09343200B2	Electrical and/or telecommunications cables with retro-reflective integral covering for use in aggressive environments with little or zero visibilty and the method for the production thereof An electric and/or telecommunications cables having retro-reflective integral covers to be used in harsh environments with low or null visibility and the manufacturing process thereof. The cable comprises a core capable of incorporating a plurality of electric and/or telecommunications conductors, reinforcement elements and/or filler elements; a first protective cover layer wrapping the core; at least one reflective tape including visible external light retro-reflective elements, and wrapping the first protective cover layer, which constitutes a second cover layer; and a third protective cover layer wrapping the second cover layer, constituted by the reflective tape having retro-reflective elements and the first protective cover layer.
US09343197B2	Insulated wire and coil An insulated wire includes a conductor, and an insulating covering layer including a first insulation layer formed around the conductor and a second insulation layer formed around the first insulation layer. An elastic modulus of the second insulation layer at 300° C. is not less than 300 MPa, and a relative permittivity of the insulating covering layer is not more than 3.0.
US09343190B2	Apparatus for screening off radiation during the sterilization of containers An apparatus for the sterilization of containers with a conveying device which conveys the containers along a pre-determined conveying path (P), with a sterilization device which acts upon at least one area of the containers with charge carriers in the course of the sterilization, with a screening apparatus for screening off beams from the environment, which has at least two screening bodies which are arranged with respect to each other in such a way that one screening body is situated on the side of the screening apparatus facing the conveying path (P) and one screening body is situated on the one facing away from it, wherein the screening bodies are thermally insulated from each other.
US09343186B2	Semiconductor storage device A semiconductor storage device has a cell array, a redundant array provided logically separated from the cell array, a cache memory having a storing area of data read from or written in the cell array by one access, defective column storage to store a column address of a defective column in the cell array, a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage, and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area at the generation timing of the clock accessing the divided page buffer area.
US09343184B2	Soft post package repair of memory devices Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
US09343180B2	Switched interface for stacked-die memory architecture with redundancy for substituting defective memory cells Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
US09343179B2	Word line address scan A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.
US09343176B2	Low-pin-count non-volatile memory interface with soft programming capability A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines.
US09343165B2	Dynamic drive strength optimization A system for optimizing drive strength may be utilized for identifying the maximum data transfer rate for different devices and different device configurations. The drive strength may be optimized for input/output (I/O) devices by measuring voltage drops on I/O power supply using different test patterns. The maximum drive strength is identified that satisfies a limit or threshold for the allowed voltage drop level. The test pattern may include a simultaneous toggling of each I/O device. A slew rate for the device may be utilized along with the drive strength for identifying the maximum data transfer rate.
US09343163B2	Semiconductor memory device and operating method based upon a comparison of program data and read data thereof A semiconductor memory device and an operating method of the semiconductor memory device change a read voltage used in a read operation by performing a moving read operation, a randomize operation, and a program/erase compensation operation independently or in combination, thereby stably performing the read operation without an error and reducing a time for the read operation even when distribution of threshold voltages of the memory cells is changed according to a program/erase cycling effect or a retention effect.
US09343157B2	Writing into an EEPROM on an I2C bus An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.
US09343155B1	Memory as a programmable logic device Methods for programming, methods for operating, and memories are disclosed. One such method for programming includes programming a group of memory cells such that a series string of memory cells of the group of memory cells is programmed to provide a logical function responsive to an input minterm whose variables are coupled to respective, associated memory cells.
US09343154B2	Nonvolatile memory device and driving method thereof According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.
US09343153B2	De-duplication in flash memory module Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.
US09343150B2	Programmable logic device with resistive change memories A programmable logic device includes: a first memory element including a first electrode connected to a first wiring line, a second electrode, and a first resistive change layer, a resistance between the first and second electrodes being changed from a low-resistance state to a high-resistance state by applying, to the second electrode, a voltage higher than a voltage applied to the first electrode; a second memory element including a third electrode connected to the second electrode, a fourth electrode connected to a second wiring line, and a second resistive change layer, a resistance between the third and fourth electrodes being changed from a low-resistance state to a high-resistance state by applying, to the fourth electrode, a voltage higher than a voltage applied to the third electrode; and a first transistor, of which a gate is connected to the second electrode and the third electrode.
US09343142B2	Nanowire floating gate transistor A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.
US09343141B2	Reprogramming memory with single program pulse per data state Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. After completion of a full programming pass, a verify test is performed to identify cells for which reprogramming is warranted. The reprogramming includes a single program pulse for each target data state, where each program pulse is longer than in the full programming pass. The pulse widths can be optimized based on factors such as a programming speed or a threshold voltage distribution width from the full programming pass.
US09343140B2	Boosted read write word line One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.
US09343135B2	Physically unclonable function based on programming voltage of magnetoresistive random-access memory One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage.
US09343134B2	Method and apparatus for increasing the reliability of an access transitor coupled to a magnetic tunnel junction (MTJ) A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.
US09343133B1	Apparatuses and methods for setting a signal in variable resistance memory An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (IREAD) through the STT memory cell and to set a pulse to write the STT memory cell using IREAD. Additional embodiments are disclosed.
US09343130B2	Antiferromagnetic storage device An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero, two or more stable magnetic states, and an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store data at ultra-high densities. An antiferromagnetic nanostructure according to another embodiment includes multiple arrays each corresponding to a bit. Each array has at least eight antiferromagnetically coupled magnetic atoms. Each array has at least two readable magnetic states that are stable for at least one picosecond. Each array has a net magnetic moment of zero or about zero. No external stabilizing structure exerts influence over the arrays for stabilizing the arrays. Each array has 100 atoms or less along a longest dimension thereof.
US09343124B1	Method and system for operating a multi-port memory system A method and system for operating a multi-port memory system are disclosed. A memory controller may service read requests by accessing requested data from an external memory and communicating it to the requesting memory ports for access by devices coupled to the memory ports. A shared memory of the memory controller may be used to temporarily store data if a buffer associated with a requesting device is full. To reduce the ability for a slower memory port to occupy the shared memory and cause faster memory ports to be underserviced, the memory controller may advantageously regulate or limit issuance of read requests by memory ports operating at slower clock frequencies. The memory ports may be regulated independently of one another based on at least one respective attribute of each memory port, at least one attribute of the external memory, etc.
US09343121B2	Storage device, including nonvolatile memory and memory controller, operating method of storage device and method of accessing storage device An operating method of a storage device is provided. The storage device includes a nonvolatile memory and a memory controller to control the nonvolatile memory. Temperature is detected. A current weighted time is calculated using the temperature. Data is read from the nonvolatile memory using a read voltage level which is adjusted based on the current weighted time. The current weighted time is determined according to an amount of charges leaked from memory cells storing the data at the temperature.
US09343116B2	Providing power availability information to memory The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.
US09343112B2	Systems and methods for supplementing content from a server Methods and systems to provide supplemental content to a user who is viewing video or other content. The user's device (through which he will access the video) then provides an identifier of that video to a server or other computing facility. Here, the video identifier is used to identify supplemental content that corresponds to the user's video. The supplemental content is then provided to the user device for the user's consumption. The supplemental content may be structured in such a way that pieces of the supplemental content are accessible at particular points in the video. The piece(s) of the supplemental content available at a particular point in the video will be related to one or more objects that are present at this point. This allows a user to access one or more pieces of supplemental content in a context-specific manner, at a point in the video where the piece(s) of supplemental content are relevant.
US09343109B2	Video editing device A video editing device, when having failed to obtain a portion of high-resolution video data from a video camera through a network, provides, to the user, low-resolution video data which has been previously transferred from the video camera, instead of the portion of the high-resolution video data. In parallel with this, the video editing device automatically searches for the missing high-resolution video data, on a network, using the ID of a video file or the ID of a recording medium, and if it is found, supplements a video which is to be provided to the user, with the found high-resolution video data.
US09343108B2	Information processing apparatus, information processing method, and non-transitory computer readable medium An information processing apparatus includes a display, a selecting unit, and a writing unit. The display displays a list of multiple combinations of multiple types of information synchronously played back as first information. The selecting unit selects a new combination of the multiple types of information from the combinations of the multiple types of information included in the first information displayed by the display. The writing unit writes out the combination of the multiple types of information selected by the selecting unit as second information synchronously played back.
US09343107B2	Windage control in a dual spindle storage device having interleaved storage media An apparatus and associated method are provided whereby first and second spindles operably rotate first and second overlapping storage discs, respectively. First and second data transfer members are operably disposed adjacent storage areas of the respective storage discs. An edge of the first disc moves in a prescribed close spatial separation from a rotating surface of the second spindle so that the second spindle strips windage, generated by the rotation of the first disc, away from the second data transfer member.
US09343104B2	Integrated servo field for memory device A pattern of features of a storage medium includes first features having a first logical state and second features having a second logical state, wherein a cross track dimension of the first features is different from a cross track dimension of the second features. A transducer of a memory device senses the pattern of features and generates a transducer signal. Read circuitry samples the transducer signal at a frequency of a sampling clock signal and generates a read signal from the sampled transducer signal. Servo electronics includes a demodulator that demodulates at least first and second orthogonal frequency components of the read signal. Timing circuitry synchronizes a phase of the sampling clock signal with a phase of the pattern of features using the first orthogonal frequency component. Position error circuitry generates a signal indicating a cross track positional offset of the transducer relative to the features using the first and second orthogonal frequency components.
US09343099B2	Magnetic devices including film structures A device including a magnetic structure, the magnetic structure having a substrate adjacent surface and a second, opposing surface, the magnetic structure having a near field transducer (NFT), wherein the NFT includes gold or an alloy thereof, and is positioned at the second surface an overcoat structure; and a film structure, the film structure positioned between the magnetic structure and the overcoat structure, the film structure having a total thickness of not greater than about 100 Å, and the film structure including: a first interfacial structure having a first and a second opposing surface; a second interfacial structure having a first and a second opposing surface; and an intermediate structure wherein the first surface of the first interfacial structure is positioned adjacent the NFT of the magnetic structure, and the second surface of the second interfacial structure is positioned adjacent the overcoat structure, and the intermediate structure is positioned between the first interfacial structure and the second interfacial structure, and wherein the first interfacial structure includes one or more rare earth elements, one or more alkaline earth metals, one or more alkali metals, or a combination thereof.
US09343098B1	Method for providing a heat assisted magnetic recording transducer having protective pads A method fabricates a heat assisted magnetic recording (HAMR) transducer having an air-bearing surface (ABS) and that is optically coupled with a laser. The method includes providing a waveguide for directing light from the laser toward the ABS and providing a write pole having a pole tip with an ABS location facing the surface. The pole tip is in a down track direction from the waveguide. The method also includes providing at least one shield including a shield pedestal. The shield pedestal is in the down track direction from the pole tip. At least one protective pad is provided adjacent to the write pole and between the ABS location and the shield pedestal.
US09343095B2	Head gimbals assembly, method for manufacturing thermal-assisted magnetic recording and manufacturing equipment of thermal-assisted magnetic recording A HAMR head includes an anti-reflecting (AR) coating on a side opposite (e.g., a flex side) of the air bearing surface (ABS). The anti-reflective coating may include one or more anti-reflective layers. The anti-reflective coating reduces the amount of light reflected back towards a light source unit. A shading layer may be disposed on the anti-reflective coating and may function as a contact electrode as well as reducing stray light escaping from the laser, thus reducing the amount of stray light reaching the ABS.
US09343089B2	Nanoimprint lithography for thin film heads Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.
US09343086B1	Magnetic recording write transducer having an improved sidewall angle profile A method and system provide a magnetic transducer having an air-bearing surface (ABS). The magnetic transducer includes a main pole and at least one coil for energizing the main pole. The main pole includes a pole tip region and a yoke region. The pole tip region includes sidewalls, a bottom and a top wider than the bottom. At least one of the sidewalls forms a first sidewall angle with a down track direction at the ABS and a second sidewall angle with the down track direction at a first distance recessed from the ABS. The first sidewall angle is greater than the second sidewall angle.
US09343080B2	Method and apparatus to prepare listener-interest-filtered works An embodiment of the present invention is a method of presenting at least a portion of an audio or audio-visual work including: (a) retrieving an average speed contour or a democratic speed contour from a database apparatus; and (b) presenting the at least a portion at a playback apparatus using the retrieved average speed contour or democratic speed contour to provide presentation rates.
US09343069B2	Methods and systems for name pronunciation In an embodiment, a system maintains a database of a plurality of persons. The database includes an audio clip of a pronunciation of a name of a first person in the database. The system determines from a calendar database that a second person has an event in common with the first person, and transmits to a device associated with the second person an indication that the database includes the pronunciation of the name of the first person.
US09343061B2	Method and apparatus for converting text information The present invention provides a method and an apparatus for converting text information. The method includes: receiving, by a first terminal, a call or data from a second terminal; obtaining, by the first terminal, according to a mapping relationship between identification information of the second terminal and voice characteristic parameters of an user of the second terminal, the voice characteristic parameters of the user of the second terminal corresponding to the identification information of the second terminal when the first terminal is in a working mode of text-to-voice conversion; and converting, by the first terminal, related text information about the call or data to audio information with the voice characteristic parameters of the user of the second terminal.
US09343059B2	Underwater noise abatement panel and resonator structure A system for reducing noise emissions in underwater environments is presented. The system can be extended to applications in any two-fluid environments where one fluid (gas) is contained in an enclosed resonator volume connected to the outside environment at an open end of the resonator body. The resonators act as gas-containing (e.g., air) Helmholtz resonators constructed into solid panels that are submerged in the fluid medium (e.g., sea water) in the vicinity of a noise generating source. The oscillations of the trapped air volume in the resonators causes reduction of certain noise energy and a general reduction in the transmitted noise in the environment of the system.
US09343052B2	D/A conversion apparatus, D/A conversion method and electric musical instrument In the present embodiment, quantizer output values including variation values corresponding to duty errors of pulse width data (PWM output signals) occurring by the difference of the pull-down/pull-up drive characteristics (drive capabilities) of a buffer are stored in advance in a feedback value memory in a quantizer as feedback values FBV0 to FBV4, and a feedback value FBVn read out from the feedback value memory in response to the quantization of a delta-sigma modulation output is inputted into a subtractor by return input. Then, a quantizer output value including a variation value corresponding to a duty error is subtracted from input data Din, and delta-sigma modulation is performed such that the difference is minimized, whereby the duty error of pulse width data (PWM output signal) is compensated.
US09343051B2	Performance information output control apparatus, keyboard instrument and control method thereof A performance information output control apparatus includes a detection part which detects a plurality of positions of a music performance interface during a single stroke with respect to an operator of a keyboard instrument, the music performance interface including a mechanism that interlocks with the operator, an estimated music-sound generation time analysis part which calculates an estimated music-sound generation time point representing a time point at which music sound according to the single stroke with respect to the operator is estimated to be generated, based on a detection result of the positions of the music performance interface by the detection part, and a music performance information output part which outputs, when the detection result by the detection part is obtained, music performance information representing music performance contents corresponding to the single stroke with respect to the operator prior to the calculated estimated music-sound generation time point.
US09343044B2	Piano extended soft pedal A piano selectively playable in normal and soft modes has multiple piano keys and actions, including a wippen assembly, and multiple piano hammers. A soft mode pedal system includes soft and ultra-soft mode pedals, and a hammer rest rail mounted for movement between normal and soft mode positions. A piano key lift rail is mounted for movement between a normal mode position spaced from lifting contact with the keys and a soft mode position in contact with and lifting the keys and the wippen assemblies. A soft mode pedal linkage assembly between the soft and ultra-soft mode pedals and the hammer rest and piano key lift rails causes movement of the hammer rest rail, piano hammers, the piano keys, and the wippen assemblies upon actuation of the soft mode pedal between normal mode position and soft and ultra-soft mode positions.
US09343042B2	Four-channel display with desaturation and luminance gain A method of presenting an image on a display device having color channel dependent light emission comprising receiving an image input signal including a plurality of three-component input pixel signals; calculating a reduction factor for each input pixel signal dependent upon differences in luminance between blue and other color components; selecting a respective saturation adjustment factor for each color component of each pixel signal; selecting a luminance gain; producing an image output signal having four color components from the image input signal using the reduction factors, saturation adjustment factors, and luminance gain to adjust the luminance and color saturation, of corresponding components of the image input signal; providing a four-channel display device having color channel dependent light emission; and applying the image output signal to the display device to cause it to present an image corresponding to the image output signal.
US09343041B2	Four-channel emissive display system A four-color emissive display system comprises a display and a controller. The controller is configured to receive and process a three-color input image signal, and provide a four-color output image signal to the display. The controller comprises units respectively configured to (1) calculate a blue reduction factor for each pixel, dependent on luminance differences between blue and other color components, (2) produce respective saturation adjustment factors for red, green, and blue, (3) apply the blue reduction factor to reduce blue luminance, and apply the saturation adjustment factors to reduce saturation of other colors, (4) produce the output image signal. An optional sensor is operable to provide a control signal to the controller, whereby display power can be reduced. An optional estimating unit is configured to estimate current required to display the input image signal, whereby the output image signal can be adjusted accordingly.
US09343037B2	Data transmission method and display device Provided is a method capable of performing serial transmission of data whose data values change in short fixed cycles, while suppressing an increase in power consumption. In a liquid crystal controller, data sequence conversion is performed on data included in an input image signal by a first data sequence conversion circuit and a second data sequence conversion circuit every predetermined period of time. The data sequence conversion is performed by reversing the values of predetermined bits of each data. The data obtained after the data sequence conversion is transmitted, as a digital video signal, to a source driver. In the source driver, the same data sequence conversion as that performed by the liquid crystal controller is performed on each data included in the digital video signal by a first data sequence restoring circuit and a second data sequence restoring circuit.
US09343032B2	Goa circuit structure sharing goa pull-down circuits to reduce TFT stress of the goa pull-down circuits A GOA circuit structure includes multiple twined GOA units cascaded with each other. Each twined GOA unit includes a (2N−1)-level GOA unit and a 2N-level GOA unit, which has a first pull-down holding circuit, a second pull-down holding circuit, a third pull-down holding circuit, and a fourth pull-down holding circuit connected with the (2N−1)-level gate signal point (Q(2N−1)) and the 2N-level gate signal point (Q(2N)). Through inputting a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the first pull-down holding circuit, the second pull-down holding circuit, the third pull-down holding circuit, and the fourth pull-down holding circuit are made working alternately. The GOA circuit structure makes each portion work for ¼ time and take rest for ¾ time by sharing the pull-down holding circuit, which can reduce the TFT stress of the pull-down holding circuit.
US09343030B2	Gate driving circuit and display apparatus including the same A gate driving circuit includes N stages (where N is a natural number greater than or equal to 2). The N stages are cascaded, and each of the N stages has a gate line connected thereto. A first stage group includes k stages of the N stages (where k is a natural number less than N), and the first stage group outputs a first output signal in response to a start signal. A second stage group (including N−k stages) generates a second output signal in response to the first output signal and outputs the second output signal to a corresponding gate line. The first stage group includes a first buffer and a second buffer, each of which receives the start signal. A size of the first buffer is smaller than a size of the second buffer.
US09343028B2	Method of driving a gate line, gate drive circuit and display apparatus having the gate drive circuit A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.
US09343021B2	Display device for mitigating the occurrence of undesirable bright lines in an image and a driving method thereof The embodiments of the present invention provide a display device and a driving method thereof, which relates the display technology and can avoid occurrence of bad bright line of the image and improve display quality of the image. The display device may comprise a display panel and a backlight module disposed below the display panel, the display panel may comprise at least one display area, the display area may comprise at least one sub display area, the backlight module may comprise at least one light emitting unit, the light emitting units are in one-to-one correspondence with the sub display areas. Each sub display area may comprise at least one row of pixel units, the pixel units may comprise switch elements. When the switch elements of the first row of pixel units in a sub display area are turned on, the light emitting unit in the backlight module corresponding to the sub display area is in a turn-on state, when the switch elements in the last row of pixel units in a sub display area are turned off, the light emitting unit in the backlight module corresponding to the sub display area is in a turn-off state. The embodiments of the present invention may be applied to the manufacture of the display device.
US09343018B2	Method for driving a liquid crystal display device at higher resolution The resolution of a low-resolution image is made high and a stereoscopic image is displayed. Resolution is made high by super-resolution processing. In this case, the super-resolution processing is performed after edge enhancement processing is performed. Accordingly, a stereoscopic image with high resolution and high quality can be displayed. Alternatively, after image analysis processing is performed, edge enhancement processing and super-resolution processing are concurrently performed. Accordingly, processing time can be shortened.
US09343006B2	Driving system for active-matrix displays Raw grayscale image data, representing images to be displayed in successive frames, is used to drive a display having pixels that include a drive transistor and an organic light emitting device by dividing each frame into at least first and second-frames, and supplying each pixel with a drive current that is higher in the first sub-frame than in the second sub-frame for raw grayscale values in a first preselected range, and higher in the second sub-frame than in the first sub-frame for raw grayscale values in a second preselected range. The display may be an active matrix display, such as an AMOLED display.
US09343005B2	Extruded frame trim arrangement An extrusion member for assembly into a display fabric supporting frame arrangement for enabling the assembly and display of a flexible fabric therewithin. The extrusion member comprises an elongated outer segment for enabling the support of a frameless flexible display in a frame arrangement, and an elongated inner segment for enabling the support of a frameless flexible display in a frame arrangement, wherein either segment or the inner segment, or both the outer segment and the inner segment may peripherally support a flexible display on a common extrusion member assembly.
US09343001B2	Display device using a display panel which prevents image distortion A display device has liquid crystal display panels aligned in a horizontal scan direction. The liquid crystal display panels constitute one virtual display area. A decoder decodes image data, to thereby generate pieces of pixel data having addressees corresponding to the virtual display area. A bridge circuit specifies a target (display destination) on which the pixel data is to be displayed on the basis of a parameter table indicating a correspondence between the virtual display area and each of display areas of the liquid crystal display panels. The pixel data are stored in line buffers corresponding to the specified display destinations and outputted to the liquid crystal display panels. Out of the pixel data, pixel data corresponding to a gap formed between two liquid crystal display panels are discarded.
US09342996B2	Trauma training system A system for simulating one or more hemorrhages in order to provide a more dynamic and realistic hemorrhage simulation in order to train medical personnel and other critical care givers, such as first responders, medics, and emergency medical technicians (EMTs) on treating hemorrhages. The system includes a reservoir, a flow controller, and at least one conduit connected to at least one simulated wound site wherein the system supplies fluid to the simulated wound site in order to simulate a hemorrhage. The system may further include a plurality of wound sites that have their respective fluid flows controlled by the fluid flow controller. In at least one embodiment, the reservoir and the flow controller are housed within a bag. In at least one embodiment, the system further includes an audio system for providing audio cues to the simulation participants to enhance the realism of the simulation.
US09342992B2	Presentation capture with automatically configurable output A device and method for simultaneously capturing a combination of content video, content audio, presenter video and presenter audio, as well as distributing a combination of content video, content audio, presenter video and presenter audio to a digital sink via an HDMI connection. Video sources are automatically routed to the digital sink depending on the source configuration.
US09342989B2	Radio-enabled collision avoidance system In the method of reducing the likelihood of collisions, the improvement comprising the step of embedding passive radio transponders in a tape, grease, or other materials; applying said passive radio transponders to an object of which collisions must be avoided, and mounting an active interrogating transponder on a moving machinery, which uses the information provided by the radio transponders to semi-autonomously avoid collisions.
US09342988B2	Method and device for determining a linear terrain profile along a lateral approach trajectory of an airport A device comprising a computation unit for computing, for each of a plurality of different distances relative to a threshold of a landing runway along a lateral approach trajectory, a geometric altitude, using a measured and stored barometric altitude, a computation unit for computing a terrain height, by subtracting, from the computed geometric altitude, a measured and stored height, and a computation unit for determining a terrain profile from the set of terrain heights computed for the set of different distances.
US09342987B2	Flight control for flight-restricted regions Systems, methods, and devices are provided for providing flight response to flight-restricted regions. The location of an unmanned aerial vehicle (UAV) may be compared with a location of a flight-restricted region. If needed a flight-response measure may be taken by the UAV to prevent the UAV from flying in a no-fly zone. Different flight-response measures may be taken based on the distance between the UAV and the flight-restricted region and the rules of a jurisdiction within which the UAV falls.
US09342985B2	Traffic condition data providing method using wireless communication device and navigation device performing the same A traffic condition data providing method using a wireless communication device and a navigation device performing the method are disclosed. The navigation device includes a travelling path displaying unit that searches a travelling path to a destination set by a user and displays the travelling path on map data, a traffic condition data receiving unit that receives traffic condition data from a content managing server through a wireless communication device in response to a request of providing the traffic condition data over the travelling path, and a traffic condition data providing unit that provides the user with the received traffic condition data.
US09342975B2	First responder wireless emergency alerting with automatic callback and location triggering Using wireless features, a public service agency is enabled to provide alert information to first responders. An automatic call back from the first responder triggers a voice call launching a location fix on the current location of the first responder. Preferably delivery confirmation that the responder has received the message is received. Once the location fix has been completed, then driving directions with map images are sent to the first responder based on their current location and desired destination for response.
US09342970B2	Mobile entity tracking and analysis Method for tracking and analysis of a mobile entity. In some embodiments a multi-dimensional geophysical area is divided into a first layer of zones each encompassing a contiguous portion of the geophysical area and having at least one rule. Geoposition values from a sensor associated with a mobile entity are accumulated in a memory. The accumulated geoposition values are used to identify an associated zone from the first layer of zones in which the mobile entity is located and the at least one rule assigned to the associated zone is applied. A second layer zone is subsequently generated in response to an input signal. The second layer zone overlays at least a portion of one zone in the first layer and expands over time. An alarm limit is output in response to a subsequently accumulated geoposition value from the sensor indicating the mobile entity is in the second layer zone.
US09342965B2	Methods and apparatus for providing assistance services for large crowds In one example embodiment, a mobile computing device provides assistance services for visitors at events which involve large crowds and long distances. The mobile computing device may be used to read a unique identifier for a visitor from an identification token for the visitor. The mobile computing device may then send visitor location data for the current location of the visitor to a remote command center. The mobile computing device may then receive leader location data from the remote command center. The leader location data may identify a last known location for a leader of a group of visitors that includes the visitor. After receiving the leader location data, the mobile computing device may compute directions from the current location of the visitor to the last known location of the leader, and the mobile computing device may display those directions on a map. Other embodiments are described and claimed.
US09342964B2	Media item characterization A deposit module is described. The deposit module comprises: a port for receiving a bunch of media items; a bunch characterization device operable to characterize the bunch prior to individual media items being removed from the bunch of media items; and a media separator for removing individual media items from the bunch and for transporting the removed individual media items to a media item validator subsequent to characterization of the bunch of media items.
US09342962B2	Gaming machine and methods of allowing a player to play gaming machines having expanding symbol positions A method of allowing a player to play a gaming machine is described herein. The method includes displaying, on a display device, a game including at least one reel being displayed with a plurality of normal symbol positions and a plurality of special symbol positions. The method includes determining a first amount of special symbol positions being displayed in a first instance of the game, spinning and stopping the at least one reel to display the first instance on the display device including the at least one reel being displayed with the first amount of special symbol positions, determining a second amount of special symbol positions being displayed in a second instance of the game, and spinning and stopping the at least one reel to display the second instance including the at least one reel being displayed with the second amount of special symbol positions.
US09342961B2	Gaming system and a method of gaming A method of gaming including: providing at least one set of player selectable symbols; receiving at least one player selection of a symbol from the at least one set of symbols; forming at least one reel strip including the at least one selected symbol; generating a game outcome from a set of reels including the at least one reel strip; and evaluating the game outcome to determine whether to make an award.
US09342960B2	Method and apparatus for managing item lottery service Provided is a technique which can increase user utilization of an item lottery service by providing users with an intuitive screen for the item lottery service, and, at the same time, a new source of fun. A method for managing an item lottery service in accordance with one exemplary embodiment of the present invention includes the steps of: displaying at least one item lottery apparatus for drawing lots for at least one item among the usable items in an online game on one part of an item lottery service screen of a user terminal; displaying an information screen with information regarding the usage of the item lottery service on one part of the item lottery service screen, other than the part where the item lottery apparatus is displayed; sensing usage input of at least one drawing of a lot from the user terminal for any one item lottery apparatus among at least one item lottery apparatus; and displaying, within the information screen, information for at least one item determined to be the winning item, according to the usage input, from among at least one winnable item from any one item lottery apparatus.
US09342959B2	Combination miniature basketball and roulette wheel table-top game A combination basketball and roulette table top self enclosed game is supervised by a chief contractor/operator with a programmable remote controller that starts a contract spinning wheel spinning around, and a time clock allowing an allotted time period to shoot a miniature basketball at a basket before a buzzer sounds. The basketball lands the on a spinning contract wheel similar to a roulette wheel with colored scoring points. Scoring is determined by number on the basketball tossed, times number it settles on the wheel. Certain colors gain point chips while other colors loose point chips. The scoring is also determined by wagers made on a wager board limes the number on the wager chip. Chips are placed on the wager board. The winning team is the team that has the most point chips at the end of a predetermined duration of the game.
US09342957B2	Gaming system, a method of gaming and an additional game controller A method of gaming comprising: determining which of a plurality of gaming devices, each operable for independent play of one or more games, are eligible for an additional game; initiating an additional game; and determining in response to initiation of the additional game, which eligible gaming devices will participate in the initiated additional game, the determination including a random determination in respect of at least one of the eligible gaming devices to determine whether the respective eligible gaming device will participate in the additional game.
US09342951B2	Wagering game establishment data import/export architecture A secure architecture can provide a wagering game establishment access to the utility and entertainment value of online social communities. An architecture that employs an internal entity that controls import and export of data (“import/export controller”) and an external entity that operates as a liaison (“data liaison”) between the import/export controller and one or more online social communities allows this access in a secure manner. The import/export controller and the data liaison handle data transmissions (e.g., data streams, data updates, etc.) between the secure entity and the one or more online social communities. The import/export controller applies rules that regulate import and export of data, and the data liaison allows the import/export controller to operate in obscurity. Funneling data transmissions through the import/export controller and the data liaison allows players to securely access an online social community from a wagering game machine while in a wagering game establishment.
US09342948B2	Head tracking in community wagering games Some embodiments include a method for conducting a multi-player wagering game. The method can include determining, by at least on processor, a head position of a player of the multi-player wagering game. The method can also include determining, based on the head position, a viewable portion of a virtual object used in the multi-player wagering game, and causing presentation of the viewable portion of the virtual object.
US09342941B2	Device for the acceptance of coins A device for the acceptance of coins which allows the acceptance of individual coins as well as the acceptance of various coins for further processing of the coins, whereby the device includes a laterally moveable holding fixture. The holding fixture has both a side with a coin insertion slot, and a receptacle area for the reception of a plurality of coins.
US09342929B2	Mixed reality experience sharing Embodiments that relate to presenting a textured shared world model of a physical environment are disclosed. One embodiment includes receiving geo-located crowd-sourced structural data items of the physical environment. The structural data items are stitched together to generate a 3D spatial shared world model. Geo-located crowd-sourced texture data items are also received and include time-stamped images or video. User input of a temporal filter parameter is used to temporally filter the texture data items. The temporally-filtered texture data items are applied to surfaces of the 3D spatial shared world model to generate a textured shared world model of the physical environment. The textured shared world model is then provided for display by a display device.
US09342928B2	Systems and methods for presenting building information Described herein are systems and methods for presenting building information. In overview, the technologies described herein provide relationships between Building Information Modeling (BIM) data (which includes building schematics defined in terms of standardized three dimensional models) and Building Management System (BMS) data (which includes data indicative of the operation of building components such as HVAC components and the like). Some embodiments use relationships between these forms of data thereby to assist technicians in identifying the physical location of particular pieces of equipment, for example in the context of performing inspections and/or maintenance. In some cases this includes the provision of 2D and/or 3D maps to portable devices, these maps including the location of equipment defined both in BIM and BMS data. In some cases, augmented reality technology is applied thereby to provide richer access to positional information.
US09342923B2	Systems and methods for creating a three-dimensional texture atlas Systems and methods for reducing the amount of texture cache memory needed to store a texture atlas by using uniquely grouped refined triangles to create each texture atlas.
US09342920B1	Volume rendering using scalable GPU-based cloud computing A GPU-based cloud computing platform is used to facilitate data computations on behalf of requesting users. In this embodiment, a user of a thin client has an associated dataset that requires computation. That dataset is adapted to be delivered to a computing platform, such as the GPU-based cloud, for computation, such as to facilitate a 3D volume rendering. The result of the computation is then returned to the user. Multiple such users may be operating clients and requesting computations from the cloud in a similar manner, possibly concurrently.
US09342919B2	Image rendering apparatus and method for preventing pipeline stall using a buffer memory unit and a processor An image rendering apparatus may include a buffer memory unit and a processor. The buffer memory unit may store input ray data for image rendering according to a ray tracing scheme while shape data corresponding to the input ray data is being fetched from a cache. The processor may output the received shape data together with the input ray data to an operation apparatus.
US09342918B2	System and method for using indirect texturing to efficiently simulate and image surface coatings and other effects Water surface and other effects are efficiently simulated to provide real time or near real time imaging on low-capacity computer graphics computation platforms. Water and other surfaces are modeled using multiple independent layers can be dynamically adjusted in response to real time events. The number of layers used in a given area can be adjusted to reduce computational loading as needed. Different algorithms can be employed on different layers to give different effects. The multiple layer modeling is preferably converted to polygons using an adaptive polygon mesh generator based on camera location and direction in the 3D world to provide automatic level of detailing and generating a minimal number of polygons. The visual effects of water droplets and other coatings on see-through surfaces can be modeled and provided using indirect texturing.
US09342917B2	Network based 3D design and collaboration In some embodiments, a system and/or method may include accessing three-dimensional (3D) imaging software on a remote server. The method may include accessing over a network a 3D imaging software package on a remote server using a first system. The method may include assessing, using the remote server, a capability of the first system to execute the 3D imaging software package. The method may include displaying an output of the 3D imaging software using the first system based upon the assessed capabilities of the first system. In some embodiments, the method may include executing a first portion of the 3D imaging software using the remote server based upon the assessed capabilities of the first system. In some embodiments, the method may include executing a second portion of the 3D imaging software using the first system based upon the assessed capabilities of the first system.
US09342914B2	Method and system for utilizing pre-existing image layers of a two-dimensional image to create a stereoscopic image Implementations of the present invention involve methods and systems for converting a 2-D multimedia image to a 3-D multimedia image by utilizing a plurality of layers of the 2-D image. The layers may comprise one or more portions of the 2-D image and may be digitized and stored in a computer-readable database. The layers may be reproduced as a corresponding left eye and right eye version of the layer, including a pixel offset corresponding to a desired 3-D effect for each layer of the image. The combined left eye layers and right eye layers may form the composite right eye and composite left eye images for a single 3-D multimedia image. Further, this process may be applied to each frame of a animated feature film to convert the film from 2-D to 3-D.
US09342912B1	Animation control retargeting The subject matter of this specification can be embodied in, among other things, a method that includes determining a transform of a portion of constituent components of a source shape. The transform includes one or more states for the portion of constituent components of the source shape. The method also includes accessing a mapping function that associates the one or more states with one or more controls for a target shape, where the one or more controls configured for access by a user for manipulating constituent components of the target shape. The method includes outputting a transform for the target shape based on the one or more controls associated with the transformed constituent components of the source shape.
US09342910B2	Systems, processes, and computer program products for creating geo-location-based visual designs and arrangements originating from geo-location-based imagery Systems, processes, and computer program products for creating visual designs and arrangements that originate from an image or images are provided. In particular, the present subject matter relates to systems, processes, and computer program products for taking captured images of an intended operating environment and creating visual designs that create visual confusion that can be utilized to disguise a recognizable form of a person or an object by breaking up its outline using portions, magnifications and distortions of a single captured image, portions, magnifications and distortions of multiple captured images, and/or disruptive patterns that can projected on an image screen or can be printed on a material.
US09342908B2	Information retrieval and presentation methods and systems The present invention provides a networked computer system for retrieving and displaying information, comprising a front-end sub-system and a back-end sub-system. The back-end comprises one or more selectable pipelines for processing the user query, each comprising one or more component software modules selected from a library of modular component software modules having predefined functions or created by a user to cooperate in extracting and processing extracted data, wherein at least one of the one or more pipelines may be customized by modifying either or both of a selection or sequence of the component software modules.
US09342901B2	Material data processing pipeline A method for generating a shader that is used by a rendering engine to render a visual representation of a computer model. A shader generation engine receives a set of surface data that describes a surface in view of various lighting conditions. The shader generation engine compresses the set of surface data to generate a compressed representation of the set of surface data based on a selected compression algorithm. The shader generation engine generates a shader based on the compressed representation that is configured to be implemented with a rendering engine, and generates a set of shader data based on the compressed representation that includes a set of material characteristics for coloring pixels of the visual representation. Advantageously, the shader generation process is simplified because different compression algorithm-rendering engine shader combinations can be generated without manually programming the shaders.
US09342898B2	Image inspection system, image inspection method, and recording medium storing image inspection program An image inspection system, an image inspection method, and an image inspection program acquires a read image obtained by reading an output image, generates an inspection image for inspecting the read image based on data of a to-be-output image, acquires an inspection result including a determination whether the read image is defective, based on a difference between the inspection image and the read image, acquires coloring-material usage data indicating extent of coloring-material usage in the output image, the coloring-material usage data being read when the read image is generated, generates coloring-material usage defect rate data indicating a defect rate in association with coloring-material usage, based on the inspection result and the coloring-material usage data, and obtains coloring-material usage of the to-be-output image, based on data of pixels forming the to-be-output image.
US09342897B2	In-vehicle target detecting device In an in-vehicle target detecting device, a captured image which is an image capturing an area ahead of the own vehicle is acquired at a predetermined measurement cycle. Radio waves are transmitted and received. Positional information indicating at least an orientation and a distance of at least one target candidate in relation to the own vehicle is acquired. The target candidate reflects radio waves. Image recognition is performed to detect a detection object by searching a predetermined image search area in the captured image. At least an image detection position of the detection object in the captured image is stored. The image search area is set, based on an image-plane measurement position corresponding to a measurement position in the captured image. The measurement position is a position in three-dimensional space of the target candidate indicated by the positional information acquired at a timing at which the captured image is acquired.
US09342896B2	Image processing apparatus, image apparatus, image processing method, and program for analyzing an input image of a camera Disclosed herein is an image processing apparatus including: a detection section configured to detect a motion area in a screen based on images taken, and output detection information; an accumulation section configured to accumulate the detection information for the past as outputted from the detection section; an area division section configured to divide the screen into an area where motions regularly occur and a motion-free area, based on the detection information for the past as accumulated in the accumulation section, and output area information; and an alarm management section configured to perform particular control based on the area information from the area division section and the detection information from the detection section.
US09342892B2	Image binarization Systems and methods convert to binary an input image having pixels defining text and background. Thresholds are determined by which pixels in the input image and a corresponding blurred image will be defined as either binary black or binary white. Thresholds derive from grouped together neighboring pixels having pixels separated out that correspond to the background. For pixels of the input image defined as binary black and having corresponding pixels in the blurred image defined as binary black relative to their thresholds, those are set to black in the binary image, else they are set white. Techniques for devising thresholds, blurring images, grouping together pixels, statistical analysis, etc., typify the embodiments.
US09342891B2	Stencil then cover path rendering with shared edges One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
US09342890B2	Registering of a scene disintegrating into clusters with visualized clusters A method for optically scanning and measuring a scene by a three-dimensional (3D) measurement device in which multiple scans are generated to then be registered in a joint coordinate system of the scene. At first at least one cluster is generated from at least one scan, further scans are registered for test purposes in the coordinate system of the cluster, if specified quality criteria are fulfilled and the generated clusters are then joined, for which purpose clusters are selected, registered for test purposes and registering is confirmed if appropriate, wherein the clusters to be joined are visualized with an optional possibility for the user to intervene, for supporting the selection of clusters.
US09342883B2	Omnibus resolution assessment target for sensors A method and system are provided to assess a resolution of an optical sensor. The method includes placing a target at a distance from a focal plane of the optical sensor. The target is oriented in a first orientation and includes a grid and a plurality of test objects having different sizes and orientations. An image of the target is acquired from the optical sensor. The target grid in the acquired image is identified. Each test object of the plurality of test objects is identified using the identified grid and an orientation of the identified test object is determined. The determined orientations of the identified test objects of the plurality of test objects are compared to a ground truth and presented.
US09342882B2	Methods and systems for determining the concentration of a contrast agent A method for determining a concentration of a contrast agent in imaging data includes calculating a pre-contrast attenuation map of a region of interest of a patient. Following an administering of a contrast agent to the patient, a post-contrast attenuation map of the region of interest of the patient is calculated. An increase in attenuation value is determined based on the pre-contrast attenuation map and the post-contrast attenuation map and a contrast agent concentration map is calculated for the region of interest based on the increase in attenuation value.
US09342881B1	System and method for automatic detection of in vivo polyps in video sequences A system and method for identifying an in-vivo image frame with one or more polyps. Center points of candidate imaged structures may be determined, each center point defining a respective circle. Polyp edge scores may be computed for a plurality of points around each center point, each polyp edge score measuring the coincidence of a respective candidate imaged structure and its respective circle. For each center point, a plurality of edge points of the respective candidate imaged structure may be detected based on the polyp edge score and a candidate imaged structure may be identified based on the detected edge points. For each candidate imaged structure, a candidate polyp may be identified for which extrapolating the detected edge points forms an edge in a shape approximating an ellipse. Image frames with candidate polyps contributing to an above threshold overall image score are determined and marked to include a polyp.
US09342880B2	Defect analyzing apparatus, substrate processing system, defect analyzing method and computer-readable storage medium A potential trouble can be in advance suppressed by analyzing a defect of a wafer. A defect analyzing apparatus of analyzing a defect of a substrate includes an imaging unit configured to image target substrates; a defect feature value extracting unit configured to extract a defect feature value in a surface of the substrate based on the substrate image; a defect feature value accumulating unit configured to calculate an accumulated defect feature value with respect to the substrates to create an accumulation data AH; a defect determination unit configured to determine whether the accumulated defect feature value exceeds a preset critical value; and an output display unit configured to output a determination result from the defect determination unit.
US09342877B2	Scaling a three dimensional model using a reflection of a mobile device A computer-implemented method for scaling a three dimensional model of an object is described. In one embodiment, first and second calibration images may be shown on a display of a mobile device. The display of the mobile device may be positioned relative to a mirrored surface. A reflection of an object positioned relative to the mobile device may be captured via a camera on the mobile device. A reflection of the first and second calibration images may be captured. The captured reflection of the object and the captured reflection of the first and second calibration images may be shown on the display. A reflection of the displayed captured reflection of the first and second calibration images may be captured. When the captured reflection of the displayed captured reflection of the first calibration image is positioned relative to the captured reflection of the second calibration image may be detected.
US09342876B2	Methods, apparatuses, and computer-readable media for projectional morphological analysis of N-dimensional signals Embodiments discussed herein in the form of methods, systems, and computer-readable media deal with the application of advanced “projectional” morphological algorithms for solving a broad range of problems. In a method of performing projectional morphological analysis, an N-dimensional input signal is supplied. At least one N-dimensional form indicative of at least one feature in the N-dimensional input signal is identified. The N-dimensional input signal is filtered relative to the at least one N-dimensional form and an N-dimensional output signal is generated indicating results of the filtering at least as differences in the N-dimensional input signal relative to the at least one N-dimensional form.
US09342873B1	Tile-based optical flow A computing device may determine a per-tile motion estimate between a first m×n pixel tile from a first captured image of a scene and a second m×n pixel tile from a second captured image of the scene. A per-tile confidence of the per-tile motion estimate may be obtained. The per-tile motion estimate and the per-tile confidence may be upsampled to obtain respective per-pixel motion estimates and associated per-pixel confidences for pixels of the first m×n pixel tile. The respective per-pixel motion estimates and associated per-pixel confidences may be iteratively filtered. The iterative filtering may involve multiplying the respective per-pixel motion estimates and associated per-pixel confidences by an affinity matrix. The iterative filtering may also smooth the respective per-pixel motion estimates and associated per-pixel confidences.
US09342872B2	Color correction parameter computation method, color correction parameter computation device, and image output system A color correction parameter computation method includes: obtaining first color-signal values respectively corresponding to colors of color patches and obtained by photographing a color chart having the patches thereon, and reference color-signal values respectively defining the colors of the patches; computing, for each color of the patches, a color difference component between the first and the reference color-signal values; selecting at least one color of the patches by comparing the magnitude of the difference components; computing a color correction parameter using the first and the reference color-signal values corresponding to the selected color; computing an accuracy measure using the difference component between a second corrected color-signal value obtained by correcting a first color-signal value corresponding to a color other than the selected color and the reference color-signal value defining the color other than the selected color; and determining correction accuracy by comparing the accuracy measure to an accuracy criterion.
US09342871B2	Scene motion correction in fused image systems Techniques to capture and fuse short- and long-exposure images of a scene from a stabilized image capture device are disclosed. More particularly, the disclosed techniques use not only individual pixel differences between co-captured short- and long-exposure images, but also the spatial structure of occluded regions in the long-exposure images (e.g., areas of the long-exposure image(s) exhibiting blur due to scene object motion). A novel device used to represent this feature of the long-exposure image is a “spatial difference map.” Spatial difference maps may be used to identify pixels in the short- and long-exposure images for fusion and, in one embodiment, may be used to identify pixels from the short-exposure image(s) to filter post-fusion so as to reduce visual discontinuities in the output image.
US09342870B2	Tree-based linear regression for denoising Image denoising techniques are described. In one or more implementations, a denoising result is computed by a computing device for a patch of an image. One or more partitions are located by the computing device that correspond to the denoising result and a denoising operator is obtained by the computing device that corresponds to the located one or more partitions. The obtained denoising operator is applied by the computing device to the image.
US09342865B2	Sigma-delta ADC with integrated raw image scaling filter A system and method of processing raw image pixel information includes an integrated decimation filter and raw image scaling filter for a set of M columns of raw image pixel information. The decimation filter operates in the time domain; for example, to calculate a weighted average of time samples. The raw image scaling filter operates in the spatial domain; for example, to calculate a weighted average of spatial samples. The raw image pixel information is modulated by a sigma-delta analog-to-digital modulator. The system and method scale the raw image pixel information by a factor of 1/N. M and N are positive integers.
US09342864B2	Alternative semantics for zoom operations in a zoomable scene A scene comprising a set of visual elements may allow a user to perform “zoom” operations in order to navigate the depth of the scene. The “zoom” semantic is often applied to simulate optical visual depth, wherein the visual elements are presented with different visual dimensions and visual resolution to simulate physical proximity or distance. However, the “zoom” semantic may be alternatively applied to other aspects of the visual elements of a scene, such as a user selection of a zoomed-in visual element, a “drill-down” operation on a data set, or navigation through a portal in a first data set to view a second data set. These alternative “zoom” semantics may be achieved by presenting the effects of a “zoom” operation within the scene on the visual presentation of the visual element in a manner other than an adjustment of the visual dimensions and resolution of the visual element.
US09342863B2	Virtualizing applications for per-monitor displaying A virtualized coordinate system is determined that describes an alternate monitor space. The virtualized coordinate system is provided to an application providing content to be displayed and the application provides virtualized rendering information including coordinates in the virtualized coordinate system. The virtualized rendering information is scaled for display on the monitor.
US09342862B2	Zooming a displayed image A system for displaying an image in a viewport includes a zoom subsystem (6) arranged for gradually zooming the image (401) towards a scale factor at which the image just fits within the viewport (302). The zoom (6) subsystem is arranged for keeping a fixed point (403) fixed within the viewport (302). The fixed point (403) depends on a pan/zoom parameter (7) of the image (401) at the time zooming starts. The fixed point (403) is a point of the image (401) which is being displayed in the viewport (302) at the time zooming starts. The image (401) is capable of being zoomed to a zoom level at which the image just fits within the viewport (302), while the fixed point (403) is kept fixed with respect to the viewport (302).
US09342861B2	Alternate viewpoint rendering Described are computer-based methods and apparatuses, including computer program products, for alternate viewpoint rendering. A first image and a set of pixel-shift values for the pixels in the first image are received. A portion of a second image is generated, the second image comprising a different viewpoint than a viewpoint of the first image. A first pixel from the set of pixels is selected based on the different viewpoint. A first destination pixel is identified for the first pixel in the second image based on a pixel-shift value from the set of pixel-shift values associated with the first pixel. A value of the first destination pixel is determined based on at least one of (a) a previously considered pixel from the set of pixels of the first image that is horizontally adjacent to the first pixel or (b) the pixel-shift value associated with the first pixel.
US09342859B2	GPU based parallel image processing at thin client Disclosed herein is a computing device that includes: a processor; a graphic processing unit having N graphic processing cores, N being an integer greater than 1; a random access memory (RAM); a video port; a non-volatile memory, and a display processing unit. The non-volatile memory stores a virtual desktop client (VDC). The VDC can communicate with a first virtual machine (VM) of a hypervisor running on a remote computing device and receive an encoded image frame from the first VM; instruct the plurality of graphic processing cores to decode the encoded image frame in parallel; and generate a decoded image frame of the encoded image frame. The display processing unit can generate display signals representing the decoded image frame and transmit the display signals to the video port.
US09342857B2	Techniques for locally modifying draw calls One embodiment sets forth a method for modifying draw calls using a draw-call shader program included in a processing subsystem configured to process draw calls. The draw call shader receives a draw call from a software application, evaluates graphics state information included in the draw call, generates modified graphics state information, and generates a modified draw call that includes the modified graphics state information. Subsequently, the draw-call shader causes the modified draw call to be executed within a graphics processing pipeline. By performing the computations associated with generating the modified draw call on-the-fly within the processing subsystem, the draw-call shader decreases the amount of system memory required to render graphics while increasing the overall processing efficiency of the graphics processing pipeline.
US09342850B2	Forward-looking transactive pricing schemes for use in a market-based resource allocation system Disclosed herein are representative embodiments of methods, apparatus, and systems for distributing a resource (such as electricity) using a resource allocation system. One of the disclosed embodiments is a method for generating a bid value for purchasing electricity in a market-based resource allocation system. In this embodiment, a desired performance value indicative of a user's desired performance level for an electrical device is received. Price information from an electricity futures market is received. A bid value for purchasing electricity from a local resource allocation market sufficient to operate the electrical device at the desired performance level is computed. In this embodiment, the computing is performed based at least in part on the desired performance value and based at least in part on the price information from the electricity futures market.
US09342842B2	Context-switching taxonomy for mobile advertisement Systems, methods, and non-transitory computer-readable storage media for mobile advertisement based on a context-switching context taxonomy. The system collects usage data associated with a device. Based on the usage data, the system determines a switching context channel and a switching context trend, wherein the switching context channel defines a user's movement through channel classifications, and wherein the switching context trend defines the user's activity over a period of time. Next, the system generates a classification model based on the switching context channel and the switching context trend. The system then books a campaign of invitational content based on the classification model.
US09342835B2	Systems and methods to deliver targeted advertisements to audience In one aspect, a system includes a transaction handler to process transactions, a data warehouse to store transaction data recording the transactions processed at the transaction handler, a profile generator to generate a profile of a user based on the transaction data, an advertisement selector to identify an advertisement based on the profile of the user in response to the transaction handler processing a transaction of the user, and a portal coupled to the transaction handler to provide the advertisement for presentation to the user in connection with information about the transaction of the user. In one example, the profile includes a plurality of values representing aggregated spending of the user in various areas to summarize the transactions of the user.
US09342834B2	System and method for setting goals and modifying segment criteria counts Methods and systems may operate to include displaying to a user a graphical user interface (GUI) to enable the user to combine multiple search criteria having variable parameters, used in searching of a database, to produce a predefined count of search results. User selections of the multiple search criteria, values for the variable parameters, and Boolean operations to combine the search criteria may be received from the user. As the received user selections change, a count of search results retrieved from the database, based on the user selections, may be dynamically displayed. Additional methods and systems are disclosed.
US09342825B2	Software license and installation process management within an organization A software license and a software installation process are managed. A status of the license can be one of at least a third party reserved status, a requester reserved status, a requester allocated status, and an available status. A first module can be operative to change the status of the license from the third party reserved status to the requester allocated status in response to receiving a mode selection. The mode selection can correspond to one of one or more modes. The modes can comprise a reserve license mode, a remove reserve mode, a request license allocation mode, a return excess license to inventory mode, an ordering mode, and an add license to inventory mode. The first module can be operative in at least one of the modes.
US09342821B2	Virtual discussion threads for activities in a trusted network Managing discussion threads within an electronic communication system includes detecting that an electronic message sent from a sender to a first recipient is forwarded from the sender to a second recipient and, responsive to the detecting, identifying at least one electronic message related to the forwarded message exchanged between the sender and the second recipient as a virtual discussion thread. A client is notified of that the virtual discussion thread exists and is correlated with the electronic message from the sender. The virtual discussion thread is provided to the client of the first recipient.
US09342819B1	Targeted notification of users of a communications system based on a location, device type, and/or software type of the users A method for transmitting data to one or more users of a communications system by establishing a connection with one or more users; designating targeting rules applicable to online users; acquiring context information of online users; applying the targeting rules to the context information to identify targeted online users; and sending data to the targeted online users.
US09342817B2	Auto-creating groups for sharing photos Methods and systems for aggregating and sharing digital content associated with social events via a network are provided. In one example embodiment, a system for aggregating and sharing digital content associated with social events via a network facilitates the aggregation and sharing of digital content, such as photos and videos. The aggregation may be performed with respect to the digital content received from different sources associated with the same social event. The digital content may also be subjected to an image recognition process to identify one or more individuals appearing in the photos or videos. The shared content may also be filtered to display only those photos or videos with specific individuals. In addition, users may be allowed to set privacy rules with respect to the photos and videos within which they appear.
US09342812B2	Taxonomy based database partitioning In one aspect of the invention, a memory is described for facilitating splitting data by taxonomy. The memory is accessed by an application program, and includes one or more top-level categories, where each top-level category comprises a subset of the items; and also includes a category group corresponding to at least one of the top-level categories and the subset of the items belonging to the top-level categories.
US09342810B2	Dynamic scan context determination for asset reconciliation Asset reconciliation is facilitated by dynamically determining and applying a scan context to asset-describing tag data. Tag data representative of assets are received from RFID tags. A working scan context defining a scope of coverage of assets to be included in an asset reconciliation is dynamically determined based on the received tag data. Additional tag data representative of additional assets are received, and the dynamically determined working scan context is applied to the additional tag data to automatically identifying which assets of the additional assets are to be included in the asset reconciliation. Assets included in the scope of coverage of the working scan context are included in the asset reconciliation, and assets not included in the scope of coverage of the working scan context are not included in the asset reconciliation.
US09342809B2	Method and apparatus to populate asset variant relationships in repositories Methods and arrangements for performing a tree-based asset search. An asset model is assimilated. The asset model is transformed into an asset tree search model. An asset search query is accepted and the asset search query is parsed. An asset search is conducted via applying the parsed asset search query to the asset tree model.
US09342803B2	Diagnose system for rearranging order of testing items in diagnose program in accordance with a log file Disclosed is a diagnose system for rearranging order of testing items in a diagnose program and a method thereof. The method is applicable to a diagnose system, including an electronic device to be tested, a storage component and a plurality of detecting apparatuses. The electronic device to be tested includes an interface and stores a diagnose program including a plurality of testing items. The storage component is electrically coupled to the electronic device to be tested through the interface for reading a log file that includes a plurality of invocation commands, so that the electronic device to be tested can sequentially execute each of the invocation commands to invoke the corresponding testing items. Each of the detecting apparatuses corresponds to at least one testing item so as to drive each of the detecting apparatuses and execute a corresponding testing process to the electronic device to be tested.
US09342797B2	Systems and methods for the detection of implicit gestures Some embodiments provide systems and methods for enabling a learning implicit gesture control system for use by an occupant of a vehicle. The method includes identifying features received from a plurality of sensors and comparing the features to antecedent knowledge stored in memory. A system output action that corresponds to the features can then be provided in the form of a first vehicle output. The method further includes detecting a second vehicle output from the plurality of sensors and updating the antecedent knowledge to associate the system output action with the second vehicle output.
US09342796B1	Learning-based data decontextualization Techniques are described for employing a crowdsourcing framework to analyze data related to the performance or operations of computing systems, or to analyze other types of data. A question is analyzed to determine data that is relevant to the question. The relevant data may be decontextualized to remove or alter contextual information included in the data, such as sensitive, personal, or business-related data. The question and the decontextualized data may then be presented to workers in a crowdsourcing framework, and the workers may determine an answer to the question based on an analysis or an examination of the decontextualized data. The answers may be combined, correlated, or otherwise processed to determine a processed answer to the question. Machine learning techniques are employed to adjust and refine the decontextualization.
US09342792B2	Quantum computer and quantum computing using ising model For each pair of a plurality of slave lasers B for which injection synchronization is performed by a master laser M, by controlling the intensity of light exchanged between two slave lasers B and an optical path length between the two slave lasers B using a slave-to-laser intensity control unit IA and an inter-slave laser optical path length control unit IP, the magnitude and the sign of pseudo ising interaction Jij between the two slave lasers B are implemented. After the plurality of slave lasers B arrive at a steady state, by measuring relative values of the oscillation phases of the plurality of slave lasers B with respect to the oscillation phase of the master laser M by using an oscillation phase measuring unit PM, pseudo ising spins σi of the plurality of slave lasers B are measured.
US09342787B2	Sensor based truth maintenance A truth maintenance method and system. The method includes receiving by a computer processor from RFID tags embedded in sensors, event data associated with events detected by said sensors. The computer processor associates portions of the event data with associated RFID tags and derives assumption data associated with each portion of the portions. The computer processor retrieves previous assumption data derived from and associated with previous portions of previous event data retrieved from the RFID tags and executes non monotonic logic with respect to the assumption data and the previous assumption data. In response, the computer processor generates and stores updated assumption data associated with the assumption data and the previous assumption data.
US09342785B2	Tracking player role using non-rigid formation priors Approaches are described for assigning roles to agents in a group of agents engaging in an activity. An assignment analysis system receives a first set of detections, where each detection in the first set of detections comprises a physical location. The assignment analysis system defines an exemplar formation comprising an arrangement of each role in a set of roles. The assignment analysis system calculates a first cost function between at least one detection in the first set of detections and at least one role in the set of roles. The assignment analysis system generates a first set of permutations based on the first cost function. The assignment analysis system assigns a first role in the set of roles to a first detection in the first set of detections based on the first set of permutations.
US09342782B2	Stochastic delay plasticity A method of operating a spiking neural network having neurons coupled together with a synapse includes monitoring a timing of a presynaptic spike and monitoring a timing of a postsynaptic spike. The method also includes determining a time difference between the postsynaptic spike and the presynaptic spike. The method further includes calculating a stochastic update of a delay for the synapse based on the time difference between the postsynaptic spike and the presynaptic spike.
US09342781B2	Signal processing systems We describe a signal processor, the signal processor comprising: a probability vector generation system, wherein said probability vector generation system has an input to receive a category vector for a category of output example and an output to provide a probability vector for said category of output example, wherein said output example comprises a set of data points, and wherein said probability vector defines a probability of each of said set of data points for said category of output example; a memory storing a plurality of said category vectors, one for each of a plurality of said categories of output example; and a stochastic selector to select a said stored category of output example for presentation of the corresponding category vector to said probability vector generation system; wherein said signal processor is configured to output data for an output example corresponding to said selected stored category.
US09342777B2	Programmatic control of RFID tags Techniques that enable a device to advertise its mode of operation using an RFID tag attached to the device. Techniques are provided for programmatically controlling an RFID tag. An RFID tag attached to a device is programmatically enabled or disabled depending upon the mode(s) of operation of the device. The RFID tag is able to transmit a signal when enabled and not able to transmit a signal when disabled. Using such a controllable RFID tag, a device can efficiently indicate or advertise its mode of operation to an RFID reader or sensor.
US09342773B2	Label for product authentication, method for generating authentication code of label, method and system for authenticating label, portable terminal for authenticating label, and computer-readable recording medium for authenticating label A product authentication label includes a carrier layer made of a transparent or translucent material, a plurality of first reflection pattern forming bodies disposed in the carrier layer and configured to reflect a substantially identical reflection pattern regardless of the direction of irradiated light, and a plurality of second reflection pattern forming bodies randomly disposed in the carrier layer and configured to reflect a reflection pattern which varies depending on the direction of irradiated light.
US09342771B2	Printer with display unit for displaying paper registration screen and storing unit for storing attribute of paper associated with paper feeding unit A printer includes a display unit, a printing unit and a printing control unit. The display unit is configured and arranged to display a paper registration screen for registering or confirming attributes of paper held in a paper feeding unit when display conditions have been satisfied. The printing unit is configured and arranged to execute printing. The printing control unit is configured to, when prescribed printing start conditions are satisfied during a period in which the paper registration screen is being displayed, control the printing unit to start printing job using the attributes registered before display of the paper registration screen as the attributes of the paper held in the paper feeding unit used with the printing job.
US09342769B2	Image processing apparatus and image processing method for correcting a line image An image processing apparatus increases, in the case of a low-density line, the density of a pixel included in the line to increase the density of the line, and increases, in the case of a high-density line, the density of a pixel adjacent to the pixel included in the line to increase the width of the line.
US09342766B2	Image generation program and printer for printing composite image on a medium arranged so as to face a lens layer having a plurality of lenses An image generation method for generating an image, which is printed on a medium arranged so as to face a lens layer having a plurality of lenses and includes a three-dimensional image and a two-dimensional image, includes performing lossy compression for the two-dimensional image in a direction in which light focusing of the lenses occurs and magnifying the two-dimensional image in the direction in which the light focusing of the lenses occurs after the lossy compression for the two-dimensional image has been performed.
US09342765B2	Image forming apparatus and image forming method An image forming apparatus includes: a printing unit configured to print at a plurality of linear velocities; an image preparing time determination unit configured to determine a print image preparing time necessary for developing print data to a print image to be printed by the printing unit; a linear velocity determination unit configured to determine the linear velocity according to the print image preparing time determined by the image preparing time determination unit; and an engine control unit configured to operate the printing unit at the linear velocity determined by the linear velocity determination unit.
US09342763B2	Image processing apparatus and method of controlling same An image processing apparatus includes an operation unit having a hardware key for accepting a user operation and a light emitting device corresponding to the hardware key. A display unit displays an operation screen based on content obtained from a web server. A control unit determines whether the content includes a description for instructing operation to transmit data input via the operation screen to the web server, and causes the light emitting device to emit light in response to having determined that the content includes the description. A transmission unit transmits the data input via the operation screen to the web server when the hardware key is operated by a user while the operation screen is being displayed based on the content including the description.
US09342758B2	Image classification based on visual words The present disclosure introduces a method and an apparatus for classifying images. Classification image features of an image for classification are extracted. Based on a similarity relationship between each classification image feature and one or more visual words in a pre-generated visual dictionary, each classification image feature is quantified by multiple visual words in the visual dictionary and a similarity coefficient between each classification image feature and each of the visual words is determined. Based on the similarity coefficient of each visual word that corresponds to different classification image features, a weight of each visual word is determined to establish a classification visual word histogram of the image for classification. The classification visual word histogram is input into an image classifier that is trained by sample visual word histograms arising from multiple sample images. An output result is used to determine a classification of the image for classification.
US09342756B2	Methods and apparatus to detect differences between images Methods and apparatus to detect differences between images are disclosed. Example methods disclosed herein include determining whether a difference between a block of pixels of a first image represented by a first signature and a block of pixels of a reference image represented by a second signature matching the first signature is resolvable using a transformation operation. Example methods disclosed herein also include, in response to determining the difference is unresolvable using the transformation operation, including the block of pixels of the first image in a difference region of the first image. Example methods disclosed herein further include generating a third signature different from the difference region of the first image to represent the difference region of the first image, and storing the third signature with version information associated with first image.
US09342755B2	Image overlay for duplicate image detection Embodiment for detecting duplicate images include systems for determining that two or more of the images have similar key attributes such as attributes related to certain data in the images or image quality. Further, the embodiments include superimposing at least a portion of a first image of the two or more images over at least a portion of the second image of the two or more images, comparing the first image and second image; and determining whether the first image and the second image are identical.
US09342753B2	Image processing apparatus, image processing method, and computer program product According to an embodiment, an image processing apparatus includes an acquisition unit, a setting unit, and a calculator. The acquisition unit is configured to acquire an image. The setting unit is configured to set a plurality of sampling points in a sampling area of the image, each sampling point being associated with a calculation area. The calculator is configured to calculate feature values of the image in the calculation area. The setting unit is configured to set the sampling points to provide at least one of an arrangement in which distances between the adjacent sampling points change with distances from a center of the sampling area, and an arrangement in which the sampling points exist on circumferences of a plurality of circles different in diameter.
US09342752B1	Adjusting an image for video conference display A video conferencing system contains one or more display adjusting components, whereby an object to be displayed can be adjusted to appropriately fit various sized display screens. A display adjusting component is contained within the sending client, which adjusts the image of the object to be appropriately displayed to one or more receiving clients. The receiving clients also contain a display adjusting component, which can further adjust the image of the object to be displayed, as necessary. The multimedia conferencing server of the video conferencing system also contains a display adjusting component, which negotiates parameters of the sending and receiving clients. Any of the display adjusting components can function alone, or in any combination together. A method, and computer readable media which contain computer readable instructions to perform a method, of adjusting an image for video conference display are also described.
US09342750B2	Method and apparatus for detecting line data based on Hough transform A method and an apparatus for detecting straight line information by Hough transform are provided, in which voting computation according to Hough transform is performed only with respect to certain pixels, while the votes of the rest pixels are calculated using the votes of the neighborhood pixels, thereby reducing overhead of voting computation and also increasing hourly throughput.
US09342747B2	Vehicle driver assistance apparatus for assisting a vehicle driver in maneuvering the vehicle relative to an object A vehicle driver assistance apparatus is provided for a vehicle. The vehicle driver assistance apparatus comprises an image capture device arranged to capture image data which is representative of an object in vicinity of the vehicle. The vehicle driver assistance apparatus further comprises an electronic controller arranged to (i) process the captured image data to identify an edge line associated with the object, and (ii) process the captured image data further based upon the identified edge line to identify a distance between the vehicle and the edge line of the object.
US09342746B1	Maneuverless passive range estimation using monocular image sequences A method to estimate range to a moving rigid body from a moving platform using a monocular camera. The method does not require the camera platform to maneuver in order to estimate range. The method relies on identification and tracking of certain principal features of the object. The method extracts a silhouette of an object from an obtained image and identifies two principal linear components of the silhouette. A normalized distance between the point of intersection of the two linear components and a centroid of the silhouette is computed, compared to a data set and used to determine a direction of movement of the object.
US09342744B2	Surveillance image retrieval apparatus and surveillance system Disclosed is a surveillance image retrieval apparatus capable of generating an image representing a search result that a surveillant can visually confirm, even if a face image used is not suitable for the visual identification of a person. The surveillance image retrieval apparatus includes a surveillance image acquirer, which acquires surveillance images; a feature amount generator, which extracts a face image from the surveillance images and generates the feature amount of the extracted face image; an image feature amount memory for storing a face image, a surveillance image, and other metadata associated with an acquired feature amount; a face image designator, which selects an appropriate face image in accordance with a user's input, and designates the selected face image as a query image for a person search; a similar image searcher for searching the series of surveillance images stored in the image feature amount memory for a face image similar to the designated face image; a presentation image selector, which examines surveillance images that are close to the search result in imaging time, and selects presentation surveillance images that include face images of the same person; and a screen data generator for outputting the presentation surveillance images selected.
US09342743B2	Method for supporting an operator in measuring a part of an object Method for supporting an operator in measuring a part of an object, comprising the steps of equipping the operator with an electronic device and with a dimension measuring apparatus. The device comprises a see-though head mounted display, a camera, and a digital processor. An image of the object is captured with the camera so that the processor recognizes or identifies the part of the object in the image. The method further comprises the steps of obtaining a model of said part and displaying on the display an indication of the dimension that is intended to be measured. A value of the dimension measured by the dimension measuring apparatus is acquired in the processor that will process it according to the model.
US09342737B2	Dynamic sampling in sports equipment Analysis of sporting equipment characteristics may be analyzed using dynamic sampling rates. For example, analyzing a golf swing may include the use of one or more sensors providing data at various sampling rates. According to some aspects, the sampling rate may be dynamically modified upon determination of one or more golf equipment characteristics, environmental conditions, player characteristics and the like. In one example, a sampling rate processor may dynamically select a sampling rate at which data is sampled from one or more sensors. In some examples, by dynamically selecting the sampling rate, an analysis may be tailored to various types, and portions of a golf swing, in addition to producing power consumption by the analysis instruments in the golf club system. According to other aspects, triggering conditions for modifying a sampling rate may be determined from a population of one or more previous golf swings performed by a user.
US09342733B2	Fingerprint sensing and calibration apparatus Methods and Apparatuses are provided for a thin high contrast optical acquisition system for fingerprint recognition. In one embodiment, a method of capturing images of a fingerprint may include emitting light from a set of light sources to generate a scattered light from the fingerprint, determining a set of sensor arrays located between an inner boundary and an outer boundary from the set of light sources based on thickness and refractive index of one or more panels between the set of light sources and the fingerprint, activating the set of sensor arrays to capture the scattered light from the fingerprint, and processing the scattered light captured by the set of sensor arrays in parallel to generate a topography of the fingerprint.
US09342730B2	Finger identification apparatus An identification apparatus keeps the conditions for imaging uniform among successive identifications, and requires a user to perform only a series of simple maneuvers. The apparatus comprises a guide member, a light source, and an imaging unit. The guide member includes a pattern or structure for a user to position his/her finger thereon or to approach his/her specific finger region thereto. A contact member is located in the guide member where a fingertip is positioned. An optical opening is formed at a position coincident with where a finger to be imaged should be placed. The light source radiates near-infrared light through the portion of the finger to be imaged. The imaging means acquires an image of the finger, and the apparatus compares the image to previously registered images. The apparatus may also include dual light sources power saving functionality, and means for limiting the interference of external light sources.
US09342729B2	Fake fingerprint detection system Methods and Apparatus are provided for fake fingerprint detection. In one embodiment, an apparatus for determining validity of a fingerprint includes a prism having an imaging surface configured to be touched by a fingerprint, one or more light sources configured to produce an image based on a refractive index of a material presented in association with the fingerprint, one or more imaging sensors configured to capture the image, and a controller configured to determine validity of the fingerprint based on whether the image has been masked.
US09342727B2	Field shaping channels in a substrate above a biometric sensing device An electronic device may include a biometric sensing device that has a sensing area, and a substrate positioned above the sensing area and/or the biometric sensing device. The substrate can include vias that are formed through at least a portion of the substrate. The vias can be positioned at least above the sensing area of the biometric sensing device. The vias may be filled with a conductive material or a dielectric material. Alternatively, some vias can be filled with a conductive material while other vias are filled with a non-conductive or dielectric material.
US09342723B2	Encoded information reading terminal with multiple imaging assemblies An encoded information reading (EIR) terminal can comprise a microprocessor, a communication interface, an image processing circuit communicatively coupled to the microprocessor, a plurality of imaging assemblies communicatively coupled to the image processing circuit, and one or more memory blocks communicatively coupled to the image processing circuit. Each imaging assembly of the plurality of imaging assemblies can be configured to output image frame data. The image processing circuit can be configured to receive the image frame data from at least one imaging assembly, buffer the image frame data received from at least one imaging assembly in at least one memory block, and/or process the image frame data received from at least one imaging assembly. The EIR terminal can be configured to output image frame data comprising decodable indicia and/or decoded message data corresponding to the decodable indicia.
US09342717B2	Tamper detection system and method A tamper detection system and method which uses a reader and one or more tags to detect tampering near a card reader slot or any other device subject to tampering. An example tamper detection method includes transmitting a signal to a tag adjacent a device susceptible to tampering, and setting an alarm condition when no reply signal or an incorrect reply signal is received in response to the signal.
US09342716B2	Software-defined multi-mode RFID read devices Devices and methods for reading multiple types of RFID tags having different frequencies and/or encoding schemes are disclosed. One or more search signals covering a plurality of RFID bands are transmitted. A presence indication of an RFID tag in one of the plurality of RFID bands is detected. An interrogating signal having a carrier frequency tuned to a frequency at which the presence indication is detected is transmitted. A tag response signal comprising tag information associated with the RFID tag is received. A digital response signal based on the tag response signal is digital signal processed to obtain the tag information.
US09342715B2	Marking paper products Methods of marking paper products and marked paper products are provided. Some methods include irradiating the paper product to alter the functionalization of the paper.
US09342713B2	Unlocking a storage device An electronic device has a lower power state in which power to a storage device is disabled. Predetermined information stored in a memory is useable to unlock the storage device during a procedure to transition the electronic device from the lower power state to a higher power state. The predetermined information is different from a credential for use in unlocking the storage device.
US09342711B2	Systems and methods for controlling access to peripherals of a computer system by software applications In general, the invention provides a computer architecture designed for enhanced data security. In embodiments, the architecture comprises two sub-systems, each with their own processing units and memories, and a defined set of interfaces that interconnect the two sub-systems and the external world. One sub-system is designed to provide a familiar environment for running computer applications. The other sub-system is designed to provide a secure bridge between the first sub-system and users via input and output devices.
US09342710B2	Electronic tamper detection An apparatus, method and package for electronic tamper detection. In one example, an apparatus, device or package for electronic tamper detection includes: a first inductor positioned at a first distance from a first conductive surface; a first oscillator generating a first frequency in dependence upon the first inductor; and a comparator setting a tamper detected status if the generated first frequency is not within an error tolerance to a pre-stored first frequency. One example of a method for fabricating an electronic tamper detection apparatus, device, or package is also provided.
US09342703B2	Managing storage permissions for logical volume managers A logical volume manager (LVM) may manage a plurality of logical volumes and a plurality of drives in a logical data storage using metadata stored on the plurality of drives. The metadata (e.g., global metadata) may include a first set of permissions for a storage location in one of the logical volumes. The LVM may analyze permission data (e.g., local permission data) associated with the storage location and may override the metadata (e.g., the permissions in the global metadata) with a second set of permissions obtained from the permission data. The LVM may use the second set of permission data to access the storage location (e.g., a logical volume, logical volume group, file, partition directory/folder, set of data blocks). Permission data may be generated based on an identifier for a virtual machine, computing device, or user, and may be generated based on user input.
US09342702B2	Controlling an analysis system of biological samples A method for controlling an analysis system is presented. The method comprises receiving, by an encryption unit, authentication data of a user. In the case of a successful authentication, a user-specific security code is generated by the encryption unit. The security code is outputted by the encryption unit to the authenticated user. The security code and the user-ID are received by an authentication unit coupled to the analysis system via a user-interface coupled to the authentication unit. The security code is decrypted by the authentication unit. If the decrypted security code matches with the user-ID, the user is authenticated at the authentication unit and an authentication signal is generated by the authentication unit for permitting the user to initialize at least one function of the analysis system.
US09342701B1	Digital rights management system and methods for provisioning content to an intelligent storage The present invention relates to digital rights management (DRM) for content that downloaded and saved to a storage device. The storage may be a disk drive, or network attached storage. In addition, the storage device performs cryptographic operations and provides a root of trust. The DRM employs a binding key, a content key, and an access key. The binding key binds the content to a specific storage and is based on a key that is concealed on the storage. The binding key is not stored on the storage device with the content. The content key is a key that has been assigned to the content. The access key is determined based on a cryptographic combination of the content key and the binding key. In one embodiment, the content is provisioned based on the access key and stored in encrypted form in the storage device.
US09342693B2	System and method of monitoring and controlling application files A system and method for updating a system that controls files executed on a workstation. The workstation includes a workstation management module configured to detect the launch of an application. A workstation application server receives data associated with the application from the workstation. This data can include a hash value. The application server module can determine one or more categories to associate with the application by referencing an application inventory database or requesting the category from an application database factory. The application database factory can receive applications from multiple application server modules. The application database factory determines whether the application was previously categorized by the application database factory and provides the category to the application server module. Once the application server module has the category, it forwards a hash/policy table to the workstation management module. Upon receipt of the hash/policy table, the workstation management module applies the policy that is associated with the launched application to control access to the application on the workstation.
US09342690B2	Method and apparatus for a scoring service for security threat management A method and system for providing a security threat scoring service to identify and prioritize potential security threats to an online service. The method and system include determining security threat patterns, comparing traffic to the online system with the security threat patterns, and identifying portions of the traffic as a potential security threat. The method and system include assigning a threat score to the potential security threat, and providing the threat score to the online service to enable the online service to secure against the potential security threat.
US09342678B2	Method for controlling content and digital device using the same The present specification discloses a method for controlling a thumbnail image page including thumbnail images with respect to visual information for which security is set, and a digital device using the same. The digital device according to the present specification provides a first thumbnail image page mode (“first mode” hereinafter) to a display unit when security information on a user corresponds to predetermined security information and provides a second thumbnail image page mode (“second mode” hereinafter) to the display unit when the security information on the user does not correspond to the predetermined security information. For example, the thumbnail image page displays thumbnail images with respect to visual information for which security is set in the first mode, whereas the thumbnail image page does not display thumbnail images with respect to visual information for which security is set in the second mode.
US09342674B2	Man-machine interface for controlling access to electronic devices This application relates to devices, methods and computer readable media that allow users using a first device to be easily authenticated. For example, while the first device is proximate to a second device, the first device requests user authentication using the one or more biometric sensors. After requesting the user authentication, the first device detects biometric information associated with the user with the one or more biometric sensors. In response to detecting the biometric information associated with the user, in accordance with a determination that the detected biometric information associated with the user meets authentication criteria, the first device provides credentials associated with the user to the second device. In accordance with a determination that the detected biometric information associated with the user does not meet the authentication criteria, the first device forgoes providing the credentials associated with the user to the second device.
US09342667B2	Extended OAuth architecture Method, device, and storage medium to receive a request to authorize a release of protected resource data, wherein the request includes one or more indicators that indicate one or more instances of the protected resource data being requested; identify a sensitivity level for each indicator of the protected resource data; determine whether the one or more indicators of the protected resource data require consent from a resource owner of the protected resource data; transmit a request, to a user device associated with the resource owner, for consent from the resource owner in response to a determination that at least one of the one or more indicators require consent from the resource owner; generate an authorization code in response to receiving consent from the resource owner; and transmit, to the sending device of the request, the authorization code.
US09342664B2	Method to make payment or charge safe transactions using programmable mobile telephones A system, method and mobile application for conducting financial transactions wherein a mobile device operated by a user is operably coupled to a server over a mobile communication network. Both the server and the user's mobile device store a user encryption key (UEK) and a user access key (UAK). A software application stored on the user's mobile device and the server are configured to conduct a transaction wherein a session key (SK) specific to the transaction is exchanged in an encrypted form based upon the UEK. The software application is further configured to i) generate transaction data, ii) access the UAK stored on the mobile device, iii) encrypt the UAK and transaction data into an encrypted form based upon the SK, and iv) send the UAK and transaction data in encrypted form from the mobile device to the server over the mobile communication network in order to conduct the transaction.
US09342663B2	Distributing media with variable resolution and format An image processor receives an image. The image processor creates a low-resolution copy of the image for distribution to one or more recipients. Prior to distribution, the image processor produces permission information specifying whether a recipient is enabled to retrieve a high-resolution copy of the image. In addition to transmitting the low-resolution copy of the image to the recipient, the image processor forwards the permission information to the recipient as well. The recipient uses the permission information to determine whether the recipient is enabled to retrieve the high-resolution copy of the image. If enabled, the recipient can retrieve the high-resolution copy of the image. If disabled, the recipient cannot retrieve the high-resolution copy of the image. Accordingly, the permission information transmitted with the low-resolution copy can be used as a way of preventing or allowing access to the higher resolution copy of the image.
US09342661B2	Apparatus and methods for rights-managed content and data delivery Methods and apparatus for providing access to content across a plurality of devices and environments. In one embodiment, a downloadable rights profile is utilized in order for a user device to determine whether to provide content to a subscriber. The user device is first registered to content delivery the network; the device then requests a rights profile indicating the rights of the subscriber associated with the device to access content. The rights profile is transmitted to the device. The rights profile may be configured to be valid only for a pre-determined time, thus enabling a subscriber's rights to be updated (including revoked). Security mechanisms may also be utilized to ensure access to content is limited only to authorized subscribers. In another embodiment, a user-based authentication procedure is utilized, thereby making the rights determination and content provision process completely agnostic to the underlying hardware.
US09342660B1	Detection of chemical analytes via optical correlations A method for detecting or identifying a chemical analyte includes measuring a nontrivial set of correlations between optical illumination wavelengths of a sample and emission wavelengths of the sample. The method includes comparing the measured set of correlations to a reference nontrivial set of correlations between optical illumination and emission wavelengths of a specific chemical analyte. The method also includes determining whether the specific chemical analyte is present in the sample based on a result of the comparing.
US09342656B2	Using EDS for extending a description of a loadware update mechanism The invention refers to a computer-implemented method and system for loading a loadware file on a CANopen device. The CANopen device comprises an electronic data sheet, which is extended to comprise a load object. After reading the load object with the load parameters, the respective loadware file is located, selected and accessed. Accessing the loadware file is done by applying the read load parameters.
US09342648B2	Optical proximity correction (OPC) accounting for critical dimension (CD) variation from inter-level effects Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.
US09342647B2	Integrated circuit design method and apparatus An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.
US09342643B2	Non-transitory computer readable medium storing timing analysis program, timing analysis device, and timing analysis method A timing analysis device includes a storage unit and a processing unit. The processing unit performs storage processing and analysis processing. The storage processing stores circuit information of a circuit to be analyzed, timing constraint information defining timing constraints on the circuit, delay information defining a plurality of delay values associated with a plurality of cells constituting the circuit, and delay upper limit information including at least one delay upper limit for setting an upper limit to the plurality of delay values associated with the plurality of cells into a storage unit. The analysis processing generates a timing analysis result of a circuit to be analyzed, with delay value change processing that changes at least one of the plurality of delay values to the delay upper limit, using the changed delay upper limit in addition to the circuit information, the timing constraint information and the delay information.
US09342637B2	Consumed power estimation device, electronic device, consumed power estimation method and recording medium A performance value DB stores multiple states of parts comprising a system, and the consumed power of parts in those states. In addition, a condition DB stores conditions when the states of the parts change. A calculator generates state sequences in which the states are arrayed in the order of change in accordance with conditions stored in the condition DB, when information indicating the states of the parts is not communicated. The calculator computes the percentage of the time the parts are in each state per unit time for each state comprising this state sequence. Furthermore, the calculator finds the products of the computed ratios and the consumed power stored in the performance value DB for each state comprising the state sequence, and estimates the sum of the products found as the consumed power of the part.
US09342635B2	Method for predicting the impact on an aircraft of debris shed off from it Computer-aided method to predict the location of an impact on an aircraft of debris shed off from the own aircraft comprising the following steps: a) providing the nominal position on the aircraft of said debris before its detachment; b) represent the debris by a body of a size and density appropriate to its characteristics; c) calculating a predetermined number of trajectories in three dimensions of said body in a predetermined fluid field when it is detached from the aircraft using an analytical model for calculating said trajectories and randomly varying one or more of the following initial conditions: the initial position of the body; the dimensions of the body; the damping coefficients of the angular velocity; the initial angles of roll, pitch and yaw; d) calculating the points of impact of said trajectories in the aircraft.
US09342634B2	Dormer calculator A method is disclosed for laying out a dormer that projects outward from a main roof and has a gable end and a dormer roof originating at a dormer point and terminating at an outer edge of the dormer roof near the gabled end. The dormer includes roof sheathing supported by dormer trusses. The dormer trusses include a gable truss and a plurality of valley trusses. The method includes receiving a plurality of dormer inputs from a user. A plurality of layouts for the roof sheathing on the dormer roof are generated as a function of the dormer inputs. One or more layouts are then recommended to a user to reduce a quantity of roof sheathing waste.
US09342633B2	System and method for manufacturing window frames An array of boxes in one or more carts is closely associated with addresses in a database of a computer. This computer-box association is used to keep track of the sequence, placement and presentation of each window frame element to each workstation. This association is maintained until these frame elements are assembled into rectangular window frames. Then, individual window frames are tracked into other workstations using bar code labels. Temporary storage of frame elements between workstations constitute work banks to each workstation. In another aspect, the lengths of frame elements are adjusted to compensate for the melt factor of the specific welding head in which a joint will be made.
US09342627B2	Determining word information entropies Determining and using word information entropies includes: determining one or more categories that correspond to a plurality of queries; sorting the plurality of queries into one or more groups based at least in part on the determined categories of the plurality of queries; segmenting queries that correspond to each of the one or more groups into a first plurality of phrases, wherein each phrase includes one or more words; determining occurrence probabilities for the plurality of phrases; and determining word information entropies for the plurality of phrases based at least in part on the determined occurrence probabilities.
US09342626B1	Query suggestions based on entity collections of one or more past queries Methods and apparatus for providing query suggestions to a user based on one or more past queries submitted by the user. Candidate query suggestions responsive to a current query may be identified. A candidate query similarity measure may be determined for a given candidate query suggestion based on matching entities related to the given candidate query suggestion and the one or more past queries. In some implementations, the similarity measure of the given candidate query suggestion may be based on a comparison of current entities of the given candidate query suggestion that match entities of one or more past queries, to a group of the current entities that includes entities that do not match the entities of one or more past queries. In some implementations a ranking of the candidate query suggestions may be determined based on the similarity measure.
US09342625B2	Management of a history of a meeting Provenance techniques are disclosed for managing a history of a meeting. For example, a method for managing a history associated with a meeting comprises the following steps. Data associated with the meeting is collected. Provenance data is generated based on at least a portion of the collected data, wherein the provenance data is indicative of a lineage of one or more data items. A provenance graph is generated that defines a visual representation of the generated provenance data, wherein graph elements comprise one or more nodes and one or more edges between nodes, wherein nodes of the graph represent records associated with the collected data and edges of the graph represent relations between the records. One or more applications are associated with at least one graph element and are selectable to invoke functionality. The generated provenance graph is stored in a repository for use in analyzing the meeting.
US09342623B2	Automatically generating nodes and edges in an integrated social graph In one embodiment, a method includes maintaining access to a data store of information corresponding to nodes and edges; receiving a user-generated character string comprising one or more characters of text entered by a user in an input form as they are entered by the user; searching the stored information for matches between the user-generated character string and existing nodes; determining whether or not a match between the user-generated character string and an existing node exists; and when it is determined that at least one match exists, generating an edge between the node corresponding to the user and the node for which the best match is determined; and when it is determined that no match between the user-generated character string and an existing node exists, generating a new node based on the user-generated character string, and generating an edge between the node corresponding to the user and the new node.
US09342618B2	Web application compositon and modification editor According to some embodiments, a method and apparatus are provided to receive a request to view a web page from a mobile device, determine characteristics associated with the user, select a web page layout based on the determined characteristics, and provide the web page based on the selected web page layout to the mobile device.
US09342614B2	Asymmetric identification of interest twins in an online community Techniques are described for identifying one or more “interest twins” of a user. An interest twin of a user in another user that has demonstrated interests in items that are the same as or similar to the items in which the user has demonstrated an interest. Various techniques are described for reducing the overhead in interest twin determination operations. Once the interest twins for a user have been identified, the knowledge of the interest twins may be used in a variety of ways to enhance to experience of the user. For example, a mechanism may be provided which allows the user to see a list of items in which the user's interest twins have indicated an interest.
US09342610B2	Portals: registered objects as virtualized, personalized displays A see-through head-mounted display (HMD) device provides an augmented reality image which is associated with a real-world object, such as a picture frame, wall or billboard. Initially, the object is identified by a user, e.g., based on the user gazing at the object for a period of time, making a gesture such as pointing at the object and/or providing a verbal command. The location and visual characteristics of the object are determined by a front-facing camera of the HMD device, and stored in a record. The user selects from among candidate data streams, such as a web page, game feed, video or stocker ticker. Subsequently, when the user is in the location of the object and looks at the object, the HMD device matches the visual characteristics to the record to identify the data stream, and displays corresponding augmented reality images registered to the object.
US09342609B1	Ranking custom search results A system searches a first search index based on a search query to obtain first search results and searches a second search index based on the search query to obtain second search results. The system further ranks the first search results using a first ranking algorithm and one or more first ranking parameters to produce ranked first search results, and ranks the second search results using a second ranking algorithm and one or more second ranking parameters to produce second search results, where the one or more first ranking parameters are different than the one or more second ranking parameters and where the one or more second ranking parameters include at least one of previous user feedback associated with custom content that corresponds to the second search index, annotations of the custom content provided by a user, or usage patterns associated with users previously accessing and searching the custom content. The system also provides the ranked first and second search results to a user.
US09342604B2	Collaborative search A collaborative search is disclosed. The collaborative search includes receiving a search request of a mobile terminal. Searching based on the search request to obtain search results. Obtaining a relationship list associated with an identifier of the mobile terminal. Obtaining search history information associated with members in the relationship list based on the relationship list and ranking the search results based on the search history information.
US09342601B1	Query formulation and search in the context of a displayed document Technology described herein enhances a user's search experience by providing refined search results that are relevant to a displayed document. Contextual search results are obtained which identify a list of documents responsive to a formulated query that is based on the user's search query, as well as one or more supplemental terms that are based on content in the displayed document during user entry of the search query. The contextual search results are then “refined” by re-ranking the documents in the list, based on the similarity between the user's original search query and terms in these documents. This re-ranking enables contextual search results to be provided that are also highly relevant to the user's informational need.
US09342600B1	Populating query suggestion database using chains of related search queries A system, computer-readable storage medium storing at least one program, and a computer-implemented method for identifying chains of related search queries is presented. Historical search query data is obtained. Chains of related search queries issued by users and search results corresponding to last related search queries in the chains of related search queries that were selected by the users are identified from the historical search query data, where each related search query in a chain of related search queries except for a last related search query in the chain of related search queries violates a search result selection criterion. The chains of related search queries are aggregated into groups, where a respective group has a common first search query and a common search result corresponding to at least one last related search query that was selected by the users. Aggregate data for the groups are stored in a query database.
US09342597B1	Associating an event attribute with a user based on a group of electronic messages associated with the user Methods and apparatus related to associating an event attribute with a user based on a group of electronic messages associated with the user. An event may be associated with the group of electronic messages. One or more event attributes of the event may be determined, including an event location identifier that identifies a physical event location. One or more of the event attributes may be determined based on the group of electronic messages. Location data of the user may be identified and a likelihood that the user interacted with the physical event location may be determined based on comparing the location data of the user to the event location identifier. The likelihood that the user interacted with the physical event location and at least one of the event attributes determined based on the group of electronic messages may be associated with the user.
US09342590B2	Keywords extraction and enrichment via categorization systems Techniques for determining a set of keywords associated with a document are provided. A document is received that may be classified into a taxonomy that includes a plurality of categories. A categorization ranking is determined for each category for the received document. A set of categories of the taxonomy having highest categorization rankings is determined for the received document. Documents representing the set of categories having highest categorization rankings are combined together into a cumulative representative text that includes a plurality of terms. A cumulative term corpus importance score is determined for each term in the cumulative representative text. The cumulative term corpus importance score for a particular term indicates an importance of the particular term in a context of the cumulative representative text. A set of terms of the cumulative representative text having highest cumulative term corpus importance scores is selected to be keywords for the received document.
US09342588B2	Reclassification of training data to improve classifier accuracy A method of creating a statistical classification model for a classifier within a natural language understanding system can include processing training data using an existing statistical classification model. Sentences of the training data correctly classified into a selected class of the statistical classification model can be selected. The selected sentences of the training data can be assigned to a fringe group or a core group according to confidence score. The training data can be updated by associating the fringe group with a fringe subclass of the selected class and the core group with a core subclass of the selected class. A new statistical classification model can be built from the updated training data. The new statistical classification model can be output.
US09342587B2	Computer-implemented information reuse Embodiments of the present invention relate to an approach for reusing information/knowledge. Specifically, embodiments of the present invention provide an approach for retrieving previously stored data to satisfy queries (e.g., jobs/tickets) for solutions to problems while maintaining privacy/security of the data as well as ensuring the quality of the results. In a typical embodiment, a query for a solution to a problem is received and details are extracted therefrom. Using the details, a search is performed on a set of data stored in at least one computer storage device. Based on the search, a set of results will be generated and classified into a set of categories. In any event, the quality of each of the set of results will be assessed based on the usefulness of the set of results.
US09342584B2	Server apparatus, information terminal, and program Provided is a server apparatus, including: keyword storage capable of storing event-identification information and one or more keywords in relation to each other, the event-identification information identifying an event, the one or more keywords relating to the event; and a first keyword-registering section configured to obtain event-identification information and detailed information from an event-information registering server, the event-identification information identifying an event, the detailed information being on the event, to extract one or more first keywords from the obtained detailed information, and to register the one or more extracted first keywords and the event-identification information in relation to each other in the keyword storage.
US09342583B2	Book content item search Methods, systems, and apparatus, including computer program products are provided for ranking distinct book content items based on implicit links to other distinct book content items. The implicit links are defined based on the identification of matching features in the distinct book content items. In some implementations, the matching features are uncommon phrases in textual content of the distinct book content items. Edges representing implicit links are generated between distinct nodes representing distinct book content items in a weighted graph. Search results for distinct book content items can be ordered based on the edges connected to the distinct nodes in the weighted graph that represent the distinct book content items.
US09342582B2	Selection of atoms for search engine retrieval Methods are provided for populating search indexes with atoms identified in documents. Documents that are to be indexed are identified, and for each document, atoms are identified and are categorized as unigrams, n-grams, and n-tuples. A list of atom/document pairs is generated such that an information metric can be computed for each pair. An information metric represents a ranking of the atom in relation to the particular document. Based on the information metric, some atom/document pairs are discarded and others are indexed.
US09342579B2	Visual analysis of multidimensional clusters Visualization techniques are provided for a clustered multidimensional dataset. A data set is visualized by obtaining a clustering of a multidimensional dataset comprising a plurality of entities, wherein the entities are instances of a particular concept and wherein each entity comprises a plurality of features; and generating an icon for at least one of the entities, the icon having a plurality of regions, wherein each region corresponds to one of the features of the at least one entity, and wherein a size of each region is based on a value of the corresponding feature. Each icon can convey statistical measures. A stabilized Voronoi-based icon layout algorithm is optionally employed. Icons can be embedded in a visualization of the multidimensional dataset. A hierarchical encoding scheme can be employed to encode a data cluster into the icon, such as a hierarchy of cluster, feature type and entity.
US09342578B1	Organizing indications of approval for collections A system and method for organizing indications of approval using a collection application is disclosed. The collection application includes a processing module, a social network application, a collection module, a sharing module, a permission module, a user interface engine and a suggestion module. The processing module receives an indication of approval submitted by a user. The collection module groups the indication of approval into a collection. The sharing module shares the collection with one or more users. The suggestion module suggests a collection or indications of approval to a user. The user interface engine generates a user interface that includes the collection.
US09342577B2	Preference-based data representation framework Described herein is a technology for facilitating preference-based data representation. In accordance with one aspect of the technology, preference information is acquired from a user. Rank scores of objects are generated based at least in part on the user preference information. The objects are grouped into one or more clusters of objects based on the rank scores. A visualization of the one or more clusters of objects is then generated.
US09342572B2	Workflow processing system and method with database system support Methods and apparatus, including computer program products, implementing and using techniques for automatic workflow processing in a workflow processing computer system. A data management system support module receives a data management activity description, determines a set of set references associated with the data management activity, determines a set of data sources associated with the set of set references within a data management system, determines whether the data management system includes infrastructure for accessing the references and for accessing the data sources, in response to determining that the infrastructure is not included, automatically creates the infrastructure from information in a metadata repository coupled to the data management system, replaces in the data management activity description references to set references and references to data sources by references to the infrastructure in the data management system, and delivers the data management activity description for execution by the system.
US09342571B1	Selective structure preserving obfuscation Obfuscating data is disclosed. A processor identifies structured information in log data. The structured information is transformed in a manner that preserves the structure to form transformed raw data. The transformed raw data is sent to a remote analysis engine. The remote analysis engine receives a query and responds to the query by providing as results at least a portion of the transformed raw data. A processor is configured to de-transform the transformed raw data.
US09342568B2	Reducing metadata controller communication volume Apparatus, methods, and other embodiments associated with reducing metadata controller communication volume are described. One example apparatus produces tracking data by tracking metadata controller communications and then controls which of two different types of metadata controller communication message types are used for metadata controller communications based, at least in part, on the tracking data. One message type provides actual state and/or location information about a metadata controller. A second message type provides only information about the state and/or location information available at a metadata controller. Selectively using the second message type facilitates reducing metadata controller communication volume.
US09342567B2	Control for persistent search results and iterative searching An embodiment of the invention provides a method for control for persistent search results and iterative searching where a query from a user is received via a web browser and a web search for the query is performed with a processor. Search results of the web search are displayed in a toolbar of the web browser, wherein at least one of the search results in the toolbar includes a refinement option. The refinement option can include a show me more like this refinement option and/or a show me less like this refinement option. A selected refinement option is received from the user with a user interface; and, refined search results are displayed in the toolbar based on the selected refinement option.
US09342566B2	Systems and methods for searching data structures of a database Method and systems may be used to provide search results in response to plain language queries from a database. A search query may be received and a database may be queried. A metadata search of the database data structures may be performed to determine a search set based on the search query. Using the search set, a data search may be performed to determine the database data structures for a result set. Result data structures may be generated based on the result set. The result data structures may be iteratively provided to a client to display the search results responsive to the search query quickly. The relevant data may be retrieved from the database in response to a selection. In some instances, the results retrieved from the database in response to a selection of a result data structure may be limited based on a count parameter.
US09342563B2	Interface for a universal search A search engine may perform a search for a user search query over a number of possible search categories. For example, the search query may be performed for general web documents, images, and news documents. The search engine ranks categories based on the search query and/or the documents returned for each category and presents the search results to the user by category. Higher ranking categories may be presented more prominently than lower ranking categories.
US09342562B2	Database anonymization At least one quasi-identifier attribute of a plurality of ranked attributes is selected for use in anonymizing a database. Each of the ranked attributes is ranked according to that attribute's effect on a database-centric application (DCA) being tested. In an embodiment, the selected quasi-identifier attribute(s) has the least effect on the DCA. The database is anonymized based on the selected quasi-identifier attribute(s) to provide a partially-anonymized database, which may then be provided to a testing entity for use in testing the DCA. In an embodiment, during execution of the DCA, instances of database queries are captured and analyzed to identify a plurality of attributes from the database and, for each such attribute identified, the effect of the attribute on the DCA is quantified. In this manner, databases can be selectively anonymized in order to balance the requirements of data privacy against the utility of the data for testing purposes.
US09342556B2	RDF graphs made of RDF query language queries A method, software and/or computer system for representing a set of SPARQL queries. The set of SPARQL queries are converting into an RDF representation of the set of SPARQL queries (that is, a SPARQL RDF graph). The SPARQL RDF graph is applied to a target RDF graph to yield a transformed target representing the responses to the set of queries, as an ontology or as text.
US09342553B1	Identifying distinct combinations of values for entities based on information in an index A server system having one or more processors and memory receives, from a requestor, a select distinct query. In response to the query, the server system identifies a set of index portions according to requestor-specified filter criteria. The server system identifies one or more distinct value combinations for entities satisfying the filter criteria, including: obtaining an initial value of a query cursor; retrieving candidate value combinations; comparing candidate value combinations to identify distinct value combinations, if any, in accordance with the query; and updating the current value of the query cursor. The server system repeats the retrieving candidate value combinations and the comparing candidate value combinations one or more times for the set of index portions until at least a respective distinct value combination has been identified and transmits information corresponding to the respective distinct value combination to the requestor.
US09342552B2	Graphical user interface for map search Particular embodiments include a method comprising accessing location data representing a first location of a first user wherein the first location corresponds to geographic coordinates, retrieving image data defining a graphical map from a remote server based on the first location accessing a search query inputted by the first user, retrieving one or more second locations in response to the search query, where the one or more second locations correspond to geographic coordinates, and displaying a first view comprising a list of the one or more second locations overlaying at least a portion of the graphical map, wherein the graphical map includes indicators for the first location and at least one of the one or more second locations in accordance with their respective geographic coordinates.
US09342549B2	Partition level operation with concurrent activities Techniques of implementing partition level operations with concurrent activities are disclosed. A first operation can be performed on a first partition of a table of data. The first partition can be one of a plurality of partitions of the table, where each partition has a plurality of rows. A first partition level lock can be applied to the first partition for a period in which the first operation is being performed on the first partition, thereby preventing any operation other than the first operation from being performed on the first partition during the period the first partition level lock is being applied to the first partition. A second operation can be performed on a second partition of the table at a point in time during which the first operation is being performed on the first partition.
US09342546B2	Extract operator In one embodiment, a method includes receiving, from a user, a search query requesting objects of a first object type. The search query includes an inner query requesting objects of a second object type. The method includes identifying objects of the second object type requested by the inner query using an inverted index of a data store corresponding to the second object type; identifying objects of the first object type requested by the search query using the identified objects of the second object type and a forward index of the data store corresponding to the second object type; and sending search results to the user responsive to the search query, each search result corresponding to an identified object of the first object type.
US09342543B2	Three-dimensional time series data A system, device, computer program product, and/or method generates display data that allows a user to ascertain relationship between related electronic information from among sent and received electronic information. The three-dimensional time series data processing system selects one electronic information, extracts electronic information relating to the selected electronic information from the electronic information database, calculates relevance between the sender of the selected electronic information and the sender of the extracted electronic information, and generates three-dimensional time series data for three-dimensionally rendering a relationship between the selected electronic information and the extracted electronic information as positional information of the respective extracted electronic information in a virtual three-dimensional space, where the sender, the send time and the relevance are axes. In addition, the three-dimensional time series data processing system renders three-dimensional time series data for relevance of electronic information in cylindrical coordinates and displays the data while modifying a viewing angle.
US09342538B2	Electronic device and database accessing method In a database accessing method using an electronic device having a database, character fields and corresponding attributes are predefined. An entity object including the character fields is generated and provided to a client device for inputting business data. After receiving an encapsulated entity object from the client device, the business data including selected character fields, corresponding character data, and an operation request for the database are acquired. When the database includes a data table and the data table includes the character fields corresponding to the selected character fields, the selected character fields and the character data of the selected character fields are verified. When the selected character fields and the character data of the selected character fields are valid, character data of the character fields corresponding to the selected character fields are updated using the character data of the selected character fields according to the operation request.
US09342537B2	Integrated snapshot interface for a data storage system A data storage system includes a generic snapshot interface, allowing for integration with a wide variety of snapshot-capable storage devices. The generic interface can be a programming interface (e.g., an application programming interface [API]). Using the snapshot interface, storage device vendors can integrate their particular snapshot technology with the data storage system. For instance, the data storage system can access a shared library of functions (e.g., a dynamically linked library [DLL]) provided by the vendor (or another by appropriate entity) and that complies with the specifications of the common programming interface. And by invoking the appropriate functions in the library, the data storage system implements the snapshot operation on the storage device.
US09342536B2	Intent based automation of data management operations by a data management engine Provided are a method, computer program product, and system for processing a data management request. User intent that defines properties of target data is determined. Policies and constraints for the data management request are determined. An abstract data management request that identifies source data, the target data, and the polices and constraints is created. A technology to use to process the data management request based on the user intent, policies, and constraints is determined.
US09342535B2	Logging events in media files Logging events in a media file, including: providing a logger tool to allow a user to view media in multiple ways and to capture and validate key events within the media file; and tracking and logging events in the media file by adding information to the media file including locations of bars and tone, slates, content, logos, commercial blacks, quality control issues, subtitles, and captions.
US09342532B2	System and method for real-time map-based lost and found A system and method for lost and found includes enabling information about found objects to be stored in real time. The method further includes enabling adjustment of a field of view of an interactive map. The method further includes receiving a search input for search of a lost object. The method further includes performing a search for the lost object based on at least the stored information about the found objects, the search input, and the field of view of the interactive map. The method further includes enabling results of the search to be overlaid on the interactive map.
US09342531B2	Managing conflicted copies Various embodiments provide a method of managing and preventing conflicted copies of a content item. For example, as changes are made to a content item, either by multiple users simultaneously or by a single user utilizing multiple devices, conflicted copies can be inadvertently created. These conflicted copes are multiple copies of the same content item where each copy may separately contain unique changes. Heuristics can be used to help users more easily avoid or manage these conflicted copies. In one example, a user could be notified and shown the difference between copies to either accept or reject changes. Further, users could also be notified when modifying a content item on a device that has not been synchronized in a determined period of time, or when the content item is known to be modified but the changes have yet to be synchronized to the device.
US09342530B2	Method for skipping empty folders when navigating a file system A method for skipping empty folders when navigating a file system. When a parent folder only contains a single child folder and a user is trying to view the contents of the parent folder, the user will be directed to the contents of the child folder rather than the contents of the parent folder. When multiple nested folders are present in a particular path, all nested folders containing only a single child folder will be skipped and the user will be taken directly to the first nested folder in the hierarchy that contains multiple data items, a single file, or no data.
US09342526B2	Providing storage resources upon receipt of a storage service request A mechanism is provided for providing storage resources of a storage management system. A storage service request is received comprising an indication of a service class. A determination is made of all resource managers mapped to the indicated service class according to a first mapping. For each of the determined resource managers: a determination is made of selected ones of all the storage resources controllable by the determined resource manager; monitoring data of the selected storage resources is gathered; the gathered monitoring data is compared for calculating a score for each one of the selected storage resources; and at least one function of the determined resource manager operable to control the storage resource having an optimum score is called.
US09342525B1	Multi-deduplication Example apparatus and methods improve deduplication efficiency for a deduplication application or process. A first blocklet repository may have been created according to a first deduplication approach that was optimized for a first set of conditions. Example apparatus and methods create a second blocklet repository from the first blocklet repository by deduplicating the first blocklet repository using a second deduplication approach that is optimized for a second set of conditions. While the first blocklet repository may have been appropriate for the first set of conditions, the second blocklet repository may be appropriate for the second set of conditions. For example, conditions that exist for an immature repository or during ingest may be different than conditions that exist for a mature repository or for applications that use a repository rather than build a repository. The first and second repositories may reside on separate deduplication apparatus.
US09342523B2	Data storage device and computer-readable storage medium An object of the present invention is to enable a storage location for data, such as a file, to be specified by a simple operation using an identifier such as a two-dimensional code. A data storage device of the present invention is provided with a selecting section which selects arbitrary data, a reading section which reads an identifier, a recognizing section which recognizes a storage destination for the data from a result of reading by the reading section, and a storing section which stores the data in the storage destination recognized by the recognizing section.
US09342512B1	System and method for repairing data synchronization links A system for detecting and repairing errors in synchronization links for data records includes a first data repository containing a first data record that maintains a data field which links to associated data records) and a self-reference record. The system also includes a second data repository containing a second data record that also maintains a data field which links to associated data records) and a self-reference record. The system also includes a synchronizer that maintains a data table containing the addresses of the first and second data records and the status of any previous synchronization activity.
US09342511B2	Fast selection in hardware or software In an exemplary embodiment, a computer-implemented method includes receiving an instruction to select an output set from an input set, where the output set is a top subset or a bottom subset of the input set, where the input set comprises a plurality of members, and where each member of the input set includes a plurality of bits. A first subset of the plurality of bits is selected. A histogram is generated, by a computer processor, based on the values in the first subset of the plurality of bits. A threshold value of the input set is determined, where the threshold value separates the values of the output set from the values of the remainder of the input set, and where the threshold value is based at least in part on the histogram. The output set is then extracted from the input set based on the threshold value.
US09342510B1	State handles State handles mark application data states within a sequence of operations for preservation. Applications can maintain non-linear sets of operations that include multiple sequences of operations between state handles. Applications can determine a sequence of operations between any two state handles, allowing applications to change from the data state associated with one state handle to the data state associated with another state handle. The sequence of operations between any two state handles may include executing operations and/or reversing operations. An application automatically adds new branches in the set of operations to preserve the sequences of operations necessary to reconstruct data states of previously set handles and removes branches that are not needed. Applications may use state handles to implement non-linear undo and redo functions, to validate journal entries, to combine incremental operations into a cumulative operation, and to speculatively execute operations for error detection, user guidance, or performance optimization.
US09342506B2	In-context exact (ICE) matching Methods, systems and program product are disclosed for determining matching level of a text lookup segment with a plurality of source texts in a translation memory in terms of context. The invention determines exact matches for the lookup segment in the plurality of source texts, and determines, in the case that at least one exact match is determined, that a respective exact match is an in-context exact match for the lookup segment in the case that a context of the lookup segment matches that of the respective exact match. Degree of context matching required can be predetermined, and results prioritized. The invention also includes methods, systems and program products for storing a translation pair of source text and target text in a translation memory including context, and the translation memory so formed. The invention ensures that content is translated the same as previously translated content and reduces translator intervention.
US09342503B1	Correlation across languages Proper nouns may be correlated across languages by identifying a proper noun term in a first language and identifying a translation associated with the proper noun term, when available. A determination may be made as to whether one or more data stores associates the proper noun term with the translation, and the translation may be correlated with the proper noun term based on the determination.
US09342502B2	Contextual validation of synonyms in otology driven natural language processing Embodiments described herein provide approaches for validating synonyms in ontology driven natural language processing. Specifically, an approach is provided for receiving a user input containing a token, structuring the user input into a semantic model comprising a set of classes each containing a set of related permutations of the token, designating the token as a synonym of one of the set of related permutations, annotating the token with a class from the set of classes corresponding to the one of the set of related permutations, and validating the annotation of the token by determining an accuracy of the designation of the token as a synonym of the one of the set of related permutations. In one embodiment, the accuracy is determined by quantifying a linear distance between the token and a contextual token also within the user input, and comparing the linear distance to a pre-specified linear distance limit.
US09342501B2	Preserving emotion of user input An aspect provides a method, identifying: receiving, at an input component of an information handling device, user input comprising one or more words; identifying, using a processor of the information handling device, an emotion associated with the one or more words; creating, using the processor, an emotion tag including the emotion associated with the one or more words; and storing the emotion tag in a memory. Other embodiments are described and claimed.
US09342499B2	Round-trip translation for automated grammatical error correction Systems and methods are provided for correcting a grammatical error in a text sequence. A first text sequence in a first language is received. The first text sequence is translated to a second language to provide a first translated text. The first text sequence is translated to a third language to provide a second translated text. The third language is different from the second language. The first translated text is translated to the first language to provide a first back translation. The second translated text is translated to the first language to provide a second back translation. A plurality of candidate text sequences that include features of the first back translation and the second back translation are determined. The plurality of candidate text sequences include alternative grammatical options for the first text sequence. The plurality of candidate text sequences are scored with the processing system.
US09342498B2	System and method for generating a design template based on graphical input The present invention relates to the field of graphic design. Specifically, embodiments of the present invention provide a system and method of generating a design template, such as a website template, that matches the color and style of graphical content, such as a logo provided to the system.
US09342496B2	Auto-completion of names Automatically completing a remainder portion of a name as it is being entered is disclosed. In some embodiments, in response to receiving at least a prescribed number of starting characters of a name being entered into a first cell as a reference name to refer to one or more other cells, a set of one or more valid reference names that begin with the received starting characters is determined and provided as auto-completion options. In such cases, a valid reference name is one that identifies using a supported syntax a spreadsheet document or a portion of a spreadsheet document.
US09342495B2	Methods, software and devices for improving visibility of user-filled data in an electronic form Methods, software, and devices for processing a user-filled form are disclosed. A parsable electronic representation of the user-filled form is received. Based on parsing this electronic representation, at least one of a first or a second subset of input elements is identified. The first subset of input elements represents input fields that have received user-filled data while the second subset of input elements represents input fields that have not received user-filled data. Those text elements representing text providing descriptive context to input fields represented by the identified subset of input elements are associated with the identified subset of input elements. A graphical representation of the user-filled form is generated. In this graphical representation, text represented by text elements associated the first subset of input elements are highlighted relative to text represented by text elements associated with the second subset of input elements.
US09342494B2	Automated annotation of a resource on a computer network using a network address of the resource A user provides an annotation, such as text or graphics, in relation to a resource available on a computer network. The annotation is automatically stored and/or retrieved without requiring separate action from the user to accomplish the storage or retrieval. An annotation interface may receive the annotation from the user. The annotation is then stored in association with the user and the network address of the resource. The user's annotation may be later retrieved and displayed to the user based on the network address of the resource. In one specific embodiment, a browser toolbar receives and displays user annotations associated with Web sites or Web pages to which the user has navigated. Preferably, the annotation interface remains available to the user throughout the time in which the resource is provided. Further controls may enable the user to make an annotation publicly available to others, and to receive annotations from others.
US09342487B2	Method for layout of speech bubbles associated with characters in an image A system and method of speech bubbles layout are described. A context module determines geometric constraints of speech bubbles for characters in an image and features of the characters in the image, receives a speech content for one or more characters, and identifies a conversation order of the characters. A layout module generates a layout of the speech bubbles based on the features of the characters, the speech content, and the conversation order. The layout of the speech bubbles is within the geometric constraints of the speech bubbles in the image.
US09342485B2	Methods and systems for conditioning signals from a speed sensor A circuit for use in conditioning a signal from a speed sensor. The circuit is configured to receive an analog signal from a speed sensor coupled to the circuit, acquire a threshold of the analog signal, generate a digital signal corresponding to the analog signal, based on the threshold, and output the digital signal.
US09342480B2	Apparatus and method for generating VLIW, and processor and method for processing VLIW An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.
US09342478B2	Processor with reconfigurable architecture including a token network simulating processing of processing elements Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory stores configuration data associated with controlling data flow of the respective PEs. The token network reads the configuration data from the configuration memory, estimates data flow of the PEs from the read configuration data, reads required configuration data from the configuration memory based on the estimated data flow, and supplies the required configuration data to corresponding PEs. By reducing configuration memory access frequency through a token network, power consumption may be reduced.
US09342476B2	Image processing apparatus, information processing apparatus, and information processing system An image processing apparatus that outputs images includes: a storage unit that stores therein a printer driver, in which configurations and functions related to image outputs are described in a text format, and device information indicating configurations related to image outputs in the image processing apparatus; a receiving unit that receives, from an information processing apparatus connected via a communication line, a transmission request message that requests transmission of the printer driver; a reflecting unit that reflects the device information on the printer driver when the receiving unit receives the transmission request message; and a transmitting unit that transmits the printer driver, on which the device information is reflected by the reflecting unit, to the information processing apparatus.
US09342475B2	Generating infrared communications on a mobile device A system and a method are disclosed for generating an infrared signal on a mobile device. The infrared signal is generated on a mobile device by generating a bitstream based on information to be transmitted as an infrared signal. The bitstream is modulated and output on a bus to an infrared-emitting diode. The bitstream is processed in a software layer configured on the computing device, enabling the computing device to generate and process signals without additional hardware configured on the device.
US09342469B2	Image forming apparatus and host computer capable of sharing terminology, method of sharing terminology and terminology sharing system A host apparatus capable of sharing terminology information and a peripheral device, a method of sharing the terminology information, and a terminology information sharing system. The host apparatus includes a communication module to provide a communication interface between the host apparatus and the peripheral device, an information sharing unit to share terminology information related to a plurality of functions of the peripheral device, and a user interface unit to operate the plurality of functions of the peripheral device and to display the shared terminology information related to each of the plurality of functions. Accordingly, the peripheral device and the host apparatus use identical terminology information related to the functions of the peripheral device.
US09342467B1	Virtual window system A virtual window system that allows a viewer to believe that he or she is looking at an actual window when actually looking at our system attached to a wall. The virtual window system comprises four elements: a processor, a computer, a monitor, and a frame. The processor is a conventional device for controlling information and lighting to achieve specified results. The computer-readable storage medium in communication with the processor is configured to transmit a digital image sequence to the monitor. The monitor is in communication with the computer-readable storage medium and the processor and is configured to display the digital image sequence. The frame surrounds the monitor with a back, a front, a top, and sides, and includes at least one light source configured to transmit light into an indoor environment to simulate an actual window.
US09342461B2	Cache memory system and method using dynamically allocated dirty mask space A cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks. A cache controller is configured to allocate one of the dirty masks to each of the cache memory lines when a write to the respective cache memory line is not a full write to that cache memory line. Each of the dirty masks indicates dirty states of data units in one of the cache memory lines. The cache controller may include a dirty buffer index which stores an identification (ID) information that associates the dirty masks with the cache memory lines to which the dirty masks are allocated. A cache line may include a fully dirty flag indicating when each byte in that cache line is dirty, so that a dirty mask does not need to be allocated for that cache line.
US09342459B2	Cache management in a mobile device A user visiting a space is equipped with a mobile device in communication with a service system. Media items held by the service system are associated with various locations around the space and a user arriving at such a location is presented with the corresponding item or items. Preferably, these media items are pre-emptively loaded into a cache of the user's mobile device in dependence on the user's progress around the space. Items can also be flushed from cache on this basis. Instead of, or as a precursor to, flushing an item from cache to free up space, the cache space occupied by an item is reduced by degrading it.
US09342457B2	Dynamically modifying durability properties for individual data volumes A block-based storage system may implement dynamic durability adjustment for page cache write logging. A rate of incoming write requests for data volumes maintained at a storage node may be monitored. Based, at least in part, on the rate of incoming write requests, a dynamic modification to a durability property for a data volume may be made, such as enabling page cache write logging the data volume or disabling write logging for the data volume. When incoming write requests are received, a determination may be made as to whether page cache write logging for a particular data volume is enabled. For write requests with disabled page cache write logging, the page cache may be updated and the write request may be acknowledged without storing a log record describing the update in a page cache write log.
US09342456B2	Storage control program for hierarchy relocation control, storage system with hierarchy relocation control and hierarchy control apparatus thereof A non-transitory computer readable storage medium that stores a storage control program causing a computer to execute a control process of a storage including a first storage device with first access speed, and a second storage device with second access speed that is slower than the first access speed, includes monitoring access frequency to data in the first and second storage devices; relocating data, the access frequency of which exceeds a first reference value, in the second storage device, to the first storage device; and conducting a overload processing of retaining, in the cache memory, at least a part of the data in the second storage device when the second storage device is in an overload state. the access frequency monitoring is executed in a state where the partial data is retained in the cache memory, and the relocating is executed based on the access frequency to the partial data.
US09342451B2	Processor management method A processor management method includes setting a master mechanism in a given processor among multiple processors, where the master mechanism manages the processors; setting a local master mechanism and a virtual master mechanism in each of processors other than the given processor among the processors, where the local master mechanism and the virtual master mechanism manage each of the processors; and notifying by the master mechanism, the processors of an offset value of an address to allow a shared memory managed by the master mechanism to be accessed as a continuous memory by the processors.
US09342450B2	On-demand hypervisor memory mapping A mechanism for on-demand hypervisor memory mapping is disclosed. A method of the invention includes trapping an access instruction to a memory location from a virtual machine (VM) managed by a hypervisor of a host machine, determining whether a number of accesses to the memory location by the VM exceeds a threshold, if the number of accesses to the memory location by the VM does not exceed the threshold, then emulating the access instruction to the memory location on behalf of the VM, and if the number of accesses to the memory location by the VM exceeds the threshold, then allocating guest physical memory for the VM associated with the memory location.
US09342446B2	Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache A non-volatile memory system includes a memory section having a non-volatile cache portion storing data in a binary format, a primary user data storage section that stores user data in multi-state format, and an update memory area where the memory system stores data updating user data previously stored in the primary user data. The memory system allows a maximum number of blocks for use in the update memory area. When the memory system receives updated data corresponding to user data already written into the primary user data storage section, it determines whether a block of memory is available in the update memory area. In response to determining that a block of memory is not available in the update memory area, the system determines a block of the update memory to remove from the update memory; copies the data content of the determined update block into the cache portion of the memory section; and subsequently writes the updated data into the update memory.
US09342445B2	System and method for performing a direct memory access at a predetermined address in a flash storage A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.
US09342443B2	Systems and methods for memory system management based on thermal information of a memory system Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.
US09342439B2	Command coverage analyzer A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided.
US09342438B2	Method and system for data-triggered dynamic log level control Embodiments of the present teachings disclose method, system, and programs for data driven dynamic logging. Data is received by a logging system where the data is flagged for dynamic logging when one or more dynamic flagging level criteria are satisfied. Data is evaluated by a logging module wrapper, which determines whether to log the data using the default logging level or dynamic logging level, according to whether the data is flagged. A logging module logs information in a logging database according to the default logging level or dynamic logging level. Based on the logged information and detected abnormalities the dynamic flagging level and dynamic logging level are automatically or manually adjusted.
US09342433B2	Elapsed cycle timer in last branch records A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.
US09342431B2	Technique to generically manage extensible correlation data A technique to generically manage extensible correlation data is provided for correlating a series of events. The technique employs a global unique identifier (GUID) for identifying an event and uses the GUID as a key to associate one or more extensible correlators of correlation data. A transport correlator may be configured to transport the GUID for associating with a GUID of a second event such that a small and fixed amount of data is passed by the communications layer providing the transport, minimally impacting communications. An arbitrary amount of data may be logged and keyed with the GUID, providing optimization and flexibility.
US09342428B2	Mobile terminal and method for managing the file system thereof A mobile terminal and a method for managing a file system thereof are provided. The method of managing a file system of a mobile terminal having a battery cover and a battery cover coupling unit includes sensing an interruption of contact at a portion of a contact area between the battery cover and the battery cover coupling unit, generating a metadata list including metadata on data to be synchronized from among data cached in a volatile memory, after the sensing of the interruption of contact at the preset portion, sensing an interruption of contact at another portion of the contact area between the battery cover and the battery cover coupling unit after the previous sensing, and storing the metadata of the metadata list in a non-volatile memory, if the interval between the sensing operations is less than or equal to a threshold value.
US09342425B2	Test apparatus and test module In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto.
US09342423B2	Selective restoration of data from non-volatile storage to volatile memory A method of controlling data transfers between a volatile memory and a non-volatile storage, the volatile memory being on a memory device operatively coupled to a computer system, the data transfers comprising: storing data from the volatile memory to the non-volatile storage when a power source of the computer system fails, the method comprising following re-establishment of the previously failed power source, the step of: selectively restoring data from the non-volatile storage to the volatile memory by a controller software after restart operations.
US09342422B2	Selectively coupling a PCI host bridge to multiple PCI communication paths Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) and the selected master PHB are synchronized, and the second PHB is coupled to the PCI communication path between the master PHB and a PCI switch. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices.
US09342420B2	Communication of conditions at a primary storage controller to a host A primary storage controller is maintained in a copy relationship with a secondary storage controller, wherein the primary and secondary storage controllers are coupled to a host that is configurable to use the secondary storage controller instead of the primary storage controller. The primary storage controller determines occurrence of at least one condition in the primary storage controller, wherein the at least one condition occurs prior to a failure of the host to perform an Input/Output (I/O) operation with respect to at least one storage volume of the primary storage controller. The primary storage controller communicates the occurrence of the at least one condition to the host, wherein in response to the communicating the host is configured to determine whether to use the secondary storage controller instead of the primary storage controller based on the occurrence of the at least one condition.
US09342419B2	Persistent messaging mechanism A method comprising using at least one hardware processor for managing persistent messaging data in a volatile memory, writing the persistent messaging data to a first section of a Fast Persistent Memory (FPM), responsive to the first section of the FPM approaching a full state, offloading the persistent messaging data from the first section of the FPM to a hard disk device (HDD), and erasing the persistent messaging data from the first section of the FPM, recording, in a second section of the FPM, an identifier of said offloading, responsive to receiving a request to erase or modify at least some of the persistent messaging data in the HDD, updating the identifier of the offloading in the second section of the FPM while leaving the persistent messaging data in the HDD intact, and responsive to a server failure, selectively reading at least some of the persistent messaging data from the HDD to the volatile memory, wherein the selective reading is based on the identifier of the offloading in the second section of the FPM.
US09342416B2	Processor and method of controlling execution of processes A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section.
US09342412B2	Managing replication of computing nodes for provided computer networks Techniques are described for providing managed computer networks, such as for managed virtual computer networks overlaid on one or more other underlying computer networks. In some situations, the techniques include facilitating replication of a primary computing node that is actively participating in a managed computer network, such as by maintaining one or more other computing nodes in the managed computer network as replicas, and using such replica computing nodes in various manners. For example, a particular managed virtual computer network may span multiple broadcast domains of an underlying computer network, and a particular primary computing node and a corresponding remote replica computing node of the managed virtual computer network may be implemented in distinct broadcast domains of the underlying computer network, with the replica computing node being used to transparently replace the primary computing node in the virtual computer network if the primary computing node becomes unavailable.
US09342407B2	Storage control apparatus and computer-readable recording medium recorded with control program A storage control apparatus includes a detection unit that detects a soft error of a memory for setting information included in a programmable logic circuit, when the soft error is detected, a communication control unit that changes a state of a communication path between the communication device and an upper device to a busy state, and a recovery processing unit that performs recovery processing of the memory for setting information of the programmable logic circuit, thereby efficiently resolving a soft error of the programmable logic circuit.
US09342405B2	Hierarchical data compression testing A hierarchical compression tester and associated method employs a grid-based storage capacity wherein a storage unit is defined by a grouping of data blocks. Each data block is stored in one of a plurality of storage devices. Each stored data block has a data portion and a data integrity field (DIF) including a data reliability qualifier (DRQ) indicating whether the respective data portion is valid. The tester also has a logical device allocation map that includes a storage unit descriptor array that identifies one or more storage units corresponding to a selected logical address. The logical device allocation map has a DIF array that identifies whether any of the data blocks in the one or more storage units corresponding to the selected logical address includes invalid data.
US09342404B2	Decoding method, memory storage device, and memory controlling circuit unit A decoding method, a memory storage device and a memory controlling circuit unit are provided. First, memory cells are read to obtain verification bits. A first hard bit mode decoding procedure is performed according to the verification bits and whether the first hard bit mode decoding procedure generates a first valid codeword is determined by a first correcting circuit. If the first valid codeword is generated, the first valid codeword is outputted. If the first valid codeword is not generated, a second hard bit mode decoding procedure is performed, and whether the second hard bit mode decoding procedure generates a second valid codeword is determined by a second correcting circuit. A precision of the first correcting circuit is less than a precision of the second correcting circuit. Accordingly, the speed of decoding is increased.
US09342402B1	Memory interface with hybrid error detection circuitry for modular designs A programmable integrated circuit with memory interface circuitry is provided. The memory interface circuitry may include soft memory interface logic and hard memory interface logic. The soft memory interface logic may be implemented using programmable circuits, whereas the hard memory interface logic may be implemented using non-programmable dedicated circuits. The soft memory interface logic may include error correction code (ECC) encoder and decoder circuits and circuitry for carrying out a read modified write (RMW) operation. The hard memory interface logic may include a write data buffer, a read data buffer, and other circuitry for supporting the RMW operation. The soft memory interface logic is interposed between the hard memory interface logic and the user logic on the programmable integrated circuit.
US09342399B2	Threshold voltage calibration using reference pattern detection A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.
US09342396B2	Self-stabilizing network nodes in mobile discovery system The disclosure relates to cloud-based mobile discovery networks. For example, a mobile discovery network may include a network responsive to successful watermark detection or fingerprint extraction. One claim recites a cloud-based computing resolver cell in a mobile discovery network, the mobile discovery network comprising a cloud-based traffic router for forwarding requests from remote devices. The resolver cell comprises: memory for storing response information; one or more processors programmed for: monitoring responses to a plurality of status checks issued by the traffic router to said resolver cell, and starting with a first response that includes an error, the monitoring monitors the next n responses from the resolver cell to the traffic router, where n is an integer more than 3, to determine whether: i) a predetermined percentage of the monitored responses included errors; ii) any response included an error within a set time period during said monitoring, and iii) the last response to the traffic router include an error; if any of items i-iii are true, entering a stabilization mode for a predetermined time; and issuing an unavailable status message to the traffic router during the predetermined time. Of course other claims and combinations are provided as well.
US09342395B2	Error checking using serial collection of error data Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.
US09342387B1	Hardware-assisted interthread push communication In a data processing system, a switch of the data processing system receives a request to push a message referenced by an instruction of a sending thread to a receiving thread. In response to receiving the request, the switch determines whether the sending thread is authorized to push the message to the receiving thread by attempting to access an entry of a data structure of the switch utilizing a key derived from at least one identifier of the sending thread. In response to access to the entry being successful, content of the entry is utilized to determine an address of a mailbox of the receiving thread, and the switch pushes the message to the mailbox of the receiving thread. In response to access to the entry not being successful, the switch refrains from pushing the message to the mailbox of the receiving thread.
US09342385B2	Reconfiguring an operator graph based on attribute usage A first processing element may be initially configured to transmit a first output stream to a second processing element. The second processing element may be initially configured to transmit a second output stream to a third processing element. The tuples of the first and second output streams may have the first and second attributes. It may be determined whether the first attribute is to be first processed at the second processing element (first condition) and whether the second attribute is to be first processed at the third processing element (second condition). When the first and second conditions are met, the first processing element may be reconfigured to transmit a third output stream to the second processing element and a fourth output stream to the third processing element. The third output stream may have only the first attribute. The fourth output stream may have only the second attribute.
US09342375B2	Managing workload at a data center Systems and methods of managing workload at a data center are disclosed. An example method may include actively managing workload at a data center to realize energy savings. The method may also include providing excess power generated for the data center onto a utility grid.
US09342373B2	Virtual machine management among networked servers Virtual machine management among networked servers coupled for data communications with a data communications network that includes a network device and a Virtual Machine Management Module (‘VMMM’), where VM management includes: monitoring, by the network device, network traffic of applications executing in virtual machines of the servers; determining, in dependence upon the monitored network traffic, whether a particular application's network traffic exceeds a predetermined threshold, the particular application executing in a particular virtual machine of a particular server; if the particular application's network traffic exceeds the predetermined threshold, allocating, by the VMMM, an additional virtual machine in a different server; and instantiating, by the VMMM, in the additional virtual machine at least one application.
US09342371B2	Boot partitions in memory devices and systems The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.
US09342366B2	Intrusion detection apparatus and method using load balancer responsive to traffic conditions between central processing unit and graphics processing unit An intrusion detection apparatus and method using a load balancer responsive to traffic conditions between a central processing unit (CPU) and a graphics processing unit (GPU) are provided. The intrusion detection apparatus includes a packet acquisition unit, a character string check task allocation unit, a CPU character string check unit, and a GPU character string check unit. The packet acquisition unit receives packets, and stores the packets in a single task queue. The character string check task allocation unit determines the number of packets in the packet acquisition unit, and allocates character string check tasks to the CPU or the GPU. The CPU character string check unit compares the character strings of the packets with a character string defined in at least one detection rule inside the CPU. The GPU character string check unit compares the character strings of the packets with the character string inside the GPU.
US09342364B2	Workflow managed composite applications A portal view generation system can receive a request from a user for a portal view of a portal site. The system determines which resources the user can access based on the user's permission level on the resources. The system further determines the user's authentication level. Each of the portal resources the user has permission to access are then vetted based on a minimum authentication level needed to view the resource, and the user's authentication level. Those resources which the user has permission to access, but in insufficient level of authentication are excluded from view. The portal view generation system then generates the code to render navigational elements for the user to access those remaining resources the user has both permission and sufficient authentication level to access.
US09342362B2	Service-processor-centric computer architecture and method of operation thereof A computer system and a method of operating a service-processor-centric computer system. In one embodiment, the computer system includes: (1) a CPU configured to issue control signals and (2) a service processor configured for intercepting and handling the control signals, the handling including delaying, modifying or ignoring the control signals, the service processor further configuring for issuing highest-priority control signals.
US09342361B2	Method and system for controlling physical actuators in pervasive computing environments For achieving a coordinated and opportunistic actuator control a method for controlling physical actuators in pervasive computing environments is claimed, wherein an entity—actuation space—is provided, the actuation space being configured to manage actuation requests and actuation status information, wherein at least one resource user sends one or more actuation requests to the actuation space that stores the one or more actuation requests, wherein at least one actuator resource controls at least one physical actuator on the basis of one or more of the actuation requests stored in the actuation space, wherein the at least one actuator resource sends actuation status information corresponding to one or more of the actuation requests to the actuation space, and wherein the at least one resource user and the at least one actuator resource share the actuation space. Furthermore, a corresponding system is disclosed.
US09342360B2	Workload migration between virtualization softwares A virtual machine (VM) migration from a source virtual machine monitor (VMM) to a destination VMM on a computer system. Each of the VMMs includes virtualization software, and one or more VMs are executed in each of the VMMs. The virtualization software allocates hardware resources in a form of virtual resources for the concurrent execution of one or more VMs and the virtualization software. A portion of a memory of the hardware resources includes hardware memory segments. A first portion of the memory segments is assigned to a source logical partition and a second portion is assigned to a destination logical partition. The source VMM operates in the source logical partition and the destination VMM operates in the destination logical partition. The first portion of the memory segments is mapped into a source VMM memory, and the second portion of the memory segments is mapped into a destination VMM memory.
US09342355B2	Joint optimization of multiple phases in large data processing Methods and arrangements for task scheduling. A plurality of jobs is received, each job comprising at least a map phase, a copy/shuffle phase and a reduce phase. For each job, there are determined a map phase execution time and a copy/shuffle phase execution time. Each job is classified into at least one group based on at least one of: the determined map phase execution time and the determined copy/shuffle phase execution time. The plurality of jobs are executed via processor sharing, and the executing includes determining a similarity measure between jobs based on current job execution progress. Other variants and embodiments are broadly contemplated herein.
US09342354B2	Systems and methods for providing safe confluence modality A system and method for providing a safe confluence modality in a mobile computing device are provided. The system and method include determining an application switch between a primary application and a secondary application, identifying the application switch as a Non-User Triggered Application (NUTA) switch based on the primary application and the secondary application, the NUTA switch corresponding to the application switch initiated by a non-user of the mobile computing device and capturing a user interaction provided after the NUTA switch.
US09342353B2	Techniques for implementing information services with tenant specific service level agreements A technique for selecting an information service implementation includes receiving a service request that includes a tenant identifier that uniquely identifies a calling tenant. Transformation logic to service the service request is selected based on the received tenant identifier. One or more data sources and one or more data targets are selected for the service request based on the received tenant identifier. Data from the selected data sources is processed using the selected transformation logic and the processed data is stored at the selected data targets.
US09342350B2	System for selecting a task to be executed according to an output from a task control circuit The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.
US09342349B2	Systems and methods for physical and logical resource profiling, analysis and behavioral prediction Methods and/or systems for performing workload analysis within an arrangement of interconnected computing devices, such as a converged infrastructure, are disclosed. A prediction system may generate a workload associated with physical and/or logical components of the converged infrastructure that are utilized to execute a client resource. The prediction system may monitor the utilization behavior of the various logical and/or physical components associated with the workload over a particular period of time to generate a workload profile. Subsequently, the prediction system may execute a prediction workload analysis algorithm that accesses the workload profile to identify optimal physical resources in the converged infrastructure that may be available to execute other workloads.
US09342343B2	Wrapped nested virtualization A number of embodiments can include a Layer 0(L0) VMM configured to provide a first number of services and a Layer 1(L1) virtual machine (VM) that is running on the L0 VMM. A number of embodiments can also include a L1 VMM that is running on the L1 VM. A number of embodiments can include configuring the L1 VMM to provide a second number of services to a target VM, second number of services being different than the first number of services. A number of embodiments can also include configuring the target VM to execute a user application.
US09342342B2	Refreshing memory topology in virtual machine operating systems According to one aspect of the present disclosure a system and technique for refreshing memory topology in virtual machine operating systems is disclosed. The system includes a processor and logic executable by the processor to: responsive to receiving, by an operating system of a virtual machine, a notification of an affinity change relative to workload memory resources, poll a hypervisor for updated memory affinity data; determine, for each logical memory block of the workload memory resources, whether an affinity string for the respective logical memory block has changed; responsive to determining that the affinity string for the respective logical memory block has changed, identify a data structure of the logical memory block maintained by the operating system; and update affinity information in the data structure based on the change to the affinity string of the logical memory block.
US09342339B2	Method and system for congestion management in a fibre channel network One embodiment of the present invention provides a system that facilitates congestion management in a Fibre Channel (FC) network. During operation, the system determines a threshold data rate on an outgoing link coupled to an FC switch. The system further determines the number of sources that send data to the outgoing link and an aggregate arrival rate of data for the outgoing link. Next, the system determines an injection data rate for a respective source based on the threshold data rate on the outgoing link, the number of sources transmitting data to the outgoing link, and the aggregate arrival data rate for the outgoing link. Subsequently, the system communicates the injection data rate to the source, thereby allowing the source to throttle its data injection in the FC network to prevent network congestion.
US09342331B2	Secure virtualized mobile cellular device Secure virtualizing of a mobile cellular device uses a cellular communication network having base transceiver station edge node servers. A virtualized-instance host server contains a virtualized instance of an enterprise environment. Base station controllers are in communication with and control the base transceiver stations. A mobile switching center in communication with the base station controllers contains the virtualized-instance host server. A cellular communication device is in communication with an edge node server, and an auxiliary data display entry device is in communication with the cellular communication device such that the virtualized instance of the enterprise environment is on the edge node server. Communications between the auxiliary display and data entry device are encrypted. In addition, movement of the cellular communication device within the cellular communication network are anticipated so that additional remote virtualized instances of the enterprise environment are provided on candidate future edge servers.
US09342330B2	Deploying a user-configured virtual appliance template including a portion of an existing computing application to enhance functionality Various embodiments provide mechanisms that mitigate organizational exposures when evaluating and choosing computer applications, enhancements, and modifications thereto. Some embodiments provide technological solutions that allow for rapid application prototyping, deployment, evaluation, testing, and the act of going live in a production environment. Some such embodiments provide applications including content and data, in the form of virtual appliance templates, that is pre-installed, pre-configured, pre-tested, and pre-loaded in a very rapid manner. Some embodiments may further allow for cloning of the instantiated application to another virtual computing environment, and utilization from that location on forward looking basis.
US09342329B2	Method and system for cross-operating systems execution of software applications A method for cross-operating systems execution of a legacy software application on a user computing device is provided. The method comprises upon launching a native application on the user computing device, executing, on a server, a cloudified application corresponding to the legacy software application, the legacy software application is compliant with a first operating system, wherein the user computing device is compliant with a second operating system, the first operating system and the second operating system are incompatible with each other; rendering outputs responsive of inputs generated by the native application and received at the cloudified application; streaming the rendered outputs to the user computing device to be displayed by the native application; and performing file system operations requested by at least one of the native application and the cloudified application on at least a cloud storage service.
US09342324B2	System and method for displaying a multimedia container A system and method for displaying a multimedia container. The method includes accessing, within a mobile device, a datastore corresponding to a multimedia container, wherein the multimedia container comprises a plurality of objects and the datastore comprises information about the plurality of objects; determining a plurality of most recently accessed objects of the plurality of objects; determining a respective image corresponding to each of the plurality of most recently used objects; determining an order of each respective image based on a respective access time of a respective object corresponding to the respective image; and displaying a multimedia container image comprising each respective image according to the order, the multimedia container image corresponds to the multimedia container. In one exemplary implementation, a first object of the plurality of objects is a first portion of content and a second object of the plurality of objects is a second portion of content.
US09342322B2	System and method for layering using tile-based renderers A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.
US09342320B2	Method for facilitating cooperative interaction between software applications A computer software system is disclosed for single step coordination between software applications. A monitoring application automatically identifies a target application and presents a prompting window, such that if possible (but not necessarily) it appears to be attached to a side of the target window. Clicking a control in the prompting window automatically activates a secondary application, and automatically transfers information from the target application to the secondary application. Target desktop windows can be identified by their window captions and target HTML windows by their URL addresses. Controls on prompting windows can activate multiple secondary applications and/or different secondary application modes. Information can be obtained from a target application by reading a file stored for that purpose by the target application, by interprocess communication, or by screen scraping. In one general aspect, a medical test result viewing application is coordinated with a medical test result processing application.
US09342308B2	Parsing-enhancement facility An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure.
US09342307B2	Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
US09342306B2	Predicate counter According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.
US09342304B2	Processing vectors using wrapping increment and decrement instructions in the macroscalar architecture Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a fixed-value addition operation dependent upon the input vector and the control vector.
US09342303B2	Modified execution using context sensitive auxiliary code A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code.
US09342301B2	Converting and input script to a natural language description Converting an input script includes obtaining an input script comprising at least one variable, obtaining at least one translation transformation rule from a library, converting the input script into a tree representation, folding the tree representation to hide a subset of variables in the input script to create a folded tree, and generating a natural language text by applying at least one translation transformation rule from the library to the folded tree.
US09342297B2	Systems and methods for providing predictive quality analysis The disclosed embodiments include methods and systems for providing predictive quality analysis. Consistent with disclosed embodiments, a system may receive input data associated with a software program and compare the input data with one or more predetermined analysis parameters. The system may further determine at least one risk rating based on the comparison, wherein each risk rating corresponds to a distinct software category. The system may perform additional operations, including determining at least one adjustment to the software program based on the determined at least one risk rating, and prioritizing the at least one adjustment based on a predetermined adjustment priority standard. Furthermore, the system may provide a report including at least an indication of the at least one prioritized adjustment, a timeline for implementing the at least one prioritized adjustment, and plan implementing the at least one prioritized adjustment.
US09342295B2	Dynamic software updates A method, and a corresponding system, for dynamically updating software while the software is running by automatically dividing a patch into a plurality of micro-updates using compiler analysis. The method includes providing the patch which includes updates to several variable units of the software, including functions, type definitions, and data stores. Next, an interference graph of the patch is generated by creating a node corresponding to each variable unit of the patch and creating connected components by adding edges connecting variable units having an impact expression with a non-zero intersection. The patch is divided into the micro-updates, where each micro-update corresponds to a connected component. The micro-updates are then applied to the software when the variable units of the micro-update are at a safepoint, and at least two of the micro-updates are applied at different times while the software is running.
US09342293B2	Device and method for facilitating secure communications over a cellular network A process for communicating utility-related data over at least one network is described. the process includes: collecting utility-related data at a hub device during a first predetermined period of time; securing the utility-related data at the hub device using digital envelopes during the first predetermined period of time; initiating by the hub device an autonomous wake up process during a second predetermined period of time; sending the secure utility-related data over a first network to a designated server via at least one User Datagram protocol (“UDP”) message during the second predetermined period of time; and receiving an acknowledgement of receipt message of the at least one UDP message from the designated server; wherein the first and second predetermined periods of time typically do not overlap, but may overlap.
US09342292B2	Customer relationship management system and method A software-based customer relationship management system and method.
US09342291B1	Distributed update service Systems and methods are disclosed that facilitate the updating of target computing devices based on versioning information. The updates to the target computing devices can utilize a series of external client workflow integration points, or integration points. The integration points allow the client computing device to interact with the computing device management component and dictate the workflow process associated with the implementation of the update procedure on the target computing device. The integration points can also be used by the client to perform additional processes specific to the client's policy-based protocols.
US09342289B2	Service node, network, and method for pre-fetching for remote program installation A system for package pre-fetching for a remote program installation includes a service node having a processor, a computing node type database, and a cache, the service node being configured to receive at least one package request for a package required for an installation of an operating system and at least one peripheral application thereof from a computing node, and determine a package request sequence by which the computing node issues the at least one package request according to a type of the computing node. In another embodiment, a method includes receiving a package request from a computing node, and determining a package request sequence by which the computing node issues at least one package request according to a type of the computing node, so as to pre-read a subsequent package into a cache before the computing node issues a request for the subsequent package.
US09342288B2	Surfacing cross platform applications A utility application store may be configured to present an interface displaying multiple applications that are available from the utility application store. By accessing the interface of the utility application store, a utility supplier may, with a single request, initiate installation or activation of an application on multiple utility meters or other smart sensors in a utility communication network. The utility application store may be configured to provide notification of the availability of applications for utility meters or other smart sensors, consumer computing devices, and/or utility supplier back office computing devices. The utility application store may include one or more distributed applications that include a first portion configured for execution by a utility meter and one or more other portions configured for execution by another computing device (e.g., a personal computer, mobile device, utility supplier back office server, cloud service, or the like).
US09342287B2	Software program ratings Improved approaches for rating a software program are disclosed. The rating can be automatically determined from a plurality of user characterizations. The user characterizations can be designated by a user (e.g., developer or publisher) with respect to a plurality of content descriptors. The user characterizations can be supplied by the user on submitting a software program to an online distribution system. Once a rating is determined and associated with a software program, the rating can be used to influence availability of the software program from an online distribution system. The rating (or how the rating influences availability) can be dependent on geographical region. The rating being determined can also be influenced by rating rules.
US09342284B2	Optimization of instructions to reduce memory access violations Mechanisms for reducing memory access violations are disclosed. Sets of instructions may be identified and the identified sets of instructions may be re-translated or optimized to generate other sets of instructions. Execution of the other sets of instructions is analyzed to determine whether additional memory access violations occur. When additional memory access violations occur, further sets of instructions may be generated or re-translation/optimization of instructions may be disabled.
US09342277B2	Method of searching data associated with nodes of a graphical program A method and apparatus for searching data associated with nodes of a visual or graphical program. The method may include the acts of searching information stored in memory using search criteria that was entered into a search box of a Graphical User Interface. The information searched is associated with nodes of the graphical program. In response to the searching, identifying one or more of the nodes. In one embodiment, the method may further include displaying one or more links corresponding to the identified one or more of the nodes, respectively, in response to the identifying.
US09342276B1	Optimization tracing A modeling environment is provided allowing a user to generate, from a source representation of a model, a target representation of a model and a listing of the optimization performed during generation of the target representation which is associated with the target representation or the source representation. The model may represent a system, such as a dynamic system. The source representation of the model may be a graphical or textual representation. In some embodiments a user may specify whether to implement the optimization.
US09342269B2	Quantum interference unit, quantum interference device, atomic oscillator, electronic apparatus, and moving object An atomic oscillator includes: a gas cell which houses metal atoms; a heater which adjusts a temperature of the gas cell; and a package which houses the gas cell and the heater. The package includes a non-magnetic metal layer.
US09342268B2	Multi-level voice menu Methods, apparatus, and computer-readable media are described herein related to a user interface (UI) that can be implemented on a head-mountable device (HMD). The UI can include a voice-navigable UI. The voice-navigable UI can include a voice navigable menu that includes one or more menu items. The voice-navigable UI can also present a first visible menu that includes at least a portion of the voice navigable menu. In response to a first utterance comprising one of the one or more menu items, the voice-navigable UI can modify the first visible menu to display one or more commands associated with the first menu item. In response to a second utterance comprising a first command, the voice-navigable UI can invoke the first command. In some embodiments, the voice-navigable UI can display a second visible menu, where the first command can be displayed above other menu items in the second visible menu.
US09342256B2	Epoch based storage management for a storage device Techniques are disclosed relating to handling snapshot data for a storage device. In one embodiment, a computing system maintains information that indicates the state of data associated with an application at a particular point in time. In this embodiment, the computing system assigns an epoch number to a current epoch, where the current epoch is an interval between the particular point in time and a future point in time. In this embodiment, the computing system writes, during the current epoch, a block of data to the storage device. In this embodiment, the writing the block of data includes storing the epoch number with the block of data.
US09342255B2	Transfer size monitor, determination, and optimization engine for storage devices A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters.
US09342254B2	Sector-based write filtering with selective file and registry exclusions A method includes mounting a persistent volume of a data storage device of an electronic device. The persistent volume is based on a protected volume stored at the data storage device. The method also includes accessing the persistent volume to enable servicing access to the data storage device of the electronic device.
US09342250B1	Dynamic distribution of replicated data A system and method for data storage. The method can include: identifying, by a computer processor, a cluster map representing a set of storage resources; for each storage resource of the set of storage resources: traversing, by the computer processor, the cluster map to map the storage resource to a candidate resource set including at least one other storage resource of the set of storage resources; identifying a first data object associated with a storage request; identifying a first candidate resource set based on the first data object; and selecting a first final resource set based at least on the first candidate resource set, where the first data object is sent to storage resources of the first final resource set for storage.
US09342249B2	Controlling partner partitions in a clustered storage system A rack-power control module (RPC) module is used for allowing a local storage partition, located on a local server, for controlling a destination storage partition, located on a destination server, by piggybacking commands on power alerts issued by the RPC module in a clustered storage system.
US09342248B2	Techniques for reducing read I/O latency in virtual machines A computer implemented method for reducing the latency of an anticipated read of disk blocks from a swap file in a virtualized environment. The environment includes a host swap file maintained by a host operating system and a guest swap file maintained but a guest operating system. First, the method identifies a sequence of disk blocks that was written in the guest swap file. The method then detects within the sequence of blocks a first disk block that contains a reference to a second disk block that is stored in the host swap file. The method then replaces the first disk block in the guest swap file with the second disk block.
US09342245B2	Method and system for allocating a resource of a storage device to a storage optimization operation Allocating a resource of a storage device to a storage optimization operation. An available resource of the storage device is monitored. Determining an allocation proportion of the resource allocated to the storage optimization operation, based on at least one of historical running information and a predicted value of a performance improvement caused by the storage optimization operation. Allocating the resource of the storage device to the storage optimization operation based on the available resource and the allocation proportion.
US09342243B2	Method and electronic apparatus for implementing multi-operating system A method for implementing multi-operating system, applied to an electronic apparatus in which a Solid State Disk, SSD, is provided, the SSD including a plurality of partitions each of which corresponding to a unique logical snapshot table, and a plurality of operating systems being installed in different partitions respectively, wherein the method includes: determining a logical snapshot table corresponding to an operating system to be loaded currently as a first logical snapshot table during a Power On Self Test process of a basic input/output system; and determining a position of a partition in the SSD which corresponds to a reading/writing operation based on the first logical snapshot table if the reading/writing operation is performed on the SSD in a manner of Logical Block Addressing.

1 2 3 4 5 6 7 8 9 10