最新美国发明专利第2016-03-15期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09287710B2	Supplying grid ancillary services using controllable loads A method includes determining a desired power draw for a plurality of loads connected to an electrical grid, each of the plurality of loads connected to the electrical grid through a load supply control and being able to obtain a desired amount of energy from the grid in a desired time period, and transmitting a plurality of instructions through a communication network to a plurality of load supply controls to cause at least some of the loads in the plurality of loads to receive power from the electrical grid at different rates than other loads of the plurality of loads such that the desired power draw is obtained and such that each load of the plurality of loads receives its corresponding desired amount of energy in the desired time period.
US09287708B2	Actuator and energy management system comprising such actuators An actuator for the power control of at least one connected load has a load detection device for detecting a magnitude of a load and/or a type of a load of the at least one as a measurement variable relating to the load of the at least one consumer. A communication interface receives at least one manipulated variable for the power control of the at least one consumer and transmits the measurement variable detected by the load detection device. Actuators of this type may be integrated into an energy management system, such as of a building automation system, for example.
US09287702B2	Universal power interface An electronic device is provided that may include an input port to couple to an external device, and a universal power interface to determine a type of the external device connected to the input port based at least on a voltage of a voltage supply line. The universal power interface may provide a power delivery path based on the determined type of the external device.
US09287699B2	Bypass control structure of link unit of chain circuit active power filter and method The present application relates to a bypass control structure of a link unit of a chain circuit active power filter and a control method thereof. The bypass control structure includes a main controller, a chain circuit multilevel inverter and a reactor connected to an external electric network. The chain circuit multilevel inverter generally comprises multiple levels of link units. A state of the switch means in each link unit in a chain circuit active power filer is detected in real time, and types of detected faults are classified so as to bypass the fault of the link unit with fault by utilizing the control of the switch means without fault in the link unit with fault. Normal operating, stability, reliability, high efficiency of the active power filter are ensured. Therefore, the problem that the operation must be suspended until the fault is eliminated is solved without any additional bypass means.
US09287698B2	Power conversion apparatus A controller for switching an inverter includes a current detecting unit, an overcurrent level determining unit which determines an overcurrent level for stopping the inverter in accordance with a value corresponding to the number of revolutions of a motor, a current comparing unit which compares a detected output current value of the inverter with the overcurrent level, and a gate signal generating unit which generates a signal for turning off all semiconductor switching devices of the inverter when the current comparing unit makes a determination that the detected output current value has reached the overcurrent level. The overcurrent level is lowered as the number of revolutions of the motor increases.
US09287694B2	Line guiding system The invention relates to a line guiding system (1) for accommodating and guiding supply lines between two connection points (2.1, 2.2) that can be moved relative to one another in a circular motion with respect to a rotational axis (d) over a rotational angle range, wherein the line guiding system (1) has an elongated strand (3.1, 3.2, 3.3) coupled to the connection points (2.1, 2.2), on or in which strand the supply lines can be arranged in a guided manner, and the strand (3.1, 3.2, 3.3) can be moved back and forth within the rotational angle range while guided over a circular arc, such as to form a first run (4.1), a second run (4.2), and a deflecting bend (5) that connects the first run (4.1) and the second run (4.2). In order to enable guidance of the supply lines over an increased rotational angle range, at least two strands, a first strand (3.1) and a second strand (3.2), are provided, which are arranged such as to be coupled one behind the other.
US09287687B2	Electrical low-voltage switchgear assembly The invention relates to an electrical low-voltage switchgear, comprising at least two power units accommodated in slide-in units or in a housing, and comprising control units assigned to the power units. The control units are spatially separated from the power units and power levers and are connected to one another via signal lines.
US09287685B2	Spark plug for internal combustion engine A spark plug for an internal combustion engine has a housing, an insulator, a center electrode, a ground electrode, and a tip projecting portion. The tip projecting portion has an air guiding surface. In the spark plug, when viewed from a plug axial direction, a straight line that connects the center, in the plug circumferential direction, of the erect portion of the ground electrode and a center point of the center electrode is a straight line. An extension line of the air guiding surface is a straight line. A distance between an intersection, between the straight line and the straight line, and the center point of the center electrode is a (positive towards the side moving away from the erect portion. An angle formed by the straight line and the straight line is b. A diameter of the housing is D. At this time, all of b≧−67.8×(a/D)+27.4, b≦−123.7×(a/D)+64.5, −0.4≦(a/D)≦0.4, and 0°
US09287683B2	Semiconductor interband lasers and method of forming A semiconductor interband laser that includes a first cladding layer formed using a first high-doped semiconductor material having a first refractive index/permittivity and a second cladding layer formed using a second high-doped semiconductor material having a second refractive index/permittivity. The laser also includes a waveguide core having a waveguide core refractive index/permittivity, the waveguide core is positioned between the first and the second cladding layers. The waveguide core including an active region adapted to generate light based on interband transitions. The light being generated defines the lasing wavelength or the lasing frequency. The first refractive index and the second refractive index are lower than the waveguide core refractive index. The first cladding layer and/or the second cladding layers can also be formed using a metal.
US09287673B2	Insulation piercing connectors and methods and connections including same An electrical connector for mechanically and electrically connecting first and second cables, each including an elongate electrical conductor covered by an insulation layer, includes a connector body, an electrically conductive first insulation piercing feature on the connector body, an electrically conductive second insulation piercing feature on the connector body and electrically connected to the first insulation piercing feature, and a compression mechanism. The first insulation piercing feature is configured to pierce through the first insulation layer and electrically engage the first electrical conductor. The second insulation piercing feature is configured to pierce through the second insulation layer and electrically engage the second electrical conductor. The compression mechanism is configured and operable to apply a clamping load along a clamping axis extending through both of the first and second electrical conductors to force the first and second insulation piercing features into electrical engagement with the first and second electrical conductors, respectively.
US09287667B2	Shield shell and shield connector The present invention concerns a shield shell (70) to be connected to a case made of metal and including a shell main body (71) with a case connecting portion (74) to be connected to the case, a single collective shield connecting portion (72) provided on the shell main body (71) and formed into an elliptical tubular shape, and a plurality of individual-core shield connecting portions (77) provided on the shell main body (71) and formed into a cylindrical shape. The present invention may also concern a shield connector (10) including the shield shell (70), a housing (40) to be held onto the shield shell (70), wires with terminal fittings (20) inserted through the interior of the housing (40), and a single braided wire (90) connected to the single collective shield connecting portion (72) of the shield shell (70).
US09287661B2	Clip and latch substitution device for modular plugs A clip and latch device including: a mount including a securing base defining a plane, a rear end and a front end, a clip base mounted at the rear end of the securing base, a clip having a normally downward angle from the clip base towards the front end of the securing base, and a latch which terminates at the clip and normally extending so that the latch reaches to at least the plane of the securing base. The clip and latch device can be used for modular male plug, for example a male RJ plug, which may be with or without a broken tab or latch.
US09287659B2	Coaxial cable connector with integral RFI protection A coaxial cable connector for coupling an end of a coaxial cable to a terminal is disclosed. The connector has a coupler adapted to couple the connector to a terminal, a body assembled with the coupler and a post assembled with the coupler and the body. The post is adapted to receive an end of a coaxial cable. The post has an integral contacting portion that is monolithic with at least a portion of the post. When assembled the coupler and post provide at least one circuitous path resulting in RF shielding such that RF signals external to the coaxial cable connector are attenuated, such that the integrity of an electrical signal transmitted through coaxial cable connector is maintained regardless of the tightness of the coupling of the connector to the terminal.
US09287657B2	Headset connector Headset assemblies and headset connectors are provided. Headset connectors can include a magnetic mating face and a plurality of electrical contacts disposed within the mating face. Engaging assemblies and engaging connectors are also provided. The engaging connectors can include a housing having a mating side, a magnetic array structure, and a plurality of spring biased contact members. The magnetic array structure can be fixed within the housing and house a plurality of spring biased contact members. The spring biased contact members can include tips that extend out of the mating side. The tips can electrically couple with electrical contacts in a headset connector.
US09287655B2	Crimped terminal attached aluminum electric wire A crimped terminal attached aluminum electric wire includes an aluminum electric wire that includes a conductor part made of aluminum or aluminum alloy and an insulative coating part which surrounds the periphery of the conductor part, and a crimped terminal that is crimped to the conductor part which is exposed by removing the insulative coating part at an end of the aluminum electric wire. The crimped terminal includes a conductor crimping part which is crimped to the exposed conductor part, and an end side conductor crimping part which is formed at an end at the side of the crimped terminal to which the aluminum electric wire is connected, and which is crimped to the conductor part at a radial compression rate which is smaller than that at which the conductor part is crimped by the conductor crimping part.
US09287652B2	Cover-fitted connector A cover-fitted connector includes a connector housing that houses a terminal connected to a terminal of an electric wire, and a cover that covers the electric wire pulled out from the connector housing. The connector housing includes a connector housing body, and a connecting portion connected to the connector housing body. The cover includes a cover body, a connected portion connected with the connecting portion at a time of mating the cover with the connector housing, and a cutout portion having an end portion positioned at a boundary between the connector housing body to cover the connecting portion and configured to expose the connector housing body outside the cover at the time of mating the cover with the connector housing.
US09287650B2	Connector and mating connector An electrical connector is configured to be electrically coupled to a mating connector. The connector includes a housing having a contact chamber and a connector face. The connector further includes a contact connector element accommodated in the contact chamber. The contact connector element includes a primary locking member configured to latch with the contact chamber. The connector also includes a secondary locking member assembled to the housing via the connector face. The secondary locking member is configured to interlock the contact connector element in the housing.
US09287649B2	Connector and housing A connector (10) includes terminals (40) each of which has a plate-like connecting portion (42) formed with a nut mounting hole (43). A housing (20) is formed with terminal accommodating portions (21) capable of accommodating the terminals (40). Nuts (44) with bolt holes (45) are mounted integrally on the connecting portion (42) so that each bolt hole (45) coaxially communicates with the nut mounting hole (43). Locking lances (29) are formed in the housing (20) and retain the connecting portions (42) by locking outer parts of the nuts (44) from behind. Front stops (23) are formed in the terminal accommodating portion (21) and stop the connecting portion (42) at a front end position by locking projections (47) formed on the terminal (40) to project from the terminal (40) from front.
US09287648B2	Contact element, in particular a solder tab and photovoltaic junction box with contact element, in particular a solder tab A contact element (1) for providing an electrical contact between a first electrical device (7) and a second electrical device, wherein the contact element (1) comprises a first contact portion (2) to be electrically connected to the first electrical device (7) and a second contact portion (4) to be connected to the second electrical device. The first contact portion (2) is arranged at a distance (D) to the second contact portion (4), whereby the contact element (1) comprises further an adjustment portion (3) connecting said first and second contact portion (2, 4), wherein with said adjustment portion (3) said distance (D) between the first contact portion (2) and the second contact portion (4) is adjustable.
US09287647B2	Electrical zero-force plug connector An electrical zero-force plug connector includes a socket housing holding sleeve contacts movable between opened and closed positions and an assembly connector having connector pins. A bolt is movable against the socket housing from an unlocked position into a locked position after the socket housing and the assembly connector are joined. A slider is connected to the bolt and the sleeve contacts such that as the bolt moves the slider moves through a seal of the socket housing and moves the sleeve contacts. While the socket housing and the assembly connector are joined and the bolt is unlocked, the sleeve contacts are opened and the connector pins are inserted into the sleeve contacts. While the socket housing and the assembly connector are joined and the bolt is locked, the sleeve contacts are closed and the connector pins inserted into the sleeve contacts are held therein.
US09287646B2	Actively cooled electrical connection A method and electrical connection for providing electrical power is disclosed. The electrical connection comprises an electrical connector connected to an electrical conductor assembly. A current greater than a rated current capacity of at least one of the electrical connector and electrical conductor assembly may be passed through the electrical conductor assembly and electrical connector. The electrical connector and electrical conductor may be actively cooled with a flow of heat transfer medium flowing substantially along a length of the electrical conductor assembly and through the electrical connector to increase the current capacity of the electrical connection.
US09287637B2	Split bolt electrical connector assembly An electrical connector includes a split bolt having a base and first and second outwardly extending legs. A conductor receiving channel is formed between the legs. A nut threadably engages the legs and has upper and lower surfaces and an opening through it. A pressure bar member is movably received in the conductor receiving channel. A head of the pressure bar member contacts the lower surface of the nut and a body of the pressure bar member extends through the opening in the nut. A spacer is disposed in the conductor receiving channel between the base and the head of the pressure bar member.
US09287630B2	Dual-band folded meta-inspired antenna with user equipment embedded wideband characteristics Embodiments of a folded meta-inspired antenna for dual-band operation and user equipment for dual-band operation in a wireless network are generally described herein. In some embodiments, the folded meta-inspired antenna may include first and second conductive layers disposed on opposite sides of a substrate to provide a wideband distributed structure comprising a plurality of high-Q resonances resulting from, at least in part, metamaterial-based loading. Conductive material on the first side of the substrate is arranged around a central longitudinal slot coupled with a plurality of perpendicular slots. For dual-band operation, the folded meta-inspired antenna may operate as a folded monopole at a higher frequency band and operate as a slot-type radiator at a lower frequency band. The plurality of resonances may cause the folded meta-inspired antenna to achieve broader bandwidth at both lower and higher frequency bands.
US09287628B2	Circular polarized antenna structure Disclosed is a circular polarized antenna structure, comprising a main body, a protruding portion and a stopping portion, the stopping portion being formed between the main body and the protruding portion. The circular polarized antenna may be disposed to penetrate through the upper and lower surfaces of a base that has a radiation conductor and a grounding conductor disposed thereon respectively, the stopping portion abutting against the lower surface of the base to prevent the main body from coming loose and being detached from the base even if the protruding portion is subjected to a great impact or squeezing pressure caused by an external force coming from the lower surface upwards.
US09287627B2	Customizable antenna feed structure Custom antenna structures may be used to compensate for manufacturing variations in electronic device antennas. An antenna may have an antenna feed and conductive structures such as portions of a peripheral conductive electronic device housing member. The custom antenna structures compensate for manufacturing variations that could potentially lead to undesired variations in antenna performance. The custom antenna structures may make customized alterations to antenna feed structures or conductive paths within an antenna. An antenna may be formed from a conductive housing member that surrounds an electronic device. The custom antenna structures may be formed from a printed circuit board with a customizable trace. The customizable trace may have a contact pad portion on the printed circuit board. The customizable trace may be customized to connect the pad to a desired one of a plurality of contacts associated with the conductive housing member to form a customized antenna feed terminal.
US09287623B2	Antenna for reception of circularly polarized satellite radio signals An antenna for receiving circularly polarized satellite radio signals has a conductive base surface and at least one a conductor loop oriented horizontally above the base surface by a height h. The conductor loop is configured as a polygonal or circular closed ring line radiator. The ring line radiator forms a resonant structure that is electrically excited so that the current distribution of a running line wave in a single rotation direction occurs on the ring line, wherein the phase difference of which, over one revolution, amounts to essentially 2π. A vertical radiator extends between the conductive base surface and the circumference of the ring line radiator. The height h is smaller than ⅕ of the free-space wavelength λ.
US09287621B2	Multi-band antenna An antenna which operates in a plurality of frequency bands includes a feeding point, a first conductor which is connected to the feeding point, and at least two second conductors which are branched from the first conductor, have a linear shape, and include open ends as ends on a side opposite to the first conductor. The open ends of the two second conductors face in almost the same direction substantially parallel to a side closest to the feeding point out of the sides of an antenna region. The two second conductors include a part at which the distance between the two conductors at a portion parallel to the side is a first distance, and another part at which the distance is a second distance shorter than the first distance, and are electromagnetically coupled at, at least the other part.
US09287614B2	Micromachined millimeter-wave frequency scanning array A frequency scanning traveling wave antenna array is presented for Y-band application. This antenna is a fast wave leaky structure based on rectangular waveguides in which slots cut on the broad wall of the waveguide serve as radiating elements. A series of aperture-coupled patch arrays are fed by these slots. This antenna offers 2° and 30° beam widths in azimuth and elevation direction, respectively, and is capable of ±25° beam scanning with frequency around the broadside direction. The waveguide can be fed through a membrane-supported cavity-backed CPW which is the output of a frequency multiplier providing 230˜245 GHz FMCW signal. This structure can be planar and compatible with micromachining application and can be fabricated using DRIE of silicon.
US09287604B1	Frequency-scalable transition for dissimilar media A frequency-scalable device for interfacing a planar medium with a coaxial medium to propagate a primary signal, the device comprises a transition medium connectable between the coaxial medium and the planar medium. The transition medium suppresses excitation of secondary electrical signals by the primary signal when the primary signal is propagated through the transition medium at a frequency below an upper limit.
US09287599B1	Miniature tunable filter Described is a miniature tunable filter, comprising at least two adjacent coaxial-type resonators coupled to one another. Each coaxial-type resonator comprises a metal-coated ceramic dielectric cavity having a tuning rod passage formed therethrough. A tuning rod is inserted through the tuning rod passage, such that the miniature tunable filter is tuned by moving the tuning rod into and out of the tuning rod passage of the ceramic dielectric cavity. A low impedance coaxial section surrounds at least a portion of the tuning rod to create an effective microwave short-circuit at a resonant frequency of the miniature tunable filter, which results in very wide tuning and low insertion loss. In a desired aspect, the tuning rod is a solid metal tuning rod. The combination of a solid metal tuning rod with a ceramic coaxial-type resonator results in high radio frequency power handling.
US09287598B2	RF window assembly comprising a ceramic disk disposed within a cylindrical waveguide which is connected to rectangular waveguides through elliptical joints A high-power microwave RF window is provided that includes a cylindrical waveguide, where the cylindrical waveguide includes a ceramic disk concentrically housed in a central region of the cylindrical waveguide, a first rectangular waveguide, where the first rectangular waveguide is connected by a first elliptical joint to a proximal end of the cylindrical waveguide, and a second rectangular waveguide, where the second rectangular waveguide is connected by a second elliptical joint to a distal end of the cylindrical waveguide.
US09287591B2	Battery pack with protective circuit board and electric bicycle including the battery pack To provide a battery pack that is less likely to be affected by vibrations, shocks and the like and has a stable characteristic, and an electric bicycle that uses the battery pack.A battery pack includes: a battery protective member having a first plate section and a second plate section which is integrally connected to both edge portions of a width direction of the first plate section and extends substantially in a direction perpendicular to both surfaces of the first plate section, wherein the flat batteries are placed on the first plate section; and a protective circuit board. A moistureproof film for the protective circuit board is formed using a plurality of film forming materials different in viscosity, hardness, and thixotropic properties.
US09287582B2	Composition for forming solid electrolyte layer, method for forming solid electrolyte layer, solid electrolyte layer, and lithium ion secondary battery A composition for forming a solid electrolyte layer for use in the formation of a solid electrolyte layer of a lithium ion secondary battery contains first particles made of a lanthanum titanate and second particles made of a lithium titanate. It is preferable that the first particles have an average particle size of 50 nm or more and 300 nm or less. It is preferable that the second particles have an average particle size of 10 nm or more and 50 nm or less.
US09287578B2	Polyoxometalate flow battery Flow batteries including an electrolyte of a polyoxometalate material are disclosed herein. In a general embodiment, the flow battery includes an electrochemical cell including an anode portion, a cathode portion and a separator disposed between the anode portion and the cathode portion. Each of the anode portion and the cathode portion comprises a polyoxometalate material. The flow battery further includes an anode electrode disposed in the anode portion and a cathode electrode disposed in the cathode portion.
US09287570B2	Planar configuration air breathing polymer electrolyte electrical device including support plate and bearing plate The present invention relates to a fuel cell device for use in planar configuration air breathing polymer electrolyte electrochemical devices and to a support plate, gas connection means and clamping means for use in the fuel cell device. The electrochemical device may be use as a fuel cell or an electrolyzer. In particular it relates to a planar configuration air breathing polymer electrolyte electrochemical device including at least two fuel cells arranged in series connection on one surface of a support plate, characterized in that the fuel cells (2′, 2″, 2′″; 943) are arranged to press against a bearing plate (218; 942), which has an area that is larger than the area of the support plate.
US09287569B2	Method of enhancing electrodes One embodiment includes a method of forming a hydrophilic particle containing electrode including providing a catalyst; providing hydrophilic particles suspended in a liquid to form a liquid suspension; contacting said catalyst with said liquid suspension; and, drying said liquid suspension contacting said catalyst to leave said hydrophilic particles attached to said catalyst.
US09287568B2	High performance, high durability non-precious metal fuel cell catalysts This invention relates to non-precious metal fuel cell cathode catalysts, fuel cells that contain these catalysts, and methods of making the same. The fuel cell cathode catalysts are highly nitrogenated carbon materials that can contain a transition metal. The highly nitrogenated carbon materials can be supported on a nanoparticle substrate.
US09287566B1	Anti-curl copper foil The present disclosure relates to an improved coated copper foil that exhibits anti-curl and anti-wrinkle properties; and to methods for manufacturing the foil. Typically, the copper foil of the instant disclosure has: (a) a shiny side; (b) a matte side, wherein the matte side has an MD gloss in the range of 330 to 620; (c) a difference in surface roughness (Rz) between the shiny side and the matte side in the range of 0.3 to 0.59 μm; and (d) a difference in tensile strength in the transverse direction of 1.2 kgf/mm2 or less.
US09287563B2	Electrode for lithium secondary battery and lithium secondary battery including the same An electrode for a lithium secondary battery includes an electrode active material, a conductive agent, and a polyurethane-based compound, and has pores having an average diameter of about 2 to about 20 nm. A lithium secondary battery includes the electrode.
US09287562B2	Negative electrode active material comprising spinel lithium titanate, electrical storage device, and method for producing negative electrode active material A negative-electrode active material disclosed herein contains a lithium titanate having a spinel structure, and satisfies the relationship B×P<50, where B is a specific surface (unit: m2/g) of the lithium titanate as measured by a BET technique; and P is obtained by immersing 1 g of the lithium titanate in 50 cm3 of redistilled water and determining a pH of the redistilled water after 30 minutes of agitation.
US09287554B2	Positive electrode active material The present invention provides a positive electrode active material. The positive electrode active material is represented by the following formula (I) and has a BET specific surface area of larger than 5 m2/g and not larger than 15 m2/g: LixM1yM31-yO2 (I) wherein M1 is at least one transition metal element selected from Group 5 elements and Group 6 elements of the Periodic Table, M3 is at least one transition metal element other than M1 and selected from among transition metal elements excluding Fe, x is not less than 0.9 and not more than 1.3, and y is more than 0 and less than 1.
US09287551B2	Method for manufacturing a battery terminal plate The present invention relates to an apparatus and method for manufacturing a battery terminal plate, and more particularly relates to an apparatus and method for manufacturing a battery terminal plate, in which a terminal plate for a secondary battery, such as a middle or large sized Lithium ion battery, which is applied to electric vehicles, hybrid vehicles, plug-in hybrid vehicles, solar cells, electric tools and so on, is processed by not pressing but forging, a shifting and supplying apparatus for shifting a material to be processed in each forming and processing step may be moved by the shortest distance through a shift-return method (one step shift-return), the material is previously processed by punching so as not to satisfy a standard of a design, and the firstly processed material is secondly processed to satisfy the standard.
US09287541B2	Single fiber layer structure of micron or nano fibers and multi-layer structure of micron and nano fibers applied in separator for battery A single fiber layer structure of micron or nano fibers, and a multi-layer structure of micron and nano fibers are provided. The single fiber layer structure of micron fibers comprises a web of micron fibers and an impregnating resin, and has a pore size of 1 nm-500 nm. The web of micron fibers is formed by plural interweaved micron fibers (D≧1 μm). The single fiber layer structure of nano fibers comprises a web of nano fibers formed by plural interweaved nano fibers (D<1 μm). The multi-layer structure of micron and nano fibers comprises a web of interweaved micron fibers, a web of nano fibers formed by plural nano fibers interweaved on the web of micron fibers, a mixture layer formed by parts of the interweaved nano and micron fibers, and a resin at least impregnating the mixture layer and parts of the micron fibers of the web of micron fibers.
US09287540B2	Separators for a lithium ion battery A separator for use in a lithium ion battery to provide a physical and electrically insulative mechanical barrier between confronting inner face surfaces of a negative electrode and a positive electrode may be formed predominantly of heat-resistant particles. The heat-resistant particles, which have diameters that range from about 0.01 μm to about 10 μm, are held together as a thin-layered, handleable, and unified mass by a porous inert polymer material. The high content of heat-resistant particles amassed between the confronting inner face surfaces of the negative and positive electrodes provides the separator with robust thermal stability at elevated temperatures. Methods for making these types of separators by a phase-separation process are also disclosed.
US09287534B2	Rechargeable battery A rechargeable battery includes an electrode assembly including first electrodes and second electrodes, a casing including a space in which the electrode assembly is embedded, a cap plate combined with the casing, and a first thin film insulating member fused with the casing and surrounding the casing.
US09287533B2	Non-aqueous secondary battery, mounted unit, and method for manufacturing non-aqueous secondary battery A non-aqueous secondary battery includes: a positive-electrode collector layer; a positive-electrode layer formed on one surface of the positive-electrode collector layer; a negative-electrode collector layer; a negative-electrode layer formed on one surface of the negative-electrode collector layer so as to be opposed to the positive-electrode layer; a separator provided between the positive-electrode layer and the negative-electrode layer; and a positive-electrode-side insulating layer and a negative-electrode-side insulating layer respectively formed on another surface of the positive-electrode collector layer and another surface of the negative-electrode collector layer. Circumferential inner surfaces of peripheral edges of the positive-electrode collector layer and the negative-electrode collector layer are joined with a sealing agent including at least a positive-electrode fusion layer, a gas barrier layer, and a negative-electrode fusion layer. The positive-electrode-side insulating layer and/or the negative-electrode-side insulating layer has a battery-side recess provided on a surface.
US09287531B2	Organic light-emitting display device and method of manufacturing the same A method of manufacturing an organic light-emitting display device is provided. A plurality of anodes and an auxiliary electrode are formed on a substrate. The auxiliary electrode is separated from the plurality of the anodes. An organic layer is formed on the plurality of the anodes and the auxiliary electrode. An opening is formed in the organic layer by applying a voltage to the auxiliary electrode. The opening exposes the auxiliary electrode. A cathode is formed on the organic layer and the exposed auxiliary electrode. The cathode is electrically connected to the exposed auxiliary electrode.
US09287529B2	Method for fabricating OLED using roll to roll processing A method for fabricating the OLED including a color conversion layer using roll-to-roll processing is provided. To elaborate, the method for fabricating an OLED comprising: bonding an OLED and an inorganic phosphor to each other through roll-to-roll processing is provided, wherein the inorganic phosphor is provided as a color conversion layer.
US09287522B2	Local seal for encapsulation of electro-optical element on a flexible substrate An electroluminescent display or lighting product incorporates a panel including a collection of distinct light-emitting elements formed on a substrate. A plurality of distinct local seals are formed over respective individual light-emitting elements or groups of light-emitting elements. Each local seal is formed by depositing a low melting temperature glass powder suspension or paste using inkjet technology, and fusing the glass powder using a scanning laser beam having a tailored beam profile. The local seal may be used in conjunction with a continuous thin film encapsulation structure. Optical functions can be provided by each local seal, including refraction, filtering, color shifting, and scattering.
US09287521B2	Transparent electrode, method for manufacturing transparent electrode, electronic device, and organic electroluminescence element A transparent electrode is provided with a nitrogen-containing layer, an electrode layer having silver as the main component thereof, and an aluminum intermediate layer, wherein the aluminum intermediate layer is in contact with the nitrogen-containing layer and the electrode layer and sandwiched between the nitrogen-containing layer and the electrode layer. The nitrogen-containing layer is formed by using a compound containing a nitrogen atom. The effective unshared electron pair content [n/M] of this compound satisfies “3.9×10−3≦[n/M]”, where n is the number of unshared electron pair(s) not involved in aromaticity and not coordinated to metal, among unshared electron pair(s) owned by the nitrogen atom, and M is molecular weight.
US09287519B2	Optoelectronic device and method for producing an optoelectronic device An optoelectronic device, comprising: a first organic functional layer structure; a second organic functional layer structure; and a charge generating layer structure between the first organic functional layer structure and the second organic functional layer structure, wherein the charge generating layer structure comprises: a first electron-conducting charge generating layer; wherein the first electron-conducting charge generating layer comprises or is formed from an intrinsically electron-conducting substance; a second electron-conducting charge generating layer; and an interlayer between first electron-conducting charge generating layer; and second electron-conducting charge generating layer; and wherein the interlayer comprises at least one phthalocyanine derivative.
US09287518B2	Light emitting device using graphene quantum dot and organic light emitting device including the same The present disclosure relates to a light emitting device using a graphene quantum dot, and an organic light emitting device including the same.
US09287517B2	Functionalization of sp3 hybridized carbon, silicon and/or germanium surfaces The invention concerns a method for preparing a grafted material comprising the following steps: a) providing a material which, on its surface, comprises sp3 hybridized carbon, silicon and/or germanium atoms carrying at least one hydrogen atom, and b) contacting in a solvent the material such as provided at step a) with a compound (C) carrying at least one amine function in the unprotonated state, whereby the said compound (C) is grafted onto the said material.
US09287513B2	Organic electroluminescent materials and devices In certain embodiments, the invention provides boron-nitrogen heterocycles having Formula (I): wherein one of the E1 and E2 is N, and one of the E1 and E2 is B; wherein E3 and E4 is carbon; wherein ring Y and ring Z are 5-membered or 6-membered carbocyclic or heterocyclic aromatic ring fused to ring X; wherein R2 and R3 represent mono, di, tri, tetra substitutions or no substitution; wherein R2 and R3 are each independently selected from various substituents; and wherein any two adjacent R2, and R3 are optionally joined to form a ring, which may be further substituted. In certain embodiments, the invention provides devices, such as organic light emitting devices, that comprise such boron-nitrogen heterocycles.
US09287512B2	Organic electroluminescent compounds, layers and organic electroluminescent device using the same The present invention relates to a novel organic electroluminescent compound, layer and an organic electroluminescent device using the same. Said organic luminescent compound provides an organic light emitting layer and/or device which has high luminous efficiency and a long operation lifetime and requires a low driving voltage improving power efficiency and power consumption.
US09287497B2	Integrated circuits with hall effect sensors and methods for producing such integrated circuits Integrated circuits with a Hall effect sensor and methods for fabricating such integrated circuits are provided. The method includes forming a buried plate layer within a substrate and overlying a substrate base, where the buried plate layer is doped with an “N” type dopant. A cover insulating layer if formed overlying the buried plate layer, and a plurality of contact points are formed adjacent to the cover insulating layer.
US09287495B2	Method of manufacturing semiconductor device According to one embodiment, a method of manufacturing a semiconductor device includes forming a silicon nitride layer on a metal layer, forming a plasma of a gas mixture of carbon oxide and oxygen, and selectively etching the silicon nitride layer with respect to the metal layer by using the plasma of the gas mixture.
US09287490B2	Laminated piezoelectric element and multi-feed detection sensor A laminated piezoelectric element that includes a piezoelectric element layer and a matching layer. The piezoelectric element layer is configured to have a plurality of piezoelectric layers and a plurality of electrode layers laminated together. The matching layer is laminated on the piezoelectric element layer, and is different in acoustic impedance from the piezoelectric element layer. When Vp represents the acoustic velocity in the piezoelectric element layer, Vm represents the acoustic velocity in the matching layer, Tp represents the thickness dimension of the piezoelectric element layer, and Tm represents the thickness dimension of the matching layer, Vp/Vm=Tp/Tm holds. Further, when W represents the dimension of the laminated piezoelectric element in the width direction, Tp+Tm>W holds.
US09287489B1	Piezoelectronic transistor with co-planar common and gate electrodes A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.
US09287488B2	Piezoelectric actuator device and method for manufacturing same A piezoelectric actuator device includes a vibrator and a driver to vibrate the vibrator. The vibrator includes a lower vibration layer configured to vibrate and an upper vibration layer coupled to an upper surface of the lower vibration layer and configured to vibrate together with the lower vibration layer. The driver includes an upper electrode layer on a lower surface of the lower vibration layer, a piezoelectric layer on a lower surface of the upper electrode layer, and a lower electrode layer on a lower surface of the piezoelectric layer. The lower vibration layer of the vibrator is made of organic material. The upper vibration layer is mainly made of inorganic material. The lower vibration layer has a smaller longitudinal elastic modulus than the upper vibration layer. The piezoelectric actuator device has a large resistance to disturbance vibrations and a large warping amount of the vibrator without increasing power consumption.
US09287487B2	Textile-based stretchable energy generator A textile-based stretchable energy generator is provided. The energy generator includes: flexible and stretchable first and second electrode substrates; and an energy generation layer, which is provided between the first and second electrode substrates and includes a dielectric elastomer for generating electrical energy from a transformation thereof.
US09287485B2	Methods for making low resistivity joints Method for joining wires using low resistivity joints is provided. More specifically, methods of joining one or more wires having superconductive filaments, such as magnesium diboride filaments, are provided. The wires are joined by a low resistivity joint to form wires of a desired length for applications, such in medical imaging applications.
US09287483B2	Thermoelectric material with improved in figure of merit and method of producing same A nanocomposite including: a thermoelectric material nanoplatelet; and a metal nanoparticle disposed on the thermoelectric material nanoplatelet.
US09287482B2	Light emitting diode package An embodiment of the invention provides a light emitting diode package. The light emitting diode package includes at least three light emitting diode chips; first leads comprising at least three chip mounting sections on which the at least three light emitting diode chips are mounted, respectively; second leads separated from the first leads and connected to the light emitting diode chips via wires, respectively; and a substrate having the first leads and the second leads formed thereon, wherein the at least three chip mounting sections are arranged around a center of the substrate through which an optical axis of the light emitting diode package passes.
US09287479B2	Luminous devices, packages and systems containing the same, and fabricating methods thereof The present invention is directed to a vertical-type luminous device and high throughput methods of manufacturing the luminous device. These luminous devices can be utilized in a variety of luminous packages, which can be placed in luminous systems. The luminous devices are designed to maximize light emitting efficiency and/or thermal dissipation. Other improvements include an embedded zener diode to protect against harmful reverse bias voltages.
US09287477B2	Light emitting diode package An LED package includes a lead frame, a housing part, and a lead heat dissipating part. The lead frame includes a first lead mounting an LED chip and a second lead spaced apart from the first lead. The housing part covers a portion of the lead frame and includes an opening part for exposing the LED chip, a first side corresponding to a support side contacting the first lead and the second lead, and a second side opposite to the first side. The lead heat dissipating part is extended from the first lead and exposed partially to the first side of the housing part. Herein, the first side of the housing part is thicker than the second side.
US09287476B2	Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means of an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.
US09287475B2	Solid state lighting component package with reflective polymer matrix layer A solid state lighting component comprising a layer having high reflectivity and/or scattering properties, the layer positioned about a solid state lighting component, and manufacturing methods of making same is disclosed. A method of increasing the luminous flux of the solid state lighting component, is also provided.
US09287474B2	Side-emitting optical coupling device An LED package includes a LED structure that outputs light in a pattern about an axis and an optical coupling device with a central axis. The coupling device is positioned relative to the LED structure and accepts light from the LED. The coupling device includes a first dielectric interface surface that is substantially cylindrical with respect to the central axis, and a reflecting surface. The first dielectric interface surface accepts a first portion of light from the LED structure and directs it toward the reflecting surface. The reflecting surface accepts the light from the first dielectric interface surface and directs it toward the first dielectric interface surface in a direction substantially perpendicular to the central axis.
US09287472B2	Light emitting device and method of manufacturing the same There is provided a light emitting device including a light emitting element, a covering member for covering a side surface of the light emitting element, and a light-transmissive member disposed on upper surfaces in a light emitting direction of the light emitting element and the covering member and having an end face on substantially the same plane as an end face of the covering member, wherein the covering member has a recess portion or a convex portion on the upper surface, a light emitting surface of the light emitting element and an upper surface other than the recess portion or the convex portion of the covering member are arranged on substantially the same plane, and the light-transmissive member is provided in contact with the recess portion or the convex portion.
US09287464B2	Light-emitting element having an optical function film including a reflection layer A light-emitting element includes a light-emitting layer, and an optical function film. The light-emitting layer is configured to include a first plane with a first electrode, a second plane with a second electrode, and a circumferential plane connecting the first and second planes, the second plane being opposing to the first plane, and the light-emitting layer being made of a semiconductor. The optical function film is configured to include a reflection layer being able to reflect light coming from the light-emitting layer, the reflection layer being provided with first and second regions, the first region covering the second plane and the circumferential plane, the second region protruding from the first region to an outside of the light-emitting layer to expose an end plane thereof.
US09287462B2	Light emitting diode and method of fabricating the same An exemplary embodiment discloses a light emitting diode including a first light emitting cell and a second light emitting cell disposed on a substrate, the first light emitting cell and the second light emitting cell being spaced apart from each other. The light emitting diode also includes a first zinc oxide (ZnO) layer disposed on the first light emitting cell, the first ZnO layer being electrically connected to the first light emitting cell. The light emitting diode also includes a current blocking layer disposed between a portion of the first light emitting cell and the first ZnO layer, an interconnection electrically connecting the first light emitting cell and the second light emitting cell, and an insulation layer disposed between the interconnection and a side surface of the first light emitting cell. The current blocking layer and a first side of insulation layer are connected to each other.
US09287461B2	Light-emitting diode and method for manufacturing the same The disclosure provides a light-emitting diode and a method for manufacturing the same. The light-emitting diode comprises a N-type metal electrode, a N-type semiconductor layer contacted with the N-type metal electrode, a P-type semiconductor layer, a light-emitting layer interposed between the N-type semiconductor layer and the P-type semiconductor layer, a low-contact-resistance material layer positioned on the P-type semiconductor layer, a transparent conductive layer covered the low-contact-resistance material layer and the P-type semiconductor layer, and a P-type metal electrode positioned on the transparent conductive layer.
US09287457B2	Light emitting device and light emitting device package Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer, an adhesive layer contacting a top surface of the first conductive semiconductor layer, a first electrode contacting a top surface of the first conductive semiconductor and a top surface of the adhesive layer, and a second electrode contacting the second conductive semiconductor layer, wherein the adhesive layer contacting the first electrode is spaced apart from the second electrode.
US09287452B2	Solid state lighting devices with dielectric insulation and methods of manufacturing Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The solid state lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure.
US09287449B2	Ultraviolet reflective rough adhesive contact A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.
US09287448B2	Semiconductor light emitting element According to one embodiment, a semiconductor light emitting element includes a light emitting layer, a current spreading layer of a first conductivity type, and a pad electrode. The light emitting layer is capable of emitting light. The current spreading layer has a first surface and a second surface. The light emitting layer is disposed on a side of the first surface. A light extraction surface having convex structures of triangle cross-sectional shape and a flat surface which is a crystal growth plane are included in the second surface. The pad electrode is provided on the flat surface. One base angle of the convex structure is 90 degrees or more.
US09287445B2	Nano-structured light-emitting devices A nano-structured light-emitting device includes a plurality of light-emitting nanostructures each having a resistant layer disposed thereon. The device includes a first semiconductor layer of a first conductivity type, and a plurality of nanostructures disposed on the first semiconductor layer. Each nanostructure includes a nanocore, and an active layer and a second semiconductor layer of a second conductivity type that enclose surfaces of the nanocores. An electrode layer encloses and covers the plurality of nanostructures A plurality of resistant layers are disposed on the electrode layer and each corresponds to a respective nanostructure of the plurality of nanostructures.
US09287442B2	Semiconductor material doping A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
US09287439B1	Method of conditioning the CdTe layer of CdTe thin-film solar cells The invention relates to a method for conditioning the CdTe layer of CdTe thin-film solar cells without the use of CdCl2. Calcium tetrachlorozincate (CaZnCl4) is to be used instead of CdCl2 for activation, and the process parameters that have proven themselves over time are to be kept. The method involves the activation of the CdTe layer of semi-finished thin-film CdTe solar cells; calcium tetrachlorozincate is applied to the CdTe layer (4) and the semi-finished thin-film CdTe solar cell subsequently undergoes a heat treatment. The calcium tetrachlorozincate layer is preferably applied via methods from the prior art, for instance roller coating with an aqueous or methanolic salt solution, spraying on an aqueous or methanolic salt solution, an aerosol coating or a dipping bath.
US09287436B2	Display device and manufacturing method thereof A display device includes: a first substrate; a photo transistor on the first substrate; and a switching transistor connected to the photo transistor. The photo transistor includes a light blocking film on the first substrate, a first gate electrode on the light blocking film and in contact with the light blocking film, a first semiconductor layer on the first gate electrode and overlapping the light blocking film, and a first source electrode and a first drain electrode on the first semiconductor layer. The switching transistor includes a second gate electrode on the first substrate, a second semiconductor layer on the second gate electrode and overlapping the second gate electrode, and a second source electrode and a second drain electrode on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are at a same layer of the display device, and each includes crystalline silicon germanium.
US09287432B2	Ge—Si P-I-N photodiode with reduced dark current and fabrication method thereof Various embodiments of a germanium-on-silicon (Ge—Si) photodiode are provided along with the fabrication method thereof. In one aspect, a Ge—Si photodiode includes a doped bottom region at the bottom of a germanium layer, formed by thermal diffusion of donors implanted into a silicon layer. The Ge—Si photodiode further includes a doped sidewall region of Ge mesa formed by ion implantation. Thus, the electric field is distributed in the intrinsic region of the Ge—Si photodiode where there is low dislocation density. The doped bottom region and sidewall region of the Ge layer prevent electric field from penetrating into the Ge—Si interface and Ge mesa sidewall region, where a large amount of dislocations are distributed. This design significantly suppresses dark current.
US09287425B2	Photodetector, liquid crystal display device, and light-emitting device One embodiment of the present invention includes a first light-blocking layer and a second light-blocking layer which are over a light-transmitting substrate, a first photodiode over the first light-blocking layer, a second photodiode over the second light-blocking layer, a first color filter covering the first photodiode, a second color filter covering the second photodiode, and a third light-blocking layer formed using the first color filter and the second color filter and disposed between the first photodiode and the second photodiode.
US09287424B2	Polyimide resin composition for use in forming reverse reflecting layer in photovoltaic cell and method of forming reverse reflecting layer in photovoltaic cell used therewith Disclosed are a method of forming a back reflection layer in a solar cell, a composition used therefor, and a solar cell having a back reflection layer formed by the method, which layer has superior heat-resistance and various types of durabilities, and can contribute to improving the conversion rate of solar cells and reliability during long-term use, and which method can form a back reflection layer in a solar cell easily and at low cost. The polyimide resin composition for use in forming a back reflection layer in a solar cell includes an organic solvent, a polyimide resin dissolved in the organic solvent, and light-reflecting particles dispersed in the organic solvent.
US09287423B2	Solid-state imaging device and method of manufacturing the solid-state imaging device A solid-state imaging device in which a plurality of pixels are two-dimensionally arranged includes a silicon layer; a plurality of photodiodes which are formed in the silicon layer to correspond to the pixels and generate signal charges by performing photoelectric conversion on incident light; and a plurality of color filters formed above the silicon layer to correspond to the plurality of the pixels. A protrusion is formed in a region on a side of the silicon layer between adjacent ones of the color filters wherein the protrusion has a refractive index lower than refractive indices of the adjacent ones of the color filters and, each of the color filters is in contact with the adjacent ones of the color filters, above the protrusion.
US09287422B2	Method for forming a photo-active layer of the solar cell The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
US09287420B2	Solar cell and paste composition for rear electrode of the same A paste composition for a rear electrode of a solar cell according to the embodiment includes conductive powder; an organic vehicle; and an additive including silicon or a metal.
US09287417B2	Semiconductor chip package and method for manufacturing thereof Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.
US09287415B2	Schottky barrier diode and method of manufacturing the same A Schottky barrier diode includes: an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a first p+ region disposed on the n− type epitaxial layer; an n type epitaxial layer disposed on the n− type epitaxial layer and the first p+ region; a second p+ region disposed on the n type epitaxial layer, and being in contact with the first p+ region; a Schottky electrode disposed on the n type epitaxial layer and the second p+ region; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate. Also, the first p+ region has a lattice shape including a plurality of vertical portions and horizontal portions connecting both ends of the respective vertical portions to each other.
US09287414B2	Integrated circuit An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.
US09287411B2	Semiconductor device and method for manufacturing the same In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
US09287410B2	Semiconductor device A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.
US09287409B2	Semiconductor device and manufacturing method thereof One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.
US09287407B2	Manufacturing method of semiconductor device A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the transistor capable of high-speed response and high-speed operation is provided. The transistor includes the oxide semiconductor film including a channel formation region and low-resistance regions in which a metal element and a dopant are included. The channel formation region is positioned between the low-resistance regions in the channel length direction. In a manufacturing method of the transistor, the metal element is added by heat treatment performed in the state where the oxide semiconductor film is in contact with a film including the metal element and the dopant is added through the film including the metal element by an implantation method so that the low resistance regions in which a metal element and a dopant are included are formed.
US09287406B2	Dual-mode transistor devices and methods for operating same A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.
US09287403B1	FinFET and method for manufacturing the same A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.
US09287402B2	Method of fabricating fin-field effect transistors (finFETs) having different fin widths Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.
US09287398B2	Transistor strain-inducing scheme A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.
US09287397B2	Semiconductor device and method of fabricating same A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.
US09287384B2	Vertical DMOS transistor A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.
US09287382B1	Structure and method for semiconductor device A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.
US09287380B2	Gate electrode having a capping layer A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
US09287378B2	Nitride semiconductor light-emitting element and method for fabricating the same Provided is a nitride semiconductor light-emitting element having a low contact resistance between an n-type nitride semiconductor layer and an n-side electrode. A portion of the n-type nitride semiconductor layer is removed by a plasma etching process using a gas containing halogen to expose a surface region of the n-type nitride semiconductor layer. Next, such an exposed surface region is further subjected to a plasma treatment using a gas containing oxygen. After that, the n-side electrode formed of aluminum is formed so as to be in contact with the surface region. In the surface region, a carrier concentration is decreased from the inside of the n-type nitride semiconductor layer toward the n-side electrode.
US09287377B2	Semiconductor device and manufacturing method A semiconductor device includes a trench extending into a semiconductor body from a first surface. At least one of a ternary carbide and a ternary nitride is in the trench.
US09287376B1	Method of manufacturing a gate trench with thick bottom oxide An insulated gate trench is manufactured by forming a first dielectric layer on a semiconductor substrate, forming a hardmask on the first dielectric layer and etching a trench into the semiconductor substrate through an opening in the hardmask and the first dielectric layer, the trench having sidewalls and a bottom. The sidewalls and bottom of the trench are lined with a second dielectric layer without an intervening oxide layer along the sidewalls and bottom of the trench. The second dielectric layer is removed from at least part of the bottom of the trench to expose part of the semiconductor substrate, and the exposed part of the semiconductor substrate is removed to form an oxide region at the bottom of the trench. Subsequently, a gate dielectric is formed on the sidewalls and bottom of the trench and a gate electrode in the trench without a separate field electrode in the trench.
US09287374B2	Semiconductor device and method for forming the same A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region, a device isolation film, a first liner nitride film disposed over a lower portion of a sidewall of the active region, and a second liner nitride film disposed over an upper portion of the sidewall of the active region and having a higher density of nitrogen than a density of nitrogen in the first liner nitride film.
US09287371B2	Semiconductor device having localized charge balance structure and method In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.
US09287363B2	Semiconductor device, method of manufacturing the same and power semiconductor device including the same A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer.
US09287362B1	Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.
US09287358B2	Stressed nanowire stack for field effect transistor A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.
US09287357B2	Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.
US09287356B2	Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.
US09287355B2	Semiconductor device A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.
US09287353B2	Composite substrate and method of manufacturing the same A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer.
US09287351B2	Composite substrate and method for manufacturing same [Problem] To provide a composite substrate which includes a silicon substrate having few lattice defects. [Solution] A composite substrate (50) that comprises a first substrate (10), which is constituted of a semiconductor material, a second substrate (40), which is constituted of an insulating material, and an oxide layer (30) and a semiconducting epitaxial layer (20) which have been disposed between the substrates (10) and (40) in this order from the second substrate (40) side, the oxide layer (30) having oxygen atoms arranged on the side thereof which faces the epitaxial layer (20).
US09287349B2	Semiconductor memory devices and methods of forming the same According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.
US09287347B2	Metal-insulator-metal capacitor under redistribution layer A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.
US09287346B2	Semiconductor device A semiconductor device includes a semiconductor substrate having a capacitor region and a resistor region. A capacitor dielectric material and a capacitor electrode are sequentially stacked on an active region in the capacitor region of the semiconductor substrate. A resistor is provided on the resistor region of the semiconductor substrate. A protection pattern is provided on a top surface of the capacitor electrode. The protection pattern is spaced apart from the capacitor electrode. The protection pattern and the resistor include the same material and have the same thickness in a direction vertical to a surface of the semiconductor substrate.
US09287343B2	Display device and method for manufacturing the same It is an object of the present invention to provide a display device preventing the external invasion of water and/or oxygen and preventing the deterioration of a luminous element due to these invading substances and to provide a production method including simple production steps for producing the display device. The invention provides a display device having a sealing material on the rim of an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Further, the invention provides a display device having a barrier body on an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Furthermore, the application of droplet discharge technique in production steps for producing the display device can eliminate a photolithography step such as exposing and developing. Thus, a method of producing a display device having an improved yield is provided.
US09287339B2	Organic light emitting display device and method of manufacturing the same An organic light emitting display and a method of manufacturing the same. The organic light-emitting display is a transparent display where one can see through the display to view an image on the other side of the display. Each pixel of the display has a first region that includes an organic light emitting diode and a thin film transistor, and a larger second region that is transparent. The second region is made of either transparent layers or ultra thin layers so that light is not blocked. A second electrode of the display may include magnesium and may be produced by a selective deposition process, so that use of a fine metal mask may be avoided.
US09287338B2	Portable electronic apparatus A portable electronic apparatus comprises a substrate comprising a first surface and a second surface; a plurality of pixel electrodes arranged over the first surface of the substrate; a pixel-defining layer arranged over the first surface of the substrate such that at least a portion of each of the plurality of pixel electrodes is exposed; a plurality of protrusions formed over the pixel-defining layer; and an electronic component arranged over the second surface of the substrate and attached to the substrate, the electronic component having a polygonal shaped surface facing and substantially parallel to the second surface of the substrate. When viewed in a direction perpendicular to the second surface, imaginary straight lines that pass the plurality of protrusions are substantially parallel to at least one among sides of the polygonal shaped surface and do not pass the exposed portions of the plurality of pixel electrodes.
US09287332B2	Light-emitting device comprising light-emitting elements having different optical path lengths A light-emitting device and a lighting device each of which includes a plurality of light-emitting elements exhibiting light with different wavelengths are provided. The light-emitting device and the lighting device each have an element structure in which each of the light-emitting elements emits only light with a desired wavelength, and thus the light-emitting elements have favorable color purity. In the light-emitting element emitting light (λR) with the longest wavelength of the light with different wavelengths, the optical path length from a reflective electrode to a light-emitting layer (a light-emitting region) included in an EL layer is set to λR/4 and the optical path length from the reflective electrode to a semi-transmissive and semi-reflective electrode is set to λR/2.
US09287331B2	Display unit A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity.
US09287329B1	Flexible display device with chamfered polarization layer There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
US09287328B2	Photoelectric conversion device and imaging device using the same An organic photoelectric conversion device having a pair of electrodes and a light receiving layer which includes at least a photoelectric conversion layer and is sandwiched by the electrodes, the device including an electron blocking layer provided between the photoelectric conversion layer and one of the electrodes, and a hole blocking layer provided between the photoelectric conversion layer and the other of the electrodes, in which the hole blocking layer is a layer that includes a fullerene and/or a fullerene derivative and a transparent hole transport material having an ionization potential of 5.5 eV or more.
US09287323B2	Perpendicular magnetoresistive elements A perpendicular magnetoresistive element comprises anovel buffer layer provided on a surface of the recording layer, which is opposite to a surface of the recording layer where the tunnel barrier layer is provided, wherein at least the portion of the buffer layer interfacing to the recording layer contains a rocksalt crystal structure having the (100) plane parallel to the substrate plane and at least a portion of the buffer layer comprises a doped element having conductivity enhancement and the perpendicular resistance of the buffer layer is relatively small than that of the tunnel barrier layer. The invention preferably includes materials, configurations and processes of perpendicular magnetoresistive elements suitable for perpendicular spin-transfer torque MRAM applications.
US09287315B2	Thin film transistor array substrate for digital photo-detector A thin film transistor array substrate for a digital photo-detector is provided. The photo-detector includes a plurality of gate lines to supply a scan signal; a plurality of data lines to output data, the data lines arranged in a direction crossing the gate lines, wherein cell regions are defined by the gate lines and the data lines; a photodiode in each of the cell regions to perform photoelectric conversion; a thin film transistor at each intersection between the gate lines and the data lines to output a photoelectric conversion signal from the photodiode to the data lines in response to a scan signal supplied by the gate lines; and a light-shielding layer over each channel region of the respective thin film transistors. Each light-shielding layer is electrically connected to the respective gate line.
US09287314B2	Solid-state imaging device, light detecting device, and electronic apparatus A solid-state imaging device includes a Multi-Quantum Wells (MQW) structure which combines and uses a non-Group IV lattice matching-based compound semiconductor with an absolute value of a mismatch ratio of less than 1% on a silicon substrate so as to have sensitivity to at least infrared light.
US09287309B2	Isolation structure having a second impurity region with greater impurity doping concentration surrounds a first impurity region and method for forming the same, and image sensor including the isolation structure and method for fabricating the image sensor An isolation structure and method of forming the same. The isolation structure includes a first isolation structure having including an insulation layer formed in a trench in a substrate and a second isolation structure, formed on the first isolation structure. The second isolation structure includes a first impurity region formed in the substrate, the first impurity region having a first impurity doping concentration, and a second impurity region that is formed around the first impurity region, the second impurity region having a second impurity doping concentration that is greater than the first doping concentration.
US09287299B2	Back plane for flat panel display and method of manufacturing the same There are provided a back plane for a flat panel display and a method of manufacturing the back plane, and more particularly, a back plane for an organic light-emitting display device, which enables front light-emitting, and a method of manufacturing the back plane. The back plane for a flat panel display includes: a substrate; a gate electrode on the substrate; a first capacitor on the substrate, the first capacitor comprising a first electrode, an insulation pattern layer on the first electrode, and a second electrode on the insulation pattern layer; a first insulation layer on the substrate to cover the gate electrode and the first capacitor; an active layer on the first insulation layer to correspond to the gate electrode; and a source electrode and a drain electrode on the substrate to contact a portion of the active layer.
US09287298B2	Liquid crystal display and manufacturing method thereof A liquid crystal display includes: a first substrate, a gate line and a data line disposed on the first substrate, a thin film transistor connected to the gate line and the data line, a first passivation layer disposed on the thin film transistor, a first electrode disposed on the first passivation layer, a second passivation layer disposed on the first electrode and a second electrode disposed on the second passivation layer. A first edge of the first electrode and a second edge of the second passivation layer have substantially the same plane shape as each other, and the second edge of the second passivation layer protrudes more than the first edge of the first electrode.
US09287295B2	Display apparatus and method of detecting short-circuit failure of the display apparatus A display apparatus is disclosed. The apparatus includes a plurality of unit pixels each comprising a plurality of sub pixels, a plurality of scan wires, and a plurality of scan lines branching off from each of the scan wires and extending in a first direction. The number of scan lines from each scan wire equals the number of sub pixels for each pixel, and each scan line connects one of the scan wires with one of the sub pixels of each of a plurality of unit pixels. The apparatus also includes a plurality of data lines extending in a second direction orthogonal to the first direction and which are connected to the plurality of sub pixels. The apparatus also includes a first power supply line extending in the second direction and connected to the sub pixels, and a plurality of test pads, each connected to the scan lines of one of the scan wires.
US09287294B2	Capacitor and semiconductor device having oxide semiconductor An object is to provide a novel semiconductor device which can store data even when power is not supplied in a data storing time and which does not have a limitation on the number of writing operations. The semiconductor device includes a transistor and a capacitor. The transistor includes a first oxide semiconductor layer, a source electrode and a drain electrode which are in contact with the first oxide semiconductor layer, a gate electrode overlapping with the first oxide semiconductor layer, and a gate insulating layer between the first oxide semiconductor layer and the gate electrode. The capacitor includes the source electrode or the drain electrode, a second oxide semiconductor layer in contact with the source electrode or the drain electrode, and a capacitor electrode in contact with the second oxide semiconductor layer.
US09287291B2	Multiple-bit-per-cell, independent double gate, vertical channel memory having split channel A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip.
US09287290B1	3D memory having crystalline silicon NAND string channel Disclosed herein are 3D NAND memory devices having vertical NAND strings with a crystalline silicon channel and techniques for fabricating the same. The NAND string channel may be a single crystal of silicon or have a few large grains of polysilicon. The single crystal may have a (100) orientation with respect to a tunnel oxide of the 3D NAND string. When the channel region comprises grains of polysilicon, predominantly all of the silicon channel is part of a grain of polysilicon having the (100) orientation. The (100) orientation may be favorable for high carrier mobility. Techniques using metal induced crystallization (MIC) for forming the NAND strings having a crystalline silicon channel are also disclosed.
US09287282B2	Method of forming a logic compatible flash memory A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.
US09287281B2	Flash devices and methods of manufacturing the same Flash devices and methods of manufacturing the same are provided. The device may include: a semiconductor substrate, with a well region therein; a sandwich arrangement on the well region, including a back gate conductor, semiconductor fins on opposite sides of the back gate conductor, and back gate dielectric layers separating the back gate conductor from the respective semiconductor fins, wherein the well region serves as a part of a conductive path to the back gate conductor; a front gate stack intersecting the semiconductor fins, including a floating gate dielectric layer, a floating gate conductor, a control gate dielectric layer, and a control gate conductor stacked sequentially, wherein the floating gate dielectric layer separates the floating gate conductor from the semiconductor fins; an insulating cap on top of the back gate conductor and the semiconductor fins to separate the back gate conductor from the front gate stack; and source and drain regions connected to a channel region provided by each of the semiconductor fins. The device can achieve high integration and low power consumption.
US09287280B2	Method to improve memory cell erasure A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.
US09287279B2	Silicon nitride (SiN) encapsulating layer for silicon nanocrystal memory storage Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.
US09287277B2	Semiconductor device and fabricating method thereof A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.
US09287276B2	Memory cell array A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.
US09287272B2	Metal trench capacitor and improved isolation and methods of manufacture A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
US09287268B2	Dynamic random access memory (DRAM) and production method, semiconductor packaging component and packaging method A dynamic random access memory (DRAM) and a production method, a semiconductor packaging component and a packaging method. The production method comprises: providing a memory wafer, the memory wafer being provided with a memory bare chip which is provided with a top metal layer which is provided with a power source bonding pad, a signal bonding pad, and a micro bonding pad, and an internal bus led out of the memory bare chip being electrically connected to the micro bonding pad; repairing the memory wafer; if a yield of the memory wafer is greater than or equal to a preset threshold, rearranging the micro bonding pad to form a butt-joint bonding pad which is electrically connected to the micro bonding pad and the power source bonding pad. A structure of the DRAM is not significantly changed, a data bandwidth of the DRAM is increased, and a high yield is ensured.
US09287265B2	Semiconductor device and method for fabricating the same A semiconductor device includes a substrate with an active region defined by a device isolation layer. A word line extends over the active region in a first direction, and a plurality of interconnections extends over the word line in a second direction perpendicular to the first direction. A contact pad is disposed between and spaced apart from the word line and the plurality of interconnections, extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view. A lower contact plug electrically connects the contact pad to the active region. An upper contact plug electrically connects the contact pad to one of the plurality of interconnections.
US09287259B2	Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
US09287258B2	Semiconductor device At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.
US09287256B2	Semiconductor device including a separation region formed around a first circuit region Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
US09287255B2	ESD protection device and related fabrication methods ESD protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base well region having a first conductivity type, a collector region of the opposite conductivity type, and a second base well region having a dopant concentration greater than the first base well region, and a portion of the second base well region is disposed between the first base well region and the collector region. A third base well region with a different dopant concentration is disposed between the collector region and the second base well region. At least a portion of the first base well region is disposed between a base contact region and an emitter region within the second base well region.
US09287254B2	Electronic device and protection circuit An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.
US09287253B2	Method and apparatus for floating or applying voltage to a well of an integrated circuit In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.
US09287250B2	Package substrate A package substrate includes an inner interlayer, a first conductor layer on the inner interlayer, a second conductor layer on which the inner interlayer is formed, an outermost interlayer on the first conductor layer, an outermost conductor layer on the outermost interlayer and including first and second pads positioned to mount first and second electronic components on the outermost interlayer, outermost vias connecting the first and outermost conductor layers through the outermost interlayer, and skip vias connecting the outermost and second conductor layers through the outermost and inner interlayers. The first conductor layer includes a first circuit connecting two outermost vias, and the outermost conductor layer includes an outermost circuit connecting one of the two outermost vias and one skip via such that the first conductor circuit, two outermost vias, outermost circuit and one skip via form a connection path connecting one second pad and the second conductor layer.
US09287246B2	Package assembly and methods for forming the same A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.
US09287244B2	Semiconductor light device having a galvanic non-insulated driver A semiconductor light-emitting device is disclosed. The device includes a plurality of semiconductor light sources and a driver with no galvanic isolation for operating the semiconductor light sources wherein the semiconductor light sources may be divided into at least two carriers, the carriers are applied on an electrically conductive substrate, and the driver, and current-conducting regions also provided on a surface of the carriers, are electrically insulated from the substrate.
US09287243B2	Optical device and method for manufacturing same The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate.
US09287236B2	Flexible packaged integrated circuit A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device.
US09287231B2	Package structure with direct bond copper substrate A package structure includes a first insulation layer, a first conductive layer, a direct bond copper substrate, and a first electronic component. A first conductive via is formed in the first insulation layer. The first conductive layer is disposed on a top surface of the first insulation layer and in contact with the first conductive via. The direct bond copper substrate includes a second conductive layer, a third conductive layer and a ceramic base. The ceramic base is disposed on a bottom surface of the first insulation layer and exposed to the first insulation layer by press-fit operation. The first electronic component is embedded within the first insulation layer and disposed on the second conductive layer. The first electronic component includes a first conducting terminal. The first conducting terminal is electrically connected with the second conductive layer and/or electrically connected with the first conductive layer through the first conductive via.
US09287226B2	Apparatus and methods for reducing impact of high RF loss plating To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.
US09287225B2	Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.
US09287224B2	High-frequency module A high-frequency module includes a lower base member having a recess part formed in an upper face thereof, and having a base metal part formed on a lower face thereof that is to be grounded, an upper substrate disposed inside the recess part of the lower base member, a semiconductor device mounted on an upper face of the upper substrate, a first ground line connected to the semiconductor device and formed on the upper substrate, and a ground metal part connected to the base metal part and disposed in the lower base member, wherein the ground metal part is connected to the first ground line on the upper substrate.
US09287222B1	Integrated semiconductor device and method for fabricating the same An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.
US09287218B2	Chip level EMI shielding structure and manufacture method thereof A chip level EMI shielding structure and manufacture method thereof are provided. The chip level EMI shielding structure includes a semiconductor substrate, at least one ground conductor line, a ground layer, and a connection structure. The ground conductor line is disposed on a first surface of the semiconductor substrate, and the ground layer is disposed on a second surface of the semiconductor substrate. The connection structure is formed on a lateral wall of the semiconductor substrate for connecting the ground conductor lines with the ground layer to form a shielding. With such arrangement, the chip level EMI shielding structure can reduce the chip size and the manufacturing cost.
US09287215B2	Source driver integrated circuit and display device comprising source driver integrated circuit A source driver integrated circuit comprises a common node; a plurality of pads for inputting power, a portion of which are connected to an external power source and the remainder of which are connected to the portion through the common node; and a common power line which is connected to the plurality of power input pads through the common node. As a result, the resolution of adjacent channels varies very little and block dimming between channels can be resolved.
US09287214B2	Semiconductor device A semiconductor device and a method of forming the same are disclosed, which forms a low-dielectric-constant oxide film only at a peripheral part of a bit line conductive material, resulting in reduction in parasitic capacitance of the bit line. The semiconductor device includes a bit line formed over a semiconductor substrate, a first spacer formed over sidewalls of the bit line, and a second spacer formed over sidewalls of the first spacer, configured to have a dielectric constant lower than that of the first spacer.
US09287212B2	Semiconductor device interconnection structure having dielectric-filled notches A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer.
US09287208B1	Architecture for on-die interconnect In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.
US09287207B2	Methods for forming conductive vias in semiconductor device components A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.
US09287206B2	Method of fabricating a semiconductor device with encapsulant A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.
US09287205B2	Fan-out high-density packaging methods and structures A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.
US09287199B2	CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.
US09287198B2	Interconnection structure including air gap, semiconductor device including air gap, and method of manufacturing the same A semiconductor device includes a first insulating layer, a second insulating layer formed on the first insulating layer, a plurality of interconnection lines formed in the second insulating layer, and a first air gap disposed between the first insulating layer and the second insulating layer to surround a lower part of the interconnection lines.
US09287193B2	Semiconductor device A semiconductor device 1 includes a thermal radiation member 4; a first semiconductor chip 21 connected to the thermal radiation member 4; a second semiconductor chip 22 connected to the thermal radiation member 4; and sealing resin 93 sealing the first semiconductor chip 21 and the second semiconductor chip 22. The semiconductor device 1 comprises a first thermal diffusion member 31 connected to the thermal radiation member 4; a second thermal diffusion member 32 connected to the thermal radiation member 4; and a cooler 5 configured to cool the first thermal diffusion member 31 and the second thermal diffusion member 32. A space between the first thermal diffusion member 31 and the second thermal diffusion member 32 is positioned to oppose a space between the first semiconductor chip 21 and the second semiconductor chip 22 via the thermal radiation member 4.
US09287192B2	Semiconductor device and method for manufacturing semiconductor device A semiconductor device includes a cooling device, an insulating substrate, a semiconductor element, an external connection terminal, and a resin portion. The insulating substrate is brazed to an outer surface of the cooling device. The semiconductor element is brazed to the insulating substrate. The external connection terminal includes a first end, which is electrically connected to the semiconductor element, and an opposite second end. The resin portion is molded to the insulating substrate, the semiconductor element, the first end of the external connection terminal, and at least part of the cooling device.
US09287186B2	Method and structure for determining thermal cycle reliability A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
US09287183B1	Using electroless deposition as a metrology tool to highlight contamination, residue, and incomplete via etch A method for detecting contamination on a patterned substrate includes: performing a via etch operation on a substrate, wherein the via etch operation is configured to define a via feature on the substrate and expose an etch-stop layer at a bottom of the via feature; performing an etch-stop removal operation on the substrate, wherein the etch-stop removal operation is configured for removing the etch-stop layer at the bottom of the via feature to expose a metallic feature underlying the etch-stop layer; applying an electroless deposition solution to the substrate, the applied electroless deposition solution configured for selectively depositing a metallic material over the exposed metallic feature and on metallic contaminants on exposed surfaces of the substrate, the metallic contaminants being generated from the metallic feature during the etch-stop removal operation; performing an inspection operation on the substrate to identify the metallic contaminants that have been deposited with the metallic material.
US09287182B2	Fabrication method for semiconductor device with three or four-terminal-FinFET Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate.
US09287181B2	Semiconductor device and method for fabricating the same Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
US09287180B2	Integrated circuits having finFETs with improved doped channel regions and methods for fabricating same Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.
US09287179B2	Composite dummy gate with conformal polysilicon layer for FinFET device The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
US09287174B2	Fiber-containing resin substrate, device-mounting substrate and device-forming wafer, semiconductor apparatus, and method for producing semiconductor apparatus A fiber-containing resin substrate for collectively encapsulating a semiconductor-device-mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor-device-forming surface of a wafer on which a semiconductor device is formed, including a resin-impregnated fibrous base material which is obtained by impregnating a fibrous base material with a thermosetting resin and semi-curing or curing the thermosetting resin and has a linear expansion coefficient (ppm/° C.) in an X-Y direction of less than 3 ppm, and an uncured resin layer formed of an uncured thermosetting resin on one side of the resin-impregnated fibrous base material.
US09287171B2	Method of making a conductive pillar bump with non-metal sidewall protection structure A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.
US09287170B2	Contact structure and formation thereof A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
US09287168B2	Semiconductor device and process for producing the same A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.
US09287164B2	Single exposure in multi-damascene process Cavities of possibly different widths can be etched in a stack of conductive layers (such as metal) using the same lithographic mask. Dielectric can be formed in the cavities. The cavities may contain voids. Other embodiments are also provided.
US09287163B2	Method for forming void-free polysilicon and method for fabricating semiconductor device using the same A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern.
US09287162B2	Forming vias and trenches for self-aligned contacts in a semiconductor structure A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.
US09287160B2	Semiconductor devices and methods of fabricating the same A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.
US09287154B2	UV curing system for semiconductors Embodiments of an ultraviolet (UV) curing system for treating a semiconductor substrate such as a wafer are disclosed. The curing system generally includes a processing chamber, a wafer support for holding a wafer in the chamber, a UV radiation source disposed above the chamber, and a UV transparent window interspersed between the radiation source and wafer support. In one embodiment, the wafer support is provided by a belt conveyor operable to transport wafers through the chamber during UV curing. In another embodiment, the UV radiation source is a movable lamp unit that travels across the top of the chamber for irradiating the wafer. In another embodiment, the UV transparent window includes a UV radiation modifier that reduces the intensity of UV radiation on portions of the wafer positioned below the modifier. Various embodiments enhance wafer curing uniformity by normalizing UV intensity levels on the wafer.
US09287153B2	Semiconductor baking apparatus and operation method thereof A semiconductor baking apparatus includes a load lock chamber, a process chamber, a transfer chamber, a first interior door, and a controller. The process chamber has a first accommodating space therein. The transfer chamber has a second accommodating space therein, and the transfer chamber is connected to the load lock chamber and the process chamber. The first interior door is between the process chamber and the transfer chamber. When the first interior door is opened, the first accommodating space is communicated with the second accommodating space. The controller is programmed to open the first interior door when the semiconductor baking apparatus idles.
US09287150B2	Reticle transfer system and method A fabrication system comprises a global system comprising a plurality of stockers and a global transportation system connected to the stockers, a local system coupled to the global system through the global transportation system, wherein the local system comprises a first buffer located at a boundary between the global system and the local system, a plurality of lithography apparatuses coupled to the first buffer through a local transportation system and an empty pod buffer.
US09287140B2	Semiconductor packages having through electrodes and methods of fabricating the same Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.
US09287135B1	Sidewall image transfer process for fin patterning A method of using sidewall image transfer (SIT) process to pattern fin structures is provided. The method includes providing a fin-patterning substrate containing a first hard-mask layer and a second hard-mask layer over a semiconductor substrate. Trench openings formed on the semiconductor substrate extending vertically through the first hard-mask layer and the second hard-mask layer. Trench openings are filled with a third hard-mask material. The second hard-mask layer is removed to reveal hard-mask mandrels. First sidewall spacers are formed on the opposite sides of the hard-mask mandrels using atomic layer deposition (ALD) process. The semiconductor substrate is etched using the first sidewall spacers and the hard-mask mandrels as mask, subsequently the spacers, the mandrels and the hard-mask layer are removed to reveal fin structures. The method of the present invention is to form fins at a very tight fin pitch by using the very tight thickness controllability of ALD process. By repeating the ALD step twice or more to form multiple SIT spacers the fin pitch size can be reduced further. The inventive method is suitable for fabricating tight fin pitch to less than about 20 nm.
US09287133B2	Hard mask removal scheme A method for hard mask layer removal includes dispensing a chemical on a hard mask layer, in which the chemical includes an acidic chemical. The chemical is drained from a chamber after hard mask removal.
US09287129B2	Method of fabricating FinFETs The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height.
US09287120B2	Method for dispersing quantum dots or quantum wires in zeolite, method for stabilizing quantum dots or quantum wires in zeolite, and zeolite containing quantum dots or quantum wires dispersed by the method The present application relates to a method for dispersing quantum dots (QDs) or quantum wires in zeolite, to zeolite containing quantum dots or quantum wires dispersed by the method, and to a method for stabilizing quantum dots or quantum wires in zeolite.
US09287117B2	Semiconductor device comprising an oxide semiconductor To provide a highly reliable semiconductor device including an oxide semiconductor by suppression of change in its electrical characteristics. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled. Further, extraction of oxygen from the oxide semiconductor layer by a source electrode layer or a drain electrode layer in the vicinity of the channel formed in the oxide semiconductor layer is suppressed, whereby oxygen vacancies which might be generated in a channel are suppressed.
US09287116B2	Method of forming multilayer graphene structure According to example embodiments, a method of forming a multilayer graphene structure includes forming a sacrificial layer on the growth substrate, growing a first graphene layer on the sacrificial layer using a chemical vapor deposition (CVD) method, and growing at least one more graphene layer on the growth substrate. The growing at least one more graphene layer includes removing at least a part of the sacrificial layer.
US09287115B2	Planar III-V field effect transistor (FET) on dielectric layer A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
US09287105B2	Mass spectrometric system There is a tendency of the intensity and the shape of a spectrum to be measured transitioning with the passage of measured time, depending on the volatility and the reactivity of a component. A mass spectrometric system includes: a mass spectrometric unit that measures a specimen and outputs a mass spectrum; and an estimator that has an estimation rule on content information, the estimation rule being assigned to each component and each measurement time. The estimator estimates, based on a mass spectrum output from the mass spectrometric unit, content information on each component of a plurality of components that may be contained in the specimen in accordance with the estimation rule.
US09287098B2	Charge removal from electrodes in unipolar sputtering system This disclosure describes a non-dissipative snubber circuit configured to boost a voltage applied to a load after the load's impedance rises rapidly. The voltage boost can thereby cause more rapid current ramping after a decrease in power delivery to the load which results from the load impedance rise. In particular, the snubber can comprise a combination of a unidirectional switch, a voltage multiplier, and a current limiter. In some cases, these components can be a diode, voltage doubler, and an inductor, respectively.
US09287091B2	System and methods for plasma application A plasma system includes a plasma device, an ionizable media source, and a power source. The plasma device includes an inner electrode and an outer electrode coaxially disposed around the inner electrode. The inner electrode includes a distal portion and an insulative layer that covers at least a portion of the inner electrode. The ionizable media source is coupled to the plasma device and is configured to supply ionizable media thereto. The power source is coupled to the inner and outer electrodes, and is configured to ignite the ionizable media at the plasma device to form a plasma effluent having an electron sheath layer about the exposed distal portion.
US09287084B2	Aberration corrector and charged particle beam apparatus using the same Provided are an aberration corrector that reduces irregularity of a magnetic field of a multipole to obtain an image of high resolution and a charged particle beam apparatus using the same. The aberration corrector includes a plurality of magnetic field type poles, a ring that magnetically connects the plurality of poles with one another and an adjustment member disposed between the pole and the ring to adjust a spacing between the pole and the ring per pole.
US09287083B2	Charged particle beam device Provided is a charged particle beam device that is capable of suppressing an field-of-view deviation occurring when observing a tilted image or a left-right parallax-angle image acquired by irradiating a tilted beam on a sample while continuously compensating a focus. By means of an aligner for compensating field-of-view (54) installed between an objective lens (7) that focuses a primary charged particle beam on a surface of the sample (10), and a deflector for controlling tilt angle (53) that tilts the primary charged particle beam, the field-of-view deviation occurring during tilting of the primary charged particle beam is suppressed based on an amount of compensation required by a tilt angle of the deflector for controlling tilt angle (53), lens conditions, and a distance between the objective lens (7) and the sample (10), in conjunction with a focus compensation of the objective lens (7).
US09287079B2	Apparatus for dynamic temperature control of an ion source An apparatus for controlling the temperature of an ion source is disclosed. The ion source includes a plurality of walls defining a chamber in which ions are generated. To control the temperature of the ion source, one or more heat shields is disposed exterior to the chamber. The heat shields are made of high temperature and/or refractory material designed to reflect heat back toward the ion source. In a first position, these heat shields are disposed to reflect a first amount of heat back toward the ion source. In a second position, these heat shields are disposed to reflect a lesser second amount of heat back toward the ion source. In some embodiments, the heat shields may be disposed in one or more intermediate positions, located between the first and second positions.
US09287076B2	Fusible link unit A fusible link unit which is fastened to a battery post clamp terminal clamped to an on-vehicle battery, includes: a bus bar made from a metal plate and including: a battery terminal including at least two mounting edges, and a plurality of fastening holes provided thereon and through which a fastening member of the battery post clamp terminal is inserted, each of the fastening holes corresponding to a respective one of the mounting edges; and at least one fusible portion provided at a side of the bus bar opposite to the battery terminal; and a resin case covering the bus bar except for the at least one fusible portion.
US09287071B1	High-safety surge protective device The invention relates to a high-safety surge protective device which comprises a casing, at least one overvoltage protection component inside the casing, a release unit used to separate the overvoltage protection component from the AC or DC circuit or the equipment, an arc suppressing apparatus used to suppress electric arc generated while separating the overvoltage protection component from the AC or DC circuit or the equipment, and a box, Wherein: the release unit comprises a compression spring, a metal dome, a slide and a soft conductor; the arc suppressing apparatus comprises an arc chute assembly, a first arc striking sheet, a second arc striking sheet, a turning block and a torsional spring.
US09287070B2	High voltage direct current circuit breaker arrangement and method A DC circuit breaker arrangement for interrupting a direct current on a line, includes: n DC circuit breakers connected in parallel, where n>2, which parallel connection of DC circuit breakers is connected in series with the line, the direct current of the line being divided between the n DC circuit breakers, and n reactors, each reactor being connected to one of the DC circuit breakers, for preserving the current division during current interruption. A method for interrupting or commutating a direct current on a transmission line or in a HVDC circuit is also provided.
US09287064B2	Switching device and method for detecting malfunctioning of such a switching device This switching device comprises at least one pair of fixed contacts and, for each pair of fixed contacts, a movable contact that is movable between a closed position and an open position. A contact holder capable of holding in place each movable contact is also provided. The contact holder is movable along a vertical direction between a first position corresponding to the closed position of each movable contact and a second position corresponding to the open position of the or each movable contact. The device also includes a plate capable of applying a force on the movable contact holder so as to move it between its first and second positions. The plate is movable relative to the movable contact holder. The device includes a sensor capable of measuring the movement of the movable plate relative to the movable contact holder, during the actuation of the movement of the plate in order to drive the movement of the contact holder from its first position to its second position. A detection member for detecting a malfunction in the switching device based on at least one value measured by the sensor is also provided.
US09287059B2	Electric storage device and method of manufacture thereof In an electric storage device, a terminal plate includes an element-connecting part electrically connected to a first electrode at a first end of an electric storage element, and an external terminal connected to this element-connecting part. A sealing member is on the element-connecting part, and includes a hole where the external terminal is inserted. The sealing member and the external terminal seal an opening of an outer jacket. The external terminal includes a tapered part on its outer periphery at a tip, and is partially exposed from the sealing member. The tapered part includes a first end and a second end farther away from the element-connecting part than the first end. An edge of a side wall at the opening of the outer jacket is between the first and second ends of the tapered part in a first direction extending from the bottom to the opening of the outer jacket.
US09287053B2	Method of manufacturing solid electrolytic capacitor A method of manufacturing a solid electrolytic capacitor having an even conductive polymer layer includes the steps of forming a conductive polymer layer on an anode element by bringing a dispersion containing a conductive solid and a first solvent into contact with the anode element having a dielectric film formed thereon, washing the anode element with a second solvent higher in boiling point than the first solvent, in which the conductive solid can be dispersed, after the conductive polymer layer is formed, and drying the anode element washed with the second solvent at a temperature not lower than the boiling point of the first solvent and lower than the boiling point of the second solvent.
US09287045B2	Dielectric ceramic composition and multilayer ceramic capacitor including the same There are provided a dielectric ceramic composition and a multilayer ceramic capacitor including the same. The dielectric ceramic composition according to embodiments of the present disclosure includes a base powder represented by xSrTiO3-(1−x)BiMO3 (M includes Mg and Ti) containing a first main component represented by SrTiO3 and a second main component represented by BiMO3, wherein x satisfies 0.5≦x≦0.9.
US09287044B2	Electronic component and fabrication method thereof There are provided an electronic component and a fabrication method thereof. The electronic component includes: a ceramic main body including end surfaces in a length direction, side surfaces in a width direction and top and bottom surfaces in a thickness direction; first and second external electrodes formed on the end surfaces, respectively; third and fourth external electrodes formed on the side surfaces, respectively; first internal electrodes formed within the ceramic main body and connected to first and second external electrodes; and second internal electrodes alternately arranged with the first internal electrodes, while having a ceramic layer interposed therebetween, and connected to the third and fourth external electrodes, wherein thickness t1 and t2 of the first and second internal electrodes is 0.9 μm or less, while a roughness R1 of the first internal electrode is lower than a roughness R2 of the second internal electrode.
US09287038B2	Coupled inductors with non-uniform winding terminal distributions A coupled inductor includes a ladder magnetic core including two opposing rails extending in a lengthwise direction and joined by a plurality of rungs. The coupled inductor further includes a respective winding wound around each of the plurality of rungs. The plurality of rungs are divided into at least two groups of rungs, and a lengthwise separation distance between adjacent rungs in each group of rungs is less than a lengthwise separation distance between adjacent rungs of different groups of rungs.
US09287037B2	Transformer-bobbin and transformer A transformer-bobbin including a winding-frame portion constituted by a middle barrel portion 63, a lower flange portion 62 and an upper flange portion 61, wherein there is provided a slit portion 67 which notches the terminal bed unit 65 and the lower flange portion 62 and concurrently which extends in the centrally approaching and separating direction toward the middle barrel portion 63 side, and wherein at the slit portion 67, there is provided a guide wall surface 68a whose side on the middle barrel portion 63 side is positioned on the lower flange portion side compared with whose side apart from the middle barrel portion 63.
US09287036B2	Supplementary transformer winding A transformer winding and a dry-transformer are disclosed, which include a main transformer winding, and a supplementary transformer winding configured to be electrically connected in series with the main transformer winding. The supplementary transformer winding can include a first winding module, a second winding module, and a third winding module, each of the winding modules having at least a first, a second and a third winding segment, and wherein each of the winding segments has a tap. A changer is configured to be connected to the taps of the second winding module, and wherein the second winding module is configured to be electrically connected in series to at least one winding segment of the first winding module and the third winding module.
US09287032B1	Single piece frame for transformer core/coil assembly A one-piece frame is provided for a core/coil assembly of a transformer. The frame includes a first wall, a second wall integral with the first wall, a third wall integral with the second wall and in opposing relation to the first wall, and a fourth wall integral with the third wall and in opposing relation to the second wall. Mounting structure secures the fourth wall to the first wall. The walls define a generally rectangular enclosure having open sides communicating with an interior space. The interior space is constructed and arranged to house at least a portion of a core/coil assembly of a transformer.
US09287028B2	Alloy composition, Fe-based nano-crystalline alloy and forming method of the same An alloy composition of Fe(100-X-Y-Z)BXPYCuz, where 4≦X≦14 atomic %, 0
US09287026B2	Magnetic material and coil component An object is to provide a magnetic material and coil component offering improved magnetic permeability and insulation resistance, while also offering improved high-temperature load, moisture resistance, water absorbency, and other reliability characteristics at the same time. A magnetic material that has multiple metal grains constituted by Fe—Si-M soft magnetic alloy (where M is a metal element that oxidizes more easily than Fe), as well as oxide film constituted by an oxide of the soft magnetic alloy and formed on the surface of the metal grains, wherein the magnetic material has bonding parts where adjacent metal grains are bonded together via the oxide film formed on their surface, as well as bonding parts where metal grains are directly bonded together in areas having no oxide film, and resin material is filled in at least some of the voids generating as a result of accumulation of the metal grains.
US09287023B2	Electrically conductive nanocomposite material An electromagnetically active composite has an electrically-nonconductive host matrix and electrically-conductive nanostrand bodies embedded in a substantially uniform distribution throughout the host matrix. Each of the nanostrand bodies comprises a volume containing at least one nanostrand of filamentary metal. Adjacent nanostrand bodies that are sufficiently mutually proximate will interact electromagnetically with each other. The filamentary metal of the one or more nanostrands in each of the nanostrand bodies occupies a deminimus fraction of the overall volume occupied by the at least one nanostrand that comprises each of the nanostrand bodies. The filamentary metal is chosen from among the group of metals that includes nickel, nickel aluminides, iron, iron aluminides, alloys of nickel and iron, and alloys of nickel and copper. Individual nanostrands of the nanostrand bodies have an average diameter in a range of from about 10 nanometers to about 4000 nanometers, and the average diameter of the nanostrand bodies is in a range of from about one micron to about 3000 microns.
US09287018B2	Method of preparing silver-based electrical contact materials with fiber-like arrangement of reinforcing nanoparticles A method for preparing silver-based electrical contact materials with fiber-like arrangement of reinforcing nanoparticles includes (1) uniformly mixing reinforcement powders and silver matrix powders for ball milling; (2) pouring the obtained composite powders and silver matrix powders into a powder mixing machine for powder mixing; (3) cold isostatic pressing; (4) sintering; (5) hot pressing; and (6) hot extruding to obtain silver-based electrical contact materials with fiber-like arrangement of reinforcing nanoparticles. The method of the present invention can obtain silver-based electrical contact materials with fiber-like arrangement of reinforcing nanoparticles with no specific requirement on processing deformation, and the plasticity and ductility of the reinforcing phase. Furthermore, it has simple processes, low cost and no particular requirements on the equipment. Contact materials prepared by the present method have good resistance to welding and arc erosion, conductivity and a greatly enhanced processing performance.
US09287015B2	Method and device for producing two different radioactive isotopes A method is provided for producing first and second radioactive isotopes using an accelerated particle beam that is directed to a first material and the first radioactive isotope is produced by a first nuclear reaction based on the interaction of the particle beam with the first material, said particle beam is also slowed down and subsequently directed to a second material, and the second radioactive isotope is produced by a second nuclear reaction based on the interaction of the particle beam with the second material. The effective cross-section for the induction of the first nuclear reaction at a first peak for a first particle energy is higher than an effective cross-section for the induction of the second nuclear reaction at a second peak for a second particle energy. A corresponding device includes an acceleration unit, a first exposure target having the first material and a second exposure target having the second material.
US09287009B2	Repair circuit and fuse circuit A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.
US09287002B2	Bootstrap sampling circuit with accurately averaging pre-charge circuit A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal. The switch controller may include a pre-charge circuit that pre-charges the control input to the electronic sampling switch prior to each commencement of the sample state to approximately the average of the voltage of the input signal and the voltage on the sampling capacitance immediately prior to each commencement of the sample state. The amount of the pre-charging may be substantially independent of the voltage of the input signal.
US09287001B2	Shift register circuit A shift register circuit includes a first pull-down control circuit, a first pull-down circuit electrically connecting to the first pull-down control circuit, a first inversed pulse signal coupling circuit outputting a first inversed pulse signal, a first pull-up circuit outputting a first gate control signal, and a first main pull-down circuit electrically connecting to the first pull-up circuit. The first pull-up circuit receives a first driving signal and a first pulse signal to output the first gate control signal. The first inversed pulse signal coupling circuit duly outputs the first inversed pulse signal to compensate a surge occurring in the first driving signal.
US09286996B2	Non-volatile memory system and method of programming the same A non-volatile memory system includes a first non-volatile memory device, a second non-volatile memory device that performs a write operation more slowly than the first non-volatile memory device, where the first and second non-volatile memory devices are different types of non-volatile memory devices, and a controller that controls the first and second non-volatile memory devices to concurrently perform the write operation for data input from a host based on a write command signal and that outputs a write completion signal to the host when one of the first and second non-volatile memory devices completes the write operation.
US09286992B2	Refresh apparatus and electronic device that ensure simplified refresh process of flash memory A refresh apparatus includes a flash memory and a refreshing unit. The flash memory includes a plurality of blocks, the plurality of blocks storing data. The refreshing unit sequentially refreshes the plurality of blocks in units of blocks. The refreshing unit includes a reading unit, a data deleting unit, and a data writing unit. The reading unit performs batch reading of data from the plurality of blocks. The data deleting unit deletes data stored in a target block for the refresh during the refresh in units of blocks. The data writing unit writes data corresponding to the deleted data among the plurality of read data to the target block so as to complete the refresh in units of blocks.
US09286991B1	Multi-chip non-volatile semiconductor memory package including heater and sensor elements A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.
US09286990B1	Storage device, nonvolatile memory and method operating same A method of operating a storage device includes; counting a number of fast cycles for the memory block when a program interval between two successive program operations directed to memory cells of the memory block is less than a minimal program interval, and/or when an erase interval between two successive erase operations directed to the memory block is less than a minimal erase interval, and selecting the memory block to be erased by an erase operation or selecting memory cells of the memory block to be programmed by a program operation in response to the counted number of fast cycles for the memory block.
US09286989B2	Partial block erase for a three dimensional (3D) memory A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.
US09286987B1	Controlling pass voltages to minimize program disturb in charge-trapping memory Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.
US09286986B2	Data writing method, and memory control circuit unit and memory storage apparatus using the same A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and detecting an operating temperature of the memory storage apparatus. The method further includes adjusting at least one predetermined operation parameter corresponding to the rewritable non-volatile memory module to generate at least one adjusted operation parameter corresponding to the rewritable non-volatile memory module and writing the data into the memory cell based on the at least one adjusted operation parameter if the operating temperature of the memory storage apparatus is larger than a predetermined temperature. Accordingly, the method can accurately store data into the rewritable non-volatile memory module, thereby lowing the operating temperature of the memory storage apparatus.
US09286985B2	Semiconductor device with power mode transitioning operation According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received.
US09286983B2	Memory string and semiconductor device including the same A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.
US09286981B2	Semiconductor device and method for operating the same A semiconductor device comprises a memory block having a content addressable memory (CAM) cell array storing data for internal operation conditions, and a memory cell array. The semiconductor device also comprises a page buffer to program data in the memory block or read the data programmed in the memory block; a control logic to activate a reset enable signal for initializing the page buffer during a reset operation and output the activated reset enable signal; and a power-supply controller to output a reset control signal for initializing the page buffer when the reset enable signal is activated, and provide a page buffer power-supply signal to the page buffer. The power-supply controller provides the page buffer power-supply signal after initialization of the page buffer.
US09286979B2	Method and structure for resistive switching random access memory with high reliable and high density The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.
US09286978B2	Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.
US09286976B2	Apparatuses and methods for detecting write completion for resistive memory Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.
US09286975B2	Mitigating read disturb in a cross-point memory The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
US09286974B2	Memory devices A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.
US09286973B2	Device and method for forming resistive random access memory cell A device and method for forming resistive random access memory cell are provided. The method includes: providing a first voltage to a first word line connected to a first RRAM cell to form the first RRAM cell; and providing a negative voltage to a second word line connected to a second RRAM cell that shares a first source line and a first bit line with the first RRAM cell. An exemplary device includes: a first RRAM cell, a second RRAM cell, a first voltage source and a charge pump circuit. The first RRAM cell is connected to a first word line. The second RRAM cell is connected to a second word line. The first voltage source provides a first voltage to the first word line to form the first RRAM cell. The charge pump circuit provides a negative voltage to the second word line.
US09286965B2	Memory refresh method and devices The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
US09286963B2	Method of writing to a spin torque magnetic random access memory Circuitry and a method provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a pulse of opposite polarity associated with a write pulse. The pulse of opposite polarity may comprise equal or less width and amplitude than that of the write pulse, may be applied with each write pulse or a series of write pulses, and may be applied prior to or subsequent to the write pulse.
US09286962B2	Magnetic memory system and methods in various modes of operation A magnetic memory system includes a superconductor circuit and one or more magnetic memory elements to store data. To write data, a driver circuit in the superconductor circuit generates a magnetic signal for transmission over a superconductor link extending between the superconductor circuit and the magnetic memory element. To read data, a sensing circuit in the superconductor circuit monitors a superconductor link extending from sensing circuit to the magnetic memory element. The magnetic memory element can be a spin-transfer type magnetic memory element.
US09286961B1	Memory controller half-clock delay adjustment A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.
US09286959B2	Low latency memory access control for non-volatile memories A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
US09286958B2	Memory with termination circuit Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
US09286952B2	SRAM with two-level voltage regulator A programmable logic device (PLD) is provided with a two-level voltage regulator for powering SRAM cells within the device. In one example, a PLD includes a plurality of static random access memory (SRAM) cells configured to store a configuration for the programmable logic device. The PLD also includes a two-level voltage regulator configured to selectively charge a first power supply node to a reduced voltage and to an enhanced voltage that is greater than the reduced voltage. The SRAM cells are powered through a coupling to the first power supply node. The PLD also includes a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during a write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device.
US09286949B2	Semiconductor memory A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair, in which the sense amplifier has precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors having a diffusion layer formed integrally with the diffusion layer of the precharging transistors for selectively connecting the plurality of bit line pairs to a common bus line.
US09286946B2	Voice recording and playback device, and control method for voice recording and playback device A voice recording and playback device of the present invention is capable of storage management of generated voice data, to which date information has been attached, as voice files, and comprises a display section capable of calendar display, and a control section for, at the time of retrieving voice files from a storage section, performing movable identification on a calendar display, as well as retrieving voice files that have been stored in the storage section based on date information attached to the files, and performing display of results of this retrieval indicating the existence of voice files close to day display on the calendar display, wherein the control section moves the identification position based on an instruction operation by the retrieval instructions section, and generates a notification in accordance with voice files that exist on the date of the identification position that has been moved.
US09286943B2	Enhancing karaoke systems utilizing audience sentiment feedback and audio watermarking A digital audio/video (A/V) content can be selected from a data store within a computing device. The content can include a vocal free recording and a subsequently recorded vocal track generated by a user. A digital marker can be embedded into the audio signal of the content. The marker can be associated with a time index of the content and a unique user identity associated with a device. A different A/V content can be identified and can be linked to the marker. The different A/V content can be at a symbol, a shape, an audio, a video, and/or a text content. In one embodiment, facial gesture and/or motion gesture feedback of a consumer can be captured during playback of the digital A/V content. In the embodiment, analysis of the feedback can be utilized to generate recommendations for improvement of A/V digital content and/or status updates.
US09286940B1	Video editing with connected high-resolution video camera and video cloud server An apparatus having a server is disclosed. The server may be configured to (i) receive via a network a first clip of video generated by a camera, (ii) receive via the network first information to edit the first clip, (iii) receive via the network one or more segments of a second clip of video generated by the camera as identified by the first information and (iv) create a third clip of video by editing the segments according to the first information. The second clip is generally a higher resolution version of the first clip. The third clip may have the higher resolution.
US09286927B1	Data storage device demodulating servo burst by computing slope of intermediate integration points A data storage device is disclosed comprising a head actuated over a disk surface comprising tracks defined by servo sectors, wherein each servo sector comprises at least one servo burst comprising a periodic pattern. The servo burst of one of the servo sectors is read to generate a read signal, and M intermediate integration points yNi are computed according to: y N i = ∑ k = 0 N i ⁢ r ⁡ ( k ⁢ ⁢ T s ) · sin ⁡ ( ω ⁢ ⁢ k ⁢ ⁢ T s ) ; i = 0 , 1 , … ⁢ , M - 1 where r(kTs) represents a sample point of the read signal, Ts represents a sample interval between the sample points, and ω represents a frequency of the periodic pattern in the servo burst.
US09286923B2	Low translational load suspension assembly Implementations described and claimed herein address the foregoing problems by providing a suspension assembly used in a storage device to support a transducer head, wherein the suspension assembly comprises a base plate for attaching to an actuator arm and a moving portion movably attached to the base plate. The base plate is fixed and/or clamped to the actuator arm and the moving portion adapted to rotate about a center of rotation. The moving portion is adapted to have a center of mass of its moving mass substantially close to its center of rotation. In one implementation, a counter-weight is attached to the moving portion to move the center of mass of its moving mass substantially close to its center of rotation to minimize inertial loads to the system during suspension actuation.
US09286919B1	Magnetic writer having a dual side gap A magnetic transducer has air-bearing surface (ABS) and includes a main pole, at least one coil, a side shield and a side gap. The coil(s) energize the main pole. A portion of the main pole resides at the ABS. The side gap is between the main pole and the side shield. The side gap is nonmagnetic and includes a first side gap and a second side gap. The first side gap is conformal with the main pole. The second side gap is conformal with the main pole. The first side gap is between the second side gap and the ABS. The second side gap is wider than the first side gap.
US09286917B1	Write pole formed with evaporation deposition A write pole may be formed by first depositing a dielectric layer onto a substrate and then patterning the dielectric layer to form a trench with a write pole shape. The trench is subsequently filled with the evaporation deposition of a magnetic material to form a write pole. The trench may have a greater depth dimension than width dimension.
US09286916B1	High frequency data writer field generator device A data writing device may be constructed and operated with at least a data writer that has at least a write pole and a magnetic feature. A controller may selectively activate the magnetic feature to magnetically oscillate and produce a radio frequency signal proximal the write pole on an air bearing surface (ABS).
US09286905B2	Frame erasure concealment for a multi-rate speech and audio codec An audio coding terminal and method is provided. The terminal includes a coding mode setting unit to set an operation mode, from plural operation modes, for input audio coding by a codec, configured to code the input audio based on the set operation mode such that when the set operation mode is a high frame erasure rate (FER) mode the codec codes a current frame of the input audio according to a select frame erasure concealment (FEC) mode of one or more FEC modes. Upon the setting of the operation mode to be the High FER mode, the one FEC mode is selected, from the one or more FEC modes predetermined for the High FER mode, to control the codec by incorporating of redundancy within a coding of the input audio or as separate redundancy information separate from the coded input audio according to the selected one FEC mode.
US09286904B2	Adjusting a data rate of a digital audio stream based on dynamically determined audio playback system capabilities A computing device may be configured to output a digital audio stream to an audio playback system for rendering as sound over speakers. The sound may be sampled. Based at least in part on a quality of the sampled sound, the data rate of the digital audio stream may be reduced by reducing a sampling rate and/or by reducing a number of bits per sample. A reduced sampling rate may be determined based on a computed maximum sampling rate of the audio playback system, and/or a reduced number of bits per sample may be determined based on a computed maximum number of bits per sample of the audio playback system. The maximum usable sampling rate and maximum usable number of bits per sample may be determined based on an upper usable frequency within a frequency spectrum of the sampled sound.
US09286903B2	Methods and apparatus for embedding codes in compressed audio data streams Example methods disclosed herein to embed a watermark in a compressed audio stream include accessing a first scale factor and a first set of mantissas for a first set of transform coefficients included in the compressed audio stream, the first set of transform coefficients corresponding to a first band of a compression standard. Such disclosed example methods also include quantizing a second set of transform coefficients based on a second scale factor corresponding to the first scale factor reduced by a unit of resolution to determine a second set of mantissas, the second set of transform coefficients corresponding to the first band of the compression standard and including the watermark. Such disclosed example methods further include replacing the first scale factor with the second scale factor and the first set of mantissas with the second set of mantissas to embed the watermark in the compressed audio stream.
US09286901B1	Communication using sound Communicating using sound includes choosing a musical genre, encoding data by selecting musical chords from a chord alphabet, where different musical chords from the chord alphabet represent different symbols from the data alphabet decodable by a receiver and wherein musical chords that are used for the chord alphabet are provided according to the musical genre that is chosen, constructing a tune using the musical chords selected in connection with encoding data, and playing the tune to a receiver. A transmitter may play the tune to the receiver and one of: the receiver and the transmitter may be a mobile device. A receiver may require authentication to decode received data. Constructing the tune may include adding filler chords that do not encode any data and cause the tune to be more aesthetically pleasing.
US09286899B1	User authentication for devices using voice input or audio signatures Techniques for authenticating users at devices that interact with the users via voice input. For instance, the described techniques may allow a voice-input device to safely verify the identity of a user by engaging in a back-and-forth conversation. The device or another device coupled thereto may then verify the accuracy of the responses from the user during the conversation, as well as compare an audio signature associated with the user's responses to a pre-stored audio signature associated with the user. By utilizing multiple checks, the described techniques are able to accurately and safely authenticate the user based solely on an audible conversation between the user and the voice-input device.
US09286898B2	Methods and apparatuses for providing tangible control of sound Methods and apparatuses for providing tangible control of sound are provided and described as embodied in a system that includes a sound transducer array along with a touch surface-enabled display table. The array may include a group of transducers (multiple speakers and/or microphones) configured to perform spatial processing of signals for the group of transducers so that sound rendering (in configurations where the array includes multiple speakers), or sound pick-up (in configurations where the array includes multiple microphones), have spatial patterns (or sound projection patterns) that are focused in certain directions while reducing disturbances from other directions. Users may directly adjust parameters related to sound projection patterns by interacting with the touch surface while receiving visual feedback by exercising one or more commands on the touch surface. The commands may be adjusted according to visual feedback received from the change of the display on the touch surface.
US09286893B2	Pre-processed annotation of street grammar in speech enabled navigation systems Embodiments of the present invention address deficiencies of the art in respect to virtualization and provide a novel and non-obvious method, system and computer program product for annotation of street grammar in speech enabled navigation devices. In an embodiment of the invention, a pre-processing street grammar annotation system can be provided. The system can include an annotated street grammar storage that contains street root names wherein each street root name has more than one street suffix associated with said street root name, and a street annotation pre-processor wherein the street annotation pre-processor contains logic enabled to annotate a set of street suffixes to a street root name prior to processing a voice input in a speech enabled navigation device, wherein the street root name has more than one street suffix associated with said street root name.
US09286891B2	Automaton determinization method, device, and computer program product involving deleting states In an embodiment, an automaton determinization method includes: state-generating, first-transition-generating, second-transition-generating, and first-deleting. The state-generating includes generating, assigned with a first symbol, a second state newly. The first-transition-generating includes generating a second transition that leaves from the first state and enters to the second state and that is assigned with the first symbol. The second-transition-generating includes generating, regarding the first transitions, a fourth transition where a state previous to a third transition is substituted with the second state. The third transition is an outgoing transition from a next state of the first transition. The first-deleting includes deleting states that are next to the first transitions where the fourth transitions are generated and that do not have incoming transitions other than the first transitions, deleting outgoing transitions from the deleted states, and deleting the first transitions where the fourth transitions are generated.
US09286889B2	Improving voice communication over a network Systems and methods for improving communication over a network are provided. A system for improving communication over a network, comprises a detection module capable of detecting data indicating a problem with a communication between at least two participants communicating via communication devices over the network, a management module capable of analyzing the data to determine whether a participant is dissatisfied with the communication, wherein the management module includes a determining module capable of determining that the participant is dissatisfied, and identifying an event causing the dissatisfaction, and a resolution module capable of providing a solution for eliminating the problem.
US09286888B1	Speech recognition system and speech recognition method A speech recognition system includes: a context storage medium storing a monosyllabic command context including a plurality of monosyllabic commands and storing a polysyllabic command context including a plurality of polysyllabic commands; a speech segment detector detecting a speech segment having a start point and an end point by analyzing a speech signal within the speech segment; a syllable determiner configured determining whether the speech signal corresponds to a monosyllabic form or a polysyllabic form; a feature vector extractor extracting a feature vector by analyzing the speech signal; and a speech recognizer selecting one of the monosyllabic command context and the polysyllabic command context according to the determination of whether the speech signal corresponds to the monosyllabic form or the polysyllabic form and recognizing at least one command in the selected one of the monosyllabic command context and the polysyllabic command context based on the extracted feature vector.
US09286880B2	Masking sound outputting device and masking sound outputting method A masking sound outputting device includes: an inputting unit which receives a picked-up sound signal relating to a picked-up sound; an extracting unit which extracts an acoustic feature amount of the picked-up sound signal; an instruction receiving unit which receives instructions for starting an output of a masking sound; and an outputting unit which, in the case where the instruction receiving unit receives the instructions for starting an output, outputs a masking sound corresponding to the acoustic feature amount extracted by the extracting unit.
US09286875B1	Electronic percussion instrument An electronic percussion instrument includes a chair having a seat, a first arm disposed on one side of the seat, and a second arm disposed on an opposite side of the seat. A set of piezoelectric triggers is arrayed along each of the first and second arms and the triggers are positioned to be struck by the thumbs of a percussionist while sitting on the seat of the chair. The triggers are connected to an electronic drum machine. Sequential striking of the triggers with the thumbs of a percussionist sitting in the chair causes corresponding percussion sounds to be played by the electronic drum machine. Additional triggers are disposed on the floor and can be struck with the feet of the percussionist to produce additional percussion sounds. Thus, drum rhythms can be played easily and naturally while sitting in the chair.
US09286873B2	Vibration sensor device for musical instruments The present invention relates to a sensor device (2) for measuring a movement and/or a vibration of at least one object of interest, in particular for musical instruments, said device comprising (i) at least two excitation inductance coils (11, 12) electrically connected to at least one electric excitation source, and capable of generating excitation magnetic fluxes, and (ii) at least one measuring inductance coil (13), electrically connected to electrical measuring means capable of measuring induced electrical signals, (iii) a magnetic circuit (10) magnetically connecting the excitation coils (11, 12) and measuring (13) coils, and comprising a measuring area (17) wherein the presence of objects of interest affects magnetic fluxes coming from excitation coils (11, 12) and passing through said measuring coil or coils (13), and (iv) excitation coils (11, 12) arranged in such a way as to generate, in the absence of an object of interest in the measuring area (17), magnetic fluxes which substantially cancel each other out in the at least one measuring coil (13). The invention also relates to a sound system implementing said device.
US09286870B2	Pedal device for electronic percussion instrument A pedal device for an electronic percussion instrument, including: a base; a foot board pivotable in a pivotable range between lower and upper limit positions; and an elastically holding mechanism for holding the foot board such that the foot board keeps an equilibrium state at an initial position within the pivotable range, the foot board being configured such that (a) when the foot board is located between the initial and the upper limit positions, it is given by the mechanism a return force having a linear characteristic with respect to a change of its pivot angle, the return force being for permitting the foot board to return to the initial position, and (b) when the foot board is located between the initial and the lower limit positions or between: an intermediate position and the lower limit position, the foot board is given the return force having a nonlinear characteristic.
US09286869B2	Media system with playing component This document describes a device for receiving and displaying graphical representations of digital music tracks and their components (in the form of digital interactive phrases, or “DIPs”). The device allows a user to play the music tracks using a new format, blend, mix or mash different music tracks together, via a digital interactive phrase process, and produce and listen to the blended, mixed or mashed digital music.
US09286868B2	Decorative drum pad and cymbal cover A decorative drum pad and cymbal cover that includes a back plate with a back side and a top side, the back plate is secured in position by a cymbal or drum stand and a mounting, the mounting removably secures the back plate to the cymbal stand and an image holding area placed on the top side of the back plate. The decorative drum pad and cymbal cover also includes a protective cover placed on top of the image holding area, the protective cover protects the image holding area from a plurality of drumstick strikes from a user and an drum trigger that includes a back side and an electrical signal outlet jack, the electrical signal outlet jack is attached to the back side of the back plate with one or more fasteners and the electrical signal outlet jack is disposed on the back side of the drum trigger.
US09286866B2	Drum and method for tuning and making a drum A drum having a vibratory member(s) tensioned over a plurality of tuned staves which acts as a sounding board and having staves which may be joined together with one or more flexible lines. The invention also includes a method of making such a drum and includes variations in the bearing edges of the tuned staves for such a drum.
US09286856B2	Display device including a white sub-pixel and method of driving the same A display device is disclosed. The display device has pixels which include three color sub-pixels, for example, red, green, and blue sub-pixels. The pixels also include a white sub-pixel. The display calculates data for the red, green, blue, and white sub-pixels based on data for red, green, and blue sub-pixels.
US09286847B2	Repairable GOA circuit and display device for flat panel display The present invention discloses a repairable GOA circuit and a display device for flat panel display. The repairable GOA circuit for flat panel display comprises multiple GOA units cascaded with each other, charging an n-th level horizontal scanning line in the display region according to the n-th level GOA unit, both ends of the n-th level horizontal scanning line being connected with one said n-th level GOA unit. The n-th level GOA unit comprises a pull-up circuit, a pull-down circuit, a pull-down holding circuit, a pull-up control circuit, a boost strap capacitor, and a first thin film transistor. The gate of the first thin film transistor inputting a level clock signal CK, the drain and the source thereof being respectively connected with the gate signal point and the n-th level horizontal scanning line. When the n-th level GOA unit is working normally, at least one of the drain and the source of the first thin film transistor keeps disconnected with the n-th level GOA unit. The present invention further provides a corresponding display device. The repairable GOA circuit for flat panel display according to the present invention makes the GOA circuit have a certain repair ability, which improves the yield of the GOA display panel.
US09286844B2	LC panel having switch unit, and LCD device having switch unit A liquid crystal panel includes a plurality of thin film transistors (TFTs), scan lines, data lines, a scan driving chip, and a data driving chip. The scan driving chip includes a compensation driving unit coupled to the scan lines. The compensation driving unit drives the TFTs corresponding to a next-row of scan line to turn on when the scan driving chip drives the TFTs corresponding to a current-row of scan line to turn on or after the scan driving chip drives the TFTs corresponding to the current-row of scan line to turn on. The compensation driving unit drives the TFTs corresponding to the next-row of scan line to turn off when the TFTs corresponding to the current-row of scan line receive a data signal of the data driving chip or before the TFTs corresponding to the current-row of scan line receive the data signal of the data driving chip.
US09286842B2	Liquid crystal display device A liquid crystal display device which includes a plurality of OCB liquid crystal pixels arrayed substantially in a matrix, and a driver circuit which cyclically writes a non-video signal and a video signal as a pixel voltage in each of the liquid crystal pixels. The liquid crystal display device further includes a control circuit which sets a first period and a second period different in length from the first period such that a total time length of the first period and the second period does not exceed one frame period, and controls the driver circuit to execute write of the non-video signal for the liquid crystal pixels in the first period and to execute write of the video signal for the liquid crystal pixels PX in the second period.
US09286839B2	Image processor, image processing method, image encoder, image encoding method, and image display device In the image processors and the image processing methods of the present invention, the number of bits for quantizing image data is adjusted on the basis of a dynamic range of each block. Therefore, the error introduced by encoding is reduced without increasing the data amount of the encoded image data, and the response speed of a liquid crystal can be controlled appropriately by preventing unnecessary voltages from being applied due to the error introduced by encoding.
US09286837B2	Display device and driving method thereof A display device includes: a display panel configured with rows of pixels, each row pixels including a first color pixel, a second color pixel, and a third color pixel; and a backlight assembly configured to supply light to the display panel, in which: a data signal is alternately applied to a first color pixel disposed in an odd row on an odd frame, and to another first color pixel disposed in an even row on an even frame, a data signal is alternately applied to a second color pixel disposed in the odd row on the odd frame, and to another second color pixel disposed in the even row on the even frame, a data signal is applied to a third color pixel on both frames, and colors of light supplied to the display panel on the odd frame and the even frame are different from each other.
US09286836B2	Image processing method, image output apparatus, and display apparatus An image processing method applies color conversion to an input image and outputs the image. The method includes the steps of: acquiring profile information concerning display characteristics of a display apparatus including a backlight unit, a control unit configured to control a light emission amount of the backlight unit, and a display panel configured to modulate light from the backlight unit, the display characteristics being changed according to the light emission amount of the backlight unit; color converting the input image into an image in a color space of the display apparatus by using the acquired profile information in the acquiring; and outputting the image being subjected to the color conversion.
US09286833B2	Buffer circuit, scanning circuit, display device, and electronic equipment A buffer circuit includes a first transistor circuit having a first conductivity type transistor, a second transistor circuit having a second conductivity type transistors, in which the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively, in which at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and in which wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is included to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.
US09286832B2	Organic light-emitting display An organic light-emitting display apparatus includes pixels at an active area, dummy pixels at a dummy area, and repair lines coupled to the plurality of dummy pixels and connectable with the plurality of pixels. Each of the plurality of dummy pixels includes: an output node coupled to a repair line corresponding to the dummy pixel from among the plurality of repair lines, a dummy circuit including a dummy driving transistor that is coupled between a driving voltage line to which a first driving voltage is applied and the output node, and a dummy initialization circuit including a dummy anode initialization transistor coupled between a dummy initialization voltage line to which a dummy initialization voltage is applied and the output node via a connectable structure. The connectable structure includes a first conductor and a second conductor that overlap, at least partially, with each other and are electrically insulated from each other.
US09286831B2	AC drive circuit for OLED, drive method and display apparatus An AC drive circuit for OLED comprises a light emitting control unit, a charging control unit, a drive unit, a storage unit, a first voltage signal input terminal, a second voltage signal input terminal and a third voltage signal input terminal. The AC drive circuit enables that the current flowing in an OLED is independent of the internal resistance of the circuit, thus the brightness of the OLED will not be influenced by the internal resistance of the circuit. Meanwhile, the AC drive circuit compensates the threshold voltage of the drive transistor, thus the influence of the threshold voltage of the drive transistor on the current of the OLED for emitting light is eliminated. In addition, the AC drive circuit reversely biases the OLED, thereby the un-recombined carriers accumulated at the light emitting interface inside the OLED and the built-in electrical field formed by these carriers are eliminated.
US09286829B2	Display device A display device includes a display panel including a display area, in which pixels are arranged, and a non-display area, a driving circuit on the non-display area of the display panel, the driving circuit being configured to drive the pixels and including a memory cell, and a delay circuit on the non-display area of the display panel, the delay circuit being connected to the memory cell of the driving circuit and being configured to delay a signal input to the memory cell of the driving circuit.
US09286827B2	Organic light emitting display apparatus and method of operating the same An organic light emitting display (OLED) apparatus including a power driver for applying a driving voltage to a display panel, a driver driving unit for applying a driving signal to the power driver, and a processor for applying a display data signal, which corresponds to a value of data displayed on the display panel, to the power driver. The power driver is configured to apply the driving voltage to the display panel when the driving signal and display data signal are each in an active state.
US09286813B2	Composite street sign with integral electrical wiring A street sign fabricated from a composite material having at least on panel for displaying indicia such as street names. Electrical conductors may be embedded into the panel to permit attachment and electrical coupling of lights and other electrical devices thereto. A battery may be installed in a hollow post supporting the panel to provide power to the electrical devices. The battery can be recharged using a solar panel mounted proximate the top of the sign.
US09286812B2	Flexible display extendable assembly In embodiments of a flexible display extendible assembly, an extendible assembly includes a slideable display guide integrated in a first housing part of an extendible electronic device. The extendible electronic device includes a flexible display that slide-engages into the first housing part of the extendible electronic device. The extendible assembly includes an extendible mechanism that is coupled in a second housing part of the extendible electronic device and to the slideable display guide. The first and second housing parts of the extendible electronic device slide-engage relative to each other. The extendible mechanism is implemented to extend as the first and second housing parts slide apart relative to each other, and also to retract as the first and second housing parts slide together relative to each other.
US09286807B2	Collision avoidance system and a method for determining an escape manoeuvre trajectory for collision avoidance A collision avoidance system including a receiver configured to receive navigational data regarding intruding aerial vehicle and own aircraft. Storage is configured to store a plurality of predefined escape trajectories. A processor is configured to compare at least a subset of the predefined escape trajectories with a presumed trajectory of the intruding aerial vehicle and to select one of the predefined escape trajectories based on the comparison. The predefined escape trajectories are pre-simulated, wherein each escape trajectory is associated to a set of navigational data and to an escape maneuver direction.
US09286805B2	Lane departure warning system, lane identification apparatus and related method thereof The present invention provides a lane departure warning system including an image sensing device, an identification module and a determination module. The image sensing device generates a video. The identification module identifies a plurality of lane lines of at least one lane on which a vehicle is currently driven from the video, to generate an identification result, wherein the identification result is generated based on specific borderlines of the lane lines. The determination module determines a determination strategy according to vehicle speed information, and generates a determination result according to the determination strategy and the identification result. The lane departure warning system determines whether to issue a warning according to the determination result.
US09286800B2	Guidance assist vehicle module The automated lane management assist method, data structure and system receive unprocessed lane-specific limited-access highway information, including lane use and speed limits, from freeway transportation management centers or traffic management centers, process and convert the unprocessed information to a form that assists in the selection of driving lanes and target speeds for vehicles, and communicate the processed information to the vehicles by suitable means. The Guidance Assist Vehicle Module combines the processed information with information from the vehicle and the driver including the information on appropriate lane changes and speed commands to the vehicle.
US09286797B1	Traffic incident location identification A location for a traffic incident can be determined by a computer system, using data from a first and second sensor along a travel path. A receiving and sending symptom of the traffic incident are detected from a first and second sensor, using traffic flow data from the sensors. The locations of the first and second sensors are determined. The location and traffic flow data from each sensor are used to create a sending and receiving profiles. From the profiles, a convergence formula is build. Using the convergence formula and by determining a convergence point for the sending and receiving symptoms, a time and location of the traffic incident is identified.
US09286796B2	Traffic flow measuring apparatus and method, and computer-readable storage medium for judging size of vehicle depending on number of times reflected wave from vehicle is detected within detection time A traffic flow measuring apparatus includes a processor configured to judge a size of a vehicle, depending on a detection frequency or a non-detection frequency of a reflected wave from the vehicle with respect to a transmission wave transmitted from a radar apparatus, within a detection time of the reflected wave from the vehicle, set according to the detection of the reflected wave.
US09286791B2	Protection and security system including three-dimensional virtual reality A system of electronic devices for the detection and location of changes in a predetermined space for the protection and security of places, persons, and goods, including at least two general sensors and two data processing electronic devices connected to each other. One of the two data processing devices includes two electronic means. One of the electronic means reproduces with an appropriate fidelity the place to be monitored into a three-dimensional virtual reality. The second electronic means is capable of acquiring and storing security rules, receiving from the sensors and mapping their signals by correlating them according to criteria of coincidence in the virtual reality to identify events predetermined by the security rules as relevant for the activation of appropriate alarms or notifications.
US09286787B2	Signal strength-based routing of network traffic in a wireless communication system A low cost, robust, wireless sensor that provides an extended period of operability without maintenance is described. The wireless sensors are configured to communicate with a base unit or repeater. When the sensor unit detects an anomalous ambient condition (e.g., smoke, fire, water, etc.) the sensor communicates with the base unit and provides data regarding the anomalous condition. The sensor unit receives instructions to change operating parameters and/or control external devices.
US09286786B2	Surveillance systems and methods Surveillance systems and methods are described herein. Surveillance systems and methods can include detecting a number of interactions within a building, determining an event based on the number of interactions, and sending a message to a number of contacts relating to the event.
US09286785B2	Anti-theft device for intercom systems A module frame for bell system modules having a module locking means for locking modules, which are to be inserted, to the frame and having a locking canceling means for canceling locking during actuator excitation. In the process, provision is made for the locking canceling means to also exhibit actuator-independent permanent catch blocking which can be selectively activated.
US09286775B2	Monitoring camera and monitoring camera control method An image signal processing DSP subjects an image captured by an imaging element having a zoom lens to image processing for identifying a tracking target. In accordance with zoom information generated by the image signal processing DSP, the main CPU controls the zoom lens; and controls a turn table that moves the imaging element in panning and tilting directions in accordance with pan and tilt information, to track the tracking target. During tracking of the tracking target, a determination is made, from information about movements of the tracking target generated by the image signal processing DSP, as to whether or not the target to be tracked has intruded the inside of the area from the outside. In a case where the target has intruded the inside of a preset area from the outside, an alarm command is produced when the target continually remains in the area for; e.g., one second.
US09286769B2	Gaming system, gaming device and method for displaying multiple concurrent games using dynamic focal points The gaming system disclosed herein changes the focal point of a display device at different points in time to assist the player in focusing on different simultaneously or concurrently played games at different points in time. Specifically, the gaming system displays a plurality of simultaneously or concurrently played games on a display device. In response to a designated event occurring in association with a specific one of the plurality of simultaneously or concurrently played games, the gaming system changes the focal point of the display device to draw the player's focus or attention to that specific one of the simultaneously or concurrently played games. Put differently, the gaming system dynamically allocates and/or indicates different portions of a display device to different simultaneously or concurrently played games at different points in time to account for different events occurring in such simultaneously or concurrently played games.
US09286768B2	Gaming machine and method having feature game highlighting A gaming machine and method for displaying and highlighting a scatter symbol among a matrix of symbols. The display includes a first layer for displaying a background and a second layer overlying the first layer. The layers are virtual layers or discrete physical layers. The second layer displays the matrix of symbols including any scatter symbol included in the matrix of symbols. The second layer enables a gaming machine player to simultaneously view the background, or at least portions of the background. According to one aspect of the invention, the second layer is at least partially transmissive to permit simultaneous viewing of the background and the matrix of symbols. The background is changeable to highlight at least one of the symbols of the matrix of symbols. Preferably, the background highlights the scatter symbol by adding depth, color, light and imagery, such as a still, changing, or moving image.
US09286767B2	Challenging players in online game to compete in modular game Methods, systems, and computer programs are presented for allowing players to challenge other players in an online game to compete by playing a modular game within the online game. One method includes an operation for providing an interface to a first player for challenging a second player to compete in the modular game after detecting completion of the modular game by the first player. The modular game is played within an online game. Further, the method includes operations for sending a challenge to the second player, and for detecting that the second player completed the modular game in response to the challenge. The first player is rewarded a challenge award if the first player obtained a higher score than the second player in the modular game.
US09286761B2	System for trade-in bonus Embodiments of the present invention are directed to gaming systems that allow customers to wager, or “trade-in” an object of value or winning situation for a chance to win an even more valuable award. The chance for valuable award may be a bonus game or chance to win a bonus game. Bonus awards are “funded” by the savings achieved from the players trading in their wins in the base game, which would otherwise be paid. Players who do not trade-in see no changes from the base game paytable, while those players who participate in the trade-in bonus have a different gaming experience.
US09286758B2	Controlling progress in wagering games A wagering game system and its operations are described herein. In embodiments, the operations can include detecting that a non-wagering activity is performed separate from a wagering game. The operations can further include determining that a progression requirement for a persistent-state game is fulfilled via the non-wagering activity. The operations can further include, after determining that the progression requirement is fulfilled, performing one or more of unlocking wagering game content, setting a progression limit in the persistent-state game until wagering game activity is performed, and removing a progression limit in the persistent-state game that was set via wagering activity.
US09286755B2	Central player control for facilitation of gaming event re-creation For facilitating re-experience of an event of a gaming device with a player, upon verification, access is granted to the player to a data processing device. The data processing device is in communication with, yet external to, the gaming device, and the data processing device has been provided a sampling of data from the gaming device through a gaming system, the sampling of data associated with the event to be re-experienced by the player. Responsive to an input received from at least one of the player and an operator, at least one of construction, presentation, and delivery of a facsimile animation re-creation of the event is customized.
US09286752B2	Dynamic mapping of photo elements to a game Systems and methods receive digital images from online sources. The digital images are analyzed and various objects are recognized within the digital images. The recognized objects may be faces of persons appearing in the digital images. A subset of the digital images is selected according to selection rules applied to the recognized objects. The selected recognized objects are incorporated into a wagering game. For example, the recognized objects may be incorporated onto symbols of wagering game.
US09286744B2	Mechanical module and key A mechanical module, such as for a vehicle comprises a body having a first body part and a second body part, a printed board and a battery. The first and second body parts are fixed mechanically relative to one another. The printed board is permanently fixed to the first body part. The battery is positioned between the printed board and the second body part, and the body is designed such that the battery can be exchanged without giving access to a compartment of the body between the printed board and the first part of the body.
US09286743B2	Key storage and retrieval Methods and systems for providing key storage and retrieval services to be performed by a service provider. The service provider provides a template to a client and instructs the client to use the template to capture, for each vehicle of a plurality of vehicles, both a vehicle identifier and a key of the vehicle in an image. The service provider stores the image in a computing system, extracts the vehicle identifier from the stored image, and associates the vehicle identifier with a location identifier corresponding to a location where the key is stored. When the service provider receives from the client a request for retrieving a key for a specific vehicle, the service provider searches a vehicle identifier of the specific vehicle in the computing system, retrieves the requested key from the location associated with the vehicle identifier, and sends the requested key to the client.
US09286742B2	User authentication system and method A user authentication system and method are disclosed. The user authentication system includes an authentication device which can be donned and doffed by the user, a sensor to determine whether the authentication device is donned or doffed by the user, and an authentication server to receive information from the sensor and to authenticate the user based on whether the authentication device is donned by the user.
US09286735B1	Generating cumulative wear-based indicators for vehicular components Methods, systems, and computer program products for generating wear-based indicators for vehicular components are provided herein. A method includes assigning a failure class label to each data point, from multiple data points derived from measurements associated with a vehicular component across a fleet of vehicles, that is within a pre-specified number of runtime hours of a replacement; assigning a non-failure class label to each data point not within the pre-specified number of runtime hours of a replacement and each data point associated with a component yet to be replaced; estimating a failure probability at each data point over a pre-specified future runtime of the component based on the assigned class label; determining a cumulative hazard function for the vehicular component based on the failure probability; and generating a cumulative wear-based indicator for the vehicular component by executing a regression function at a given time based on the cumulative hazard function.
US09286733B2	Location based systems for entry and exit A system and methods using applications for entry and exit from registered locations, where a registered location has an associated geo-fence of any size or shape. A registered location may be mobile or stationary. An internet-connected device running an app transmits the current geographic location of the device, and a remote processing center executes a default action when finding correspondence between the geo-fence of a registered location and the current geographic information of an end user's device, and in one embodiment, the default action may be to enter and pay for parking at a registered location.
US09286729B2	Image mapping to provide visual geographic path Provided is a computer system and method for mapping a visual path. The method includes receiving one or more images included in a predefined area; receiving one or more parameters associated with the image; and integrating the images and parameters into a map of the predefined area to enable mapping the visual path through the predefined area in response to one or more input path parameters.
US09286727B2	System and method for presenting true product dimensions within an augmented real-world setting Methods, systems, computer-readable media, and apparatuses for presenting a representation of an augmented real-world setting are presented. In some embodiments, a method includes presenting a representation of an augmented real-world setting. The method includes capturing a plurality of images of a real-world setting. The method also includes analyzing one or more real-world objects within the plurality of images of the real-world setting. The method further includes receiving information pertaining to a real-world product, wherein the information is indicative of first physical dimensions of the real-world product during a first mode of operation and second physical dimensions of the real-world product during a second mode of operation and overlaying an augmented reality object depicting the real-world product during the first mode of operation, and having the first physical dimensions, within at least one of the plurality of images of the real-world setting, based at least in part on the analyzing step.
US09286726B2	Mobile information gateway for service provider cooperation A mobile information gateway comprises a wearable human interface module having an image delivery and display mechanism for presenting information overlaid upon a wide field of view, a computing and communication module adapted receive information from the human interface module and adapted to send commands and information to the human interface module including information for presentation; and a backend service server coupled for processing data from the computing and communication module including user identification and verification. The present invention also includes a method for using the mobile information gateway for augmented use by employees interacting in the back office of a financial services company and comprises capturing information with a first human interface module; processing the information captured by the first human interface module; retrieving a set of shared information based upon the processing of the information captured by the first human interface module; presenting the shared set of information overlaid upon a field of view of the first user using the first human interface module; and presenting the shared set of information overlaid upon a field of view of the second user using a second human interface module.
US09286723B2	Method and system of discretizing three-dimensional space and objects for two-dimensional representation of space and objects In one exemplary embodiment, a method includes obtaining a digital image of an object. A coordinate-space position of a digital camera is defined in relation to the digital object for the digital image. A coordinate-space region around the coordinate-space position is defined. The coordinate-space region is associated with the digital image based on the coordinate-space position defined for the digital image. A digital image of a room is obtained. A three-dimensional representation of the digital image of the room is created according to the coordinate system based on the positional information of another digital camera that obtained the digital image of the room. An object proxy is located in the three-dimensional representation of the digital image. A coordinate-space region of the room of the object proxy is mapped with a substantially matching coordinate-space region of the object. The digital image of the object associated with substantially matching coordinate-space region is overlaid onto the digital image of the room.
US09286721B2	Augmented reality system for product identification and promotion A system, method, and computer program product for automatically combining computer-generated imagery with real-world imagery in a portable electronic device by retrieving, manipulating, and sharing relevant stored videos, preferably in real time. A video is captured with a hand-held device and stored. Metadata including the camera's physical location and orientation is appended to a data stream, along with user input. The server analyzes the data stream and further annotates the metadata, producing a searchable library of videos and metadata. Later, when a camera user generates a new data stream, the linked server analyzes it, identifies relevant material from the library, retrieves the material and tagged information, adjusts it for proper orientation, then renders and superimposes it onto the current camera view so the user views an augmented reality.
US09286719B2	Automated detection of airway and vessel orientations for quantitative analysis and visualization A method including displaying a three-dimensional (3D) image of a lung, receiving a selection of an airway of the lung and displaying a two-dimensional (2D) cross-section image of the airway perpendicular to the airway's long axis, wherein the display of the 2D cross-section image occurs almost immediately after the selection of the airway is received.
US09286715B2	Systems and methods for adjusting a virtual try-on According to at least one embodiment, a computer-implemented method for generating a virtual try-on is described. A first model is obtained. The first model includes a first set of attachment points. A second model is obtained. The second model includes a first set of connection points. The first model and the second model are combined. Combining the first and second models includes matching the first set of attachment points with the first set of connection points. An image is rendered based on at least a portion of the combined first and second models.
US09286714B2	Apparatus and method for processing graphics primitives A method and apparatus includes primitive setup circuitry for determining a plurality of functions for an input graphics primitive, including an edge function associated with each edge of the input graphics primitive and a depth function associated with the input graphics primitive. Rasterization circuitry performs a rasterization operation in order to calculate position data for a plurality of graphics fragments to be used to represent the input graphics primitive. In a default mode of operation, depth bound clipping circuitry performs a depth bound clipping operation by determining, for each graphics fragment in said plurality of graphics fragments, a depth value for said graphics fragment using the depth function, and determining whether said depth value resides within a valid depth range of a view frustum, the graphics fragment being discarded from further processing if its depth value does not reside within said valid depth range.
US09286705B1	Presenting wireless-telecommunications coverage areas Systems, methods, and computer-readable media for displaying an area of wireless-telecommunications coverage of a geographic region by a plurality of images is provided. In embodiments, an image representing an amount of wireless-telecommunications coverage for a geographic region is referenced. A plurality of image data points, including corners, is mapped to real-world geographic coordinates to create a registered image. A plurality of colors, each representing a different wireless-telecommunications coverage area, is identified. A second image is created that includes only pixels associated with selected colors and, thus, only represents the wireless-telecommunications coverage areas associated with the selected colors.
US09286704B2	Graphical user interface for efficiently visualizing multiple messages of different severities in a tabular format A technique is provided for a graphical user interface on a computer. The technique includes receiving messages individually corresponding to resources being monitored, displaying rows in a table, and generating bar graphs of the messages respectively corresponding to the resources in the rows. Each of the bar graphs displays a color coded scheme to visually distinguish severity of the messages in each of the rows for the resources. The bar graphs display the severity of the messages for one resource per the given row without requiring user intervention to view severities of the messages displayed by the color coded scheme, without requiring user intervention to view a total number of messages for the given row, while maintaining a same row height regardless of the total number of messages for the given row, and without changing a table size including a table height and a table width of the table.
US09286701B1	Method and apparatus for estimating scatter in a positron emission tomography scan at multiple bed positions A method is provided for estimating scatter in a positron emission tomography (PET) scan at multiple bed positions, the method comprising calculating a first scatter sinogram based on scatter data obtained at a first bed position, calculating a second scatter sinogram based on scatter data obtained at a second bed position, and deriving a third scatter sinogram for a third bed position between the first bed position and the second bed position, wherein the third scatter sinogram is derived from the first scatter sinogram according to a first percentage of overlap of the first bed position with the third bed position, and from the second scatter sinogram according to a second percentage of overlap of the second bed position with the third bed position.
US09286697B2	Reconfigurable image processing apparatus with variable compression rate and recording medium for reconfigurable image processing An image processing apparatus includes a reconfigurable circuit, a compression unit, an image processing unit, and a controller. The reconfigurable circuit has a reconfigurable circuit configuration. The compression unit is configured as a circuit in the reconfigurable circuit to compress image data. The image processing unit is configured as a circuit in the reconfigurable circuit to perform image processing on the compressed image data. The controller changes the circuit configuration of the reconfigurable circuit so as to vary a compression rate of the compression unit in accordance with a processing capacity of the image processing unit.
US09286694B2	Apparatus and method for detecting multiple arms and hands by using three-dimensional image Provided are an apparatus and method for detecting a plurality of arms and hands by using a three-dimensional (3D) image. The apparatus includes an image input unit configured to acquire a 3D image of an object, an arm detecting unit configured to detect one or more component-unit candidate regions of the object in the 3D image, and detect one or more arm regions by using arm detection feature information, extracted from each of the candidate regions, and a pattern recognition algorithm, and a hand detecting unit configured to calculate a position of a hand and a position of a wrist in each of the arm regions detected by the arm detecting unit, and detect a hand region by using the position of the hand and the position of the wrist.
US09286693B2	Method and apparatus for detecting abnormal movement Provided are a method and apparatus for detecting an abnormal movement. The apparatus includes a feature tracing unit configured to extract features of a moving object in an input image, trace a variation in position of the extracted features according to time, and ascertain trajectories of the extracted features; a topic online learning unit configured to classify the input image in units of documents which are bundles of the trajectories, and ascertain probability distribution states of topics, which constitute the classified document, by using an online learning method which is a probabilistic topic model; and a movement pattern online learning unit configured to learn a velocity and a direction for each of the ascertained topics, and learn a movement pattern by inferring a spatiotemporal correlation between the ascertained topics.
US09286692B2	System and method of book leaf tracking A method of book leaf tracking comprises receiving a video image comprising a book, estimating the current position and orientation of the book within the video image in response to a fiduciary marker of the book visible in the image, estimating the visibility of one or more predetermined features of the book, calculating a range of leaf turning angles that is consistent with the detected visibility of the or each predetermined feature of the book for the estimated current position and orientation of the book, and estimating the angle of a turning leaf of the book responsive to the calculated range.
US09286690B2	Method and apparatus for moving object detection using fisher's linear discriminant based radial basis function network A method for moving object detection based on a Fisher's Linear Discriminant-based Radial Basis Function Network (FLD-based RBF network) includes the following steps. A sequence of incoming frames of a fixed location delivered over a network are received. A plurality of discriminant patterns are generated from the sequence of incoming frames based on a Fisher's Linear Discriminant (FLD) model. A background model is constructed from the sequence of incoming frames based on a Radial Basis Function (RBF) network model. A current incoming frame is received and divided into a plurality of current incoming blocks. Each of the current incoming blocks is classified as either a background block or a moving object block according to the discriminant patterns. Whether a current incoming pixel of the moving object blocks among the current incoming blocks is a moving object pixel or a background pixel is determined according to the background model.
US09286686B2	Assessing the condition of a joint and assessing cartilage loss Methods are disclosed for assessing the condition of a cartilage in a joint and assessing cartilage loss, particularly in a human knee. The methods include converting an image such as an MRI to a three dimensional map of the cartilage. The cartilage map can be correlated to a movement pattern of the joint to assess the affect of movement on cartilage wear. Changes in the thickness of cartilage over time can be determined so that therapies can be provided. The amount of cartilage tissue that has been lost, for example as a result of arthritis, can be estimated.
US09286685B2	System and method for creating a virtual backdrop Some implementations may provide a method for generating a portrait of a subject for an identification document, the method including: receiving a photo image of the subject, the photo image including the subject's face in a foreground against an arbitrary background; determining the arbitrary background of the photo image based on the photo image alone and without user intervention; masking the determined background from the photo image; and subsequently generating the portrait of the subject for the identification document of the subject, the portrait based on the photo image with the determined background masked.
US09286684B2	Application system and method for measuring and compensating for optical distortion Aspects of the present invention relate to systems, methods, and computer program products for measuring and compensating for optical distortion. The system includes a plurality of reference marks; a recording device configured to record a first orientation and a first position of a plurality of reference marks relative to a pointing angle of the recording device when an object is located outside of a field of view of a recording device, the recording device configured to record a second orientation and a second position of a plurality of reference marks relative to the pointing angle of the recording device when an object is located inside the field of view; and a processor configured to compare the first orientation and the first position of the plurality of reference marks to the second orientation and the second position of the plurality of the reference marks for measuring distortion of the object.
US09286681B2	Edit guided processing method for time-lapse image analysis A computerized mask edit guided processing method for time-lapse image analysis performs by a computer program an assisted mask editing on an input image sequence to generate mask edit data, and performs a mask edit guided processing using the image sequence and the mask edit data. A computerized track edit guided processing method for time-lapse image analysis performs by a computer program an assisted track editing on an input image sequence to generate track edit data, and performs a track edit guided processing using the image sequence and the track edit data. A computerized edit guided processing method for time-lapse image analysis performs by a computer program a combination of assisted mask editing and assisted track editing on an input image sequence to generate edit data, and performs a combination of mask edit guided processing and track edit guided processing using the image sequence and the edit data.
US09286678B2	Camera calibration using feature identification Disclosed are methods, systems, computer readable media and other implementations, including a method to calibrate a camera that includes capturing by the camera a frame of a scene, identifying features appearing in the captured frame, the features associated with pre-determined values representative of physical attributes of one or more objects, and determining parameters of the camera based on the identified features appearing in the captured frame and the pre-determined values associated with the identified features.
US09286677B2	Reorientation of cardiac images In a method for estimating an orientation of a cardiac long axis from corresponding early frame and late frame images implemented in a computerized processor, a bounding box of the myocardium is defined in the late frame image and the bounding box is applied to the early frame image. A main axis of the image of the early frame within the bounding box is estimated, and the image of the early frame is oriented according to the estimated main axis. A main axis of the image of the late frame within the bounding box is also estimated, and the late frame image is reoriented according to the estimated main axis. The estimated main axis of the early frame to the estimated main axis of the late frame are compared, and in attribute of the comparison result is made available as an output from the processor.
US09286676B2	Method for separating and estimating multiple motion parameters in X-ray angiogram image A method for separating and estimating multiple motion parameters in an X-ray angiogram image. The method includes: determining a cardiac motion signal cycle and a variation frame sequence of translational motion according to an angiogram image sequence, tracing structure feature points of vessels in the angiogram image sequence whereby obtaining a motion sequence, processing the motion sequence via multivariable optimization and Fourier frequency-domain filtering, separating an optimum translational motion curve, a cardiac motion curve, a respiratory motion curve and a high-frequency motion curve according to the variation frame sequence of translational motion, a cycle of the cardiac motion signal, a range of a respiratory motion signal cycle, and a range of a high-frequency motion signal cycle.
US09286674B2	Ophthalmic analysis apparatus and ophthalmic analysis program There is provided an ophthalmic analysis apparatus configured to acquire an analysis result of a tomographic image of a subject eye which is acquired by using optical coherence tomography (OCT), and to output the analysis result. The apparatus functions as a display control unit configured to control a display unit to display a two-dimensional image based on an OCT tomographic image; an analysis region setting unit configured to set multiple analysis regions on the two-dimensional image displayed on the display unit by the display control unit; and an output control unit configured to acquire an analysis result in the multiple analysis regions set by the analysis region setting unit and to output the acquired analysis result.
US09286672B2	Integrated multivariate image-based method for disease outcome predicition The described invention provides a system and method for predicting disease outcome using a multi-field-of-view scheme based on image-based features from multi-parametric heterogenous images.
US09286671B2	Method for determining at least one applicable path of movement for an object in tissue A method for determining an applicable path of movement of an object in human or animal tissue is based on intensity data obtained by a 3D imaging technique. The applicable path of movement connects a starling position of the object with a defined target location. The method includes defining the target location of a reference point of the object and choosing at least one possible starting position of the reference point of the object. Further, the method includes determining a candidate path of movement between the corresponding possible starling position and the defined target location. Next, the candidate path of movement is evaluated for being an applicable path. The candidate path is evaluated based on information about local intensity extrema and/or intensity variation resulting from the intensity data along the candidate path of movement.
US09286670B2	Pathological diagnosis assisting apparatus, pathological diagnosis assisting method and non-transitory computer readable medium storing pathological diagnosis assisting program A pathological diagnosis assisting apparatus according to the present invention provides the diagnosis assisting information for assisting diagnosis of tissue fibrosis from the image of the stained sample, and includes an image reading unit configured to read the image of the stained sample and an image processing unit configured to process the image. The image processing unit includes an image classification unit configured to classify the collagenous fiber and the elastic fiber, a tissue area extraction unit configured to extract a tissue area, an occupancy rate calculation unit configured to calculate the occupancy rates of the collagenous fiber and the elastic fiber in the tissue area, and a diagnosis assisting information providing unit configured to provide the diagnosis assisting information based on the calculated occupancy rates of the collagenous fiber and the elastic fiber.
US09286665B2	Method for dynamic range editing A method of displaying a high dynamic range image, comprising receiving the high dynamic range image, calculating a first set of tone mapping parameters as a function of the high dynamic range image, sub-sampling the first set of tone mapping parameters at a first resolution to create a first sub-sampled parameter set, creating a first tone-mapped image by processing the high dynamic range image as a function of the first sub-sampled parameter set, and displaying the first tone-mapped image. A method of composting a plurality of versions of an image to create the high dynamic range image is also disclosed such that the compositing may be modified as a function of received user input.
US09286663B2	Method and apparatus for filtering an image using a guidance image A method and an apparatus for filtering an image using a guided image filter are described. A filter computes a filtering output using a guidance image. For calculating the filtering output confidence values associated to a filter input are taken into account. A confidence-weighted averaging is performed using the confidence values.
US09286658B2	Image enhancement Techniques described in the disclosure are generally related to enhancing portions of an image relative to other portions of the image. The example techniques may utilize depth information in conjunction with one or more viewer perceivable information to enhance portions of the image relative to other portions. The techniques may then display the enhanced image to provide the viewer with a possibly more realistic image.
US09286652B2	Screen generating apparatus, screen generating system, and screen generating method According to an embodiment, provided is a screen generating apparatus that includes: a position information acquirer that acquires a screen position information file that sets a font size of a font included in a screen and position information of an image or a part included in the screen; a screen display size acquirer that acquires a screen display size of a display devise as a target display; a magnification calculator that calculates a magnification by using a predetermined screen display size and the acquired screen display size; a font size determiner that determines a font size in the display devise as the target display based on the calculated magnification; a converter that converts the screen position information file based on the calculated magnification and the determined font size; and a screen generator that generates a screen compatible with the converted screen position information file.
US09286649B2	Conditional execution of rendering commands based on per bin visibility information with added inline operations A GPU may determine, based on a visibility stream, whether to execute instructions stored in an indirect buffer. The instructions include instructions for rendering primitives associated with a bin of a plurality of bins and include one or more secondary operations. The visibility stream indicate if one or more of the primitives associated with the bin will be visible in a finally rendered scene. The GPU may, responsive to determining not to execute the instructions stored in the indirect buffer, execute one or more secondary operations stored in a shadow indirect buffer. The GPU may, responsive to determining to execute the instructions stored in the indirect buffer, execute the instructions for rending the primitives associated with the bin of the plurality of bins and executing the one or more secondary operations stored in the indirect buffer.
US09286646B1	Method for managing centralized power generation with the aid of a digital computer Value of solar (VOS) analysis begins with the observation that photovoltaic power production represents a unique form of energy resource that is indifferent to demand and price signals. Accurate VOS assessment requires consideration of technical and economic components. The technical analysis predicts future central power generation requirements, as reflected by estimated customer demand, using an energy balance approach. A customer demand forecasting equation with three unknown values, distributed photovoltaic power production, centralized power generation, and losses associated with the centralized power generation, is solved by applying key rational assumptions in combination with historical data of centralized power generation and distributed photovoltaic power production. The solution to the demand equation is then provided with economic data, such as avoided fuel cost, avoided plant operations and maintenance cost, avoided generation capacity cost, avoided reserve capacity cost, avoided transmission and distribution capacity cost, fuel price guarantee value, and avoided environmental cost.
US09286645B2	Academic activity stream A method and computer-readable medium for generating an activity stream is provided. The activity stream includes a ranked set of objects that are presented to one or more users. The ranking of objects is updated to reflect events associated with objects.
US09286642B2	Content access management in a social networking system for externally stored content A content access management system receives an access determination requested identifying an access rule and a requesting user. The access rule may be created in advance by the content owner at the content access management system. The access rule may allow access to content objects based on the requesting user's biographic information, geographic information, affiliation information, payment information, or any other user characteristic. The user information may be entered by the requesting user at a social networking system interface for purposes unrelated to the content object or content owner. The content access management system retrieves the identified access rule and retrieves requesting user information based on the access rule. An access determination is made based on the retrieved access rule and requesting user information, and is transmitted to the content owner.
US09286641B2	Automatic photo capture based on social components and identity recognition In one embodiment, a mobile device automatically captures image frames by acquiring a real-time video sequence, selecting one or more frames from the real-time video sequence based on social network information and identity recognition, and storing the selected one or more frames in a local storage of the mobile device.
US09286635B2	Method of transmitting information from efficient communication protocol card readers to mobile devices A method is provided of transmitting information with a communication protocol to a mobile device. A card reader is provided with a read head that has a slot for swiping a magnetic stripe of a card, an output jack and device electronics that includes a microcontroller. The read head is used to read data on a magnetic stripe of a card. A raw magnetic signal is produced indicative of data stored on the magnetic stripe. The raw magnetic head signal is converted into a processed digital signal that the microcontroller can interpret. A synchronous Manchester encoded stream is produced that makes a greater number of 0 crossings. A Manchester encoded stream output jack signal is delivered to the mobile device through the output jack.
US09286629B2	Methods and systems for transacting travel-related goods and services Provided are methods and systems for efficient matching of suppliers and customers for travel-related and other types of goods and services. These methods and systems are based on an exchange or market concept, in which a computer system performs matching between different parties. Specifically, an exchange system may compare customers' requests with suppliers' content records. In certain embodiments, an exchange system sends notifications of customers' requests to suppliers based on criteria presented by the suppliers. Users' requests and/or vendors' content records may be processed using natural language parser to determine appropriate components for searches and matches. This substantially improves efficiency of the exchange system and makes it more user friendly as users and vendors may present different terms in their respective searches and entries. An exchange system may include a pattern recognition component and semantic natural language parser to perform this function.
US09286623B2	Method for determining an area within a multimedia content element over which an advertisement can be displayed A method and system for detecting at least an advertising attractive area within a multimedia content element over which an advertisement item can be displayed. The method comprises extracting the multimedia content element from a web-page; partitioning the multimedia content element into a predefined number of portions; generating at least one signature for each portion of the multimedia content element; analyzing the at least one signature generated for each portion of the multimedia content elements; and identifying at least one attractive advertising area within the multimedia content element based on the signature analysis.
US09286622B2	Press release distribution system A press release distribution system provides press release and other news to forum sites as posts. The forum software that runs at forum sites includes press release interface software or is adapted to receive press release interface plug-in modules for interfacing with the press release distribution system. The press release interface software or plug-in module may also monitor and/or analyze user data of forum members and/or forum activities of the users. The monitored user data and forum activities may be provided to the press release distribution system for analysis and generation of user profiles. Using the result of the analysis (e.g., user profiles), the press release distribution system can target particular users or forums to direct the press releases, news, or advertisements for most effective advertising campaign.
US09286614B2	Electronic digital direct-mail collateral An electronic digital direct-mail collateral. In an embodiment, the device comprises a card stock mailer similar to a CD case, center hinged and printed with branded advertising information and graphic. The device may further comprise video, audio and cell phone operations.
US09286613B2	Ordering of goods or services using memory for storing digital content A memory tag is a transponder device with a memory for storing digital content. The memory contains code for generating an order for goods or services from a plurality of order choices.
US09286612B2	Integrated change management unit An integrated system for managing changes in regulatory and nonregulatory requirements for business activities at an industrial or commercial facility. Application of this system to environmental, health and safety activities, and to food, drug, cosmetic, and medical treatment and device activities, are discussed as examples. The system: provides one or more databases that contain information on operations and requirements concerning an activity or area of business; receives information on regulatory and nonregulatory changes that affect operations of the business; converts these changes into changes in data entry forms, data processing and analysis procedures, and presentation (by printing, electronic display and/or distribution) of data processing and analysis results to selected recipients, without requiring the services of one or more programmers to re-key and/or reformat the items affected by the change; and implements receipt of change information and dissemination of data processing and analysis results using the facilities of the Internet.
US09286611B2	Map topology for navigating a sequence of multimedia A computer implemented method providing a sequence of multimedia files in a map topology includes layers and sub-layers to enable a user to navigate and play a particular multimedia file that demonstrates a feature of a product. Each layer and sub-layer corresponds to a multimedia file that demonstrates a feature of a product. The sequence of multimedia files are stored in an application server (104). The method includes processing a selection of a layer from the user based on a preview of the layer that includes a first reveal branches field, a first hide branches field, and a first play field, displaying at least one branch of a sub-layer of said layer when the reveal branches field is selected, and playing the particular multimedia file corresponding to any of the layer, the sub-layer, or any further sublayer of the sub-layer when a play field is selected.
US09286609B2	Wireless devices for storing a financial account card and methods for storing card data in a wireless device A wireless device is enabled to receive a financial account card that is inserted into a card slot of the wireless device. The wireless device reads card data from the financial account card when it is inserted into the slot and programs an RFID (radio frequency identification) tag or a memory included in the wireless device. The wireless device may then be used to provide payment by transmitting the card data via radio frequency to a nearby RFID reader using the RFID tag. The financial account card may also be ejected from the wireless device and swiped by a magnetic card reader.
US09286608B1	System and method for predictive payment authorizations Embodiments may include a payment management system that receives information indicating a first transaction is to be initiated, the information specifying a first quantity of funds. The system may determine that an additional transaction for a respective quantity of funds is expected to be initiated within a given time period. The system may, prior to initiation of the additional transaction, generate a payment authorization request for a combined quantity of funds equal to at least a sum of the first quantity of funds and the respective quantity of funds of the additional transaction. The system may, subsequent to receiving information indicating that a payment authorization for the combined quantity of funds was issued and subsequent to receiving information indicating that the additional transaction is to be initiated, initiate settlement of the first transaction and the at least one additional transaction using the combined quantity of funds of the payment authorization.
US09286607B2	Method and apparatus for payment transactions A contactless card reader system comprises the a contactless card reader for short range wireless communication with a payment device using a contactless card protocol. The reader also comprises a terminal for exchanging data with the payment device and with a remote server to perform a contactless card transaction. The terminal is comprised in a personal computing device. The remote server may provide functionality to the terminal in performance of the transaction. A method of performing a transaction is also described.
US09286599B2	Redacting content in online meetings A method, computer program product, and system for redacting content in online meetings is described. A method may comprise receiving, via one or more computing devices, a selected portion of content to redact in a first online meeting. The method may further comprise determining, via the one or more computing devices, if a participant of the first online meeting is in an un-trusted location. The method may additionally comprise, in response to determining that the participant of the first online meeting is in the un-trusted location, redacting, via the one or more computing devices, the selected portion of content from content available to the participant in the first online meeting.
US09286597B2	Tracking co-authoring conflicts using document comments A comment infrastructure for managing co-authoring conflict resolutions is provided. During co-authoring, multiple users may make edits to a document at the same time or users may merge edits to a document. Embodiments determine if changes submitted by a user conflict with previously submitted changes. If a conflict is found, the conflicting change may be saved to the document as a comment, allowing for the user to choose when to resolve the conflict. The original content and the different co-authoring edits may be displayed side-by-side, allowing users to make an informed decision about a desired resolution of a conflict. Additional commenting functionalities may be provided for allowing users to leave comments, replies, or messages associated with a co-authoring conflict, providing communication and collaboration between users about a best way to resolve a co-authoring conflict.
US09286594B1	Visually readable electronic label A visually readable electronic label is disclosed. The system comprises a radio frequency identity (RFID) component that is operable to store data, an antenna coupled to the radio frequency identity component that is operable for deriving electrical power from an incident radio frequency field, where the derived electrical power is the sole electrical power available to the electronic label and a display coupled to the radio frequency identity component that is operable to present a visual indication of the data when commanded by the radio frequency identity component and when electrical power derived from an incident radio frequency field is available.
US09286588B2	Vending machine service scheduling Techniques are provided for calculating vending machines' service priorities and scheduling the vending machines for service taking into account a number of factors and thresholds (520). In some embodiments, the machines (110) are subdivided into subroutes (320). Each subroute has one or more machines, and at least one subroute has a plurality of machines. The vending machine service schedule is generated by selecting the highest priority subroute (410) and selecting the machines in that subroute (420). Other subroutes can be selected (430, 440) if there is time left in the Service Period.
US09286585B2	Automated data-driven closed-loop-feedback method for adaptive and comparative quality control in a discrete data aggregation environment A method for determining quality includes receiving supplier quality data from a supplier. The supplier quality data includes discrete quality data. The supplier quality data is for a quantity of a component supplied to a company or for a service provided on behalf of the company over a supplier measurement period. The method includes aggregating quality data from two or more suppliers. The quality data is for the supplied component or provided service over a baseline time period. The method includes determining a quality benchmark using the aggregated quality data and setting one or more alarm levels. The alarm levels are based on the quality benchmark of the aggregated quality data. The method includes determining supplier quality level for the supplier for the supplier measurement time period. The supplier quality is based on the supplier quality data. The method includes determining if the supplier quality data exceeds an alarm level.
US09286584B2	Visualizing business processes or scenarios in a business software model using transit maps A business scenario landscape map can show a scenario-centric view of a business scenario landscape that includes business scenarios accessible to members of an organization and supported by a business software architecture. In the scenario-centric view, first user interface elements can be arranged to show a linear representation of business process features of a selected business scenario and a visual depiction of relationships between the selected business scenario and other business scenarios. Upon receiving selection of a first user interface element(s) related to another business scenario, at least some of the first user interface elements can be rearranged to show a new scenario-centric view of the business scenario landscape in which business process features of the newly selected business scenario are arranged in a new linear representation including a visual depiction of relationships between the newly selected business scenario, the originally selected business scenario, and/or relationships with other additional scenarios.
US09286582B2	Systems and methods for detecting changes in energy usage in a building A computer system for use with a building management system for a building includes a processing circuit configured to determine a building's baseline energy usage model. The processing circuit may be configured to determine one or more automatically selected variables for use in the baseline energy usage model for predicting energy use in a building. The processing circuit may be further configured to cause the display of the one or more automatically selected variables on a user interface device. The processing circuit may be configured to receive, from the user interface, a selection of one or more variables which differ from the one or more automatically selected variables. The processing circuit may be further configured to use the received selection to generate a new baseline energy usage model.
US09286575B2	Adaptive ranking of news feed in social networking systems Machine learning models are used for ranking news feed stories presented to users of a social networking system. The social networking system divides its users into different sets, for example, based on demographic characteristics of the users and generates one model for each set of users. The models are periodically retrained. The news feed ranking model may rank news feeds for a user based on information describing other users connected to the user in the social networking system. Information describing other users connected to the user includes interactions of the other users with objects associated with news feed stories. These interactions include commenting on a news feed story, liking a news feed story, or retrieving information, for example, images, videos associated with a news feed story.
US09286574B2	Systems and methods for layered training in machine-learning architectures A computer-implemented method for layered training of machine-learning architectures includes receiving a plurality of data elements wherein each data element is associated with a timestamp, determining a training window for each model layer of a layered stack of model layers, determining a plurality of training data elements for each training window by identifying the data elements with timestamps corresponding to each of the training windows, identifying a previous checkpoint for each model layer wherein the previous checkpoint for each model layer is generated by a parent model layer, training each model layer with the determined training data elements for each model layer and the identified previous checkpoint for each model layer, generating a plurality of current checkpoints wherein each current checkpoint of the plurality of current checkpoints is associated with a model layer, and storing the plurality of current checkpoints at the memory.
US09286571B2	Machine learning for database migration source Technologies are generally provided for maintaining performance level of a database being migrated between different cloud-based service providers employing machine learning. In some examples, data requests submitted to an original data store/database may be submitted to a machine learning-based filter for recording and analysis. Based on the results of the data requests and the filter analyses, new key value structures for a new data store/database may be created. The filter may assign performance scores to the original data requests (made to the original data store) and data requests made to the newly-created key value structures. The filter may then compare the performance scores associated with the created key value structures to each other and to performance scores associated with the original data requests and may select the created key value structures with performance scores that are at least substantially equal to those of the original data requests for the new data store.
US09286564B2	Apparatuses and methods for printed radio frequency identification (RFID) tags Apparatuses and methods are provided for providing a printed radio frequency identification (RFID) tag assembly. In one exemplary embodiment, the RFID tag assembly includes a substrate including a top surface, and a receiving layer, comprising a plurality of receiving pads having conductive properties, located on the top surface of the substrate. The RFID tag assembly may further include a chip located on the top surface of the substrate. In addition, the RFID tag assembly may include an antenna printed on the receiving layer and bonded to the receiving layer using at least one of a wedge bonding technique and a ball bonding technique. The antenna may include at least one of copper, aluminum, palladium-covered copper, and aluminum-covered copper wire or ribbon.
US09286560B2	Creation and management of dynamic quick response (QR) codes A quick response (QR) code change event configured to cause a processor to change encoding of a displayed dynamic QR code is detected. The dynamic QR code includes an encoded unique value associated with an item displayed in a retail environment. Encoding of the dynamic QR code is changed to encode a new unique value. The new unique value is based upon a set of contemporaneous data elements associated with the item displayed in the retail environment. The changed dynamic QR code including the encoded new unique value is displayed in association with the item displayed in the retail environment.
US09286552B2	Image forming apparatus, image forming method, and computer-readable recording medium An image forming apparatus includes a communication interface unit which receives print data, an image forming unit which prints the received print data, a volatile memory which, if the received print data is data that needs to be stored, stores the received print data, and a controller which, if a power-off command regarding the image forming apparatus is input, backs up print data stored in the volatile memory in a storage medium connectable to the image forming apparatus and converts an operation mode of the image forming apparatus to a power-off mode.
US09286546B2	Identifying labels for image collections Methods, systems, and apparatus for identifying labels for image collections are presented. In one aspect, a method includes obtaining a collection of images; obtaining, for each image in the collection of images, image similarity data that indicates a measure of similarity of the image to other images in the collection of images; generating, based on the similarity data, two or more image clusters from the collection of images, each image cluster including one or more images from the collection of images; for each image cluster: obtaining, for each image in the image cluster, a set of image labels; generating, from each set of image labels obtained for each image in the image cluster, a set of cluster labels; selecting one or more cluster labels from the set of cluster labels; and identifying the selected cluster labels as a set of collection labels for the collection of images.
US09286545B1	System and method of using images to determine correspondence between locations In one aspect, a system and method is provided that matches images that are associated with street addresses with images that are associated with locations that are stored with respect to another reference system, such as latitude/longitude. If the images match, the street address is associated with the location. In a further aspect, text contained in the images is extracted and associated with the street address as well.
US09286542B1	Photographic stage A photographic stage is provided that includes at least one camera, a scanner, and a computer configured to capture a plurality of images from the at least one camera. The computer is also configured to detect a tagged item based on data from the scanner and to identify the tagged item in at least one of the images. A method of using the photographic stage and an apparatus is also provided.
US09286540B2	Fast dense patch search and quantization In techniques for fast dense patch search and quantization, partition center patches are determined for partitions of example image patches. Patch groups of an image each include similar image patches and a reference image patch that represents a respective patch group. A partition center patch of the partitions is determined as a nearest neighbor to the reference image patch of a patch group. The partition center patch can be determined based on a single-nearest neighbor (1-NN) distance determination, and the determined partition center patch is allocated as the nearest neighbor to the similar image patches in the patch group. Alternatively, a group of nearby partition center patches are determined as the nearest neighbors to the reference image patch based on a k-nearest neighbor (k-NN) distance determination, and the nearest neighbor to each of the similar image patches in the patch group is determined from the nearby partition center patches.
US09286536B2	Image processing system for determining a boundary line using a shadow image An image processing apparatus including a candidate pixel detector for detecting candidate pixels of boundary lines of sides of a document region, a classifier for classifying coordinates of the candidate pixels into coordinate groups, an approximate line calculator for calculating approximate lines for the boundary line based on each of the coordinate groups, a provisional line determination unit for determining a provisional line of the boundary line based on the approximate lines that is selected based on the number of candidate pixels that are within a distance from the approximate line, a shadow detector for detecting a shadow image of an edge of the document within a predetermined distance from the provisional line, and a boundary line determination unit for determining whether the boundary line is within the predetermined distance from the provisional line based on the shadow image.
US09286527B2	Segmentation of an input by cut point classification Techniques are provided for segmenting an input by cut point classification and training a cut classifier. A method may include receiving, by a computerized text recognition system, an input in a script. A heuristic may be applied to the input to insert multiple cut points. For each of the cut points, a probability may be generated and the probability may indicate a likelihood that the cut point is correct. Multiple segments of the input may be selected, and the segments may be defined by cut points having a probability over a threshold. Next, the segments of the input may be provided to a character recognizer. Additionally, a method may include training a cut classifier using a machine learning technique, based on multiple text training examples, to determine the correctness of a cut point in an input.
US09286525B2	Method for evaluating an object recognition device of a motor vehicle For testing an object recognition device for a motor vehicle at reasonable costs for different routes, image data for testing the object recognition device may be generated with a camera simulation device. Because the image data of a camera simulation device are artificially generated, it must be made certain that they have a realistic effect on the object recognition device. Reference image data are generated with a camera and simulation image data are generated with the camera simulation device for at least one route. The simulation image data and the reference image data are compared with each other based on at least two comparison measures. A value which is independent of the object recognition device to be tested can be determined for each of the comparison measures. It is then checked if the totality of the generated comparison values satisfies a predetermined validation criterion.
US09286524B1	Multi-task deep convolutional neural networks for efficient and robust traffic lane detection Disclosed herein are devices, systems, and methods for detecting the presence and orientation of traffic lane markings. Deep convolutional neural networks are used with convolutional layers and max-pooling layers to generate fully connected nodes. After the convolutional and max-pooling layers, two sublayers are applied, one to determine presence and one to determine geometry. The presence of a lane marking segment as detected by the first sublayer can serve as a gate for the second sublayer by regulating the credit assignment for training the network. Only when the first sublayer predicts actual presence will the geometric layout of the lane marking segment contribute to the training of the overall network. This achieves advantages with respect to accuracy and efficiency and contributes to efficient robust model selection.
US09286522B2	Stereo assist with rolling shutters An imaging system for a vehicle may include a first image capture device having a first field of view and configured to acquire a first image relative to a scene associated with the vehicle, the first image being acquired as a first series of image scan lines captured using a rolling shutter. The imaging system may also include a second image capture device having a second field of view different from the first field of view and that at least partially overlaps the first field of view, the second image capture device being configured to acquire a second image relative to the scene associated with the vehicle, the second image being acquired as a second series of Image scan lines captured using a rolling shutter. As a result of overlap between the first field of view and the second field of view, a first overlap portion of the first image corresponds with a second overlap portion of the second image. The first image capture device has a first scan rate associated with acquisition of the first series of image scan lines that is different from a second scan rate associated with acquisition of the second series of image scan lines, such that the first image capture device acquires the first overlap portion of the first image over a period of time during which the second overlap portion of the second image is acquired.
US09286519B2	White turbid state diagnostic apparatus A white turbid state diagnostic apparatus has an imaging part installed on a vehicle and configured to convert a light signal from a periphery of the vehicle into an image signal, a region detection part configured to detect a region from the image signal, the region being constituted by pixels having brightness values over a predetermined brightness and being in a substantially circular shape having a predetermined area or more, a brightness gradient calculation part configured to calculate a brightness gradient on a line which is directed from a predetermined position in a predetermined direction based on brightness values of pixels on the line in the region, and a white turbid level calculation part configured to calculate a white turbid level of the lens based on the brightness gradient.
US09286517B2	Methods and apparatus to specify regions of interest in video frames Methods and apparatus to specify regions of interest in video frames are disclosed. Example disclosed methods to mark a region in a graphical presentation include selecting a first point located at a substantially central position within the region, selecting a plurality of second points to define a boundary of the region, and comparing a plurality of stored templates with the selected first and second points to identify a first one of the stored templates to represent the region.
US09286515B2	Doze detection method and apparatus thereof A doze detection method, which accurately detects a blink burst and improves speed and accuracy of doze detection, includes measuring a state where the eye is substantially open as an open eye time and another state as a closed eye time, defining a time shorter than an average blink interval of a healthy adult in an alert state as a first threshold time; defining a time longer than an average closed eye time of a healthy adult in an alert state as a second threshold time; and defining blinks as a blink burst when detecting an eye opening equal to or shorter than the first threshold time. A doze state is determined when the closed eye time of a blink among the blinks during the blink burst reaches at least the second threshold time, the blink occurring after an open eye time equal to at most the first threshold time.
US09286509B1	Image optimization during facial recognition Described is a technique for optimizing an image for facial detection. More specifically, described is a process of predicting the location of a face within an image and adjusting image settings based on at least a portion of the predicted location of the face. An image may be adjusted based on the characteristics of a metering region, which may be selected prior to performing facial detection. For example, the metering region may be a specified shape with dimensions equal to a certain percentage of the input image and placed at a specified location. The result of using such a metering region is that the image adjustments may be based on a portion of the face, and therefore, may be optimized for facial detection.
US09286506B2	Stereoscopic measurement system and method A stereoscopic measurement system captures stereo images and determines measurement information for user-designated points within stereo images. The system comprises an image capture device for capturing stereo images of an object. A processing system communicates with the capture device to receive stereo images. The processing system communicates with the capture device to receive stereo images. The processing system displays the stereo images and allows a user to select one or more points within the stereo image. The processing system processes the designated points within the stereo images to determine measurement information for the designated points.
US09286502B1	Barcode reader A barcode reader may perform image processing functions to generate distinct image data records from the frame of image data of a barcode, select an image data record from the distinct image data records and decode the selected image data record. Each image data record may be generated by applying a distinct image processing function to the frame of image data. The barcode reader may capture multiple frames of image data in sequence based on image capture parameters. At least one of the multiple frames of image data may be captured with a distinct parameter value. The image capture parameters may include an exposure setting, a gain setting, a resolution setting, and/or an illumination setting.
US09286498B2	Remote management of a barcode reader A computer includes an application that expects to receive data via a unidirectional communication interface. The computer also includes a background service having a first thread and a second thread. The computer additionally includes device management client software. A barcode reader scans one or more barcodes to generate scanned data. The scanned data is sent to the computer via the unidirectional interface. The first thread of the background service reads the scanned data from the unidirectional interface and sends the scanned data to the application. The second thread of the background service enables the device management client software to perform management operations on the barcode reader via a bidirectional communication interface.
US09286494B1	Card reader having discriminator contact A card reader for a point-of-sale system that is configured to accept both magnetic strip-type and integrated circuit (IC) chip-type payment cards. The card reader is a component of a point-of-sale system including a portable computing device in communication with the card reader that is configured to present a first graphical user interface (GUI) when a magnetic stripe-type card is detected and a second GUI when an IC chip-type card is detected in the card reader. The card reader comprises a slot configured to receive the payment card, a magnetic reading device and an IC chip reading device. The card reader also includes a discriminator contact disposed within the slot that is configured to conduct across a surface of a metal pad of the IC chip-type card prior to the CI chip reading device making contact with the IC chip.
US09286482B1	Privacy control based on user recognition In some examples, an electronic device may include one or more recognition devices able to be used to recognize a current user. If the electronic device recognizes that a primary user, such as an owner, is currently using the electronic device, the electronic device may allow access to all of the primary user's private information and all of the features of the electronic device. On the other hand, when the electronic device determines that the current user is an unknown user, or that the current user is a known user who is authorized to access only limited information or features of the electronic device, the electronic device may send a communication to restrict the current user from accessing private information of the primary user. In some cases, the electronic device may enable the primary user to designate which items known users and/or unknown users may access.
US09286478B2	Image processing device and computer readable storage medium therefor An image processing device is provided. The image processing device includes a scanner to scan an image formed in a scannable area which is allocated on a sheet, an image obtainer to obtain a processible image formed in the scannable area and scanned by the scanner, a judging unit to judge as to whether the processible image obtained by the image obtainer includes an identifying image, which qualifies a predetermined authentication criterion, and a function controller to activate a predetermined function of the image processing device, which processes the processible image obtained by the image obtainer, when the judging unit judges that the obtained processible image includes the identifying image therein.
US09286475B2	Systems and methods for enforcement of security profiles in multi-tenant database Embodiments relate to systems and methods for the enforcement of security profiles in a multi-tenant database. A multi-tenant database can be populated with data from different users or other entities. Different users may enjoy different sets of permissions to access, modify, store, and/or otherwise manipulate sets of data within the database. After authentication, a user's associated set of permissions are retrieved. When data is requested, matching tables or other objects located in the database are identified based on the user's query. Rather than retrieving matching tables or other objects directly, a meta data security engine can check the requesting user's permissions, and apply any filters or restrictions required by those permissions to the data present in the table(s). A substitution can be made of a table-valued function, including any filtered data entries, for the table itself. Flexible and granular data security rules can thereby be applied, transparently to the user.
US09286471B2	Rules based detection and correction of problems on mobile devices of enterprise users A system is disclosed that includes components and features for enabling enterprise users to securely access enterprise resources (documents, data, application servers, etc.) using their mobile devices. An enterprise can use some or all components of the system to, for example, securely but flexibly implement a BYOD (bring your own device) policy in which users can run both personal applications and secure enterprise applications on their mobile devices. The system may, for example, implement policies for controlling mobile device accesses to enterprise resources based on device attributes (e.g., what mobile applications are installed), user attributes (e.g., the user's position or department), behavioral attributes, and other criteria. Client-side code installed on the mobile devices may further enhance security by, for example, creating a secure container for locally storing enterprise data, creating a secure execution environment for running enterprise applications, and/or creating secure application tunnels for communicating with the enterprise system.
US09286470B2	Protection of a volatile memory against viruses by modification of the content of an instruction A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes for which the access to the areas is authorized or forbidden is associated with each of these areas.
US09286468B2	Option read-only memory use Example embodiments disclosed herein relate to altered option read-only memory. A copy of an option read-only memory is stored. The copy is used during a boot process based on a determination that the option read-only memory has been altered.
US09286465B1	Method and apparatus for federated single sign on using authentication broker Example embodiments of the present invention provide a method, an apparatus, and a computer program product for brokering establishment of a trusted relationship between a first domain and a second domain. The method includes receiving, from a first domain, a request to establish a trusted relationship with a second domain and brokering establishment of the trusted relationship between the first domain and the second. Other example embodiments include brokering authenticated access for a client in the first domain to a resource in the second domain according to the established trusted relationship.
US09286464B2	Display apparatus using key signals and control method thereof A display apparatus including an image processor which processes a video signal is provided. The display apparatus includes; a display which displays an image based on a processed video signal; a receiver which receives a key signal input by a user; a storage which stores a password key; and a controller which receives a user's first key signal which comprises an arrow key signal when a password is set up for the display apparatus, sets up and stores the password key which corresponds to the received first key signal, receives a user's second key signal when access is attempted, and allows the access in response to the received second key signal and the stored password key matching each other through a comparison.
US09286463B1	System and method for touchscreen combination lock Systems and methods for touchscreen security gateways are described, wherein a mechanical lock simulation is presented and operated by the user of a touchscreen interface. Comparisons between entered and stored combinations may be processed and/or stored utilizing local or remote processing and/or storage resources. The mechanical lock aspect of the user interface may comprise simulated rotating elements that may be operated by user-induced sliding interactions upon the user interface. Several aspects of the mechanical lock simulation may be customized or programmed by the user, and the presentation of the user interface operation to the user may include audible and/or haptic feedback.
US09286456B2	Method and apparatus for managing multiple media services A system that incorporates teachings of the subject disclosure may include, for example, obtaining a group of facial objects detected from an image captured by a camera coupled with a media device where the facial objects correspond to a plurality of users, determining authentication information for each of the plurality of users based on the facial objects, and providing the authentication information to a group of content service systems for enabling the media device to access aggregated media services from the group of content service systems. Other embodiments are disclosed.
US09286447B2	Portable digital vault and lending of same A portable digital vault and related methods are disclosed that can provide a digital equivalent to the physical act of lending copyrighted content (such as a book or CD) while also providing security to prevent copying of the content. The vault acts as a self-contained authority that contains permissions relating to actions that can be taken with respect to the vault and vault contents. Vault contents can be moved between vaults, vaults can be moved between computing devices, and a vault and its contents can be moved together as a single unit. A vault can store any type of content, such as digital books, audio and video. In some embodiments, the vault can be issued by a government authority and contain currency note information that allows the vault to be used as cash. A vault can also serve as a receipt of a digital legal contract.
US09286446B2	Domain spanning applications Managing and accessing media items, including: a plurality of domains configured to provide access to media items; a plurality of clients associated with the plurality domains, and providing a pathway for accessing the media items; and a spanning application configured to track and aggregate accessible media items from the plurality of domains based on authentication and registration information and associated rights of the plurality of clients and the plurality of domains, wherein the spanning application enables accessing of the media items across the plurality of domains.
US09286444B2	Next generation secure gateway A system includes a cloud-computing infrastructure to provide multitenant access from a public Internet Protocol (IP) network and multiple instances of a virtualized secure gateway operating on one or more physical devices within the cloud-computing infrastructure. The multiple instances of the virtualized secure gateway provide a point of entry to a private IP network. Each instance of the multiple instances of the virtualized secure gateway is configured to terminate multiple virtual private network (VPN) tunnels from a single customer accessing the private IP network via the public IP network, and each instance of the multiple instances of the virtualized secure gateway resides on a different processing core of the physical devices within the cloud-computing infrastructure.
US09286443B2	Systems and methods for data aggregation and prioritization Computer-enabled systems and methods aggregate data related to a particular subject or field and present the data in a simplified display. The data is divided into predetermined categories, which are graphically displayed in a predetermined arrangement. Systems and methods differentiate and visually display critical data abnormalities separately from non-critical data. The systems and methods enable an observer to identify the critical deviations or anomalies of data with respect to a predetermined base line by an intuitive visual display of all of the data from any sized data universe on a single screen. The data is indexed at multiple display levels such as a stack of one patient's data, a stack of all patient data for the universe of patients of a single practitioner, or a group of practitioners of any size. A portion of the display preferably may be selected and expanded to show only that portion in greater detail.
US09286442B2	Telecare and/or telehealth communication method and system A telecare and/or telehealth communication method is described. The method comprises providing predetermined voice messages configured to ask questions to or to give instructions to an assisted individual, providing an algorithm configured to communicate with the assisted individual, and communicating at least one of the predetermined voice messages configured to ask questions to or to give instructions to the assisted individual. The method further comprises analyzing a responsiveness and/or compliance characteristics of the assisted individual, and providing the assisted individual with voice messages in a form most acceptable and effective for the assisted individual on the basis of the analyzed responsiveness and/or the analyzed compliance characteristics.
US09286440B1	Self-contained emergency situation assistance kit with programmed audio and visual instructions An emergency response information and supply system, software and method capable of providing audio and/or visual or video instructions as to how to use the medical supplies contained in the kit and location information to emergency professionals. The system is organized so that the medical supplies for different traumas or emergency situations are packaged into individual and separated bags. The user can activate the audio and/or visual or video instructions by pushing at least one button on the unit's console that corresponds to the particular trauma or emergency event. Alternatively, instructions can be activated by removing a bag from the case which automatically begins the instructions. If a victim has sustained multiple injuries and the user has depressed multiple buttons or removed multiple bags, then the device automatically prioritizes the emergency situations and provides instructions on the appropriate emergency response to provide and in the proper order. The system can potentially notify emergency professionals and provide information on the status of a patient or first responder using the system.
US09286439B2	System and method for editing and manipulating DNA A system and method for planning, manipulating, processing and editing DNA molecules utilizing a core operation on a given input DNA molecule to produce a targeted DNA molecule.
US09286429B2	System and method for amplifier design At least one example embodiment discloses a method of generating parameters of an amplifier. The method includes displaying, by a processor, a graphical user interface on a display, the graphical user interface associated with input and output parameters of the amplifier, receiving input parameter values for the amplifier, generating output parameter values for the amplifier based on the obtained input parameter values and displaying the generated output values on the display.
US09286428B2	Boundary based power guidance for physical synthesis A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.
US09286426B2	Method and apparatus for testing A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.
US09286423B2	Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
US09286421B1	Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.
US09286420B1	Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.
US09286413B1	Presenting a service-monitoring dashboard using key performance indicators derived from machine data One or more processing devices cause display of a service-monitoring dashboard that includes one or more key performance indicator (KPI) widgets. Each KPI widget provides a numerical or graphical representation of one or more values for a corresponding KPI indicating how a service provided by one or more entities is performing at one or more points in time. Each entity of the one or more entities is associated with machine data. A KPI is defined by a search query that derives the one or more values represented by the corresponding KPI widget from the machine data associated with the one or more entities that provide the service whose performance is reflected by the KPI.
US09286410B2	Electronic document retrieval and reporting using pre-specified word/operator combinations An approach is provided for retrieving electronic documents. The approach provides a Web-based graphical user interface that allows users to construct complex queries that include Boolean clauses, proximity clauses and/or keyword phrases, without requiring the users to have a working knowledge of query languages. The Web-based graphical user interface also allows users to specify a semantic meaning for one or more search terms. The approach also allows users to generate various reports for search results. Various filters may be applied to manage the amount of reporting data and semantic meanings may be applied to increase relevancy. A time cost estimator provides an estimated review time for search results.
US09286409B2	Advanced URLs for web navigation A method, computer program product, and system for providing advanced downloading of Uniform Resource Locators (URLs) for a WEB browser running on a computer. The system is capable of providing a WEB browser with Uniform Resource Locators (URLs). The system comprises a client computer and a server. The client computer includes the WEB browser for use by a user and includes a URL component. The server provides WEB data to the client computer. The server includes a URL downloader, which is responsive to the URL component for downloading the URLs to the client computer.
US09286407B2	Bookmarking internet resources in an internet browser A method of bookmarking internet resources in an internet browser includes providing to a user an internet resource discovered by a search conducted via the browser in accordance with user supplied criteria; creating, responsive to a bookmarking request from the user, bookmark data having identifying data for the internet resource and an associated resource representation of the internet resource; and creating a hierarchy, for presentation to the user, of representations of internet resources for which bookmarking has been requested and of associated search criteria, each bookmarked resource representation being placed subordinate to corresponding associated search criteria representation in the hierarchy. A user can navigate to a bookmarked representation of a resource of interest via the corresponding associated search criteria representation for selection and subsequent retrieval of the resource of interest.
US09286401B2	Method of providing search service and display device applying the same A method of providing a search service and a display device applying the same are provided. According to the method of providing a search service, a web page that is searched by a specified keyword is accessed, at least one keyword is extracted from text included in the web page being accessed, and the at least one extracted keyword is displayed.
US09286399B2	Metadata management convergence platforms, systems and methods Metadata management convergence platforms, systems, and methods to organize a community of users' data records are presented. More specifically, methods are presented for managing metadata records related to content housed in unique, disparate or federated holdings in centralized or distributed environments. Also systems and methods for creating and managing metadata records using domain specific language, vocabulary and metadata schema accepted by a community of users of unique, disparate or federated databases in centralized or distributed environments are presented. Such environments can include digital multimedia repositories while providing for, but not limited to: the convergence, enhancement and management of metadata schemas that relate to content, information, networks, devices and users to deliver an interoperable multimedia-driven application infrastructure across a horizontal market.
US09286398B2	Systems and methods for retrieving data in a computer network A data retrieval system comprising a first computing device communicatively coupled to a second computing device; the first computing device having a processor that supports operation of at least one software application that is used for retrieving data; the second computing device communicatively coupled to one or more storage media; the software application having a retrieval module for retrieving data from the one or more storage media; a storage and backup map that maps to the second computing device; and a data index stored on the second computing device that indicates to the retrieval module a particular location of the data that is to be retrieved by the retrieval module.
US09286395B1	Modifying query in discourse context Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for modifying queries in a discourse context. In one aspect, a method includes determining whether a query received from a user device subsequent to information provided to a user device and that defines a discourse context belongs to the discourse context. If the query belongs to the discourse context, the query is modified to take into account attributes of the discourse context.
US09286390B2	Presentation of rich search results in delineated areas Search results are provided with rich content in defined display areas defined via a border, background, other like graphical elements, or combinations thereof. Within the defined display area, search results content is formatted to evoke a particular theme or concept appropriate for the information identified by the search result. Additionally, within the defined display area, a graphical preview of the search result is provided in an animated manner evocative of user scrolling. Collections of search results are arranged in grids, like tiles. Search results are reviewed on a grid-by-grid basis, with small portions of prior, or subsequent, grids being displayed at the edges of the display, thereby visually indicating that further, or subsequent, grids are accessible. Alternatively, other grids can represent different types of search results. The quantity in a grid, and their size, are dynamically adjusted based on the size of the display.
US09286387B1	Double iterative flavored rank Determining the relevance of a web node is disclosed. A seed score value of a first type is assigned to a seed set of nodes. A score value of a second type is derived for the web node based on a mapping of a reachability relationship between one or more seed nodes and the web node. A score value of the first type is derived for the web node based on a mapping of a reachability relationship between the web node and one or more evaluation nodes having derived weight values of the second type.
US09286385B2	Method and system for providing access to information of potential interest to a user The present invention provides a method and system for providing access to information of potential interest to a user. Closed-caption information is analyzed to find related information on the Internet. User interactions with a TV which receives programming including closed-caption information are monitored to determine user interests or topics.
US09286380B2	Social media data analysis system and method A system analyzes data to determine an activity around a product. The system includes a user interface configured to enable one or more data analysts to provide input data and an acquisition module coupled to user interface and configured to retrieve social media data in response to the input data. The social media data is received from one more social media platforms. The system further includes processing circuitry coupled to the acquisition module and includes an analysis module configured to analyze the social media data to generate processed data and classify the processed data based on a plurality of criteria and a visualization module coupled to the analysis module and configured to generate a plurality of visual representations of classified data.
US09286377B2	System and method for identifying semantically relevant documents A system and method for identifying semantically relevant documents is provided. An index having semantic index key terms from one or more documents is maintained. A query is obtained and semantic key terms of the query are identified. Each of the query key terms are associated with information, including use of the word and a grammatical role of the word. Each of the query key terms and variants of the query key terms is looked up in the index based on the information. One or more of the documents in the index are identified as possible relevant candidates based on the look up. A potential match candidate set is generated by filtering the possible relevant candidates. At least one of the documents that match the query is identified by comparing a semantic representation for each non-filtered potential match candidate in the set with a semantic representation for the query.
US09286368B2	Linking framework for information technology management A data synchronization task is received at a console, wherein the data synchronization task is associated with information technology management. A configuration document is configured using the data synchronization task, wherein the configuration document defines data synchronization through declarations. A linking framework is configured based on the configuration document. Data is synchronized from a first and second source to a target as defined by the configuration document.
US09286362B2	System and method to customize metadata for different users running on the same infrastructure A metadata management system and method enables complex query searches by users, e.g., different users having different query needs, using the same infrastructure. For querying metadata, the metadata management system provides functionality for aggregating all the concepts (metadata items) and relationships of the metadata across one or more users in a common format; extracting concepts and storing them in a metadata store (e.g., a relational database); extracting relationships and modeling them in a standard semantic representation. The system and method further records users' different needs on relationships into user-specific configuration files. The system is configured for retrieving, in response to a user query, relevant data items by using the meta-data selectively. In one embodiment, a selection of meta-data used in the retrieving is determined according to captured context information.
US09286361B2	Extract-transform-load processor controller A controller is coupled to an Extract-Transform-Load (ETL) processor, which is connected to data storage devices. The controller comprises: a hardware storage device; a storage control component for storing, on said hardware storage device, a set of criteria for preferredness of ETL stage placements; an I/O input device detecting component for recognizing a proposed placement of a stage on a GUI canvas on the display device; an analytical component for analyzing an eventual result of the proposed placement in an ETL activity represented on the GUI canvas; a comparator for comparing the eventual result of the proposed placement in the ETL activity with the set of criteria; and an indicator control component for, responsive to an outcome of an operation of the comparator, providing to the user an indicator of a degree of preferredness of said proposed placement according to the set of criteria.
US09286359B2	Providing enhanced business listings with structured lists to multiple search providers from a source system A source server receives listing identification data for transmission of an enhanced listing comprising enhanced content to a plurality of provider servers. For each provider server of the plurality of provider servers, the source server transmits to the provider server the listing identification data. When the source server determines that an identifier corresponding to the listing identification data that indicates the listing is present on the provider server does not exist in a database associated with the source server, the source server searches the provider server for a matching listing based on the received listing identification data. When the source server determines that a matching listing exits on the provider server, the source server transmits to the provider server the enhanced listing with the identifier employed by the provider server as an indication to the provider server to update the listing on the provider server with the enhanced content.
US09286356B1	Adjusting a ranking of search results A method performed by one or more processing devices includes obtaining search results responsive to a search query submitted by a user; determining a maturity score for the user, where the maturity score represents a measure of development of a particular user attribute; determining, based on the maturity score, utility scores for the search results, where a utility score represents a measure of utility of a particular type of content to a particular type of user as defined by the measure of development of the particular user attribute; and adjusting rankings of the search results based on the utility scores.
US09286354B2	Systems and/or methods for forecasting future behavior of event streams in complex event processing (CEP) environments Certain example embodiments described herein relate to forecasting the future behavior of event streams in Complex Event Processing (CEP) environments. For each received event in an event stream, a reference window indicative of a predefined temporal range during which the forecast is to be computed is updated so that the reference window ends with the received event, with the reference window moving with the event stream. Within this processing loop, when a forecasting update policy indicates that the forecast is to be updated based on the received event: a forecasting window indicative of a temporal range in which events are to be forecasted is updated; and while the time period of the forecasting window is not exceeded, (a) a next forecasted event is generated via at least one processor and (b) the next forecasted event is inserted into the forecast window; and the forecast window is published.
US09286352B2	Hybrid execution of continuous and scheduled queries Techniques for implementing the hybrid execution of continuous and scheduled queries are provided. In some examples, a query engine may be initialized with relational data from at least a first source. For example, the first source may include a database or other system that can provide historical data. Additionally, the query engine may be enabled to provide query results based at least in part on the relational data from at least the first source and streaming data from at least a second source. In some examples, the second source may be a data stream.
US09286350B2	Estimating most frequent values for a data set Provided are techniques for estimating most frequent values. A sample of values made up of rows is received from each of multiple nodes. The sample of values from each of the multiple nodes are aggregated to generate a sample table storing the rows. A descending list of most frequent values and associated frequencies is obtained using the sample table. Most frequent values are pruned from the descending list whose associated frequencies are below a minimum absolute frequency. The remaining most frequent values are extrapolated to reflect a data set.
US09286349B2	Dynamic search system A method is described of dynamically searching a search domain. A first result set of data objects is presented. The first result set is obtained from a first search of a search domain having active and inactive data objects for first search features obtained from a source data object. An update is detected in the search domain. Key features are extracted from the source data object to be included in second search features when the update in the search domain is in the source data object. A second search of the updated search domain is performed for data objects having the second search features.
US09286345B2	Query tree navigation System, computer implemented method and computer program product for preparing and navigating a query tree including a plurality of query nodes and informational nodes. Each query node is associated with a prompt, branching criteria and keywords. A current query node provides a prompt to a user and a user response is received and analyzed to identify branching criteria and keywords from the user response. The method navigates to another node in the query tree in consideration of the branching criteria received in the user response and a comparison between the keywords received in the user response and the keywords associated with the query nodes. The comparison may validate navigation to a destination node corresponding to the branching criteria or the comparison may indicate incorrect navigation of the query tree. Corrective navigation can be implemented in various ways based upon the keywords received in the user response.
US09286342B1	Tracking changes in on-line spreadsheet A computer-implemented method for method for tracking changes in an internet-accessible document is disclosed. The method includes providing, with a presentation server system, data for producing a display of a document at a client computing device; receiving, at the presentation server system from a data server system, a timestamp that is sent by the data server system in response to an indication by a user of the client computing device to record changes to the document, wherein the timestamp indicates a time after which changes have been made to the document; and providing from the presentation server system to the data server system data indicating changes made to the document since a time corresponding to the timestamp.
US09286339B2	Dynamic partitioning of a data structure A method for dynamically partitioning a B-tree data structure, includes: determining if the B-tree data structure requires a partition; establishing a midpoint of the B-tree data structure; migrating from a beginning of the B-tree data structure to the midpoint of the B-tree data structure to a first B-tree data structure; migrating from the midpoint of the B-tree data structure to an end of the B-tree data structure to a second B-tree data structure; and allowing normal operations on the B-tree data structure during migration.
US09286336B2	Unified architecture for hybrid database storage using fragments Data records of a data set can be stored in multiple main part fragments retained in on-disk storage. Each fragment can include a number of data records that is equal to or less than a defined maximum fragment size. Using a compression that is optimized for each fragment, each fragment can be compressed. After reading at least one of the fragments into main system memory from the on-disk storage, an operation can be performed on the fragment or fragments while the in the main system memory.
US09286335B1	Performing abstraction and/or integration of information Abstraction and/or integration can be performed on information, e.g. transaction data items in standard and/or proprietary formats, using data processing systems. For example, standard-based abstraction operations can analyze transaction data items in standard format to obtain transaction segment data items, each about a transaction segment; transaction segment data items can be used to obtain and store segment group data structures, each about a type of transaction segment data items and which can also include standard-based abstraction artifacts. Abstraction operations on standard or proprietary format can automatically extract pre-integration information, such as usage attributes. A resulting data structure can include test case scenarios, each a combination of segment group data structures with usage attributes. Integration can be performed on transaction type attribute data, producing integration attributes such as merged attribute data. A universal integration attribute language can be used, allowing comparison of segment group data structures from different proprietary formats.
US09286333B2	Stream compression and decompression A method for compressing a sequence of records, each record comprising a sequence of fields, comprises steps of buffering a record in a line of a matrix, reordering the lines of the matrix according to locality sensitive hash values of the buffered records such that records with similar contents in corresponding fields are placed in proximity, and consolidating fields in columns of the matrix into a block of codes. In this, consolidating yields codes of one of a first type comprising a sequence of individual fields and a second type comprising a sequence of fields with at least one repetition. The second type of code comprises a presence field indicating repeated fields and an iteration field indicating a number of respective repetitions. Decompression of the records from the block codes compressed above is also described.
US09286329B2	Generating analytics application using reusable application modules Analytics applications are generated using application modules. An application module stores metadata for use in an analytics application. The application module is associated with one or more data fields that correspond to data used in the analytics reports of an application module. An application module may be a composite application module that includes other application modules. An analytics application is generated from a specification including a set of fields. The set of data fields of the specification are matched against the data fields of the application modules. An application module matches the specification of the analytics application if the specification includes all the data fields of the application module. All matching application modules are selected and sent for deployment of the analytics application. The analytics application generated is configured to present information based on analytics reports.
US09286326B1	System and method for selecting sponsored images to accompany text A system for selecting an image to accompany text from a user in connection with a social media post. The system includes receiving text from the user; identifying one or more search terms based on the text; identifying candidate images from images in one or more image databases using the search terms, where the candidate images comprise a sponsored image; presenting one or more candidate images to the user, where the sponsored image is presented preferentially compared to other candidate images; receiving from the user a selected image from the one or more candidate images; generating the social media post comprising the selected image and the user-submitted text; and transmitting the social media post for display.
US09286321B2	Systems and methods for providing an automated validity check of transactional data postings Systems and methods are provided for providing an automated validity check of transaction data postings. In one implementation, a method is provided that includes entering at least one code for specifying at least one posting to be performed for a transactional data processing operation. The method may also include starting the transactional data processing operation, sending a request to a service component for performing a validity check of the at least one code, buffering one or more posting requests resulting from execution of the transactional data processing operation. Further, the method may include sending, in response to receipt of a first signal indicative of code validity from the service component, the one or more buffered posting requests with the at least one code to a posting component.
US09286320B2	System and method for maintaining consistency among metadata elements of filesystem's logical objects A method for maintaining consistency among metadata elements (MDEs) of a logical object, includes: configuring a child MDE to include a correlation value uniquely indicative of a parent MDE. The parent MDE includes a reference to the child MDE; determining an order of performing at least two write operations included in a transaction related to the logical object: at least one write operation with respect to the parent MDE and at least one write operation with respect to the child MDE; the determined order assures that the child MDE is indicated as existing and includes the first correlation value, as long as the parent MDE exists; upon a first access to the parent MDE, subsequent to the transaction, verifying consistency between the parent MDE and the child MDE, using the first correlation value; and deleting the parent MDE if the verifying of consistency is unsuccessful.
US09286313B1	Efficient lossless reduction of data by deriving data from prime data elements resident in a content-associative sieve This disclosure relates to lossless data reduction on large and extremely large datasets while providing high rates of data ingestion and data retrieval. Some embodiments can generate a losslessly reduced representation of a data chunk, wherein the losslessly reduced representation includes a reference to one or more prime data elements stored in a prime data store, and optionally a description of a reconstitution program which, when applied to the one or more prime data elements results in the data chunk.
US09286305B2	Virtual storage gate system An example embodiment includes a distributed file management system. The distributed file management system includes a central storage device that is communicatively coupled to data repositories configured to store one or more files. The central storage device includes a processor and a tangible computer-readable storage medium. The tangible computer-readable storage medium is communicatively coupled to the processor and has computer-executable instructions stored thereon that are executable by the processor to perform operations. The operations include receiving file access requests from the data repositories. The operations also include transmitting location information of files requested in the file access requests. The location information includes internet protocol (IP) addresses of the data repositories on which the files are stored. The operations also include receiving updated file indices from the data repositories indicating remote access to files and updating a central access log and a central file index to include the updated file indices.
US09286299B2	Backup of data items A method and system for automatic backup of desktop items is described.
US09286298B1	Methods for enhancing management of backup data sets and devices thereof A method, non-transitory computer readable medium, and apparatus that enhance management of backup data sets include receiving an operation on a region of a production data set. A corresponding region of a backup data set is marked as having a change state status until the received operation is completed on the region of the production data set and mirrored on a corresponding region of a backup data set.
US09286296B2	Mobile terminal and method of controlling the same Disclosed herein are a mobile terminal and a method of controlling the mobile terminal. The mobile terminal may include a radio communication interface, a storage device configured to store a content playlist, and a controller configured to update the content playlist. The controller may acquire content information corresponding at least one streaming content from on a web page accessed through the radio communication unit interface. The content information may include address information for retrieving the at least one streaming content. The controller may update the content play list to include the at least one streaming content based on the acquired content information.
US09286295B2	Apparatus and method for cloud based storage using a multi-layer scannable tag An apparatus and method for cloud-based storage, retrieval and sharing of files tagged with scannable tags and alphanumeric coding is provided. This application and method includes: either scanning a scannable tag by mobile device or inputting a code into a computer; decoding of the scannable tag or text provided, by installed application; accessing, by a cloud based storage system which hosts the associated or tagged file; and retrieving the file associated with the scannable tag or alphanumeric code. This method also includes a process by which: either by smart phone or personal computer; uploading or storing of files onto a cloud-based storage system; tagging of those stored files with a unique scannable tag and alphanumeric code; generating a scannable tag and alphanumeric code to associate with those tag files; and a method of transmitting scannable tag or alphanumeric codes between smart-phone users or computer uses for the purposes of sharing extra information with others using momentos.
US09286291B2	Disambiguation of dependent referring expression in natural language processing A system, and computer program product for disambiguation of dependent referring expression in natural language processing are provided in the illustrative embodiments. A portion of a document in a set of document is selected, the portion including a set of dependent referring expression instances. The portion is filtered to identify an instance from a set of dependent referring expression instances by using a linguistic characteristic of the instance, the instance of dependent referring expression referring to a full expression occurring in the set of documents. The full expression is located in one member document in the set of documents by locating where the dependent referring expression is defined to be a stand-in for the full expression. The instance is resolved using the full expression such that information about the full expression is available at a location of the instance.
US09286287B1	Reference content determination from audio content Systems and methods are provided for causing aural and/or visual presentation of reference content, such as word definitions, in response to a request regarding a portion of media content during playback. In some embodiments, one or more words may be determined that may be of interest to the user from among words in a content window preceding a current playback position in the content, without the user specifying a specific word of interest. A presentation of reference content corresponding to the determined one or more words may be generated and presented aurally and/or visually in order to provide definitions, encyclopedia information, summary information, and/or other information regarding a portion of media content near the current playback position.
US09286286B1	Method, apparatus, and computer program product for optimizing parameterized models using functional paradigm of spreadsheet software The present disclosure provides a method, an apparatus, and a computer program product to interact with a spreadsheet application for computing the value of a formula that depends explicitly or implicitly on one or more cells designated as variables, based on provided values for the variables, and without modifying any data of the spreadsheet application. In one aspect, the present disclosure provides an optimization process executed by spreadsheet functions of a spreadsheet application, and arranged in a functional paradigm for computing optimal parameters for a parameterized system modelled by variables, parameters, and dependent formulas.
US09286277B2	Inputting in a textbox Inputting in a textbox comprises: monitoring a related event of inputting text in a textbox; providing an extended window for displaying excess text in response to detecting that the text exceeds the textbox; hiding the extended window, and storing a state of inputted context and the inputted text in response to a monitored event that the textbox loses focus; and displaying the extended window and the textbox, with their text, according to the stored state of inputted context in response to monitoring again the related event of inputting text in the textbox after monitoring the event that the textbox loses the focus. A global view can thus be provided for a user, whereby the user is capable of seeing at one time the content as a whole inputted by himself/herself, and immediately locating the last text inputted when the user leaves the textbox and then comes back for inputting.
US09286273B1	Method and system for implementing a website builder A method and system for a site builder. The site builder is an application designed to create and edit websites for hosting providers, resellers and end users. Built with hosting in mind, the proposed site builder allows providers to easily offer site building capabilities to their customers. The easy five-step wizard interface provides for an effortless way for customers to create, modify and update their own websites without any technical skills or HTML know-how. The site builder application for LINUX/Unix or WINDOWS also comes with a comprehensive administration panel that allows providers to quickly and easily tailor the application to their needs.
US09286272B2	Method for transformation of an extensible markup language vocabulary to a generic document structure format A method determines structures and features of an original document to make style decisions. The extensible markup language of the original document is analyzed to produce instance mapping. The document type definitions of the original document are analyzed to produce document type definitions mapping. Lastly, the instance schema of the original document is analyzed to produce schema mapping. A transform is generated from the produced instance mapping, document type definitions mapping, and schema mapping. The transform is applied to the original document to generate an instance in an intermediate format. A stylesheet is selected and applied to the intermediate format to produce a styled document.
US09286265B2	Device and method for managing an electronic control unit of a vehicle An add-on device and method for managing an electronic control unit (ECU) of a vehicle is disclosed. The add-on device includes a transceiver adapted for communicating with the communication network of a vehicle. The add-on device further includes a controller being communicatively connected to the transceiver, and adapted to generate a user-interface control signal addressed to the user interface of the vehicle, in order to manipulate the user interface of the vehicle and to present thereon command options prompting a user to enter a command selection in response to the command options presented. The controller is further adapted to receive the command selection from the user interface, and to generate in response thereto, an ECU control signal to be sent to the communication network for executing an operation with respect to a targeted ECU, in order to manage the targeted ECU from the user interface of the vehicle.
US09286260B2	Serial-to parallel converter using serially-connected stages A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using serially-connected stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage.
US09286258B2	Opaque bridge for peripheral component interconnect express bus systems A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.
US09286257B2	Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
US09286255B2	Motherboard A motherboard includes a platform controller hub (PCH) chip, a connector, and a switch chip. The PCH chip includes a first group of pins and a second group of pins. The switch chip is connected to either the first group of pins or the second group of pins according to a type of a card connected to the connector.
US09286254B2	Microcontroller programmable system on a chip with programmable interconnect Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
US09286245B2	Hardware enforced memory access permissions Embodiments of apparatuses and methods for hardware enforced memory access permissions are disclosed. In one embodiment, a processor includes address translation hardware and memory access hardware. The address translation hardware is to support translation of a first address, used by software to access a memory, to a second address, used by the processor to access the memory. The memory access hardware is to detect an access permission violation.
US09286244B2	Method and device for monitoring an unauthorized memory access of a computing device, in particular in a motor vehicle A method and a device for monitoring an unauthorized memory access to a predetermined memory area in a computing device are described, in which a monitoring medium is provided, having at least one sensor medium, which is set up for the purpose of recognizing an event of the computing device, and at least one recognition medium, which is set up for the purpose of tracking the behavior of the event recognized by the sensor medium, the monitoring medium being integrated into a sequence pattern on the computing device, and the monitoring medium being set up for the purpose of monitoring the sequence pattern at its runtime, in that memory accesses to a memory address or an address range are detected by the monitoring medium as events.
US09286243B2	Logical-to-physical address translation for a removable data storage device A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.
US09286242B2	Information processing apparatus and program execution method According to one embodiment, an information processing apparatus includes a processor, a main memory, and a memory controller. The memory controller executes an access restriction for each memory region. A first program decodes a protected program which was encrypted in a secure mode. The first program places the protected program which was decoded in a memory region. A second program executes the protected program in a secure mode. The processor places a code region and a protected data region in the protected program which was decoded in a memory region having an access restriction by using the first program. When an access to the protected data region is confirmed, the processor confirms by using the second program that the access is caused by a command from the code region placed by the first program, and then, executes the command.
US09286241B2	Cryptographic transmission system A microcontroller includes on-chip key storage slots stored in a non-volatile memory, wherein selecting which key is to be used is restricted to software, wherein a predetermined key storage slot stores a Key Encrypt Key (KEK), and a register flag is provided for determining whether the predetermined key storage slot stores a key for encrypting/decrypting data or the KEK for encrypting/decrypting a key.
US09286240B1	Systems and methods for controlling access to content in a distributed computerized infrastructure for establishing a social network A computer-implemented method for storing content, the stored content being accessible by a computerized system comprising at least one central processing unit, memory, storage system and a network interface unit, computerized system being accessible by a user, the method comprising: generating first cryptographic key; encrypting the content with the first cryptographic key; storing the encrypted content in a data storage system, the data storage system comprising at least one data storage medium; a data storage controller and a network interface module, the data storage system being a part of a cloud-based distributed storage system, the cloud based storage system being connected via a data network with computerized system accessible by the user; generating a second cryptographic key; and re-encrypting the content with the second cryptographic key and storing the re-encrypted content in data storage system, wherein the re-encryption of the content is performed within cloud-based distributed storage system.
US09286232B2	Administering registered virtual addresses in a hybrid computing environment including maintaining a cache of ranges of currently registered virtual addresses Administering registered virtual addresses in a hybrid computing environment that includes a host computer, an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining a cache of ranges of currently registered virtual addresses, the cache including entries associating a range of currently registered virtual addresses, a handle representing physical addresses mapped to the range of currently registered virtual addresses, and a counter; determining whether to register ranges of virtual addresses in dependence upon the cache of ranges of currently registered virtual addresses; and determining whether to deregister ranges of virtual addresses in dependence upon the cache of ranges of currently registered virtual addresses.
US09286230B1	Sparse volume management cache mechanism system and method A method, computer program product, and computer system for instantiating, by a computing device, a slice-object associated with a slice when the slice-object is accessed. The slice-object is released to a slice object cache when accessing is complete. It is determined whether the slice is accessed within a threshold period of time. If the slice is accessed within the threshold period of time, the slice-object is retrieved from the slice-object cache. If the slice is not accessed within the threshold period of time, memory used for the slice-object is released.
US09286228B2	Facilitating caching in an image-processing system Embodiments of the present invention provide a system for performing caching in an image-processing system. The system starts by receiving a filtering query for resources in a cache. The system then returning a subcache in response to the filtering query. Upon receiving a resource query for resources in the subcache, the system performs the filtering query on the cache, populates the subcache with addresses of resources returned by the filtering query until the resource query is satisfied, and returns available resources from the subcache in response to the resource query.
US09286227B2	Efficient processing of cache segment waiters For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks is initiated, and the at least one complete data track is removed off of a free list by a first I/O waiter.
US09286223B2	Merging demand load requests with prefetch load requests A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.
US09286222B2	Data processing apparatus and method for transferring workload between source and destination processing circuitry In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry.
US09286221B1	Heterogeneous memory system A heterogeneous memory system includes a main memory arrangement, a first-level cache, a second-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and the second-level cache includes a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the first-level cache or the second-level cache for storage of the first data and stores the first data in the selected one of the first or second-level caches. The MMU reads second data from one of the first-level cache or second-level cache and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.
US09286212B2	Semiconductor device and method of controlling non-volatile memory device A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.
US09286211B2	Health reporting from non-volatile block storage device to processing device Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service.
US09286207B2	Method of managing the endurance of non-volatile memories The invention relates to a method for managing the endurance of a data storage system provided with a set of sectors endowed with a guaranteed native endurance capacity (G), comprising the steps consisting in: —partitioning said data storage system into a plurality of work sectors, and into a plurality of replacement sectors able to form an endurance reservoir, certain of the work sectors being intended to be replaced by replacement sectors when said work sectors are expended after a certain number of programming and/or erasure cycles; —defining an address management area making it possible to retrieve the location of the replacement sectors assigned to expended work sectors; —determining, sector by sector, whether a current work sector is physically expended, and executing a step of replacing this work sector by a replacement sector, only when said current work sector is declared physically expended. This method of managing endurance is in particular characterized in that in order to measure the expenditure of a sector, automatic reading of the quality of erasure of the memory points of the sector with respect to a severized reading criterion (margin Vref.) is carried out, that is to say one which is more severe than a normal criterion (Normal Vref.).
US09286205B2	Apparatus and method for phase change memory drift management A system and method are described for selecting a demarcation voltage for read and write operations. Embodiments of the invention provide a scheme to use multiple VDMs to cover the case where power-on drift is different from power-off drift of the PCMS cells. The controller automatically manages this through tracking refreshes and writes. In addition, the embodiments of the invention provide an efficient scheme to reduce the performance impact of the penalty box following a write by tracking recent write addresses through a hash-table or similar scheme. By way of example, a method in accordance with one embodiment comprises: detecting a read operation directed to a first block of a PCMS memory; determining whether a write operation has previously occurred to the first block within a specified amount of time prior to the read operation; using a first demarcation voltage (VDM) for the read operation if the write operation has previously occurred to the first block within the specified amount of time prior to the write operation; and using a second VDM for the read operation if the write operation has not previously occurred to the first block within the specified amount of time prior to the write or refresh operation.
US09286197B2	Method and system of testing software using real time replication Method and system of testing software using real time replication. At least some illustrative embodiments are methods comprising interacting (by a human tester) with a first software program executed on a first computer system (the interacting causes an operation to be performed on the first software program), duplicating the operation on a second software program executed on a second computer system coupled to the first computer system (the duplicating on the second computer system in real time with the interacting and the duplicating without a human tester), programmatically analyzing a result of the operation on the first computer system against a result of the operation on the second computer system, and notifying the human tester (by way of the first computer system) when the result of the operation on the second computer system is unexpected.
US09286193B2	Prioritization and assignment manager for an integrated testing platform A method of prioritizing and assigning test scripts is provided in a testing platform configured to organize, manage, and facilitate the debugging of test scripts. The test scripts are used in testing software modules. The method includes receiving a plurality of test scripts, applying a predetermined set of factors to each test script, and assigning a weight value to each factor based on a relative importance of the factor. A priority value is set for each test script based on the weighted factors, and the test script is assigned to a queue position for execution based on the corresponding priority value, where the assigned test script is associated with one or more bias factors. The test script is then selected from the testing queue and forwarded if the bias factors indicate that requirements of the test script match corresponding bias factors of the testing individual.
US09286189B2	Self-evolving computing service template translation Methods and apparatus for automatically generating translation programs for translating computing services templates to service blueprints are disclosed. An example method includes generating a population of translation logic elements from a plurality of verified computing services template translation programs, where each of the verified programs is configured to correctly translate at least one computing services template of a plurality of known templates to a respective service blueprint. The example method further includes identifying a new computing services template and programmatically augmenting the population of translation logic elements. The example method also includes generating one or more additional translation programs based on the augmented population of translation logic elements and validating each of the one or more additional computing services template translation programs. Based on the validating, each of the one or more additional computing services template translation programs is added to the verified translation programs or is discarded.
US09286187B2	Static enforcement of process-level security and compliance specifications for cloud-based systems Implementations of the present disclosure are directed to statically checking conformance of a computer-implemented service at a source code level to requirements specified at a process level and include actions of receiving source code of the computer-implemented service, receiving one or more rules, the one or more rules being generated based on a mapping and including a set of technical requirements that can be checked on the source code level, the mapping associating the requirements with the source code, and processing the source code and the one or more rules using static code analysis (SCA) to generate a result, the result indicating whether the computer-implemented service conforms to the requirements.
US09286184B1	Probabilistic correlation of system events with program instructions A method and system for associating system events with program instructions in a computer system are disclosed. A program is executed or manually processed to identify instructions which cause system events. Then, markers are inserted into the program, each marker being associated with at least one of the identified instructions. When the program is executed, system events which occur during the execution are associated with program instructions using the markers.
US09286180B1	Final result checking for system with pre-verified cores Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core.
US09286179B1	Service testing framework Disclosed are various embodiments for a service testing application. A service testing application executes test operations for services in a service-oriented architecture. If a test is failed, services that are dependent upon a failing service are reconfigured to instead call a corresponding service in a different installation of the service-oriented architecture. A dependency model of the service-oriented architecture may be searched to determine which service dependencies to reconfigure.
US09286178B2	Controller, storage apparatus, method of testing storage apparatus, and computer-readable storage medium A controller includes an address generator that sets a plurality of different paths, each connecting an information processing apparatus connected to a storage apparatus via a network, first and second storage mediums, and the controller, and generates a second address that is different from a first address used for a communication with the information processing apparatus via the network; an access monitor that determines that no access has been issued for a certain time duration from the information processing apparatus to the first or second storage medium; an access issuing unit that issues a test access to the first and second storage mediums on one of the paths, using the second address; and an access decoder that converts the test access to an access including the first address, receives a result of the access including the first address from the first or second storage mediums, and checks for an error.
US09286170B2	Preventing extreme coresidency hazards in cloud computing Various exemplary embodiments relate to a method of preventing extreme coresidency hazards among application instances in a cloud network. The method includes determining a first failure group of a first instance of an application; establishing a connection with a second instance of a peer application; determining a second failure group of the second instance; comparing the first failure group to the second failure group; and establishing a second connection with a third instance of the peer application if the first failure group and the second failure group share a failure point.
US09286166B2	Electronic backup of applications Systems and methods are provided for storing and restoring digital data. In some implementations, a method is provided. The method includes receiving, while a current view of an application is displayed in a user interface, a first user input requesting that a history view associated with the current view of the application be displayed, retrieve data associated with the history view, determining a presentation format for the data, and displaying the history view in response to the first user input in accordance with the presentation format, the history view including data associated with at least a first visual representation of an earlier version of the current view of the application.
US09286162B2	System and method for guaranteeing consistent data synchronization from a volatile data source Systems and methods for, among other things, updating a destination data set of hierarchical data in relation to a source set of hierarchical data. The method, in certain embodiments, includes receiving an indication that the source data set has one or more changes, initiating a comparison between the source data set and the destination data set, identifying differences and related hierarchical relationships, and altering the destination data set by performing changes in an order that preserves the hierarchical relationships. The method may use the change notifications as an indicator to start the comparison and restart the comparison upon the receipt of a new notification. By using this method, the two data sets can be kept synchronized while preserving hierarchical relationships between the data elements in an environment where the source data set experiences unpredictable changes and cannot be locked.
US09286157B2	Address detection circuit and memory including the same An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units.
US09286156B2	Data storage device and method for processing error correction code thereof A data storage device includes a data storage medium, and an error correction code unit configured to process an error correction code for data to be stored in the data storage medium. The error correction code unit includes a storage block configured to store the data to be stored in the data storage medium, and an encoder configured to divide the data stored in the storage block into a plurality of data groups according to an address of the storage block, to encode the plurality of data groups, to encode a plurality of parity data groups that are generated by encoding the plurality of data groups, and to generate final parity data.
US09286151B2	Computerised storage system comprising replaceable units for managing testing of replacement units A method for use in a computerized storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode.
US09286150B2	Dynamic band boundaries Systems and methods are disclosed for dynamic band boundaries in data storage devices, particularly devices employing shingled magnetic recording. Band boundaries may be modified to include spare sectors from guard areas between bands to achieve field defect-slipping. Band boundaries can also be shifted to migrate spare sectors from one guard area to another in order to dynamically distribute spare sectors. In one embodiment, an apparatus may comprise a data storage medium and a controller. The data storage medium may have a first and second sequence of circumferentially adjacent data sectors, and a first guard area disposed between the first and second sequence such that no sector of the first sequence is directly adjacent to a sector of the second sequence. The controller may be configured to restructure the first sequence to include a sector from the first guard area to produce a shifted first sequence.
US09286149B2	Enhanced error detection with behavior profiles Methods, systems, and computer-readable media for detecting errors within a system by using behavior profiles are presented. At a first time, user requests may be received and serviced. The serviced user requests may be logged. Based on the logged user requests, profiles may be determined. At a second time, user requests may be received and serviced. The serviced user requests may be logged. The logged serviced user requests may be compared to the profiles determined at a first time. For example, the determined profiles may include an error rate for serviced user requests. At the second time, an error rate for the logged serviced user requests may be compared to an error rate included the determined profiles. Serviced users requests may be flagged based on the comparison.
US09286148B1	Hardware-assisted interthread push communication In a data processing system, a switch of the data processing system receives a request to push a message referenced by an instruction of a sending thread to a receiving thread. In response to receiving the request, the switch determines whether the sending thread is authorized to push the message to the receiving thread by attempting to access an entry of a data structure of the switch utilizing a key derived from at least one identifier of the sending thread. In response to access to the entry being successful, content of the entry is utilized to determine an address of a mailbox of the receiving thread, and the switch pushes the message to the mailbox of the receiving thread. In response to access to the entry not being successful, the switch refrains from pushing the message to the mailbox of the receiving thread.
US09286146B2	Multi-application workflow integration Techniques are described for managing interactions between workflows being performed by different applications, such as to enable a combination of multiple workflows in multiple applications of different types to aggregate varying capabilities available from the different types of applications. In some situations, an integrated workflow is created by separating portions of its functionality into multiple constituent workflows that is each performed by a different application and that initiate one or more inter-workflow interactions between the constituent workflows as they are performed (e.g., for one of the constituent workflows to, while it is being performed, invoke another constituent workflow in order to begin its performance). As one non-limiting example, the multiple applications of different types may include a least an enterprise business application program that provides various core business functions, and a desktop collaborative application program that provides various user activity management capabilities.
US09286145B2	Processing data communications events by awakening threads in parallel active messaging interface of a parallel computer Processing data communications events in a parallel active messaging interface (‘PAMI’) of a parallel computer that includes compute nodes that execute a parallel application, with the PAMI including data communications endpoints, and the endpoints are coupled for data communications through the PAMI and through other data communications resources, including determining by an advance function that there are no actionable data communications events pending for its context, placing by the advance function its thread of execution into a wait state, waiting for a subsequent data communications event for the context; responsive to occurrence of a subsequent data communications event for the context, awakening by the thread from the wait state; and processing by the advance function the subsequent data communications event now pending for the context.
US09286144B1	Handling context data for tagged messages The subject disclosure relates to a machine-implemented method handling context data for tagged messages. The method includes identifying a tagged message, wherein the tagged message is generated by a user and includes content, obtaining context data associated with the tagged message, wherein the context data is obtained based on at least one of user input for the tagged message or server data for the tagged message, and providing access to the tagged message according to the obtained context data.
US09286143B2	Flexible event data content management for relevant event and alert analysis within a distributed processing system Methods, systems, and computer program products for flexible event data content management for relevant event and alert analysis within a distributed processing system are provided. Embodiments include capturing, by an interface connector, an event from a resource of the distributed processing system; inserting, by the interface connector, the event into an event database; receiving from the interface connector, by a notifier, a notification of insertion of the event into the event database; based on the received notification, tracking, by the notifier, the number of events indicated as inserted into the event database; receiving from the notifier, by a monitor, a cumulative notification indicating the number of events that have been inserted into the event database; in response to receiving the cumulative notification, retrieving, by the monitor, from the event database, events inserted into the event database; and processing, by the monitor, the retrieved events.
US09286142B2	Methods and systems for supporting a rendering API using a runtime environment A computing device can comprise an I/O interface and a processing element connected to the I/O interface and implementing a runtime environment. The processing element can implement a program component that causes the processing element to expose a rendering API not natively supported by the runtime environment, the rendering API invocable by code comprised in a markup document accessed by the processor over the I/O interface. The rendering API can be exposed by causing the runtime environment to respond to and update a proxy object that mirrors properties, methods, and behaviors defined by the rendering API.
US09286141B2	Image forming apparatus, program management system, program management method, and computer-readable storage medium An image forming apparatus may be coupled to another image forming apparatus that manages first programs using a first program execution environment providing part in response to a request in accordance with first interface specifications using a predetermined communication protocol. The image forming apparatus manages second programs using a second program execution environment providing part that has a structure different from that of the first program execution environment providing part in response to an a request in accordance with second interface specifications, accepts the request in accordance with the first interface specifications, and converts the accepted request into a request in accordance with the second interface specifications to be input to the program management part.
US09286137B2	Achieving deterministic execution of time critical code sections in multi-core systems Systems and methods may provide for detecting a time critical code section associated with a real time processor core and suspending execution on a suspendable processor core in response to the time critical code section. Additionally, execution on the suspendable core may be resumed when the real time processor core reaches the end of the time critical code section. In one example, execution is suspended by issuing an inter-processor interrupt (IPI) from the real time core to the suspendable core, wherein execution may be resumed when the real time core conducts a write to a memory location that is monitored by the suspendable core during suspension of execution.
US09286136B1	Hash-based region locking A region lock (RL) method and system for ensuring data integrity is disclosed. The method and system in accordance with the present disclosure works in conjunction with a balanced-tree based RL scheme. By eliminating steps and checks that in most cases are unnecessary, the relatively high overhead associated with the balanced-tree based RL scheme may be reduced. For instance, the solution in accordance with the present disclosure may utilize a hash table to determine whether RL overlap checks may be bypassed for certain I/O commands. Since the new solution requires very little processing, therefore by reducing unnecessary RL overlap checks, RL overhead may be dramatically reduced and may lead to significant increases in overall system performance.

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