最新美国发明专利第2016-02-16期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09264033B2	Feed-forward frequency control method for current mode hysteretic buck regulator A hysteresis generator provides a hysteresis parameter V_hyst to a hysteresis comparator of a voltage regulator. The hysteresis parameter V_hyst is a function of circuit components of the hysteresis generator, a voltage output Vout of the regulator, a voltage input Vin of the regulator, and a signal that drives one of a plurality of switches of the regulator. A switch driver drives the switches based on the hysteresis parameter. One or more of the circuit components of the hysteresis generator that provide the hysteresis parameter also define a hysteresis time period T_hyst. The hysteresis time period T_hyst defines in combination with a delay time period T_Td of the regulator, a switching time period T for the regulator that is substantially constant.
US09264032B2	Voltage protection scheme for semiconductor devices Various examples are provided for voltage protection of semiconductor devices. In one example, among others, a circuit includes a MOS device, a protective device connected between the MOS device and an output voltage connection, and gate protection circuitry configured to provide a bias voltage to a gate of the protective device. The bias voltage includes a DC bias component and an AC bias component that synchronously varies with a voltage of the output voltage connection. Another example includes a plurality of protective devices connected between the MOS device and the output voltage connection. The gate protection circuitry may be configured to provide a plurality of bias voltages to the plurality of protective devices. In another example, a method includes attenuating an output voltage, combining the attenuated output voltage with a constant offset voltage to generate a gate bias voltage, and providing the gate bias voltage to a protective device.
US09264026B2	Phase interpolation clock generator and phase interpolation clock generating method A phase interpolation clock generator includes: a phase detector configured to detect a phase difference between an input signal and a clock; a phase control signal generator configured to generate a phase control signal that is inverted for a certain phase difference and changes between a high level and a low level based on the phase difference; a controller configured to generate a combining control signal for combining a plurality of phase clocks and performing phase interpolation based on the phase control signal; an overshoot detector configured to detect overshoot in which the phase control signal rises above the high level; an overshoot canceller configured to lower the phase control signal which rises above the high level at an occurrence of the overshoot; and a phase interpolator configured to generate the clock by combining the plurality of phase clocks in accordance with the combining control signal.
US09264025B2	Glitch filter and filtering method A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. The high glitch filter circuit is configured for generating a pull-up control signal in accordance with the input signal. The low glitch filter circuit is configured for generating a pull-down control signal in accordance with the input signal. The control circuit is configured for determining the logic level of the output of the glitch filter in accordance with the pull-up control signal and the pull-down control signal. A filtering method for filtering glitches is disclosed herein as well.
US09264011B2	Impedance-matching switching circuit, antenna device, high-frequency power amplifying device, and communication terminal apparatus An antenna device includes an impedance-matching switching circuit connected to a feeding circuit, and a radiating element. The impedance-matching switching circuit matches the impedance of the radiating element as a second high frequency circuit element and the impedance of the feeding circuit as a first high frequency circuit element. The impedance-matching switching circuit includes a transformer matching circuit and a series active circuit. The transformer matching circuit matches the real parts of the impedance and matches the imaginary parts of the impedance in the series active circuit. Thus, impedance matching is performed over a wide frequency band at a point at which high frequency circuits or elements having different impedances are connected to each other.
US09264008B2	Filter apparatus, a method for filtering harmonics in an electrical power transmission or distribution system, and such a system A filter apparatus includes at least one filter, each filter being tunable and including at least one capacitor arrangement. The capacitor arrangement includes a plurality of first capacitors, a plurality of second capacitors, and a plurality of switches. Each switch is switchable between a non-conducting mode and a conducting mode. The plurality of second capacitors and the plurality of switches are arranged to connect or disconnect the second capacitors on different potentials in order to tune the filter by adjusting the capacitance of the filter. An electrical power transmission or distribution system includes such a filter apparatus. A method is provided for filtering harmonics in an electrical power transmission or distribution system by means of such a filter apparatus.
US09264006B2	Cable connector having high resolution adjustable capacitance and method for using the same A cable connector configured to receive a sound signal and alter the tonality of the sound by switching among a plurality of capacitors. The cable connector comprises a switch coupled to a binary coded plurality of capacitors. The cable connector receives an input signal corresponding to a sound through a conductor, which is also coupled to the switch. The switch may be used to select one of a plurality of capacitances, affecting the tonality of the sound. A cable implementing the cable connector and a method for using the cable connector are also disclosed.
US09264003B2	Apparatus and method for modifying an audio signal using envelope shaping An apparatus for modifying an audio signal has an envelope shape determiner, a filterbank processor, a signal processor, a combiner and an envelope shaper. The envelope shape determiner determines envelope shape coefficients based on the a frequency domain audio signal representing a time domain input audio signal and the filterbank processor generates a plurality of bandpass signals in a subband domain based on the frequency domain audio signal. Further the signal processor modifies a subband domain bandpass signal of the plurality of subband domain bandpass signals based on a predefined modification target. The combiner combines at least a subset of the plurality of subband domain bandpass signals containing the modified subband domain bandpass signal to obtain a time domain audio signal. Further, the envelope shaper is operative to obtain a shaped audio signal.
US09264002B2	Apparatus and methods for improving common mode rejection ratio In certain applications, differential amplifiers with infinite common mode rejection ratios are desirable. However, resistance mismatches due to imperfections in the manufacturing create finite common mode rejection ratio in differential amplifiers degrading their performance. Disclosed are apparatus and method for improving the common mode rejection ratio of practical differential amplifiers.
US09263997B2	Self setting power supply using negative output impedance A self-setting power supply monitors a supply current drawn by a power amplifier and sets a supply voltage based on the supply current to achieve efficient power operation. In order to maintain operation of the power amplifier above minimum operating conditions, the self-setting power supply sets the supply voltage to the minimum operating voltage when the supply current drops below a threshold bias current. When the supply current is above the threshold bias current, the self-setting power supply adjusts the supply voltage approximately proportionally to the supply current to maintain approximately constant gain of the power amplifier.
US09263994B2	Amplifying device, distortion compensating device, and amplifying method An amplifying device including: a first amplifier configured to generate a first output signal by amplifying an input signal, a second amplifier configured to generate a second output signal by amplifying the first output signal, and a processor configured to perform a first compensation by compensating a distortion for the second amplifier in accordance with the first output signal and the second output signal.
US09263993B2	Low pass filter with common-mode noise reduction A low pass filter includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential operational amplifier, wherein the first amplifier stage is arranged to process a differential input signal to generate a differential intermediate signal, the differential input signal having a first input signal and a second input signal, and the differential intermediate signal having a first intermediate signal and a second intermediate signal. The second amplifier stage has no common-mode feedback and is arranged to process the differential intermediate signal to generate a differential output signal, wherein the differential output signal has a first output signal corresponding to the first input signal and a second output signal corresponding to the second input signal. Since the noisy common-mode feedback is removed from the second amplifier stage, the overall common-mode noise of the low pass filter can be decreased.
US09263991B2	Power management/power amplifier operation under dynamic battery drops In one embodiment, a digital internal amplified voltage of power management circuitry is forced to an input threshold voltage upon a determination that a set of emergency conditions is satisfied, and is set to an input minimum battery voltage upon a determination that the set of emergency conditions is not satisfied. The emergency conditions may include determining that a battery voltage is less than a threshold voltage and determining that an input minimum battery voltage is less than an input threshold voltage.
US09263988B1	Crystal oscillation circuit A crystal oscillation circuit is provided with a crystal oscillator, an inverter unit coupled in parallel with the crystal oscillator and including a plurality of inverters, a current supply unit that supplies current to at least a first inverter of the plurality of inverters, a signal converter that supplies current to at least a last inverter of the plurality of inverters and outputs a voltage to an external circuit, and a current controller that makes the current supply unit provide current corresponding to a voltage level of the output voltage of the signal converter. The crystal oscillation circuit is capable of reducing power consumption.
US09263987B2	Oscillator circuit An oscillator circuit (100, 200, 300, 10, 11) comprising a resonator (105) connected serially with a series to series feedback amplifier (110, 92), in which the series to series amplifier comprises a feedback network (210, 91) which has an impedance value which is below a certain first predefined limit and a phase value which increases with the operational frequency of the oscillator circuit with a rate which is above a second predefined limit. In one embodiment, the impedance value of the feedback network (210, 91) also varies with the operational frequency of the oscillator circuit, but is always below said first predefined value within the operational frequency of the oscillator circuit.
US09263986B2	Solar hybrid photovoltaic-thermal collector assembly A solar collector assembly includes a photovoltaic panel having first and second sides, a frame, and a first gas-filled chamber on the first side of the photovoltaic panel. The first gas-filled chamber is at least partially defined by a portion of the frame and by a portion of the first side of the photovoltaic panel. A gas functions as a heat exchange fluid and collects heat from solar energy and/or heat generated by the photovoltaic panel. The photovoltaic panel accumulates and converts solar energy to electrical energy. The solar collector assembly may include a second gas-filled chamber provided on the second side of the photovoltaic panel. The second gas-filled chamber is at least partially defined by a portion of the frame and by a portion of the second side of the photovoltaic panel. Solar collector systems and methods of generating electrical energy and/or thermal energy are also described.
US09263984B2	Air-conditioning apparatus A high efficiency refrigerant compressor standby heating method reduces vibrations and noise in a bearing of the compressor. The compressor comprises a motor, an inverter, an inverter controller, and a bus voltage detector to detect a bus voltage of the inverter. The inverter controller includes a dormant refrigerant detector to detect a dormant state of refrigerant in the compressor, a high-frequency AC voltage generator to output a high-frequency AC voltage command, which is out of a range of an operating frequency when the compressor is running, to a coil of the motor on the basis of an output of the dormant refrigerant detector, an amplitude, and a phase. A pulse width modulation signal generator to cause the inverter to generate a high-frequency AC voltage by generating a signal on the basis of the output of the high-frequency AC voltage generator and the output of the bus voltage detector.
US09263973B2	MEMS electrostatic actuator A MEMS electrostatic actuator includes a bottom plate affixed to a substrate and a top plate suspended above the bottom plate. The top plate has a parallel plate center section and two rotating members electrically connected to the center section. Each rotating member is attached centrally of the rotating member for rotation about an axis of rotation to a set of anchor posts. The attachment includes at least one pair of torsional springs attached along each axis, each spring comprising a rectangular metal square that twists as the rotational members rotate. Electrostatic pull-down electrodes are underneath each rotational member.
US09263971B2	Distributed voltage source inverters Systems and methods are disclosed with multiple direct current (DC) voltage source inverters to supply power to an alternating current (AC) power system. The system includes a plurality of full bridge inverter stages, each having a primary node and a secondary node, each of said full bridge inverter stages having positive and negative node, each of said full bridge inverter stages having a voltage supporting device electrically connected in a parallel relationship between said positive node and said negative node and a direct current (DC) source connected between the positive and negative nodes; at least one stacked inverter phase, each stacked inverter phase having a plurality of said full bridge inverter stages, each of said full bridge inverter stages in each stacked inverter phase interconnected in a series relationship with said secondary node of one of said full bridge inverter stages connected to said primary node of another full bridge inverter, said series interconnection defining a first full bridge inverter stage and a last full bridge inverter stage, each phase having an input node at said primary node of said first full bridge inverter stage and an output node at said secondary node of said last full bridge inverter stage; a local controller coupled to each full bridge inverter stage providing the control signals to each full bridge inverter stage to output an approximate nearly sinusoidal voltage waveform; and a system controller which communicating with each local controller; the system controller generating system control signals for configuration, synchronization, activation, deactivation and operating mode selection of said local controller.
US09263970B2	AC battery employing Magistor technology A DC/AC converter incorporates at least one Magistor module having a first sp control switch, a second sz control switch and a third sm control switch. An AC source is connected to an input of the at least one Magistor module. A switch controller connected to the first sp control switch, second sz control switch and third sm control switch to and provides pulse width modulation (PWM) activation of the switches for controlled voltage at an output.
US09263969B2	Double module for a modular multi-stage converter A submodule for a high-voltage converter with reduced risk of cross-ignition includes first and second series-connected energy storage devices, first and second semiconductor series circuits connected in parallel with the energy storage devices, respectively, and having first and second, and respectively third and fourth, switched power semiconductor switching units. A first terminal connects to a first potential point between the first and second switching units, a second terminal connects to a second potential point between the third and fourth switching units. A connecting switching unit is connected between the first and second semiconductor series circuits. A first connecting branch with a first diode connects the first potential point and the potential point between the energy storage devices. A second connecting branch with a second diode connects the second potential point and the potential point between the energy storage devices. The connecting branch diodes are oriented in mutually opposite directions.
US09263968B2	Bidirectional inverter-charger A bidirectional inverter-charger includes a first stage receiving or delivering energy from a line or to a load. The first stage including at least one inductor coupled with a split phase bridge. A link storage is connected between rails of a first bus and between the first stage and a second stage. The second stage includes a DC-to-DC converter connectable to a battery. The DC-to-DC converter includes a transformer providing galvanic isolation between a second bridge, connected between the rails of the first bus, and a third bridge connected between the rails of a second bus. In operation, the first stage provides power factor correction and a voltage boost while charging the battery and inverting when providing power to the line or the load. The second stage provides a controllable charge current to the battery and a voltage boost of a voltage of the battery to the link storage.
US09263967B2	AC/DC power conversion methods and apparatus An AC/DC converter that converts an AC input voltage Vin to a DC output voltage comprises an inductor, a capacitor selectively coupled to the inductor, a plurality of switches, and a controller. The controller configures the plurality of switches, inductor, and capacitor to operate as a buck converter during times when Vin>Vout and to operate as an inverting buck converter during times when Vin<−Vout. The controller modulates the duty cycles of the plurality of switches to regulate the DC output voltage Vout to the desired, constant output level.
US09263965B1	Producing an odd number full wave voltage multiplier Full wave voltage multipliers mostly provide only even multiples (2×, 4×, 8× . . . ). This invention details a process to produce a full wave multiplier that will provide voltage with an odd numbered multiplicand (3×, 5×, 7×, etc.) from the next-higher-numbered, and thus even-numbered, full wave multiplier (so a 3× will be devised from the 4×, a 5× from the 6×, and for any odd (n)×, from the even (n+1)×). Each of a simplified, base 3× and 5× full wave voltage multiplier are also disclosed.
US09263964B1	Systems and methods for low-power lamp compatibility with an electronic transformer In accordance with systems and methods of the present disclosure, an apparatus for providing compatibility between a load having a reactive impedance and a secondary winding of an electronic transformer may include a power converter and a circuit. The power converter may be configured to transfer electrical energy from the secondary winding to the load. The circuit may be configured to charge an energy storage device coupled to the power converter following start-up of the electronic transformer in order to increase a voltage of the energy storage device to at least a voltage level sufficient for the electronic transformer to enter steady-state operation.
US09263959B2	Forward converter with self-driven BJT synchronous rectifier An AC-to-DC converter circuit includes DC-to-DC converter that in turn includes a secondary side circuit. The secondary side circuit includes a secondary winding, a pair of bipolar transistor-based self-driven synchronous rectifiers, a pair of current splitting inductors, and an output capacitor. Each of the synchronous rectifiers includes a bipolar transistor and a diode whose anode is coupled to the transistor collector and whose cathode is coupled to the transistor emitter. The current splitting inductors provide the necessary base current to the bipolar transistors at the appropriate times such that the bipolar transistors operate as synchronous rectifiers. As compared to using conventional self-driven synchronous rectifiers based on field effect transistors in the secondary side, using the novel bipolar-transistor based synchronous rectifiers in the secondary side of the forward converter circuit results in lower power consumption and allows the converter to operate from a wider range of VAC input voltages.
US09263956B2	Switch-mode power supply control apparatus and flyback switch-mode power supply including the control apparatus A switch-mode power supply control apparatus includes a PWM controller for outputting a driving signal and a short-circuit protection module coupled to a detection terminal. The detection terminal receives a zero-crossing detection voltage. If the time that the detection voltage input to the detection terminal is lower than a first reference voltage exceeds a predetermined time period, the short-circuit protection module determines that a short-circuit abnormal situation occurs, the short-circuit protection module outputs a short-circuit signal to the PWM controller, and the driving signal output by the PWM controller becomes a turn-off signal. If the short-circuit protection module does not detect the short-circuit abnormal situation, the PWM controller operates normally. A flyback switch-mode power supply includes the switch-mode power supply control apparatus. The flyback switch-mode power supply has a low power consumption when a short-circuit protection is taking place.
US09263951B2	LLC balancing A converter arrangement (C.5, C.7, C.8, C.9, C.11, C.12) with at least two single LLC converters (L), a pulse generator (2) per single LLC converter (L) wherein each pulse generator (2) is configured to supply switching pulses to one single LLC converter (L) and an output controller (11) configured to use switching frequency control and/or phase-shift control to control the pulse generators (2) comprises a load balancing control (7.5, 7.7, 7.8, 7.9, 7.11, 7.12) for overcoming unbalanced loading of the converter arrangement (C.5, C.7, C.8, C.9, C.11, C.12).
US09263948B1	Input output balanced bidirectional buck-boost converters and associated systems and methods Various embodiments of the present invention relate to an input output balanced bidirectional buck-boost converter and associated system and method. In one example, a DC/DC bidirectional buck-boost power converter has both input and output voltages centered around chassis. This converter allows for overlapping input and output voltages, and allows for use of offset based leakage fault detection.
US09263939B2	Capacitor discharging circuit and converter A capacitor discharging circuit and a converter are disclosed. The converter comprises: a capacitor connected between the live line and null line of an AC power input terminals, a conversion module coupled to the capacitor and comprising an energy storage component at least, an energy transfer unit coupled with the energy storage component and the capacitor, an AC power-off detecting unit and a control unit; wherein the energy transfer unit comprises a switch device; when AC power is disconnected, the AC power-off signal triggers the control unit to output a switch driving signal, controlling the operation of the energy transfer unit to transfer the energy stored in the capacitor to the energy storage component to discharge the capacitor.
US09263936B2	Systems and methods for increasing output current quality, output power, and reliability of grid-interactive inverters Various enhancements to grid-interactive inverters in accordance with embodiments of the invention are disclosed. One embodiment includes input terminals configured to receive a direct current, output terminals configured to provide an alternating output current to the utility grid, a controller, an output current sensor, and a DC-AC inverter stage comprising a plurality of switches controlled by control signals generated by the controller. In addition, the controller is configured to: generate control signals that cause the switches in the DC-AC inverter stage to switch a direct current in a bidirectional manner; measure the alternating output current; perform frequency decomposition of the output current; and generate control signals that cause the switches in the DC-AC inverter stage to switch current in a way that the magnitude of a plurality of unwanted current components is subtracted from the resulting output current.
US09263935B2	Charge and discharge signal circuit and DC-DC converter A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a level shifter; a capacitor switch string connected in series, being connected in parallel with the transistor; and a drive part, to which an output of the level shifter is supplied, at least one pair of neighboring ones of the level shifters are commonly formed, and two neighboring ones of the drive parts receive a same output from the common shifters.
US09263934B2	Method and apparatus for determining zero-crossing of an ac input voltage to a power supply An example controller for a power supply includes a first circuit and a drive signal generator. The first circuit receives a first signal representative of a switch current flowing through a switch of the power supply and then generates a second signal in response the switch current not reaching a current threshold within an amount of time. The second signal indicates when a dimming circuit at an input of the power supply is utilized. The drive signal generator generates a drive signal to control switching of the switch in response to the second signal, where energy is transferred across an energy transfer element of the power supply in response to the switching of the switch.
US09263930B2	Electric machine having magnetic poles including a primary magnet and auxiliary magnets An electric machine has a stator and a rotor. The stator has a housing and at least one pair of magnetic poles. Each magnetic pole has a primary magnet and two auxiliary magnets disposed on respective sides of the primary magnet. All of the magnets are disposed on an inner surface of the housing. All the magnets of a magnetic pole have the same polarity.
US09263927B2	Stator of an electrical machine A stator of an electrical machine provides a sensor carrier having a spring element that presses the sensor element against one of the coils.
US09263926B2	Permanent magnet electric machine having magnets provided with a thermal enhancement bonding coating A rotor assembly for a permanent magnet electric machine includes a plurality of rotor laminations joined to form a rotor body. Each of the plurality of rotor laminations includes a plurality of slots. One or more permanent magnets are mounted within respective ones of the plurality of slots. Each of the one or more permanent magnets includes a thermal enhancement bonding coating. A method of forming a rotor assembly is also disclosed.
US09263925B2	Blower The blower comprises: a blower case; a motor case; and a shaft pierced through the both cases. A first communication hole, which is formed in one of axial end faces of the motor case, introduces a part of compressed air into the motor case. A second communication hole, which is formed in the other axial end face of the motor case, discharges the compressed air to outside of the motor case. An external guidance path introduces the discharged air toward an outside face of the motor case. By actuating a motor, the compressed air, which has been introduced from the blower case into the motor case via the first communication hole, is discharged from the second communication hole, and the discharged air is introduced by the external guidance path and blown out toward the outside face of the motor case.
US09263922B2	Stepping motor having a band holding two stator end plates A stepping motor comprises: a first plate having plural band connection portions; a second plate mounting a band; a stator; and a structure that the stator is held by the first plate and the second plate from a front side and a back side of axial direction, wherein the plural band connection portions are positioned at a side surface of the stator and extend toward the second plate, and each of the plural band connection portions has an engagement portion at an outside thereof, the band has plural arms extending toward the first plate and engaging with the engagement portion of each of the plural band connection portions, and the band is connected to the first plate by engaging the arm portions with the engagement portions in a condition that the band holds the second plate and the stator.
US09263921B2	Stator core compression Embodiments of the invention relate generally to electromagnetic devices and, more particularly, to the compression of stator core laminations using wire rope members and to stator cores and electromagnetic devices employing such wire rope members. In one embodiment, the invention includes: affixing a first end of a wire rope member to a first flange plate disposed adjacent a first end of a plurality of stator laminations; affixing a second end of the wire rope member to a second flange plate disposed adjacent a second end of the plurality of stator laminations; tensioning at least one of the first end or the second end of the wire rope member against at least one of the first flange plate and the second flange plate to exert a compressive force against the first flange plate, the second flange plate, and the plurality of stator laminations.
US09263908B2	Battery pack having linear voltage profile, and SOC algorithm applying to the battery pack A battery pack includes a rechargeable battery module and a battery management system for controlling charging and/or discharging of the battery module. The battery module may include a substantially linear charging and discharging voltage-time profile within at least part of the charging and discharging cycle of the battery module, and the battery management system may be configured to calculate a state of charge of the battery module by using linear charging and/or discharging characteristics of the battery module.
US09263904B2	Frequency based rechargeable power source charging A charging method and system. The method includes detecting and monitoring by a computer processor, a frequency signal associated with an input voltage signal used for powering power consumption devices at a first specified location. The computer processor generates frequency level data associated with the monitoring. The computer processor receives a request to enable a charging process for charging a rechargeable power source and power source data associated with the rechargeable power source and a user. In response to the request, the computer processor enables a customized charging process associated with charging the rechargeable power source based on the frequency level data and/or the power source data.
US09263897B2	Power supply control system A power supply control system includes power supply switch devices each including main relays, sub relays, and control units and a control line connected to sub control lines for controlling the sub relays. The control units control the sub relays of other power supply switch devices via the control line.
US09263893B2	Electricity storage device, electricity storage control method, management device, management method, and electricity storage system An electricity storage control device that transmits a charging rate of at least one of electricity storage devices to a management device that manages electric power interchange between the electricity storage devices, the electricity storage control device including: a charge information acquisition unit that acquires the charging rate of the at least one electricity storage device as a first charging rate; a communication unit that transmits the first charging rate to the management device; and a control unit that causes the communication unit to transmit, instead of the first charging rate, a second charging rate that charge and discharge determining information defines as the charging rate at which the charge and discharge are prohibited, when the charge and discharge determining information defines the first charging rate as the charging rate at which the charge and discharge are permitted.
US09263886B2	Information processing apparatus and method for supplying electrical power An information processing apparatus includes: a plurality of electric power generating elements; detection means for determining whether each of the plurality of electric power generating elements has an electromotive force equal to or higher than a predetermined value; determination means determining an input operation performed by a user by identifying an electric power generating element having an electromotive force below the predetermined value when at least one of the plurality of electric power generating elements is determined as having an electromotive force below the predetermined value according to the detection means; processing means carrying out a process associate with the input operation determined by the determination means; and bypass means which is provided in parallel with the electric power generating elements and through which a current flows when the electric power generating elements have an electromotive force below the predetermined value.
US09263878B2	Circuit protector A circuit protector includes a plurality of detection lines that connect between a battery pack and a monitoring circuit, an overvoltage protection element connected between the detection lines that keeps the voltage applied to the monitoring circuit at a fixed voltage, and a circuit protection element disposed in each detection line that disconnects an electrical link between the monitoring circuit and the battery pack when a current beyond a predetermined current value flows into the detection line. When the excess voltage occurs in the battery pack, the overvoltage protection element maintains between each detection line in a short circuit state, and the circuit protection element disconnects the electrical link between the battery pack and the monitoring circuit by a short-circuit current that flows between the detection lines via the overvoltage protection element.
US09263870B2	System and method for applying an adhesive coated cable to a surface A system and method for installing a fiber or cable on a wall or ceiling of a structure includes providing a fiber, wire or cable pre-coated with a hot melt adhesive that simply needs to be activated by the application of sufficient heat for a sufficient amount of time immediately before installation. Rolls or cartridges of wire or cable pre-coated with the hot melt adhesive are provided. The hot melt adhesive coated wire or cable is fed through a heated chamber, preferably a tip on a portable heating device such as a battery operated soldering iron, which activates the pre-coated hot melt adhesive prior to utilizing the heating tip to apply pressure to the adhesive wire directly to a wall or ceiling thereby adhering the fiber, wire or cable to the desired surface.
US09263869B2	Cart with cable management system A cart with one or more of a power supply system that includes an outlet box and a plurality of flexible receptacles, a bi-layer shelf, a positionable cable routing tray, and a removable cable management module.
US09263866B2	Corrugated tube and wire harness with corrugated tube A corrugated tube includes a corrugated tube main body, a plurality of first extended tabs, and a plurality of second extended tabs. The corrugated tube main body is formed in a tubular shape, has annular projections and annular depressions alternatingly formed along a length direction, and has a slit formed along the length direction. The plurality of first extended tabs is provided at intervals on the corrugated tube main body on one of two lateral edges having the slit therebetween. A first engagement notch is formed on two lateral portions of each of the first extended tabs. The plurality of second extended tabs is provided at intervals on the corrugated tube main body on the other of the two lateral edges having the slit therebetween. A second engagement notch is formed on two lateral portions of each of the second extended tabs and engages with the first engagement notch.
US09263863B2	Method and apparatus for positioning in-wall power The present invention discloses a method and apparatus for locating a pre-wired electrically isolated power source. The invention includes a plurality of embodiments of encased receptacles combined with recessed electrical enclosures for mounting the receptacles. The recessed electrical enclosures allow for the input and output receptacles to be mounted externally to the enclosure, to create space internal to the enclosure, and for visual isolation of receptacle outlets and associated plugs/connectors that may also be present in the enclosure.
US09263861B2	Mounting rail and module latching system A module latching arrangement for mounting and dismounting on a generally U-shaped support rail at least two module base bodies arranged orthogonally above and extending transversely across the support rail, each of the base bodies having a pair of bottom corner portions arranged on opposite sides of the support rail. At least one foot member is connected for horizontal longitudinal sliding movement relative to one of the base body corner portions relative to the adjacent support rail horizontal flange portion. A lateral displacement arrangement on the foot member is operable, when the foot member is displaced from a locked position toward an unlocked position relative to the support rail, to displace the first base body laterally away from an adjacent second base body mounted on the support rail. The foot member is latched in either a locked or an unlocked position relative to the base member.
US09263858B2	Ionizer An efficient and safe ionizer is disclosed. The ionizer includes a circuit to generate high voltage, a circuit case to surround the circuit, an electrode disposed outside of the circuit case and caused to discharge electricity by the high voltage generated by the circuit to ionize molecules in air, and an electrode cover disposed at a portion around the electrode.
US09263857B2	Ignition system A superior ignitability is realized assuredly by specifying at least either of a relation in magnitude between absolute values of a plus-side voltage and a minus-side voltage and a relation in magnitude between absolute values of a plus-side current and a minus-side current when alternating current power is introduced. An ignition system includes a spark plug, a discharging power supply which applies a voltage to a spark gap of the spark plug to thereby generate an electric spark discharge and an alternating current power supply which introduces alternating current power to an electric spark generated by the electric spark discharge to generate an alternating current plasma.
US09263856B2	Electrode for a spark plug and method for its production An electrode for a spark plug includes an electrode base material and a noble metal element, the noble metal element being fastened to the electrode base material using a welding connection. The welding connection has a maximum extension perpendicular to an area of the electrode at which the noble metal element is fastened, and the welding connection has a maximum width at the area. A ratio of the maximum extension to the maximum width is greater than, or equal to 3.
US09263852B2	Semiconductor laser and optical semiconductor device In the semiconductor laser including a diffraction grating in which a first diffraction grating region with a first pitch, a second diffraction grating region with a second pitch and a third diffraction grating region with the first pitch, an anti-reflection film coated on an end facet to the light-emitting side, and a reflection film coated on an opposite end facet, the first diffraction grating region is greater than the third diffraction grating region, and the second diffraction grating region is formed, in such a manner that phases of the first and third diffraction grating regions are shifted in a range of equal to or more than 0.6 π to equal to or less than 0.9 π, phases are successive on a boundary between the first and second diffraction grating regions and the phases are successive on a boundary between the second and third diffraction grating regions.
US09263851B2	Cooling system, reservoir unit and cartridge, as well as solid-state laser oscillator system provided with the same A reservoir unit which is included as an element along a circulation path of a cooling system includes a cartridge and a cartridge loading unit which are configured to be removable from each other. The cartridge includes a reservoir chamber that stores a circulating liquid, and a connection portion in fluid communication with the reservoir chamber. The cartridge loading unit includes a connection receiving portion, to which the connection portion is connected, and a connection port. When the cartridge and the cartridge loading unit are attached to each other, the connection portion, the connection receiving portion and the connection port form a feed path that allows feeding the circulating liquid to the circulation path outside, and a collection path that allows collecting the circulating liquid into the reservoir chamber.
US09263846B2	Systems and methods for amplifying space-multiplexed optical signals In one embodiment, an optical system for amplifying space-multiplexed optical signals includes an input fiber that propagates multiple spatially-separated optical signals and a bulk amplifier formed of a doped material that receives the multiple spatially-separated optical signals and simultaneously amplifies those signals to generate multiple amplified signals.
US09263845B2	Air-cooled gas lasers with heat transfer resonator optics and associated systems and methods Embodiments of an air-cooled gas laser with heat transfer resonator optics are disclosed herein. A laser configured in accordance with one embodiment includes resonator optics having an optical element, a first heat sink element in surface-to-surface contact with a first side surface of the optical element, a second heat sink element in surface-to-surface contact with a second side surface of the optical element, and a carrier member carrying the optical element and the first heat sink element, and including a forward facing surface in surface-to-surface contact with the backside surface of the optical element. The resonator optics further include first and second biasing elements biasedly coupled to the carrier member and configured to bias the first and second heat sink elements against the first side and second side surfaces, respectively, of the optical element.
US09263844B2	Air-cooled gas lasers and associated systems and methods Embodiments of an air-cooled gas laser are disclosed herein. A laser configured in accordance with one embodiment includes a laser superstructure, an optical assembly, and an elongated thermal decoupler member having a first end portion fixedly coupled to the optical assembly and a second end portion fixedly coupled to the laser superstructure. The laser further includes an optical assembly that includes a first holder member fixedly coupled to the first end portion of the thermal decoupler, a second holder member pivotally coupled to the first holder member and fixedly coupled to the laser superstructure, and a flexible seal having a portion coupled to the laser structure and disposed at least between the first holder member and the second holder member.
US09263837B2	Electrical connector with improved contact arrangement An electrical connector includes an insulative housing defining a receiving space (110), a number of contacts retained in the insulative housing, a cable (6) electrically connected with the contacts, and a shielding member (5) enclosing on the insulative housing to form a cavity (120). The contacts comprise a set of first contacts (2) and a set of second contacts (3), each of the first and second contacts having a contacting portion and a tail portion. The cavity has a smaller length than the receiving space along a transverse direction, the cavity is stacked on one side of the receiving space along an up-to-down direction, the cavity has a lateral boundary coplanar with the receiving space, the second contacts are received in the receiving space, and the first contacts are retained in the cavity for transmitting high speed signal.
US09263835B2	Electrical connector having better anti-EMI performance An electrical connector includes an insulative housing defining a rear wall and a mating cavity running through a front end of the insulative housing from the rear wall, the rear wall defines an inner surface facing the mating cavity. A plurality of conductive terminals are fixed in the insulative housing and include a plurality of grounding terminals, each conductive terminal defines a body portion and a first contacting arm extending into the mating cavity. And a grounding plate is disposed in the rear wall and defines a plurality of contacting portions running through the inner surface and extending into the mating cavity and a plurality of connecting portions connecting to the respective body portions of the grounding terminals.
US09263834B2	Electrical connector having a flange An electrical connector includes an insulative housing, a shell covering the insulative housing, and a flange mounted to the shell. The insulative housing has a front face, a number of outer faces, and a receiving cavity extending through the front face for receiving a mating connector. The shell has a front wall and a number of outer walls covering the housing front and outer faces, respectively. The flange has a mating sleeve mounted to the shell and a mating flange portion for engaging a panel along a front-to-back direction. The mating sleeve is bent from a material band, and the mating flange portion is bent from the mating sleeve. The mating flange portion is substantially perpendicular to and resiliently flexible relative to the mating sleeve.
US09263830B2	Charging connector A charging connector includes a connector housing to be fitted to a power receiving connector, a connector case housing the connector housing, a lock arm arranged to be swingable about a swing fulcrum between a lock position and a release position, and a coil spring located toward a power receiving connector away from the swing fulcrum to bias the lock arm toward the lock position. The lock arm is provided with a spring compartment housing the coil spring in a manner such that the periphery of the coil spring is enclosed. The spring compartment is provided, on a bottom portion thereof, with a penetration hole extending in the lock arm.
US09263829B2	Durable plug connector assembly and method of assembling the same A plug connector assembly for mating with a complementary connector includes a printed circuit board (PCB) defining a plurality of conductive pads, a pair of metal members mounted on two sides of the PCB and soldered with the PCB for electrically connecting with the complementary connector, an inserting member electrically connected on a front end of the PCB to connect to the complementary connector, and a housing enclosing the PCB. The PCB includes a front portion, an opposite rear portion, and a middle portion connecting the front portion and the rear portion. The conductive pads include a plurality of first pads disposed on the front portion. The inserting member includes an insulative member and a plurality of terminals held on the insulative member. The terminals are soldered with corresponding first pads.
US09263825B2	Electric wire terminal connection structure and intermediary cap used for the same An electric wire terminal connection structure includes an electric wire including a core made of a metallic material and an insulation layer covering the core, a terminal fitting attached to a terminal of the electric wire and made of a metallic material other than the metallic material of the core, and an intermediary cap to be crimped to the core by the terminal fitting and to cover an exposed portion of the core exposed by removing the insulation layer at the terminal of the electric wire. The intermediary cap has conductivity and is made of a metallic material having a value of a standard electrode potential between that of the core and that of the terminal fitting.
US09263823B2	Lever connector A lever connector includes a first connector housing, a second connector housing that includes a distal fitting portion intended for a distal end of the first connector housing to be fittedly connected thereto, and is adapted to be attached to a connector attaching plate in a state of inserting the second connector housing through a connector attaching hole of the connector attaching plate, a lever adapted to fit the first connector housing into the second connector housing by a pivoting operation, and a grommet for ensuring a waterproofing property of an inside of the first connector housing. The lever includes a lever body, a pivoting connection portion, and a lever locking piece. The grommet is fitted and mounted on the lever and includes a lever covering portion, and a tubular.
US09263820B2	Electrical press-fit pin for a semiconductor module An electrical module includes a housing, at least one electrical component mounted within the housing and an electrical press-fit contact. The electrical press-fit contact is located in part within the housing and has a press fit portion and a stop portion at its distal end and a mounting portion at its proximal end. The mounting portion is electrically coupled to the electrical component. The press-fit portion is located exterior of the housing such that the stop portion is able to block movement of the press-fit section into the housing when a press-in force is introduced onto the press-in contact to press the press-fit contact into the housing.
US09263814B2	Metal material for electrical electronic component A metallic material for an electrical electronic includes a CU—Sun alloy layer (2) provided on a conductive base (1). A Cu concentration of the Cu—Sn alloy layer gradually decreases from the base side to the surface (3) side.
US09263811B2	Connector having a step-like support portion for providing a wicking space The present invention is to provide a connector having support portions like steps for improving yield rate of soldering, which includes an isolation base provided therein with signal terminals each having two ends respectively exposed out of front and back side surfaces of the isolation base. Support portions each is formed by a protruded part and a recessed part like steps on the back side surface. An end of a positioning terminal can be inserted into a positioning groove on the recessed part and then be exposed out of the back side surface with a length larger than the length of the protruded part that is approximately equal to the length of the signal terminal extended out the back side surface, whereby the end of the positioning terminal can be inserted into a positioning hole on a circuit board when the back side surface is positioned on the circuit board.
US09263810B2	Clamp for connecting battery terminals A clamp for freely connecting sheet metal terminals made of a battery in a lateral or vertical direction suitable for working environment is provided. A bolt and a nut connecting both walls are parallel to each other at an open end. Wedge-shaped recesses, into which chamfers of the terminal units are inserted, are formed on inner sides of the walls facing each other. The clamp tightens the terminal units using the wedge-shaped recesses and enables a vertical connection and a lateral connection.
US09263808B2	Connection structural body, connector and method of manufacturing connection structural body There is provided a pressure-bonding connection structural body and a female connector which can surely prevent the intrusion of moisture from an insulating cover side, and a method of manufacturing the connection structural body. In the connection structural body which is configured by connecting a crimp terminal and an insulated wire to each other, the crimp terminal having a barrel portion which is an integral body formed of; a cover pressure-bonding section which pressure-bonds by caulking the insulating cover; and a core wire pressure-bonding section which pressure-bonds an aluminum core wire by caulking, a water blocking projecting portion which prevents the intrusion of moisture in a longitudinal direction in a pressure-bonding state is formed, at the time of pressure-bonding the barrel portion, on an inner surface of the cover pressure-bonding section of the barrel portion where a cross-sectional shape in a width direction is formed into a closed cross-sectional shape.
US09263807B2	Waveguide or slot radiator for wide E-plane radiation pattern beamwidth with additional structures for dual polarized operation and beamwidth control An apparatus and method are provided for producing a wide E-plane half power beamwidth. The apparatus can include a dipole antenna and a complimentary slot antenna in an infinite ground plane. The apparatus can also include a waveguide with surrounding structure that can be adjusted to produce the desired half power beamwidth.
US09263804B2	Composites for antennas and other applications Composite material, devices incorporating the composite material and methods of forming the composite material are provided. The composite material includes interstitial material that has at least one of a select relative permittivity property value and a select relative permeability property value. The composite material further includes inclusion material within the interstitial material. The inclusion material has at least one of a select relative permeability property value and a select relative permittivity property value. The select relative permeability and permittivity property values of the interstitial and the inclusion materials are selected so that the effective intrinsic impedance of the interstitial material and the inclusion material match the intrinsic impedance of air. Devices made from the composite include metamaterial and/or metamaterial-inspired (e.g., near-field LC-type parasitic) substrates and/or lenses, front-end protection, stealth absorbers, filters and mixers. Beyond the intrinsic, applications include miniature antennas and antenna arrays, directed energy weapons, EMI filters, RF and optical circuit components, among others.
US09263802B2	Electromagnetic wave absorber An electromagnetic wave absorber includes a rectangular plate-shaped part having a surface including a flat space at a center of the plate-shaped part and a plurality of oblong rectangular spaces, surrounding the flat space, on each of which at least one pyramidal or wedge-shaped part having an oblong rectangular bottom face is provided, and the plurality of oblong rectangular spaces of the surface of the plate-shaped part are arranged along inside a perimeter of the plate-shaped part so that a longer side of any one of the plurality of oblong rectangular spaces is adjoining with a shorter side of another of the plurality of oblong rectangular spaces adjacent thereto while leaving the flat space at the center of the plate-shaped part.
US09263801B2	Directional mobile antenna with polarization switching by displacement of radiating panels An antenna with polarization switching comprises a support comprising at least two faces each supporting a plurality of waveguides fed with radiofrequency signals and pierced with apertures disposed so as to illuminate radiating elements placed some distance from the said apertures. For at least one given antenna pointing, the said support is able to toggle between at least two different configurations, the said support being configured so as to place, in the second configuration, the second face in a position identical to that taken by the first face in the first configuration, several radiating elements of the first face being, in the said position, oriented differently from radiating elements of the second face. It applies notably to the switching of antennas embedded onboard moving objects on the ground having to operate high-speed communications with a satellite, in particular a geostationary satellite.
US09263800B2	Artificial skin for radar mannequins An artificial skin for use on a radar mannequin exposed to electromagnetic radiation having a predetermined frequency and a radar mannequin having the artificial skin are provided. The artificial skin and the radar mannequin with the artificial skin are configured to produce a radar cross section that closely approximates the radar cross section of a human. The artificial skin includes a conductive layer of material and a shielding layer of material. The conductive layer and the shielding layer are configured to reflect electromagnetic radiation at a level of an electromagnetic response of human skin exposed to the electromagnetic radiation. The shielding layer also electromagnetically shields an inside surface of the artificial skin from electromagnetic radiation.
US09263798B1	Reconfigurable antenna apparatus An antenna apparatus may include a reflective layer connected to a ground, one or more first antennas disposed on the reflective layer, wherein each first antenna includes a first active element and one or more first parasitic elements; one or more first switching devices, each associated with corresponding one of the one or more first parasitic elements in at least one of one or more first antennas, one or more second antennas disposed on the reflective layer, wherein each second antenna includes a second active element and one or more second parasitic elements, and one or more second switching devices, each associated with corresponding one of the one or more second parasitic elements in at least one of one or more second antennas. The first antennas operate at a first frequency. The second antennas operate at a second frequency different from the first frequency.
US09263796B1	Shielding cell phone radiation Devices and methods to reduce or attenuate electromagnetic radiation emitted by an electronic device such that the electromagnetic radiation does not impinge on a user of the electronic device include one or more layers of material. The one or more layers of material have properties including one or both of absorption and/or reflection of electromagnetic radiation in frequency ranges used for wireless telephonic communication. The one or more layers of material are arranged to be disposed near the back side of the electronic device. Use of the one or more layers of material attenuates the electromagnetic radiation as measured at or near the front of the electronic device during use by about 75%.
US09263795B2	Mobile wireless communications device having dual antenna system for cellular and WiFi A mobile wireless communications device includes a housing and circuit board carried by the housing. Radio Frequency (RF) circuitry is mounted on the circuit board. A first antenna is supported by the circuit board within the housing and operatively connected to the RF circuitry and configured for cellular phone communications. A second antenna is supported by the circuit board within the housing and operatively connected to the RF circuitry and configured for WiFi communications. The second antenna comprises an inverted-F or monopole antenna having an opening gap that is pointed away from the first antenna.
US09263794B2	Node in a wireless communication network with at least two antenna columns A node in a wireless communication network, the node comprising at least two antenna columns which are physically separated from each other, each antenna column comprising at least one dual polarized antenna element. Each antenna element has a first polarization and a second polarization. The node further comprises at least two four-port power dividers/combiners, each power divider/combiner having a first port pair and a second port pair, where, for each power divider/combiner, power input into any port in a port pair is isolated from the other port in said port pair, but divided between the ports in the other port pair. Antenna ports of antenna columns that are pair-wise physically separated, from those pairs of antenna columns that are most physically separated to those that are least physically separated, are cross-wise connected to the first port pair in corresponding power dividers/combiners.
US09263791B2	Scanned antenna having small volume and high gain A scanned radio frequency (RF) antenna having a small volume is described.
US09263788B2	Mobile device having reconfigurable antenna and associated methods A mobile wireless communications device includes a wireless transceiver, and a reconfigurable antenna coupled to the wireless transceiver. The reconfigurable antenna has a dielectric substrate, with a plurality of electrical conductors on the dielectric substrate laterally adjacent the ground plane and arranged in a series of spaced apart antenna loops with each successive outer antenna loop surrounding an adjacent inner loop, each antenna loop having a pair of endpoints. A plurality of switches are associated with respective endpoints of the antenna loops. A processor is adapted to reconfigure the reconfigurable antenna and couple the wireless transceiver thereto via the plurality of switches.
US09263787B2	Power combiner and fixed/adjustable CPL antennas An N-way radio frequency (RF) divider/combiner is formed as a combination including an input port electrically coupled to a first 2-way divider/combiner and a second 2-way divider/combiner. An antenna may be coupled to at least one port of the N-way divider. The antenna may be formed as a compound printed loop (CPL) antenna. The N-way RF divider/combiner may be configured to provide N inputs and M output ports, wherein N and M are integers and any of the M output ports and N input ports can be connected to any combinations of devices. Such devices may include, e.g., an antenna including but not limited to a CPL antenna, RF receive port, transmit port, amplifier, RF switch, low noise amplifier (LNA), oscillator, tuning circuit, matching circuit, lumped element circuit, active circuit, diode, adjustable inductive circuit, and adjustable capacitive circuit.
US09263785B2	Electrically tunable waveguide filter and waveguide tuning device The present invention relates to a waveguide tuning device (1) arranged for mounting in a waveguide structure (2) which has a longitudinal extension (L) and comprises a first inner wall (3), a second inner wall (4), a third inner wall (5) and a fourth inner wall. The inner walls are arranged such that a rectangular cross-section is obtained for the waveguide structure. The first inner wall (3) and the second inner wall (4) have a first length (b) and are facing each other. The third inner wall (5) and the fourth inner wall (6) have a second length (a) and are facing each other. The electrical field (E) is parallel to the main surfaces of the first inner wall (3) and the second inner wall (4). The tuning device (1) is electrically controllable and arranged for mounting at the first inner wall (3) and/or the second inner wall (4). The present invention also relates to a tunable waveguide structure.
US09263782B2	Notch filter structure with open stubs in semiconductor substrate and design structure On-chip millimeter wave (mmW) notch filters with via stubs, methods of manufacture and design structures are disclosed. The notch filter includes a signal line comprising a metal trace line connected to a metal via stub partially extending into a semiconductor substrate. The notch filter further includes a defected ground plane connected to at least one or more additional metal via stubs partially extending into the semiconductor substrate.
US09263781B2	Waveguide polarizers A method and apparatus for a polarizer. The apparatus comprises a dielectric rod, a first array of slots, and a second array of slots. The first array of slots and the second array of slots are formed in sidewalls of the dielectric rod. The first array of slots is substantially opposite to the second array of slots. The first array of slots and the second array of slots are configured to shift a first component orthogonal to a second component in a signal traveling through the dielectric rod by around 90 degrees with respect to each other. The dielectric rod may be a solid material or comprised of layers of dielectric substrates with metal tabs.
US09263769B2	Process for the production of low flammability electrolyte solvents The invention provides a method for producing electrolyte solvent, the method comprising reacting a glycol with a disilazane in the presence of a catalyst for a time and at a temperature to silylate the glycol, separating the catalyst from the silylated glycol, removing unreacted silazane; and purifying the silylated glycol.
US09263766B2	Additive for electrolyte of lithium battery, organic electrolyte solution comprising the same, and lithium battery using the organic electrolyte solution An additive for an electrolyte of a lithium battery including a disultone-based compound represented by Formula 1 below, an organic electrolyte solution including the additive, and a lithium battery including the organic electrolyte solution are provided: wherein, in Formula 1, A1, A2, A3, and A4 are each independently a substituted or unsubstituted C1-C5 alkylene group; a carbonyl group; or a sulfinyl group.
US09263761B2	Electrode assembly and rechargeable battery having the same An electrode assembly includes a positive electrode including a positive active material layer on each of first and second surfaces of a positive electrode current collector, a negative electrode including a negative active material layer on each of first and second surfaces of a negative electrode current collector, and an inner separator between the positive electrode and the negative electrode, wherein each of the positive electrode and the negative electrode includes a side end uncoated region at respective side ends of the positive electrode and the negative electrode, the side end uncoated regions of each of the positive and negative electrodes including no active material layers on respective electrode current collectors, and wherein at least one of the positive electrode and the negative electrode has an inner uncoated region positioned at a center of the electrode assembly, the inner uncoated region including no active material layer thereon.
US09263760B2	Stepped electrode assembly having predetermined a reversible capacitance ratio in the interface between electrode units, battery cell and device comprising the same There are provided an electrode assembly, and a battery cell, a battery pack, and a device. The electrode assembly includes a combination of two or more types of electrode units having different areas, wherein the electrode units are stacked such that steps are formed, and electrode units are formed such that a positive electrode and a negative electrode face one another at an interface between the electrode units.
US09263759B2	End plate for fuel cell including anti-bending plate Disclosed is an end plate for a fuel cell including an anti-bending plate, in which an anti-bending plate is assembled with an insert having a sandwich structure and the insert is injection molded, thereby easily preventing the insert from being bent due to an injection molding pressure. In the disclosed end plate, a sandwich insert including two or more stacked plates each having a specific shape is manufactured, and an anti-bending plate is coupled to the sandwich insert and then is injection molded, thereby easily preventing the sandwich insert from being bent due to a resin pressure in the injection molding process, contrary to a conventional integral metal insert.
US09263758B2	Reversible solid oxide fuel cell stack and method for preparing same A reversible SOFC monolithic stack is provided which comprises: 1) a first component which comprises at least one porous metal containing layer (1) with a combined electrolyte and sealing layer on the porous metal containing layer (1); wherein the at least one porous metal containing layer (1) hosts an electrode; 2) a second component comprising at least one porous metal containing layer (1) with a combined interconnect and sealing layer on the porous metal containing layer; wherein the at least one porous metal containing layers hosts an electrode. Further provided is a method for preparing a reversible solid oxide fuel cell stack. The obtained solid oxide fuel cell stack has improved mechanical stability and high electrical performance, while the process for obtaining same is cost effective.
US09263753B2	Flowing electrolyte battery with electric potential neutralization Flowing electrolyte batteries capable of being selectively neutralized chemically; processes of selectively neutralizing flowing electrolyte batteries chemically; and processes of selectively restoring the electrical potential of flowing electrolyte batteries are disclosed herein.
US09263752B2	Magnetic fluid coupling assemblies and methods Fluid coupling assemblies and methods are discussed. The fluid coupling assemblies include a first coupling member, a second coupling member magnetically engageable with the first coupling member, and a seal member disposed between a portion of the first coupling member and a portion of the second coupling member. A magnetic engagement of the first coupling member and the second coupling member unseals a fluid flow path therebetween. In certain examples, the first coupling member is sealed by a valve member and the second coupling member includes an activation member. When engaged, the valve member is moved from a closed position to an open position by the activation member, thereby unsealing the fluid flow path. A magnetic force between the first coupling member and the second coupling member can be chosen such that the members disengage when a predetermined fluid flow path pressure is reached.
US09263748B2	Reversal tolerant membrane electrode assembly for a fuel cell A membrane electrode assembly (MEA) for a fuel cell which exhibits enhanced reversal tolerance. In particular, a layer of iridium or an iridium compound, preferably metallic iridium or iridium oxide supported on TiO2, is provided on the anode to electrolyze available water and pass the majority of the current during a reversal of the fuel cell, thereby preventing damage to the MEA. The iridium or iridium compound is applied to an anode structure according to a predetermined pattern, with only part of the anode active area containing Ir. The parts of the MEA that do not contain Ir are not expected to suffer degradation from Ir cross-over, so that overall degradation of the cell will be diminished. Having less precious metals will also translate into less cost.
US09263746B2	Binder for electrode of lithium rechargeable battery and electrode for rechargeable battery comprising the same In one aspect, a binder for an electrode of a lithium rechargeable battery, which increases adhesion between the electrode and an active material by saving characteristics of two monomers by grafting an acryl group to a vinyl alcohol group, and an electrode for a rechargeable battery comprising the same are provided. The electrode can improve charge and discharge cycle life characteristics of the rechargeable battery.
US09263745B2	Rechargeable electrochemical battery cell Rechargeable lithium battery cell having a housing, a positive electrode, a negative electrode and an electrolyte containing a conductive salt, wherein the electrolyte is based on SO2 and the positive electrode contains an active material in the composition LixM′yM″z(XO4)aFb, wherein M′ is at least one metal selected from the group consisting of the elements Ti, V, Cr, Mn, Fe, Co, Ni, Cu and Zn, M″ is at least one metal selected from the group consisting of the metals of the groups II A, III A, IV A, V A, VI A, IB, IIB, IIIB, IVB, VB, VIB and VIIIB, X is selected from the group consisting of the elements P, Si and S, x is greater than 0, y is greater than 0, z is greater than or equal to 0, a is greater than 0 and b is greater than or equal to 0.
US09263744B2	Active material, electrode, secondary battery, battery pack, electric vehicle, electric power storage system, electric power tool, and electronic apparatus A secondary battery includes: a cathode; an anode; and an electrolytic solution. The anode includes a lithium composite oxide represented by following Formula (1), LiwZnxSnyMzO4 (1) where M is one or more of Co, Mg, Ni, Ca, Al, Ti, V, Cr, Mn, Fe, Cu, and Ag; and w to z satisfy 0.3≦w≦1, 0.3≦x≦1, 0.8≦y≦1.2, and (w+x+y+z)=3.
US09263742B2	Negative electrode active substance for lithium secondary battery and method for producing same The present invention provides an anode material for a lithium secondary battery, which material realizes prolongation of the cycle life of a lithium secondary battery. The present invention relates to an anode active material for a lithium secondary battery, the active material containing a powder produced by a step of forming an etched foil through etching of both surfaces of a foil of Al having a purity of 90 mass % or higher, and a step of shredding the etched foil, the steps being carried out in this order.
US09263739B2	Composite anode active material, method of preparing the same, and lithium battery including the composite anode active material In an aspect, a composite anode active material including lithium titanium oxide particles; and a TiN, and TiN a method of preparing the composite anode active material, and a lithium battery including the composite anode active material is provided.
US09263735B2	Anode and battery An anode and battery including the anode capable of improving the cycle characteristics while securing the input and output characteristics is provided. The battery includes a cathode, an anode, and an electrolytic solution. The anode includes an anode active material layer on an anode current collector, wherein the anode active material layer includes an anode active material capable of intercalating and deintercalating an electrode reactant, wherein a thickness of the anode active material layer ranges from 60 μm to 120 μm, and wherein the anode active material includes a carbon material and at least part of a surface is covered by a covering, the covering including at least one of an alkali metal salt and an alkali earth metal salt.
US09263732B2	Positive electrode active material for lithium-ion battery, positive electrode for a lithium-ion battery, lithium-ion battery using same, and precursor to a positive electrode active material for a lithium-ion battery The present invention provides a positive electrode active material for lithium ion batteries, which realizes a lithium ion battery that is, while satisfying fundamental characteristics of a battery (capacity, efficiency, load characteristics), low in the resistance and excellent in the lifetime characteristics. In the positive electrode active material for lithium ion batteries, the variation in the composition of transition metal that is a main component inside of particles of or between particles of the positive electrode active material, which is defined as a ratio of the absolute value of the difference between a composition ratio inside of the particles of or in a small area between the particles of the transition metal and a composition ratio in a bulk state to the composition ratio in a bulk state of the transition metal, is 5% or less.
US09263728B2	Electrode composite A composite electrode includes a mixture of active matter (AM) particles and EC material particles generating an electronic conductivity, the mixture being supported by an electrical lead forming a DC current collector. The electrode can be manufactured by a method which consists of modifying the AM particles and the EC particles so as to react with each other and with the material of the collector in order to form covalent and electrostatic bonds between said particles, as well as between the particles and the current collector, and then placing the different constituents in contact.
US09263726B2	Secondary battery A secondary battery is disclosed. In one embodiment, the secondary battery includes i) a first electrode plate having two opposing surfaces, wherein the first electrode plate comprises a first electrode collector and a first electrode coating portion disposed on at least one of the two surfaces of the first electrode collector and ii) a second electrode plate having two opposing surfaces, wherein the second electrode plate comprises a second electrode collector and a second electrode coating portion disposed on at least one of the two surfaces of the second electrode collector. The secondary battery may further include a separator disposed between the first and second electrode plates and electrically insulating the first and second electrode plates from each other. The first electrode plate may further include a first electrode tab that extends from a first side surface of the first electrode collector, wherein the first side surface connects the two opposing surfaces of the first electrode collector, and wherein the first electrode coating portion extends to an extension region of the first electrode tab. The second electrode plate may further include a second electrode tab that extends from a second side surface of the second electrode collector, where in the second side surface connects the two opposing surfaces of the second electrode collector, and wherein the second electrode coating portion extends to an extension region of the second electrode tab.
US09263725B2	Secondary battery case and method for manufacturing secondary battery Provided are a secondary battery case and a method for manufacturing a secondary battery. The secondary battery case includes a can accommodating an electrode assembly and a top cap sealing an upper opening of the can. The top cap includes a top plate sealing the upper opening of the can, a filling hole passing through the top plate to fill an electrolyte into the can, and a protrusion protruding from the top plate on an upper portion of the filling hole. The protrusion is press-fitted into the filling hole to seal the filling hole. According to the present invention, the protrusion may protrude from the top plate. Thus, the protrusion may be press-fitted into the filling hole and thus broken to seal the filling hole. Therefore, the member for sealing the filling hole may be integrated with the top plate to reduce manufacturing costs and simplify a manufacturing process.
US09263722B2	Connection structure for a wiring member There is provided a structure for connecting a wiring member to a bus bar in which smooth connection is enabled while ensuring high reliability. In an end portion of a bus bar, a soldering portion which is smaller in cross-sectional area than the bus bar is formed. A connection projecting piece which is raised up in a pin-like manner is formed on the soldering portion. The connection projecting piece is passed through a connection hole which is formed in a connection end of a branch wiring portion of a wiring member configured by a flexible printed circuit board. The connection projecting piece which is passed through the connection hole is soldered to a circuit pattern.
US09263718B2	Battery kit for use with headset A battery kit is provided for use with a headset including a headband, and an upper support portion coupled to the headband. An electronic component is coupled to the headset. The electronic component is coupled to a power port configured to receive a power plug. The battery kit includes a power source, a power plug coupled to the power source, and a coupling mechanism configured to removably couple the power source to the upper support portion. The power plug is coupleable to the power port.
US09263715B2	Battery pack, electric tool and battery charger A battery pack includes a casing having an opening, an engaging member having a stopper, and a regulating member configured to regulate a movement of the engaging member. The engaging member is supported in a slidable and rotatable manner relative to the casing, and is applied with a biasing force such that the stopper projects from the opening. The regulating member includes a contact portion configured to block a rotation of the engaging member and an operating portion configured to displace the contact portion to release a blocking of the rotation of the engaging member. When the operating portion is a non-operated state, the engaging member is slidable against the biasing force to retract the stopper. When the operating portion is in an operated state, the engaging member is rotatable against the biasing force to retract the stopper.
US09263714B2	Power source encapsulation A system includes a power source having a set of power terminals, a cover encapsulating the power source including the set of power terminals and sealing the power source including the set of power terminals within the cover, and a set of conductive contacts passing through the cover, contacting the set of power terminals, and providing conductive access to the set of power terminals of the power source from outside the cover without allowing exposure of the power source to an environment outside the cover.
US09263713B2	Battery pack A battery pack includes a battery module including a plurality of battery cells; a housing accommodating the battery cells, the housing having a bottom plate and a plurality of side walls extending from the bottom plate; and a middle cover covering the battery module, the middle cover having a body and a coupling flange extending away from the body and located between one of the side walls and the battery module.
US09263711B2	Organic light-emitting display device and method of manufacturing the same An organic light-emitting display device and a method of manufacturing the organic light-emitting display device are provided. The organic light-emitting display device includes a plurality of pixels each including: a first region including a light-emitting region for emitting light, a first electrode and an emission layer covering the first electrode being located in the light-emitting region; and a second region including a transmissive region for transmitting external light through the display device. The display device also includes: a third region between the pixels; a first auxiliary layer in the first and third regions; a second electrode on the first auxiliary layer in the first and third regions; a second auxiliary layer covering the second electrode and located in the first and second regions and not in the third region; and a third electrode on the second electrode in the third region.
US09263707B2	Mask assembly and method of fabricating organic light emitting display device using the same A mask assembly and a method of fabricating an organic light emitting display device using the same are provided. The mask assembly includes: a mask frame including a window therein; and a mask which is disposed on the window and fixed to the mask frame, wherein the mask includes a plurality of open parts and a plurality of blocked parts which extend in a column direction. Each open part and each blocked part may alternately be arranged in a row direction. Each open part may include a plurality of pixel openings and a plurality of pixel connection openings, which are alternately arranged in the column direction, and a maximum width of the pixel opening may be larger than a maximum width of the pixel connection opening.
US09263703B2	Display apparatus and method of manufacturing the same A display apparatus includes a substrate, a display unit on the substrate and including an emission area and a non-emission area, a first blocking layer at the non-emission area on the display unit, the first blocking layer having a thickness that tapers toward an edge of the first blocking layer, and a second blocking layer on the first blocking layer and configured to block external light reflection.
US09263694B2	Organic EL element, display device, and illuminating device There is provided an organic EL element including a light emitting unit including at least a plurality of light emitting layers each containing an organic compound and emitting light when a predetermined potential difference is supplied and an intermediate layer that is arranged between the light emitting layers to inject electric charge into the light emitting layers, an anode and a cathode between which the light emitting unit is interposed in a stacking direction and which supply the predetermined potential difference to the light emitting unit, and a potential control mechanism configured to control potential of the intermediate layer in a manner that the potential is set to potential between potential of the anode and potential of the cathode.
US09263693B2	Light-emitting element, light-emitting device, electronic device, and lighting device A light-emitting element having high external quantum efficiency is provided. A light-emitting element having a long lifetime is provided. A light-emitting element includes a light-emitting layer between a pair of electrodes. The light-emitting layer contains at least a phosphorescent compound, a first organic compound (host material) having an electron-transport property, and a second organic compound (assist material) having a hole-transport property. The light-emitting layer has a stacked-layer structure including a first light-emitting layer and a second light-emitting layer, and the first light-emitting layer contains a higher proportion of the second organic compound than the second light-emitting layer. In the light-emitting layer (the first light-emitting layer and the second light-emitting layer), a combination of the first organic compound and the second organic compound forms an exciplex.
US09263692B2	Organic light emitting diode having emission layer with host, emitting dopant and auxiliary dopant and method of fabricating the same Provided is an organic light emitting diode which can easily control color coordinates and improve a device's life span characteristic by using an auxiliary dopant having a higher band gap energy than that of a host, and preferably, having an absolute value of the highest occupied molecular orbital energy level equal to or higher than that of the host, or an absolute value of the lowest unoccupied molecular orbital energy level equal to or lower than that of the host. The organic light emitting diode includes a first electrode, an emission layer disposed on the first electrode and including a host, an emitting dopant and an auxiliary dopant, and a second electrode disposed on the emission layer. Here, the auxiliary dopant has a higher band gap energy than the host. A method of fabricating the organic light emitting diode is provided.
US09263689B2	Organic optoelectronic devices incorporating plasmonic electrodes An organic optoelectronic device that includes a substrate and a plurality of structures disposed thereon, the structures include: (a) a first electrode; vertically separated from (b) a second electrode by (c) an electrode gap that includes an organic photoactive layer disposed within the gap, wherein one of the electrodes includes a plurality of plasmonic nanopores or metal nanostructures, wherein the nanostructures project towards the electrode gap and the metal is selected from gold, aluminum, silver, calcium, copper, and nickel is presented.
US09263687B2	Organic molecular memory An organic molecular memory in an embodiment includes a first conducive layer, a second conductive layer, and an organic molecular layer provided between the first conductive layer and the second conductive layer, the organic molecular layer having an organic molecule, the organic molecule having a linker group bonded to the first conductive layer, a π conjugated chain bonded to the linker group, and a phenyl group bonded to the π conjugated chain opposite to the linker group and facing the second conductive layer, the π conjugated chain including electron-accepting groups or electron-donating groups arranged in line asymmetry with respect to a bonding direction of the π conjugated chain, the phenyl group having substituents R0, R1, R2, R3, and R4 as shown in the following formula, the substituent R0 being an electron-accepting group or an electron-donating group.
US09263682B2	Light emitting device and display unit A light emitting device is configured to include a substrate and a luminous layer provided overlying the substrate, which includes a semiconductor nanocrystal to which a carbazole derivative is coordination-bonded or attached, the carbazole derivative having aromatic rings of a compound represented by the chemical structure 1, which is substituted by one to three substitution groups: The one to three substitution groups are represented by the chemical structure 2: -X-Y-Z Chemical Structure 2. X represents a methylene group, a carbonyloxy group, an oxycarbonyl group, a carbonyl group, an oxygen atom, and a sulfur atom, Y represents a substituted or non-substituted alkylene group, and Z represents a carboxyl group, a hydroxyl group, and a thiol group.
US09263678B2	Method for manufacturing organic solar cell A method of manufacturing an organic solar cell is provided. According to the exemplary embodiments of the present invention, a laminate section can be easily removed from a substrate by causing a cleaning unit to move up and down above the substrate or to move forward and backward in a reciprocating manner in the width direction of the substrate. Furthermore, when a contact member is detachably connected to the cleaning unit, the contact member that has been contaminated with a laminate material can be separated from the cleaning unit and easily washed. Also, the laminate section can be removed by spraying a solvent through a discharging unit to dissolve the laminate section, and suctioning the laminate section through a suctioning unit. In this case, the laminate section can be easily removed from the substrate by dissolving the laminate section with the solvent.
US09263677B2	Method for manufacturing a transparent gas barrier film A method for manufacturing a transparent gas barrier film for an organic electroluminescence element having a substrate with a gas barrier layer thereon. The gas barrier layer is formed on the substrate by plasma CVD using an organic silicon compound as a raw material gas and an oxygen gas as a decomposition gas. Formation of the gas barrier layer is carried out so that a carbon content of the gas barrier layer in the thickness direction repeatedly changes more than two times from high value, via intermediate value, low value and intermediate value, to high value.
US09263665B1	Two-bits per cell structure with spin torque transfer magnetic random access memory and methods for fabricating the same A method of fabricating a vertical two-bits per cell STT MRAM for high density storage includes forming a bottom electrode within an interlayer dielectric (ILD) layer, forming an anti-ferromagnetic (AF) layer over the bottom electrode, and forming a fixed layer along sidewalls of the AF layer. The method further includes forming a tunnel layer along the fixed layer, forming a free layer along the tunnel layer, and forming a top electrode along the free layer and over an upper surface of the AF layer.
US09263659B2	System and method for thermal protection of an electronics module of an energy harvester A thermoelectric energy harvesting system may include a thermoelectric generator and an electronics module. The thermoelectric generator may produce a voltage in response to a temperature difference across the thermoelectric generator and generate power when coupled to a load. The system may include a housing mounted on top of the thermoelectric generator. The housing may include a cavity containing the electronics module. The electronics module may condition the power generated by the thermoelectric generator. The cavity may be enclosed by an inner surface of the housing. A radiation shield may cover at least a portion of the inner surface and may block radiative heating of the cavity from the housing.
US09263658B2	Light-emitting device and method of manufacturing the same Disclosed are a light-emitting device and a manufacturing method thereof. A light-emitting device according to an exemplary embodiment of the present invention includes a base, a lighting element disposed on the base, the lighting element including an epitaxial layer and a substrate disposed on the epitaxial layer, a contact member disposed between the lighting element and the base, the contact member electrically connecting the lighting element and the base, and a lens disposed on the substrate.
US09263650B2	Epitaxial substrate, light-emitting diode, and methods for making the epitaxial substrate and the light-emitting diode An epitaxial substrate includes: a base member; and a plurality of spaced apart light-transmissive members, each of which is formed on and tapers from an upper surface of the base member, and each of which is made of a light-transmissive material having a refractive index lower than that of the base member. A light-emitting diode having the epitaxial substrate, and methods for making the epitaxial substrate and the light-emitting diode are also disclosed.
US09263649B2	Layered product for fine pattern formation and method of manufacturing layered product for fine pattern formation Disclosed is a layered product for fine pattern formation and a method of manufacturing the layered product for fine pattern formation, capable of easily forming a fine pattern having a thin or no remaining film in order to form a fine pattern having a high aspect ratio on a processing object. The layered product for fine pattern formation (1) of the present invention used to form a fine pattern (220) in a processing object (200) using a first mask layer (103) includes: a mold (101) having a concavo-convex structure (101a) on a surface; and a second mask layer (102) provided on the concavo-convex structure (101a), wherein in the second mask layer (102), a distance (lcc) and a height (h) of the concavo-convex structure (101a) satisfy Formula (1) 0
US09263645B2	Light-emitting element, light-emitting device, and electronic device The present invention provides a light-emitting element, a light-emitting device and an electronic device in which an optical path length through which generated light goes can be changed easily. The present invention provides a light-emitting element including a light-emitting layer between a first electrode and a second electrode, and a mixed layer in contact with the first electrode; in which the light-emitting layer includes a light-emitting substance; the mixed layer includes a hole transporting substance and a metal oxide showing an electron accepting property to the hole transporting substance, and has a thickness of 120 to 180 nm, and when a voltage is applied between the first electrode and the second electrode such that a potential of the first electrode is higher than that of the second electrode, the light-emitting substance emits light.
US09263641B2	Light emitting diodes An electric contact structure adopted for an LED comprises a nitride middle layer and an N-type metal electrode layer. The LED includes an N-type semiconductor layer, a light emission layer and a P-type semiconductor layer that are stacked to form a sandwich structure. The nitride middle layer is patterned and formed on the N-type semiconductor layer. The N-type metal electrode layer is formed on the nitride middle layer and prevented from being damaged by diffusion of the metal ions as the nitride middle layer serves as a blocking interface, thus electric property of the N-type semiconductor layer can be maintained stable. The nitride middle layer would not be softened and condensed due to long-term high temperature, thereby is enhanced adhesion. Moreover, the N-type metal electrode layer further can be prevented from peeling off, hence is increased the lifespan of the LED.
US09263640B2	Semiconductor light emitting device According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a p-side metal pillar, an n-side metal pillar, and an insulator. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side metal pillar includes a p-side external terminal. The n-side metal pillar includes an n-side external terminal. At least one selected from an area and a planar configuration of the p-side external terminal is different from at least one selected from an area and a planar configuration of the n-side external terminal.
US09263637B2	Plasmonic light emitting diode A light emitting diode (100 or 150) includes a diode structure containing a quantum well (120), an enhancement layer (142), and a barrier layer (144 or 148) between the enhancement layer (142) and the quantum well (120). The enhancement layer (142) supports plasmon oscillations at a frequency that couples to photons produced by combination of electrons and holes in the quantum well (120). The barrier layer serves to block diffusion between the enhancement layer (142) and the diode structure.
US09263636B2	Light-emitting diode (LED) for achieving an asymmetric light output A light emitting diode (LED) for achieving an asymmetric light output includes a multilayered structure comprising a p-n junction, where at least one layer of the multilayered structure comprises a surface configured to provide a peak emission in a direction away from a normal to a mounting surface, the surface being a top or bottom surface of the layer.
US09263635B2	Semiconductor structure A semiconductor structure includes a silicon substrate, a buffer layer, a nitride-based epitaxial structure layer and multiple discontinuous strain-releasing layers. The buffer layer is disposed on the silicon substrate. The nitride-based epitaxial structure layer is disposed on the buffer layer. The discontinuous strain-releasing layers are disposed between the silicon substrate and the nitride-based epitaxial structure layer, wherein a material of the discontinuous strain-releasing layers is silicon nitride.
US09263633B2	Nanowire-based optoelectronic device for light-emission A light-emitting diode is provided, including an active semiconductor area for the radiative recombination of electron-hole pairs having a plurality of nanowires, each made of an unintentionally doped semiconductor material, a first semiconductor area for radially injecting holes into each nanowire, the first semiconductor area being made of a doped semiconductor material having a first conductivity type and having a bandgap that is greater than the bandgap of the semiconductor material of the nanowires, and a second semiconductor area for axially injecting electrons into each nanowire, the second semiconductor area being made of a doped semiconductor material having a second conductivity type that is opposite to that of the first conductivity type.
US09263631B2	Semiconductor light emitting device and method for manufacturing same According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.
US09263629B2	Semiconductor light emitting device and light coupling device According to one embodiment, a semiconductor light emitting device includes a semiconductor laminated body provided on a semiconductor substrate. The semiconductor laminated body includes a light emitting layer. The light emitting layer includes a quantum well structure made by alternately laminating n (an integer of not less than 1) well layers and (n+1) barrier layers and emits light with a peak wavelength of 650 nm to 1000 nm. Each of the well layers has a thickness of smaller than 15 nm. Each of the barrier layers has a thickness of 15 nm to 50 nm.
US09263624B2	High-output apparatus for manufacturing a polycrystal silicon ingot for a solar cell The present invention relates to a high-output apparatus for manufacturing a polycrystal silicon ingot for a solar cell, and more particularly, to an apparatus for manufacturing a polycrystal silicon ingot by means of heating and melting raw silicon in a vacuum chamber, and then cooling the molten silicon, wherein the apparatus comprises: a plurality of crucibles arranged so as to be horizontally separated from one another within the vacuum chamber, and in each of which raw silicon is filled for manufacturing polycrystal silicon ingots; heating means provided at the outside of each of the crucibles so as to heat each crucible and melt the raw silicon filled therein; and cooling means for cooling the crucibles, so as to enable the silicon melted by the heating means to be cooled in one direction and be formed into polycrystal ingots.
US09263622B2	Method of fabricating a solar cell Methods of fabricating solar cells are described. A porous layer may be formed on a surface of a substrate, the porous layer including a plurality of particles and a plurality of voids. A solution may be dispensed into one or more regions of the porous layer to provide a patterned composite layer. The substrate may then be heated.
US09263621B2	Inclined photonic chip package for integrated optical transceivers and optical touchscreen assemblies An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation.
US09263615B2	Non-power cooling type solar panel The present invention relates to a solar panel that is cooled without using power, and more particularly, to a solar panel which is cooled without using power and which is naturally cooled by means of ascending air heated in a passage provided in a cooling plate so as to maintain the temperature of the solar panel suitable for the efficient generation of power without requiring a separate power source. For this purpose, the solar panel of the present invention includes: a cell panel including solar cells for converting solar energy into electric energy; and a cooling plate directly or indirectly contacting the back surface of the cell panel so as to transfer heat, the cooling plate having a cooling-air passage which is formed so as to extend vertically within the cooling plate, and the upper and lower ends of which are in contact with the outside air.
US09263614B2	In-fiber filament production In a fiber there is provided a fiber matrix material having a fiber length; and an array of isolated in-fiber filaments that extend the fiber length. The in-fiber filaments are disposed at a radius in a cross section of the fiber that is a location of a continuous filament material layer in a drawing preform of the fiber. As a result, there is provided a fiber matrix material having a fiber length; and a plurality of isolated fiber elements that are disposed in the fiber matrix, extending the fiber length, where the plurality is of a number greater than a number of isolated domains in a drawing preform of the fiber.
US09263612B2	Heterojunction wire array solar cells This disclosure relates to structures for the conversion of light into energy. More specifically, the disclosure describes devices for conversion of light to electricity using ordered arrays of semiconductor wires coated in a wider band-gap material.
US09263607B2	Photodetector using graphene and method of manufacturing the same A photodetector using graphene includes: a gate electrode; a graphene channel layer which is opposite to and spaced apart from the gate electrode and does not have π-binding; a first electrode which contacts a first side of the graphene channel layer; and a second electrode which contacts a side of the graphene channel layer, where the first and second sides are opposite to each other, and where the graphene channel layer includes a first graphene layer and a first nanoparticle disposed on the first graphene layer. The first graphene layer may include a single graphene layer, or the first graphene layer may include a plurality of single graphene layers, which is sequentially stacked and does not have π-binding.
US09263605B1	Pulsed stimulated emission luminescent photovoltaic solar concentrator A solar concentrator comprising: a light-transmissive sheet including: a plurality of luminescent particles capable of becoming excited by absorbing light within at least a first spectrum of absorption frequencies and, once excited, capable of being stimulated to emit light having a spectrum within at least a first spectrum of emission frequencies; and a first light-guide; and a light source for generating a pulsed probe light having a spectrum, at least a portion of which is within at least the first spectrum of emission frequencies, for stimulating at least one of the excited luminescent particles having absorbed light within the first spectrum of absorption frequencies such that when the probe light traveling in a first direction of travel stimulates the excited luminescent, the excited luminescent particles emit emitted light having a spectrum within the first spectrum of emission frequencies in the first direction of travel of the probe light.
US09263599B2	Semiconductor system and method for manufacturing same A semiconductor system having a trench MOS barrier Schottky diode is described, including an n-type epitaxial layer, in which at least two etched trenches are located in a two-dimensional manner of presentation on an n+-type substrate which acts as the cathode zone. An electrically floating, p-type layer, which acts as the anode zone of the p-n type diode, is located in the n-type epitaxial layer, at least in a location below the trench bottom. An oxide layer is located between a metal layer and the surface of the trenches. The n-type epitaxial layer may include two n-type layers of different doping concentrations.
US09263598B2	Schottky device and method of manufacture A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.
US09263595B2	Non-volatile memories and methods of fabrication thereof Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode.
US09263594B2	Thin film transistor array baseplate An embodiment of the present invention provides a TFT array substrate including: a base substrate (1) and thin film transistors. The thin film transistor includes a gate electrode (2), a semiconductor layer (5), a semiconductor protective layer, a source electrode (8) and a drain electrode (9). The semiconductor protective layer is disposed adjacent to the semiconductor layer (5) and includes a composite lamination structure, which includes a protective layer formed of an insulating material capable of preventing de-oxygen of the semiconductor layer (5) and an insulating layer formed of an insulating material to be etched more easily.
US09263591B2	Metal oxide field effect transistors on a mechanically flexible polymer substrate having a die-lectric that can be processed from solution at low temperatures The present invention relates to a method for producing an electronic component, in particular a field-effect transistor (FET), comprising at least one substrate, at least one dielectric, and at least one semiconducting metal oxide, wherein the dielectric or a precursor compound thereof based on organically modified silicon oxide compounds, in particular based on silsequioxanes and/or siloxanes, can be processed out of solution, and is thermally treated at a low temperature from room temperature to 350° C., and the semiconductive metal oxide, in particular ZnO or a precursor compound thereof, can also be processed from solution at a low temperature from room temperature to 350° C.
US09263589B2	Semiconductor device An object of the present invention is to manufacture a semiconductor device where fluctuation in electrical characteristics is small and reliability is high in a transistor in which an oxide semiconductor is used. An insulating layer from which oxygen is released by heating is used as a base insulating layer of an oxide semiconductor layer which forms a channel. Oxygen is released from the base insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the base insulating layer and the oxide semiconductor layer can be reduced. Thus, a semiconductor device where fluctuation in electrical characteristics is small and reliability is high can be manufactured.
US09263586B2	Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.
US09263579B2	Semiconductor process for modifying shape of recess A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
US09263572B2	Semiconductor device with bottom gate wirings A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.
US09263571B2	Silicon carbide semiconductor device and manufacturing method thereof When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time.
US09263568B2	Fluctuation resistant low access resistance fully depleted SOI transistor with improved channel thickness control and reduced access resistance The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional δ-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor.
US09263565B2	Method of forming a semiconductor structure A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer.
US09263556B2	Silicide process using OD spacers A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region.
US09263555B2	Methods of forming a channel region for a semiconductor device by performing a triple cladding process One illustrative method disclosed herein includes, among other things, forming a plurality of trenches that define a fin, performing a plurality of epitaxial deposition processes to form first, second and third layers of epi semiconductor material around an exposed portion of the fin, removing the first, second and third layers of epi semiconductor material from above an upper surface of the fin so as to thereby expose the fin, selectively removing the fin relative to the first, second and third layers of epi semiconductor material so as to thereby define two fin structures comprised of the first, second and third layers of epi semiconductor material, and forming a gate structure around a portion of at least one of the fin structures comprised of the first, second and third layers of epi semiconductor material.
US09263554B2	Localized fin width scaling using a hydrogen anneal Transistors and methods for fabricating the same include forming one or more semiconductor fins on a substrate; covering source and drain regions of the one or more semiconductor fins with a protective layer; annealing uncovered channel portions of the one or more semiconductor fins in a gaseous environment to reduce fin width and round corners of the one or more semiconductor fins; and forming a dielectric layer and gate over the thinned fins.
US09263553B2	Transistor and its method of manufacture A transistor includes a substrate, a source terminal and a drain terminal, each terminal being supported by the substrate, and the source and drain terminal being separated by a portion of the substrate, a layer of semiconductive material deposited so as to cover the portion of the substrate and to connect the source terminal to the drain terminal, a layer of dielectric material deposited so as to cover at least a portion of the layer of semiconductive material, and a layer of electrically conductive material deposited so as to cover at least a portion of the layer of dielectric material. The layer of electrically conductive material providing a gate terminal to which a potential may be applied to control a conductivity of the layer of semiconductive material connecting the source and drain terminals.
US09263552B2	MOS-transistor with separated electrodes arranged in a trench A MOS transistor is produced by forming a first trench in a semiconductor body, forming a first isolation layer on inner surfaces of the first trench, and filling the first trench with conductive material to form a first electrode within the first trench. A portion of the first electrode is removed along one side wall of the first trench to form a cavity located within the first trench. A second isolation layer is formed on inner surfaces of the cavity, and the cavity is at least partially filled with conductive material to form a second electrode within the cavity. A structured third isolation layer is formed on a top surface of the semiconductor body, and a metallization layer is formed on the structured third isolation layer. The first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer.
US09263550B2	Gate to diffusion local interconnect scheme using selective replacement gate flow A method of fabricating a device is provided which includes selectively implanting one or more dopants into a semiconductor wafer so as to form doped and undoped regions of the wafer; forming fins in the wafer with at least a given one of the fins being formed both from a portion of the doped region of the wafer and from a portion of the undoped region of the wafer; forming dummy gates on the wafer; depositing a filler layer around the dummy gates; removing the dummy gates forming trenches in the filler layer, at least one of which extends down to the undoped portion of the fin and at least another of which extends down to the doped portion of the fin; selectively forming a gate dielectric lining the trenches which extend down to the undoped portion of the fin; and forming replacement gates in the trenches.
US09263549B2	Fin-FET transistor with punchthrough barrier and leakage protection regions A method of forming a field effect transistor includes forming a punchthrough region having a first conductivity type in a substrate, forming an epitaxial layer having the first conductivity type on the substrate, patterning the epitaxial layer to form a fin that protrudes from the substrate, forming a dummy gate and gate sidewall spacers on the fin defining preliminary source and drain regions of the fin on opposite sides of the dummy gate, removing the preliminary source and drain regions of the fin, implanting second conductivity type dopant atoms into exposed portions of the substrate and the punchthrough region, and forming source and drain regions having the second conductivity type on opposite sides of the dummy gate and the gate sidewall spacers.
US09263548B2	Method for manufacturing semiconductor devices using self-aligned process to increase device packing density A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.
US09263546B2	Method of fabricating a gate dielectric layer A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.
US09263543B2	Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device includes (a) providing a silicon carbide semiconductor substrate; and (b) forming an electrode structure on the silicon carbide semiconductor substrate by (i) forming a Schottky layer including a metal selected from the group consisting of titanium, tungsten, molybdenum, and chrome on a front surface of the silicon carbide semiconductor substrate; (ii) heating the Schottky layer to form a Schottky electrode which has a Schottky contact with the silicon carbide semiconductor substrate; and (iii) forming a surface electrode comprised of aluminum or aluminum including silicon on a surface of the Schottky electrode, while heating at a temperature range effective for the surface electrode to closely cover any uneven portion of the Schottky electrode and provide a surface electrode having a predetermined reflectance that is equal to or less than 80% so that an improved recognition rate by an automatic wire bonding apparatus is obtained.
US09263539B2	Thin-film transistor and fabrication method thereof, array substrate and display device Embodiments of the invention provide a thin-film transistor and a fabrication method thereof, an array substrate and a display device. The thin-film transistor comprises a gate electrode (2), an active layer (4), source and drain electrodes (6), and a gate insulating layer (3) provided between the gate electrode (2) and the active layer (4). The gate electrode (2) comprises a gate electrode metal layer (23) and a first protection layer (32), the first protection layer (32) is provided between the gate electrode metal layer (23) and the gate insulating layer (3) to isolate the active layer (4) from the gate electrode metal layer (23). The gate electrode metal layer (23) is made of copper or copper alloy.
US09263537B2	Methods of forming a semiconductor device with a protected gate cap layer and the resulting device One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.
US09263536B2	Methods of fabricating semiconductor devices with electrode support patterns Methods include sequentially forming a first mold film, a first support film, a second mold film, and a second support film on a substrate, forming a contact hole through the second support film, the second mold film, the first support film and the first mold film, forming an electrode in the contact hole, and removing portions of the second support film, the second mold film and the first mold film to leave a portion of the first support film as a first support pattern surrounding the electrode and to leave a portion of the second support film as a second support pattern surrounding the electrode.
US09263533B2	High-voltage normally-off field effect transistor including a channel with a plurality of adjacent sections A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel.
US09263526B2	Semiconductor component A semiconductor component (1, 20, 30) comprising a semiconductor substrate (3) composed of silicon carbide and comprising separate electrodes (4, 5) applied thereto, said electrodes each comprising at least one monolayer of epitaxial graphene (11) on silicon carbide, in such a way that a current channel is formed between the electrodes (4, 5) through the semiconductor substrate (3).
US09263525B2	Silicon carbide semiconductor device and manufacturing method thereof The present invention includes an n+ type substrate, a drift epitaxial layer formed on the n+ type substrate and having a lower concentration of impurity than the n+ type substrate, a Schottky electrode formed on the drift epitaxial layer, and a PI formed as an insulating film by covering at least an end of the Schottky electrode and an end and a side surface of the drift epitaxial layer.
US09263519B2	Nanowire array structures for sensing, solar cell and other applications Nanowire array structures based on periodic or aperiodic nanowires are provided in various configurations for sensing and interacting with light and substances to provide various functions such as sensors for detecting DNAs and others and solar cells for converting light into electricity.
US09263515B2	Super-junction schottky PIN diode A semiconductor chip has an n+-doped substrate, above which an n-doped epilayer having trenches is introduced, the trenches being filled with p-doped semiconductor material and in each case having a highly p-doped region at their top side, such that an alternating arrangement of n-doped regions having a first width and p-doped regions having a second width is present. A first metal layer functioning as an anode is provided on the front side of the chip and forms a Schottky contact with the n-doped epilayer and forms an ohmic contact with the highly p-doped regions. A second metal layer which represents an ohmic contact and functioning as a cathode is formed on the rear side of the semiconductor chip. A dielectric layer is provided between each n-doped region and an adjacent p-doped region.
US09263511B2	Package with metal-insulator-metal capacitor and method of manufacturing the same A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.
US09263510B2	EL display device A EL display device has EL display panel including the a display area where a pixel is arranged in matrix, and a wiring pattern formed in a circumferential portion of the display area and supplying voltage to a pixel. The EL display panel includes a flexible substrate having an electrode connected to a source signal line or a gate signal line arranged thereon. The flexible substrate includes an anode reinforcement wiring and a cathode reinforcement wiring which are electrically parallel to the wiring pattern.
US09263509B2	Pixel structure having light emitting device above auxiliary electrode A pixel structure, including a data line, a scan line, at least one active device, a first auxiliary electrode, and a light emitting device, is provided. The at least one active device is electrically connected with the data line and the scan line, and each active device includes a gate, a channel layer, a source, and a drain. The first auxiliary electrode is electrically insulated from the active device. The light emitting device is disposed above the first auxiliary electrode, wherein the light emitting device includes a first electrode layer, a light emitting layer, and a second electrode layer. The first electrode layer is electrically connected with the first auxiliary electrode. The light emitting layer is disposed on the first electrode layer. The second electrode layer is disposed on the light emitting layer, wherein the second electrode layer is electrically connected with the active device.
US09263508B2	Display panel and system for displaying images utilizing the same An embodiment of the invention provides a display panel, which includes a substrate having a pixel region and a peripheral region, a control element overlying the pixel region of the substrate, a conducting layer overlying the substrate in the peripheral region, a first insulating layer overlying the conducting layer in the peripheral region, wherein a ratio between an area of the first insulating layer and an area of the conducting layer in the peripheral region is between about 0.27 and 0.99, a lower electrode layer overlying the first insulating layer, and a second insulating layer overlying the lower electrode layer.
US09263506B2	Organic light emitting diode (OLED) display including curved OLED An organic light emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a flexible substrate and a plurality of OLEDs. The flexibility substrate includes at least one curved portion. The OLEDs are positioned in every pixel area that is set on the flexible substrate and includes a pixel electrode, an organic emission layer, and a common electrode. At least one OLED that is positioned at a curved portion in the OLEDs is formed in a lens shape and concentrates light toward the center of a pixel area.
US09263505B2	Display, method for driving display, and electronic apparatus having parallel holding capacitors Disclosed herein is a display including: a pixel array part configured to include pixels that are arranged in a matrix, each having an electro-optical element, a write transistor for writing a video signal, a drive transistor for driving the electro-optical element based on the video signal written by the write transistor, and a holding capacitor connected between the gate and source of the drive transistor, wherein the holding capacitor includes a first electrode, a second electrode disposed to face one surface of the first electrode for forming a first capacitor, and a third electrode disposed to face the other surface of the first electrode for forming a second capacitor, and the first capacitor and the second capacitor are connected in parallel to each other electrically.
US09263504B2	Light-emitting device, information processing device, and imaging device Provided is a light-emitting device and an information processing device which include a light-emitting element mounted on a housing and an optical component detachable from the housing. The optical component is capable of condensing light emitted from the light-emitting element. This structure allows a user to select the emission of diffused light and condensed light by attaching or detaching the optical component.
US09263501B1	Memory device and method of manufacturing the same According to one embodiment, a memory device includes a first diffusion layer region on, a second diffusion layer region, a third diffusion layer region, a first gate electrode and a second gate electrode. The memory device also includes a first via contact group, a second via contact group and a variable resistance element. At least one of the plurality of first via contacts is electrically connected to the first diffusion layer region with one end and at least one of the plurality of second via contacts is electrically connected to the third diffusion layer region with one end. The variable resistance element being electrically a first interconnect layer.
US09263500B2	Integrated circuit comprising a gas sensor An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a thermal conductivity based gas sensor having an electrically resistive sensor element located on the major surface for exposure to a gas to be sensed. The integrated circuit further includes a barrier located on the major surface for inhibiting a flow of the gas across the sensor element.
US09263493B2	Image pickup element, imaging apparatus, manufacturing apparatus for image pickup element, and manufacturing method for image pickup element Provided is an image pickup element, including: condenser lenses made of a resin containing fine metal particles; photoelectric conversion elements formed in a silicon substrate and each configured to photoelectrically convert incident light that enter from an outside through corresponding one of the condenser lenses; and a protective film made of a silicon compound, the protective film being formed between the condenser lenses and the silicon substrate.
US09263492B2	Image sensor package An image sensor package including a PCB including bonding areas, an image sensor including bonding pads on edge portions thereof on the PCB, bonding wires connecting the bonding pads with the bonding areas, an insulating adhesion film attaching the bonding wires to the bonding pads on the edge portions of the image sensor, a heat spread pattern spaced apart from the bonding wires and the image sensor on the insulating adhesion film, a supporting holder spaced apart from the edge portions of the image sensor, encloses the image sensor, contacts a top surface of the heat spread pattern and the PCB, and includes a supporting portion at an upper portion thereof, and a transparent cover covering the image sensor on the supporting portion of the supporting holder and spaced apart from the top surface of the image sensor is provided.
US09263491B2	Solid-state imaging apparatus, method for manufacturing the same, and camera A back-side illumination solid-state imaging apparatus, comprising a light-shielding member including a plurality of openings, and a plurality of pixels corresponding to the plurality of openings, wherein each pixel includes a photoelectric conversion portion, a microlens and an inner lens, the inner lens of a first pixel of an Mth row×an Nth column and the inner lens of a second pixel of an (M+1)th row×an (N+1)th column are separated from each other through a dielectric member, and the dielectric member contacts with part of the light-shielding member between a first opening corresponding to the first pixel and a second opening corresponding to the second pixel.
US09263489B2	Image sensor with hybrid heterostructure An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter.
US09263488B2	Semiconductor device, manufacturing method of semiconductor device, semiconductor wafer, and electronic equipment The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a semiconductor wafer, and electronic equipment, which allow a semiconductor device, in which miniaturization is possible, to be provided. A semiconductor device includes a semiconductor substrate, a wiring layer that is formed on the semiconductor substrate, and a drive circuit that is provided in a circuit forming region of the semiconductor substrate. Then, the semiconductor device is configured to include a pad electrode that is electrically connected to the drive circuit and exposed from the side surface of the wiring layer, and an external connection terminal that is provided in side surfaces of the semiconductor substrate and the wiring layer, and is electrically connected to the pad electrode.
US09263486B2	Method for forming structure for reducing noise in CMOS image sensors A method and device is disclosed for reducing noise in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes an opaque layer or a black light filter layer in conjunction with an opaque layer, covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer and the black light filter layer where the light blocking portion is desired, but not over the active section. The method also provides for forming microlenses over the photosensors in the active section.
US09263485B2	Solid-state imaging apparatus and method for manufacturing the same The present invention reduces color mixture (cross talk) and the degradation of sensitivity in a peripheral region of a pixel area to achieve a reduction of sensitivity irregularity in the pixel area. A solid-state imaging apparatus having a pixel area including a plurality of photoelectric conversion elements includes: a semiconductor substrate in which the plurality of photoelectric conversion elements are formed; a plurality of air gap formed layers which are arranged above the semiconductor substrate, and correspond to the photoelectric conversion elements in the plurality of photoelectric conversion elements, respectively; and air gaps arranged between the air gap formed layers in the plurality of air gap formed layers, respectively, wherein the air gap in a peripheral region B of the pixel area has a width larger than the air gap in a central region A of the pixel area.
US09263481B2	Array substrate The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.
US09263475B2	Thin film transistor substrate and display apparatus A thin film transistor (TFT) substrate comprises a substrate, a plurality of pixel electrodes, a gate layer, an active layer, a first source layer and a second source layer, and a drain layer. The pixel electrodes are disposed on the substrate. The gate layer is disposed on the substrate. The active layer is disposed corresponding to the gate layer. The first source layer and the second source layer contact the active layer respectively. The drain layer contacts the active layer and is electrically coupled to one of the pixel electrodes. The gate layer, the active layer, the first source layer and the drain layer constitute a first transistor. The gate layer, the active layer, the second source layer and the drain layer constitute a second transistor. When the first and second transistors are disabled, the first and second source layers are electrically isolated from each other.
US09263474B2	Thin film transistor array substrate and organic light-emitting display apparatus including the same A thin film transistor array substrate includes an active area in which a plurality of pixels are formed; driver integrated circuits (DICs) disposed in a non-active area around the active area and configured to supply a driving signal to each of the plurality of pixels; power input units partially overlapping with the DICs, disposed below the DICs, and configured to supply power voltages to the active area; and a user key mounting area formed not to overlap with the DICs in the non-active area. The thin film transistor array substrate may be used for an organic light-emitting display apparatus.
US09263473B2	Oxide semiconductor memory device In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.
US09263472B2	Semiconductor device and method for manufacturing semiconductor device An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.
US09263470B1	Semiconductor device, manufacturing method thereof, and display apparatus Provided is a semiconductor device including a buffer layer that is on a substrate and includes an inclined surface; a crystalline silicon layer that is on the buffer layer; a gate electrode that is on the crystalline silicon layer while being insulated from the crystalline silicon layer; and a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer, the angle between the substrate and the inclined surface being in a range of about 17.5 degrees to less than about 70 degrees.
US09263461B2	Apparatuses including memory arrays with source contacts adjacent edges of sources Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.
US09263456B2	Semiconductor device and method for manufacturing the same A semiconductor device comprises a semiconductor substrate, a first transistor including a gate insulating film and a gate electrode sequentially formed on the semiconductor substrate, a sidewall, an interlayer insulating film formed on the semiconductor substrate, and a contact plug which penetrates through the interlayer insulating film and reaches the semiconductor substrate. The sidewall is formed on a side surface of the gate electrode, and includes a first insulating film and a second insulating film formed on the first insulating film and containing a metal oxide different from the first insulating film.
US09263455B2	Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
US09263454B2	Semiconductor structure having buried conductive elements Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.
US09263452B2	Reservoir capacitor of semiconductor device A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material.
US09263451B2	Storage device including memory cell using transistor having oxide semiconductor and amplifier circuit A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data.
US09263448B2	Semiconductor device with buried metal layer A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.
US09263444B2	Devices having inhomogeneous silicide schottky barrier contacts A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided having a plurality of transistors formed thereon, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region on the silicon including surface. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and n-type surface regions.
US09263442B2	Replacement gate structures and methods of manufacturing Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further includes segmenting the continuous replacement gate structure into separate replacement gate structures. The method further includes forming insulator material between the separate replacement gate structures.
US09263441B2	Implant for performance enhancement of selected transistors in an integrated circuit A first implant is performed into a substrate to form a well in which a plurality of transistors will be formed. Each transistor of a first subset of the plurality of transistors to be formed has a width that satisfies a predetermined width constraint and each transistor of a second subset has a width that does not satisfy the constraint. A second implant is performed at locations in the well in which transistors of the first subset will be formed and not at locations in the well in which transistors of the second subset will be formed. The transistors are formed, wherein a channel region of each transistor of the first subset is formed in a portion of the substrate which received the second implant and a channel region of each transistor of the second subset is formed in a portion of the substrate which did not receive the second implant.
US09263440B2	Power transistor arrangement and package having the same Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second terminal region being electrically isolated from each other; a first power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the main region of the carrier such that its first power electrode is facing towards and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the terminal regions of the carrier such that its control electrode and its first power electrode are facing towards the terminal regions, and having its control electrode being electrically coupled to the first terminal region and its first power electrode being electrically coupled to the second terminal region.
US09263433B2	Integrated circuit, integrated circuit package and method of providing protection against an electrostatic discharge event An integrated circuit comprising a power supply node, a ground node and a gated domain coupled between the power node and the ground node. A Charged Device Model electrostatic discharge protection module is provided for shunting electrical energy of a CDM ESD event away from the gated domain. A gating switch makes an electrical connection in a connected state between the gated domain and at least one of the power node and the ground node. ESD gating control circuitry is coupled to the CDM ESD protection module and controls shunting of energy away from the gated domain by the CDM ESD protection module, thereby avoiding the energy flowing through the gated domain. The ESD gating control circuitry inhibits actuation of the CDM ESD protection module to prevent response to CDM ESD events when the gating domain is powered-up.
US09263430B2	Semiconductor ESD device and method of making same A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
US09263423B2	Interdigitated multiple pixel arrays of light-emitting devices The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
US09263414B2	Flip chip packaging method, and flux head manufacturing method applied to the same Flip chip packaging methods, and flux head manufacturing methods used in the flip chip packaging methods may be provided. In particular, a flip chip packaging method including printing flux on a pad of a printed circuit board (PCB), mounting the die in a flip chip manner on the PCB such that a bump of the die faces the pad of the PCB, and bonding the bump of the die to the pad of the PCB using the flux may be provided.
US09263411B2	Submount, encapsulated semiconductor element, and methods of manufacturing the same The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps, are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount.
US09263408B2	Method for producing microbumps on a semiconductor component The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.
US09263402B2	Self-protected metal-oxide-semiconductor field-effect transistor Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
US09263401B2	Semiconductor device comprising a diode and a method for producing such a device The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction.
US09263396B2	Photo alignment mark for a gate last process A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.
US09263394B2	Multiple bond via arrays of different wire heights on a same substrate An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.
US09263393B2	Sputter and surface modification etch processing for metal patterning in integrated circuits One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.
US09263391B2	Interconnect structures incorporating air-gap spacers A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.
US09263390B2	Semiconductor component that includes a protective structure In accordance with an embodiment a semiconductor component includes an electrically conductive structure formed over a portion of a semiconductor material. An electrical interconnect having a top surface and opposing edges contacts the electrically conductive structure. A protective structure is formed on the top surface and the opposing edges of the electrical interconnect and over a portion of the electrically conductive structure, wherein the protective structure forms a seal that protects the electrical interconnect.
US09263384B2	Programmable devices and methods of manufacture thereof Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.
US09263382B2	Through substrate via structures and methods of forming the same A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.
US09263380B2	Semiconductor interposer and package structure having the same A semiconductor interposer is provided, which includes: a substrate body having a surface defined with an inner area and a peripheral area around the inner area; a plurality of conductive posts embedded in the substrate body and each having one end exposed from the surface of the substrate body; a passivation layer formed on the surface of the substrate body and having a peripheral portion formed in the peripheral area, a plurality of ring-shaped portions formed around peripheries of the exposed ends of the conductive posts in the inner area and a plurality of strip-shaped portions formed between the ring-shaped portions for connecting the ring-shaped portions; and a UBM layer formed on the exposed end of each of the conductive posts and extending on the ring-shaped portion around the periphery of the exposed end of the conductive post, thereby effectively reducing stresses to prevent warping of the semiconductor interposer.
US09263378B1	Ball grid array and land grid array assemblies fabricated using temporary resist Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.
US09263377B2	POP structures with dams encircling air gaps and methods for forming the same A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.
US09263374B2	Semiconductor device and manufacturing method therefor A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region.
US09263372B2	Anisotropic conductive film and semiconductor device A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a phenoxy resin including a fluorene-substituted phenoxy resin; and a radically polymerizable resin including a fluorene-substituted acrylate.
US09263371B2	Semiconductor device having through-silicon via A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.
US09263369B2	Chip arrangement, wafer arrangement and method of manufacturing the same Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure.
US09263368B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate on which a plurality of contact regions are defined, a plurality of transistors formed in the plurality of contact regions, a support body formed over the plurality of transistors and including a top surface, portions of which have different heights in the plurality of contact regions, a plurality of stacked structures including a plurality of conductive layers stacked over the support body, slits located between the plurality of stacked structures, first lines coupled to first junctions of the plurality of transistors through the slits, and second lines coupled to second junctions of the plurality of transistors through the slits.
US09263367B2	Semiconductor device Provided is a semiconductor device comprising a cooler in which, by improving the shape of the connecting portions of an inlet/outlet of a coolant or the like, the pressure loss in the connecting portion or the like can be reduced.A cooler 20 of a semiconductor device 1 includes: an inlet 27 and an outlet 28 provided on side walls 22b1, 22b2 of a case 22 opposing to each other at diagonal positions; an introduction path 24 which is connected to the inlet 27 and formed in the case 22; a discharge path 25 which is connected to the outlet 28 and formed in the case 22; and a cooling flow channel 26 between the introduction path 24 and the discharge path 25. The height of the opening of the inlet 27 is larger than the height of the introduction path 24, and a connecting portion 271 between the inlet 27 and the introduction path 24 includes an inclined surface 271b which is inclined from the bottom surface of the connecting portion 271 toward the longitudinal direction of the introduction path 24.
US09263365B2	Electronic component and electronic component cooling method An electronic component includes a base substance, a cooling channel formed in the base substance and flows a cooling medium in a second direction from a first direction, a radiator formed in a surface of the cooling channel using a material of which thermal conductivity is higher than a thermal conductivity of the base substance or formed so that the radiator may project to the cooling channel, and that contacts the cooling medium.
US09263360B2	Liquid compression molding encapsulants Thermosetting resin compositions useful for liquid compression molding encapsulation of a silicon wafer are provided. The so-encapsulated silicon wafers offer improved resistance to warpage, compared to unencapsulated wafers or wafers encapsulated with known encapsulation materials.
US09263358B2	Crashworthy memory module having a crack repair system A memory module is disclosed. The memory module may have an insulator. The memory module may also have a device disposed within the insulator. The memory module may further have a filler disposed on the device. The filler may be configured to expand and flow into one or more cracks in the insulator, when the filler is subjected to a threshold temperature.
US09263357B2	Carrier with hollow chamber and support structure therein According to various embodiments, a carrier may include: a hollow chamber spaced apart from a surface of the carrier; and at least one support structure within the hollow chamber connecting a first region of the carrier disposed over the hollow chamber with a second region of the carrier disposed below the hollow chamber, wherein at least a part of a surface of the at least one support structure is spaced apart from an inner surface of the hollow chamber, and wherein the at least one support structure includes an electrically insulating material.
US09263356B2	Semiconductor device A partition in lattice form forms a plurality of housing sections. A plurality of circuit blocks including a semiconductor block and a terminal base block are electrically connected one to another in a state of being housed in the housing sections to form a power semiconductor circuit. The semiconductor block is formed by covering an IGBT with an insulating material. A collector of the IGBT is connected to an electrode through a metal plate. The electrode is led out from an inner portion of the insulating material to a side surface of the insulating material. A terminal base block includes a power terminal to which an external power wiring for supplying electric power to the IGBT is electrically connected, and a screw hole into which a screw for fixing the power wiring is inserted.
US09263355B2	Electronic signal transmitting device and integrated circuit thereof An electronic signal transmitting device is disposed in a housing of an integrated circuit. The integrated circuit includes at least one first signal end and at least one second signal end. The electronic signal transmitting device includes at least one electromagnetic transmitting unit, coupled between the first signal end and the second signal end for transmitting an electronic signal between the first signal end and the second signal end; and an electromagnetic insulating layer covering the electromagnetic transmitting unit for protecting the integrated circuit from electromagnetic interference.
US09263352B2	Singulation apparatus comprising an imaging device Disclosed is a singulation apparatus for cutting a workpiece. The singulation apparatus comprises: i) a processor; ii) at least one chuck device for securing the workpiece to be cut; iii) a cutting device spaced from the at least one chuck device by a separation distance, the cutting device being for cutting the workpiece secured to the at least one chuck device; and iv) an imaging device operable to capture one or more images comprising the cutting device and a reference feature. In particular, the processor is configured to determine a separation distance between the cutting device and the reference feature based on the one or more images as captured by the imaging device, to thereby determine the separation distance between the cutting device and the workpiece as secured to the at least one chuck device.
US09263349B2	Printing minimum width semiconductor features at non-minimum pitch and resulting device Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.
US09263347B2	Method of manufacturing silicon carbide semiconductor device A silicon carbide substrate having a main surface angled off in an off direction relative to a {0001} plane is prepared. A protruding first alignment mark is formed on the main surface of the silicon carbide substrate. A second alignment mark is formed on the first alignment mark by forming a silicon carbide epitaxial layer on the first alignment mark. The first alignment mark includes a first region and a second region, the second region being in contact with the first region and extending from the first region in the off direction. The second alignment mark includes a first portion formed on the first region and a second portion formed on the second region. An alignment step includes the step of capturing an image of the first portion while not including the second portion, and recognizing an edge of the first portion based on the image.
US09263345B2	SOI transistors with improved source/drain structures with enhanced strain A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance.
US09263340B2	Methods for removing selected fins that are formed for finFET semiconductor devices One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate to thereby define a plurality of fins in the substrate, forming a layer of insulating material in the trenches, performing an etching process sequence to remove at least a portion of one of the plurality of fins and thereby define a fin cavity, wherein the etching process sequence includes performing a first anisotropic etching process and, after performing the first anisotropic etching process, performing a second isotropic etching process. In this embodiment, the method concludes with the step of forming additional insulating material in the fin cavity.
US09263339B2	Selective etching in the formation of epitaxy regions in MOS devices A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region.
US09263337B2	Semiconductor device and method of manufacture A system and method for etching a substrate is provided. An embodiment comprises utilizing an inert carrier gas in order to introduce a liquid etchant to a substrate. The inert carrier gas may prevent undesirable chemical reactions from taking place during the etching process, thereby helping to reduce the number of defects that occur to the substrate and other structures during the etching process.
US09263335B2	Discrete semiconductor device package and manufacturing method Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.
US09263330B2	Semiconductor device, method for forming contact and method for etching continuous recess A method for forming a contact is provided. The method includes: forming a first dielectric layer over a substrate; forming a second dielectric layer over the first dielectric layer; patterning the second dielectric layer to form a first recess; patterning the first dielectric layer by a first etchant through the first recess to form a second recess, wherein the first etchant has a higher etching rate with respect to the first dielectric layer than with respect to the second dielectric layer and further wherein the second recess is aligned with the first recess; and forming a continuous contact plug in the first recess and the second recess.
US09263326B2	Interconnection structure and method of forming the same After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.
US09263323B2	Semiconductor device having parallel conductive lines including a cut portion and method of manufacturing the same A semiconductor device includes a plurality of parallel conductive lines that are spaced apart from one another in a first direction and extend in a second direction transverse to the first direction. The parallel conductive lines includes first and second lines that are adjacent, and a third line that is adjacent to the second line, and the first and third lines each have a cut portion at different points along the second direction.
US09263316B2	Method for forming a semiconductor device with void-free shallow trench isolation A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is formed in the semiconductor substrate, and includes an isolation oxide and a spin coating material. The isolation oxide is peripherally enclosed by the semiconductor substrate. The spin coating material is peripherally enclosed by the isolation oxide.
US09263315B2	LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate An LED leadframe or LED substrate includes a main body portion having a mounting surface for mounting an LED element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the LED element is disposed over the mounting surface of the main body portion. The reflection metal layer comprises an alloy of platinum and silver or an alloy of gold and silver. The reflection metal layer efficiently reflects light emitted from the LED element and suppresses corrosion due to the presence of a gas, thereby capable of maintaining reflection characteristics of light from the LED element.
US09263312B2	Joining device and joining position adjustment method using joining device A joining device includes a first holding unit configured to load and hold the first member on its top surface; a second holding unit disposed above the first holding unit while facing the first holding unit and configured to hold the second member; and a position adjustment mechanism configured to adjust a joining position between the first member held by the first holding unit and the second member held by the second holding unit. The second holding unit is of a circular plate shape, and the position adjustment mechanism includes four position-adjusting cam members disposed at equal intervals along an outer peripheral surface of the second holding unit, and moves the second holding unit in a horizontal direction.
US09263309B2	Method and apparatus for an automated tool handling system for a multilevel cleanspace fabricator The present invention provides methods and apparatus capable of routine placement and replacement of fabricator tools in a designated tool location. The tool location can be selected from multiple tool locations arranged in a matrix with horizontal and vertical designations. The operation may be fully automated. In another aspect, the invention describes Cleanspace fabricators which use devices to routinely remove and place tooling.
US09263308B2	Water soluble mask for substrate dicing by laser and plasma etch Methods of dicing substrates having a plurality of ICs are disclosed. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer is washed off.
US09263307B2	Apparatus and method for treating substrate Provided are an apparatus and method for treating a substrate, and more particularly, to a substrate treatment apparatus having a cluster structure and a substrate treatment method using the same. The apparatus for treating the substrate includes a load port on which a container for receiving the substrate is placed, a treatment module for treating the substrate, and a transfer module including a robot for transferring the substrate between the container and the treatment module. The treatment module includes a transfer chamber including a robot for transferring the substrate, a load lock chamber disposed between the transfer chamber and the transfer module, a first treatment chamber disposed spaced from the transfer module around the transfer chamber to perform a first treatment process, and a second treatment chamber disposed around the transfer chamber to perform a second treatment process.
US09263305B2	High definition heater and method of operation An apparatus is provided, by way of example, a heater for use in semiconductor processing equipment that includes a base functional layer having at least one functional zone. A substrate is secured to the base functional layer, and a tuning layer is secured to the substrate opposite the base functional layer. The tuning layer includes a plurality of zones that is greater in number than the zones of the base functional layer, and the tuning layer has lower power than the base functional layer. Further, a component, such as a chuck by way of example, is secured to the tuning layer opposite the substrate. The substrate defines a thermal conductivity to dissipate a requisite amount of power from the base functional layer.
US09263302B2	Via structure for packaging and a method of forming A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
US09263299B2	Exposed die clip bond power package In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.
US09263298B2	Plasma etching apparatus and plasma etching method A plasma etching apparatus 11 includes a mounting table that holds a semiconductor substrate W thereon; a first heater 18a that heats a central region of the semiconductor substrate W held on the mounting table 14; a second heater 18b that heats an edge region around the central region of the semiconductor substrate W held on the mounting table 14; a reactant gas supply unit 13 that supplies a reactant gas for a plasma process toward the central region of the semiconductor substrate W held on the mounting table 14; and a control unit 20 that performs a plasma etching process on the semiconductor substrate W while controlling the first heater 18a and the second heater 18b to heat the central region and the edge region of the processing target substrate W held on the mounting table 14 to different temperatures.
US09263294B2	Method of forming semiconductor device A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.
US09263293B2	Flash memory structure and method for forming the same Embodiments of mechanisms of a semiconductor structure are provided. The semiconductor device structure includes a substrate and a floating gate having a first sidewall and a second sidewall formed over the substrate. The semiconductor device further includes an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate. The semiconductor device further includes a control gate formed over the insulating layer. In addition, the floating gate is formed in a shark's fin shape.
US09263291B2	Method of manufacturing semiconductor device To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
US09263288B2	Etching method using block-copolymers A method for lithography is disclosed. The method includes obtaining a self-organizing block-copolymer layer on a neutral layer overlying a substrate, the self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, the self-organizing block-copolymer layer furthermore comprising a copolymer pattern structure formed by micro-phase separation of the at least two polymer components. Further, the method includes etching selectively a first polymer component of the self-organizing block-copolymer layer, thereby remaining a second polymer component. Still further, the method includes applying a plasma etching to the neutral layer using the second polymer component as a mask, wherein the plasma etching comprises an inert gas and H2.
US09263283B2	Etching method and apparatus An etching method and apparatus for etching a silicon oxide film selectively with respect to a silicon nitride film formed on a substrate are provided. A processing gas containing a plasma excitation gas and a CHF-based gas is introduced into a processing chamber such that a flow rate ratio of the CHF-based gas to the plasma excitation gas is 1/15 or higher. By generating a plasma in the processing chamber, the silicon oxide film is etched selectively with respect to the silicon nitride film formed on the substrate in the processing chamber.
US09263280B2	Semiconductor device with equipotential ring contact at curved portion of equipotential ring electrode and method of manufacturing the same A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.
US09263275B2	Interface for metal gate integration A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide.
US09263264B2	Oxide removal from semiconductor surfaces using a flux of indium atoms A method of removing at least one oxide from a surface of a body of semiconductor material is disclosed. The method includes arranging the body in a vacuum chamber and maintaining a temperature of the body in the vacuum chamber within a predetermined range, or substantially at a predetermined value, while exposing said surface to a flux of indium atoms. Corresponding methods of processing an oxidized surface of a body of semiconductor material to prepare the surface for epitaxial growth of at least one epitaxial layer or film over said surface, and methods of manufacturing a semiconductor device are also disclosed.
US09263263B2	Method for selective growth of highly doped group IV—Sn semiconductor materials Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.
US09263262B2	Nanowires made of novel precursors and method for the production thereof The invention relates to nanowires which consist of or comprise semiconductor materials and are used for applications in photovoltaics and electronics and to a method for the production thereof. The nanowires are characterized in that they are obtained by a novel method using novel precursors. The precursors represent compounds, or mixtures of compounds, each having at least one direct Si—Si and/or Ge—Si and/or Ge—Ge bond, the substituents of which consist of halogen and/or hydrogen, and in the composition of which the atomic ratio of substituent:metalloid atoms is at least 1:1.
US09263257B2	Semiconductor device having fin-shaped structure and method for fabricating the same A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.
US09263254B2	Method for making epitaxial structure The disclosure relates to a method of making epitaxial structure. The method includes following steps: providing a free-standing carbon nanotube film, wherein the carbon nanotube film includes a number of carbon nanotubes aligned and connected with each other via van der Waals force; suspending the carbon nanotube film and inducing defects on the surface of the carbon nanotubes; growing a nano-material layer on the surface of the carbon nanotubes via atomic layer deposition; removing the carbon nanotube film by annealing to form a number of nanotubes; wherein the number of nanotubes are successively aligned and connected with each other to form a free-standing nanotube film; setting the nanotube film on an epitaxial growth surface of a substrate; and growing an epitaxial layer on the epitaxial growth surface.
US09263252B2	Method of protecting an interlayer dielectric layer and structure formed thereby This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.
US09263251B2	Method of manufacturing semiconductor device, semiconductor device and substrate processing apparatus An oxide film capable of suppressing reflection of a lens is formed under a low temperature. A method of manufacturing a semiconductor device includes forming a metal-containing oxide film on a substrate by performing a cycle a predetermined number of times, the cycle comprising: (a) supplying a metal-containing source to the substrate; (b) supplying an oxidizing source to the substrate; and (c) supplying a catalyst to the substrate.
US09263242B2	Imaging mass spectrometry method and device A method of performing imaging mass spectrometry of a sample. The method comprises performing a first mass analysis of the sample using a first mass analyzer comprising a multi-pixel ion detector to obtain first mass spectral data representative of pixels of the sample. The method further comprises identifying clusters of pixels sharing one or more characteristics of first mass spectral data. The method also comprises performing a second mass analysis of the sample using a second mass analyzer to obtain second mass spectral data at at least one location in each cluster, wherein the number of locations is significantly less than the number of pixels in each cluster, said second mass analysis being of higher resolution than said first mass analysis. Also a mass spectrometry apparatus configured for carrying out the method.
US09263239B1	Etching method of multilayered film Verticality of a space formed in the multilayered film can be improved while suppressing an opening of a mask from being clogged. The multilayered film includes a first film and a second film that have different permittivities and are alternately stacked on top of each other. An etching method of etching the multilayered film includes preparing, within a processing vessel of a plasma processing apparatus, a processing target object having the multilayered film and a mask provided on the multilayered film; and etching the multilayered film by exciting a processing gas containing a hydrogen gas, a hydrofluorocarbon gas, a fluorine-containing gas, a hydrocarbon gas, a boron trichloride gas and a nitrogen gas within the processing vessel.
US09263233B2	Charged particle multi-beam inspection system and method of operating the same A charged particle multi-beam inspection system comprises a beam generator directing a plurality of primary charged particle beams onto an object to produce an array of beam spots; an array of a first number of detection elements generating detection signals upon incidence of electrons; imaging optics imaging the array of beam spots onto the array of detection elements; wherein the beam generator includes a multi-aperture plate having an array of a second number of apertures greater than the first number; wherein the beam generator includes a selector having plural different states, wherein, in each of the plural different states, the apertures of a different group of apertures are each traversed by one primary charged particle beam, wherein a number of the apertures of the different group of apertures is equal to the first number.
US09263232B2	Charged particle beam device A charged particle beam device (1) includes a charged particle optical lens barrel (10), a support housing (20) equipped with the charged particle optical lens barrel (10) thereon, and an insertion housing (30) inserted in the support housing (20). A first aperture member (15) is disposed in the vicinity of the center of the magnetic field of an objective lens, and a second aperture member (15) is disposed so as to externally close an opening part provided at the upper side of the insertion housing (30). Further, when a primary charged particle beam (12) is irradiated to a sample (60) arranged under the lower side of the second aperture member (31), secondary charged particles thus emitted are detected by a detector (16).
US09263230B2	Method for transmitting a broadband ion beam and ion implanter A method for transmitting a broadband ion beam (100) and an ion implanter adopt an analyzing magnetic field (1), a calibration magnetic field (2) and an analyzing grating (6) to transmit a broadband ion beam. If the analyzing magnetic field (1) enables the broadband ion beam (100) emitted into the analyzing magnetic field from an incident face (101) thereof to be deflected anticlockwise in a horizontal direction, the calibration magnetic field (2) enables an ion beam diffusing again after passing through the analyzing grating (6) to be deflected clockwise in the horizontal direction; if the analyzing magnetic field (1) enables the broadband ion beam (100) emitted into the analyzing magnetic field from the incident face (101) thereof to be deflected clockwise in the horizontal direction, the calibration magnetic field (2) enables an ion beam diffusing again after passing through the analyzing grating (6) to be deflected anticlockwise in the horizontal direction. The analyzing magnetic field (1) and the calibration magnetic field (2) enable the ion beam to be deflected along different directions in the horizontal direction, so that distribution of the required ions in the broadband ion beam (100) when emitted out of the calibration magnetic field (2) from an emergence face (202) thereof is the same as the distribution when being emitted into the analyzing magnetic field.
US09263229B2	Device and method for electron emission and device including such an electron emission system A device and method for emitting electrons by a field effect. The device (10) includes a vacuum chamber (12) including a tip (14) having an end (18) and forming a cold cathode, an extracting anode (16), components adapted for generating a potential difference between the tip (14) and the anode (16); an electromagnetic wave source (22) outside the chamber (12); a system (24) for forwarding the electromagnetic wave emitted by the electromagnetic wave source from the outside to the inside of the chamber as far as the vicinity of the tip (14); a system (26) for focusing the electromagnetic wave, laid out inside the chamber (12); and a system (28) for aligning the electromagnetic wave outside the chamber and adapted for allowing alignment of the electromagnetic wave focused by the focusing system on the end of the tip.
US09263225B2	X-ray tube anode comprising a coolant tube An anode for an X-ray tube includes at least one thermally conductive anode segment in contact with a rigid support member and cooling means arranged to cool the anode. The anode may further include a plurality of anode segments aligned end to end, each in contact with the support member.
US09263218B2	Variable resistance memory cell based electrically resettable fuse device An integrated circuit includes an electrically resettable fuse device. The electrically resettable fuse device has a plurality of resettable fuse modules coupled in parallel. Each resettable fuse module including a fuse element characterized by a first and a second impedance states. The plurality of resettable fuse modules are configured such that when the fuse element is in the first impedance state, and a current flowing through each fuse element in a first direction exceeds a current limit, the fuse element enters into the second impedance state. When the fuse element is in the second impedance state and, in response to a global reset signal and a local reset signal, a current is applied to the fuse element in a second direction opposite the first direction, the fuse element is reset to the first impedance state.
US09263216B2	Circuit breaker with arc shield A circuit breaker which includes a shielding component. The shielding component includes an external portion which defines a space external to the circuit breaker housing. The external portion prevents insertion of the circuit breaker into a breaker box closer than the distances defining the space. This can have the advantage of preventing arcing from the breaker contacts to the breaker box. The external portion may also prevent insertion of the circuit breaker into a breaker box such that a vent in the circuit breaker housing is blocked. In some implementations, the shielding component contains an internal portion which extends into the circuit breaker housing and is disposed to impede debris generated by contact arcing, or other debris, from entering the mechanism of the circuit breaker.
US09263215B2	Tool and method for switching an electromagnetic relay A tool and method for switching an electromagnetic relay may be provided, whereby the tool comprises a switching member capable of moving between a first position and a second position along a path oriented to the relay; wherein movement of the switching member from the first position to the second position is capable of switching a switch state of the electromagnetic relay via a magnetic force exerted by the switching member.
US09263213B2	Power switching control device and closing control method thereof A power switching control device and a closing control method thereof that can suppress generation of a transient voltage or current that is possibly caused by a variation in a load-side voltage after interrupting a current are obtained. A circuit-breaker-gap-voltage estimate value at and after a present time is calculated based on a power-supply-side voltage estimate value and a load-side voltage estimate value at and after the present time, a target closing-time domain from a closing controllable time to a closing control limit time in which a circuit breaker can be closed at a timing when an absolute value of the circuit-breaker-gap-voltage estimate value falls within a preset allowable range is calculated based on this circuit-breaker-gap-voltage estimate value, and the closing controllable time is delayed by a preset delay time in a case of a subsequent closing phase of a second or later closing phase.
US09263209B2	Backlighting assembly for a keypad A backlighting assembly for use in a keypad assembly. The backlighting assembly includes at least one light emitting source configured to emit light; and a light guide assembly configured to receive the emitted light and direct the light toward the at least one key. The light guide assembly includes both a light guide film and a substantially rigid frame to guide light and to provide structural support.
US09263197B2	Electrolyte synthesis for ultracapacitors A method of forming an electrolyte solution involves combining ammonium tetrafluoroborate and a quaternary ammonium halide in a liquid solvent to form a quaternary ammonium tetrafluoroborate and an ammonium halide. The ammonium halide precipitate is removed from the solvent to form an electrolyte solution. The reactants can be added step-wise to the solvent, and the method can include using a stoichiometric excess of the ammonium tetrafluoroborate to form a substantially halide ion-free electrolyte solution. Filtration can be done at low temperatures to reduce the amount of excess bromide in the resulting electrolyte.
US09263195B2	Three-dimensional network aluminum porous body, electrode using the aluminum porous body, and nonaqueous electrolyte battery, capacitor and lithium-ion capacitor with nonaqueous electrolytic solution, each using the electrode A three-dimensional network aluminum porous body which enables to produce an electrode continuously, an electrode using the aluminum porous body, and a method for producing the electrode. A long sheet-shaped three-dimensional network aluminum porous body is provided to be used as a base material in a method for producing an electrode including at least winding off, a thickness adjustment step, a lead welding step, an active material filling step, a drying step, a compressing step, a cutting step and winding-up, wherein the three-dimensional network aluminum porous body has a tensile strength of 0.2 MPa or more and 5 MPa or less.
US09263192B2	Method for forming electret containing positive ions A method for forming an electret containing positive ions, includes: a first step of contacting water vapor including positive ions to a Si substrate to which heat is being applied, and forming an oxide layer including those ions; a second step of, along with applying an electric field that makes the side of the oxide layer that does not contact the Si substrate be the negative side, and that makes its other side be a positive side, applying heat to the Si substrate in a hydrogen atmosphere, and causing the ions in the oxide layer to shift; and a third step of contacting water vapor including a chemical substance, in an atmosphere of an inactive gas, for forming a hydrophobic chemically adsorbed monomolecular layer, and thus forming a hydrophobic membrane upon the oxide layer; wherein the second step and the third step are performed continuously within one common vessel.
US09263191B2	Electronic component An electronic component comprises an element body, an external electrode, and an insulating resin coating layer. The element body has a pair of end faces opposed to each other, a pair of principal faces extending so as to connect the pair of end faces and opposed to each other, and a pair of side faces extending so as to connect the pair of principal faces and opposed to each other. The external electrode is formed so as to cover at least a partial region of the principal face and/or a partial region of the side face and has a plating layer comprised of Sn or an Sn alloy. The insulating resin coating layer covers at least the portion of the external electrode formed so as to cover the side face.
US09263190B2	Multilayer ceramic capacitor having high moisture resistance In a multilayer ceramic capacitor, an inner ceramic layer includes a perovskite-type compound containing Ba and Ti. A region within an electrically effective portion of the inner ceramic layers sandwiched between inner electrodes, which is near an area where inner and outer electrodes connect to each other, is subjected to a mapping analysis using EDS. ((L2−L3)/L1)×100≧50 is satisfied, L1 denotes a total length of ceramic grain boundaries detected from a TEM transmission image, L2 denotes a total length of grain boundaries, detected from a mapping image and the TEM transmission image, where the rare earth element is present, and L3 denotes a total length of portions, detected from a mapping image and the TEM transmission image, in which the grain boundaries where the rare earth element is present and grain boundaries where at least one of Mn, Mg, and Si is present are overlapped.
US09263189B2	Magnetic capacitor An apparatus for storing electrical energy comprising at least: a first multilayer section; a second multilayer section disposed above the first multilayer section; and a spacer layer disposed between the first and second multilayer sections and comprising a dielectric material, wherein each of the first and second multilayer sections comprising a pinned magnetic layer having a fixed magnetization direction, a free magnetic layer having a reversible magnetization direction, and an isolative layer disposed between the pinned and free magnetic layers, the pinned and free magnetic layers are substantially anti-ferromagnetically exchange coupled to each other through the isolative layer; and wherein the pinned magnetic layers of the first and second multilayer sections are electrically coupled in parallel with each other, and the free magnetic layers of the first and second multilayer sections are electrically coupled in parallel with each other.
US09263188B2	Conductive resin composition and chip-type electronic component A conductive resin composition which allows a resin electrode which is favorable in terms of shape and adhesion to a ceramic device to be formed reliably, and a chip-type electronic component including resin electrodes formed with the conductive resin component are described. The conductive resin composition contains a linear bifunctional epoxy resin having a molecular weight of 11000 to 40000 and a terminal glycidyl group, a conductive silver powder, and a solvent, and has a yield value of 3.6 Pa or less. In addition, the conductive powder can have a surface attached to a fatty acid or a salt thereof, and the ratio of the fatty acid or salt thereof to the conductive powder is 0.5 wt % or less. Furthermore, the conductive powder can be spherical, and the ratio of the conductive powder in solids constituting the conductive resin composition can be 42 to 54 vol %.
US09263177B1	Pin inductors and associated systems and methods A magnetic device includes a magnetic core and N windings wound at least partially around respective portions of the magnetic core. Each of the N windings has opposing first and second ends. Each first end forms a first connector, and each second end forms a second connector. Each first connector is adapted for coupling to a first substrate in a first plane, and each second connector is adapted for coupling to a second substrate in a second plane, where the second plane is different from the first plane. N is an integer greater than zero. An electrical assembly includes a substrate and a power supply module including a magnetic device. The magnetic device at least partially electrically couples the power supply module to the substrate.
US09263171B2	Conductive masterbatches and conductive monofilaments The present invention relates to a polyester matrix powder comprising a polybutylene terephthalate, a homogeneously dispersed carbon nanotube powder, a dispersant and a chain extender; to a conductive masterbatch with homogeneous and smooth surface; to a process for the preparation of the conductive masterbatch; to a conductive monofilament prepared from the conductive masterbatch; to a process for the preparation of the conductive monofilament; and to a fabric article prepared from the monofilament. The present invention is characterized in the preparation of carbon nanotube-containing fiber materials with higher conductivity and the improvement of the spinning property of the conductive masterbatches to avoid blocking and yarn breakage during the spinning process.
US09263169B2	Aluminum paste and solar cell An aluminum paste and a solar cell, the aluminum paste including aluminum powder; an organic vehicle; and antimony oxide, the antimony oxide being present in an amount of about 0.001 wt % to less than about 1.0 wt %, based on a total weight of the aluminum paste.
US09263168B2	Aluminum alloy wire rod, aluminum alloy stranded wire, coated wire, wire harness and manufacturing method of aluminum alloy wire rod An aluminum alloy wire rod has a composition consisting of 0.10-1.00 mass % Mg; 0.10-1.00 mass % Si; 0.01-1.40 mass % Fe; 0.000-0.100 mass % Ti; 0.000-0.030 mass % B; 0.00-1.00 mass % Cu; 0.00-0.50 mass % Ag; 0.00-0.50 mass % Au; 0.00-1.00 mass % Mn; 0.00-1.00 mass % Cr; 0.00-0.50 mass % Zr; 0.00-0.50 mass % Hf; 0.00-0.50 mass % V; 0.00-0.50 mass % Sc; 0.00-0.50 mass % Co; 0.00-0.50 mass % Ni; and the balance being Al and incidental impurities, wherein at least one of Ti, B, Cu, Ag, Au, Mn, Cr, Zr, Hf, V, Sc, Co and Ni is contained in the composition or none of Ti, B, Cu, Ag, Au, Mn, Cr, Zr, Hf, V, Sc, Co and Ni is contained in the composition. A precipitate free zone exists inside a crystal grain, and the precipitate free zone has a width of less than or equal to 100 nm.
US09263160B2	Collimator module, radiation detector having collimator module, radiological imaging apparatus having collimator module, and control method of radiological imaging apparatus A collimator module which may be disposed in a radiation detector of a radiological imaging apparatus using the collimator module may include a first collimator having a plurality of openings, through which radiation having passed through an object passes, and a second collimator located below the first collimator and having a plurality of openings, through which radiation having passed through the first collimator passes. The first collimator or the second collimator is designed so as to be movable or rotatable relative to the second collimator or the first collimator. Through movement of the first collimator or the second collimator, the size of a passage region that allows radiation having passed through the object to pass through the first collimator or the second collimator is adjustable.
US09263157B2	Detecting defective connections in stacked memory devices A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
US09263156B2	System and method for adjusting trip points within a storage device The embodiments described herein include a method and device for adjusting trip points within a storage device. The method includes: obtaining one or more configuration parameters; and based on the one or more configuration parameters, determining a trip voltage. The method also includes comparing the trip voltage with an input voltage. The method further includes triggering a power fail condition in accordance with a determination that the input voltage is less than the trip voltage.
US09263154B2	Method and device for evaluating a chip manufacturing process A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.
US09263151B2	Memory interface with selectable evaluation modes A memory interface enables AC characterization under test conditions without requiring the use of Automated Test Equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).
US09263148B2	Semiconductor device with pass/fail circuit A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit suitable for performing a program operation and a verify operation on memory cells coupled to a selected word line, wherein, when performing the program operation, the operation circuit applies a first program allowance voltage to a bit line of a first program fail cell to keep a program fall status, and a second program allowance voltage having a voltage level different from the first program allowance voltage to a bit line of a second program fail cell to change a program pass status to a program fail status.
US09263147B2	Method and apparatus for concurrent test of flash memory cores An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.
US09263144B2	Semiconductor memory device According to one embodiment, a semiconductor memory device includes a first sub-array including a plurality of first memory cells; a second sub-array including a plurality of second memory cells; a first bit line electrically connected to a first group of the first memory cells; a second bit line electrically connected to a first group of the second memory cells; a bit line connection unit configured to connect the first bit line and the second bit line; a first sense amplifier configured to receive a first voltage from either of the first bit line and the second bit line in a read operation, and transfer a second voltage either of the first bit line and the second bit line in a write operation; a first source line electrically connected to the first memory cells; a second source line electrically connected to the second memory cells; and a source line driver configured to apply voltages to the first source line and the second source line.
US09263143B2	Three dimensional memory device and data erase method thereof A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.
US09263141B2	Methods for erasing, reading and programming flash memories The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of −7V˜−10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC−6.5V˜VCC−4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V. In full consideration of factors including the chip manufacturing process, chip circuit design, chip quality and cost, optimal operating conditions fit for erasing, reading and programming, a NOR-type embedded 2T PMOS flash memory are determined.
US09263139B2	Method and system for improving the radiation tolerance of floating gate memories A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.
US09263133B2	Techniques for providing a semiconductor memory device Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.
US09263132B2	Double gated flash memory A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.
US09263131B2	High-speed readable semiconductor storage device According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.
US09263130B2	Memory device page buffer configuration and methods Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.
US09263128B2	Methods and apparatuses for programming memory cells Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming time being a time when a most recent programming operation was applied to a reference memory cell in the memory array. A programming signal is then applied to a target memory cell in the memory array, the programming signal having a programming parameter which depends at least in part on the most recent programming time.
US09263125B2	Nonvolatile memory apparatus, and semiconductor system and computer device using the same A nonvolatile memory apparatus includes a memory cell array including a plurality of sub arrays. A plurality of analog-to-digital converters (ADCs) configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays and a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply voltage in a second operation mode.
US09263123B2	Memory device and a method of operating the same A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level.
US09263113B2	Semiconductor memory device with memory array and dummy memory array A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.
US09263112B2	Semiconductor integrated circuit A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set.
US09263105B2	Memory systems including an input/output buffer circuit Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.
US09263104B2	Semiconductor device Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal data strobe signals in response to the data strobe signal; and a serial-to-parallel conversion circuit configured to respond to the data strobe and internal data strobe signals to convert the serial write data signal into a parallel write data signal that includes at least four bits produced in parallel to each other.
US09263096B1	Voltage comparator circuit and usage thereof A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.
US09263095B2	Memory having buried digit lines and methods of making the same A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
US09263093B2	Drive carrier light source control A drive carrier includes a first computing device with light source control capacity and a light source proximate to a front plate of the drive carrier. The first computing device receives a signal from a second computing device (external to the drive carrier) and controls the light source proximate to the front plate of the drive carrier based on the signal.
US09263091B2	Systems and methods for video playback control Methods and apparatus are provided for a video playback control system for a vehicle having a front cabin and a rear cabin. The apparatus can include at least one first display located in the front cabin, and at least one second display located in the rear cabin. The apparatus can also include a source of video data for display on the at least one first display and the at least one second display. The apparatus can include a control module that outputs a single still video frame or series of still video frames from a continuous video stream provided by the source of video data for display on the at least one first display.
US09263090B2	Image processing apparatus, image processing method, and program An image processing apparatus for editing moving image data of successive frames to which a time code of a same value is made to correspond every first predetermined number of frames, the moving image data being coded on a unit basis of a coding unit which includes a second predetermined number of frames, obtains information regarding the coding unit from management information of the moving image data, determines a candidate of an editing point of the moving image data based on the obtained information and the time code made to correspond to the frames of the moving image data, sets the editing point of the moving image data based on a designated editing point and the determined candidate, and edits the moving image data according to the set editing point.
US09263089B2	Editing apparatus, editing method, and editing program Herein disclosed are an editing apparatus, an editing method, and an editing program allowing quick editing of video data. In order to clip a section in the video data and play it to be broadcasted as a replay, receiving a request to start playback from a desired position, an in-point is set in response to the request, and an out-point is set in response to a request to finish playback. Then, other video data from the video data of a section between the in-point and the out-point is generated.
US09263087B2	Quasi-statically tilted head having dilated transducer pitch A method according to one embodiment includes reading and/or writing data to a magnetic medium using a head having an array of transducers. An axis of the array is defined between opposite ends thereof, and is tilted at an angle greater than 0° from a line oriented perpendicular to an intended direction of tape travel thereacross during the reading and/or writing. The method further includes at least one of: introducing, by a controller, a timing offset to at least one servo channel to compensate for offset in servo readback signals introduced by the tilt of the head, introducing, by the controller, a timing offset to at least some read channels to compensate for offset in readback signals introduced by a tilt of the head, and introducing, by the controller, a timing offset to at least some write channels to enable writing of transitions that are readable by a non-tilted head.
US09263085B2	Method for copy protection A method for copy protection in which an audiovisual or audio data is divided into a plurality of portions. The plurality of portions is at least partly scrambled and prepared so as to be stored on a record carrier in the scrambled order. This is done so that a physical position on the record carrier, e.g., a sector of the record carrier, where a respective portions of the divided data is stored depends on the scrambled order.
US09263082B2	High density hybrid storage system A system includes a linear storage media tier; a second storage tier having higher performance than the linear storage media tier; a data controller for moving data between the tiers; and a host interface responsive to disk and/or network storage commands. The linear storage media tier includes: a rest area for storing reels having linear media thereon, at least one linear media drive configured for reading and/or writing the linear media, and at least one robot for transporting the linear storage media between the rest area and the at least one linear media drive. The robot moves along a first surface via contact with the surface. A system according to another embodiment includes a linear storage media tier characterized by having a read access time to any block of data stored on any reel in the rest area in less than 10 seconds.
US09263081B2	Optical pickup device An optical pickup device is one in which a lens holder is held by a movable base by using a resilient wire. A restricting abutting portion is formed at a lower portion of the lens holder. When the lens holder moves excessively downward, the restricting abutting portion comes into contact with a stopper portion to restrict a downward movement of the lens holder, so that it is possible to prevent the lens holder from contacting a unit chassis. When the unit chassis is not mounted on the movable base, it is possible to prevent excessive flexing of the resilient wire caused when an opposing abutting portion of the lens holder comes into contact with the unit chassis.
US09263079B2	Method for producing and device for producing magnetic recording medium The present invention provides a device and a method for producing a magnetic recording medium having a lubricant membrane with a uniform thickness on a surface. The device for producing the magnetic recording medium includes: a hanger device that is inserted into the central hole of the magnetic recording medium and supports the magnetic recording medium in a hanging state; and a raising and lowering device that raises and lowers one of the hanging device and an immersion tank with respect to the other thereof. The hanger device includes a support plate of which an upper end comes into contact with an inner circumference of the magnetic recording medium and a liquid-cutting plate which extends from a lower end of the support plate and is distant by a space along the inner circumference of the magnetic recording medium from the inner circumference of the magnetic recording medium.
US09263075B2	Magnetic recording medium for heat-assisted recording device and manufacturing method thereof Disclosed are a magnetic recording medium for a heat-assisted recording device, which has a high SNR at high density, and a manufacturing method thereof. The magnetic recording medium includes a non-magnetic substrate; a magnetic recording layer; a protective layer; and a liquid lubricating layer. The magnetic recording layer has a granular structure formed by magnetic portions and non-magnetic portions that surround the magnetic portions in which the non-magnetic portions between adjacent magnetic portions are recessed with respect to the magnetic portions. The non-magnetic portions have a volume percentage based on total volume of the granular structure ranging from 15 vol % to 30 vol % and include a carbon-based material. The magnetic recording medium has a surface having an arithmetic mean roughness Ra and an average length of roughness curve elements RSm such that Ra/RSm ranges from 0.05 to 0.15.
US09263070B1	Actuator pivot assembly including a bonding adhesive barrier configured to reduce contamination One aspect of an actuator assembly configured for use in a disk drive includes an actuator body including a bore, an adhesive inlet port, and an adhesive vent, a pivot bearing disposed at least partially within the bore of the actuator body, an adhesive disposed between the pivot bearing and the actuator body, and a barrier coupled to the actuator body and positioned over the adhesive vent.
US09263069B2	Spectral noise analysis for read head structures A testing device tests a magnetic head with a read head structure including a read head element while applying an external magnetic field to the magnetic head. The testing device receives signals from the read head element and processes the signals to generate a spectral power density for the signals. The spectral power density is characterized for at least one frequency range. The characterization of the spectral power density is used to determine a characteristic of noise from the read head structure. The signals from the read head may be received with different applied magnetic fields and/or before or while thermally exciting the magnetic head. Additionally, a histogram of the signals may be generated and used to determine a second characteristic of the noise.
US09263068B1	Magnetic read head having a CPP MR sensor electrically isolated from a top shield An apparatus having a transducer structure with: a lower shield; an upper shield above the lower shield, the shields providing magnetic shielding; a current-perpendicular-to-plane sensor between the upper and lower shields; at least one of an upper electrical lead between the sensor and the upper shield and a lower electrical lead between the sensor and the lower shield, the at least one lead being in electrical communication with the sensor; and an insulating layer between the at least one of the leads and the shield closest thereto. Another embodiment includes a transducer structure having: a lower shield; an upper shield above the lower shield; a current-perpendicular-to-plane sensor between the upper and lower shields; an upper electrical lead between the sensor and the upper shield, the upper electrical lead being in electrical communication with the sensor; and an insulating layer between at upper electrical lead and the upper shield.
US09263065B2	Variable stopwrite threshold with variable smoothing factor In one embodiment, a method includes determining a stopwrite threshold based on a standard deviation or a variance at a current position error signal sample, and determining whether the current position error signal sample exceeds the stopwrite threshold. Writing is disabled in response to determining that the current position error signal sample exceeds the stopwrite threshold. Writing is enabled in response to determining that the current position error signal sample does not exceed the stopwrite threshold.
US09263059B2	Deep tagging background noises In a method for deep tagging a recording, a computer records audio comprising speech from one or more people. The computer detects a non-speech sound within the audio. The computer determines that the non-speech sound corresponds to a type of sound, and in response, associates a descriptive term with a time of occurrence of the non-speech sound within the recorded audio to form a searchable tag. The computer stores the searchable tag as metadata of the recorded audio.
US09263055B2	Systems and methods for three-dimensional audio CAPTCHA Systems and methods for generating and performing a three-dimensional audio CAPTCHA are provided. One exemplary system can include a decoy signal database storing a plurality of decoy signals. The system also can include a three-dimensional audio simulation engine for simulating the sounding of a target signal and at least one decoy signal in an acoustic environment and outputting a stereophonic audio signal based on the simulation. One exemplary method includes providing an audio prompt to a resource requesting entity. The audio prompt can have been generated based on a three-dimensional audio simulation of the sounding of a target signal containing an authentication key and at least one decoy signal in an acoustic environment. The method can include receiving a response to the audio prompt from the resource requesting entity and comparing the response to the authentication key.
US09263053B2	Method and apparatus for generating a candidate code-vector to code an informational signal A method (1100) and apparatus (100) generate a candidate code-vector to code an information signal. The method can include producing (1110) a weighted target vector from an input signal. The method can include processing (1120) the weighted target vector through an inverse weighting function to create a residual domain target vector. The method can include performing (1130) a first search process on the residual domain target vector to obtain an initial fixed codebook code-vector. The method can include performing (1140) a second search process over a subset of possible codebook code-vectors for a low weighted-domain error to produce a final fixed codebook code-vector. The subset of possible codebook code-vectors can be based on the initial fixed codebook code-vector. The method can include generating (1150) a codeword representative of the final fixed codebook code-vector. The codeword can be for use by a decoder to generate an approximation of the input signal.
US09263051B2	Speech coding by quantizing with random-noise signal A method, system and program for decoding a speech signal. In some embodiments, the method comprises: receiving an encoded speech signal having quantization values; transforming the quantization values by adding simulated random-noise samples; and from the encoded speech signal, determining a parameter of the transformation that is usable to control the transformation of the quantization values.
US09263047B2	Apparatus and method for providing messages in a social network A system that incorporates teachings of the present disclosure may include, for example, a server including a controller to receive audio signals and content identification information from a media processor, generate text representing a voice message based on the audio signals, determine an identity of media content based on the content identification information, generate an enhanced message having text and additional content where the additional content is obtained by the controller based on the identity of the media content, and transmit the enhanced message to the media processor for presentation on the display device, where the enhanced message is accessible by one or more communication devices that are associated with a social network and remote from the media processor. Other embodiments are disclosed.
US09263043B2	Stuttering inhibition method and device A method and device is disclosed for reducing and controlling stuttering. The method involves tactile feedback of the stutterer's own speech to reducing stuttering. In one embodiment, the device may detect speech by audible or mechanical means, and the feedback may be produced by vibration mechanisms.
US09263042B1	Providing pre-computed hotword models Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining, for each of multiple words or sub-words, audio data corresponding to multiple users speaking the word or sub-word; training, for each of the multiple words or sub-words, a pre-computed hotword model for the word or sub-word based on the audio data for the word or sub-word; receiving a candidate hotword from a computing device; identifying one or more pre-computed hotword models that correspond to the candidate hotword; and providing the identified, pre-computed hotword models to the computing device.
US09263040B2	Method and system for using sound related vehicle information to enhance speech recognition An audio signal may be received, in a processor associated with a vehicle. Sound related vehicle information representing one or more sounds may be received by the processor. The sound related vehicle information may or may not include an audio signal. A speech recognition process or system may be modified based on the sound related vehicle information.
US09263037B2	Interactive manual, system and method for vehicles and other complex equipment A method and system of providing an interactive manual, including a speech engine to receive and process speech from a user, convert the speech into a word sequence, and identify meaning structures from the word sequence, a structured manual including information related to an operation of a device, a visual model to relate visual representation of the information, a dialog management arrangement to interpret the meaning structures in a context and to extract pertinent information and the visual representation from the structured manual and the visual model, and an output arrangement to output the information and visual representation.
US09263032B2	Voice-responsive building management system A voice-responsive building management system is described herein. One system includes an interface, a dynamic grammar builder, and a speech processing engine. The interface is configured to receive a speech card of a user, wherein the speech card of the user includes speech training data of the user and domain vocabulary for applications of the building management system for which the user is authorized. The dynamic grammar builder is configured to generate grammar from a building information model of the building management system. The speech processing engine is configured to receive a voice command or voice query from the user, and execute the voice command or voice query using the speech training data of the user, the domain vocabulary, and the grammar generated from the building information model.
US09263030B2	Adaptive online feature normalization for speech recognition A speech recognition system adaptively estimates a warping factor used to reduce speaker variability. The warping factor is estimated using a small window (e.g. 100 ms) of speech. The warping factor is adaptively adjusted as more speech is obtained until the warping factor converges or a pre-defined maximum number of adaptation is reached. The speaker may be placed into a group selected from two or more groups based on characteristics that are associated with the speaker's window of speech. Different step sizes may be used within the different groups when estimating the warping factor. VTLN is applied to the speech input using the estimated warping factor. A linear transformation, including a bias term, may also be computed to assist in normalizing the speech along with the application of the VTLN.
US09263029B2	Instant communication voice recognition method and terminal The present disclosure discloses a speech recognition method and a terminal, which belong to the field of communications. The method comprises: receiving speech information inputted by a user; acquiring the current environment information, and judging whether the speech information needs to be played according to the current environment information; and recognizing the speech information as text information, when it is judged that the speech information needs not to be played. The terminal comprises an acquisition module, a judgment module and a recognition module. The present disclosure provides the speech receiver with a speech recognition function, when the speech information of the instant messaging is received by the terminal, it can help the receiver to normally acquire the content to be expressed by the speech sender under an inconvenient situation.
US09263028B2	Methods and systems for automated generation of nativized multi-lingual lexicons An input signal that includes linguistic content in a first language may be received by a computing device. The linguistic content may include text or speech. The computing device may associate the linguistic content in the first language with one or more phonemes from a second language. The computing device may also determine a phonemic representation of the linguistic content in the first language based on use of the one or more phonemes from the second language. The phonemic representation may be indicative of a pronunciation of the linguistic content in the first language according to speech sounds of the second language.
US09263019B2	Percussion instrument and method of manufacture A percussion instrument including a first acoustic chamber housing having a tapered shape, a second acoustic chamber housing having the tapered shape, a sound board having the tapered shape arranged between the first acoustic chamber housing and the second acoustic chamber housing to form a first acoustic chamber defined by the first acoustic chamber housing and the sound board, and a second acoustic chamber defined by the second acoustic chamber housing and the sound board.
US09263018B2	System and method for modifying musical data A computer-implemented method comprises receiving musical data including reference timing data, and a succession of musical notes arranged with respect to the reference timing data, receiving input corresponding to a selection of a groove template, and altering the arrangement of the notes (shifting in a positive or negative direction) with respect to the reference timing data based on the selected groove template. Altering the arrangement of notes can further include adding additional musical notes to the succession of musical notes to add stylistic embellishments particular to the selected groove template, where one of the selectable groove templates includes adding a shuffle dynamic to the succession of musical notes by determining a positive offset associated with each of the musical notes along the musical bar, and applying the positive offset to each of the musical notes, wherein the positive offset corresponds to the position of the musical note.
US09263015B2	Wireless electric guitar An electronics module for an electric guitar is provided. The electronics module includes a processor, a plurality of controls, an antenna, and a computer-readable medium. The processor receives an audio signal generated by a vibration of a plurality of strings of the electric guitar. The plurality of controls are operably coupled to the processor and provide a mechanism for adjusting a sound created from the audio signal. The computer-readable medium is operably coupled to the processor and configured to cause the electric guitar to determine a control of the plurality of controls associated with the received effects parameter; adjust a state of the determined control based on the received effects parameter; modify the audio signal based on the plurality of controls and on the received effects parameter; and output the modified audio signal through the antenna to a second device.
US09263013B2	Systems and methods for analyzing melodies In one embodiment, a system for analyzing melodies is disclosed that may receive data for a musical composition, the data including a sequence of notes that make up a melody contained in the musical composition, and store, in a database, a pitch and a duration for at least one note in the sequence of notes in association with the melody. In addition, the system may determine at least one pitch differential and at least one duration ratio for at least two consecutive notes in the sequence of notes, and store, in the database, the at least one pitch differential and the at least one duration ratio in association with the melody. The system may also generate at least one metric associated with the melody based on the at least one pitch differential and/or the at least one duration ratio.
US09263007B2	Guitar pick A guitar pick is described that places the playing edge and associated tip at an angle relative to a planar body that is grasp by the thumb and forefinger of a player to permit the player to hold his/her wrist at a more natural angle when playing. The pick is characterized by an arcuate wall that rises from a distal end of the pick, which in combination with the body forms a cradle for the thumb. A planar jut extends from the top edge of the arcuate wall and includes the playing edge and tip of the pick. The plane defined by the jut and the plane defined by the body define an acute angle of intersection.
US09263000B2	Leveraging compression for display buffer blit in a graphics system having an integrated graphics processing unit and a discrete graphics processing unit A graphics system includes an integrated graphics processor and a discrete graphics processing unit. An intra-system bus coupled data from the discrete graphics processing unit to the integrated graphics processor. In a high performance mode the discrete graphics processing unit is used to render frames. Compression techniques are used to aid in the data transfer over an intra-system bus interface.
US09262999B1	Content orientation based on user orientation Described herein are systems, devices and methods for presenting content based on the spatial relationship between a media device and a user of the media device. The media device may present content based on an angle between an eye axis of the user and a device axis of the media device.
US09262997B2	Image display apparatus An image display apparatus includes a liquid crystal panel with a dual-view function to display two different first and second screen-sized images that are visible in a driver-seat direction and a passenger-seat direction, respectively. The first screen-sized image in the driver-seat direction contains a guidance image and a guidance manipulation image; the second screen-sized image in the passenger-seat direction contains a video image and a video manipulation image. When an occupant in the driver seat manipulates an icon within the guidance manipulation image on the liquid crystal display panel, the same guidance manipulation image is also displayed in the passenger-seat direction by replacing the video manipulation image.
US09262996B2	Apparatus and method for displaying images A mask region extraction unit extracts a region that is to be masked in a panoramic image. A mask processing unit generates the object image where the region to be masked in the panoramic image is masked. A positioning unit adjusts the direction of a spherical image to the shooting direction of the object image. A mapping processing unit maps the mask-processed object image and the spherical image onto a three-dimensional (3D) object space as textures. A 3D image generator generates a 3D panoramic image, when the 3D panoramic image is viewed in a specified line of sight in such a manner so as to regard the shooting location of the panoramic as a viewpoint position.
US09262992B2	Multiple hardware paths for backlight control in computer systems The disclosed embodiments provide a system that drives a display from a computer system. The system includes a first hardware path for controlling a backlight of a display of the computer system. The system also includes a second hardware path for controlling the backlight. Finally, the system includes a backlight controller that enables use of the first and second hardware paths in controlling the backlight from the computer system.
US09262991B2	Displaying visual analytics of entity data According to an example, in a method for displaying visual analytics of entity data, geographic locations of entities may be plotted as first pixel cells on a first region and as second pixel cells on a second region of a geographic map. A determination may be made that the first pixel cells have a higher degree of overlap with each other in the first region compared to the second pixel cells in the second region. The geographic map may be distorted to enlarge the first region and the first pixel cells may be arranged in the first region in a manner that prevents the first pixel cells from overlapping each other. A color value for each of the pixel cells may be determined from a multi-paired color map that represents two variables corresponding to the entities by color and the pixel cells may be caused to be displayed on the distorted geographic map according to the determined respective color values.
US09262990B2	Projector spatially modulating incident light to display images of different colors Green and red light from first green and red light sources light a first element. Green and red light from second green and red light sources light a second element. Blue light from a blue light source light a third element. A control unit causes an image of a first video signal to be displayed on the first element during lighting of first red source, and causes an image of a second video signal to be displayed on the first element during lighting of the first green source. The unit causes an image of the first signal to be displayed on the second element during lighting of the second red source, and causes an image of the second signal to be displayed on the second element during lighting of the second green source. The unit causes an image of a third video signal to be displayed on the third element.
US09262988B2	Radio frequency interference reduction in multimedia interfaces A device for communications over a multimedia communication interface. The device can be a source device including a scrambling circuit that receives control data associated with multimedia data to be transmitted over the multimedia channel of the multimedia communication interface, and generates scrambled control codes based on the control data. An encoding circuit generates transition minimized control codes based on the scrambled control codes. The device transmits the transition minimized control codes to a sink device via the multimedia channel. The sink device may also decode and de-scramble the transition minimized control codes received from the source device via the multimedia channel.
US09262984B2	Device and method for controlling rotation of displayed image A device and method for controlling rotation of a displayed image is provided. The device includes a sensor unit for detecting whether the device has been rotated; a photography unit for taking a picture of the face of a user in response to a determination that the device is rotated; a rotation determination unit for determining a rotation of the displayed image based on the captured face image of the user; and an image rotation unit for rotating the displayed image according to the determined rotation of the displayed image.
US09262983B1	Rear projection system with passive display screen Described herein are systems and techniques for projecting content, periodically or continuously, onto a rear surface of a display medium from behind. The rear projected image is presented on an opposing or front surface of the display medium to a human audience for viewing. Additionally, non-visible light (e.g., IR light) is passed through the display medium to an area in front of the medium. The non-visible light is used to detect human gestures. In this manner, the rear projection arrangement avoids viewer obstruction during projection, yet detects and recognizes gestures made by the viewer in front of the display medium.
US09262973B2	Electrophoretic display capable of reducing passive matrix coupling effect and method thereof An electrophoretic display capable of reducing passive matrix coupling effect includes an electrophoretic panel, a plurality of first scan lines, and a plurality of second scan lines. The electrophoretic panel includes a plurality of pixels. Each pixel of the plurality of pixels corresponds to a storage capacitor, and the storage capacitor is coupled to a first scan line and a second scan line. When the pixel is used for displaying a first color, the first scan line receives a first driving voltage, the second scan line is coupled to ground, and other first scan lines and other second scan lines receive a first voltage. A voltage difference between the first driving voltage and the first voltage and a voltage difference between the ground and the first voltage are smaller than a first threshold value corresponding to the first color.
US09262972B2	Method for controlling electro-optic device, device for controlling electro-optic device, electro-optic device, and electronic apparatus A method for controlling an electro-optic device switches between a first driving scheme for changing an optical state between a-number of optical states and a second driving scheme for changing an optical state between b-number of optical states (b>a). In the first driving scheme, an integrated value W (A→B) of drive voltage and drive time when changing an optical state A to an optical state B, and an integrated value W (B→A) of drive voltage and drive time when changing the pixel from the optical state B to the optical state A satisfy a relation of W (A→B)=−W (B→A), and the integrated value W (A→B) and W (B→A) for the optical state A and B in the second driving scheme are equal to the integrated value W (A→B) and W (B→A) in the first driving scheme, respectively.
US09262970B2	Display device and electronic apparatus According to an aspect, a display device includes: an image display panel; a color conversion device including a signal processing unit and a signal output unit; a planar light-source device; and a light-source-device control unit. The signal processing unit includes a color conversion circuit that converts an input signal in a reference color area into a converted input signal generated in a definition color area where a chromaticity point of at least one of a first color, a second color, and a third color is inside of a reference color area, and a four-color generation circuit that generates an output signal and a light-source-device control signal from the converted input signal. The signal output unit outputs the drive signal to each sub-pixel based on the output signal. The light-source-device control unit outputs a drive voltage for emitting white light on the planar light-source device based on the light-source-device control signal.
US09262969B2	Electronic device and method for backlighting LCD display to provide different display definitions Electronic device and a method for backlighting a liquid crystal display (LCD) display to provide different display definitions, the LCD display includes a backlight unit composed of one or more backlighting blocks. The method determines a display definition of a video image and illuminates or turns off backlighting blocks of the backlight unit to display the video image accordingly. The video image is displayed in full screen by all backlighting blocks if the video image is an ultra high definition (UHD) image, and turns on a smaller number of the backlighting blocks to display the video image if the video image has other than UHD display definition. As such, the electronic device is controlled to save power consumption in different display definitions of the LCD display.
US09262968B2	Image display apparatus and control method thereof An image display apparatus according to the present invention includes: a light emitting unit configured to include a light source; a display unit configured to display an image on a screen by transmitting light irradiated from the light emitting unit; a detection unit configured to detect light from the light source; and a control unit configured to extend a lighting duration of the light source when the detection unit detects light in a case where the lighting duration of the light source is shorter than a predetermined time length.
US09262967B2	Display apparatus and driving method therefor A display apparatus disclosed herein includes a plurality of pixel circuits, each having a plurality of switches configured to receive a driving signal of a predetermined period and to be controlled for opening and closing operation by the driving signal, a drive circuit configured to control the open/closed state of the switches, being operable to scan the pixel circuits and open and close the switches in periods independent of each other.
US09262961B2	Pixel arrangement of color display apparatus A color display apparatus includes pixels P(i, j) arranged in a matrix having M columns and N rows, where i=1, 2, . . . , M, j=1, 2 . . . , N. A plurality of pixel pairs is defined along either the columns or the rows. Each pixel pair includes one pixel P(i, j) and the next immediate pixel, where if i is an odd integer, j is an odd integer, and if i is an even integer, j is an even integer. Each pixel pair has a first subpixel configured to display a first color and symmetrically positioned across the pixels, a pair of second subpixels configured to display a second color and symmetrically positioned in the pixels respectively, and a pair of third subpixels configured to display a third color and symmetrically positioned in the pixels respectively. The first subpixel is positioned between the pair of second subpixels.
US09262959B2	EL display device Provided is an EL display device that includes: an EL display panel including an array of a plurality of pixel circuits each having a drive transistor that applies a current to an organic EL element; a driver circuit that applies, to each of the pixel circuits, a signal in response to an image signal and a signal for selecting pixel circuits that are expected to emit light; and an N-bit D/A converter. An image display period in a single frame is divided into a first subframe and a second subframe, the first subframe performing display by light emission based on a gray-level signal of high N bits, the second subframe performing display by light emission based on a gray-level signal of low M bits (where M satisfies ML2.
US09262957B2	Pixel arrangement of color display panel A pixel arrangement of color display panel includes a plurality of first sub-pixels for providing a first color light, a plurality of second sub-pixels for providing a second color light, a plurality of third sub-pixels for providing a third color light and a plurality of white sub-pixels for providing a white light. The first sub-pixels extend along a first direction, and form a plurality of first sub-pixel columns disposed in parallel. The second and third sub-pixels are disposed between two adjacent first sub-pixel columns. The white sub-pixels are disposed between two adjacent first sub-pixel columns, and the white sub-pixels extend along the first direction, and form a plurality of white sub-pixel columns disposed in parallel.
US09262955B2	Display device and driving method thereof A display device includes a display panel, a gate driver, a gate clock signal modulating unit, and a gate clock signal generator. The display panel includes gate lines and pixels connected to the gate lines via respective switching elements. The gate driver includes stages configured to output gate signals to the gate lines. The gate clock signal modulating unit is configured to modulate an input gate clock signal based on a scanning start signal to generate an output gate clock signal. The gate clock signal generator is configured to generate a clock signal based on the gate clock signal and output the clock signal to the gate driver. The gate clock signal modulating unit is configured to modulate a width of a pulse of the input gate clock signal overlapping a pulse of the scanning start signal.
US09262952B2	Organic light emitting display panel Provided is an organic light emitting display panel. The organic light emitting display panel includes a pixel unit including a plurality of pixels I displaying mutually different colors, a plurality of data pads electrically connected to wirings extending from the data lines, each of the plurality of data pads being connected to corresponding data lines, respectively, and an array test unit applying an array test signal to the plurality of pixels of the pixel unit, and sensing a current outputted from the plurality of pixels. The array test unit includes an array test pad electrically connected to a plurality of data pads through a plurality of array test switches.
US09262947B2	Apparatus and method for display of electronic advertising An apparatus for displaying electronic advertisements or the like is provided herein. In one embodiment, the apparatus may include a first planar body having a first electronic display and a second planar body having a second electronic display. The apparatus may include a connector for connecting the first and second planar bodies, and at least one controller component operatively coupled to the first and second electronic displays. The apparatus may include at least one alarm component attached to at least one of the first and second planar bodies, and at least one movement detection component operatively coupled to the at least one alarm component. The apparatus may include at least one power component operatively coupled to the first and second electronic displays and the at least one alarm component.
US09262945B2	Corner tab kit and system for portable fabric panel displays A panel element includes a fabric panel, a corner gasket element and two auxiliary gaskets. The corner gasket element has a tab member and two gasket legs. Each leg extends to respective outer ends from a common intersection in a manner orthogonal to one another. The tab member extends from the intersection in a manner orthogonal to the legs. The auxiliary gaskets each have at least one gasket end positioned adjacently to a respective outer end. The fabric panel has a display face and an outer perimeter portion. The outer perimeter portion is affixed to the gasket legs and the auxiliary gaskets. The gasket legs and auxiliary gasket elements are removably insertable into a perimeter groove disposed in the closed-contour framework, thereby facilitating tensioned attachment of the fabric panel across an opening defined by the closed contour with said tab member gripably protruding outward of the display face.
US09262944B2	Curvilinear solid for information input, map for information input, drawing for information input Problems of dot pattern technology include latitude/longitude information not being able to be acquired from a curvilinear solid. To read coordinate and/or code information from the vicinity of a line segment to acquire information associated with the line segment, it is necessary to define manually an area including the line segment to form the dot-pattern associated with the information in the area. In the case where line segments are adjacent, a sufficient area cannot be secured and information cannot be defined accurately for the line segment. Stream dot-patterns which are formed based on a prescribed rule, and which have few moires that are streaky periodic patterns are connected and formed in a belt-like shape. It becomes possible to create an information inputting medium that accurately defines the latitude/longitude and coordinate information on various line segments on the curvilinear solid, the map, the drawing, or the like.
US09262941B2	Systems and methods for assessment of non-native speech using vowel space characteristics Computer-implemented systems and methods are provided for assessing non-native speech proficiency. A non-native speech sample is processed to identify a plurality of vowel sound boundaries in the non-native speech sample. Portions of the non-native speech sample are analyzed within the vowel sound boundaries to extract vowel characteristics. The vowel characteristics are used to identify a plurality of vowel space metrics for the non-native speech sample, and the vowel space metrics are used to determine a non-native speech proficiency score for the non-native speech sample.
US09262937B2	System and method for correlating curricula A system and method for correlating learning objectives, curriculum items or elements or competency expectations between multiple curricula, or between a curriculum and established national, industry or governmental standards, includes multiple steps. A first curriculum, including multiple curriculum items, is selected. A second curriculum or standard, containing multiple elements, is selected. A curriculum item from within the first curriculum is selected. A filter is applied to the elements of the second curriculum or standard to produce a visible display of a subset of elements from within the second curriculum. Individual elements, from within the subset of elements, are identified as correlating to the curriculum item. The individual elements that correlate to the curriculum item are tagged, or cross-walked, to create a link between the curricula.
US09262936B2	Determining individuals for online groups The disclosed subject matter relates to encouraging an individual to assume a leadership role associated with an online group relating to a subject matter. In one innovative aspect, the disclosed subject matter can be embodied in a method. The method includes determining a leadership score corresponding to an individual. The leadership score corresponds to a level of correlation between the individual and a leadership role associated with an online group relating to a subject matter. The method further includes providing, based on the leadership score, an invitation to be sent to the individual, inviting the user to assume a leadership role associated with the online group. The method further includes receiving an indication of an acceptance of the invitation. The method further includes assigning to the individual, based on the received indication of the acceptance, the leadership role associated with the online group relating to the subject matter.
US09262927B2	Method and device for automatically managing audio air control messages on an aircraft Methods and devices for automatically managing audio air control messages on an aircraft are described. The device comprises a unit for automatically transcribing an audio message received on board an aircraft into a textual message, a unit for automatically processing the textual message in order to extract all the indications included in this message, and a unit for automatically displaying, for each extracted indication, on at least one screen of the aircraft cockpit, an information message relating to the indication and a validation request for the pilot.
US09262926B2	Using pass code verification to organize a vehicle caravan A reference pass code is received from a first user. Location information of a vehicle of the first user is received from a first computer. A pass code is received from a second user. Location information of a vehicle of the second user is received from a second computer. One or more computer processors verify that the pass code received from the second user matches the reference pass code. Based on verification of the pass code received from the second user, the location information of the vehicle of the first user is transmitted to the second computer and the location information of the vehicle of the second user is transmitted to the first computer.
US09262918B2	Vehicle-use signal information processing device and vehicle-use signal information processing method, as well as driving assistance device and driving assistance method A signal information processing device and a signal information processing method for calculating the state of a traffic light for driving assistance for traffic lights for which signal information is not transmitted from a roadside apparatus, and a driving assistance device and a driving assistance method for performing driving assistance on the basis of the calculated state of the traffic light. A driving assistance ECU of a vehicle acquires signal information corresponding to a first traffic light and information indicating the driving environment of the vehicle corresponding to a second traffic light placed at a position different from the first traffic light. The driving assistance ECU is provided with a signal information processing unit, which estimates signal information of the second traffic light by performing a computation on the basis of the signal information corresponding to the first traffic light and the information indicating the driving environment of the vehicle.
US09262916B2	Server for providing traffic image to user device, and the user device A server for providing a traffic image to a user device includes a location information receiving unit which receives information relating to a respective location of each of a plurality of vehicles, a location management unit which receives information relating to a particular area from a user device, and which detects at least one vehicle located within the particular area based on the location information, an information sending unit which sends information relating to the at least one detected vehicle to the user device, an image requesting unit which receives information relating to a vehicle selected from among the at least one detected vehicle from the user device, and which requests, from a device installed in the selected vehicle, transmission of a traffic image of the selected vehicle, and an image providing unit which receives the image and which provides the traffic image to the user device.
US09262915B2	Intelligent urban communications portal and methods A system, device, and methods for monitoring and responding to information needs of users in an urban grid or local map area. The system is a platform to virtualize an urban space, provide map overlayers with local data content, and allow users to access personalized content having relevance based on proximity, location, time, and keyword search criteria such as guest entries, local ties recent user internet activity, time of day, special events related to a user's profile, appointments in a user's calendar, traffic conditions, destinations along a user's footpath having possible significance, schedules and routes for transit, taxi or rental information for visitors, environmental conditions, and the like. In a second embodiment, the system may be expanded to assist guests with parking and traffic management issues.
US09262914B2	Rogue vehicle detection The present subject matter relates to a method for rogue vehicle detection. The method includes receiving at least one violation report for a vehicle from at least one mobile communication device. The at least one violation report is indicative of a traffic violation made by the one or more vehicles. The method further includes categorizing the vehicle as a rogue vehicle, based on at least one rogue vehicle detection metric, the at least one rogue vehicle detection metric being determined from the violation report. The method also includes compiling a traffic observation record based on at least one of the violation report and the rogue vehicle detection metric.
US09262911B2	Information processing apparatus, control method for information processing apparatus, control method for electronic device, and storage medium containing control program An information processing apparatus (1) includes a processing execution unit (19) that, if a positional-relationship specification unit (18) detects that a positional relationship between an electronic device (2) and the own apparatus is held continuously for a predetermined time or longer, references a processing specification table (17), specifies processing, and executes the specified processing.
US09262910B1	Precision wireless sensor A precision wireless sensor for monitoring the environment surrounding the sensor. The precision wireless sensor comprises a wireless transmitter, a wireless receiver with bank of down converters and bank of correlators, a receive signal strength measurement circuit, and a control processor with timing counter. The control processor utilizes the received information, received signal strength and timing information to estimate and calculate various environmental parameters which can be used to activate different devices.
US09262909B1	Audio monitoring and sound identification process for remote alarms In a method for remote monitoring of alarms, a user interface is provided to a user of a mobile computing. The user interface enables the user to enter alarm descriptors associated with alarm devices, and indicate timings of triggering alarm devices. A timing of triggering a first alarm device indicated by the user is received, after which a microphone of the mobile computing device is utilized to detect a first audio test signal generated by the first alarm device. The first audio test signal is processed to generate first alarm identification data, and a first alarm descriptor entered by the user is received. The first alarm descriptor and first alarm identification data are transferred from the mobile computing device to an alarm monitoring system to enable the alarm monitoring system to identify the first alarm device when the first alarm device detects an alarm condition and generates an audio signal.
US09262903B2	System and method to monitor events and personnel locations A method and apparatus where the apparatus performs the steps of receiving a location of a person; determining via a database a hazard level of the location confirming via a database that the person is qualified to be present at the location based upon a training level of the person for the determined hazard level of the location and wirelessly notifying the person to leave the location upon determining that the person is not qualified for the hazard level of the location based upon the training level of the person.
US09262900B2	Security tag for application to footwear Systems (100) and methods (1300) for operating a security tag (132). The methods involve: slidingly coupling a first engagement member (212) of the security tag to a first sidewall (208) forming a first right angle with a base (220) of an article; and extending a securement member (218) of the security tag across an exterior surface of the base of the article. A second engagement member (210) of the security tag is slidingly coupled to a second sidewall (206) opposed from the first sidewall and forming a second right angle with the base of the article. A length of the securement member is then decreased so as to place the securement member in a tensioned position whereby the security tag is secured to the article. The securement member can be locked in the tensioned position using a mechanical locking mechanism (222) of the security tag.
US09262898B2	System and method for validating video security information A method is provided in one example and includes receiving video data captured by a camera at a location; comparing a portion of the video data to security information characteristics stored in a policy; and identifying a violation of the policy when the portion of the video data does not match at least one of the security information characteristics stored in the policy. In more particular instances, the method can include triggering an alert when the violation of the policy is identified.
US09262888B1	Wagering system and method A system is provided that, in some aspects, determines a user's intent to place a wager or redeem a wager based on bar codes generated by a client device operated by the user.
US09262886B2	Processing wagering game events This description describes techniques for processing events in a wagering game machine. In some embodiments, a wagering game machine includes a game controller configured to instantiate a game state element based on game state element generation information and game state types, wherein the game state element is configured to present a wagering game, and wherein the game state element includes states, wherein each state includes behaviors. The wagering game machine can also include an event controller to notify the game state element about events, wherein the events cause the game state element to move between the states and to perform the behaviors.
US09262885B2	Methods and systems for facilitating table games A gaming table provides for use of RFID technology to track chip movement on a table game and to infer an association between a wager and a player position based on a chip identifier of a chip placed on a particular position of the table. In some embodiments, previous position history of the chip is also taken into account in determining a player position associated with a wager.
US09262884B1	System and method for evaluating gaming machines A system and method for facilitating the evaluation of a prototype gaming machine by an at least one respondent provides, in the exemplary embodiment, a gaming room containing the prototype gaming machine and an at least one alternative gaming machine. Each respondent is provided with an equal number of play credits to be selectively used in the prototype and alternative machines in lieu of actual money. A game play session is commenced, during which time the respondents are able to freely and selectively interact with each of the prototype and alternative machines. Upon conclusion of the game play session, the number of credits accumulated by each respondent during the game play session are calculated and the respondents are ranked accordingly. Prizes are subsequently awarded to each of the respondents based on their respective rankings, and a survey is conducted with respect to each respondent's opinion of the prototype gaming machine.
US09262883B2	Performance apparatus as top box with external input for gaming machine A performance apparatus includes an accepting unit, a memory, an output unit and a performance unit. The accepting unit accepts first performance information from a source outside of the performance apparatus, and the memory stores second performance information. The output unit outputs one of a performance signal based on the first performance information accepted by the accepting unit and a performance signal based on the second performance information stored in the memory on the basis of a predetermined performance condition. The performance unit executes a performance according to the performance signal output from the output unit.
US09262882B2	Social voting-based campaigns in search Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, determining that a voting user interface (VUI) is to be provided with search results, the VUI enabling a user to submit one or more votes in a voting-based campaign; receiving social content, the social content having been distributed using one or more social networking services; receiving search results that are responsive to a search query; and transmitting instructions to display the search results and the VUI, the VUI comprising the social content.
US09262879B2	Remote notification of phone for home security A lock system is provided with a lock and a wireless device. The lock may be capable of sending and receiving Bluetooth messages to and from the wireless device, and the wireless device may be capable of sending and receiving Bluetooth messages to and from the lock.
US09262877B2	Access authorization servers, methods and computer program products employing wireless terminal location An access authorization server includes an access authorization processor configured to receive information concerning an access attempt at a subscribed location, to obtain location information from a wireless network provider for a wireless terminal associated with the subscribed location, to correlate a location of the wireless terminal with the subscribed location, to generate authorization information for the access attempt in response to a result of the correlation of the location of the wireless terminal and the subscribed location, and to transmit the authorization information to a security processor at the subscribed location or to the wireless terminal. Corresponding method and computer program embodiments are disclosed.
US09262876B2	Method for controlling fraud and enhancing security and privacy by using personal hybrid card A method for controlling fraud using a personal hybrid card and a verification process is disclosed. The method includes registering personal information of an individual in a database forming a registered account for the individual, and assigning a personal hybrid card to the individual with the registered account. The personal hybrid card includes a data storage and a copy of the personal information, including first biometric data stored in the data storage. The method continues by verifying, at an access point, that the individual with the personal hybrid card matches the first biometric data of the individual, that is stored on the personal hybrid card. Next, the individual's personal information is transmitted from the access point to the database for requesting verification of the individual to use the personal hybrid card, and receiving eligibility verification or denial of the individual for accessing services, benefits, programs, and combinations thereof.
US09262875B1	Lock structure of dual protection A lock structure of dual protection includes a lock core rotating shaft, swing rod, push rod, brake shoe and handle rotating shaft coupled pivotally to a door handle configure on a lock, wherein a first latch element is configured above the swing rod, and a second latch element at one side of the handle rotating shaft, allowing the first latch element and second latch element to be in respective connection with indoor and outdoor card readers through a control circuit. Whereby, the lock must be unlocked by swiping an access card outdoors or indoors while being locked, and a user is allowed to turn a door handle to unlock the lock indoors or outdoors by means of the motion of the first latch element of second latch element subjected to or released from magnetic suction while the access card is swiped so that the dual protection can be achieved.
US09262872B2	Postage sheet product A printable postage sheet includes a plurality of substantially equally sized preprinted postage labels arranged in a matrix of n rows by m columns, where n and m are integers. The plurality of preprinted postage labels are symmetrically arranged in the printable postage sheet with respect to a first axis and a second axis perpendicular to the first axis. Preprinted indicia on each of the preprinted postage labels are preprinted on generally the same location on all of the preprinted postage labels. The preprinted indicia are all oriented in a same orientation relative to the sheet. A printable area of each preprinted postage label is positioned on the label such that when indicia are printed on one or more of the preprinted postage labels, the indicia are positioned within the printable area irrespective of a right side up or upside down feeding orientation of the printable postage sheet into a printer.
US09262870B2	Methods and a system for dispensing In one example, the invention includes steps of: activating feeding and exiting motors of a dispensing device that cause corresponding rollers to rotate in forward direction, wherein the feeding motor is operatively connected to a displacement optical sensor, wherein the feeding and exiting rollers move a dispensing object; wherein an exit sensor generates a first signal, indicating that a leading edge of the dispensing object has activated the exit sensor, generating, by the stationary displacement optical sensor, a second signal, when, by passing at least one light beam over a surface of the portion of the dispensing object, the stationary displacement optical sensor determines that the portion of the dispensing object has traveled a pre-determined distance along the dispensing passage.
US09262869B2	Method of 3D model morphing driven by facial tracking and electronic device using the method the same A method of 3D morphing driven by facial tracking is provided. First, a 3D model is loaded. After that, facial feature control points and boundary control points are picked up respectively. A configure file “A.config” including the facial feature control points and boundary control points data that are picked up corresponding to the 3D avatar is saved. Facial tracking algorithm is started, and then “A.config” is loaded. After that, controlled morphing of a 3D avatar by facial tracking based on “A.config” is performed in real time by a deformation method having control points. Meanwhile, teeth and tongue tracking of the real-time face image, and scaling, translation and rotation of the real-time 3D avatar image is also provided. In addition, a control point reassignment and reconfiguration method, and a pupil movement detection method is also provided in the method of 3D morphing driven by facial tracking.
US09262867B2	Mobile terminal and method of operation A method of operation of a mobile terminal includes displaying, on a display module, a preview image generated by a camera module, obtaining object information for at least one object shown in the preview image or at least one object within a predetermined distance of a current location of the mobile terminal, and displaying the object information on the display module using a display form that is determined according to a user preference level of the object information.
US09262863B2	Creating dynamic sets to automatically arrange dimension annotations A computer-implemented method and system creates dynamic sets to automatically arrange dimension annotations in a CAD model. The invention method/product/data storage medium/system determines a location to place a new dimension annotation based on dimension type of the entity selected to annotate. One or more sets of existing dimension annotations are created. The existing dimension annotations in the same set together with the new dimension annotation with similar characteristics as those in the same set are sorted, and then displayed in sorted order in a view of the CAD model on the computer screen.
US09262862B2	Method and apparatus for reconstructing three dimensional model A method and an apparatus for reconstructing a three dimensional model of an object are provided. The method includes the following steps. A plurality of first depth images of an object are obtained. According to a linking information of the object, the first depth images are divided into a plurality of depth image groups. The linking information records location information corresponding to a plurality of substructures of the object. Each depth image group includes a plurality of second depth images, and the substructures correspond to the second depth images. According to the second depth image and the location information corresponding to each substructure, a local module of each substructure is built. According to the linking information, the local models corresponding to the substructures are merged, and the three-dimensional model of the object is built.
US09262859B2	Surface patch techniques for computational geometry A method and system for computer aided design (CAD) is disclosed for designing geometric objects, wherein interpolation and/or blending between such objects is performed while deformation data is being input. Thus, a designer obtains immediate feedback to input modifications without separately entering a command (s) for performing such deformations. A novel N-sided surface generation technique is also disclosed herein to efficiently and accurately convert surfaces of high polynomial degree into a collection of lower degree surfaces. E.g., the N-sided surface generation technique disclosed herein subdivides parameter space objects (e.g., polygons) of seven or more sides into a collection of subpolygons, wherein each subpolygon has a reduced number of sides. More particularly, each subpolygon has 3 or 4 sides. The present disclosure is particularly useful for designing the shape of surfaces. Thus, the present disclosure is applicable to various design domains such as the design of, e.g., bottles, vehicles, and watercraft. Additionally, the present disclosure provides for efficient animation via repeatedly modifying surfaces of an animated object such as a representation of a face.
US09262855B2	Stateless animation, such as bounce easing An animation system is described herein that uses a transfer function on the progress of an animation that realistically simulates a bounce behavior. The transfer function maps normalized time and allows a user to specify both a number of bounces and a bounciness factor. Given a normalized time input, the animation system maps the time input onto a unit space where a single unit is the duration of the first bounce. In this coordinate space, the system can find the corresponding bounce and compute the start unit and end unit of this bounce. The system projects the start and end units back onto a normalized time scale and fits these points to a quadratic curve. The quadratic curve can be directly evaluated at the normalized time input to produce a particular output.
US09262847B2	Method and system for improved glyph cache efficiency A method, system and computer program product encoded on a computer-readable medium for obtaining a glyph rendering are described. A request is received for a rendered first glyph for display on a display device. The request includes rendering information including a first origin. Each device pixel of the display device includes n sub-pixels, where n is an integer greater than 1. A rendered second glyph matching the first glyph is found in a cache of rendered glyphs. A matching rendered second glyph includes a rendered glyph having a second origin offset from the first origin by x/n of a device pixel, where x is an integer ranging between 1 and (n−1). If the second origin is offset from the first origin by x/n, then the density values associated with each sub-pixel of the matching rendered second glyph are shifted by x/n of a device pixel.
US09262834B2	Systems and methods for performing segmentation and visualization of images A method for visualizing an object of interest includes obtaining an image of an object of interest, automatically separating the image into tissue clusters, automatically selecting foreground clusters from the tissue clusters, automatically generating a contour based on the selected foreground clusters, and displaying an image of the object of interest including the foreground clusters and the contour. A system and non-transitory computer readable medium are also described herein.
US09262833B2	Methodology for performing depth estimation with defocused images under extreme lighting conditions A methodology for performing a depth estimation procedure with defocused images under extreme lighting conditions includes a camera device with a sensor for capturing blur images of a photographic target under extreme lighting conditions. The extreme lighting conditions may include over-exposed conditions and/or under-exposed conditions. The camera device also includes a depth generator that performs the depth estimation procedure by utilizing the captured blur images. The depth estimation procedure includes a clipped-pixel substitution procedure to compensate for the extreme lighting conditions.
US09262832B2	Cart inspection for suspicious items Methods and apparatus provide for a Cart Inspector to create a suspicion level for a transaction when a video image of the transaction portrays an item(s) left in a shopping cart. Specifically, the Cart Inspector obtains video data associated with a time(s) of interest. The video data originates from a video camera that monitors a transaction area. The Cart Inspector analyzes the video data with respect to target image(s) associated with a transaction in the transaction area during the time(s) of interest. The Cart Inspector creates an indication of a suspicion level for the transaction based on analysis of the target image(s). Creation of a high suspicion level for the transaction indicates that the transaction's corresponding video images most likely portray occurrences where the purchase price of an item transported through the transaction area was not included in the total amount paid by the customer.
US09262828B2	Method and device for online calibration of vehicle cameras A method for determining the orientation of a video camera attached to a vehicle relative to the vehicle coordinate system is disclosed. Using a video camera an incremental motion is measured based on the optical flow of the video stream. A linear motion component and a rotational motion component are determined. Based on a determined rotational angle the incremental motion is classified as linear or as rotational. The directional vector of the linear motion is used to estimate the longitudinal axis of the vehicle, and the rotational vector of the rotational motion is used for estimating the normal to the vehicle plane. Based thereon the orientation of the camera follows.
US09262827B2	Lung, lobe, and fissure imaging systems and methods An automated or semi-automated system and methods are disclosed that provide a rapid and repeatable method for identifying lung, lobe, and fissure voxels in CT images, and allowing for quantitative lung assessment and fissure integrity analysis. An automated or semi-automated segmentation and editing system and methods are also disclosed for lung segmentation and identification of lung fissures.
US09262825B2	Image reconstruction in interleaved multi-energy imaging The present invention discloses a method for reconstructing an image obtained from kVp switched imaging of a body by acquiring a plurality of images at a first kVp defining a first image scan and a plurality of images at a second kVp defining a second image scan, wherein the plurality of images at the first kVp are acquired interleaved with the plurality of images of the second image scan and by reconstructing an image from the first and second image scan, comprising determining at least one gradient location for at least two images in the first and second image scans, determining divergent gradient locations in respect of a same part of the body for said at least two images in the first and second image scans, tagging each divergent gradient location as an under sampling artifact, generating the reconstructed image from the at least two images in the first and second image scans by correcting for each tagged under sampling artifact. The invention further discloses an imaging system for imaging at least a part of a body by means of a first image scan and a second image scan and a computer program product.
US09262823B2	Medical image generating apparatus and medical image generating method A 3D ultrasound image generating apparatus and method includes a volume-data generator to generate 3-dimensional (3D) volume data based on at least one cross-sectional image with respect to a body tissue of a subject, and a controller that generates the final 3D image having the adjusted 3D effect by volume rendering the 3D volume data based on the input stereo-depth value when a stereo-depth value used to adjust the 3D effect of a final 3D image generated based on the 3D volume data is input.
US09262820B2	Method and apparatus for integrated circuit design A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.
US09262819B1	System and method for estimating spatial characteristics of integrated circuits Methods of the present disclosure can include a method for estimating a spatial characteristic of an integrated circuit (IC), the method comprising: calculating a correlation between a dimension of a photoresist layer and exposure to a scanning electron microscope (SEM) for at least one reference IC pattern in the photoresist layer, the correlation providing a relationship between the dimension of the photoresist and the spatial characteristic, wherein the calculating is based on: an SEM image of the at least one reference IC pattern produced from reducing the dimension of the photoresist layer with the SEM from an initial value to a reduced value, the initial value of the dimension, and the reduced value of the dimension; and estimating the spatial characteristic of a target IC based on the correlation.
US09262818B2	System for detecting image abnormalities An image capture system for capturing images of an object, the image capture system comprising a moving platform such as an airplane, one or more image capture devices mounted to the moving platform, and a detection computer. The image capture device has a sensor for capturing an image. The detection computer executes an abnormality detection algorithm for detecting an abnormality in an image immediately after the image is captured and then automatically and immediately causing a re-shoot of the image. Alternatively, the detection computer sends a signal to the flight management software executed on a computer system to automatically schedule a re-shoot of the image. When the moving platform is an airplane, the detection computer schedules a re-shoot of the image such that the image is retaken before landing the airplane.
US09262817B2	Environment estimation apparatus and vehicle control system An environment estimation apparatus includes an image area dividing unit for dividing a camera image taken with a vehicle camera into a plurality of image areas, a camera image information extracting unit for extracting, from an image area that has the sky taken and is acquired from among the plurality of image areas undergoing the division by the image area dividing unit, image information indicating features of the image area, and an environment estimation unit for estimating, from the image information extracted by the camera image information extracting unit, the weather or intensity of light of a surrounding environment by referring to corresponding data indicating the correspondence between the features of the image area and the weather or the intensity of light of the surrounding environment.
US09262815B2	Algorithm for minimizing latent sharp image cost function and point spread function cost function with a spatial mask in a regularization term A method for deblurring a blurry image (18) includes utilizing a spatial mask and a variable splitting technique in the latent sharp image estimation cost function. Additionally or alternatively, the method can include the utilizing a spatial mask and a variable splitting technique in the PSF estimation cost function. The spatial mask can be in a regularization term of either or both the latent sharp image estimation cost function and the PSF cost function. The latent sharp image estimation cost function can be used for non-blind deconvolution. Alternatively, one or both cost functions can be used for blind deconvolution.
US09262813B2	Image processing apparatus and image processing method An image processing apparatus for generating corrected image data from a plurality of input image data by performing an iterative calculation process includes an input unit configured to input the plurality of input image data, an acquisition unit configured to acquire a photographing parameter used for photographing to acquire the input image data, a setting unit configured to set for each image area a number of iterations for generating the corrected image data based on the photographing parameter, and a generation unit configured to generate correction data from the plurality of image data by performing an iterative calculation process on each image area based on the number of iterations set for each image area.
US09262805B2	Method and device for processing image in Bayer format A method for processing an image in Bayer format is provided. The method may include: performing a binning process in a horizontal and/or vertical direction on an image which is to be processed, so that an arrangement mode of pixels in a processed image after binning is the same with that in the image to be processed, wherein the binning process may include: determining a position of an output pixel; selecting, from the image to be processed, a plurality of pixels which have the same color component with that of the output pixel, and calculating a weighted average of the plurality of pixels, so as to obtain a pixel value of the output pixel, wherein the plurality of pixels are selected from particular positions, so that the weighted average of the plurality of pixels can be calculated. According to the present disclosure, quality of image processing can be guaranteed.
US09262804B2	Method and apparatus for performing interpolation based on transform and inverse transform Provided are a method and apparatus for interpolating an image. The method includes: selecting a first filter, from among a plurality of different filters, for interpolating between pixel values of integer pixel units, according to an interpolation location; and generating at least one pixel value of at least one fractional pixel unit by interpolating between the pixel values of the integer pixel units by using the selected first filter.
US09262802B2	Independent digital templating software, and methods and systems using same Provided are a computer-aided system (medical device), a computer-aided method, and a computer program product useful in digital templating for prosthetic arthroplasty, for example, total hip arthroplasty. The invention includes digital image capture and scaling features that can be used in conjunction with any digital radiographic image stored using picture archiving and communication system (PACS), regardless of PACS provider or PACS format. Patient radiographic images are captured, imported, and scaled, e.g., to actual size, to match the scale of a digital template of any prosthesis selected by the user. The computer program product is a stand-alone product, used independently of any software interface, including software accessed through connection to a network or the internet. The software, method, and system are suitable for use with a stand-alone computer and permit improved and cost-effective selection of prostheses for any particular clinical situation.
US09262801B2	Image taping in a multi-camera array Multiple cameras are arranged in an array at a pitch, roll, and yaw that allow the cameras to have adjacent fields of view such that each camera is pointed inward relative to the array. The read window of an image sensor of each camera in a multi-camera array can be adjusted to minimize the overlap between adjacent fields of view, to maximize the correlation within the overlapping portions of the fields of view, and to correct for manufacturing and assembly tolerances. Images from cameras in a multi-camera array with adjacent fields of view can be manipulated using low-power warping and cropping techniques, and can be taped together to form a final image.
US09262800B2	Omnidirectional camera for use in police car event recording A system and method for an omnidirectional camera for use in recording events around a police vehicle is disclosed. The system and method include an omnidirectional camera and a digital processor for processing the omnidirectional images captured by the omnidirectional camera. The digital processor may be operable to locate one or more regions of interests disposed within the omnidirectional images. A recordable medium is also disclosed for storing at least some of the captured images.
US09262799B2	Shared memory eigensolver A method for computing eigenvectors and eigenvalues of a square matrix in a high performance computer involves dynamically reallocating the computer's computing cores for various phases of the computation process.
US09262797B2	Multi-sample surface processing using one sample A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel.
US09262794B2	Transactional video marking system Methods, devices, systems and computer program products facilitate embedding and extraction of transactional watermarks into and from a video content. One method for selecting an area for watermark insertion includes selecting a candidate area within a frame of the video content that is smaller in size that the frame itself, adding a first and a second watermark value to obtain corresponding first and second versions of the area, add noise to each of the first and second versions, and perform watermark extraction operations to obtain corresponding correlation values for the selected area. The above operations are repeated using different areas that are selected at pseudo-random offset values from the previously selected areas until the entire video frame is exhausted. One or more areas with the highest correlation value(s) are selected and designated as areas that are suitable for watermark insertion.
US09262793B2	Transactional video marking system Methods, devices, systems and computer program products facilitate embedding and extraction of transactional watermarks into and from a video content. One such method includes selecting a first number of frames from a video content and performing temporal and a spatial psychovisual analysis on the selected frames. For each selected frame, at least one area for insertion of watermarks is identified. A first and a second watermark symbol is embedded separately in the identified area(s), and the embedded frames are re-encoded to obtain a first and a second alternative data. An inserter manifest is formed that includes the first and the second alternative data to enable insertion of a watermark into the video content by selecting one or the other of the first and second alternative data for insertion into the video content.
US09262788B1	Methods and systems for capturing the condition of a physical structure via detection of electromagnetic radiation In a computer-implemented method and system for capturing the condition of a structure, the structure is scanned with a three-dimensional (3D) scanner. The 3D scanner generates 3D data. A point cloud or 3D model is constructed from the 3D data. The point cloud or 3D model is then analyzed to determine the condition of the structure.
US09262785B1	Automated banking machine in communication with a remote computer that generates an alert message when a calculated number of transactions exceeds a threshold An automated banking machine operates to cause financial transfers responsive at least in part to data read from data bearing records. The automated banking machine is operative to communicate with at least one remote computer that generates an alert message when a calculated number of transactions on a particular account exceeds a threshold.
US09262782B2	Secure transaction processing system and method A secure transaction processing system/method allowing injection and execution of credit card and ACH payment forms in a third party web page via cross domain requests is disclosed. The system/method provides a mechanism to inject and execute payment forms into a third (customer) party's website via Cross Domain Requests by providing a set of client application instructions that retrieves presentation and behavior logic and delivers it in a third party application. A browser based client application detects and manages style and behavior conflicts to render forms within in an existing third party web page. The client application then submits the forms via Cross Domain Requests to the transaction processing web server and directs the client application to a new navigation target within the third party website.
US09262772B2	Systems and methods using a wearable device to determine an individuals daily routine The methods and systems described herein may involve determining at least one lifeotype of at least one individual, analyzing the at least one lifeotype, and delivering content to at least one individual based on the analysis. The methods and systems described herein may involve providing a game, determining at least one lifeotype of at least one player of the game, analyzing the at least one lifeotype, and affecting the game play based on the analysis. The methods and systems described herein may involve providing an interactive space, determining at least one lifeotype of at least one individual in the space, analyzing the at least one lifeotype, and modifying at least one attribute of the space based on the analysis.
US09262770B2	Correlating web page visits and conversions with external references Particular embodiments comprise a method for estimating the value of an organic marketing campaign. A computing device receives an identification of one or more entry pages associated with a website, as well as one or more keywords related to the entry pages. The computing device may determine conversion data, wherein the conversion data is based on traffic information identifying visits to at least one of the entry pages, and wherein the visits comprise organic referrals from a search engine. Using the keywords, the computing device may retrieve organic search results from the search engine, and then analyze the organic search results to determine rank positions of the entry pages. Finally, the computing device may identify a correlation between the rank positions of the entry pages, the conversion data, and the keywords.
US09262764B2	Modification of content representation by a brand engine in a social network A brand engine receives a request from a user device operated by a first user to display user information of a second user. User information of the first user is mapped to at least the user information of the second user by the brand engine. The mapping may map the user information of the first user to user information of further users in a social network. The mapping may map of any combination of spatial, temporal, social, and topical data related to the users. A modified representation of received content is generated by the brand engine based on the mapping. The modified representation is transmitted to the user device. The user device displays the modified representation for the first user. The modified representation of the received content may include any combination of filtered and/or sorted content items, recommended content items, and/or modified content items.
US09262762B2	System and method for processing fees for a card A processing system is operable for issuance and processing of cards with fee options applicable to a group of fee types. In one embodiment, the processing system includes a processing module, a secure card network, an issuer fee database and card account database. The card issuance database is operable to store a fee record associated with a card, wherein the fee record includes the fee options configured to apply to the group of fee types. The card account database is operable to store a card account record for the card, wherein the card account record includes a universal fee access counter for tracking parameters associated with the fee options configured to apply to the group of fee types.
US09262761B2	Time-varying security code for enabling authorizations and other uses of financial accounts A portable device is provided that carries account data. The account data may include a security code having a value that is time-varying. The value of the security code may be programmatically varied based on at least one of an algorithm or event. Authorization and use of the account may be sought from an authorization agent using the account data provided on the portable device.
US09262760B2	Fuel dispensing payment system for secure evaluation of cardholder data A system used in a retail environment for providing end-to-end encryption of payment cardholder data. An input device configured to receive cardholder data is operative to encrypt the cardholder data according to a first encryption method to produce first encrypted cardholder data. A cardholder data handling device is in electronic communication with the input device. A secure evaluation assembly (SEA) is operatively connected to the cardholder data handling device and comprises antitampering control electronics adapted to decrypt the first encrypted cardholder data to produce unencrypted cardholder data. The antitampering control electronics evaluate the unencrypted cardholder data to determine whether the unencrypted cardholder data is payment cardholder data or nonsensitive cardholder data. Finally, if the unencrypted cardholder data is payment cardholder data, the antitampering control electronics of the SEA are adapted to encrypt the unencrypted cardholder data according to a second encryption method to produce second encrypted cardholder data.
US09262754B1	Request tracking system and method A computer-implemented method for granting a user access to an on-line banking area of a website belonging financial institution responsive to receiving the valid user name and password. The method providing the user with account information regarding checking, savings, mortgage, home equity and/or loan accounts held by the user at the financial institution. The method grants the user access to a request tracking area of the website of the financial institution, receive request related data from the user, the request related data including data relating to at least one expense or goal, calculate portions of each expense respectively owed by each of a plurality of participants in the request and track whether a participant has paid. The method includes sending a message to at least one participant, the message requesting payment for the portion owed by the participant and receiving the payment from the participant in various payment forms.
US09262752B2	Attendee suggestion for events based on profile information on a social networking site A system and machine-implemented method for suggesting a user for an event within a social networking site is provided. The method includes receiving a social suggestion indication from a first user of the social networking site and determining, using the one or more computing devices, an event associated with the first user. The method also includes accessing a data structure storing a plurality of user models comprising social information of users, and comparing, using the one or more computing devices, the event with the plurality of user models, to determine a second user model from the plurality of user models, based on a predetermined criteria. The method further includes identifying a second user associated with the second user model, and generating a user suggestion identifying the second user.
US09262748B2	Identifying locations of potential user errors during manipulation of multimedia content Disclosed is a novel system and method for indicating a probability of errors in multimedia content. The system determines a user state or possible user distraction level. The user distraction level is indicated in the multimedia content. In one example, work is monitored being performed on the multimedia content. Distractions are identified while the work is being monitored. A probability of errors is calculated in at least one location of the multimedia content by on the distractions that have been identified. Annotations are used to indicate of the probability of errors. In another example, the calculating of probability includes using a function F(U,S,P) based on a combination of: i) a determination of user state (U), ii) a determination of sensitivity (S) of user input, and iii) a determination of user characteristics stored in a profile (P).
US09262746B2	Prescription of electronic resources based on observational assessments Various embodiments for prescribing electronic resources based on observational assessments are described. One example system includes a communication unit for sending and receiving data, a recommendation engine, and an assignment engine. The recommendation engine receives observation data related to a target subject, identifies one or more electronic resources that correspond to the observation data, and provides data describing the one or more electronic resources for display to an observer. The recommendation engine is coupled to the communication unit to provide the data representing the one or more electronic resources. The assignment engine receives an assignment request requesting an assignment of at least one electronic resource from the one or more electronic resources to the target subject for completion. The assignment engine also assigns the at least one electronic resource to the target subject. The assignment engine is coupled to the communication unit to receive the assignment request.
US09262745B2	Generating roles for a platform based on roles for an existing platform A computer-implemented method includes: receiving, using a computer system, first metadata portions regarding each of multiple first-platform roles defined for a first platform, each of the first-platform roles identifying at least one of multiple first-platform applications; generating, using the computer system, second-platform roles for a second platform, each of the second-platform roles corresponding to at least one of the first-platform roles; for each of the second-platform roles, accessing the first metadata portions for the corresponding at least one of the first-platform roles, and comparing, using the computer system, the accessed first metadata portions with second metadata portions assigned to multiple second-platform applications; and for each of the second-platform roles, assigning, using the computer system, at least one of the multiple second-platform applications to the second-platform role based on a match between at least one of the accessed first metadata portions and at least one of the second metadata portions.
US09262744B2	Efficient navigation of hierarchical data displayed in a graphical user interface Techniques are described for display and navigation of hierarchical messages, which displays include contextual data for the messages. Context information for a current message includes reply messages, parent messages, and metadata representations. Message representations are also associated with visual depth indicators that are independent of the text of the messages. Users may navigate displays of hierarchical message data using different navigational inputs. For example, more information may be requested for messages, without selecting a new message for viewing as a focal message, using swipes across portions of the display dedicated to displaying the messages. A limited number of messages for a requested list of messages is initially retrieved and displayed, and a mechanism for viewing more messages from the list is provided. Historical usage of the mechanism is recorded and the number of messages to be displayed for the list of messages is adjusted based on the historical usage data.
US09262742B2	User list identification Systems, methods, computer program products are provided for presenting content. An example computer implemented method includes identifying, by a data exchange engine executing on one or more processors, one or more user lists based on owned or permissioned data, each user list including a unique identifier; associating metadata with each user list including data describing a category for the user list, population data describing statistical or inferred data concerning a list or members in a given user list and subscription data including data concerning use of a given user list; storing in a searchable database a user list identifier and the associated metadata; and publishing for potential subscribers a list of the user lists including providing an interface that includes for each user list the unique identifier and the associated metadata.
US09262737B2	Intelligent cloning of a business object graph Embodiments of the present invention provide a method, system and computer program product for context sensitive cloning of a business object graph. In an embodiment of the invention, a method for context sensitive cloning of a business object graph is provided. The method includes selecting a business object of an application executing in memory of a computer for cloning and ascertaining a contemporaneous state of the selected business object. The method also includes applying a cloning rule to the state of the selected business object to determine a business object graph from amongst a set of pre-determined business object graphs to be used when cloning the selected business object. Finally, the method includes cloning the determined business object graph in the memory of the computer.
US09262736B2	System and method for efficient creation and reconciliation of macro and micro level test plans A method includes creating a macro plan for a test project, creating a micro plan for the test project, wherein the micro plan and the macro plan are based on at least one common parameter, and reconciling the macro plan and the micro plan by identifying deviations between the macro plan and the micro plan based on the at least one common parameter.
US09262735B2	Identifying and amalgamating conditional actions in business processes Methods and systems for identifying conditional actions in a business process are disclosed. In accordance with one such method, text fragments are extracted from input documents. In addition, a plurality of pairs of the text fragments that respectively include text fragments that are similar according to a pre-defined similarity standard are determined. For each pair of at least a subset of the pairs, at least one difference between the text fragments of the corresponding pair is determined. Further, at least two particular pairs of the subset of the pairs are merged in response to determining that the particular pairs have at least one of the determined differences in common. Additionally, the merged particular pairs are output to indicate the conditional actions in the business process.
US09262733B2	Job supporting apparatus, portable terminal and job supporting method A job supporting apparatus comprises a management section configured to manage a job schedule, containing a predetermined job content to be carried out by a person in charge and a work position at which the job content is performed, that is associated with respective portable terminal carried by each person in charge, a position specifying section configured to specify the position of the portable terminal, a first extracting section configured to extract a job schedule containing a work position corresponding to the location of the portable terminal specified by the position specifying section from the job schedules associated with the portable terminals, and a first notifying section configured to notify the job schedule extracted by the first extracting section to a portable terminal associated with the extracted job schedule.
US09262732B2	System and method of enterprise action item planning, executing, tracking and analytics A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.
US09262728B2	Auto insurance system integration An approach is provided for acquiring and integrating data into external services. According to the approach, image and/or video data and identification data are received from a client device. The image and/or video data includes one or more images and/or video data of an object that are acquired by the client device and the identification data is data that uniquely identifies the object. Record data is generated and stored that includes the identification data and at least a reference to the image and/or video data. The image and/or video data and the identification data are transmitted to an external service. This identification data allows an external service to associate the image and/or video data with other data maintained by the external service.
US09262727B2	Confidential content search engine A security compliance search engine is provided for searching one or more client computing devices for items of information that meet a security criteria identifying items of information containing confidential content. Results of the search are provided to an analysis engine for determining if the items of information identified by the search are being maintained in accordance with a security policy for ensuring the confidentiality of the confidential content. Results of the analysis may be used to generate a report or log and to generate a notification to the client computing device identifying any violations of the security policy and possible solutions for bringing the item of information into compliance with the security policy. In addition, an administrator may be notified of any violations so that corrective action may be taken.
US09262724B2	Low-rank matrix factorization for deep belief network training with high-dimensional output targets Systems and methods for reducing a number of training parameters in a deep belief network (DBN) are provided. A method for reducing a number of training parameters in a deep belief network (DBN) comprises determining a network architecture including a plurality of layers, using matrix factorization to represent a weight matrix of a final layer of the plurality of layers as a plurality of matrices, and training the DBN having the plurality of matrices.
US09262718B2	Systems and methods to predict a reduction of energy consumption A computing device for use with a demand response system is provided. The computing device includes a communication interface for receiving customer data of a plurality of customers, wherein the customer data includes a participation history and historical consumption values for each customer for participating in at least one demand response event. A processor is coupled to the communication interface and is programmed to select at least one customer from the plurality of customers by considering the participation history and the historical consumption values for each of the customers. The processor is also programmed to estimate a future reduction in energy consumption for the customer based on the customer data and to determine whether the estimated future reduction in energy consumption is substantially accurate.
US09262711B2	NFC tag, communication method and system A near field communication tag (101), comprises a first tag interface (107) for wireless near field communication with a first device (105), a second tag interface (113) for wired communication with a second device (103), a field detection section (119) for detecting a near field (109) for the wireless near field communication, a pin (121) connectable to the second device (103), wherein an output signal (127) is determined based on a result of the detecting of a near field (109) and the output signal (127) is provided to the pin (121), and an electronic storage (125) storing pin configuration information specifying the output signal.
US09262709B1	Electronic card readable by magnetic card readers An electronic card uses a magnetic stripe communication device in which either a horizontal magnetic field generator or a vertical magnetic field generator is selectively activated on a transaction specific basis as determined by the electronic card to transmit data to a magnetic reader to emulate a magnetic stripe.
US09262703B2	Image processing device An image processing device determines whether or not a data size per page of a received print job is greater than a preset threshold. When it is determined that the data size is greater than the threshold, the image processing device estimates a first RIP time per page, which is the time required to RIP process when a resolution of an image of the print job is not optimized, an optimization time per page, which is the time required to optimize, and a second RIP time per page when the resolution of the image of the print job is optimized. Then, the image processing device optimizes the resolution of the image of the print job on the basis of the first RIP time, the optimization time, and the second RIP time so that the rates of decreasing the resolution in each image after conversion are substantially the same.
US09262694B2	Dictionary learning device, pattern matching apparatus, method for learning dictionary and storage medium Provided is a technology which enables further improvement of the accuracy of the determination in the pattern matching processing. A dictionary learning device 1 includes a score calculation unit 2 and a learning unit 3. The score calculation unit 2 calculates a matching score representing a similarity-degree between a sample pattern, which is a sample of a pattern which is likely to be subjected to a pattern matching processing, and a degradation pattern resulting from a degrading processing on the sample pattern. The learning unit 3 learns a quality dictionary based on the calculated matching score and the degradation pattern. The quality dictionary is a dictionary which is used in a processing to evaluate a degradation degree (quality) of a matching target pattern of being pattern of an object on which the pattern matching processing is carried out.
US09262687B2	Image processing apparatus and method of operation of image processing appartus An image processing apparatus includes a feature value calculating section that calculates a feature value from an image picked up of a living mucous membrane, an extraction section that extracts a structure corresponding to the feature value, and a region division section that divides the structure into partial regions according to a predetermined condition.
US09262683B2	Image processing device, image processing method, and program There is provided an image processing device including an image input unit configured to input captured image data of a portion of parking stalls that are compartmented at least by a first side line extending in a first direction and a second side line extending in the first direction, an image processing unit configured to generate edge image data by performing an edge extraction process on the captured image data, and a parking determination unit configured to obtain an integrated value of edge pixels of the first direction portion corresponding to the parking stalls in each position of a second direction that is orthogonal to the first direction based on the edge image data, and then to determine whether or not vehicles are parked in the parking stalls based on the obtained integrated value of each position of the second direction.
US09262670B2	Adaptive region of interest This disclosure relates to adaptively determining and improving the quality of a region of interest in video content. A region inspection component inspects regions of an image. A detection component determines chroma values contained in the regions. A comparison component compares the chroma values against a set of predetermined chroma values, and determines, based on the comparison, a set of regions of interest in the frame. An encoder encodes the regions of interest in the image at a higher or better quality than a remainder of the image.
US09262668B2	Distant face recognition system A method and system for automatic face recognition. A primary and a plurality of secondary video cameras can be provided to monitor a detection area. The primary video camera can detect people present in the detection zone. Data can be then transmitted to a prioritizor module that produces a prioritized list of detected people. The plurality of secondary video cameras then captures a high-resolution image of the faces of the people present in the detection area according to the prioritized list provided by the prioritizor module. The high-resolution images can be then provided to a face recognition module, which is used to identify the people present in the detection area.
US09262662B2	Optical reading apparatus having variable settings A laser scanning indicia reading apparatus (1000) comprises one or more adjustable aperture assemblies (2024) for adjusting the diameter of a laser beam and adjustable lens assemblies (2026) for adjusting the distance of a laser beam waist (W).
US09262658B2	Read sensor and management system The present invention provides a read sensor that can acquire data from the read object reliably, with a simple configuration, by making it possible to acquire data from the read object using both a magnetic field and an electric field. A read sensor 10 has conductive elements 30 that have a shape in which first elements 31 and second elements 32 are connected with each other along a first plane 20a, as if drawn unicursally in one stroke, so that the angle θ1 formed between a first element 31 and a second element 32 becomes a predetermined sharp angle, and a metal plate 40 that covers a second plane 20b of the dielectric plate 20, which is the back plane of the first plane 20a.
US09262655B2	System and method for enhanced RFID instrument security A system and method for using an RFID read/write device to secure an RFID operable instrument or an RF communication is provided. The invention includes security databases in communication with a processor for storing and communicating security protocols to the RFID read/write device. The invention includes a method for restricting the unauthorized use of an RFID read/write device. The invention includes a subscription service for communicating user credentials to a certificate authority to obtain a counter security protocol. The invention also includes decrypting information stored on an RF operable device or transmitted via radio-frequency using counter security protocols.
US09262647B2	Information input display device and control program thereof An information input display device, having an input section for inputting information and a display section for displaying the information, which enables an access to protected information after being authenticated by an authentication processing executed after starting up of the information input display device, the information input display device including: an authentication processor which executes the authentication processing based on authentication information inputted by the input section; and an input display controller which, after the starting up of the information input display device and before being authenticated by the authentication processing, accepts inputting of prescribed information different from the authentication information through a screen displayed on the display section, and allows the display section to display the prescribed information on the screen.
US09262646B1	Systems and methods for managing web browser histories A computer-implemented method for managing web browser histories may include (1) identifying a website visited via a web browser, (2) selecting one or more website categories for which websites are not to be referenced in the web browser history, (3) querying a website categorization database to verify whether the visited website belongs to a selected website category, (4) receiving, in response to querying the website categorization database, an indication that the website belongs to a selected website category, and (5) blocking, based on the website belonging to a selected category, the website from being referenced in the web browser history. Various other methods, systems, and computer-readable media are also disclosed.
US09262645B2	Method and apparatus for privacy policy management Various methods are provided for determining run-time characteristics of an application at the time of installation and/or modification. Based on the determined run time characteristics, various methods control the installation and/or modification of the application based on a user privacy profile. One example method may comprise receiving a request to modify an application. A method may further comprise determining whether a conflict is present between the application and a user privacy profile. A method may further comprise causing the determined conflict and at least one conflict resolution to be displayed in an instance in which a conflict is determined. A method additionally comprises causing a user privacy profile to be modified in an instance in which an indication of acceptance is received in response to the displayed at least one conflict resolution.
US09262644B2	Server, recording medium, and image display system A server connectable to an apparatus providing contents and an image display apparatus includes an index information processing part configured to provide the image display apparatus with index information for causing a list of information items associated with the contents to be displayed by the image display apparatus, an image data processing part configured to provide the image display apparatus with image data for causing a content associated with an information item selected from the list to be displayed by the image display apparatus, and an apparatus authentication part configured to cause the index information processing part and the image data processing part to execute respective processes when the identification information of the image display apparatus that has requested to obtain the content associated with the selected information item by using access authority information regarding authority to access the content is managed in correlation with the access authority information.
US09262641B1	System and methods of providing data to a mobile computing device A system for authorizing data to be provided to a mobile computing device is provided. The system includes the mobile computing device and a server computer that includes a processor and a memory coupled to the processor, the memory including processor-executable instructions for performing the steps of storing, in the memory, parameters for authorizing data to be provided to the mobile computing device and determining at least one contextual cue associated with at least one of a task to be performed, the mobile computing device, and a user of the mobile computing device, wherein the at least one contextual cue is associated with the parameters. The processor-executable instructions also perform the steps of authorizing data to be provided to the mobile computing device when the at least one contextual cue aligns with the parameters and providing the data to the mobile computing device.
US09262640B2	Controlling access to resources based on affinity planes and sectors A first person (which may be a natural person, organization, brand, or other entity) has one or more affinity planes. Each affinity plane represents a distinct closeness of relationship with the first person. The first person also has one or more sectors, each of which may be associated with a domain. Each of the other people may be associated with zero or more of the first person's affinity planes and zero or more of the first person's sectors. Each of the first person's resources may be associated with zero or more of the first person's affinity planes and zero or more of the first person's sectors. A request by one of the other people to access one of the first person's resources is granted based on the overlap between the affinity planes and sectors associated with the requestor and the affinity planes and sectors associated with the requested resource.
US09262638B2	Hygiene based computer security A reputation server is coupled to multiple clients via a network. Each client has a security module that detect malware at the client. The security module computes a hygiene score based on detected malware and provides it to the reputation server. The security module monitors client encounters with entities such as files, programs, and websites. When a client encounters an entity, the security module obtains a reputation score for the entity from the reputation server. The security module evaluates the reputation score and optionally cancels an activity involving the entity. The reputation server computes reputation scores for the entities based on the clients' hygiene scores and operations performed in response to the evaluations. The reputation server prioritizes malware submissions from the client security modules based on the reputation scores.
US09262636B2	Method for neutralizing PC blocking malware using a separate device for an antimalware procedure activated by user The invention relates to the field of anti-virus protection. The technical result of the invention lies in providing possibility for unblocking the computer with no data loss and computer resetting, for increasing the antivirus systems operation efficiency and consequently improving the computer systems security. A method for neutralizing malicious software blocking computer operation, the method being performed by means of a separate antivirus activation device developed for the antimalware procedure activation to be run by a PC user, the device comprising connectors for connection to a control bus, a controller and an activation unit. Computer unblocking and malware neutralizing procedure is activated after receiving an activation signal from the antivirus activation device. Whereby said unblocking and malware neutralizing procedure includes: examining OS graphics subsystem state, searching for all the created windows and desktops viewed by the user; analyzing all the processes and flows executed with the PC at the time of infection; creating bindings on the collected data basis for each said window and desktop to a particular process and/or process hierarchy; analyzing the obtained data on the processes and identifying in each of them loaded modules involved in the process running; searching for the software automatically run in the course of OS start-up; compiling a list of the objects considered as malicious; isolating each malicious object, deleting its links out of OS configuration files, and aborting the malicious process produced by the object.
US09262635B2	Detection efficacy of virtual machine-based analysis with application specific events A computerized system and method is described for classifying objects as malicious by processing the objects in a virtual environment and monitoring behaviors during processing by one or more monitors. The monitors may monitor and record selected sets of process operations and capture associated process parameters, which describe the context in which the process operations were performed. By recording the context of process operations, the system and method described herein improves the intelligence of classifications and consequently reduces the likelihood of incorrectly identifying objects as malware or vice versa.
US09262633B1	Barcode reader with security features Indicia may include security threats that, when scanned by a barcode reader, may cause unwanted actions to be performed by a host device communicatively coupled to the barcode reader. To prevent these security threats from affecting the host device, security software running on a processor in the barcode reader or the host device compares the scanned data with items in a threat-signature library. Scanned data that match, at least part of, the threat signature library are blocked from being transmitted to the host device.
US09262630B2	System, method, and computer program product for isolating a device associated with at least potential data leakage activity, based on user support A system, method, and computer program product are provided for isolating a device associated with at least potential data leakage activity, based on user input. In operation, at least potential data leakage activity associated with a device is identified. Furthermore, at least one action is performed to isolate the device, based on user input received utilizing a user interface.
US09262624B2	Device-tailored whitelists A particular set of attributes of a particular computing device is identified. A first plurality of whitelisted objects is identified in a global whitelist corresponding to the particular set of attributes. A particular whitelist is generated to include the identified set of whitelisted objects, the particular whitelist tailored to the particular computing device. In some aspects, device-tailored updates to the particular whitelist are also generated.
US09262623B2	Anonymous shipment brokering A request is received for a brokered shipment from a particular entity to an anonymous user. A shipping identifier is obtained from a shipping entity, on behalf of the particular entity, for the shipment from the particular entity to the anonymous user. The shipping identifier is communicated to the particular entity and the shipping identifier is associated with a unique user identifier unique, within a system, to a pairing of the anonymous user with the particular entity. Address information of the anonymous user is unknown to the particular entity, and address information is obtained from the shipping entity for the anonymous user. In some aspects, address information of the particular user is received from a second entity and applied to the shipment identifier in connection with delivery of the shipment to the particular user.
US09262622B2	Secure connection between a data repository and an intelligence application Embodiments of the invention are directed to systems, methods and computer program products for establishing a secure connection between a data repository and an intelligence application. In one embodiment, a method includes receiving, from a user device and using a processing device, a request from the intelligence application, the request communicated from the intelligence application through a data virtualization application and for obtaining access to the data repository; responding, using the processing device, to the request comprising preparing and sending an authentication request through the data virtualization application to the intelligence application; receiving authentication credentials from the intelligence application through the data virtualization application, the authentication credentials associated with one or more users of a plurality of users authorized to access the data repository; determining that the authentication credentials are valid; and providing device, access to the data repository in response to validating the authentication credentials.
US09262621B1	Methods systems and articles of manufacture for implementing user access to remote resources Methods, systems, and articles of manufacture for implementing user access to remote resources residing on an external domain. Various implementations include authenticating and authorizing a user on a first system and receiving user request to access remote resources. The first system invokes processes or modules to initiate a new session to perform auto logon on behalf of the user on a second system by using stored user's credentials and subdomain delegation techniques without user intervention. The second system authenticates and authorizes this new session to allow user access to remote resources residing thereupon. The first system further prepares the user's system to take over the new session by setting cookie(s) and also by redirecting the URL so the user may continue to use the new session to access the desired remote resources residing on the second system.
US09262616B2	Simplified multi-factor authentication A reader element is associated with an identity verification element. The reader element has a biometric input device and is configured, through enrollment of a biometric element is used to encrypt a character sequence associated with the identity verification element. In a verification phase subsequent to the enrollment, a user may be spared a step of providing the character sequence by, instead, providing the biometric element. Responsive to receiving the biometric element, the reader element may decrypt the character sequence and provide the character sequence to the identity verification element.
US09262614B2	Image processing device, image processing method, and storage medium storing image processing program An image processing device includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute, acquiring a captured image; extracting a first feature amount and a second feature amount of a user included in the image, and a third feature amount indicative of a likelihood of a portion from which the second feature amount is extracted; generating an authentication table including a plurality of the first feature amounts, a plurality of the second feature amounts, and a plurality of the third feature amounts extracted from a plurality of the images; and selecting the third feature amount extracted at authentication of the user, and the first feature amount and the second feature amount included in the authentication table, based on the third feature amount included in the authentication table, and authenticating the user based on the first feature amount.
US09262609B2	Authentication frequency and challenge type based on environmental and physiological properties An apparatus and method are disclosed for determining authentication frequency (i.e., the length of time between authenticating and re-authenticating a user) and challenge type (e.g., username/password, fingerprint recognition, voice recognition, etc.) based on one or more environmental properties (e.g., ambient noise level, ambient luminosity, temperature, etc.), or one or more physiological properties of a user (e.g., heart rate, blood pressure, etc.), or both. Advantageously, the illustrative embodiment enables authentication frequency and challenge type to be adjusted based on the likelihood of malicious activity, as inferred from these properties. In addition, the illustrative embodiment enables the authentication challenge type to be tailored to particular environmental conditions (e.g., noisy environments, dark environments, etc.).
US09262607B1	Processing user input corresponding to authentication data A system and machine-implemented method for processing user input. User input by a user is received within a first input field. An authentication entry, for authenticating the user via a second input field, is accessed from a database. The received user input is compared with the authentication entry. Based on the comparison, a determination is made that the received user input matches the authentication entry. In response to the determination, a notification that the first input field is incorrect for the user input is provided.
US09262603B2	Advanced authentication technology for computing devices Receiving an input authentication pattern, the input authentication pattern including non-alphanumeric input data. Determining if the input authentication pattern matches a previously stored authentication pattern. Providing access to a computing resource if the input authentication pattern matches the previously stored authentication pattern.
US09262598B1	Digital rights management for applications This disclosure describes systems and associated processes that provide digital rights management for applications. In some embodiments, these system and processes couple DRM protection with individual applications, rather than with a centralized service. For instance, these systems and processes can be implemented in the context of an application store or distribution service that distributes applications for purchase or for free to user devices. Developers can submit applications to the application distribution service for distribution to end users. In response to receiving an application from a developer, the application distribution service can modify the application to include DRM features. The application distribution service can accomplish this modification without input from or the knowledge of the developer. The DRM features included in the modified application can prevent or otherwise reduce copying or modifying of the application.
US09262597B2	Validating normalized code representations A request that includes an indication of an execution context and data that represents executable code is obtained. An analysis of the data is initiated based on generating a first templatized representation of the executable code. A list of clearance indicators that indicate a blocking status associated with respective forms of templatized representations is accessed. A workflow policy is determined based on the accessing of the list of clearance indicators. The list of clearance indicators is updated, based on a result of the analysis of the data.
US09262595B2	Methods and systems for accessing licensable items in a geographic area Methods and apparatus for accessing licensable items unique to a geographic area via a wireless device are provided. The method and apparatus may include obtaining access to licensable items available in a first location of the wireless device. The methods and apparatus may further include downloading a licensable item. The licensable item is associated with a license providing the wireless device with a right to distribute the licensable item. The methods and apparatus may also include leaving a virtual copy of the licensable item in a second location of the wireless device different from the first location using the right to distribute.
US09262593B2	Client services for web-based applications A system for acquiring access to a web-based application includes one or more computer-readable storage media and an application (e.g., a web browser) for accessing and retrieving over a network a plurality of resources. The system also includes a program interface embodied on the one or more computer-readable storage media. The program interface is configured to present a common set of application program interfaces (APIs) that can be used by the application to demonstrate that a user of the application is entitled to access a first resource. The system also includes programming logic configured to determine if the user of the application is authorized to access the first resource. If it is determined that authorization has not been established to access the first resource, the application is directed to communicate with a marketplace to obtain authorization to access the first resource.
US09262591B2	Electronic state computing method, electronic state computing device, and recording medium A method for computing an exact solution for an electronic state of a substance by performing a first principle calculation using a computer, the method is characterized in that evaluating a deviation of an approximate value obtained by local density approximation or generalized gradient approximation from the exact solution of the electronic state to be obtained using an energy functional determined by an electronic density, a space derivative for the electronic density and fluctuations of physical quantities; and computing the exact solution by solving an optimization problem being defined by the energy functional.
US09262587B2	Systems and methods for collecting medical images Disclosed herein are systems and methods for collecting a plurality of medical images. According to one embodiment, a system may include an image acquisition unit to acquire image data, a processing unit to process the image data, a workflow unit to receive a selection of a primary workflow, and an insertion unit to suspend the workflow system. The insertion unit may receive a second selection of a secondary workflow. Upon the completion of the collection of the second plurality of medical images, the workflow unit may resume the collection of the first plurality of medical images. According to certain embodiments, the primary workflow or the secondary workflow may specify an order for collecting a primary and secondary plurality of medical images. Annotations may be added to the plurality of images based on the primary workflow and/or the secondary workflow.
US09262585B2	First time confirmation of database entry Provided is an apparatus that stores a formulary. The apparatus includes a memory device that stores the formulary, the formulary comprising a plurality of drug entries. A user input device allows a user to verify a drug of the plurality of drug entries of the formulary. A code reader interprets computer-readable codes. After a computer-readable code that is associated with the drug is read by the code reader, the drug is verified using the user input device.
US09262580B2	Support method and apparatus The disclosed method includes: first generating, from data of a plurality of parts that are string-shaped or band-shaped parts formed by end surfaces and side surfaces, first data including control point candidate data for control point candidates within the end surfaces, end surface data defining the end surfaces and path candidate data for path candidates between the control point candidates, for each of the plurality of parts; second generating second data of continuous shape paths representing continuous parts by searching the first data for parts having same control point candidate data and same end surface data; and third generating third data including data of control points determined on end surface portion of the parts and data of paths between the control points for the continuous shape paths and a group of the continuous shape paths from the first data and the second data.
US09262579B2	Integration of lithography apparatus and mask optimization process with multiple patterning process The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow.
US09262577B2	Layout method and system for multi-patterning integrated circuits A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.
US09262574B2	Voltage-related analysis of layout design data Disclosed are representative embodiments of methods, apparatus, and systems for voltage-related analysis of layout design data. According to embodiments of the disclosed technology, voltage association data objects are generated for drawn layers in a net of a layout design and voltage values or ranges of voltage values associated with the net are collected. The voltage values or ranges of voltage values are then associated with the voltage association data objects. A voltage-related analysis may be performed by searching the voltage association data objects according to a predetermined criterion.
US09262569B2	Balancing sensitivities with respect to timing closure for integrated circuits Systems and methods for improving timing closure of new and existing semiconductor products by balancing sensitivities. More specifically, a method is provided for that includes defining at least one set of correlated parameters for a semiconductor product, the at least one set of correlated parameters comprising a first parameter and a second parameter. The method further includes measuring performance of embedded devices within the semiconductor product. The method further includes closing timing of the semiconductor product using the measured performance of the semiconductor product. The closing the timing of the semiconductor product comprises calculating a sensitivity to the first parameter based on the measured performance of the embedded devices within the semiconductor product and balancing the sensitivity to the first parameter with a sensitivity to a second parameter such that timing degradation is shifted from the first parameter to the second parameter.
US09262564B2	Method of estimating damage to a roof A damage assessment module operating on a computer system automatically evaluates a roof, estimating damage to the roof by analyzing a point cloud of a roof. The damage assessment module identifies individual shingles from the point cloud and detects potentially damaged areas on each of the shingles. The damage assessment module then maps the potentially damaged areas of each shingle back to the point cloud to determine which areas of the roof are damaged. Based on the estimation, the damage assessment module generates a report on the roof damage.
US09262563B2	Methods and systems of modeling hydrocarbon flow from kerogens in a hydrocarbon bearing formation Modeling hydrocarbon flow from kerogens in a hydrocarbon bearing formation. At least some of the illustrative embodiments are methods including modeling flow of hydrocarbons through a hydrocarbon bearing formation by: obtaining an indication of kerogen-wet porosity of kerogen within a portion of the formation; obtaining an indication of water-wet porosity within the portion of the formation; modeling hydrocarbon movement through the kerogen-wet porosity; and modeling hydrocarbon movement through the water-wet porosity.
US09262560B2	Automatic recovery of reservoir simulation runs from processing system failures Reservoir simulation is performed for giant reservoir models in a parallel computing platform composed of a number of processor nodes. Automatic precautionary checkpoints are made at regular time intervals when computational time exceeds a preset value. The simulator receives and reacts to signals from a real time monitoring interface tool which monitors the health of the system. Checkpoints are also made done if a system problem which may cause a simulation job to fail is projected. The simulation job is subsequently restarted to continue simulation from the last checkpoint. The monitoring and automatic recovery are done automatically without need for user intervention.

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