| Document | Document Title |
|---|---|
| US09264237B2 |
Verifying requests for access to a service provider using an authentication component
The subject disclosure is directed towards processing requests for accessing a service provider. After examining at least one security token, a public key and a portion of attribute information are identified. An authentication component is accessed and applied to the public key. A unique user identifier is employed in generating the public key. The authentication component is generated using information from at least one revoked security token or at least one valid security token. The authentication component is configured to prove validity of the at least one security token. |
| US09264236B2 |
Embedded extrinsic source for digital certificate validation
A computer uses the information included within a digital certificate to obtain a current date and time value from a trusted source extrinsic to the computer. The computer requests and receives the trusted current date and time value and compares the trusted current date and time value to a validity period included in the digital certificate, to determine if the digital certificate is expired. The information included within the digital certificate specifying an extrinsic source for the current date and time value can be included in an extension of the digital certificate, and the information can specify a plurality of extrinsic sources. |
| US09264235B2 |
Apparatus, system and method for verifying server certificates
A device and method are provided for a device that authenticates a server over a network. The device and method are operable to contact the server to initiate a handshaking operation. The device receives certificate information and handshaking information from the server. The device completes the handshaking operations to establish the connection with the server. The device downloads the content from the server through the connection before authenticating the server to establish a secure connection. In some aspects, the device may display a portion of the downloaded content before the server is authenticated. |
| US09264232B2 |
Cryptographic device that binds an additional authentication factor to multiple identities
Binding a security artifact to a service provider. A method includes generating a pseudonym for a security artifact. The pseudonym is an identifier of the security artifact to the service provider that is unique to the service provider in that the pseudonym is not used to identify the security artifact to other service providers. Further, the pseudonym uniquely identifies the particular security artifact to the service provider even when a user has available a number of different security artifacts to authenticate to the same service provider to access a user account for the user. The method further includes providing the pseudonym for the security artifact to the service provider. The pseudonym for the security artifact is bound with a user account at the service provider for a user associated with the security artifact. |
| US09264229B1 |
System and method for generating random key stream cipher texts
A method for performing a cryptographic function on text to generate converted text comprises producing a random key stream having a first block size in a first frequency domain; converting the random key stream having a first block size in the first frequency domain to a random key stream in a second frequency domain; converting the random key stream having the first block size in the second frequency domain into smaller block sizes, thereby producing smaller block-sized random key stream of the second frequency domain; and converting the text using the smaller block-sized random key stream of the second frequency domain to produce the converted text. The frequency in the first frequency domain is preferably lower than the frequency in the second frequency domain. |
| US09264228B2 |
System and method for a secure display module
A system for a secure display module includes a display element array, a driver controller, a communication interface, a host controller and a cryptographic engine. The display element array includes one or more segments, and the driver outputs are configured to drive the one or more segments, respectively. The host controller is configured to send commands and data to the driver controller via the communication interface and the cryptographic engine is configured to encrypt communication data between the display element array and the host controller. |
| US09264218B2 |
Rising and falling edge detection and re-assembly for high speed serial data communications
A method according to one embodiment includes receiving a serialized data stream; detecting rising and falling edges in the serialized data stream; correlating the rising and falling edges to data values using a clock signal that is not derived from the serialized data stream; and converting the serialized data stream to a parallel data stream. In a further embodiment a system includes a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a serialized data stream; detect rising and falling edges in the serialized data stream; correlate the rising and falling edges to data values using a clock signal that is not derived from the serialized data stream; and convert the serialized data stream to a parallel data stream. |
| US09264216B1 |
Method for reducing power consumption when estimating timing errors in wireless signals
A method and apparatus for low power timing recovery is provided. In an embodiment, different gains are used to estimate timing errors during different portions of the data packet. In an embodiment, timing errors are only estimated during known sequences of a data packet. In further embodiments, errors are initially estimated independently in a first portion of the data packet in order to determine a phase shift between the errors. In the second portion of the data packet, the total error is derived from one estimated error and the phase shift between the errors. |
| US09264207B2 |
Control channel signaling using code points for indicating the scheduling mode
The invention relates to a control channel signal for use in a mobile communication system providing at least two different scheduling modes. Further the invention relates to a scheduling unit for generating the control channel signal and a base station comprising the scheduling unit. The invention also relates to the operation of a mobile station and a base station for implementing a scheduling mode using the control channel signal proposed by the invention. In order to facilitate the use of different scheduling schemes for user data transmission while avoiding an additional flag for indicating the scheduling mode in the control signaling, the invention proposes the use of code points in existing control channel signal fields. Further, the invention proposes a specific scheduling mode for use in combination with the proposed new control channel signal according to the invention. According to this scheduling mode control channel information is only provided for retransmissions, while initial transmissions are decoded using blind detection. |
| US09264205B2 |
Full duplex communication in the presence of mixed full and half duplex users
A method, an apparatus, and a computer program product for providing full duplex (FD) wireless communication to an FD capable (FDC) user equipment (UE) among one or more UEs include determining allocations of one or more resource blocks (RBs) to the one or more UEs, determining FD capabilities and scheduling parameters of the one or more UEs, determining at least one FD portion and at least one half duplex (HD) portion in the one or more RBs based on the FD capabilities and the scheduling parameters of the one or more UEs, wherein a concurrent downlink (DL) and uplink (UL) communication is scheduled in the at least one FD portion, and adjusting the allocations of the one or more RBs based on the at least one FD portion and the at least one HD portion. |
| US09264204B2 |
Method and apparatus for inter-cell interference coordination for transmission point group
The present invention relates to a wireless communication system, and more specifically to a method and an apparatus for inter-cell interference coordination for a transmission point group. The method for carrying out an interference coordination in a wireless communication system according to one embodiment of the present invention comprises a step for exchanging interference coordination messages between transmission point groups, wherein one transmission group comprises a plurality of transmission points, and the interference coordination message can comprises interference coordination information about each individual transmission point unit within the one transmission point group, and interference coordination information about the overall transmission point unit within the one transmission point group. |
| US09264203B2 |
Apparatus and method for signaling in a wireless communication system
A method of signaling in a wireless communication system (300) comprising a first network element (310) serving a wireless communication unit (325) with at least one packet data network (PDN) connection. The method comprises transmitting, by the first network element (310) to the wireless communication unit (325), a signaling message relating to a wireless communication unit (325) uplink (UL) PDN transmission, where the signaling message comprises a parameter indicative of at least one aggregate maximum bit rate (AMBR) value. |
| US09264200B2 |
Method and apparatus for transmitting a reference signal in a multi-antenna system
A method is described for transmitting, by a user equipment (UE), a demodulation reference signal (DMRS) for a physical uplink shared channel (PUSCH) in a wireless communication system. A cyclic shift field is received through a physical downlink control channel (PDCCH) from a base station. The cyclic shift field indicates first, second, third and fourth cyclic shifts, first orthogonal cover code (OCC) and a second OCC. A first DMRS sequences is generated by using the first cyclic shift and the first OCC. A second DMRS sequence is generated by using the second cyclic shift and the first OCC. A third DMRS sequence is generated by using the third cyclic shift and the second OCC. A fourth DMRS sequence is generated by using the fourth cyclic shift and the second OCC. The first, second, third and fourth DMRS sequences are transmitted to the base station. |
| US09264198B2 |
Methods and apparatus for employing different capabilities for different duplexing modes
Certain aspects of the present disclosure propose techniques for independently signaling features supported by a user equipment (UE) in different duplexing modes. The UE may be capable of communicating in frequency division duplexing (FDD) and time division duplexing (TDD) modes. The UE may obtain a FDD-specific feature group indicators (FGIs) set and a TDD-specific FGIs set, and signal at least one of the FDD-specific FGIs set or TDD-specific FGIs set. In addition, the UE may take one or more actions to reduce the likelihood of transitioning to a mode of operation that is different from its current mode of operation. |
| US09264195B2 |
Downlink signal transceiving method and device, in wireless communication system, taking into account antenna port relationship
The present invention relates to a wireless communication system, and more particularly, to a downlink signal transmission and reception method and device taking into account antenna port relationship. A method for the reception of a physical downlink shared channel (PDSCH) signal by a terminal in a wireless communication system, according to one embodiment of the present invention, can comprise: a step for determining a start symbol index for the PDSCH in a downlink subframe; and a step for receiving the PDSCH signal on the basis of the start symbol index. The PDSCH start symbol index (k) when the downlink subframe belongs to a specific subframe set is determined according to k=min(KThreshold, K), KThreshold being a prescribed threshold, K being the PDSCH start symbol index when the downlink subframe does not belong to the specific subframe set, and min(KThreshold, K) being the minimum value among KThreshold and K. |
| US09264192B2 |
Coordinated multi-point transmission and reception method in overlaid cell environment
According to the present invention, a method of performing coordinated multipoint transmission and reception in an overlaid cellular system in which a first base station and a second base station overlay each other, the method comprising performing a handover using a coordinated multi-point transmission and reception scheme based on Channel State Indicator-Reference Signal (CSI-RS) information of user equipment by the first and second base stations. |
| US09264189B2 |
Method and device for detecting downlink control information
A method and device for detecting DCI are provided. The method includes: obtaining intermediate data in DCI blind detection, the intermediate data including descrambled data, decoded data and detected RNTI values; determining data to be processed from the decoded data based on a matching result of the detected RNTI values and configured RNTI values; performing encoding, rate matching and modulation on the data to be processed to obtain modulated data; calculating confidence levels of the configured RNTI values based on the modulated data and the descrambled data; and when a maximum confidence level of the configured RNTI value is greater than a predetermined threshold of confidence level, determining that the data to be processed contains detected DCI. The probability of DCI misdetection may be reduced, and further the accuracy of uplink and downlink data on a mobile terminal and system stability may be ensured. |
| US09264184B2 |
Coordinated signaling of scheduling information for uplink and downlink communications
A coordinated signaling scheme for both uplink and downlink transmissions between a base station and a user terminal reduces the amount of time that the user terminal must turn on its receiver to listen for scheduling messages and ACK/NACK signaling. A scheduler at a base station aligns the transmission of downlink scheduling messages (e.g., downlink assignments) with uplink grants and ACK/NACK signaling for uplink transmissions. Aligning the downlink scheduling messages with uplink control signaling enables the user terminal to turn off its receiver for longer periods of time. |
| US09264179B2 |
Decision feedback equalizer for highly spectrally efficient communications
One or more embodiments describe a decision feedback equalizer for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include initializing values of tap coefficients of the DFE based on values of tap coefficients of a partial response filter through which said transmitted symbols passed en route to said sequence estimation circuit. The method may include receiving estimates of transmitted symbols from a sequence estimation circuit, and receiving an error signal that is generated based on an estimated partial response signal output by the sequence estimation circuit. The method may include updating values of tap coefficients of the DFE based on the error signal and the estimates of transmitted symbols. The method may include generating one or more constraints that restrict the impact of the error signal on the updating of the values of the tap coefficients of the DFE. |
| US09264173B2 |
Method for jamming communications in an open-loop-controlled network
A method for optimizing the jamming of P predefined zones or positions in a communications network of transmitters, jammers and receivers comprising several platforms, uses a local reception situation at the level of each friendly platform, a local jamming situation at the level of each friendly reception platform, and determines for each friendly transmitting platform and each friendly receiving platform, one or more parameters so as to minimize or to eliminate the fratricidal effects on the friendly reception platforms. |
| US09264171B2 |
Multi-mode fiber-based optical transmission/reception apparatus
An optical transmission apparatus includes: a transmission light source configured to generate single-mode light of a specific wavelength; a power coupler configured to split the light generated by the transmission light source into a plurality of light sections; at least one modulator configured to modulate an electrical signal carrying different data into at least one optical signal using the light section from the power coupler; and a mode multiplexer configured to convert the modulated optical signal into a different mode, and to transmit the mode-converted optical signal to a fiber. |
| US09264167B2 |
Optical add drop multiplexer
An optical add-drop multiplexer having first and second routes includes: an optical cross connect; a first multiplexer optically coupled to a plurality of output ports of the optical cross connect; a second multiplexer optically coupled to a plurality of other output ports of the optical cross connect; a first wavelength selective switch to generate a first WDM optical signal including an optical signal output from the first multiplexer and to guide the first WDM optical signal to the first route; and a second wavelength selective switch to generate a second WDM optical signal including optical signal output from the second multiplexer and to guide the second WDM optical signal to the second route. |
| US09264166B2 |
Method and device for processing data and communication system comprising such device
A method and a device are provided for processing first data, wherein said first data are distributed, in particular temporally spread over and/or on top of second data. In addition, a communication system comprising such device is suggested. |
| US09264161B2 |
Wireless fire system with idle mode and gateway redundancy
A method and apparatus that includes the steps of providing a plurality of wireless nodes including at least one parent node and at least one child node, a control panel sending instructions to and receiving data from the plurality of nodes through a primary gateway and a wireless subsystem of the gateway, the primary gateway synchronizing the plurality of nodes by periodically transmitting a synchronization signal and one of the plurality of nodes detecting failure of the gateway and transmitting an idle synchronization signal for so long as the one of the plurality of nodes detects failure of the gateway. |
| US09264150B2 |
Reactive metal optical security device and methods of fabrication and use
A reactive metal optical security device for implementation in an optical network and/or system to provide a mechanism for disrupting the optical network and/or system. The security device includes a mirror comprising a reactive metal stack and configured to reflect an optical signal and receive an electrical signal. The security device further includes a semiconductor chip configured to send the electrical signal to the mirror. |
| US09264147B2 |
Method and apparatus for phase shift keyed optical communications
A burst-mode phase shift keying (PSK) communications system according to an embodiment of the present invention enables practical, power-efficient, multi-rate communications between an optical transmitter and receiver. Embodiments may operate on differential PSK (DPSK) signals. An embodiment of the system utilizes a single interferometer in the receiver with a relative path delay that is matched to the DPSK symbol rate of the link. DPSK symbols are transmitted in bursts, and the data rate may be varied by changing the ratio of the burst-on time to the burst-off time. This approach offers a number of advantages over conventional DPSK implementations, including near-optimum photon efficiency over a wide range of data rates, simplified multi-rate transceiver implementation, and relaxed transmit laser line-width requirements at low data rates. |
| US09264143B2 |
Method and system for split voltage domain receiver circuits
Methods and systems for split voltage domain receiver circuits are disclosed and may comprise amplifying complementary received signals in a plurality of partial voltage domains, and combining the amplified received signals, utilizing a stacked cascode amplifier for each domain, into a single differential signal in a single voltage domain. The stacked cascode amplifiers may comprise a feedback loop having a comparator which controls a current source in each domain. The complementary signals may be received from a photodiode, which may be integrated in the integrated circuit. The amplified received signals may be combined via stacked common source or common emitter amplifiers. The received signals via may be amplified by stacked inverters. The amplified received signals may be AC or DC coupled prior to the combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked and may be controlled by feedback loops. |
| US09264142B2 |
RZ optical modulator and RZ optical modulation method
In an optical transmission system using an RZ code, in order to improve the quality of the modulated transmission signal, an RZ optical modulator includes an RZ carver that outputs a optical pulse train of the RZ code, a polarization adjustment device which improves and outputs a polarization extinction ratio of optical pulse train outputted from the RZ carver and an optical modulator which modulates and outputs the optical pulse train outputted from a polarization adjustment device. |
| US09264141B2 |
Multi-domain scheduling for subordinate networking
Multi-domain scheduling for subordinate networking is contemplated. The scheduling may include controlling a terminal to facilitate interfacing an Internet Protocol (IP) network with a point-to-multipoint (P2MP) network where the P2MP network includes one or more aggregating devices to facilitate interfacing signaling with devices/units associated with one or more subordinate P2MP networks. |
| US09264140B2 |
Transmission method, transmission equipment and transmission system
A transmission method that transmits an optical signal via a plurality of virtual lanes in dual polarization or multi-level modulation includes: receiving a first frame signal of a first frequency and a second frame signal of a second frequency, and storing the first and second frame signals on a memory; reading out the first frame signal from the memory at a third frequency, and inserting a stuff into the first frame signal such that a difference between the first frequency and the third frequency is adjusted to generate a third frame signal; reading out the second frame signal from the memory at the third frequency, and inserting a staff into the second frame signal such that a difference between the second frequency and the third frequency is adjusted to generate a fourth frame signal; and transmitting the third and fourth frame signals respectively via different virtual lanes. |
| US09264137B2 |
Rapid in-the-field auto-alignment for radio frequency and free-space optical data communication transceivers
A local communications apparatus is aligned with a remote apparatus, each apparatus comprising radio frequency (RF) and free space optical (FSO) transceivers with substantially parallel boresight. Coarse alignment is performed using the RF transceiver and fine alignment is performed using the FSO transceiver. A patterned search is performed to locate the RF signal from the remote apparatus and known features of the intensity profile are utilized to locate the global maximum, thus coarsely aligning the pair of apparatuses. A second patterned search is performed to locate the FSO signal from the remote apparatus and an iterative step-search is used to align the FSO signal centroid with the FSO transceiver, thus finely aligning the pair of apparatuses. |
| US09264133B2 |
Network traffic monitoring apparatus for monitoring network traffic on a network path and a method of monitoring network traffic on a network path
A network traffic monitoring apparatus and method of monitoring network traffic on a network path is disclosed. The apparatus comprises a first path arranged to receive a portion of the network traffic from the network path and a monitoring port arranged to monitor the portion of network traffic. The apparatus further comprises a switch having an input port communicatively coupled to the first path, and an output port communicatively coupled to the monitoring port. The switch is arranged to selectively toggle between the first state in which the portion of network traffic can pass from the input port to the output port and a second state, in which the portion of network traffic is prevented from passing from the input port to the output port, in dependence of a switching signal. The apparatus further comprises a second path for communicating a monitoring status signal to a network device. |
| US09264132B2 |
Universal asymmetry compensation for packet timing protocols
The notion of a “PTP aware” path is one current proposed approach to reduce asymmetry effects. In a fully PTP aware path there is the notion of on-path support mechanisms such as boundary clocks and transparent clocks at every switching or routing node. However, on-path support methods only address time-transfer errors introduced inside network elements and any asymmetry in the transmission medium, such as, for example, the fiber strands for the two directions of transmission, cannot be compensated for by on-path support mechanisms. Furthermore, in a real operational network, which may traverse different operational domains administered by different entities, full on-path support is a difficult challenge. In certain managed network scenarios full on-path support can be contemplated. Nevertheless, the universal asymmetry compensation method described herein mitigates the asymmetry in a network path, without requiring on-path support mechanisms such as transparent clocks and boundary clocks. |
| US09264123B2 |
Antenna activity detection in multi-antenna communication
The present subject matter discloses a method for antenna activity detection in multi-antenna communication devices. In one embodiment, the method comprises computing a received signal strength indicator (RSSI) value for each of a plurality of antennas based on a sampled data associated with each of the antennas. The RSSI values may then be analyzed to identify an antenna having a highest RSSI value as a primary antenna and one or more antennas having the RSSI value less than the highest RSSI value as auxiliary antennas. Further, an RSSI difference for each of the auxiliary antennas is calculated and compared with a first threshold value to ascertain one or more potentially inactive antennas from among the auxiliary antennas. The potentially inactive antennas may then be further analyzed to identify one or more inactive antennas based at least in part on the RSSI value. |
| US09264122B2 |
Training-based channel estimation for multiple-antennas
The burden of designing multiple training sequences for systems having multiple transmit antennas, is drastically reduced by employing a single sequence from which the necessary multiple sequences are developed. The single sequence is selected to create sequences that have an impulse-like autocorrelation function and zero cross correlations. A sequence of any desired length Nt can be realized for an arbitrary number of channel taps, L. The created sequences can be restricted to a standard constellation (that is used in transmitting information symbols) so that a common constellation mapper is used for both the information signals and the training sequence. In some applications a training sequence may be selected so that it is encoded with the same encoder that is used for encoding information symbols. Both block and trellis coding is possible in embodiments that employ this approach. |
| US09264121B2 |
Efficient utilization of control channels in a communication system
A method and arrangement in a first node (110) for sending feedback data on a feedback channel (121) to a second node (111) is provided. The feedback data is indicative of channel properties of a data channel (120) for sending data from the second node (111) to the first node (110). A wireless MIMO communications system (100) comprises the first and second nodes (110, 111). The first node (110) sends (420), in a time period of the feedback channel (121), feedback data comprising a first rank indicator of the data channel (120). Furthermore, the first node (110) sends additional data (212, 242) being independent of the first rank indicator in the time period. Moreover, a corresponding method and arrangement in a second node (111) for receiving feedback data on a feedback channel is provided. |
| US09264118B1 |
System and method for communicating data symbols via wireless doubly-selective channels
A method for decoding data symbols modulated with a corresponding codeword from a constellation set of codewords expands the constellation set of codewords with a set of basis functions to produce a basis-expanded constellation set and projects projecting a received modulated data symbol onto orthogonal complements of the basis expanded constellation set to obtain a set of distance metric of a generalized likelihood ratio test (GLRT) for each codeword of the constellation set. The set of basis functions includes a Fourier exponential basis function in a frequency domain, a Legendre polynomial basis function in a time domain, and a Fourier-Legendre product basis function in the frequency domain. The method selects a codeword corresponding to a minimal distance metric or a maximal correlation metric and decodes the data symbol from the received modulated data symbol using the codeword. |
| US09264117B2 |
Rank and PMI in download control signaling for uplink single-user MIMO (UL SU-MIMO)
A method of operating a user equipment device includes extracting at least one rank indicator (RI) from an uplink grant, and adapting a transmission rank in response to said RI. At least two transmit antennas are configured to transmit according to said transmission rank. |
| US09264115B2 |
Wireless communication system for high-speed moving object that moves along fixed route
The present invention relates to a method in which a signal is transmitted between a base station and a terminal in a multi-antenna wireless communication system. The method transmits pre-estimated channel information to the terminal when the terminal moves to a specific position when channel estimation for a specific position is performed. As for the terminal which moves along a fixed route or the route of which can be estimated, the position of the terminal in the near future can be easily detected. Therefore, the transception of channel information can be performed in a more efficient manner in consideration of the above-described special environment. |
| US09264109B2 |
Detection of change in generated magnetic field due to tag-loading
The invention concerns a Near Field Communication method comprising a step (1) of generating, by an antenna of a transmitter, a magnetic field (H), a step (2) of receiving, by an antenna of a tag, power from the generated magnetic field (H), then causing a drop in the generated magnetic field (H), wherein the method further comprises a step (3) of estimating the drop by sensing a voltage swing across said transmitter antenna. |
| US09264106B2 |
Method for controlling flows of logical link layer in near field communication software stack
A method for controlling flows of a logical link layer in a near field communication (NFC) software stack includes steps of: arranging a Send Window and a Receive Window in the logical link layer for controlling flows of transmitted data frames; adjusting the size of the Send Window and the size of the Receive Window according to a transfer rate determined based on upper-layer application, communication delay time determined based on channel quality, and the size of a data frame; and controlling flows of the output terminal according to the size of the Send Window, and controlling flows of the input terminal according to the size of the Receive Window. |
| US09264104B2 |
Sharing of information common to two mobile device users over a near-field communication (NFC) link
A method for exchanging information between two communication devices includes communicating first identity information from a first communication device to a second communication device over a short-range communication link in response to an event. A second identity is received from the second communication device over the short-range communication link. The first identity information identifies a user of the first communication device and the second identity information identifies a user of the second communication device. Based on the first and second identity information, information is obtained specifying at least one attribute of the first and second users that they have in common. |
| US09264102B2 |
Trace canceller with equalizer adjusted for trace length driving variable-gain amplifier with automatic gain control loop
Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line. |
| US09264101B2 |
Communication system with proactive network maintenance and methods for use therewith
A transmitter for use in a cable modem termination system includes a data processing module that generates a plurality of OFDM symbols from a data packet. A probe symbol generator generates a probe symbol, as one of a plurality of probe symbol types. The probe symbol is selectively inserted within the plurality of OFDM symbols, at a pre-defined probe symbol interval. |
| US09264099B1 |
Frequency-block hopping
A method (of operating an end node) includes: wirelessly receiving an instance of a non-hopping beacon signal, B, periodically-transmitted from a central node; interpreting a frequency-block hopping guide (FBHG) according to FN(i) and IDCN thereby to determine a corresponding set, CSET(i), of at least two channels available to the end node for transmission, respectively, during frame FN(i); selecting, at least pseudo-randomly, at least one channel amongst the set CSET(i); and wirelessly transmitting at least one message from the end node using the at least one selected channel, respectively. Each instance B(i) includes: a corresponding frame number, FN(i); and an identification, IDCN, of the central node. The FBHG establishes: a total of L frames; a set of channels CSET for each frame, respectively; and that, for any two consecutive ones of the L frames, FN(j) and FN(j+1), the corresponding sets CSET(j) and CSET(j+1) will be different, CSET(j)≠CSET(j+1). |
| US09264098B2 |
Process for finger insertion and removal in a rake receiver and receiver for carrying out the process
Process of assignment and deallocation of a correlation unit or finger of a rake receiver intended to treat a received signal of a wireless communication system characterized in that the assignment of a finger is ordered by a CPICH detector operating on the level of the frame of said signal and in that the deallocation of the same finger is controlled by the analysis of a criterion derived from the RSCP indicator calculated on the level of a slot of said signal.The invention also achieves a rake receiver for the implementation of the process. |
| US09264097B2 |
Interference mitigation for downlink in a wireless communication system
Techniques for mitigating interference in a wireless communication system are described. In an aspect, pertinent transmission parameters for a served UE may be sent to at least one interfered UE to support interference mitigation. In one design, information for at least one transmission parameter for a data transmission sent by a first cell to a first UE may be transmitted to at least one UE served by a second cell to enable the at least one UE to perform interference mitigation for the data transmission sent by the first cell to the first UE. The information may be transmitted by either the first cell or the second cell. In another aspect, a cell may send transmission parameters for a UE via a pilot. In yet another aspect, scrambling may be performed by a cell at symbol level to enable an interfered UE to distinguish between modulation symbols of desired and interfering transmissions. |
| US09264096B2 |
Receiver
Disclosed herein is a receiver including: a first mixer adapted to mix satellite signals from first and second satellites and a first local oscillation signal so as to convert a carrier frequency of the satellite signals into a lower first intermediate frequency; a second mixer adapted to mix a satellite signal of the second satellite frequency-converted by the first mixer and a second local oscillation signal so as to convert the first intermediate frequency of the frequency-converted satellite signal from the second satellite into an even lower second intermediate frequency; and a first frequency divider adapted to generate the second local oscillation signal by dividing a frequency of the first local oscillation signal. |
| US09264095B2 |
Ultra-wideband signal amplifier
Amplifier for an ultra-wideband (UWB) signal receiver having a signal input (15) for receiving an ultra-wideband signal which is sent by a transmitter (1) and which is transmitted in a sequence of transmission channels (K.sub.i) (which each have a particular frequency bandwidth) which has been agreed between the transmitter (1) and the receiver (4); a transistor (18) whose control connection is connected to the signal input (15); a resonant circuit (26, 30, 31) which is connected to the transistor (18) and whose resonant frequency can be set for the purpose of selecting the transmission channel (K.sub.i) in line with the agreed sequence of transmission channels; and having a signal output (29) for outputting the amplified ultra-wideband signal, the signal output being tapped off between the transistor (18) and the resonant circuit. |
| US09264091B2 |
Mixer unit
A mixer unit (30) for frequency translating, based on an LO signal, an input signal having one or more input signal components is disclosed. The mixer unit has a signal processing path (50a-d, 60a-d) from each Input terminal (32+, 32−) to each output terminal (34_I+, 34_I−, 34_Q+,34_Q−) of the mixer unit (30), The LO signal has an associated LO signal component (LO_Ia-d, LO_Qa-d) for each signal processing path. The mixer unit (30) comprises a plurality of mixer switches (70a-N) and a control unit (90). The control unit (90) is adapted to, for each signal processing path (50a-d, 60a-d), dynamically select an associated subset, in the following denoted active switch subset, of the plurality of mixer switches (70a-N) for operation in the signal processing path (50a-d, 60a˜d) such that which of the plurality of mixer switches (70a-N) belong to said active switch subset varies in time. At any instant in time, the union of all the active switch subsets is a strict subset, denoted combined active subset, of the plurality of mixer switches (70a-N). The control unit (90) is further adapted to activate only the mixer switches (70a-N) in said combined active subset by, for each mixer switch (70a-N) in the combined active subset, supplying the corresponding LO signal component to the mixer switch. A related radio receiver circuit (10), a related radio communication apparatus (1, 2), and a related method are also disclosed. |
| US09264090B2 |
Metallic protective case for electronic device
A metallic protective case for an electronic device having an antenna structure includes a first metallic case element and a second metallic case element. The first metallic case element includes at least two metallic case portions joined to each other by a first set of electrical insulators and also includes a lip. The second metallic case element is hingedly attached to the first metallic case element to form a hinged enclosure having an open position and a closed position. The hinged enclosure is adapted to receive the electronic device when in the open position and at least partially enclose the electronic device when in the closed position. The second metallic case element includes at least two metallic case portions joined to each other by a second set of electrical insulators, a first latch portion, and a second latch portion. |
| US09264078B2 |
Transmitter with quantization noise compensation
The invention discloses a transmitter comprising a pulse encoder for creating pulses from the amplitude of an input signal to the transmitter, a compensation signal generator for cancelling quantization noise caused by the pulse encoder, a mixer or I/Q modulator for mixing an output of the pulse encoder with the phase of an input signal to the transmitter and an amplifier for creating an output signal from the transmitter. In the transmitter, a control signal (CA) for controlling a function of the amplifier comprises an output signal from the compensation signal generator, and an input signal to the amplifier comprises an output from the mixer having been modulated to a desired frequency. |
| US09264075B2 |
Dynamic buffer partitioning
At least one implementation herein enables interleaver and deinterleaver buffer modification during Showtime. That is, at least one implementation herein enables a multicarrier controller apparatus to reallocate interleaver and deinterleaver buffer memory to accommodate data rate changes in the upstream and downstream communication channels. |
| US09264072B2 |
Encoding apparatus and communication apparatus
According to one embodiment, an encoding apparatus includes an encoding unit. The encoding unit encodes a data bit sequence to generate a codeword corresponding to a parity check matrix. The parity check matrix is based on a protograph. In the protograph, each of n check nodes of a first type is connected to n variable nodes of a first type by a total of at least one edge of a first type, and to n variable nodes of a second type by a total of at least two edges of a second type. In the protograph, each of n check nodes of a second type is connected to the n variable nodes of the second type by a total of r edges of a third type, and to n variable nodes of a third type by a total of g edges of a fourth type. |
| US09264071B2 |
Applying forward error correction in 66B systems
A method and apparatus for applying Forward Error Correction (FEC) in 66b systems. For a user data, the apparatus uses a method comprising the steps of generating one or more data blocks using a 66b code format and the user data; generating one or more FEC parity blocks using the 66b code format, wherein the parity is calculated over the data blocks; and generating an FEC codeword using the data blocks and the FEC parity blocks. |
| US09264062B1 |
Digital-to-analog converter circuit
A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current. to the second sub digital to analog converter The digital to analog converter is configured to operate in a second mode for generating a ramp wave with a second bit level accuracy and, when in the second mode, the overlap adjustment circuit adds current to the second sub digital to analog converter. When in the second mode, the total current of the second sub digital to analog converter and the overlap converter is greater than one of the plurality of currents generated by the first sub digital to analog converter. |
| US09264061B2 |
Apparatus and method for generating sinusoidal waves, and system for driving piezoelectric actuator using the same
An apparatus for generating sinusoidal waves may includes a look-up table storage unit including a plurality of sampling points with respect to a base frequency, a waveform-synthesizing unit calculating an integer ratio between an input target frequency and the base frequency and loading at least some of the plurality of sampling points from the look-up table storage unit according to the integer ratio, a correction unit substituting a digital value of at least one sampling point among the sampling points loaded from the look-up table with a digital value of a sampling point among the plurality of sampling points included in the look-up table storage unit having a maximum value, and a sinusoidal generation unit generating sinusoidal waves using the sampling points changed by the correction unit. |
| US09264058B1 |
Analog-to-digital converting device and related calibration method and calibration module
An analog-to-digital converting device includes a converting module for sampling an input voltage according to a plurality of sampling signals, to generate a comparing signal; a control module, for adjusting the plurality of sampling signal according to the comparing signal, to generate a first digital signal corresponding to the input voltage and a plurality of weights; and a calibration module, for adjusting the plurality of sampling signal according to the first digital signal to make the control module generate a second digital signal and for adjusting the plurality of weights according to the first digital signal and the second digital signal; wherein the second digital signal is different from the first digital signal and is corresponding to the plurality of weights. |
| US09264054B1 |
DLL lock detector
An apparatus includes a lock detect circuit configured to receive a phase detect signal and generate a lock signal according to the phase detect signal. The phase detect signal is a single bit signal having a first value or a second value. A method includes receiving a phase detect signal using a lock detect circuit, and generating a lock signal according to the phase detect signal. The phase detect signal is a single bit signal having a first value or a second value. |
| US09264053B2 |
Variable frequency charge pump
A charge pump circuit that utilizes a sensing circuit for determining the current loading or status of the output supply generated by the charge pump circuit to determine a corresponding frequency for a variable rate clock for the charge pump circuit. When a current load is present, the clock frequency automatically ramps up to a relatively high level to increase the output current of the charge pump circuit. When the current load is removed and the supply is settled out, the clock frequency is automatically reduced to a relatively quieter level and the charge pump circuitry operates at a lower power level. Accordingly, the charge pump circuit is only noisy when it has to be, thus providing optimal power when required and being electrically quiet and operating at lower power at all other times. |
| US09264050B2 |
Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated measure initialization circuitry
Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element. |
| US09264049B2 |
Synchronous on-chip clock controllers
A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses. |
| US09264046B2 |
Resonant inductor coupling clock distribution
The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal. |
| US09264041B2 |
Digital control device for a parallel PMOS transistor board
A digital control device for a parallel PMOS transistor board, includes: an operative memory for digitally storing error data between a target voltage and a setpoint voltage as well as control data, each datum being provided with a time marker, a digital selected order filter (36) for computing setpoint incrementation data from error data in the operative memory selected based on input error data, and for storing the input error data with a corresponding time marker in the operative memory, and a control computer (38) for computing new control data from the control incrementation data and control data in the operative memory selected based on input error data and for storing the new control data in the operative memory. |
| US09264040B2 |
Low leakage CMOS cell with low voltage swing
A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit. |
| US09264031B2 |
Rail-to-rail input hysteresis comparator
A rail-to-rail input hysteresis comparator includes: an input hysteresis comparator module, a transmission module, an output comparator, a switching signal module and a bias module. Compared to the conventional device, the rail-to-rail input hysteresis comparator of the present invention can turn off an output of the N-type input hysteresis comparator of the input hysteresis comparator module when the common mode input voltage is relatively low and turn off an output of the P-type input hysteresis comparator of the input hysteresis comparator module when the common mode input voltage is relatively high, thereby avoiding operating in a linear mode and hence achieving a stable CMRR. |
| US09264028B2 |
Zero crossing detector using current mode approach
An apparatus includes a signal converter configured to convert a voltage signal into a current signal and an analog digital converter (ADC) configured to convert the current signal to a digital signal. The apparatus also includes a digital processor configured to process the digital signal and generate an output signal that indicates a zero crossing point of the mains voltage signal. |
| US09264027B1 |
Process compensated delay
A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility. |
| US09264024B2 |
Apparatus and method of correcting output characteristics in a power combination apparatus
An apparatus and a method of correcting output characteristics in a power combination apparatus are provided. The method includes synchronizing Digital UpConverters (DUCs) included in a plurality of power amplifiers, adjusting a fine delay between signals outputted by the DUCs based on a Frequency Assignment (FA), combining fine delay-compensated signals output from the plurality of power amplifiers, and outputting the combined signal. |
| US09264021B1 |
Multi-bit flip-flop with enhanced fault detection
A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch. |
| US09264019B2 |
Suppression of fixed-pattern jitter using FIR filters
FIR filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component, with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the output signal. In another embodiment, a FIR filter includes a delay line with a total delay longer than the period of the jitter. A signal is passed down the delay line, the number of signal edges that have occurred as the signal passes each delay element in the counted. Drivers corresponding to the delay elements in which a number of signal edges occur at the desired frequency during the period of fixed pattern jitter activate impedance elements attached to those delay elements. A processor configures the activated impedance elements to provide the desired filter response. |
| US09264017B2 |
Electronically tunable filter
An electronically tunable filter (ETF) and systems comprising an ETF are disclosed herein. The ETF comprises: a first image rejection mixer; a second image rejection mixer; a first hybrid coupler, the first hybrid coupler being coupled to the first image rejection mixer; a second hybrid coupler, the second hybrid coupler being coupled to the second image rejection mixer; an internal filter coupled to the first hybrid coupler and the second hybrid coupler; a control port for receiving a control signal; a power splitter coupled to the control port, the first image rejection mixer, and the second image rejection mixer; a first port coupled to the first image rejection mixer; and a second port coupled to the first image rejection mixer. |
| US09264016B2 |
Piezoelectric component having a cover layer including resin that contains translucent filler
A piezoelectric component includes a piezoelectric element that includes: a piezoelectric plate; a comb-shaped electrode and an input/output electrode on a principal surface of the piezoelectric plate; a cover layer disposed above the comb-shaped electrode; and a rib to form a void between the comb-shaped electrode and the cover layer. The cover layer includes a photosensitive thermosetting resin in which translucent filler is contained. |
| US09264012B2 |
Radio frequency signal splitter
Disclosed is a signal splitter that includes a coupled transmission line element coupled between two output ports of the signal splitter. The coupled transmission line element is used to lower the isolation between the two output ports for a particular frequency band. The coupled transmission line element includes a first and a second elongate electrical conductor. The first and the second elongate electrical conductor first ends are coupled to the signal transmission path that connects the two output ports. The first and the second elongate electrical conductor second ends are un-terminated. The first elongate electrical conductor and the second elongate electrical conductor are not shorted together, and the first elongate electrical conductor and the second elongate electrical conductor are electrostatically coupled, such as by twisting them together into a helix. |
| US09264010B2 |
Via structure having open stub and printed circuit board having the same
The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided. |
| US09264000B2 |
Versatile audio power amplifier
An audio power amplifier includes a first and a second amplification unit, each including a switching voltage amplifier, an output filter, a current compensator, an inner current feedback loop feeding a measurement of current measured at the output inductor back to a summing input of the current compensator, a voltage compensator coupled to the summing input of the current compensator, and an outer voltage feedback loop. A controlled signal path provides the output of the voltage compensator of the first amplification unit to the current compensator of the second amplification unit. The first and second amplification units are operable with separate loads, in parallel driving a common load, or across a bridge-tied-load. A second pair of amplification units may be added and operated together with the first pair to drive a single speaker with a parallel pair of amplifiers on each side of a bridge-tied-load. |
| US09263998B2 |
Broadband single-ended input to differential output low-noise amplifier
A low-noise amplifier accepts a single-ended input signal at an input port and provides a differential output signal at an output port. Each of a pair of transistors in the amplifier has a pair of input terminals and a pair of output terminals that share a common terminal. A feedback circuit is electrically connected between the non-common output terminal and the non-common input terminal of a closed-loop one of the transistors and is electrically disconnected from any two terminals of an open-loop one of the transistors. The input port has a signal-carrying input terminal electrically connected to the non-common input terminal of both of the transistors and a ground terminal. The output port has a positive terminal electrically connected to the common terminal of the open-loop transistor and a negative terminal electrically connected to non-common output terminal of the closed-loop transistor. |
| US09263995B2 |
Multi-mode OPAMP-based circuit
A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal. |
| US09263985B2 |
Rooftop photovoltaic modules
A photovoltaic module may include a first frame portion defining a first plane, a second frame portion defining a second plane angled relative to the first plane, and a photovoltaic panel mounted to the second frame portion. The second frame portion may be supported only at opposing ends. The photovoltaic module may be stackable with similar modules. |
| US09263983B2 |
Vibration generating apparatus
A vibration generating apparatus with high yield, low cost, and can exhibit vibration tactile haptic effects even with variation in the natural frequency of a mechanical vibrator, including a damping system having a damping ratio ζ<1 to support a mechanical vibrator to a fastening part, and a magnetizing unit generating a dynamic magnetic field to vibrate the mechanical vibrator by non-contact, the mechanical vibrator generating a beat vibration by making the frequency of a drive voltage applied to the magnetizing unit, from a drive start or middle of drive, to be a non-resonant frequency out of a damped natural frequency of the mechanical vibrator, wherein the apparatus comprises a forced vibration control unit controlling to stop application of the drive voltage, in a beat wave defining an amplitude of the beat vibration, at a second valley part after a first peak part from the side of the drive start. |
| US09263982B2 |
Motor control system having common-mode voltage compensation
A motor control system is provided, and includes a motor, at least one differential amplifier configured to monitor phase current applied to the motor, and a current compensation controller. The current compensation controller is in communication with the at least one differential amplifier, and is configured to periodically determine a common-mode voltage of the at least one differential amplifier. The current compensation controller is also configured to determine a corrected phase current value based on the common mode voltage. |
| US09263981B2 |
Drive device for use in a laboratory device
The invention relates to a drive device (100) for use in a laboratory device, having a stepping motor (10) having rotor and stator, and having a motor controller (20), which is designed for the purpose of activating the stepping motor (10). In one embodiment, the drive device (100) comprises an encoder (11), which supplies a respective current encoder signal (e(t)) in operation (ia, ib), which reflects the current rotor position of the rotor, and phase terminals (14, 27), to tap the currently flowing motor phase currents (ia, ib). The motor controller (20) comprises a transformation module (13), in order to decompose the currently flowing motor phase currents (ia, ib) using a transformation method into a slip component (ix) and a torque component (iy). Furthermore, it comprises a slip regulation module (15), to which the slip component (ix) and a first target value (ix*) are supplied as input variables, and a torque regulation module (16), to which the torque component (iy) and a second target value (iy*) are supplied as input variables. The slip regulation module (15) and the torque regulation module (16) predefine the rotor phase currents (ia, ib) so that the difference between the slip component (ix) and the first target value (ix*) and the difference between the torque component (iy) and the second target value (iy*) are minimal. |
| US09263980B2 |
Reduction of noise and vibrations of an electromechanical transducer by using a modified stator coil drive signal comprising harmonic components
A method for controlling the operation of an electromechanical transducer is provided. The method includes (a) determining during a first period of time a first strength of the harmonic operational behavior of the transducer, (b) determining during a second period of time a second strength of the harmonic operational behavior of the transducer, wherein the second period of time is different from the first period of time, (c) calculating a harmonic control signal in response to both the determined first strength of the harmonic operational behavior and the determined second strength of the harmonic operational behavior, (d) generating a modified drive signal based on the calculated harmonic control signal, and (f) supplying the generated modified drive signal to electromagnetic coils of a stator of the transducer. Further, a corresponding control system for controlling the operation of an electromechanical transducer is provided. |
| US09263978B2 |
Drive unit, image forming apparatus incorporating same, peripherals incorporating same, and control method therefor
A drive unit, which can be included in an image forming apparatus with peripherals disposed thereto and use a control method therefore, includes an inner rotor brushless DC motor, a driver, a rotation detector, and a controller. The driver supplies power to drive the brushless DC motor. The rotation detector detects an amount and direction of rotations of an output shaft. The controller controls the rotations of the brushless DC motor and obtains a target drive signal of the brushless DC motor externally and a detection signal from the rotation detector and outputs a signal to the driver. The controller controls a speed of rotation of the brushless DC motor by varying the signal output to the driver based on the target drive signal and the detection signal. |
| US09263977B2 |
Current detection circuit, motor driving device, magnetic disk storage device, and electronic appliance
A current detection circuit for detecting a maximum current value in a three-phase motor includes an identifier configured to identify a maximum current phase having the maximum current value among phases of the motor, and a detector configured to detects the maximum current value by summing current values of phases other than the maximum current phase when the current direction in the maximum current phase is a predetermined first direction. |
| US09263974B1 |
Hover engine for a hoverboard which generates magnetic lift to carry a person
A hoverboard is described. The hoverboard includes four hover engines each including a motor. The motor rotates an arrangement of magnets to induce eddy currents and generate magnetic lift which causes the hoverboard to hover in the air. The hoverboard can be tilted to propel it in a particular direction. The hover engines can each be coupled to a tilt mechanism which is coupled to a flexible rider platform. When rider platform is flexed via rider induced forces, the hover engines can be tilted individually to provide translational forces. |
| US09263966B2 |
Power supply circuit with low stand-by losses
A circuit for converting an A.C. power supply voltage into a D.C. voltage, including: a first branch capable of providing a first power level; and a second parallel branch capable of providing a second power level greater than the first one, the second branch including a bidirectional activation switch. |
| US09263963B2 |
Current-responsive active rectification for a power supply operable in a discontinuous mode
An embodiment is an apparatus that includes an energy-storage circuit and a rectifying circuit. The energy-storage circuit is configured to generate a current that flows in a direction, and the rectifying circuit is configured to substantially block the current from flowing in a reverse direction in response to the current. Such an apparatus may be configured to block a reverse current before it begins to flow. For example, such an apparatus may include a transistor disposed in the path of the current, and may be configured to deactivate the transistor while a forward current is still flowing. Furthermore, by being configured to block the current from flowing in a reverse direction in response to the current itself, such an apparatus may better block a reverse current than an apparatus that blocks a reverse current in another manner, such as in response to a voltage across a rectifying transistor. |
| US09263962B2 |
Power conversion system and method
An exemplary power conversion system includes a first power conversion module, a second power conversion module, and a controller. The first power conversion module includes a first source side converter, a first load side converter, and a first DC link coupled between the first source side converter and the second load side converter. The second power conversion module includes a second source side converter, a second load side converter, and a second DC link coupled between the second source side converter and the second load side converter. The controller is configured to generate a number of switching signals according to a circuit structure of the power source module or a circuit structure of the load module. The switching signals are provided to the first power conversion module and the second power conversion module to balance a first DC link voltage and a second DC link voltage. |
| US09263960B2 |
Power converters for wide input or output voltage range and control methods thereof
A power converter topology is adapted for efficiency according to input voltage, output voltage or output current conditions. Topology adaptation is achieved by control responsive to the input and output operating conditions, or to one or more external control signals. Transition between any two topologies is implemented by pulse width modulation in the two switches in one of two bridge legs of a full bridge converter. When transitioning from full-bridge to half-bridge topology, the duty ratio of one switch in one leg of the full bridge is increased, while simultaneously the duty ratio of the other switch in the same leg is reduced until one switch is continuously on, while the other switch is continuously off. The transition from the half-bridge to the full-bridge topology is accomplished by modulating the same switches such that, at the end of the transition, both switches operate with substantially the same duty cycle. |
| US09263958B2 |
Single-stage power supply with power factor correction and constant current output
An example power supply includes an energy transfer element, a switch, and a controller. The switch is coupled to the energy transfer element to control a transfer of energy from an input to a galvanically isolated output of the power supply. The controller includes a delayed ramp generator, an integrator, an arithmetic operator, and a drive signal generator. The integrator generates a first signal responsive to integrating an input current of the power supply. The arithmetic operator generates a second signal responsive to the first signal and responsive to a ratio of a rectified input voltage to a dc output voltage of the power supply. The drive signal generator generates a drive signal in response to a delayed ramp signal and the second signal to control switching of the switch to provide power factor correction of the power supply and to provide a regulated current at the output. |
| US09263957B2 |
Switching power supply circuit and LED illumination device
A flyback-type switching power supply circuit provided with a transformer including a primary coil and a secondary coil, and a switching element connected to the primary coil, comprising: a multiplying circuit for multiplying a first value obtained by multiplying the on-duty ratio of a secondary current flowing to the secondary coil by a predetermined first constant, and a second value obtained by multiplying the peak value of a primary current flowing to the primary coil by a predetermined second constant; and a switching control circuit for controlling switching of the switching element so that the result of multiplication by the multiplying circuit and a third value obtained by multiplying a reference voltage by a predetermined third constant match; and the flyback-type switching power supply circuit is configured so that at least one of the first constant, the second constant, and the third constant is variable by an external signal. |
| US09263954B2 |
Switched mode power supply
A power supply having over power protection based on the same signal as used by the feedback path for controlling the switching of the power supply is disclosed. This means that no additional signal needs to be supplied to the control circuit to implement mains over protection. |
| US09263950B2 |
Coupled inductors for improved power converter
The disclosure relates to inductors fabricated on a substrate. A first inductor is formed by depositing conducting material on a first side of the substrate and a second inductor is formed by depositing material on a second side of the substrate. The inductors have the same cross section and the paths of the conducting materials are mirror images and provide magnetic flux on a portion of the substrate when equal currents flow in the inductors. |
| US09263949B2 |
Voltage conversion circuit and electronic circuit
A voltage conversion circuit includes: a first voltage conversion unit configured to perform voltage conversion on an input signal, the voltage conversion causing a predetermined delay time, and supply a resultant signal as a first converted signal; a second voltage conversion unit configured to perform voltage conversion on the input signal, the voltage conversion causing a delay time that is different from the predetermined delay time, and supply a resultant signal as a second converted signal; and an output unit configured to generate and output an output signal corresponding to the first and second converted signals in a matching period of time in which voltages of the first converted signal and the second converted signal are matched with each other, and continuously output the output signal in a period of time excluding the matching period of time, the output signal being output in the matching period of time. |
| US09263946B2 |
Power supply apparatus, power supply system and power supply method
A power supply apparatus, comprising: a driver connected to a power source voltage and configured to perform an ON/OFF operation of power supply to a load; a digital control circuit configured to perform an ON/OFF control of the driver; and an oscillator configured to output an oscillator signal for performing the ON/OFF control of the driver every constant period. The digital control circuit operates in a normal control mode in which the output operation of the oscillator signal by the oscillator and the ON/OFF operation of the driver are continuously activated, or in a low power control mode in which the output operation of the oscillator signal by the oscillator and the ON/OFF operation of the driver are intermittently activated. |
| US09263942B2 |
Low-consumption and high-efficiency energy-scavenging interface, method for operating the energy-scavenging interface, and system comprising the energy-scavenging interface
An energy-scavenging interface receives an input signal from a transducer and supplies an output signal to a load. A switch is connected between the transducer and a reference node, and a diode is connected between the transducer and the load. A control circuit closes the switch for a time interval to permit energy storage in the transducer. A scale copy of a peak value of stored electric current is obtained. The switch is opened when the time interval elapses and the stored energy exceeds a threshold. The stored energy is then released to supply the load through the diode. The switch remains open as long as the value of current in the output signal exceeds the value of the scaled copy of the peak value. |
| US09263940B2 |
Power converter and power factor corrector thereof
A power converter includes a rectifier and a power factor corrector. The rectifier is to be coupled to an alternating current power source and is configured to output a rectified signal. The power factor corrector includes a correcting circuit and a control circuit. The correcting circuit receives the rectified signal and is configured to generate an output voltage based on the rectified signal and a driving signal. The control circuit is configured to generate a first to-be-compared signal based on the rectified signal, to generate a second to-be-compared signal based on the output voltage, to compare the first and second to-be-compared signals, and to generate the driving signal based on a result of comparison performed thereby. |
| US09263938B2 |
Power factor correction
A power factor correction circuit includes an inductor L1, a diode D1, a switch Q3 and a controller 24. An input voltage Vin is applied to the inductor L1 which is cyclically discharged through the diode D1 by the operation of the switch Q3. The method of operation includes: operating a controller 24 to obtain an indication of the voltage across the switch Q3, monitoring the indication of the voltage across the switch Q3 to determine when the inductor L1 reaches a discharged state in response to the switch being in an off state, and the switch Q3 being controlled by the controller 24 to vary the on period of the switch Q3, during which the inductor is charged, for adjusting an output voltage Vbus towards a target value Vbus—target. The controller 24 monitors at least one of the indication of the voltage across the switch Q3 and the ratio of the switch on period Ton to the switch off period Toff for detecting that the input voltage Vin has a low value. |
| US09263932B2 |
DC-DC converter
A DC-DC converter includes: an error amplifier for outputting an error between an output voltage and a predetermined voltage; a phase compensation impedance element for accumulating the error across one end to generate an error phase; a determination unit for determining whether the voltage output by the error amplifier is higher, or lower than a reference voltage that is consonant with the predetermined voltage, and outputting a determination signal indicating determination results; and a voltage setting unit for setting a voltage for one end of the phase compensation impedance element higher than a lower output voltage limit for the error amplifier when the determination signal indicates that the voltage output by the error amplifier is lower than the reference voltage, or for canceling setting of the voltage when the determination signal indicates that the voltage output by the error amplifier is higher than the reference voltage. |
| US09263931B2 |
Linear solenoid and manufacturing method of the same
An inner diameter of a third stator core is greater than an inner diameter of a second stator core. When a first stator core, the second stator core, and the third stator core are placed in an inner periphery of a coil, a jig is inserted from an inner-periphery opening of a first end side of the third stator core into the third stator core to directly position the first stator core, the second stator core, and the third stator core in a radial direction. Therefore, a side force generated by an axis deviation between the first stator core, the second stator core, and the third stator core can be reduced. |
| US09263924B2 |
Motor support for a hybrid electric transmission
An assembly for supporting a motor of a vehicle powertrain includes a housing, a stator secured to the housing, a bearing having a radial position established by the housing, a member contacting the bearing, and a rotor secured to the member and including a radial outer surface spaced radially from the stator by an air gap established by contact between the bearing and the member. |
| US09263918B2 |
Connection for motor stator segments
A motor is provided for use in a machine. The motor includes a segmented stator and a resiliently flexible clip. The stator includes a core having spaced apart arms and a yoke. The arms define an opening therebetween, and the yoke spans the opening. The clip is removably retained on the core so as to apply pressure against each arm toward the yoke such that the arms are retained in contact with the yoke. |
| US09263917B2 |
Non-contact power receiving apparatus, non-contact power transmitting apparatus, and non-contact power transmitting and receiving system
A non-contact power receiving apparatus includes a power reception unit for receiving electric power in a non-contact manner from a power transmitting apparatus external to a vehicle, and a control device for controlling the transmitted power from the power transmitting apparatus. The control device controls the transmitted power based on a monitoring result obtained by monitoring the surroundings of the vehicle, and an occupant detection result obtained by detecting whether or not an occupant enters the vehicle. When the monitoring result indicates the approach of a moving object to the vehicle, the control device causes the power transmitting apparatus to reduce the transmitted power. The power transmitting apparatus and the power reception unit transmit and receive electric power in a non-contact manner by electromagnetic field resonance. |
| US09263916B2 |
Power management system, power management apparatus, and power management method
There is provided a power management system including a power receiving unit for receiving power from outside according to consumption of power, an electrical storage unit for storing the power received by the power receiving unit, and a discharge control unit for controlling a second power amount discharged from the electrical storage unit so that a first power amount provided by the power receiving unit attains a predetermined time-series pattern. |
| US09263913B2 |
Controlling current draw
Systems, methods, and apparatuses for controlling current in an electronic device may involve sensing a first voltage, the first voltage representing a battery voltage. The first voltage can be compared to a cutoff voltage. A current may be provided to power a display based on the comparison of the first voltage to the cutoff voltage. |
| US09263907B2 |
Method and apparatus for providing supplemental power to an engine
A method and apparatus provides supplemental power to an engine. The method and apparatus includes a pair of conductive leads for connecting the supplemental power to an engine electrical system, one or more batteries connected in parallel with one or more capacitors, a relay connected to the conductive leads, a shunt cable connecting the batteries and capacitors to the relay and a processor for controlling the relay to selectively apply electrical power to the engine electrical system. The method and apparatus includes safety features to reduce the risk of injury to the operator and damage to the apparatus and/or engine electrical system. |
| US09263902B2 |
Battery management system and battery pack having the same
A battery management system and a battery pack having the same including a charging circuit path for charging a battery and a discharging circuit path for discharging the battery is disclosed. The battery pack also includes a controller configured to control a charge switch unit in the charging circuit path during charging and to compensate for a change in voltage across the battery during discharging by controlling a discharge switch unit in the discharging circuit path to supply substantially constant power to an output terminal unit. |
| US09263899B2 |
Power conditioning system
The present disclosure relates to a power conditioning system that includes an electrical energy source interface for connecting to an electrical energy source and includes a load interface for connecting to a load. Between the electrical energy source interface and the load interface is a plurality of electrical energy storage devices. Also included in the power conditioning system of the present disclosure is a charging switching subsystem that electrically connects a grouping of electrical energy storage devices to the electrical energy source interface for a selected time interval. A grouping includes less than all of the individual electrical energy storage devices. |
| US09263896B2 |
Current control device, current control method, and current control system
A current control device is a current control device which supplies current to a load device by controlling a current source including a first electric appliance and a voltage source including a second electric appliance. The current control device includes: an obtaining unit which obtains information indicating non-linear components included in load current that is current supplied to the load device; a determining unit which determines a first current that includes the non-linear components; and a notifying unit which notifies the current source of a command value for causing the current source to output the first current to cause the current source to output the first current. |
| US09263895B2 |
Distributed energy conversion systems
A distributed energy conversion system may include one or more DC power sources and two or more inverters to convert DC power from the power sources to AC power. The AC power from the two or more inverters may be combined to provide a single AC output. A module may include one or more photovoltaic cells and two or more inverters. An integrated circuit may include power electronics to convert DC input power to AC output power and processing circuitry to control the power electronics. The AC output power may be synchronized with an AC power distribution system. |
| US09263894B2 |
Customized electric power storage device for inclusion in a collective microgrid
An electric power storage device is described herein, wherein the electric power storage device is included in a microgrid. The electric power storage device has at least one of a charge rate, a discharge rate, or a power retention capacity that has been customized for a collective microgrid. The collective microgrid includes at least two connected microgrids. The at least one of the charge rate, the discharge rate, or the power retention capacity of the electric power storage device is computed based at least in part upon specified power source parameters in the at least two connected microgrids and specified load parameters in the at least two connected microgrids. |
| US09263892B2 |
Method and a device for managing energy distribution
A method of managing energy supply in which an aggregator receives an energy demand from at least one operator of an energy distribution network and sends instructions to a plurality of energy facilities suitable for providing energy in order to satisfy the demand, the method being characterized by the following steps: each energy facility transmits to the aggregator a description of instantaneous variations of the energy state and technical constraints linked to its operation in order to satisfy the demand; and the aggregator defines in automatic manner for each energy facility a response profile for the demand as a function of the description by taking into account non-linear responses and energy state history data from each energy facility, and transmits the response profile of the energy distribution network to the operator, and transmits a set of control signals to each energy facility in order to satisfy the demand. |
| US09263890B2 |
Power management apparatus and method for controlling the same
A power management apparatus including an information collecting unit configured to collect at least one reference electric signal and at least one product information that correspond to at least one load, a storage unit configured to store the collected at least one reference electric signal and the collected at least one product information that correspond to the at least one load, a measurement unit configured to measure electric signals of loads provided in a power management domain, and a control unit configured to find a reference electric signal, corresponding to the measured electric signal, among the stored reference electric signals, check product information corresponding to the found electric signal and display the checked product information. The reference electric signal of each load is acquired in advance, and electric signals of loads are distinguished among all electric signals, thereby enhancing the efficiency in recognizing each load. |
| US09263888B2 |
Side wall bracket for cable tray
A cable tray and at least one side wall bracket secured to the cable tray wherein the cable tray has a plurality of transverse and longitudinal wires. The side wall bracket has angled legs defined by a U-shaped inside leg portion and a hook that leads to an outside leg portion. The inside leg portion of each angled leg engages a first surface of side longitudinal wires and bottom longitudinal wires and the outside leg portion of each angled leg engages a second surface opposite the first surface of side longitudinal wires and bottom longitudinal wires to secure the side wall bracket to the cable tray. |
| US09263885B2 |
Distributed power delivery scheme for on-die voltage scaling
A high-speed low dropout (HS-LDO) voltage regulation circuit suitable to enable a power gate unit to produce a variable voltage signal based on the load of a processor is disclosed herein. In various embodiments, selection logic may dynamically enable or disable the HS-LDO circuit to allow the power gate unit to operate under a fully-on or fully-off mode. Other embodiments may be disclosed or claimed. |
| US09263884B2 |
Electrostatic protection circuit
An electrostatic protection circuit includes a trigger circuit connected between a first and second power source line. The trigger circuit outputs a trigger signal in response to a voltage difference between the power source lines, such as occurs when an electrostatic discharge is received along the power source lines. A buffer circuit in the protection circuit outputs a drive signal in response to the trigger signal. A switch circuit is connected between the first and second power source lines and controls the ON/OFF conduction state between the power source lines in response to the drive signal. A control circuit supplies a control signal to the switch circuit after the drive signal causes the switch circuit to switch to the ON conduction state. The control signal maintains the switch in the ON conduction state while the voltage difference between power source lines exceeds a predetermined value. |
| US09263883B2 |
Semiconductor integrated circuit
A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included. |
| US09263882B2 |
Output circuits with electrostatic discharge protection
An output circuit is provided and includes first and second output stage elements, a detection circuit, a control circuit, and a first pre-driver. The first and second output stage elements are coupled in series between a power terminal and the ground terminal. The detection circuit detect whether an electrostatic discharge event occurs at an output terminal between the two output stage elements to generate a control signal. The control circuit controls a state of the first output stage element when the control circuit is enabled according to the control signal. The first pre-driver controls the state of the first output stage element when the first per-driver is enabled according to the control signal. When the detection circuit detects that the electrostatic discharge event occurs at the output terminal, the control circuit is enabled to turn on the first output stage element, and the first pre-driver is disabled. |
| US09263881B2 |
Digital amplitude modulation apparatus and control method of digital amplitude modulation apparatus
A digital amplitude modulation apparatus is provided with a measuring section, a fast surge protection section, a slow vector protection section, and a controller. The measuring section detects a voltage and a current from an RF signal. The fast surge protection section calculates an SWR from a detection signal of the measuring section, and obtains a first upper limit of the number of power amplifiers which can be put into an ON state based on the SWR and generates a first control signal. The slow vector protection section obtains a reflection coefficient from the output detection signal of the measuring section, and obtains a second upper limit of the number of the power amplifiers which can be put into an ON state based on the reflection coefficient and generates a second control signal. The controller controls the power amplifiers to be ON/OFF. |
| US09263876B2 |
Multi-phase switching converter with over current protection and control method thereof
A multi-phase switching converter includes a plurality of switching circuits and a controller. The output terminals of the plurality of switching circuits are coupled together to provide an output voltage to a load. The controller is configured to generate a plurality of control signals to control the plurality of switching circuits. When an over current condition of a current switching circuit of the plurality of switching circuits is detected, the controller skips the current switching circuit and successively turns on the remaining plurality of switching circuits that have not yet been turned on and where an over current condition has not been detected. |
| US09263875B2 |
Device for electric field control
A device for controlling an electric field at a high voltage component includes an inner deflector electrically connected to live voltage component; a resistive layer adapted for field control, arranged along the high voltage component, and electrically connected to the live high voltage component and electrically connected to a grounded part, the resistive layer having a nonlinear current-voltage characteristics; an insulating layer extending but ending without reaching the end of the resistive layer; and a semi-conducting or conducting layer arranged on the insulating layer and extending towards the resistive layer and past the end of the insulating layer, thereby defining an outer triple point at the intersection of the resistive layer, the insulating layer, and the semi-conducting or conducting layer. The resistive layer has first, second, and third adjacent sections, wherein a portion of the first section extends below the inner deflector. |
| US09263873B2 |
Polarized lightning arrestors
Systems and methods for dynamically defending a site from lightning strikes are provided. The systems and methods involve dynamically altering electrostatic fields above the site and/or dynamically intervening in lightning discharge processes in the vicinity of the site. |
| US09263871B2 |
Side-loading straight-line deadend clamp assembly
A clamp assembly includes a body member having a first and second ends. A cable groove is formed in the body member between the first and second ends thereof to receive a conductor. A keeper is connected to the body member and has a lower surface to engage the conductor received in the cable groove. A threaded fastener connects the keeper to the body member. A biasing member is disposed between the keeper and the body member on the threaded fastener to bias the keeper in a direction away from the body member. |
| US09263864B2 |
Universal, point-mounting apparatus and method
An anchor for lightning protection systems includes a base and pad that extend over a sufficient area and a sufficient bearing length to hold in shear and in tension against the weight, shear force, and moment of cables, points, and other components of a lightning protection systems. A universal point mount includes a head presenting greater cross sectional area and greater contact surface area than any other part of the mounting system. Drilled and tapped to receive a point oriented vertically, the head mounts easily on a horizontal or vertical mounting surface by receiving studs from a cleat plate (mandible) whose teeth capture the cable against a relief slot in the head. Apertures and studs provide rotating arbitrarily to any necessary orientation. |
| US09263862B2 |
Method for operating an electrical apparatus
A method and device for operating a fluid-insulated electrical apparatus. The insulation fluid of the electrical apparatus includes at least two components. The method includes the step of determining a physical state of the insulation fluid by measuring at least three measurement variables with sensors. The method further includes the step of deriving trend variables indicative of changes over time for the measurement variables and/or for characterizing variables. These characterizing variables are derived from the measurement variables by using a relating equation, such as an equation of state, and are also indicative of the physical state of the insulation fluid. By testing for specific patterns of the trend variables, an operating state of the electrical apparatus is determined. The possible operating states correspond to specific and distinguishable non-fault and fault scenarios for the electrical apparatus. Thus, operating states can be distinguished and trouble-shooting in case of a failure is simplified. |
| US09263855B2 |
Injection locking of gain switched diodes for spectral narrowing and jitter stabilization
Pulse power can be stabilized by applying spectrally narrow pulses to a laser diode during gain switching. An injection locking laser with a narrow emission bandwidth is tuned to a gain bandwidth of a laser diode to be gain switched. The injection locking emission is pulsed to provide locking pulses that are attenuated and then coupled to a laser diode. A gain switching pulse drive is applied to the laser diode in the presence of the attenuated locking pulses. The gain switched output is then stabilized with respect to pulse energy and pulse amplitude, and is suitable as a seed pulse for lasers to be used in materials processing. |
| US09263854B2 |
Non-linear vertical-cavity surface-emitting laser equalization
Technologies are generally described for implementing non-linear VCSEL equalization. In some examples, a rising edge tap parameter, a falling edge tap parameter, an equalization delay and a bias current may be used to equalize a data signal to be output from a VCSEL. A VCSEL model may be used to derive a VCSEL response to one or more isolated data pulses. The derived response may then be used to determine the rising and falling edge tap parameters and an equalization delay, based on a bias current value for the VCSEL and a data rate associated with the data signal. The data signal may then be adjusted based on the equalization delay and the rising and falling edge tap parameter and sent to the VCSEL for output. At the same time, the VCSEL may be biased with a bias current having the bias current value. |
| US09263853B2 |
Optical semiconductor device, method for manufacturing optical semiconductor device, and method for manufacturing optical module
An optical semiconductor device includes: a resonator end face; an optical waveguide; a window structure located between the resonator end face and the optical waveguide; and a vernier on the window structure and allowing measurement of length of the window structure along an optical axis direction. |
| US09263847B2 |
Light delivery component and laser system employing same
A light delivery component includes a delivery fiber configured to include a core and a clad; and a heat radiating member, wherein the delivery fiber is configured to include a first light emitting unit connected to a first heat radiating member which is a portion of the heat radiating member and a second light emitting unit connected to a second heat radiating member which is another portion of the heat radiating member, and at least the second light emitting unit is bent, and wherein the first light emitting unit is installed closer to a light incidence end of the delivery fiber than the second light emitting unit, and a bending radius of the first light emitting unit is set to be larger than that of the second light emitting unit. |
| US09263843B2 |
Spherical liquid-crystal laser
The patent refers to one or more droplets of chiral liquid crystals used as point source(s) of laser light. The source is shaped as a droplet of chiral liquid crystals (1) and an active medium preferably dispersed in the liquid crystals. The source is spherical and with a size of preferably between a few nanometres and 100 micrometres. A droplet consists of chiral liquid crystals (1) that have selective reflection in the range of the active medium's emission and can be cholesteric liquid crystals, a mixture of nematic liquid crystals and a chiral dopant or any other chiral liquid-crystal phase, preferably the blue phase, the ferroelectric phase, the antiferroelectric phase, any of the ferrielectric phases or another chiral phase of a soft substance, that need not be chiral by itself. |
| US09263842B2 |
Method for assembling an electronic device
An electronic device is provided. The device may include a plate placed behind a screen formed from a window and a display module to provide the screen with additional stiffness (e.g., to resist dropping events). The window may be maintained in the electronic device by trapping the window between a bezel and the display module. In some embodiments, the window may include a chamfered edge operative to be received by a recessed edge in the bezel. In some embodiments, the input mechanism of the electronic device may be metallic and need to be grounded, but may be surrounded by components or other non-grounding components. The device may include screws operative to pass through a circuit board to reach a frame, which may serve as a ground, where the screws are located in proximity of the button. In some embodiments, the circuit board may include an additional component for grounding the button. |
| US09263841B2 |
Shielding electrical connector and method of making the same
An electrical connector includes a seat having a signal contact receiving slot and a grounding contact receiving slot, and a signal contact and a grounding contact retained therein. The seat includes a first insulating member and a second insulating member surrounding the first insulating member, wherein the grounding contact receiving slot is defined on the first insulating member, the first insulating member further includes a through hole substantially parallel to the grounding contact receiving slot, a shielding member is defined on at least the inner surfaces of the grounding contact receiving slot and the through hole, the second insulating member includes a column formed into the through hole, the signal contact receiving slot is defined on the column of the second insulating member. |
| US09263838B1 |
Slip ring for high speed data transmission
The current invention is regarding a slip ring for transmitting high speed electrical signal across a rotating interface, especially for transmitting Ethernet data. It consists of sandwich assembly with multiple conducting plates individually sandwiched by multiple insulating spacers and a brush block assembly with multiple conducting brushes. The input Ethernet cable is attached on said sandwich assembly and the wires from input cable can be individually soldered into the central hole of each conducting plate (The wires are always off-centered in prior art). The output Ethernet cable is soldered on said brush block. Said brush block assembly and said sandwich assembly are rotatable relative to each other through bearings to form a rotational interface. As a result, high speed electrical signal can be transmitted across the rotating interface without suffering from phase shift and data distortion as in prior arts due to unequal path lengths. |
| US09263836B2 |
Electrical connector reducing antenna interference
An electrical connector (100) includes an insulative body (2), a number of contacts (1), and a metal shell (5). The insulative body includes an upper wall (21), a lower wall (22), a pair of sidewalls (23), and a rear wall (24) connecting between the upper wall, the lower wall, and the sidewalls for cooperatively defining a receiving space (20). The insulative body has a mating tongue (25) extending forwardly from the rear wall into the receiving space. The contacts are retained in the mating tongue and partly exposed in the receiving space. The metal shell has a length along a front-and-rear direction smaller than that of the receiving space. The metal shell has a length along a front-and-rear direction smaller than that of the receiving space so as to be positioned on a front part of the lower wall for reducing interference between the metal shell and an antenna. |
| US09263831B2 |
Plug having improved release mechanism
A plug (100) is configured for latching engagement with a cage (200). The plug has a housing (10) and a release mechanism (12) mounted on the housing. The housing has a nose portion (11) configured for latching engagement with a latch tab (21) formed on the cage. The release mechanism includes a rotatable lever (123) and a movable actuator arm (124). The lever has a front portion (1231), a rear portion (1232) and a middle portion (1234) adapted to be hinged with the housing. A front portion (1241) of the actuator arm could lift the front portion of the lever for releasing the nose from the latch tab when the actuator arm is moved forwardly, and a rear portion (1243) of the actuator arm could lift the rear portion of the lever when the actuator arm is moved backwardly. |
| US09263828B2 |
Magnetic power connector and an electronic system using the magnetic power connector assembly
A magnetic power connector and an electronic system using a magnetic power connector assembly are disclosed, wherein a magnetic element of the magnetic power connector is magnetically attracted to a matching magnetic connector to ensure a stable contact. In addition, the electrical conductive path created between the contact elements does not pass through any elastic elements, thereby avoiding heating and improving the lifespan of the elements. Furthermore, sealing member can be disposed in the gaps between the connector elements to make the connector waterproof. In addition, a trigger signal can be generated by establishing an electrical connection between a signal contact element and the conductive element in the magnetic power connector so as to achieve the purpose of identification or control, thereby avoiding the functional failure caused by the damage of the contact element of the matching magnetic connector. |
| US09263826B2 |
Connector assembly with cable tie
A connector assembly in a vending machine is disclosed. The connector assembly includes a connector body and a cable tie. The connector body includes a mounting case and a pivoting part. The mounting case defines a plurality of inserting holes configured for receiving a first end of cables. The pivoting part includes a connecting portion and a pivoting portion coupled to the connecting portion. The cable tie includes an installation portion defining a plurality of cable holes configured for receiving a second end of cables and a rotating end coupled to the installation portion and rotatably mounted in the pivoting portion. The cable tie is rotatable relative to the connector body to rotate the second end relative to the first end. |
| US09263822B2 |
Wire terminal structure
A wire terminal structure capable of fully enclosing internal components to prevent external dust or impurity from entering the insulation case to affect the normal operation thereof. The wire terminal structure includes an insulation case and a conductive holding frame disposed in the case. The case is formed with a wire socket and a press window. The conductive holding frame has an elastic holding member corresponding to the wire socket. The elastic holding member is formed with a holding mouth. A push section is disposed on the elastic holding member corresponding to the press window. A pushbutton is elastically movably disposed in the press window between the press window and the push section. The pushbutton is spaced from the case. When an external force is applied to the pushbutton, the pushbutton is elastically moved to push the push section and open the holding mouth. |
| US09263809B2 |
Terminal block
A terminal block allows wires to be connected to the block by insertion at a front portion of the block and along a direction parallel to the length of the block. The block includes a securing feature to retain the electrical conductor securely in the block while also allowing simplified connection and disconnection of the wire. |
| US09263805B2 |
Reconfigurable self complementary array
An antenna structure for the transmission or receipt of electromagnetic signals, the structure formed as a self complementary array having a series of high and low impedance patches, with predetermined low impedance patches interconnected to one another by an impedance matching amplifier network so as to provide self complementary properties. |
| US09263797B1 |
Pivoting sensor drive system
A system comprises a base having a sensor support frame moveably mounted thereto such that the support frame is pivotal about at least two axes with respect to a pivot point. A sensor is coupled to the support frame. At least one actuator is provided for pivoting the support frame about the pivot point. |
| US09263779B2 |
Lithium air battery module
A lithium air battery module including a lithium air battery cell including a first electrolyte; an additional electrolyte disposed non-adjacent the first electrolyte; and a housing which accommodates the lithium air battery cell and the additional electrolyte. |
| US09263778B2 |
Electric vehicle running control system
An electric vehicle running control system is provided. The electric vehicle running control system comprises a heating circuit coupled with an in-vehicle battery and configured to heat the in-vehicle battery. The vehicle running control system further comprises a load capacitor and a first current storage element. The first current storage element may be coupled with the load capacitor and the heating circuit respectively configured to reduce interference between the heating circuit and the load capacitor. |
| US09263777B2 |
Semiconductor device, battery pack, and electronic device
A semiconductor device generates battery state information including information of a capacity that can be extracted from a battery in the case of discharging from a full charge state until a discharge cutoff voltage at a predetermined discharge rate, based on measurement results of battery voltage, current, and temperature. The device calculates a first estimate value of capacity that can be extracted in the case of discharging the battery from the full charge state until the discharge cutoff voltage and calculates a second estimate value of capacity that can be extracted in the case of discharging the battery until a voltage larger than the discharge cutoff voltage. The device corrects the first estimate value based on a difference between a capacity value extracted from the battery by discharging the battery from the full charge state until the voltage larger than the discharge cutoff voltage and the second estimate value. |
| US09263776B2 |
Battery system and energy storage system including the same
A battery system having components with reduced maximum voltage tolerance requirements is disclosed. The battery system includes a battery pack with battery modules, and measuring units, which are connected to the battery modules. The measuring units have first analog front ends (AFEs) for monitoring the at least two battery modules. Each first AFE is configured to transmit information related to the monitored characteristic via an isolator to a processor configured to control the battery pack based on the transmitted information. The isolator receives the transmitted information from an AFE which is not connected to the battery module having the least electric potential or to the battery module having the greatest electric potential. |
| US09263775B1 |
External battery for mobile devices with intelligent display
Battery pack with intelligent display and methods to make various types of a battery pack with an intelligent display for the benefit of a user. One embodiment is a method of making a battery pack with intelligent display. A second embodiment is a battery pack with intelligent display that can display one or more parameters, such as charge remaining, current out, current in, watts out, watts in, time remaining, time to recharge one or more batteries, battery temperature, battery voltages, the age of the battery, and clock time. |
| US09263770B2 |
Method for providing electrical potential from a sodium-based secondary cell
The present invention provides a method for providing electrical potential from a solid-state sodium-based secondary cell (or rechargeable battery). A secondary cell is provided that includes a solid sodium metal negative electrode that is disposed in a non-aqueous negative electrolyte solution that includes an ionic liquid. Additionally, the cell comprises a positive electrode that is disposed in a positive electrolyte solution. In order to separate the negative electrode and the negative electrolyte solution from the positive electrolyte solution, the cell includes a sodium ion conductive electrolyte membrane. The cell is maintained and operated at a temperature below the melting point of the negative electrode and is connected to an external circuit. |
| US09263768B2 |
Non-aqueous electrolyte and electrochemical device with an improved safety
Disclosed are a non-aqueous electrolyte comprising a lithium salt and a solvent, the electrolyte containing, based on the weight of the electrolyte, 10-40 wt % of a compound of Formula 1 or its decomposition product, and 1-40 wt % of an aliphatic nitrile compound, as well as an electrochemical device comprising the non-aqueous electrolyte. |
| US09263757B2 |
Highly basic ionomers and membranes and anion/hydroxide exchange fuel cells comprising the ionomers and membranes
This invention provides a family of functionalized polymers capable of forming membranes having exceptional OH− ionic conductivity as well as advantageous mechanical properties. The invention also provides membranes including the provided polymers and AEMFC/HEMFC fuel cells including such membranes. In a preferred embodiment, preferred function groups include a quaternary phosphonium, and in a more preferred embodiment the provided polymer is (tris(2,4,6-trimethoxyphenyl)phosphine)3 functionalized phosphonium polysulfone hydroxide. |
| US09263751B2 |
Method to reduce pressure when injectors are stuck open under faulted conditions and remedial action to prevent walk-home incident
A method for controlling a fuel cell system, capable of quickly detecting the pressure rise caused by a faulted open anode injector, reducing pressure in the fuel cell stack when the fault occurs, and taking remedial action to allow continued operation of the fuel cell stack, and militate against a walk-home incident. |
| US09263750B2 |
Method for manufacturing fuel cell separator
A method for manufacturing a fuel cell which includes layering and compression molding at least one of each of: thermoplastic resin sheets (A) containing 130 to 3,200 parts by weight of a carbonaceous material per 100 parts by weight of a thermoplastic resin; and thermoplastic resin sheets (B) containing 3 to 280 parts by weight of a carbonaceous material per 100 parts by weight of a thermoplastic resin, 50% to 100% by weight of the carbonaceous material being fibrous carbon. The thermoplastic resin sheets (A and B) are compression molded at a temperature 60° C. higher than the higher of the melting points of the two types of sheets such that the ratio between the final thickness (dA) of the compressed first thermoplastic resin sheet(s) (A) and the final thickness (dB) of the compressed second thermoplastic resin sheet(s) (B) satisfies the relation dA/dB≧2. |
| US09263749B2 |
Fuel cell
Provided is a fuel cell having a long product life. In the fuel cell, an interlayer is arranged between a portion of an interconnector which contains at least one of Ag, Pd, Pt, Fe, Co, Cu, Ru, Rh, Re and Au and a first electrode containing Ni. The interlayer is formed of a conductive ceramic. |
| US09263747B2 |
Positive electrode, nonaqueous electrolyte battery and battery pack
According to one embodiment, a positive electrode includes a positive electrode material layer and a positive electrode current collector. The positive electrode material layer includes a positive electrode active material having a composition represented by a formula (1) described below. The positive electrode material layer satisfies a formula (2) described below. The positive electrode material layer is formed on the positive electrode current collector. LixNi1-a-bCoaMbO2 (1) 35≦S1/V1≦70 (2) |
| US09263743B2 |
Electrode, secondary battery, battery pack, electric vehicle, electric power storage system, electric power tool, and electronic apparatus
(A) A cathode active material of a cathode includes a lithium phosphate compound represented by LiaM1bPO4 (M is Fe and the like, 0≦a≦2, b≦1). (B) Fine pore distribution of the cathode measured by a mercury intrusion method indicates a peak P1 in a range where a pore diameter is equal to or more than about 0.01 micrometers and less than about 0.15 micrometers, and indicates a peak P2 in a range where the pore diameter is from about 0.15 micrometers to about 0.9 micrometers both inclusive. (C) A ratio I2/I1 between intensity I1 of the peak P1 and intensity I2 of the peak P2 is from about 0.5 to about 20 both inclusive. (D) Porosity of the cathode is from about 30 percent to about 50 percent both inclusive. |
| US09263740B2 |
Battery anode containing CoSnC material
A battery capable of inhibiting swollenness of the battery is provided. A cathode and an anode are layered with a separator and an electrolyte layer in between. The anode contains an anode active material containing Sn or Si as an element. The electrolyte layer contains an electrolytic solution and a high molecular weight compound. It is preferable that the distance between the cathode and the anode is from 15 μm to 50 μm, and the distance between the cathode and the separator and the distance between the anode and the separator are respectively from 3 μm to 20 μm. Thereby, expansion of the anode is absorbed, stress on the anode is reduced, and occurrence of wrinkles in the anode is inhibited. |
| US09263738B2 |
Cathode active material and lithium secondary battery containing the same
Provided is a non-aqueous electrolyte-based, high-power lithium secondary battery having a long service life and superior safety at both room temperature and high temperature, even after repeated high-current charging and discharging. The battery comprises a cathode active material composed of a mixture of lithium/manganese spinel oxide and lithium/nickel/cobalt/manganese composite oxide wherein the cathode active material exhibits the life characteristics that the capacity at 300 cycles is more than 70% relative to the initial capacity, in the provision of satisfying the condition (i) regarding the particle size and the condition (ii) regarding the mixing ratio. |
| US09263734B2 |
Multilayer-structured carbon material for nonaqueous electrolytic solution secondary battery negative electrode, negative electrode for nonaqueous secondary battery, lithium ion secondary battery, and process for producing multilayer-structured carbon material for nonaqueous electrolytic solution secondary battery negative electrode
The present invention resolves the problem by using a multilayer-structured carbon material, as a nonaqueous electrolytic solution secondary battery negative electrode, which satisfies the following (a) and (b): (a) (Void fraction calculated from DBP oil absorption)/(Void fraction calculated from tapping density) is less than 1.01; and (b) Surface oxygen content (O/C) determined by X-ray photoelectron spectroscopy is 1.5 atomic % or more. |
| US09263731B2 |
High performance lithium or lithium ion cell
Disclosed herein are lithium or lithium-ion batteries that employ an aluminum or aluminum alloy current collector protected by conductive coating in combination with electrolyte containing aluminum corrosion inhibitor and a fluorinated lithium imide or methide electrolyte which exhibit surprisingly long cycle life at high temperature. |
| US09263729B2 |
Lithium secondary battery
A lithium secondary battery of the present invention has a positive electrode is provided with a positive electrode mix layer that includes a positive electrode active material and a conductive material. The positive electrode mix layer has two peaks, large and small, of differential pore volume over a pore size ranging from 0.01 μm to 10 μm in a pore distribution curve measured by a mercury porosimeter. A pore size of the smaller peak B of the differential pore volume is smaller than a pore size of the larger peak A of the differential pore volume. |
| US09263723B2 |
Secondary battery having a collecting plate
A secondary battery includes a wound electrode assembly having a first electrode plate having a non-coating portion, a second electrode plate having a non-coating portion, and a separator between the first electrode plate and the second electrode plate; a collecting plate having a track accommodating and electrically coupled to the non-coating portion of one of the electrode plates; a case housing the electrode assembly and the collecting plate, the case comprising an upper opening; and a cap assembly sealing the upper opening of the case. |
| US09263719B2 |
Sealing plate for prismatic secondary battery and prismatic secondary battery using the sealing plate
A prismatic secondary battery includes a prismatic hollow outer body having a mouth and a bottom; a flat electrode assembly, a positive electrode collector, a negative electrode collector, and an electrolyte, all of which are stored in the prismatic outer body; a sealing plate sealing up the mouth of the prismatic outer body; and a positive electrode terminal attached to the sealing plate in an electrically insulated manner. The sealing plate includes a gas release valve and an electrolyte pour hole and further includes, on the front face, a concaved flat face having an identification code. With the prismatic secondary battery of the invention, a jig for assembly or the like is unlikely to come into contact with the identification code during an assembly process of the prismatic secondary battery, hence the identification code is unlikely to be abraded, and the traceability is unlikely to be lost. |
| US09263717B2 |
Battery pack
A battery pack detachably mounted in a device for supplying power to the device to operate the device includes at least one rechargeable secondary battery (1), a battery case (31) housing the rechargeable secondary battery (1), a mounting mechanism for mechanically mounting the battery case (31) in the device, an electrical connection connected electrically to the device for supplying power to the device, and a pack circuit board (74) securing the electrical connection. The battery case (31) is divided into a first casing and a second casing, the pack circuit board (74) is secured to the inside surface of the first casing, and the mounting mechanism is installed so the mounting mechanism is at least partially exposed on the surface of the first casing. |
| US09263712B2 |
Secondary battery pack with improved safety
Disclosed is a secondary battery pack including an anode terminal of a battery cell, the anode terminal being made of a plate-shaped conductive member, the anode terminal being electrically connected to a protection circuit module (PCM) via a safety element, a cathode terminal of the battery cell, the cathode terminal being made of a plate-shaped conductive member, the cathode terminal being directly electrically connected to the PCM, a battery cell having the anode terminal and the cathode terminal formed at one end thereof, the battery cell being provided at the end thereof with a thermally welded surplus portion, and a PCM including a printed circuit board (PCB) having a protection circuit formed thereon. |
| US09263706B2 |
Method of manufacturing flexible display apparatus
A method of manufacturing a flexible display apparatus, the method including forming a thin film transistor (TFT), a first electrode, and a pixel defining film on a flexible substrate by using a roll-to-roll device; separating the flexible substrate from the roll-to-roll device; attaching the flexible substrate to a support substrate; forming an organic light-emitting diode (OLED) and an encapsulating layer at the first electrode; and separating the flexible substrate from the support substrate. |
| US09263705B2 |
Successive deposition apparatus and successive deposition method
A successive deposition apparatus by which a reduction in the luminous efficiency of a light-emitting element can be suppressed even in high-speed deposition of a light-emitting layer thereof is provided. The apparatus includes: a second deposition chamber; a third deposition chamber coupled to the second deposition chamber; a transfer unit for transferring a substrate from second deposition chamber to third deposition chamber; plural third deposition sources arranged in the substrate transfer direction in the second deposition chamber; and a fourth and fifth deposition sources alternately arranged in the transfer direction in the third deposition chamber. In the third deposition chamber, the fourth deposition source is placed nearest to the second deposition source. The fourth deposition source contains a host material, and the fifth deposition source contains a dopant material. The HOMO level of a material of the third deposition source is adjusted to that of the host material. |
| US09263704B2 |
Organic light emitting diode display device
An organic light emitting diode display device includes a first substrate including a display area, wherein a plurality of pixels each including sub-pixels is defined in the display area; a switching thin film transistor and a driving thin film transistor in each of the sub-pixels over the first substrate; light-blocking patterns in at least one of the sub-pixels; a color filter layer in at least one sub pixel; a first passivation layer over the switching thin film transistor, the driving thin film transistor and the light-blocking patterns; a first electrode in each of the sub-pixels over the first passivation layer; an organic light emitting layer on the first electrode all over the display area; and a second electrode on the organic light emitting layer all over the display area. |
| US09263701B2 |
Coated article and/or device with optical out-coupling layer stack (OCLS) including vacuum deposited index match layer over scattering matrix, and/or associated methods
Certain example embodiments relate to light emitting diode (e.g., OLED and/or PLED) inclusive devices, and/or methods of making the same. Certain example embodiments incorporate an optical out-coupling layer stack (OCLS) structure that includes a vacuum deposited index matching layer (imL) provided over an organo-metallic scattering matrix layer. The imL may be a silicon-inclusive layer and may include, for example, vacuum deposited SiOxNy. The OCLS including scattering micro-particles, the imL, and the anode may be designed such that the device extraction efficiency is significantly improved, e.g., by efficiently coupling the light generated in the organic layers of the devices and extracted through the glass substrate. In certain example embodiments, the refractive index of the ITO, SiOxNy index matching layer, OCLS scattering layer and the glass substrate may be provided in decreasing order. |
| US09263699B2 |
Dispenser and method of fabricating organic light emitting display device using the same
A dispenser capable of forming a uniform material layer and a method of fabricating an organic light emitting display device using the same are disclosed. The dispenser includes a syringe including a coating material and provided with a nozzle for ejecting the coating material to a substrate and a syringe cap for controlling a coating amount from the nozzle, a pressing unit providing a pressure for ejecting the coating material, a transporting unit for moving the syringe above, and a cap-driving unit for driving the syringe cap to control the coating amount. |
| US09263697B2 |
Light-emitting device and display device
Although an organic resin substrate is highly effective at reducing the weight and improving the shock resistance of a display device, it is required to improve the moisture resistance of the organic resin substrate for the sake of maintaining the reliability of an EL element. Hard carbon films are formed to cover a surface of the organic resin substrate and outer surfaces of a sealing member. Typically, DLC (Diamond like Carbon) films are used as the carbon films. The DLC films have a construction where carbon atoms are bonded into an SP3 bond in terms of a short-distance order, although the films have an amorphous construction from a macroscopic viewpoint. The DLC films contain 95 to 70 atomic % carbon and 5 to 30 atomic % hydrogen, so that the DLC films are very hard and minute and have a superior gas barrier property and insulation performance. |
| US09263696B2 |
Organic semiconductor component comprising a doped hole conductor layer
An organic semiconductor component with a hole conductor layer having p-type doping with a superacid salt has greatly improved charged transport and optical properties. Besides increasing the specific conductivity at very low doping concentrations, the doping brings about substantially no negative change in the color impression of the layer for the human eye. The absorbtivity of the hole conductor layer is not increased in the visible wavelength range as a result of the p-type doping with the superacid salt. Deposition from solution and from the gas phase is possible. |
| US09263686B2 |
Method of manufacturing organic thin film transistor having organic polymer insulating layer
An organic thin film transistor and a manufacturing method thereof are provided. The organic thin film transistor comprises: a substrate; a gate electrode layer (21) and a source/drain electrode layer (24), formed on the substrate; an organic semiconductor layer (25), formed between source and drain electrodes (24) of the source/drain electrode layer; and an organic insulating layer (23), formed between the gate electrode layer (21) and the organic semiconductor layer (25) and made from an organic polymer material. |
| US09263685B2 |
Thin film transistor
A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a transition layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The transition layer is sandwiched between the insulating layer and the semiconductor layer. The transition layer is a silicon-oxide cross-linked polymer layer including a plurality of Si atoms. The plurality of Si atoms is bonded with atoms of the insulating layer and atoms of the semiconductor layer. |
| US09263683B2 |
Use of cobalt complexes for preparing an active layer in a photovoltaic cell, and corresponding photovoltaic cell
A method for employing certain cobalt complexes as electron donors and in combination with an electron acceptor is provided for preparing an active layer in a photovoltaic conversion cell, as well as to the photovoltaic conversion cell in which the electron donor of the active layer includes such cobalt complexes. |
| US09263681B2 |
Organic light emitting host materials
Heteroaryl-aryl compounds such as compounds represented by the Formula: HT-[Ph1]r-Py-Het-ET may be used in electronic devices such as organic light-emitting devices. For example, the compounds may be used as an emissive material in an emissive layer. |
| US09263675B2 |
Switching components and memory units
Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior. |
| US09263672B2 |
Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate. |
| US09263671B1 |
3D variable resistance memory device and method of manufacturing the same
A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer. |
| US09263670B2 |
Memory element and memory device
A memory element and a memory device, the memory element including a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer provided on the second electrode side and is higher in resistance value than the resistance change layer. A resistance value of the resistance change layer is changeable in response to a composition change by applied voltage to the first and second electrodes. |
| US09263666B2 |
Magnetic random access memory
A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni. |
| US09263664B1 |
Integrating a piezoresistive element in a piezoelectronic transistor
A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer. |
| US09263662B2 |
Method for forming thermoelectric element using electrolytic etching
The present disclosure provides a thermoelectric element comprising a flexible semiconductor substrate having exposed surfaces with a metal content that is less than about 1% as measured by x-ray photoelectron spectroscopy (XPS) and a figure of merit (ZT) that is at least about 0.25, wherein the flexible semiconductor substrate has a Young's Modulus that is less than or equal to about 1×106 pounds per square inch (psi) at 25° C. |
| US09263661B2 |
Thermally driven power generator
A thermally driven power generator having a base and a heat source placed within the base. The thermally driven power generator further having a heat collector is adapted to collect the heat from the heat source through a plurality of fins and a heat sink adapted to release heat into the environment. The thermally driven power generator further having a thermal electric power generation module is sandwiched between the heat collector and a heat sink; the thermal electric power generation module is designed to convert heat collected by the heat collector to electrical power. A tray assembly for a thermally driven power generator, the tray assembly having: a transport tray; and a magnetic element integrated with the transport tray, the magnetic element designed to attract a wick keeper of a candle such that the wick is held in place. |
| US09263660B2 |
Generator
A generator includes a heat-electricity transforming device and a heat collector. The heat-electricity transforming device is configured to transform heat into electricity. The heat collector includes at least one heat absorption module. The at least one heat absorption module includes a carbon nanotube structure. The at least one heat absorption module is connected to the heat-electricity transforming device and transfers heat to the heat-electricity transforming device. |
| US09263657B2 |
Manufacturing method for semiconductor device and semiconductor device
A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line. |
| US09263655B2 |
Optoelectronic component and method for the production thereof
An optoelectronic component has a semiconductor chip and a carrier, which is bonded to the semiconductor chip by means of a bonding layer of a metal or a metal alloy. The semiconductor chip includes electrical connection regions facing the carrier and the carrier includes electrical back contacts on its back remote from the semiconductor chip. The back contacts are connected electrically conductively to the first electrical or second connection region respectively, in each case by at least one via extending through the carrier. The first and/or second electrical back contact is connected to the first or second electrical connection region respectively by at least one further via extending through the carrier. |
| US09263654B2 |
LED package improved structure and fabricating method thereof
A LED (Light-Emitting Diode) package structure is provided. The LED package improved structure includes a base, a plurality of metallic nanoparticles and a LED unit. The base has an accommodating space, wherein the accommodating space has a bottom surface and at least one side surface surrounding the bottom surface. The metallic nanoparticles cover the bottom surface and/or the side surface. The LED unit is disposed in the accommodating spare, in which light emitted from the LED unit is reflected or scattered by the metallic nanoparticles, each of the metallic nanoparticles has a diameter smaller than 10 nm and is electrically isolated. |
| US09263653B2 |
Light-emissive devices and light-emissive displays
In some embodiments, a light-emissive device may include a reflector assembly, a dielectric layer, an electrode pin, a second semiconductor, and an electrode connector. The reflector assembly may define a cavity, a light opening, and an electrode pin opening. The dielectric layer may be positioned adjacent to the reflector assembly. The dielectric layer may define an electrode pin aperture and an electrode connector aperture. The electrode pin may include a head and a shaft. The head may be positioned in the cavity and coated with a first semiconductor. The shaft may be at least partially positioned in the electrode pin opening and through-mounted to the electrode pin aperture. The second semiconductor may be disposed in the cavity. The second semiconductor may surround the first semiconductor. The electrode connector may be electrically coupled to the second semiconductor and through-mounted to the electrode connector aperture. |
| US09263651B2 |
Collimator
An LED package including a collimator body adapted to collect and/or reflect and/or focus light. An upper plane provided by the collimator body defines a mainly horizontal plane. At least one reflection surface is provided by the collimator body and is at least partially angled to the horizontal plane. The collimator body includes a recess for receiving a lighting element including a light emitting front face such that the reflection surface extends at least partially below the level of the front face in an assembled state. Due to the angle of the reflection surface with respect to the horizontal plane of the collimator body, a small light source and a high luminous flux at the same time are provided so that the luminance and the brightness of the LED package are increased. |
| US09263646B2 |
Phosphor particle group and light emitting apparatus using the same
Provided is a phosphor particle group of divalent europium-activated oxynitride green light emitting phosphor particles each of which is a β-type SiAlON substantially represented by a general formula: EuaSibAlcOdNe, where 0.005≦a≦0.4, b+c=12, d+e=16, wherein 60% or more of the phosphor particle group is composed of the phosphor particles in which a value obtained by dividing a longer particle diameter by a shorter particle diameter is greater than 1.0 and not greater than 3.0. A high-efficiency and stable light emitting apparatus using a β-type SiAlON, which includes a light converter using the phosphor particle group, and a phosphor particle group therefor are also provided. |
| US09263643B2 |
Light-emitting device
A light-emitting device includes: a light-emitting stack including a first surface and a second surface opposite to the first surface, wherein the light-emitting stack emits a light having a wavelength between 365 nm and 550 nm; and a first electrode formed on the first surface and comprising a first metal layer and a second metal layer alternating with the first metal layer, wherein the first electrode has a reflectivity larger than 95% for reflecting the light, and the second metal layer has a higher reflectivity index relative to the light than that of the first metal layer. |
| US09263642B2 |
III nitride semiconductor light emitting device and method for manufacturing the same
A III nitride semiconductor light emitting device with improved light emission efficiency achieved without significantly increasing forward voltage by achieving both good ohmic contact between an electrode and a semiconductor layer, and sufficient functionality of a reflective electrode layer, and a method for manufacturing the same. The III nitride semiconductor light emitting device has a III nitride semiconductor laminate including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer; an n-side electrode, a p-side electrode; and a composite layer having a reflective electrode portion and a contact portion made of AlxGa1-xN (0≦x≦0.05) on a second surface of the III nitride semiconductor laminate. The second surface is opposite to a first surface on the light extraction side. |
| US09263639B2 |
Group III nitride semiconductor light-emitting device
The present invention provides a Group III nitride semiconductor light-emitting device exhibiting improved emission output. The light-emitting device comprises an n-type contact layer on which an n-electrode is formed, a light-emitting layer, an n-type cladding layer formed between the light-emitting layer and the n-type contact layer. The n-type cladding layer has a structure of at least two layers including a first n-type cladding layer closer to the light-emitting layer and a second n-type cladding layer farther from the light-emitting layer than the first n-type cladding layer. The first n-type cladding layer has a Si concentration higher than that of the second n-type cladding layer, and the first n-type cladding layer has a thickness smaller than that of the second n-type cladding layer. |
| US09263634B2 |
Thin light emitting diode and fabrication method
A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure. |
| US09263632B2 |
Semiconductor light emitting device
According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers containing a nitride semiconductor and a light emitting layer. The emitting layer includes a barrier layer containing III group elements, and a well layer stacked with the barrier layer and containing III group elements. The barrier layer is divided into a first portion on an n-type semiconductor layer side and a second portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the second portion is lower than that of the first portion. The well layer is divided into a third portion on an n-type semiconductor layer side and a fourth portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the fourth portion is higher than that of the third portion. |
| US09263630B2 |
Inorganic layer light-emitting device
There is provided an inorganic layer light-emitting device including: a light-emitting layer including an emission body made of an inorganic material; and a metal-based particle assembly layer being a layer consisting of a particle assembly including 30 or more metal-based particles separated from each other and disposed in two-dimensions, said metal-based particles having an average particle diameter in a range of from 200 to 1600 nm, an average height in a range of from 55 to 500 nm, and an aspect ratio in a range of from 1 to 8, and said metal-based particles that compose said metal-based particle assembly layer are disposed such that an average distance between adjacent metal-based particles is in a range of from 1 to 150 nm. The inorganic layer light-emitting device exhibits high luminous efficiency through emission enhancement and improvement in light extraction efficiency. |
| US09263627B2 |
Method and structure for receiving a micro device
A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material. |
| US09263626B1 |
Crystalline thin film photovoltaic cell
A material stack including an ohmic contact layer and a single crystalline semiconductor base substrate of a first conductivity type and having a surface Fermi level pinned close to a band edge (either the conduction band or valence band) is first provided. A stressor layer is then formed above the ohmic contact layer and a material portion of the single crystalline semiconductor base substrate is removed by a process referred to as spalling. A transparent conductive oxide layer is then formed on an exposed surface of the material portion of the single crystalline semiconductor base substrate that was removed by spalling. |
| US09263625B2 |
Solar cell emitter region fabrication using ion implantation
Methods of fabricating solar cell emitter regions using ion implantation, and resulting solar cells, are described. In an example, a back contact solar cell includes a crystalline silicon substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region is disposed above the crystalline silicon substrate. The first polycrystalline silicon emitter region is doped with dopant impurity species of a first conductivity type and further includes ancillary impurity species different from the dopant impurity species of the first conductivity type. A second polycrystalline silicon emitter region is disposed above the crystalline silicon substrate and is adjacent to but separated from the first polycrystalline silicon emitter region. The second polycrystalline silicon emitter region is doped with dopant impurity species of a second, opposite, conductivity type. First and second conductive contact structures are electrically connected to the first and second polycrystalline silicon emitter regions, respectively. |
| US09263623B2 |
Plasma spray deposition of photovoltaic thin films with grain boundary minimization
Methods are described for depositing thin films, such as those used in forming a photovoltaic cell or device. In particular embodiments, one or more layers are deposited on a substrate by plasma spraying over the substrate. A grain size of grains in each of the one or more layers is at least approximately two times greater than a thickness of the respective layer. Accordingly, large flat-grained structures are formed in each respective layer, and grain boundaries within each respective layer can be minimized. |
| US09263619B2 |
Semiconductor component and method of triggering avalanche breakdown
A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. |
| US09263617B2 |
Semiconductor device and manufacturing method thereof
(OBJECT) The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials.(MEANS FOR SOLVING THE PROBLEM) In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member. |
| US09263611B2 |
Method for etching multi-layer epitaxial material
A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate. |
| US09263610B2 |
Electrochemical method of producing copper indium gallium diselenide (CIGS) solar cells
The present invention describes a method of producing a photovoltaic solar cell with stoichiometric p-type copper indium gallium diselenide (CuInxGa1-xSe2) (abbreviated CIGS) as its absorber layer and II-IV semiconductor layers as the n-type layers with electrodeposition of all these layers. The method comprises a sequence of novel procedures and electrodeposition conditions with an ionic liquid approach to overcome the technical challenges in the field for low-cost and large-area production of CIGS solar cells with the following innovative advantages over the prior art: (a) low-cost and large-area electrodeposition of CIGS in one pot with no requirement of post-deposition thermal sintering or selenization; (b) low-cost and large-area electrodeposition of n-type II-VI semiconductors for the completion of the CIGS solar cell production; and (c) low-cost and large-area deposition of a buffer layer of CdS or other compounds with a simple chemical bath method. |
| US09263609B2 |
Metal plating composition and method for the deposition of copper—zinc—tin suitable for manufacturing thin film solar cell
To be able to form a copper-zinc-tin alloy which optionally comprises at least one chalcogenide and thus forms a semiconductor without the use of toxic substances a metal plating composition for the deposition of a copper-zinc-tin alloy is disclosed, wherein said metal plating composition comprises at least one copper plating species, at lease one zinc plating species, at least one tin plating species and at least one complexing agent and further, if the alloy contains at least one chalcogen, at least one chalcogen plating species. |
| US09263585B2 |
Methods of forming enhanced mobility channel regions on 3D semiconductor devices, and devices comprising same
Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches. |
| US09263584B2 |
Field effect transistors employing a thin channel region on a crystalline insulator structure
A single crystalline dielectric layer is provided on an insulator layer including an amorphous dielectric material. The single crystalline dielectric layer can be patterned into various crystalline dielectric portions including dielectric fins, dielectric nanowires, and a dielectric fin-plate assembly. A semiconductor material can be deposited on the single crystalline surfaces of the various crystalline dielectric portions by a selective epitaxial deposition process while not growing on the surfaces of the insulator layer. Single crystalline semiconductor material portions can be formed on the surfaces of the dielectric fins, around the dielectric nanowires, and on horizontal and vertical surfaces of the dielectric fin-plate assembly. Source and drain regions can be formed in the single crystalline semiconductor material portions, and gate electrodes can be formed to provide various field effect transistors. |
| US09263580B2 |
Methods of forming isolated channel regions for a FinFET semiconductor device and the resulting device
One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity. |
| US09263575B2 |
Semiconductor device with one-side-contact and method for fabricating the same
A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. |
| US09263574B1 |
Semiconductor device and method for fabricating the same
A semiconductor device includes a semiconductor layer formed over a semiconductor substrate. A well region is disposed in a portion of the semiconductor layer, and a plurality of first doped regions is disposed in various portions of the well region. A second doped region is disposed in a portion of the well region. An isolation element is disposed in a portion of the top-most one of the first doped regions, and a third doped region is disposed in a portion of the top-most one of the first doped regions. A fourth doped region is disposed in a portion of the second doped region. An insulating layer overlies the third doped region, the isolation element, the second doped region, and the fourth doped region, and a conductive layer overlies the insulating layer. |
| US09263570B2 |
Semiconductor device including a high breakdown voltage DMOS and method of manufacturing the same
A semiconductor device includes a high breakdown voltage DMOS transistor formed on a first conductivity type semiconductor substrate. The semiconductor device includes: a DMOS second conductivity type well; a DMOS first conductivity body region; a DMOS second conductivity type source region; a DMOS second conductivity type drain region; a LOCOS oxide film formed between the DMOS second conductivity type drain region and the DMOS first conductivity type body region; and a DMOS gate insulating film formed in succession to the LOCOS oxide film to cover a DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well, wherein the DMOS gate insulating film includes a first insulating film which is disposed outside the DMOS channel region and a second insulating film which is disposed in the DMOS channel region and is thinner than the first insulating film. |
| US09263569B2 |
MISFET device and method of forming the same
Embodiments of the present disclosure include a method for forming a semiconductor device, a method for forming a MISFET device, and a MISFET device. An embodiment is a method for forming a semiconductor device, the method including forming a source/drain over a substrate, forming a first etch stop layer on the source/drain, and forming a gate dielectric layer on the first etch stop layer and along the substrate. The method further includes forming a gate electrode on the gate dielectric layer, forming a second etch stop layer on the gate electrode, and removing the gate dielectric layer from over the source/drain. |
| US09263564B2 |
Power integrated circuit with incorporated sense FET
In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET. |
| US09263563B2 |
Semiconductor device package
In an embodiment, a semiconductor device package includes a bidirectional switch circuit. The bidirectional switch circuit includes a first semiconductor transistor mounted on a first die pad, a second semiconductor transistor mounted on a second die pad, the second die pad being separate from the first die pad, and a conductive connector extending between a source electrode of the first transistor and a source electrode of the second transistor. |
| US09263561B2 |
Semiconductor device and an electronic device
The reliability of a semiconductor device is improved. The semiconductor device includes a wire which is a conductive film pattern for a terminal formed over a first insulation film over a semiconductor substrate, a second insulation film formed over the first insulation film in such a manner as to cover the wire, and a nickel layer formed over the wire at a portion thereof exposed from an opening in the second insulation film. The wire is formed of a lamination film having a main conductor film containing aluminum as a main component, and a conductor film formed over the entire top surface of the main conductor film. The conductor film is formed of a titanium film, a tungsten film, or a titanium tungsten film. The nickel layer is formed over the conductor film at a portion thereof exposed from the opening. |
| US09263557B2 |
Techniques for forming non-planar germanium quantum well devices
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. |
| US09263551B2 |
Simultaneous formation of source/drain openings with different profiles
A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening. |
| US09263544B2 |
Method for fabricating semiconductor device
A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer. |
| US09263542B2 |
Semiconductor device having a charged insulating layer
A semiconductor device comprises a substrate, an active layer over the substrate, and an insulating layer between the substrate and the active layer. The insulating layer is doped with one of positive charge and negative charge and configured to establish an electric field across the active layer when the semiconductor device is powered. |
| US09263541B2 |
Alternative gate dielectric films for silicon germanium and germanium channel materials
Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance. |
| US09263538B2 |
Ohmic contact to semiconductor
An ohmic contact to a semiconductor layer including a heterostructure barrier layer and a metal layer adjacent to the heterostructure barrier layer is provided. The heterostructure barrier layer can form a two dimensional free carrier gas for the contact at a heterointerface of the heterostructure barrier layer and the semiconductor layer. The metal layer is configured to form a contact with the two dimensional free carrier gas. |
| US09263535B2 |
Method for fabricating a gate all around device
The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base. |
| US09263534B2 |
Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of the recess is reflected on a surface of a metal film which is also provided on the back surface of the semiconductor substrate. |
| US09263530B2 |
Field effect transistor
A field effect transistor (FET) disclosed herein comprising a substrate, a C-doped semiconductor layer disposed on the substrate, a channel layer disposed on the C-doped semiconductor layer, and an electron supply layer disposed on the channel layer. The FET further comprises a diffusion barrier layer disposed between the C-doped semiconductor layer and the channel layer, wherein the diffusion barrier layer contacts the channel layer directly. |
| US09263528B2 |
Method for producing strained Ge fin structures
Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer. |
| US09263523B2 |
Advanced transistors with punch through suppression
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor. |
| US09263520B2 |
Facilitating fabricating gate-all-around nanowire field-effect transistors
Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges. |
| US09263517B2 |
Extremely thin semiconductor-on-insulator (ETSOI) layer
Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess. |
| US09263516B1 |
Product comprised of FinFET devices with single diffusion break isolation structures
An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure. |
| US09263513B2 |
Vertical outgassing channels
InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices. |
| US09263512B2 |
Memory cell with integrated III-V device
A method including forming an oxide layer on a top of a substrate; forming a deep trench capacitor in the substrate; bonding a III-V compound semiconductor to a top surface of the oxide layer; and forming a III-V device in the III-V compound semiconductor. |
| US09263503B2 |
Display device and method of fabricating the display device
In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented. |
| US09263496B2 |
Method of manufacturing an image sensor by joining a pixel circuit substrate and a logic circuit substrate and thereafter thinning the pixel circuit substrate
The present technology includes: bonding a device formation side of a first substrate having a first device and a device formation side of a second substrate having a second device in opposition to each other; forming a protective film on at least an edge of the second substrate having the second device; and reducing a thickness of the first substrate. |
| US09263494B2 |
CMOS image sensor
A CMOS image sensor including a pixel including: a photodiode in series with a MOS transistor between a first reference potential and a sense node; a MOS transistor connecting the sense node to a second reference potential; and a third MOS transistor assembled as a source follower between the sense node and a read circuit, wherein the oxide thickness of the third transistor is smaller than that of the first and second transistors, the voltage difference between the first and second reference potentials is greater than the maximum voltage capable of being applied between two terminals of the third transistor, and the body or drain region of the third transistor is connected to a third reference potential in the range between the first and second potentials. |
| US09263484B2 |
Pixel of image sensor and method for fabricating the same
A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure. |
| US09263483B2 |
Array panel and manufacturing method for the same
An array panel including a substrate, a scanning line, a data line, and a pixel array is disclosed. A pixel unit in the pixel array includes a thin film transistor, a pixel electrode, and a color filter layer disposed between a first plane and a second plane. The first plane is a plane in which a gate electrode of the thin film transistor is located. The second plane is a plane in which the pixel electrode is located. The scanning line, the data line, and the pixel array are disposed on the substrate. The present invention is advantageous since it reduces power consumption. |
| US09263469B2 |
Semiconductor device and manufacturing method thereof
A display device including TFT elements having satisfactory characteristics and being easy to assemble. In the display device, a pixel emitting red light comprises a red color filter. The red color filter forms a light shielding film for the TFT elements in a driver circuit portion or in a pixel portion. |
| US09263468B2 |
Display device and electronic device
An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed. |
| US09263464B2 |
Field effect transistors including contoured channels and planar channels
Disposable gate structures and a planarization dielectric layer are formed over doped semiconductor material portions on a crystalline insulator layer. Gate cavities are formed by removing the disposable gate structures selective to the planarization dielectric layer. Doped semiconductor material portions are removed from underneath the gate cavities to provide pairs of source and drain regions separated by a gate cavity. Within a first gate cavity, a faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer, while a second gate is temporarily coated with an amorphous material layer. A contoured semiconductor region is epitaxially grown on the faceted crystalline dielectric material portion in the first gate cavity, while a planar semiconductor region is epitaxially grown in the second gate cavity. The semiconductor regions can provide at least one contoured channel region and at least one planar channel region. |
| US09263463B2 |
Semiconductor integrated circuit, programmable logic device, method of manufacturing semiconductor integrated circuit
According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode. |
| US09263462B2 |
Semiconductor device
A semiconductor device may include a first insulating pillar having a substantially Y-shaped cross-sectional structure to define first through third regions, channel pillars formed in the first through third regions, respectively, and second insulating pillars disposed opposite one another across the first through third regions. The semiconductor device may also include third insulating pillars disposed between the second insulating pillars and disposed opposite one another across the first through third regions. The third insulating pillars may extend in a direction intersecting the second insulating pillars. |
| US09263457B2 |
Cross-coupling of gate conductor line and active region in semiconductor devices
Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme. |
| US09263449B2 |
FinFET and fin-passive devices
A method of forming a semiconductor structure within a semiconductor substrate is provided. The method may include forming, on the substrate, a first group of fins associated with a first device; a second group of fins associated with a second device; and a third group of fins located between the first group of fins and the second group of fins, whereby the third group of fins are associated with a third device. A shallow trench isolation (STI) region is formed between the first and the second group of fins by recessing the third group of fins into an opening within the substrate, such that the recessed third group of fins includes a fin top surface that is located below a top surface of the substrate. The top surface of the substrate is substantially coplanar with a fin bottom surface corresponding to the first and second group of fins. |
| US09263446B1 |
Methods of forming replacement gate structures on transistor devices with a shared gate structure and the resulting products
One illustrative method disclosed herein includes, among other things, forming a shared gate cavity that spans across an isolation region and is positioned above first and second active regions, forming at least one layer of material in the shared gate cavity above the first and second active regions and above the isolation region, forming a first masking layer that covers portions of the shared gate cavity positioned above the first and second active regions while exposing a portion of the shared gate cavity positioned above the isolation region, with the first masking layer in position, performing at least one first etching process to remove at least a portion of the at least one layer of material in the exposed portion of the shared gate cavity above the isolation region, and removing the first masking layer. |
| US09263432B2 |
High voltage semiconductor device and method for manufacturing the same
A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT. |
| US09263431B2 |
Method and apparatus for integrated circuit protection
In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage. |
| US09263429B2 |
Semiconductor device and manufacturing method of the same
A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping. |
| US09263427B2 |
Semiconductor integrated circuit having differential amplifier and method of arranging the same
A semiconductor integrated circuit comprises: a transistor region having a center line; a first block arranged in one side of the center line of the transistor region, and comprising a plurality of first and second groups each having a plurality of first and second segment transistors constituting first and second transistors of a differential amplifier; and a second block arranged in the other side of the center line, and having an arrangement corresponding to the arrangement of the first and second groups of the first block. |
| US09263424B2 |
Semiconductor chip stacking assemblies
Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second semiconductor device. An assembly comprises a first semiconductor chip that has a first and a second set of electrical interconnect regions disposed on its surface and a second semiconductor chip. The first set of electrical interconnect regions are electrically connected with the electrical interconnect regions of a second semiconductor chip, and the second set of electrical interconnect regions are electrically interconnected with the substrate. Direct electrical connections are for example, silicon photonics device-to-driver or device-to-signal converters, logic-to-memory, memory-to-memory, and logic-to-logic chip interconnections. |
| US09263422B2 |
Interlayer communications for 3D integrated circuit stack
Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules. |
| US09263415B2 |
Decoupling MIM capacitor designs for interposers and methods of manufacture thereof
Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device. |
| US09263413B2 |
Substrate-less stackable package with wire-bond interconnect
A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. |
| US09263412B2 |
Packaging methods and packaged semiconductor devices
An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux. |
| US09263409B2 |
Mixed-sized pillars that are probeable and routable
An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and multiple macro-pillars also attached to the surface of the integrated circuit. The micro-pillars provide an electrical interface to the integrated circuit during regular operation. The macro-pillars provide an electrical interface to the integrated circuit both during regular operation and during testing of the integrated circuit. |
| US09263407B2 |
Method for manufacturing a plurality of metal posts
A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad. |
| US09263404B2 |
Managing method of building material and wireless chip applied to the method
A lot of buildings have been built while it is concerned that a building material is used fraudulently. Therefore, the present invention provides a managing method of the material and a system thereof. The present invention provides a managing method including a step of attaching a sheet including a plurality of memories to each surface of a plurality of materials, a step of dividing the plurality of materials with the sheet in accordance with data in the memory, a step of constructing a building by using the divided material in accordance with the data in the memory, and a step of checking the data on the constructed building, which is stored in the plurality of memories. |
| US09263400B2 |
X-ray obscuration film and related techniques
An X-ray obscuration (XRO) film comprising one or more metallic wire mesh layers and an adjacent layer of indium foil having portions which extend into openings of the wire mesh and in contact with metallic portions thereof. The XRO film can be capable of absorbing at least a portion of X-ray energy thereby creating an interference pattern when the XRO film is coupled with an electronic circuit and placed between an X-ray source and an X-ray detector and subjected to radiographic inspection. The interference pattern can create sufficient visual static to effectively obscure circuit lines in the electronic circuit when subjected to radiographic inspection techniques. The XRO film can be substantially thinner than existing solutions for preventing X-ray inspection with an exemplary embodiment being no more than 5 mils thick. The metallic XRO film can also provide electromagnetic shielding and/or heat dissipation for electronic circuits. |
| US09263398B1 |
Semiconductor packaging identifier
Described is a semiconductor package frame including a material comprising wire openings a die-mounting surface area with a die-mounting surface and identification markings included within the die-mounting surface. The identification markings uniquely identify the semiconductor package frame from among other semiconductor package frames comprising different identification markings. |
| US09263395B2 |
Sensor having damping
A sensor device, having a flexible printed circuit board that has a fastening section for a chip structure, a chip structure situated on the fastening section of the flexible printed-circuit board, and a damper element for damping the chip structure from mechanical influences. The fastening section of the flexible printed circuit board, the chip structure and the damper element are situated one on top of the other. |
| US09263392B1 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess. |
| US09263389B2 |
Enhancing barrier in air gap technology
A method of forming a semiconductor structure including a barrier layer between a metal line and an air gap oxide layer. The barrier layer may be formed in-situ or by a thermal annealing process and may prevent diffusion or electrical conduction. |
| US09263387B2 |
GOA circuit of array substrate and display apparatus
The embodiments of the present disclosure provide a GOA circuit of an array substrate and a display apparatus, which are used in the field of display technology, and enable reducing short-cut of a GOA unit due to ESD, and improving the yield of the GOA circuit. The GOA circuit includes a GOA unit and an STV signal wire electrically connected to the GOA unit, the STV signal wire including a first part and a second part; the GOA circuit further includes a first transparent electrode and an insulating layer located between the first transparent electrode and the first part, the first transparent electrode, the first part and the insulating layer forming a first capacitor. |
| US09263386B2 |
Forming BEOL line fuse structure
In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size that is smaller than a nominal grain size of the plurality of grains in a remaining portion of the line. |
| US09263385B1 |
Semiconductor fuses and fabrication methods thereof
Semiconductor fuses with epitaxial fuse link regions and fabrication methods thereof are presented. The methods include: fabricating a semiconductor fuse including an anode region and a cathode region electrically linked by a fuse link region, and the fabricating including: forming, epitaxially, the fuse link region between the anode region and the cathode region, wherein the fuse link region facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region thereof. The semiconductor fuses include: an anode region and a cathode region electrically linked by a fuse link region, wherein the fuse link region includes an epitaxial structure and facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region, wherein the epitaxial structure is in at least partial crystallographic alignment with the anode region and the cathode region of the semiconductor fuse. |
| US09263381B2 |
Semiconductor module and method for manufacturing the same
A semiconductor module according to one embodiment includes a semiconductor chip, a wiring substrate, a mounting plate provided with the wiring substrate thereon, a frame body defining a case for the wiring substrate, together with the mounting plate, a bus bar extending from the case and being inserted into a side wall of the frame. The side wall has a projection. The bus bar includes a first region in the side wall, a second region extending from a first end of the first region outward from the frame, a third region extending from a second end of the first region into the frame. The third region is bent based on the shape being close to the wiring substrate of the projection. The mounting plate with the wiring substrate is attached to the frame such that the third region is in press-contact with the wiring pattern. |
| US09263379B2 |
IC package with metal interconnect structure implemented between metal layers of die and interposer
An integrated circuit package includes a die having a first substrate implementing an integrated circuit comprising circuit elements. The die includes a first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit. The die also includes a first plurality of pads at or overlying a top metal layer of the first plurality of metal layers. The integrated circuit package includes an interposer having a second plurality of metal layers implementing a second portion of the metal interconnect structure. The interposer includes a second plurality of pads at or overlying a top metal layer of the second plurality of metal layers. A plurality of solder structures couple the first and second pluralities of pads. The first and second portions of the metal interconnect structure together complete a signal path between two or more circuit blocks of the integrated circuit. |
| US09263376B2 |
Chip interposer, semiconductor device, and method for manufacturing a semiconductor device
A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad. |
| US09263362B2 |
Method of forming a ring-shaped metal structure
A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the semiconductor chip. The method includes encapsulating the first semiconductor chip with an encapsulation body thereby defining a second main surface and depositing a metal layer over the first semiconductor chip and the encapsulation body. A plurality of external contact pads are placed over the second main surface of the encapsulation body, the metal layer electrically coupling at least one external contact pad of the plurality of external contact pads to the ring-shaped metal structure. A seal ring is placed between the ring-shaped metal structure and the contour of the first main surface of the first semiconductor chip. |
| US09263361B2 |
Semiconductor device having a vertical interconnect structure using stud bumps
A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump. |
| US09263359B2 |
Mixed metal-silicon-oxide barriers
A method of forming a thin barrier film of a mixed metal-silicon-oxide is disclosed. For example, a method of forming an aluminum-silicon-oxide mixture having a refractive index of 1.8 or less comprises exposing a substrate to sequences of a non-hydroxylated silicon-containing precursor, activated oxygen species, and metal-containing precursor until a mixed metal-silicon-oxide film having a thickness of 500 Ångstroms or less is formed on the substrate. |
| US09263351B2 |
Method of forming an integrated inductor by dry etching and metal filling
The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. |
| US09263342B2 |
Semiconductor device having a strained region
The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region. |
| US09263336B2 |
Symmetrical bipolar junction transistor array
A method of manufacturing a bipolar junction transistor (BJT) array may include forming a substrate of doped silicon and forming a plurality of BJTs on the substrate. Each of the BJTs may have a first region and a second region sandwiching a base region vertically. The first region may be in contact with the substrate, where the BJTs are formed in a first row and a second row. The first row and the second row may each have BJTs separated from one another by a word line distance and the first row and second row may be separated by a bit line distance. A plurality of word line contacts may be formed laterally enclosing and electrically connected to each base region of the BJTs. The word line contacts may have a lateral thickness more than one half the word line distance and less than one half the bit line distance. |
| US09263334B2 |
Method of severing a semiconductor device composite
A method of severing a semiconductor device composite includes a carrier having a main surface and a semiconductor layer sequence arranged on the main surface including forming a separating trench in the semiconductor device composite by a first laser cut such that the separating trench only partially severs the semiconductor device composite in a vertical direction running perpendicular to the main surface, and severing the semiconductor device composite completely along the separating trench with a severing cut with a laser. |
| US09263332B2 |
Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer. |
| US09263328B2 |
Semiconductor device and method for making same
One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer. |
| US09263325B1 |
Precut metal lines
Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. |
| US09263324B2 |
3-D integration using multi stage vias
A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias. |
| US09263322B2 |
Reliable contacts
Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component. |
| US09263321B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure formed on a first portion of the active region, and at least one local interconnection layer formed on a portion of the substrate, wherein the at least one local interconnection layer is located on a side of the gate structure, and covers at least a second portion of the active region and a portion of the groove isolation region adjoining the active region. |
| US09263318B2 |
Method of forming a laminated semiconductor film
According to some embodiments of the present disclosures, a method of forming a laminated semiconductor film is constituted by alternately laminating first and second semiconductor films on an underlying film of each of a plurality of substrates to be processed. The method includes performing a first operation of forming the first semiconductor film and a second operation of forming the second semiconductor film until a predetermined number of laminated films are obtained. In the method, a film forming temperature in the first operation and a film forming temperature in the second operation are set to be equal to each other, and temperatures between the first and second operations are set to be constant. |
| US09263317B2 |
Method of forming buried word line structure
A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer. |
| US09263314B2 |
Multiple bonding layers for thin-wafer handling
Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side. |
| US09263311B2 |
Transport system and transport method
In a transport system, a local track is disposed so as to be below an overhead travelling vehicle track in parallel or substantially in parallel therewith, and furthermore above a loading port of a processing device from upstream of the loading port to downstream of the loading port. A local vehicle including a hoist travels along the local track. Below the local track, a first buffer is disposed upstream of the loading port of the processing device, and a second buffer is disposed downstream of the loading port of the processing device, and the overhead travelling vehicle and the local vehicle can both perform delivery and receipt of the article with the first buffer and the second buffer. |
| US09263300B2 |
Etch back processes of bonding material for the manufacture of through-glass vias
A method for manufacturing vias in a glass substrate includes bonding, through a bonding layer, a first face of the glass substrate including a plurality of holes to a first face of a glass carrier. The bonding layer has a thickness t between the first face of the glass substrate and the first face of the glass carrier and extends into at least some of the plurality of holes to a depth h from the first face of the glass substrate. The method includes etching back the bonding layer to a depth d through the plurality of holes in the glass substrate. The depth d is less than the sum of the thickness t and the depth h. The method can include filling the plurality of holes with an electrically conductive material, and de-bonding the glass substrate from the bonding layer and the glass carrier. |
| US09263297B2 |
Method for self-aligned double patterning without atomic layer deposition
A method for self-aligned double patterning without needing atomic layer deposition techniques is disclosed. Techniques include using a staircase etch technique to preferentially shrink one material without shrinking an underlying material, followed by a resist-based chemical polishing and planarization technique that yields a narrowed and protruding feature (single-layer thickness) that is sufficiently physically supported, and that can be transferred to one or more underlying layers. After removing a resist coating, the result is a pattern that has been doubled without using ALD techniques. Such techniques improve efficiencies over conventional techniques for self-aligned double patterning. |
| US09263296B2 |
Chemical mechanical polishing (CMP) composition comprising two types of corrosion inhibitors
A chemical-mechanical polishing (“CMP”) composition (P) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) at least one type of A/-heterocyclic compound as corrosion inhibitor, (C) at least one type of a further corrosion inhibitor selected from the group consisting of: (C1) an acetylene alcohol, and (C2) a salt or an adduct of (C2a) an amine, and (C2b) a carboxylic acid comprising an amide moiety, (D) at least one type of an oxidizing agent, (E) at least one type of a complexing agent, and (F) an aqueous medium. |
| US09263295B2 |
Nanowire MOSFET with support structures for source and drain
A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. |
| US09263290B2 |
Sub-lithographic semiconductor structures with non-constant pitch
Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process. |
| US09263289B2 |
Adhesion-promoting composition used between curable composition for imprints and substrate, and semiconductor device using the same
Provided is an adhesion-promoting composition between a curable composition for imprints and a substrate, which excellent in adhesiveness and can control pattern failure. An adhesion-promoting composition used between a curable composition for imprints and a substrate, which comprises a compound having a molecular weight of 500 or larger and having a reactive group, and has a content of a compound, with a molecular weight of 200 or smaller, of more than 1% by mass and not more than 10% by mass of a total solid content. |
| US09263287B2 |
Method of forming fin-shaped structure
A method of forming fin-shaped structures includes the following steps. A plurality of spacers is formed on a substrate. The substrate is etched by using the spacers as hard masks to form a plurality of fin-shaped structures in the substrate. A cutting process is then performed to remove parts of the fin-shaped structures and the spacers formed on the removed parts. |
| US09263286B2 |
Diarylamine novolac resin
A novel diarylamine novolac resin such as a phenylnaphthylamine novolac resin, and further a resist underlayer film-forming composition in which the resin is used in a lithography process for manufacturing a semiconductor device. A polymer including a unit structure (A) of Formula (1): (in Formula (1), each of Ar1 and Ar2 is a benzene ring or a naphthalene ring). A method for manufacturing a semiconductor device, including: forming an underlayer film on a semiconductor substrate with the resist underlayer film-forming composition; forming a hardmask on the underlayer film; forming a resist film on the hardmask; forming a resist pattern by irradiation with light or an electron beam followed by development; etching the hardmask with the resist pattern; etching the underlayer film with the hardmask thus patterned; and processing the semiconductor substrate with the underlayer film thus patterned. |
| US09263284B2 |
Line width roughness improvement with noble gas plasma
A method for forming lines in an etch layer on a substrate may comprise providing a ultra-violet (UV) producing gas to a vacuum chamber having a photoresist mask, ionizing the UV producing gas to produce UV rays to irradiate the photoresist mask, and etching the lines into the etch layer through the photoresist mask. |
| US09263278B2 |
Dopant etch selectivity control
Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices. |
| US09263276B2 |
High-k/metal gate transistor with L-shaped gate encapsulation layer
A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack. |
| US09263273B2 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor substrate that includes a first substrate region, a second substrate region, and a third substrate region; providing a first mask that overlaps the semiconductor substrate; etching, using the first mask, the first semiconductor substrate to form a trench in each of the substrate regions; providing a second mask that overlaps the semiconductor substrate and includes three openings corresponding to the substrate regions; performing first ion implantation through the three openings to form a P-doped region in each of the substrate regions; performing second ion implantation through the three openings to form an N-doped region in each of the substrate regions; and performing third ion implantation through the three openings to form another N-doped region in each of the substrate regions; and forming an isolation member in each of the trenches. |
| US09263272B2 |
Gate electrodes with notches and methods for forming the same
A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region. |
| US09263270B2 |
Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structure
Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure. |
| US09263269B2 |
Reaction tube, substrate processing apparatus and method of manufacturing semiconductor device
Provided are a reaction tube, a substrate processing apparatus, and a method of manufacturing a semiconductor device capable of suppressing a non-uniform distribution of a gas in a top region to improve the flow of the gas and film uniformity within and between substrate surfaces. The reaction tube has a cylindrical shape, accommodates a plurality of substrates stacked therein, and includes a cylindrical portion and a ceiling portion covering an upper end portion of the cylindrical portion, the ceiling portion having a substantially flat top inner surface. A thickness of a sidewall of the ceiling portion is greater than that of a sidewall of the cylindrical portion. |
| US09263267B2 |
Silicon carbide semiconductor device and method of manufacturing the same
In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared. At a portion of the semiconductor substrate where a first electrode is to be formed, a metal thin film made of electrode material including an impurity is formed. After the metal thin film is formed, the first electrode including a metal reaction layer in which the impurity is introduced is formed by irradiating the metal thin film with a laser light. |
| US09263266B2 |
Group III nitride articles and methods for making same
Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films. |
| US09263265B2 |
Crystallization of amorphous films and grain growth using combination of laser and rapid thermal annealing
A method is disclosed for crystallizing semiconductor material so that it has large grains of uniform size comprising delivering a first energy exposure of high intensity and short duration, and then delivering at least one second energy exposures of low intensity and long duration. The first energy exposure heats the substrate to a high temperature for a duration less than about 0.1 sec. The second energy exposure heats the substrate to a lower temperature for a duration greater than about 0.1 sec. |
| US09263261B2 |
Method for supplying source gas for producing polycrystalline silicon and polycrystalline silicon
In a method according to the present invention, an occurrence ratio of popcorn is suppressed by adjusting kinetic energy of a source gas supplied to a reaction furnace for producing polycrystalline silicon with a Siemens method (flow velocity and a supply amount of the source gas in source gas supply nozzle ejection ports). Specifically, in performing deposition reaction of the polycrystalline silicon under a reaction pressure of 0.25 MPa to 0.9 MPa, when flow velocity of the source gas in gas supply ports of the source gas supply nozzles (9) is represented as u (m/sec), a source gas supply amount is represented as Q (kg/sec), and an inner volume of the reaction furnace (100) is represented as V (m3), values of u and Q of each of the source gas supply nozzles (9) are set such that a total Σ(Q×u2/V) of values Q×u2/V is equal to or larger than 2500 (kg/m·sec3). |
| US09263260B1 |
Nanowire field effect transistor with inner and outer gates
A semiconductor device comprising a suspended semiconductor nanowire inner gate and outer gate. A first epitaxial dielectric layer surrounds a nanowire inner gate. The first epitaxial dielectric layer is surrounded by an epitaxial semiconductor channel. The epitaxial semiconductor channel surrounds a second dielectric layer. A gate conductor surrounds the second dielectric layer. The gate conductor is patterned into a gate line and defines a channel region overlapping the gate line. The semiconductor device contains source and drain regions adjacent to the gate line. |
| US09263259B2 |
Semiconductor device comprising an oxide semiconductor
A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for metal films of a source electrode layer, a drain electrode layer, and a gate electrode layer, whereby diffusion of oxygen to the metal films is suppressed. |
| US09263256B2 |
Method of forming seed layer, method of forming silicon film, and film forming apparatus
Provided is a method of forming a seed layer as a seed of a thin film on an underlayer, which includes: forming a first seed layer on a surface of the underlayer by heating the underlayer, followed by supplying an aminosilane-based gas onto the surface of the heated underlayer; and forming a second seed layer on the surface of the underlayer with the first seed layer formed thereon by heating the underlayer, followed by supplying a disilane or higher order silane-based gas onto the surface of the heated underlayer. |
| US09263255B2 |
Method for separating epitaxial layers from growth substrates, and semiconductor device using same
The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness. |
| US09263247B2 |
Electric lamp and associated production method
In various embodiments, a lamp has a bulb with a pinch seal, which holds a light-emitting element by means of a wire clip. The wire clip consists of tungsten and has, at an end remote from films embedded in the pinch seal, an eyelet for holding the light-emitting element. An end of the wire clip which is close to a film is bent back. A film associated with the wire clip is folded in a roof-shaped manner. Overall, it is thus possible to realize a lamp with a long life. |
| US09263244B2 |
Mass spectrometer
A mass spectrometer is disclosed comprising a time of flight mass analyser. The time of flight mass analyser comprises an ion guide comprising a plurality of electrodes which are interconnected by a series of resistors forming a potential divider. Ions are confined radially within the ion guide by the application of a two-phase RF voltage to the electrodes. A single phase additional RF voltage is applied across the potential divider so that an inhomogeneous pseudo-potential force is maintained along the length of the ion guide. |
| US09263243B2 |
Assemblies for ion and electron sources and methods of use
Certain embodiments described herein are directed to devices that can be used to align the components of a source assembly in a source housing. In some examples, a terminal lens configured to couple to the housing through respective alignment features can be used to retain the source components in a source housing to provide a source assembly. |
| US09263241B2 |
Current threshold response mode for arc management
This disclosure describes systems, methods, and apparatuses for extinguishing electrical arcs in a plasma processing chamber. Once an arc is detected, the steady state voltage provided to the plasma processing chamber can be reduced, and the current being provided to the chamber decays below a steady state value as the arc is extinguished. When the current falls to or below a current threshold, the voltage can be ramped back up bringing the voltage and current back to steady state values. This technique enables power to return to a steady state level faster than traditional arc mitigation techniques. |
| US09263240B2 |
Dual zone temperature control of upper electrodes
A system and method of plasma processing includes a plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric temperature control zones and a controller coupled to the plasma chamber. |
| US09263238B2 |
Open plasma lamp for forming a light-sustained plasma
An open plasma lamp includes a cavity section. A gas input and gas output of the cavity section are arranged to flow gas through the cavity section. The plasma lamp also includes a gas supply assembly fluidically coupled to the gas input of the cavity section and configured to supply gas to an internal volume of the cavity section. The plasma lamp also includes a nozzle assembly fluidically coupled to the gas output of the cavity section. The nozzle assembly and cavity section are arranged such that a volume of the gas receives pumping illumination from a pump source, where a sustained plasma emits broadband radiation. The nozzle assembly is configured to establish a convective gas flow from within the cavity section to a region external to the cavity section such that a portion of the sustained plasma is removed from the cavity section by the gas flow. |
| US09263236B2 |
Sensing of plasma process parameters
A system for monitoring a condition in an enclosed plasma processing space (102). The system comprises a sensor (338), arranged to be provided within the enclosed plasma processing space, for sensing a condition in the enclosed plasma processing space and a modulation circuit (342), connected to the sensor, and arranged to modulate an output of the sensor to provide a modulated signal. The system further comprises a first transmission line coupler (330) arranged to be disposed within the enclosed plasma processing space. The first transmission line coupler (546) is connected to the modulation circuit and is arranged to couple the modulated signal to a transmission line, which is arranged to deliver energy into the enclosed plasma space. The system further comprises a second transmission line coupler, arranged to be disposed outside the enclosed plasma processing space and coupled to the transmission line and a demodulator (550), connected to the second coupler, for receiving and demodulating the modulated signal. |
| US09263235B2 |
Method for coincident alignment of a laser beam and a charged particle beam
A method and apparatus for aligning a laser beam coincident with a charged particle beam. The invention described provides a method for aligning the laser beam through the center of an objective lens and ultimately targeting the eucentric point of a multi-beam system. The apparatus takes advantage of components of the laser beam alignment system being positioned within and outside of the vacuum chamber of the charged particle system. |
| US09263234B2 |
Target processing unit
The invention relates to a projection lens assembly for directing a beam toward a target. This assembly includes a lens support body (52) that spans a plane (P), and has a connection region (58) and a lateral edge (56). The lens support body is arranged for insertion into a frame (42) of a processing unit along an insertion direction (X) parallel with the plane (P). The projection lens assembly includes conduits (60-64) emanating from the connection region, and a conduit guiding body (70-81) for accommodating the conduits. The guiding body includes a first guiding portion (72) for guiding the conduits from the connection region, along the plane to a lateral region (B) beyond the lateral edge. The guiding body also includes a second guiding portion (78) for guiding the conduits from the lateral region (B) toward a tilted edge (79) of the conduit guiding body. |
| US09263231B2 |
Moveable current sensor for increasing ion beam utilization during ion implantation
An ion implant apparatus and moveable ion beam current sensor are described. Various examples provide moving the ion beam current sensor during an ion implant process such that a distance between the ion beam current sensor and a substrate is maintained during scanning of the ion beam toward the substrate. The ion beam current sensor is disposed on a moveable support configured to move the ion beam current sensor in a first direction corresponding to the scanning of the ion beam while the substrate is moved in a second direction. |
| US09263224B2 |
Liquid bearing assembly and method of constructing same
A bearing assembly is disclosed that includes a sleeve having an opening formed therein and a shaft positioned within the opening of the sleeve such that a gap is formed between an inner surface of the sleeve and an outer surface of the shaft. A lubricant is disposed in the gap and a plurality of grooves are formed on at least one of the outer surface of the shaft and the inner surface of the sleeve. An anti-wetting coating is disposed on the at least one of the outer surface of the shaft and the inner surface of the sleeve between adjacent grooves of the plurality of grooves. |
| US09263221B2 |
Luminophore and light source containing such a luminophore
A luminophore from the class of nitridic or oxynitridic luminophores with at least one cation M and an activator D, wherein a proportion x of the cation is replaced with Cu and D is at least one element from the series Eu, Ce, Sm, Yb and Tb |
| US09263217B2 |
Protective switch with status detection
A protective switch assembly (100) includes switch position sensors (109) that sense switch blade (14) position and indicate whether one or more switches (104) are open. According to another aspect, the voltage and current of the switch circuits are monitored to determine switch position as well as overall circuit status. |
| US09263214B2 |
Make-up air intake system
An embodiment make-up air system includes a switch assembly including a housing configured to be mounted to an exhaust air duct, a rod pivotally mounted to the housing, the rod having a paddle mounted on a first rod end disposed outside the housing, the paddle including an angled portion, and a switch disposed in the housing, the switch actuated by the rod when the paddle experiences a predetermined flow of air through the exhaust duct, and a fresh air intake assembly operably coupled to the switch assembly, the fresh air intake assembly configured to open a damper disposed in a fresh air intake duct to initiate a flow of fresh air when the switch in the switch assembly has been actuated. |
| US09263211B2 |
Electrical switch with built in fuse
An electrical switch having an activation component that closes and opens contact points within a switch housing. The activation component can include a front end and a rear end. The rear end can be within the switch housing and the front end can protrude from the switch housing. The front end of the activation component can include a fuse slot. A fuse can be placed in the fuse slot and removed from the fuse slot. A rubber cover can be removably attachable to the outside of the fuse slot to protect a fuse within the fuse slot. |
| US09263206B2 |
Switching device
A switching device, in particular an electrical power circuit breaker, is disclosed for protecting an electrical circuit. The switching device includes two pole terminals, a switching mechanism for automatically interrupting the electrical connection of the two pole terminals in the event of an overload, electrical components for controlling the switching device and a pole cassette in which the switching mechanism is disposed in a switching chamber. The pole cassette includes at least one gas duct which is connected to the switching chamber in a gas-communicating manner and is designed to discharge gas from the pole cassette past the electrical components to the environment. |
| US09263204B2 |
Self capturing and keyed mobile device button
A housing of an electronic device encloses and supports at least one operational component and includes at least one opening sized to accommodate a mechanical input assembly. The mechanical input assembly includes a feature arranged to receive an input event, at least a portion of the feature exposed at an outside surface of the housing, an operational indicia visible on the exposed portion and having a preferred orientation with respect to the housing, the operational indicial providing an indication of how an operation of the operational component is influenced, and a shaft having a size and shape in accordance with the opening, the shaft attached to the external feature at a first end and an integrally formed self-capturing feature at the second end. The self-capturing feature is inserted into the opening until activated. The indicia is then properly aligned and the mechanical input assembly is locked to the housing. |
| US09263203B2 |
In cable micro input devices
A small form-factor input device operative to be coupled to an electronic device using a cable may include a circuit board; a first electrical switch disposed on a first side of the circuit board; a second electrical switch disposed on a second side of the circuit board; a frame defining a periphery, wherein the circuit board is maintained within the periphery of the frame; first and second shells that house the circuit board, the first shell placed over the first side of the circuit board, and the second shell placed over the second side of the circuit board; and at least one clip coupled to each one of the first shell and the second shell, wherein the at least one clip is operative to engage the frame. |
| US09263202B2 |
Internal stack-up structure of touch panel and method for producing the same
The present invention relates to an internal stack-up structure of a touch panel including a touch sensing substrate having a joint area with an electronic assembly placed thereon; a cover substrate facing to and being spaced out from the touch sensing substrate and having a first border region with a first mask layer coated thereon, the first border region corresponding to the joint area; a reflection layer disposed on the first mask layer and corresponding to the electronic assembly; and a bonding layer formed at least between the electronic assembly and the reflection layer, the bonding layer being formed by liquid bonding materials which change from liquid state to solid state to improve the bonding strength between the cover substrate and the touch sensing substrate after being exposed to light reflected from the reflection layer. |
| US09263194B2 |
Porphyrin-peptoid conjugate and the preparation process thereof
Disclosed are a porphyrin-peptoid conjugate and a method for preparing the same. The porphyrin-peptoid conjugate according to the present disclosure has porphyrins arranged face-to-face on a helical peptoid. The porphyrin-peptoid conjugate according to the present disclosure is a new-concept photosensitizing dye material wherein the distance, arrangement and number of porphyrins are controllable. Since the porphyrin-peptoid conjugate is monodisperse and has a precisely defined structure, selective decoration of dyes is easy and dyes can be arranged on the peptoid helix sequence and space specifically. Accordingly, a new high-efficiency photosensitizing dye molecule system having wide absorption spectrum including the visible and near-infrared range and high absorption coefficient can be prepared. |
| US09263193B2 |
Solid electrolytic capacitor and method for manufacturing the same
A solid electrolytic capacitor includes: a porous sintered body; an anode wire extending in a first direction and connected to the porous sintered body such that one end portion of the anode wire in the first direction is exposed; a resin package covering the porous sintered body and the anode wire; and a lead including a terminal exposed from the resin package and a lead side connector connected to the terminal. The anode wire includes a base and a connector placed at one side of the base in the first direction, a sectional area of the connector is smaller than that of the base, and the connector and the lead side connector are welded together. |
| US09263187B2 |
Multilayer ceramic electronic component and method of manufacturing the same
There is provided a multilayer ceramic electronic component, including: a ceramic main body including a dielectric layer; and first and second internal electrodes provided on upper and lower surfaces of the dielectric layer and formed of a thin film including graphene. The multilayer ceramic electronic component includes internal electrodes formed of a thin film including graphene, thereby having increased capacitance and improved thermal stability and withstand voltage characteristics. |
| US09263185B2 |
Multilayer ceramic capacitor and circuit board for mounting the same
A multilater ceramic capacitor includes: a ceramic body in which a plurality of dielectric layers are laminated; and an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body with the dielectric layer interposed therebetween, and forming capacitance. An upper cover layer is formed on an upper portion of the active layer; a lower cover layer is formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer. First and second external electrodes cover both end surfaces of the ceramic body. Specific sizing of ceramic body and electrodes is defined. |
| US09263184B2 |
Simulation apparatus and simulation method
A computer-readable medium stores a magnetic substrate simulation program causing a computer to execute a process that includes calculating an effective magnetic field for each area of an element in the magnetic substrate, when magnetization of each area changes and based on a magnetic field generated from magnetic energy in each area and a rate of change of magnetization working in a direction inhibiting change in the average magnetization of the areas; obtaining for each area and based on the calculated effective magnetic fields and magnetization of each area, changes in magnetization and calculating for each area, magnetization after the changes; judging based on magnetization of each area before and after the changes, whether magnetization in the element converges; and storing a combination of the average magnetization of the areas for which magnetization in the given element converges and a static magnetic field based on the average magnetization. |
| US09263183B2 |
Modular photovoltaic power supply assembly
An apparatus, device, and system for generating an amount of output power in response to a direct current (DC) power input includes a configurable power supply, which may be electrically coupled to the DC power input. The configurable power supply is selectively configurable between multiple circuit topologies to generate various DC power outputs and/or and AC power output. The system may also include one or more DC power electronic accessories, such as DC-to-DC power converters, and/or one or more AC power electronic accessories such as DC-to-AC power converters. The power electronic accessories are couplable to the configurable power supply to receive the corresponding DC or AC power output of the configurable power supply. |
| US09263182B2 |
Control distribution transformer and method of making same
A distribution transformer comprises a sensor system and a communications module. The distribution transformer is configured to convert a first high voltage electricity from a high voltage distribution line to a first low voltage electricity and convey the first low voltage electricity along a low voltage line to an electrical device. The sensor system is configured to determine a temperature of the distribution transformer, and the communications module is configured to transmit a load reduction request along the low voltage line to the electrical device based on the temperature of the distribution transformer. |
| US09263181B2 |
Multi-phase transformer and transformation system
Provided are a multi-phase transformer having an easier-producible structure, and a transformation system wherein a plurality of such transformers are serially connected. Disclosed is a three-phase transformer (Tra) provided with three coils (1u, 1v, 1w) and a pair of magnetic members (21, 22) respectively provided on opposite ends in the axial direction of the coils (1u, 1v, 1w), wherein the coils (1u, 1v, 1w) are respectively provided with first and second sub-coils (11u, 12u; 11v, 12v; 11w, 12w). |
| US09263176B2 |
Conductor pattern and electronic component having the same
Disclosed herein are a conductor pattern of an electronic component formed in an oval coil shape on a magnetic substrate, the conductor pattern including: a straight part; and a curved part connected to the straight part at both sides thereof, wherein a line width of the curved part is smaller than that of the straight part, and an electronic component including the same. With the conductor pattern and the electronic component including the same according to the present invention, the high precision fine line width and the high resolution conductor pattern may be implemented to improve connectivity, thereby improving characteristics and reliability of the electronic component. |
| US09263174B2 |
Sintered cobalt ferrites composite material with high magnetostriction
Disclosed herein is a sintered cobalt ferrite composite material comprising of nano and micron sized powders of cobalt ferrite with high magnetostriction. The present invention further discloses preparation of nano and micron sized powders of cobalt ferrite, in particular, the auto combustion process using glycine as fuel for preparing nano sized cobalt ferrite powders. |
| US09263173B2 |
Method for producing a high-voltage electrical insulator with a mortar including a superplasticizer
A method of manufacturing a high-voltage electrical insulator (1), having at least one metal insulator element (4, 6) cemented to a dielectric insulator element (2) by a cement mortar (5), includes at least one of the following steps: preparing the cement mortar (5) from aluminous cement and sand that are mixed with at least water; assembling the dielectric element (2) with the metal element (4, 6), the mortar (5) being placed between the dielectric insulator element (2) and the metal element (4, 6); and vibrating the dielectric element (2) and the metal element (4, 6) as assembled together, so as to distribute the mortar (5) between the dielectric element and the metal element (2, 4, 6). In order to prepare the mortar (5), an active ingredient of the polymer superplasticizer type based on polyglycol methacrylic acid ester is added, and the vibrating is performed for a duration lying in the range 2 seconds to 20 seconds, and preferably in the range 4 seconds to 15 seconds. |
| US09263170B2 |
Composite material, heating products and method for making
Uniform heating with low voltage electrical power supply is provided by sheet form products as free standing films, coatings, or embedded in laminates, foams and the like and comprising a carbon black/graphite composite dispersed in a plastic carrier. |
| US09263167B2 |
Aluminum alloy wire rod, aluminum alloy stranded wire, coated wire, wire harness and manufacturing method of aluminum alloy wire rod
An aluminum alloy wire rod has a composition consisting of Mg: 0.10 to 1.00 mass %, Si: 0.10 to 1.00 mass %, Fe: 0.01 to 2.50 mass %, Ti: 0.000 to 0.100 mass %, B: 0.000 to 0.030 mass %, Cu: 0.00 to 1.00 mass %, Ag: 0.00 to 0.50 mass %, Au: 0.00 to 0.50 mass %, Mn: 0.00 to 1.00 mass %, Cr: 0.00 to 1.00 mass %, Zr: 0.00 to 0.50 mass %, Hf: 0.00 to 0.50 mass %, V: 0.00 to 0.50 mass %, Sc: 0.00 to 0.50 mass %, Co: 0.00 to 0.50 mass %, Ni: 0.00 to 0.50 mass %, and the balance: Al and incidental impurities. The aluminum alloy wire rod has an average grain size of 1 μm to 35 μm at an outer peripheral portion thereof, and an average grain size at an inner portion thereof is greater than or equal to 1.1 times the average grain size at the outer peripheral portion. |
| US09263162B2 |
Method for manufacturing microstructure
A method is provided for producing a microstructure. The method includes the first step of forming a supporting layer on a base substrate including a silicon substrate provided with recessed sections at a first surface thereof and a metal structure filling the recessed sections so as to come in contact with the metal structure at the first surface, the second step of forming a structure including the metal structure and the supporting layer by selectively etching the silicon substrate to expose at least the surface of the metal structure opposite the surface in contact with the supporting layer from the silicon substrate, and the third step of selectively etching the supporting layer of the metal structure. |
| US09263159B2 |
High radioactivity filter
A high radioactivity filter system is disclosed. The invention utilizes within a container substructure a filter employing a combination of specially selected filtration and ion exchange media and a structural design of equipment for substantially or totally providing and/or rendering Class A waste forms and preventing the formation of Class B, C and GTCC waste forms. The invention also provides both ion exchange and filtration of liquid radioactive wastestreams. |
| US09263153B2 |
Semiconductor storage device, nonvolatile semiconductor memory test method, and medium
According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block. |
| US09263150B2 |
One-time programmable memory
A one-time programmable memory includes a first cell array including a plurality of one-time programmable memory cells, and a second cell array including a plurality of one-time programmable memory cells, wherein the first cell array and the second cell array are programmed separately during a program operation, and read in combination during a read operation. |
| US09263149B2 |
Semiconductor device with OTP memory cell
A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor. |
| US09263145B2 |
Current detection circuit and semiconductor memory apparatus
The invention provides a current detection circuit and a semiconductor memory apparatus using the current detection circuit thereof. The current detection circuit is capable of rapidly sensing the current flowing through a tiny bit line structure. A page buffer/sensing circuit of the invention includes: a transistor TP3 pre-charging a node SNS during a pre-charge period and providing a target constant current to the node SNS during a discharge period; a transistor TN3 pre-charging the bit line according to the voltage pre-charged to the node SNS; and a transistor TP2 connected to the node SNS. The transistor TP2 detects whether or not a current larger than the constant current supplied by the transistor TP3 is discharged from the bit line and outputs a detection result to a node SENSE. |
| US09263142B2 |
Programming a memory cell using a dual polarity charge pump
Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In some embodiments, an apparatus includes an array of memory cells and a dual polarity charge pump. The dual polarity charge pump has a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state, and a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state. |
| US09263140B2 |
Non-volatile semiconductor storage device
For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage. |
| US09263138B1 |
Systems and methods for dynamically programming a flash memory device
The present inventions are related to systems and methods for storing data, and more particularly to systems and methods for writing data to a storage device. |
| US09263137B2 |
NAND array architecture for multiple simutaneous program and read
This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1/10- 1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed. |
| US09263127B1 |
Memory with specific driving mechanism applied on source line
An embodiment of the invention provides a memory. The memory includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a memory cell array. The memory cell array has a plurality of memory cells disposed at the intersections of the word and bit lines to form a matrix of rows and columns, wherein each memory cell comprises a resistive memory device and a transistor. The source lines are each disposed between two word lines, wherein each source line is coupled to source terminals of the transistors. When a RESET operation is applied to a selected memory cell, the voltage level of the source line is pulled up to a first voltage level, and when another operation is applied to the selected memory cell, the source line is grounded. |
| US09263124B2 |
UV sensor with nonvolatile memory using oxide semiconductor films
A ultra-violet sensor has a gate on a substrate, a dielectric formed over the gate and the substrate, an oxide semiconductor formed over the dielectric, and a source electrode and a drain electrode formed at the edges of the oxide semiconductor. A memory device has an array of ultra-violet sensors, each sensor having a gate on a substrate, a dielectric formed over the gate and the substrate, an oxide semiconductor formed over the dielectric, and a source electrode and a drain electrode formed at the edges of the oxide semiconductor, an array of ultra-violet light sources corresponding to the array of ultra-violet sensors, an array of detectors electrically coupled to the array of ultra-violet sensors, driving circuitry attached to the array of sensors and the ultra-violet light sources to allow addressing of the arrays, and a reset mechanism. |
| US09263122B2 |
Data-controlled auxiliary branches for SRAM cell
A circuit includes a first inverter, a second inverter, a first auxiliary branch and a second auxiliary branch. The first and second inverters are cross-coupled to form a first storage node and a second storage node. The first auxiliary branch is coupled to the first storage node and configured to assist the first inverter in holding data based on data stored at the second storage node during a read operation, and assist the first inverter in flipping data based on data to be written to the first storage node during a write operation. The second auxiliary branch is coupled to the second storage node and configured to assist the second inverter in holding data based on data stored in the first storage node during the read operation, and assist the second inverter in flipping data based on data to be written to the second storage node during the write operation. |
| US09263121B2 |
Low power transient voltage collapse apparatus and method for a memory cell
Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node. |
| US09263118B2 |
Semiconductor memory device and method for operating the same
A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation. |
| US09263115B2 |
Semiconductor device
A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse width including a period from starting a first data writing of the resistance variable memory cell by applying a voltage between the first and second terminals to ending the first data writing of the resistance variable memory cell, and measuring a second pulse width of the resistance variable memory cell coupled between the first and the second terminal. The method includes setting longer one of the first and second pulse widths in a first storage area as a pulse width to be used in program. |
| US09263111B2 |
Sub-block disabling in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described. |
| US09263109B2 |
Output driver to drive semiconductor device and memory system
According to one embodiment, an output driver which outputs an output signal to a transmission line, the output driver includes a pre-driver and a main driver. The pre-driver changes the duty ratio of a first drive signal and the duty ratio of a second drive signal to a plurality of patterns in accordance with a control signal. The main driver connects in series a first driver driven by the first drive signal and a second driver driven by the second drive signal. The main driver outputs the output signal to the transmission line from a connection node of the first and second drivers. |
| US09263108B2 |
Semiconductor device
The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential and from before the start timing of a preamble of the two signals. A second comparator circuit compares the level of DQS or DQSB with a reference voltage Vref and outputs a signal ODT_DET representing the result of the comparison. A gate circuit masks the signal DQSIN with a signal EW in a masking state. A control circuit identifies the start timing of the preamble based on ODT_DET, and sets the signal EW to the masking state before the start of the preamble and to an unmasking state from the start timing of the preamble. |
| US09263107B1 |
Load isolation for pad signal monitoring
A driver circuit includes an output driver including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster configured to adjust a duty cycle of a signal provided to the output driver. The driver circuit further includes an isolation module configured to isolate at least one output driver leg of the output driver legs from remaining output driver legs of the output driver legs. The driver circuit further includes a duty cycle monitor configured to monitor an output of the at least one output driver leg when the at least one output driver leg is isolated from the remaining output driver legs, and to provide the monitored output to the duty cycle adjuster. |
| US09263106B2 |
Efficient command mapping scheme for short data burst length memory devices
An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer system perform a method of requesting data from the memory device. This method comprises receiving a plurality of commands for the memory device from the command bus, the memory device clocked by a clock. At least one command of the plurality of commands includes a first command and a second command within a single clock cycle of said clock. At least one of the first command and second command is a data access command. The first command is executed during a first clock cycle and the second command is executed during a second subsequent clock cycle. |
| US09263103B2 |
Method and apparatus for calibrating write timing in a memory system
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship. |
| US09263101B2 |
Semiconductor memory device
A semiconductor memory device includes first and second memory regions configured to store data in a mirrored fashion with respect to each other during a high speed operation period; and a read operation block configured to repeatedly and alternately select the first and second memory regions and read data from a selected memory region, in the case where the first or second memory region is repeatedly selected n read operations of at least two times during the high speed operation period. |
| US09263099B2 |
Semiconductor memory device for reducing standby current
A semiconductor memory device includes a standby voltage providing unit. The standby voltage providing unit is configured to receive an external voltage, primarily clamp and secondarily clamp a predetermined voltage, and provide the predetermined voltage as an internal voltage, during a standby mode. |
| US09263098B2 |
Voltage regulator, memory controller and voltage supplying method thereof
A memory controller of inventive concepts may include an active regulator configured to operate in an active mode and be inactive in a sleep mode, an active logic configured to receive a drive voltage, a power gating switch configured to connect the active regulator to the active logic after a transient state of the active mode, the transient state being an initial time period of the active mode, and a charging circuit configured to charge the active logic during the transient state. |
| US09263094B2 |
Hard disk drive disk separator plate construction
Improving track following performance and reliability in a hard disk drive involves the use of disk separator plates positioned between adjacent recording disks, where a disk separator plate is made of stamped metal with plastic over-molded mounting portions coupled to the metal, thereby reducing the reliability risks associated with the use of fiber-filled materials. |
| US09263092B2 |
Extended diagnostic overlay control for tape storage devices
A method according to one embodiment includes monitoring a plurality of parameters relating to operation of a tape drive to collect data from the operation of the tape drive. A specification of one or more of the parameters to log during one or more collection windows is received. At least some of the data collected from the operation of the tape drive is logged to a memory during the one or more collection windows, where the at least some of the data collected is stored in a plurality of fields. The method further includes dynamically overlaying one or more of the fields with data corresponding to the one or more specified parameters. |
| US09263088B2 |
Data management for a data storage device using a last resort zone
A data storage device (DSD) includes a non-volatile memory (NVM) media for storing data. A last resort zone of the NVM media is associated with a higher risk of data loss or data corruption than other portions of the NVM media and is reserved as unavailable for storing data. It is determined whether a current data storage capacity and/or an environmental condition for the NVM media has reached a threshold. The last resort zone is set as available for storing data if it is determined that the threshold has been reached and data is written in the last resort zone. |
| US09263086B2 |
Magnetization control for magnetic shield in magnetic recording head
A hard disk drive (HDD) is described which includes a magnetic field-generating device in the vicinity of a load/unload ramp such that the write head moves into a magnetic field generated by the device while the head is being unloaded from disk, whereby the magnetic field pins in a predominant direction the direction of magnetization of a magnetic shield associated with the write head, and away from the direction toward the disk. Recording magnetic field leakage associated with the shield is thereby suppressed and corresponding far track interference is inhibited. |
| US09263083B2 |
Recording and reproducing apparatus
A recording and reproducing apparatus of this disclosure includes, reader writer 5 which acquires magazine identifying information and capacity information from RF tag 13 provided with magazine, information storage unit 6 which stores contents information recorded on optical discs 12 and the magazine identifying information and the capacity information acquired by the information acquiring unit 5, information comparing unit 7 which compares the capacity information acquired by reader writer 5 and the capacity information stored in information storage unit 6. When two pieces of the capacity information compared by information comparing unit 7 match, the contents information stored in information storage unit 6 is displayed on display unit 9. When two pieces of the capacity information compared by information comparing unit 7 are different, the contents information is read out from optical discs 12 by controlling drive 4, and the read-out contents information is displayed on display unit 9. |
| US09263080B2 |
Method of aligning light sources in an optical pickup device, and optical pickup and optical disc drive employing the method
Provided is an optical pickup device and a method of aligning a twin-light source in an optical disc drive. The method operates two light emitting chips in the light source simultaneously to cause two laser beams to be transmitted through a grating element at the same time. Location errors and rotation errors of the two light emitting chips with respect to the grating element may be corrected while monitoring the laser beams transmitted through the grating element. |
| US09263078B2 |
Patterning of magnetic thin film using energized ions
A method for patterning a magnetic thin film on a substrate includes: providing a pattern about the magnetic thin film, with selective regions of the pattern permitting penetration of energized ions of one or more elements. Energized ions are generated with sufficient energy to penetrate selective regions and a portion of the magnetic thin film adjacent the selective regions. The substrate is placed to receive the energized ions. The portions of the magnetic thin film are rendered to exhibit a magnetic property different than selective other portions. A method for patterning a magnetic media with a magnetic thin film on both sides of the media is also disclosed. |
| US09263074B2 |
Devices including at least one adhesion layer
Devices that include a near field transducer (NFT), the NFT having at least one external surface; and at least one adhesion layer positioned on at least a portion of the at least one external surface, the adhesion layer including arsenic (As), antimony (Sb), selenium (Se), tellurium (Te), polonium (Po), bismuth (Bi), sulfur (S), or combinations thereof. |
| US09263073B2 |
Magnetic tape storage medium
A magnetic tape storage medium includes at least one servo band with at least two sub-bands along a longitudinal extension of the medium. Servo bursts are written to the sub-bands to determine positional information of the medium. A first of the sub-bands includes a first burst with at least one servo stripe inclined at a first non-zero angle with respect to a direction orthogonal to the longitudinal extension of the medium followed by a second burst comprising at least one servo stripe inclined at a second non-zero angle with respect to the direction orthogonal to the longitudinal extension of the medium, which second angle is different from the first angle. A second of the sub-bands includes a first burst having at least one servo stripe followed by a second burst having at least one servo stripe, the first and the second bursts parallel to each other. |
| US09263071B1 |
Flat NFT for heat assisted magnetic recording
The present disclosure generally relates to an EAMR head having a plasmonic bulk metal plate adjacent thereto. The waveguide core has a trapezoidal shaped cross-section, when viewed from the ABS, and the plasmonic bulk metal plate is disposed adjacent the short side of the trapezoid. The plasmonic bulk metal plate reduces the temperature of the NFT. |
| US09263067B1 |
Process for making PMR writer with constant side wall angle
A process for manufacturing a writer main pole for a perpendicular magnetic recording system is provided. The writer pole may have a constant sidewall angle from the ABS to yoke and may be formed out of an insulating material and a magnetic material. The sidewall angle of the yoke region may be adjusted during manufacture. The ABS region may correspond to the magnetic material and the yoke region may correspond to the insulating material. The insulating material may comprise Alumina. The magnetic material may comprise a NiFe alloy. |
| US09263063B2 |
Switching off DTX for music
The invention relates to a method for disabling a discontinuous transmission node DTX of a speech encoder if a music signal is detected in a call input signal. The music signal is detected by determining an activity factor corresponding to the relation of sound signal periods relative to scheme signal periods. If the activity factor is higher than a specified activity factor, the DTX is disabled. |
| US09263061B2 |
Detection of chopped speech
Methods and systems are provided for detecting chop in an audio signal. A time-frequency representation, such as a spectrogram, is created for an audio signal and used to calculate a gradient of mean power per frame of the audio signal. Positive and negative gradients are defined for the signal based on the gradient of mean power, and a maximum overlap offset between the positive and negative gradients is determined by calculating a value that maximizes the cross-correlation of the positive and negative gradients. The negative gradient values may be combined (e.g., summed) with the overlap offset, and the combined values then compared with a threshold to estimate the amount of chop present in the audio signal. The chop detection model provided is low-complexity and is applicable to narrowband, wideband, and superwideband speech. |
| US09263057B2 |
Time warp activation signal provider, audio signal encoder, method for providing a time warp activation signal, method for encoding an audio signal and computer programs
An audio encoder has a window function controller, a windower, a time warper with a final quality check functionality, a time/frequency converter, a TNS stage or a quantizer encoder, the window function controller, the time warper, the TNS stage or an additional noise filling analyzer are controlled by signal analysis results obtained by a time warp analyzer or a signal classifier. Furthermore, a decoder applies a noise filling operation using a manipulated noise filling estimate depending on a harmonic or speech characteristic of the audio signal. |
| US09263056B2 |
Method of simultaneously transforming a plurality of voice signals input to a communications system
A method of simultaneously transforming at least two input voice signals xi of a communications system (30), each input voice signal xi being received at a specific reception frequency Fi and corresponding to the voice of a remote party communicating with a user of the communications system (30). During an initialization stage, a transformation Ti is allocated to at least one reception frequency Fi of the input voice signals xi, and during a utilization stage, transformations Ti are applied simultaneously to the input voice signals xi as a function of the reception frequencies Fi, modifying at least one characteristic of each of the input voice signals xi. Thus, the voice of each remote party in communication with the user of the communications system (30) is modified artificially by a transformation Ti, thereby making it easier for the user to perceive and discriminate between simultaneous voices from the remote parties. |
| US09263054B2 |
Systems and methods for controlling an average encoding rate for speech signal encoding
A method for controlling an average encoding rate by an electronic device is described. The method includes obtaining a speech signal. The method also includes determining a first average rate. The method further includes determining a first threshold based on the first average rate. The method additionally includes controlling the average encoding rate by determining at least one other threshold based on the first threshold. The method also includes sending an encoded speech signal. |
| US09263052B1 |
Simultaneous estimation of fundamental frequency, voicing state, and glottal closure instant
A method and system is disclosed for simultaneously determining glottal closure instants (GCIs), fundamental frequency (F0s), and voicing state of a speech signal. A speech signal may be processed to determine a sequence of candidate GCIs. For each candidate GCI, a set of candidate F0s may be determined. A lattice of hypotheses may be constructed, where each lattice point is a hypothesis of a concurrence of a candidate GCI, a candidate F0, and voicing state. Each given hypothesis may also include a score of the candidate GCI, F0, and voicing state for evaluating a cost of the given hypothesis and a cost of connections between the given hypothesis and other hypotheses of the lattice. Dynamic programming may be used to determine a least-cost path through the lattice, and backtracking across the path may be used to determine an optimal set of GCIs, F0s and voicing states of the speech signal. |
| US09263050B2 |
Allocation, by sub-bands, of bits for quantifying spatial information parameters for parametric encoding
A method is provided for allocating bits for quantifying spatial information parameters by frequency sub-band for parametric encoding/decoding of a multichannel audio stream representative of a soundstage consisting of a plurality of sound sources. The method includes a step of quantifying or inversely quantifying, by frequency sub-band, spatial information parameters for the sound sources of the soundscape. The method further includes: assessing a spatial resolution of the current sub-band on the basis of the spectral properties of the sub-band; and determining a number of bits to be allocated to the current sub-band, the number of bits to be allocated being inversely proportional to the estimated spatial resolution. Also provided is a device for allocating quantification bits implementing the above-described method. |
| US09263049B2 |
Artifact reduction in packet loss concealment
Various techniques are disclosed for improving packet loss concealment to reduce artifacts by using audio character measures of the audio signal. These techniques include attenuation to a noise fill instead of attenuation to silence, varying how long to wait before attenuating the extrapolation, varying the rate of attenuation of the extrapolation, attenuating periodic extrapolation at a different rate than non-periodic extrapolation, and performing period extrapolation on successively longer fill data based on the audio character measures, adjusting weighting between periodic and non-periodic extrapolation based on the audio character measures, and adjusting weighting between periodic extrapolation and non-periodic extrapolation non-linearly. |
| US09263048B2 |
Word-level correction of speech input
The subject matter of this specification can be implemented in, among other things, a computer-implemented method for correcting words in transcribed text including receiving speech audio data from a microphone. The method further includes sending the speech audio data to a transcription system. The method further includes receiving a word lattice transcribed from the speech audio data by the transcription system. The method further includes presenting one or more transcribed words from the word lattice. The method further includes receiving a user selection of at least one of the presented transcribed words. The method further includes presenting one or more alternate words from the word lattice for the selected transcribed word. The method further includes receiving a user selection of at least one of the alternate words. The method further includes replacing the selected transcribed word in the presented transcribed words with the selected alternate word. |
| US09263046B2 |
Distributed dictation/transcription system
A distributed dictation/transcription system is provided. The system provides a dictation manager having a data port to receive and transmit audio signals. The dictation manager includes a dictation server selector to a dictation server to transcribe the audio based on whether the dictation server already has a user profile uploaded. |
| US09263044B1 |
Noise reduction based on mouth area movement recognition
A computing device can capture video data of at least a portion of a mouth area (e.g., mouth, lips, tongue, chin, jaw) of a user of the device. The computing device can also capture sound data including a voice of the user as well as noise (e.g. background noise). The video data can be processed to detect a movement of the portion of the mouth area. The movement of the portion of the mouth area can be analyzed and compared with mouth area movement models characteristic of oral communication (e.g., speech, song). If the movement of the portion of the mouth area corresponds to at least one model characteristic of oral communication, then the movement indicates that the user is likely engaging in oral communication. Noise reduction can be applied and/or increased on the captured sound data to reduce noise and in turn enhance the user's voice. |
| US09263041B2 |
Channel detection in noise using single channel data
Methods related to Generalized Mutual Interdependence Analysis (GMIA), a low complexity statistical method for projecting data in a subspace that captures invariant properties of the data, are implemented on a processor based system. GMIA methods are applied to the signal processing problem of voice activity detection and classification. Real-world conversational speech data are modeled to fit the GMIA assumptions. Low complexity GMIA computations extract reliable features for classification of sound under noisy conditions and operate with small amounts of data. A speaker is characterized by a slow varying or invariant channel that is learned and is tracked from single channel data by GMIA methods. |
| US09263039B2 |
Systems and methods for responding to natural language speech utterance
Systems and methods are provided for receiving speech and non-speech communications of natural language questions and/or commands, transcribing the speech and non-speech communications to textual messages, and executing the questions and/or commands. The invention applies context, prior information, domain knowledge, and user specific profile data to achieve a natural environment for one or more users presenting questions or commands across multiple domains. The systems and methods creates, stores and uses extensive personal profile information for each user, thereby improving the reliability of determining the context of the speech and non-speech communications and presenting the expected results for a particular question or command. |
| US09263038B2 |
System and method for analyzing and classifying calls without transcription via keyword spotting
A facility and method for analyzing and classifying calls without transcription via keyword spotting is disclosed. The facility uses a group of calls having known outcomes to generate one or more domain- or entity-specific grammars containing keywords and related information that are indicative of particular outcome. The facility monitors telephone calls by determining the domain or entity associated with the call, loading the appropriate grammar or grammars associated with the determined domain or entity, and tracking keywords contained in the loaded grammar or grammars that are spoken during the monitored call, along with additional information. The facility performs a statistical analysis on the tracked keywords and additional information to determine a classification for the monitored telephone call. |
| US09263036B1 |
System and method for speech recognition using deep recurrent neural networks
Deep recurrent neural networks applied to speech recognition. The deep recurrent neural networks (RNNs) are preferably implemented by stacked long short-term memory bidirectional RNNs. The RNNs are trained using end-to-end training with suitable regularization. |
| US09263035B2 |
Promoting voice actions to hotwords
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for designating certain voice commands as hotwords. The methods, systems, and apparatus include actions of receiving a hotword followed by a voice command. Additional actions include determining that the voice command satisfies one or more predetermined criteria associated with designating the voice command as a hotword, where a voice command that is designated as a hotword is treated as a voice input regardless of whether the voice command is preceded by another hotword. Further actions include, in response to determining that the voice command satisfies one or more predetermined criteria associated with designating the voice command as a hotword, designating the voice command as a hotword. |
| US09263033B2 |
Utterance selection for automated speech recognizer training
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a set of training utterances. The methods, systems, and apparatus include actions of obtaining a target multi-dimensional distribution of characteristics in an initial set of candidate utterances and selecting a subset of the initial set of candidate utterances based on speech recognition confidence scores associated with the candidate utterances. Additional actions include selecting a particular candidate utterance from the subset of the initial set of utterances and determining that adding the particular candidate utterance to a set of training utterances reduces a divergence of a multi-dimensional distribution of the characteristics in the set of training utterances from the target multi-dimensional distribution. Further actions include adding the particular candidate utterance to the set of training utterances. |
| US09263023B2 |
Audio speaker with spatially selective sound cancelling
A system and method for reproducing audio sound. Audio sound, based on an audio signal, is emitted within a space comprising an audio beamwidth. Modulated ultrasonic sound energy based on a modulated ultrasonic sound signal is emitted in an ultrasonic sound direction within an ultrasonic beamwidth that is less than and within the audio beamwidth. The modulated ultrasonic sound signal is generated such that the emitted modulated ultrasonic sound energy creates an audible cancellation sound with an amplitude substantially equal to an amplitude of the audio sound at a point within the ultrasonic beamwidth so as to combine with and cancel the audio sound at the point by being substantially out of phase with the audio sound along the ultrasonic sound direction. |
| US09263017B2 |
Modular electronic musical keyboard instrument
In one aspect, the present invention is directed to a modular electronic musical keyboard instrument, comprising: an array of separate keyboard segments (30, 32), each comprising a piano keyboard (20) in a range of one octave; a control system, for converting a keystroke of each key in the array of keyboard segments to a note sound in a level corresponding to the order of the key in the array of keyboard segments; octave order setting means (22), for determining to the control system the order of each keyboard segment in the array of keyboard segments; communication means of each of the keyboard segments with the control system; and connection means (12, 14) with another keyboard segment. |
| US09263012B2 |
Cymbal striking surface
According to some aspects, a cymbal is provided comprising a metal plate having a plurality of perforations therein, and a coating of a resilient material in contact with the metal plate that covers at least a portion of the surface of the metal plate. According to some aspects, a cymbal is provided comprising a metal plate, and a dampening element attached to at least a portion of the circumference of the metal plate. According to some aspects, a method of producing a cymbal is provided, comprising forming a metal plate having a plurality of perforations therein, and forming a resilient material over at least a portion of the surface of the metal plate and in contact with the metal plate. |
| US09263011B2 |
Custom printed removable bass drum head cover
A removable bass drum head cover with a printed display is provided. The drum head cover may be releasably attachable to a bass drum head. In certain embodiments, the drum head cover may be releasably attachable to the bass drum head cover by a hook and loop fastener. Therefore, drummers may easily interchange the designs, artwork, and band names displayed on their bass drum heads. |
| US09263010B2 |
Multi-tonal box drum kit
The present invention generally relates to cajón drums. Specifically, this invention relates to a multi-tonal box drum kit that provides a form factor that is easy and convenient to use while producing the tones and sounds of a full drum kit or some subset thereof. |
| US09263002B2 |
Application and user interface framework interaction
Interaction between an application, a user interface framework, and a graphics module to render a portion of an application surface. The application requests a surface corresponding to a particular range of the application surface from the user interface framework. In response, the user interface framework provides the requested ranged surface to the application. The application instructs the graphics module to populate the ranged surface by drawing into the ranged surface. The application then instructs the user interface framework to compose the ranged surface using the drawn ranged surface and other information available to the user interface framework. The user interface framework composing a composed surface using the drawn surface provided by the application, and additional information available to the user interface framework. The user interface framework may cache information from previously composed surface to allow for faster re-rendering should those portions later come into view on the display. |
| US09263001B2 |
Display control device
A display control device of the present disclosure is a device for controlling a video image displayed on a display unit. The display control device includes a controller configured to generate an image including a first image and a second image superimposed on the first image to display the image on the display unit. The controller performs control to display the first image of a first field angle on the display unit when a first mode is set, and performs control to display the first image of a second field angle which is wider than the first field angle on the display unit when a second mode is set. The second mode is a mode for setting a region of the second image in a region of the first image of the second field angle. |
| US09262995B2 |
Image projection apparatus and control method therefor
The image projection apparatus of the present invention includes a light source that outputs coherent light; a phase modulator that performs phase modulation on the light output from the light source to create a Fourier transform image; an amplitude modulator that performs amplitude modulation on the Fourier transform image in accordance with an image signal; a projection optical system that projects the light that has been amplitude modulated, and a controller that divides the image represented by the image signal into a plurality of divided images, determines the target luminance value of each of the areas of the Fourier transform image that is divided corresponding to the division of the image, based on the image signal, and outputs phase data indicating the amount of phase modulation so as to make the luminance value of each area of the Fourier transform image acquire the target luminance value of the associated area. |
| US09262982B2 |
Timing controller for liquid crystal panel
A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time. |
| US09262979B2 |
Display device and method for correcting gamma deviation
A display device may include a display panel that includes a first region and a second region. The display device may include a controller that may receive a first gamma value and a second gamma value, use the first gamma value or a third gamma value to generate first image data, use the first gamma value and the second gamma value to generate a fourth gamma value, and use the fourth gamma value to generate second image data. The display device may include a data driver that may use the first image data and the second image data to generate a first data voltage set and a second data voltage set. The first region may use the first data voltage set to display a first portion of an image. The second region may use the second data voltage set to display a second portion of the image. |
| US09262978B2 |
Driving circuit of a semiconductor display device and the semiconductor display device
There are provided a driving circuit of a semiconductor display device which can obtain an excellent picture without picture blur (display unevenness) and with high fineness/high resolution, and the semiconductor display device. A buffer circuit used in the driving circuit of the semiconductor display device is constituted by a plurality of TFTs each having a small channel width, and a plurality of such buffer circuits are connected in parallel with each other. |
| US09262965B2 |
System and methods for power conservation for AMOLED pixel drivers
A system is provided for conserving energy in an AMOLED display having pixels that include a drive transistor and an organic light emitting device, and an adjustable source of a supply voltage for the drive transistor. The system monitors the content of a selected segment of the display, sets the supply voltage to the minimum supply voltage required for the current content of the selected segment of the display, determines whether the number of pixels requiring a supply voltage larger than the set value is greater than a predetermined threshold number, and, when the answer is negative, reduces the supply voltage by a predetermined step amount. |
| US09262963B2 |
Display unit and electronic apparatus
A display unit provided with a display panel including a light emitting element and a pixel circuit for each pixel, and a drive circuit configured to drive each of the pixels. The pixel circuit includes: a first transistor configured to sample a voltage corresponding to a picture signal, the first transistor having characteristics that a parasitic capacitance at a time when the first transistor is turned off is decreased as magnitude of negative bias applied to a gate voltage is increased; a second transistor configured to control a current flowing through the light emitting element based on magnitude of the voltage sampled by the first transistor; and a retention capacitance configured to retain the voltage sampled by the first transistor. |
| US09262960B2 |
Organic light emitting diode display apparatus with power circuit to accelerate a voltage level
An organic light emitting diode (OLED) display apparatus includes a power circuit and a pixel. The power circuit serves to provide a first voltage. The pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and an OLED. During a programming period, a first terminal of the capacitor receives a data voltage through the turned-on first transistor, a first terminal of the second transistor receives the first voltage, a control terminal of the second transistor is coupled to a second terminal of the capacitor and coupled to a second terminal of the second transistor through the turned-on third transistor, and the power circuit regulates a voltage level or a current of the first voltage to accelerate a voltage level of the control terminal of the second transistor to reach a target voltage. |
| US09262958B2 |
Control head with electroluminescent panel in land mobile radio
An exemplary land mobile radio control head and method are provided. In one embodiment, the control head has the capability to utilize halo light of the control head to implement a multi-function indicator that communicates a state of the land mobile radio. In another embodiment, the control head has the capability to provide buffer images constructed from data received from the land mobile radio into a video stream for rendering on an electroluminescent display. In another embodiment, the control head provides the capability for a user to modify a configuration stored on the land mobile radio that defines one of several display modes to be utilized in generating data for use in forming images to be rendered on an electroluminescent display. |
| US09262956B2 |
Display device, data processing apparatus, and related method
A data processing apparatus includes a diagonal detector, a first processor, and a second processor. The diagonal detector may determine whether a red-blue data set includes data for controlling a display device to display any diagonal line, the display device including subpixels arranged in first-type lines and second-type lines that are alternately disposed, the red-blue data set including 9 data values that correspond to 9 subpixels among the subpixels, the 9 subpixels forming a 3-by-3 array that includes a center subpixel, the 9 data values including a center data value that corresponds to the center subpixel. The first/second processor may process the center data value using a first/second coefficient to produce a first/second value that corresponds to the center subpixel if the center subpixel is in the first-type/second-type lines. |
| US09262951B2 |
Stereoscopic 3D display systems and methods for improved rendering and visualization
Techniques for stereoscopic 3D display systems with active shuttered glasses are provided which overcomes the real-world limitations of sample/load & hold displays, resulting in greater overall brightness, while reducing crosstalk between each eye perspective. In some embodiments, a first left-eye perspective frame and a first right-eye frame are determined from image data. A first composite frame of a first type is then created. This first composite frame of the first type comprises one or more left-eye pixel values from the first left-eye frame and one or more right-eye pixel values from the first right-eye frame. The first composite frame of the first type is outputted to the display area. This may also include use of scanning backlight synchronized to loading/hold of display in conjunction with the composite frame. |
| US09262949B1 |
Portable collapsible fabric-tensioned sign assembly
A portable collapsible sign assembly including a fabric covering and support frame which is adjustable between a collapsed and expanded position. When the sign assembly is expanded, or in its deployed state, the fabric covering and support frame possess a connective tension relationship with respect to one another which creates and supports both the sign assembly display sign and base in a stable manner. The fabric covering engagement with the support frame enables the entire sign assembly, including both the display sign and assembly base, to be simultaneously deployed in one user-initiated motion. |
| US09262943B2 |
CPR mannequin
A CPR training mannequin includes a humanoid torso, the torso composed of a material having a degree of transparency. A humanoid head is connected to the torso and has a mouth opening connected to a ventilation tube within the head. The torso is supported by resilient elements from the base to simulate resistance to chest compressions. A simulated heart and simulated lungs are arranged within the torso and are visible through the front surface of the torso. Sensors measure the air flow during CPR ventilation and depth of CPR chest compressions. Lights within the heart, brain and lungs indicate the chest compressions and ventilation are adequate to resuscitate the simulated victim. |
| US09262935B2 |
Systems and methods for extracting keywords in language learning
Systems, methods, and products for language learning that may extract text from various resources having text, using various natural-language processing features, which can be combined with custom-designed learning activities to offer a needs-based, adaptive learning methodology. The system may receive a resource, extract keywords pedagogically valuable to non-native language learning and academic exercises. Metadata describing various aspects of resources from which keywords are extracted may be associated with keywords. Metadata describing various aspects of keywords may also be associated with keywords. Extracted keywords may be stored into a keyword store along with any metadata associated with keywords. |
| US09262934B2 |
Commercial transportation information presentation techniques
A portable wireless data transfer and display device includes a user interface, a display, a processor, and a short-range wireless communication module configured to wirelessly receive vehicle data, in real-time, from a data acquisition device mounted inside a vehicle when in close proximity to the data acquisition device. The device is configured to receive an input of driver information and driver communications from a user via the user interface. The short-range wireless communication module is configured to communicate two ways, in real-time, the driver communications via a long-range wireless network. The device is configured to process into a trip schedule at least one of: the vehicle data, the driver information, and the driver communications via the processor. The device is further configured to present the trip schedule and the driver communications to the user via the display. |
| US09262933B2 |
Lateral avoidance maneuver solver
A system on-board an unmanned aerial vehicle for controlling a lateral maneuver to avoid a loss of separation between the unmanned aerial vehicle and an intruder into its airspace. The system receives as inputs the desired miss distance, desired bank angle, state vectors for the unmanned aerial vehicle, wind, and an intruder, and a target vector; and outputs a lateral route change which will achieve the desired miss distance and return the unmanned aerial vehicle back to path. In one embodiment, the system comprises a computer programmed with software that runs automatically and guides the unmanned aerial vehicle to perform a lateral maneuver that avoids loss of separation. In another embodiment, the software runs automatically and advises a pilot on the ground (who is flying the drone by remote control) that a maneuver is about to happen, which maneuver the pilot can either accept or reject. |
| US09262931B2 |
System and method for graphically generating an approach/departure course
A system and method for graphically creating an approach course on a navigation display is provided. A processor operatively coupled to a display and is configured to generate an approach course by (1) generating a graphical representation of at least one terminal area procedure, (2) selecting the at least one terminal area procedure on the display, and (3) displaying the approach course including the at least one terminal area procedure. The approach course is then accepted and inserted into a flight plan. |
| US09262930B2 |
Arrival Traffic scheduling system incorporating equipage-dependent in-trial spacing
Systems and methods for generating arrival traffic schedules incorporating equipage-dependent in-trail spacing (time or distance). An arrival management system has a ground-based scheduling tool that applies customized spacing buffers between in-trail aircraft depending on the types of FMS equipage onboard aircraft sequence pairs. |
| US09262929B1 |
Ground-sensitive trajectory generation for UAVs
Embodiments described herein may help to automatically create flight plans that incorporate information regarding a number of different societal considerations. An illustrative computer-implemented method may involve receiving societal-consideration data for a plurality of geographic areas over which unmanned aerial vehicles (UAVs) are deployable. For a given geographic area from the plurality of geographic areas, the societal-consideration data may include one or more land-use indications for the geographic area that are indicative of a type of land use in the geographic area. The method may also involve, for each of one or more of the plurality of geographic areas: applying a cost function to the one or more land-use indications for the geographic area to determine a societal-consideration cost of UAV flight over the geographic area; and sending an indication of the determined societal-consideration cost to a computer-based flight planner. |
| US09262925B2 |
Vehicle display apparatus
A vehicle display apparatus includes a plurality of display devices that superpose and display a plurality of pieces of information by displaying information at each position of a plurality of different positions in a predetermined direction towards the front of a vehicle that can be viewed by a driver of the vehicle, and includes as at least one of the plurality of display devices, an attention attracting display device that displays as the information, attention attracting information on the nearest side to the driver in the predetermined direction. |
| US09262923B2 |
Blind spot detection system
A blind spot detection system for a vehicle includes a vehicle information detecting module for obtaining at least one vehicle information of the vehicle corresponding to an external environment, an alarm for generating an alarm signal, a plurality of sensors each for emitting a radio signal and receiving a reflecting signal of the transmitted radio signal to detect whether an object exists within a specific range and generate a detection result accordingly, and a control module for controlling the alarm to generate the alarm signal according to the at least one vehicle information and a plurality of detection results generated by the plurality of sensors. |
| US09262919B2 |
Street lamp for providing safe driving information and system for providing safe driving information using street lamp
A street lamp for providing the safe driving information comprises: a main lighting portion for lighting a road; a vehicle reception portion for receiving an accident or malfunction occurrence signal from a vehicle in an accident or which is malfunctioning; a control portion for generating accident or malfunction recognition signals that can be distinguished, in accordance with the reception of the accident or malfunction occurrence signal; and a vehicle transmitting portion for selectively transmitting the accident or malfunction occurrence signal to vehicles in front and behind the location of the accident or the malfunction. |
| US09262917B2 |
Safety directional indicator
Provided is a safety directional indicator to improve highway safety. Embodiments of the invention include devices for guiding a driver of a vehicle in a desired direction, typically away from highway workers, pedestrians, curbs, and opposing lanes of traffic. Specifically included is a safety directional indicator system comprising a flexible belt with a plurality of light transmitting bars disposed along the belt and having a plurality of LEDs disposed at one elongated end of each light transmitting bar and in operable communication with a control system for illuminating the LEDs in a manner to indicate a direction for traffic. Safety devices according to the invention can be stand-alone devices, devices capable of being attached to objects or structures at a highway scene, or configured to be worn on a person's body. An object of the safety devices according to embodiments of the invention is to increase driver awareness of highway situations especially during conditions of restricted visibility. |
| US09262913B2 |
Communication device
A mobile device includes a position sensing unit, a remote control information obtainment unit, and a storage unit. Position information obtained by the position sensing unit is stored in the storage unit in association with remote control information. The mobile device further includes a directional space obtainment unit and an apparatus specification unit. The mobile device recognizes a direction pointed by a user using the mobile device, and enables operation of a terminal apparatus existing in the pointing direction. |
| US09262908B2 |
Method and system for alerting contactees of emergency event
The system of the present disclosure can determine, based on a satellite positioning system-based location of a communication device associated with a selected person and/or presence information associated with the selected person, that the selected person is currently in or will be in an area that has been or may be impacted by an emergency event and, in response, contact a communication device of the selected person to provide information related to the emergency event. |
| US09262907B2 |
Methods and apparatus for centralized and decentralized emergency alert messaging
Apparatus and methods for providing emergency alert system (EAS) data to subscribers of a content-based network for multiple locations including via mobile devices. In one embodiment, the apparatus comprises a server performing real-time receipt and encapsulation of the EAS data, transport of the EAS data to client devices over an IP or other packet-switched network, and use of applications running on the client devices to decode and display the EAS data. In one variant, a centralized EAS (CEAS) entity is used to aggregate and distribute EAS messages to video registration servers (VRS), which use stored client device data and user preferences to map delivery of relevant EAMs over the IP network. In another variant, instant messaging (IM) infrastructure is used to deliver and display at least portion of the EAS data via a separate transport process. |
| US09262906B2 |
Processing sensor data
Methods, systems, computer-readable media, and apparatuses for processing sensor data are presented. In some embodiments, a security server may receive sensor data from one or more sensors that are located at a premises. Subsequently, the security server may classify a first portion of the received sensor data as critical sensor data, (e.g., based on the first portion of the received sensor data being associated with a critical function). In addition, the security server may classify a second portion of the received sensor data as non-critical sensor data (e.g., based on the second portion of the received sensor data being associated with a non-critical function). Thereafter, the security server may process the critical sensor data, and further may provide the non-critical sensor data to a network server for processing. |
| US09262901B1 |
Identification system and method of use
A marking and identification system and method includes a dispersing device configured to disperse marker therefrom when in an activated mode. An activating device is configured to arm the dispersing device from an inactivated mode wherein the dispensing device does not disperse marker to the activated mode. A triggering device is configured to operate the dispersing device and disperse marker when in the activated mode. The marker can be identified at a later time to positively identify a person that triggered the marking and identification system. |
| US09262897B2 |
Image information management system
An image information management system includes: a reading device which reads unique information from a storage medium in which the unique information is stored; an imaging device which automatically starts shooting a video at a time of detecting a change of a picture image in an image area; and a processing device which includes a database which receives the unique information read by the reading device and the image information shot by the imaging device and associates the unique information and the image information to store the unique information and the image information. The processing device includes a control unit which associates the unique information and the image information to store the unique information and the image information in the database in a case of receiving the unique information and the image information, and which associates the image information and identification information indicating that no unique information is received to store the image information and the identification information in the database in a case of receiving only the image information from the imaging device and no unique information from the reading device. |
| US09262896B1 |
Transportation security system and associated methods
A security system for monitoring a shipping container being transported on a cargo transport vehicle and methods for making and using same. A mounting device removably couples a container security device (CSD) to the cargo container. Monitoring cargo inside the container and detecting vehicle intrusions and container damage, the CSD includes an anti-tamper sensor, a microcontroller, a communication device, and a plurality of accelerometers and strain gages. The microcontroller generates an alarm signal based on output data from the anti-tamper sensor and records container events. The anti-temper sensor undergoes individual and integrated sensor processing procedures; whereas, the integrated sensor processing procedure determines a container alert status. The accelerometers and strain gages define a moment of inertia of the cargo container. Communicating with a telecommunications network, a network operations center of the security system receives data from the CSD for storage and creating an archive of the container events. |
| US09262895B2 |
Gaming system, gaming device, and method for providing a cascading symbols game having magnetic symbols and target symbols
A gaming system displays one of a plurality of symbols in each of a plurality of symbol positions, at least one of the plurality of symbols being a target symbol for establishing a direction of shifting and at least one of the plurality of symbols being a magnetic symbol for shifting toward a target symbol. If any generated magnetic symbol is associated with a generated target symbol, the gaming system shifts that magnetic symbol toward the associated target symbol, resulting in an empty symbol position. The gaming system fills the empty symbol position by shifting a displayed symbol or by generating one of the plurality symbols and repeats until no magnetic symbol is associated with a target symbol. The gaming system provides an award for any displayed winning symbol combination. The gaming system removes symbols from each winning combination, fills the empty symbol positions, and repeats as above. |
| US09262891B2 |
Method and apparatus for dynamically selecting a multiplier and dynamically applying the multiplier to a limited number of paylines among a plurality of pre-defined paylines
A gaming method for adding a bonus feature to a main game comprising: providing a display screen comprised of cells arranged in rows and columns; providing a plurality of paylines, each payline comprising one cell from a plurality of columns; automatically and randomly selecting a multiplier value from among a plurality of multiplier values; automatically and randomly applying the selected multiplier value to a limited number of paylines to create one or more selected multiplier paylines; and displaying the multiplier value and the selected multiplier payline(s) to the user on the display screen. |
| US09262890B2 |
Customizing player-generated audio in electronic games
Methods and apparatuses for customizing player-generated audio in electronic games are provided. Sound generated by a player may be recorded in an audio clip. A modification is selected by a player, and the modification is applied to the audio clip. The modified audio clip is associated with a game event designated by the player. When the designated game event is detected, the associated audio clip may be played. In some embodiments, playing the modified audio clip includes broadcasting the modified audio clip to another player in a network. |
| US09262889B2 |
Competitive gaming method and system
Disclosed is gaming apparatus, which may be a gaming system and a method of gaming implemented on gaming apparatus. A plurality of linked gaming machines are monitored for the occurrence of a first event. The number of occurrences of the first event for each gaming machine is recorded. On the occurrence of a second event, a bonus is awarded on each said gaming machine on which at least one monitored occurrence of the first event has occurred, the bonus award being dependent on the number of occurrences of the first event. |
| US09262881B2 |
Vehicular portable device
A portable device for a vehicle includes a short range communication antenna, a near field communication antenna, and a housing case. The short range communication antenna is utilized in a short range wireless communication with a communication device equipped to a vehicle. The near field communication antenna is utilized in a near field wireless communication. The short range communication antenna is disposed in the housing case. The near field communication antenna is disposed on the housing case by decorative printing. A communicable range of the short range wireless communication is longer than a communicable range of the near field wireless communication. |
| US09262874B2 |
Real-time performance models for vessels
A computer implemented method, apparatus, and computer program product for real-time creation of vessel performance models. Performance inputs are received from a set of sensors during a voyage of a vessel. The performance inputs are data associated with a performance of the vessel during the voyage. A real-time performance model is generated during the voyage using a subset of the performance inputs. A predicted value for velocity made good is identified for the vessel using the real-time performance model. |
| US09262873B2 |
Systems and methods for processing vehicle data to report performance data interchangeably
Systems and methods to process vehicle operation data are described. A data module associated with a vehicle can collect a set of metrics relating to the operation of the vehicle, as well as events related to an operator's interaction with the vehicle. The data module can correlate the set of metrics with the events to generate a correlated set of data. A user can request various contexts in which to view the data, such as via a vehicle context or an operator context. The data module can generate, using the correlated set of data, a data view according to the request. Further, the correlated set of data and the various contexts can be updated on a real-time basis. |
| US09262866B2 |
Augmented reality methods and systems including optical merging of a plurality of component optical images
The present disclosure provides augmented reality methods and systems where two or more component optical images are optically overlaid via one or more beam splitters to form composite optical images. In some embodiments a second component optical image is an electronic optical image (an image from an electronically controlled emission source) while the first component optical image is one of a physical optical image (an image of a physical object from which diffuse reflection occurs), an electronic optical image, an emission optical image (an image from a non-electronic source that emits radiation), or a hybrid optical image (composed of at least two of a physical optical image, and electronic optical image, or an emission optical image). In some embodiments the first and second component optical images are used to provide feedback concerning the quality of the overlaying and appropriate correction factors to improve the overlay quality. |
| US09262864B2 |
Synchronized views of video data and three-dimensional model data
Video data acquired during a three-dimensional scan of dentition provides a source of still images that can be displayed alongside a rendered three-dimensional model of the dentition, and the two views (model and still image) may be synchronized to provide a common perspective of the model's subject matter. This approach provides useful visual information for disambiguating surface features of the model during interactive model processing steps such as marking a margin of a prepared tooth surface for a restoration. |
| US09262861B2 |
Efficient computation of shadows
Methods and apparatus are provided for displaying shadows of polygonal light sources. A computing device can determine a light-source polygon of a polygonal light source, where the light-source polygon includes light-source vertices. The computing device can determine an occluding polygon between the light-source polygon and a background surface. The computing device can determine a shadow of the occluding polygon on the background surface by: for each light-source vertex, determining a vertex-shadow region of the background surface corresponding to a shadow cast upon the background surface by the occluding polygon for light emitted from the light-source vertex, determining an umbra of the shadow based on an intersection of the vertex-shadow regions, and determining a penumbra of the shadow based on a convex representation of a union of vertex-shadow regions. The computing device can display the shadow. |
| US09262858B2 |
Apparatus and method for display
Display apparatus and method are provided. The display apparatus may include a receiver for receiving an image; a grouper for analyzing the received image and grouping a plurality of frames of the received image based on the analysis; a depth allocator for determining at least two key frames from a plurality of frames grouped into at least one group, and allocating a depth per object in the determined key frames; and an image generator for generating a 3D image corresponding to other frames excluding the key frames based on a depth value allocated to the key frames. Hence, the display apparatus can allocate the depth value of a higher quality to the object in the frames of the received image. |
| US09262854B2 |
Systems, methods, and media for creating multiple layers from an image
A process for creating a composite picture with a plurality of parts extrapolated from an input picture. The process includes analyzing a picture for color content to detect at least one dominant color in the picture and for shape recognition to detect at least one object in the picture and generating a concentric grid for the input picture based on the color content analysis and the shape recognition for a depth calculation of the input picture. The concentric grid includes a center point, a plurality of lines that radiate from the center point, and a plurality of concentric circles that expand at a spatial distance in the picture, dividing the input picture into a plurality of sections, each representing an equal spatial depth. The process further includes generating a plurality of partial pictures using at least two of the plurality of sections. |
| US09262852B1 |
Generating a road network based on satellite imagery
A system and method for generating a road network based on satellite imagery. Plural pixels corresponding to satellite imagery of a region are obtained. For each of the plural pixels, a probability value corresponding to the probability that the pixel belongs within the road network is calculated. A grayscale image is formed based on the calculated probability values. Plural curves are produced based on the grayscale image, wherein the producing of each curve includes positioning a shape on the grayscale image so that an average intensity of the grayscale image covered by the shape exceeds a preset threshold, moving the shape about the grayscale image while the average intensity is maintained, and tracking the movement of the shape to produce the curve. A planar-connected graph is generated by connecting at least portions of the plural curves. The planar-connected graph corresponds to the road network. |
| US09262846B2 |
System and method for labeling maps
A system and method for label placement is disclosed that achieves the twin goals of practical efficiency and high labeling quality by employing cartographic heuristics. A caller defines map and label properties. Then labels are pulled within a map boundary. Labels are next ordered by priority in descending importance. The order of testing labels is determined. Attempts are made to move overlapping labels. This is an iterative process; therefore there must be criteria that halt the procedure. Upon reaching an acceptable solution, the label properties are adjusted to reflect the new label placements. |
| US09262844B2 |
Method to compensate gating effects on image uniformity and quantification for PET scan with continuous bed motion
Methods and systems for processing data for medical imaging are disclosed. The method includes obtaining a set of continuous bed motion (CBM) data from a first imaging modality. The set of CBM data includes a plurality of gating signals. A CBM normalization matrix is calculated. The CBM normalization matrix calculation includes the plurality of gating signals. An image is reconstructed from the CBM data and the CBM normalization matrix. The first imaging modality can be a PET imaging device. |
| US09262843B1 |
Time encoded based network for image processing
A circuit for detecting features in an image, the circuit including M time encoders, each time encoder having two inputs, Xi and Ti, where Xi is an ith element of an input vector X1 XM of the image and Ti is an ith element of a template vector T1 TM, and having an oscillatory output, wherein when the input vector X1 XM and the template vector T1 TM are more matched, the oscillatory outputs of the time encoders are more synchronized, and wherein when the input vector X1 XM and the template vector T1 TM are less matched, the oscillatory outputs of the time encoders are less synchronized. |
| US09262840B2 |
Optical non-contacting apparatus for shape and deformation measurement of vibrating objects using image analysis methodology
Apparatuses and methods related to measuring motion or deformations of vibrating objects are provided. A plurality of images of an object are acquired in synchronization with a plurality of determined times of interest during oscillation of the object. The plurality of images are compared to obtain one or more quantities of interest of the object based at least in part on the plurality of images. |
| US09262839B2 |
Image processing device and image processing method
There is provided an image processing device including a depth generation unit configured to generate, based on an image of a current frame and an image of a preceding frame of the current frame, a depth image indicating a position of a subject in a depth direction in the image of the preceding frame as a depth image of the current frame. |
| US09262836B2 |
All-focused image generation method, device for same, and recording medium for same, and object height data acquisition method, device for same, and recording medium for same
An all-focused image generation method comprises the steps (i) to (vi). The step (i) is a step of taking L images of an object at different focal positions. The step (ii) is a step of acquiring gray scale images of the object at the respective focal positions. The step (iii) is a step of performing multiresolution transform for the gray scale images. The step (iv) is a step of calculating focal position probability distribution regarding the focal positions, for each pixel position. The step (v) is a step of acquiring an optimal focal position for each of the pixel positions. The step (vi) is a step of generating an in-focus image by providing a pixel corresponding to the acquired pixel value to the pixel position. In the step (v), the optimal focal position is approximately calculated by belief propagation. |
| US09262835B2 |
Method, apparatus, and medical imaging system for segmenting image of object from image of organ
A method, an apparatus, a computer readable recording medium, and a medical imaging system are provided for segmenting an image of an object from an image of an organ. The method includes: generating a reference model of the object by using a priori knowledge related to the object of the organ; determining whether the first image includes a first area in which a shape of the object is unidentified; and in response to determining that the first image excludes the first area, segmenting a second image of the object from the first image, and in response to determining that the first image includes the first area, estimating a progression direction of the first area from the reference model to segment the second image from the first image. |
| US09262829B2 |
Method and apparatus for generating a diagnostic image based on a tissue emphasis image and medical imaging system employing the apparatus
A method of processing an image is provided. The method includes generating a tissue emphasis image by emphasizing a predetermined tissue of at least two radiation images of different energy bands, and generating a diagnostic image by combining at least one of the at least two radiation images of different energy bands and the tissue emphasis image. |
| US09262822B2 |
Malignant mass detection and classification in radiographic images
An image analysis embodiment comprises subsampling a digital image by a subsample factor related to a first anomaly size scale, thereby generating a subsampled image, smoothing the subsampled image to generate a smoothed image, determining a minimum negative second derivative for each pixel in the smoothed image, determining each pixel having a convex down curvature based on a negative minimum negative second derivative value for the respective pixel, joining each eight-neighbor connected pixels having convex down curvature to identify each initial anomaly area, selecting the initial anomaly areas having strongest convex down curvatures based on a respective maximum negative second derivative for each of the initial anomaly areas, extracting one or more classification features for each selected anomaly area, and classifying the selected anomaly areas based on the extracted one or more classification features. |
| US09262814B2 |
Image processing device and method for sharpening a blurred image
An image processing device includes a processor and a memory storing instructions causing the processor to: generate a first intermediate image by applying, to an input image, inverse conversion being inverse of conversion corresponding to degrading process of imaging the input image; generating a second intermediate image by adding a frequency component to the input image; generate a weighting factor so that a second residual error between a second image and the input image becomes smaller than a first residual error between a first image and the input image, the first image being obtained by applying the conversion to the second intermediate image, and the second image being obtained by applying the conversion to a composite image obtained by the weighted addition of the first and second intermediate images; and generate the composite image by performing the weighted addition of the first and second intermediate images using the weighting factor. |
| US09262809B2 |
Method and apparatus for image noise filtering
Methods and apparatus for filtering noise of low frequency from an image of the surface characteristics of an object expressed with reference to orthogonal first and second axis and obtained with linear light scanning, involve calculating a difference between pixel values of an image column vector along the second axis adjacent a selected reference image column vector and respective pixel values of the selected reference image column vector to obtain a pixel difference vector. The pixel difference values not mainly associated with a corresponding atypical change of surface characteristics as compared with noise are then selected, and a mean value from the selected pixel difference values are calculated as an estimated value of the noise. The estimated noise value are subtracted from the adjacent image column vector to obtain a corrected image column vector. The calculations are repeated using the corrected image vector as the reference image column vector and a further adjacent image column vector to obtain further corrected image column vectors, from which a noise filtered image is generated. |
| US09262798B2 |
Parameter FIFO
A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit. |
| US09262796B2 |
Communication apparatus
In an agent function, when a character image in motion is displayed, a number of the character images to be displayed is changed, depending on whether or not a speech utterance of a user is being received. In other words, during receipt the speech utterance of the user, the communication apparatus sends the character images to the vehicle-mounted apparatus at a first reduced frequency. Thus, even when a process of receiving the speech utterance and a process of displaying the character images are concurrently performed, the vehicle-mounted apparatus is not overloaded with the processes. Therefore, a stopping state of a process caused by overload of the vehicle-mounted apparatus with processes can be prevented and stoppage of the motion of the character image can also be prevented even during the receipt of the speech utterance. |
| US09262795B2 |
Hybrid rendering systems and methods
Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency. |
| US09262791B2 |
Targeting stories based on influencer scores
A story describing an activity performed by an interacting user is distributed to viewing users according to the influencer scores for the viewing users. Each influencer score can be calculated based at least in part on the influence of a viewing user on those users connected to the viewing user, and on the influencer scores for the users connected to the viewing user. Based on the determined influencer scores, at least one of the viewing users can be provided with the story describing the activity performed by the interacting user. |
| US09262789B1 |
System and method for assessing a claim using an inspection vehicle
Disclosed systems and methods automatically assess claims. A device may receive one or more images of a claimed object, such as a building or vehicle, compare the images to reference images and generate an estimate of financial damages to the object. The device may then generate a claim assessment based on previous comparisons and generated estimates. The claim assessment may be sent directly to a client or to an agent for review and/or processing. |
| US09262787B2 |
Assessing risk using vehicle environment information
A method includes receiving first sensor data representing information collected, during a first time period, by a sensor located on or in a vehicle configured to sense an environment external to the vehicle, storing the data in a memory, processing the data to determine a first set of one or more characteristics of the external environment, and determining, based on the first set of characteristics, a first risk indicator representing a risk of loss during the first time period. The method also includes receiving second sensor data representing information collected, during a second time period, by the sensor, storing the data in the memory, and processing the data to determine a second set of one or more characteristics of the external environment. The method also includes determining, based on the second set of characteristics, a second risk indicator representing a risk of loss during the second time period. |
| US09262786B1 |
Configuring composite ratebooks
Configuring composite ratebooks includes receiving configuration parameters associated with a composite ratebook; receiving a selection of one or more rate routines to be associated with the composite ratebook; receiving input defining one or more rate tables to be included in the composite ratebook; and generating a composite ratebook including the configuration parameters, the one or more rate routines, and the defined one or more rate tables. A rate routine includes operations used to determine a premium for an insurance coverage. The one or more rate tables include insurance factors used by the one or more selected rate routines to determine premiums for insurance coverages. |
| US09262784B2 |
Method, medium, and system for comparison shopping
Embodiments of computer implemented systems and methods for comparison shopping are described. One example embodiment includes receiving a data resource associated with a web page, the web page including an offering of a product and product offering terms, extracting product descriptors from the data source, requesting a search of marketplace offerings of the product based on the product descriptors, receiving results of the search (the results including marketplace offering terms of the marketplace offerings of the product), and displaying the marketplace offering terms, thereby facilitating comparison of the product offering terms with the marketplace offering terms. |
| US09262781B2 |
System and method for facilitating secure self payment transactions of retail goods
Disclosed herein are various embodiments for systems and methods for self-payment and verification of the purchase of retail goods and services. According to an embodiment of the invention, a method for verifying the purchase using a mobile electronic device in wireless communication with a payment verification system and a code generating system is provided, the method comprising the steps of: receiving from a consumer information identifying an item for purchase; receiving from a consumer information identifying payment means for purchasing the item for purchase; processing the information identifying the item for purchase and information identifying payment means and generating a unique QR code indicating a purchase of the item; sending the unique QR code to a mobile device for display by a consumer to the vendor of the item for purchase. |
| US09262780B2 |
Method and apparatus for enabling real-time product and vendor identification
A method and apparatus for enabling dynamic product and vendor identification and the display of relevant purchase information are described herein. According to embodiments of the invention, a recognition process is executed on sensor data captured via a mobile computing device to identify one or more items, and to identify at least one product associated with the one or more items. Product and vendor information for the at least one product is retrieved and displayed via the mobile computing device. In the event a user gesture is detected in response to displaying the product and vendor information data, processing logic may submit a purchase order for the product (e.g., for an online vendor) or contact the vendor (e.g., for an in-store vendor). |
| US09262773B2 |
Method of ranking and displaying certified content
A social media platform and method for displaying and ranking content from an individual user against content from other users. The method prompts the individual user to input user-generated information; receives the user-generated information; acquires related information; receives at least one visual recording related to the user-generated information; associates the user-generated information, the related information, and the captured visual recording to create a user single trophy entry in a remote database; ranks the user single trophy entry relative to a plurality of single trophy entries in the remote database to determine a relative rank; and displays the user single trophy entry with the determined rank. The social media platform displays and ranks trophies taken by a plurality of users utilizing a database, a ranking module, and an output module. |
| US09262771B1 |
Method and system for providing offers for automated retail machines via mobile devices
A mobile device with a display, processor(s), and memory: displays promotional offers; detects a user input selecting one of the promotional offers; and initiates performance of a transaction with an automatic retail machine to purchase a product stocked by the automatic retail machine. The mobile device also: receives a transaction completion notification from the payment module indicating that the product corresponding to the selected promotional offer was vended by the automatic retail machine; and, in response to receiving the transaction completion notification, provides a prompt to the user of the mobile device to obtain a product code for the vended product to validate the promotional offer. The mobile device further: obtains the product code for the vended product; transmits the product code to the server; and, in response: receives promotion validation information from the server; and displays the promotion validation information indicating whether the respective promotion offer was validated. |
| US09262769B2 |
Computer implemented methods for protecting and promoting products of a given brand by using machine readable codes
Computer implemented methods for protecting and promoting products of a given brand by using machine readable codes, including assigning, by a given brand, a particular value to a machine readable code localized in a packaging of a product; a user scanning the machine readable code by using a mobile computing device having installed therein a processor adapted to read the machine readable code; upon the scanning being performed, establishing communication between the processor and a remote server for storing the scanned code and performing a series of checkings of the scanned code; depending on the result of the checkings the remote server assigns a monetary compensation from the brand to the user that is delivered through the processor; and the processor informing the user about the checking, wherein the machine readable code contains information regarding a marketing campaign of the given brand, a product code and the particular value encrypted. |
| US09262768B2 |
System and methods for determining preference and identifying content within a social network
A system for determining preference, including a client device with feedback controls, a server and addressable URIs; the device and server in communication over an electronic network and the URIs' content retrievable over the network; the server automatically receiving and storing ratings, tracking URIs, using ratings to create a preference model for URIs, and using the preference model to suggest URIs; the stored ratings include a record having a rated item URI, a rater having a unique identification, a rating value provided by the rater, and at least one metadatum for creating subsets of ratings. Also, a method for automatically creating a chimeric preference vector, the method steps including identifying a multiplicity of datasets of rated items; automatically combining the datasets to form a combined dataset; automatically identifying ratings collisions; treating ratings collisions to form a data subset; and generating a chimeric preference vector based on the data subset. |
| US09262766B2 |
Systems and methods for contextualizing services for inline mobile banner advertising
The present disclosure is directed to systems and methods for processing advertisement opportunities when a user views content on a mobile device. An agent on a mobile device may contextualize a portion of a page being viewed to identify and send contextual data to a contextualization service. The contextualization service may use the contextual data to select a campaign from a plurality of campaigns to deliver an in line banner advertisement for content being viewed. Based on the selected campaign, the contextualization service may send the agent an advertisement or campaign information for display, such as an inline banner at a natural break in the content being viewed. Instead of having an advertisement predetermined or fixed prior to the display of the content, the present systems and methods may dynamically contextualize the page at the point of viewing based on the content of the page being viewed. |
| US09262765B2 |
System, method, and program product for identifying and providing suggestions
A system, method, and program product for identifying and providing suggestions includes registering information of a behavior of a user in an environment within a domain. Behavior processes identify the behavior, identify an item associated with the behavior, identify an identity of the user, and store the identified information. Task processes prepare a suggestion list using the information and a stored configuration. A participant account in the environment requests suggestions to serve to the user where the participant account belongs to a participant belonging to a group of affiliated participants. Suggestion processes identify a request item, identify the identity of the user and attributes associated with the request, aggregate suggestions using the stored configuration and a suggestion list set, and record served suggestions. The participant account receives the served suggestions where the participant account can offer the served suggestions on behalf of an affiliated participant. |
| US09262759B2 |
Wearable device as a payment vehicle
The present invention is directed to apparatuses, methods, and computer-program products for a multipurpose wearable device that is associated with one or more financial accounts wherein, in use, the wearable device is configured to facilitate a financial transaction using at least one of the one or more financial accounts. The wearable device comprises: a wearable article, wherein the wearable article comprises one or more features securing the wearable article to a person or an item associated with the person; and a portion comprising a machine-readable indicia, wherein the machine-readable indicia, when successfully read, provides payment information for conducting a financial transaction. |
| US09262751B1 |
Providing feedback-based rate adjustment for electronic communication services
A communication service is provided for monitoring recipient receptiveness of communications that are received from a sender. Based on feedback received from the recipients, the cost of utilizing the communication service may be adjusted. For example, in response to determining that one or more communications associated with a particular sender are identified by recipients as unwanted communications, the cost of utilizing the communication service may be adjusted based on whether the level of feedback exceeds a threshold. |
| US09262747B2 |
Tracking participation in a shared media session
A system, method, and computer program product for tracking user participation in a shared media session. A shared media session is connected to, where the shared media session includes a plurality of participants. A first identity is determined for a first participant with a first confidence level. The first participant is identified as the first identity if the first confidence level is above a first threshold. An amount of participation is tracked for the first identity. The amount of participation by the first identity is displayed on an electronic calendar for the shared media session to the plurality of participants. |
| US09262743B2 |
Method and apparatus for sociable computing in ad-hoc and configured peer-to-peer networks
Executing a program structure for spanning a thread of control and a thread of execution across multiple peers in a peer-to-peer network comprises generating a program structure comprising a plurality of program instructions. A first of a plurality of network peers then executes a portion of the program instructions which initiates the execution of code hosted by said first network peer, where said portion comprising fewer than all program instructions. The first network peer then migrates one or more of the program instructions, including one or more controlling program instructions, together with any requisite data, some of which may include control data, to at least one other of the plurality of network peer. The at least one other network peer then continues execution of the program instructions in accordance with the controlling program instructions and control data until one or more of the objections of the program structure are achieved. |
| US09262741B1 |
Continuous barcode tape based inventory location tracking
Disclosed are a method, system and/or device of continuous barcode tape based inventory location tracking. In one aspect, a method includes analyzing a layout diagram of a distribution center. The method further includes determining that the layout diagram includes a shelf. A number of segments associated with the shelf based on a forecasted allocation of an inventory on the shelf are calculated. A bar code tape having a globally unique identifier (GUID) associated with each segment of the number of shelves is automatically generated using a processor and a memory of a central inventory tracking system. |
| US09262740B1 |
Method for monitoring a plurality of tagged assets on an offshore asset
A method for monitoring a plurality of tagged assets on at least one offshore asset, by creating a customer profile and a library of survey set ups and storing information from independent survey set ups mounted on or proximate to the offshore asset on the administrative data storage. The method includes creating a library of tagged assets for the offshore asset using at least one independent survey set up, wherein each tagged asset has an icon with a hyperlink to a library of images. The method includes identifying placement locations on offshore assets and forming an executive dashboard for display on at least one client device, wherein a virtually positioned icon positioned on an image of the tagged assets presents a hyperlink to the library of survey set ups for that tagged asset, thereby enabling toggling from the image to the library of survey set ups. |
| US09262738B2 |
Methods of marking products and products produced by such methods
A method of marking a product to permit later identification and tracking of the product, includes: utilizing a processor for producing information as to the identification and history of the product since its production; converting the information into a code in the form of a unique monomers sequence embedded in or added to the product; and introducing the code into the respective product in a retrievable and non-destructible manner such as to enable the identification and history of the respective product to be retrieved despite transformations which may have occurred in the product since its production. Also described are applications of, and products produced in accordance with, the forgoing method. |
| US09262734B2 |
Satellite scheduling system
Systems and methods are provided for scheduling objects having pair-wise and cumulative constraints. The systems and methods presented can utilize a directed acyclic graph to increase or maximize a utilization function. Violation of cumulative constraints can be identified at the moment of constraint violation such that events resulting in constraint violations can be removed from the schedule while the schedule is being determined. By removing the events triggering constraint violations at the point of constraint violation, the systems and methods provided can determine optimal or near-optimal schedules in a relatively quick and efficient manner compared to systems and methods that check for violations of cumulative constraints after determining a schedule. The objects can comprise satellites in a constellation of satellites. In some implementations, the satellites are imaging satellites, and the systems and methods for scheduling can use crowd-sourced data to determine events of interest for acquisition of images. |
| US09262729B2 |
Selecting solution for carbon emission prediction
A computer-implemented method, apparatus, and system for selecting a solution for carbon emission prediction. The method includes the steps of: obtaining historical records of carbon emission and a current demand for carbon emission, locating from the historical records of carbon emission a best matching historical record with respect to the current demand and selecting, based on the located best matching historical record, one of (i) a data prediction solution record and (ii) a rule prediction solution, where at least one step is carried out using a computer device. |
| US09262726B2 |
Using radial basis function networks and hyper-cubes for excursion classification in semi-conductor processing equipment
A method and system for analysis of data, including creating a first node, determining a first hyper-cube for the first node, determining whether a sample resides within the first hyper-cube. If the sample does not reside within the first hyper-cube, the method includes determining whether the sample resides within a first hyper-sphere, wherein the first hyper-sphere has a radius equal to a diagonal of the first hyper-cube. |
| US09262723B2 |
Predicting climate data using climate attractors derived from a global climate model
Embodiments generally relate to methods of accurately predicting seasonal fluctuations in precipitation or other approximate functionals of a climate state space, such as the number of heating or cooling degree days in a season, maximum river flow rates, water table levels and the like. In one embodiment, a method for predicting climate comprises: deriving a climate attractor from a global climate model, wherein a tuning parameter for the climate attractor comprises a value of total energy for moving air and water on the earth's surface; estimating a predictive function for each of a plurality of computational cells within the global climate model; and predicting an approximate climate functional of interest for a given specific location utilizing a combination of the predictive functions from each of the plurality of computational cells geographically proximate the location, where at all stages, predictive functions are selected in part by comparison to historical data. |
| US09262722B1 |
System and method of measuring a social networker's influence on social networking websites
The present disclosure relates generally to a computer application software program for mobile phones, and more specifically to an application program related to social networking websites wherein an individual's influence on social networking websites can be quantified based on his/her quantitative and qualitative activity postings. A social networker may register any one or more social networking websites for which he/she is a participant and the system and method discussed herein will measure all activity postings, responses, replies, discussions, third party use of the original activity postings and the like, to generate weighted scores that are aggregated for an impact score that is reflective of the social networkers respective influence. |
| US09262720B2 |
Computer-readable recording medium, extracting device, and extracting method
According to one aspect, a computer-readable recording medium stores therein an extracting program 330a causing a computer to execute a process. The process includes based on event data obtained by associating a plurality of events stored in a storage unit and an occurrence time of each event, sequentially adding an event to a first pattern obtained by associating the plurality of events and the occurrence order of each event, and sequentially generating a second pattern which includes the first pattern and occurs in the event data; and extracting a pattern which satisfies a predetermined condition from the generated second pattern. |
| US09262715B1 |
System and method to provide a customized problem solving environment for the development of user thinking about an arbitrary problem
Preferred embodiments of the invention provide a customized or specialized environment to facilitate customized development of thinking about a problem or inquiry based project. |
| US09262713B2 |
Wellbore completion and hydraulic fracturing optimization methods and associated systems
Methods and systems for optimizing wellbore completion and, in particular, methods and systems for optimizing hydraulic fracturing parameters are disclosed. In some embodiments, a method of optimizing wellbore completion includes gathering wellbore data, screening and processing the gathered wellbore data, utilizing the screened and processed wellbore data to define an optimized model, and utilizing the optimized model to evaluate combinations of available wellbore completion parameters. In some instances, the optimized model is defined using artificial neural networks, genetic algorithms, and/or boosted regression trees. Further, in some embodiments the combinations of available wellbore completion parameters include hydraulic fracturing parameters, such as number of fractures, fracturing fluid type, proppant type, fracturing volume, and/or other parameters. |
| US09262707B2 |
Image forming apparatus, image processing system, and computer program product
An image forming apparatus has a display device and a mechanically-configured operating unit, and enables use of a function implemented in an information processing apparatus via a network. The image forming apparatus includes: a remote function-displaying unit that obtains display information to display a visual interface of the function implemented in the information processing apparatus to display the visual interface on the display device; a remote operating unit that sends operation information indicating contents of an operation on the display screen to the information processing apparatus; and a mechanical operation detecting unit that obtains contents of an operation on the mechanically-configured operating unit. When the visual interface of the function implemented in the information processing apparatus is being displayed on the display device, the mechanical operation detecting unit sends mechanical operation information indicating the contents of the operation on the mechanically-configured operating unit to the information processing apparatus. |
| US09262702B1 |
Method and system for forced unidirectional trapping (“FUT”) for constant sweep color object-background combination
The present disclosure relates to a computer-implemented method, device, and computer-readable storage medium used for trapping an object against a gradient background comprising: obtaining a trapping parameter for the object in both a fast scan and slow scan direction; forming a first, a second, and a third color trap for the object; comparing the first color trap for the object with the second color trap for the object; comparing the first color trap for the object with the third color trap for the object; determining that a result of the comparing the first color trap for the object with the second color trap for the object yields a larger result than a result of the comparing the first color trap for the object with the third color trap for the object; and applying trapping to the inner side of the object. |
| US09262701B2 |
Image processing apparatus and method for operating the same
An image processing apparatus includes a reading unit configured to read an image formed on a sheet, an erasing unit configured to erase the image formed on the sheet, and a controller configured to determine whether or not the image on the sheet as read by the reading unit is formed of an erasable material and prevent the sheet that is determined to have an image formed of the non-erasable material from being conveyed to the erasing unit. |
| US09262700B2 |
Image processing device and method of detecting missing dots in an image processing device
An image processing device for detecting a large number of missing dots. The image processing device comprises a print data image acquisition unit that acquires a print data image; an inkjet printer unit that prints on the back of a check; a back CIS unit that scans the back of the printed check; a print area extraction unit that extracts a print area R from the scanned image of the back of the check as an extracted image; and a missing dot detection unit determines if there are missing dots based on the print data image and the extracted image extracted by the print area extraction unit. |
| US09262699B2 |
Method of handling complex variants of words through prefix-tree based decoding for Devanagiri OCR
An electronic device and method identify a block of text in a portion of an image of real world captured by a camera of a mobile device, slice sub-blocks from the block and identify characters in the sub-blocks that form a first sequence to a predetermined set of sequences to identify a second sequence therein. The second sequence may be identified as recognized (as a modifier-absent word) when not associated with additional information. When the second sequence is associated with additional information, a check is made on pixels in the image, based on a test specified in the additional information. When the test is satisfied, a copy of the second sequence in combination with the modifier is identified as recognized (as a modifier-present word). Storage and use of modifier information in addition to a set of sequences of characters enables recognition of words with or without modifiers. |
| US09262698B1 |
Method and apparatus for recognizing objects visually using a recursive cortical network
A computer-implemented method for object recognition using a recursive cortical network comprising receiving an input image at an input module, applying a trained recursive cortical network (RCN) to the image using an inference module to activate child features of the RCN, selecting pools of the RCN containing the activated child features, propagating the selection of the pools to identify probabilities of one or more high-level features matching one or more objects in the input image. |
| US09262697B2 |
Sample imaging and classification
Disclosed herein are methods and apparatus for obtaining at least one non-birefringence image and at least one birefringence image of a stained sample, and classifying regions of the stained sample into a plurality of classes based on the at least one non-birefringence image and the at least one birefringence image. |
| US09262696B2 |
Image capture feedback
Embodiments for image capture feedback are disclosed. In some embodiments, a computing system may receive a first image from an image capture device and generate a score for the first image. The computing system may generate a recommendation for an action, such that if the image capture device captures a second image after the action is performed, the score for the second image will be better than the score for the first image. The computing system may indicate the recommended action to the user on an output device. Other embodiments may be disclosed and/or claimed. |
| US09262695B2 |
Method for detecting a predefined set of characteristic points of a face
A method of detecting a predefined set of characteristic points of a face from an image of the face includes a step of making the shape and/or the texture of a hierarchy of statistical models of face parts converge over real data supplied by the image of the face. |
| US09262691B2 |
Method for extracting salient object from stereoscopic image
The method for extracting salient object from stereoscopic video includes: dividing regions based on the similarity of color and the distance between pixels in a left-eye image and a right-eye image which are used for an input stereoscopic image; creating a disparity map based on a disparity obtained from a pixel difference of the left-eye image and the right-eye image; calculating a contrast-based saliency by comparing the divided regions and the divided regions of the disparity map; calculating a prior-knowledge-based saliency based on a prior-knowledge for the divided regions and the divided regions of the disparity map; and extracting salient regions of the image based on the contrast-based saliency and the prior-knowledge-based saliency. |
| US09262689B1 |
Optimizing pre-processing times for faster response
Embodiments of the subject technology provide for determining a region of a first acquired image based at least on a viewing mode and a set of respective positions of graphical elements to decrease the pre-processing time and perceived latency for the first image. One or more regions of text in the first image are detected, and a set of regions of text that overlap with the region of the image is determined and pre-processed. The subject technology may then pre-process an entirety of a subsequent image (e.g., to pick up missing text from the region of the first image). Thus, additional OCR results may be provided to the user by using the subsequent image(s) and merging subsequent results with previous results from the first image. |
| US09262688B1 |
Method and system for analyzing and recognition of an emotion or expression from multimedia, text, or sound track
Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, OCR (text), background, relationship, position, pattern, and object), large number of images (“Big Data”) analytics, machine learning, training schemes, crowd-sourcing (using experts or humans), feature space, clustering, classification, similarity measures, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, Natural Language Processing (NLP), Computing-with-Words (CWW), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability (e.g., using Z-number (e.g., “About 45 minutes; Very sure”)), rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, and data compression. |
| US09262686B1 |
Product image information extraction
A system and method for receiving an image of a product's packaging and extracting information (e.g., a set of facts) associated with a product from the image. The extracted information associated with the product may be added to a product profile if a confidence score associated with the extracted information is greater than or equal to a threshold. |
| US09262684B2 |
Methods of image fusion for image stabilization
Systems, methods, and computer readable media to improve image stabilization operations are described. Novel approaches for fusing non-reference images with a pre-selected reference frame in a set of commonly captured images are disclosed. The fusing approach may use a soft transition by using a weighted average for ghost/non-ghost pixels to avoid sudden transition between neighborhood and almost similar pixels. Additionally, the ghost/non-ghost decision can be made based on a set of neighboring pixels rather than independently for each pixel. An alternative approach may involve performing a multi-resolution decomposition of all the captured images, using temporal fusion, spatio-temporal fusion, or combinations thereof, at each level and combining the different levels to generate an output image. |
| US09262679B2 |
System and method for identification and separation of form and feature elements from handwritten and other user supplied elements
A system and methods for progressive feature evaluation of an electronic document image to identify user supplied elements is disclosed. The system includes a controller in communication with a storage device configured to receive and accessibly store a generated plurality of candidate images. The controller is operable to analyze the electronic document image to identify a first feature set and a second feature set, wherein each of the first and second feature sets represent a different form feature, compare the first feature set to the second feature set, and define a third feature set based on the intersection of the first and second feature sets, wherein the third feature sets represents the user provided elements. |
| US09262678B2 |
Method and system for analyzing an image generated by at least one camera
A method for analyzing an image of a real object, generated by at least one camera includes the following steps: generating at least a first image by the camera capturing at least one real object, defining a first search domain comprising multiple data sets of the real object, each of the data sets being indicative of a respective portion of the real object, and analyzing at least one characteristic property of the first image with respect to the first search domain, in order to determine whether the at least one characteristic property corresponds to information of at least a particular one of the data sets of the first search domain. If it is determined that the at least one characteristic property corresponds to information of at least a particular one of the data sets, a second search domain comprising only the particular one of the data sets is defined and the second search domain is used for analyzing the first image and/or at least a second image. |
| US09262677B2 |
Valuable file identification method and identification system, device thereof
A valuable file identification method includes step 1: selecting a characteristic area of the valuable file, and extracting a valuable file characteristic for last classification; step 2: an input valuable file is fast classified according to the extracted valuable file characteristic in step 1 to gain the banknote kind, denomination, direction and image quality information of the valuable file, and the banknote with better image quality and bad image quality are selected; step 3: an image restoration technique is utilized based on a partial differential equation to restore the old banknote image; step 4: the new banknote is directly identified and the old banknote is identified via the restored image to judge the authenticity of the current banknote; step 5: a result is output. The method enables eliminating restoration treatment for images comprising good quality and uninterested area, and saving time and improving system processing efficiency. A valuable file identification system and a valuable file identification device are also disclosed. |