最新美国发明专利第2016-02-02期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09252918B2	Method and apparatus for control channel transmission and reception A communication system is provided wherein a user equipment (UE) receives control information from a wireless network. The UE monitors control channel candidates using common reference signals (CRS) and monitors enhanced control channel candidates using demodulation reference signals (DMRS) when the UE is configured in a first transmission mode, such as transmission mode 9, for receiving a downlink shared traffic channel based on DMRS. The UE monitors control channel candidates only using CRS when the UE is configured in a second transmission mode, such as any of transmission modes 1-6, for receiving a downlink shared traffic channel based on CRS. The UE then receives downlink control information (DCI) in a subframe in one of the monitored control channel candidates or enhanced control channel candidates in the subframe.
US09252911B2	Flexible remote node (RN) for dynamic traffic allocation in passive optical networking (PON) and mobile backhaul (MBH) applications A computer implemented method for dynamically allocating traffic in a passive optical communication system includes employing an individual wavelength channel to carry different data services from an individual transmitter, configuring an optical network unit into optical network unit groups serving at least two community of users; and providing a flexible remote node with wavelength routing flexibility including switching wavelength traffic from optical network user groups with low capacity requirements to optical network user groups with increased wavelength traffic requirements.
US09252910B2	Expandable multicast optical switch A scalable multicast M×N optical switch (MCS) includes a non-scalable MCS having a plurality of (L+1)×1 selector switches east coupled at one of its L entrance ports to egress ports of the non-scalable MCS, the remaining L−1 entrance ports being coupled to an LN upgrade ports, where M and N are integers ≧2, and L is an integer ≧1. This allows the scalable MCS to be cascaded in a daisy-chain fashion, providing scalability from the M common ports to LM common ports. In another embodiment, the selector switches are integrated into the MCS, providing scalability of common MCS ports.
US09252908B1	Non-line of sight wireless communication system and method A non-line of sight backhaul system and method are described that provides self-alignment of the antennas beams of the wireless radios of the system, that provides robust operation in licensed and unlicensed frequency bands, that facilitates the use of a reduced number of frequency channels from M to 1 and that enables operation in a non-line of sight (NLOS) propagation environment.
US09252907B2	Methods and apparatus for providing multi-antenna enhancements using multiple processing units Certain aspects of the present disclosure relate to techniques for providing multi-antenna enhancements using multiple processing units. A UE (User Equipment) may receive data via three or more antennas. The UE may determine a number of independent processing units to be employed to process the data, wherein the determined number of independent processing units includes at least two processing units and at least one processing unit jointly processes at least two streams of data. The data may be processed by the determined number of independent processing units and the results of the processing units may be combined.
US09252901B2	Method and apparatus for managing synchronization groups in wireless communication system A synchronization group management apparatus of a node recognizes a node belonging to a different group if groups having mobility are moved and located in the same area, and performs an operation of merging the different groups into one group by changing the frame start time and the synchronization reference time of the node.
US09252898B2	Music distribution systems Music is blanket transmitted to each customer's computer-based user station. Customers preselect from a list of available music in advance using an interactive screen selector, and pay only for music that they choose to have recorded for unlimited playback. An antipiracy “ID tag” is woven into the recorded music so that any illegal copies therefrom may be traced to the purchase transaction. Music is transmitted on a fixed schedule or through an active scheduling process that monitors music requests from all or a subset of satellite receivers and adjust scheduling according to demand for various CD's. In those instances where transmission interruptions result in data loss, the system downloads the next transmission of the requested CD and uses both transmissions to produce a “good copy”. In conjunction to the blanket transmission, an automated CD manufacturing facility may be provided to manufacture CD's and distribute them by ground transportation.
US09252897B2	Multi-feed event viewing A method may include receiving a number of video feeds from video capture devices located at an event venue. The number of video feeds may be dynamically analyzed to determine feed information associated with the number of video feeds. A request to view a multi-feed event may be received from a user device. At least some of the number of video feeds may be provided to the user device in response to the request. Feed information corresponding to the at least some of the number of video feeds may be provided based on the dynamically analyzing.
US09252895B1	System and method of measuring full spectrum of modulated output signal from device under test A system for measuring a full spectrum of a modulated output signal provided by a device under test (DUT) includes a signal generating device that provides a radio frequency (RF) stimulus signal to the DUT, and generates a trigger signal, where the DUT outputs the modulated output signal in response. A receiver, having an intermediate frequency (IF) bandwidth less than a total bandwidth of the modulated output signal, includes mixers, an analog-to-digital converter (ADC) triggered by the trigger signal, and a local oscillator (LO) that consecutively generates multiple LO signals having different LO frequencies. A harmonic phase reference (HPR) generator generates a repetitive HPR signal having an HPR bandwidth wider than the total bandwidth of the modulated output signal and a modulation repetition rate the same as that of the RF stimulus signal. The mixers consecutively mix the LO signals with the HPR signal and the modulated output signal to provide IF signals input to channels of the ADC to form ADC data records, respectively, that capture the full spectrum of the modulated output signal.
US09252888B2	Coherent optical receiver device and coherent optical receiving method In a coherent optical receiver device, the control process for keeping received signals in high quality is complicated, therefore, a coherent optical receiver device according to an exemplary aspect of the invention includes a coherent optical receiver receiving input signal light; an input power monitor obtaining input power information determined on the basis of the power of the input signal light; a local oscillator connected to the coherent optical receiver; and a controller connected to the coherent optical receiver, the input power monitor, and the local oscillator; wherein the coherent optical receiver comprises a 90-degree hybrid circuit, a photoelectric converter, and an amplifier; the input power monitor is disposed in the optical path of the input signal light in a stage preceding the amplifier; and the controller obtains the input power information from the input power monitor and controls the power of local oscillation light output from the local oscillator on the basis of the input power information.
US09252884B2	Apparatus, method, and system for improving bandwidth of a plug and a corresponding receptacle Described herein is an apparatus for improving bandwidth of a transceiver system e.g., a Universal Serial Bus (USB) micro-B connector. The apparatus comprises a first pair of lens units, each lens unit of the pair positioned on either side of an input-output (I/O) bus interface, the pair of lens units to send and receive optical signals respectively; a first housing to shield the first pair of lens units and for physically coupling the I/O bus interface and the first pair of lens units to a receptacle; and a key to grasp the first housing and to lock the first housing with the receptacle.
US09252874B2	Power management for remote antenna units in distributed antenna systems Power management for a remote antenna unit(s) (RAUs) in a distributed antenna system. Power can be managed for an RAU configured to power modules and devices that may require more power to operate than power available to the RAU. For example, the RAU may be configured to include power-consuming RAU modules to provide distributed antenna system-related services. As another example, the RAU may be configured to provide power through powered ports in the RAU to external power-consuming devices. Depending on the configuration of the RAU, the power-consuming RAU modules and/or external power-consuming devices may demand more power than is available at the RAU. In this instance, the power available at the RAU can be distributed to the power-consuming modules and devices based on the priority of services desired to be provided by the RAU.
US09252868B1	Wireless communication with interference mitigation In one implementation, a wireless communication terminal includes a primary antenna array and a first controller configured to steer a main beam of the primary antenna array in a desired direction. The wireless communication terminal also includes an auxiliary antenna array and a second controller configured to control complex weights to be applied by at least some antenna elements of the auxiliary antenna array to corresponding variants of a second signal received by the at least some auxiliary antenna elements. Furthermore, the wireless communication terminal includes at least one signal combiner configured to combine variants of the second signal received from auxiliary antenna elements into an interfering signal that models interference from a co-located wireless communication terminal and subtract the interfering signal from variants of the first signal received from antenna elements of the principal antenna array to produce an interference mitigated signal.
US09252866B2	Relay node aggregation of data transfers in a wireless telecommunication system A relay node for aggregating data transfers in a wireless telecommunications network includes a receiver configured to receive uplink signals from multiple terminals, each uplink signal including respective uplink data, a decoder operatively connected to the receiver and configured to decode the uplink signals to obtain the uplink data, a machine-readable storage medium operatively connected to the decoder and configured to store the uplink data, an encoder operatively connected to the machine-readable medium and configured to encode an aggregate uplink signal including the uplink data obtained from the uplink signals, and a transmitter configured to transmit an uplink transmission of the aggregate uplink signal to the base station.
US09252864B2	Method and apparatus for fast beam-link construction in mobile communication system A method of forming a beam-link by a Base Station (BS) in a wireless communication system using a beamforming scheme includes determining at least one downlink beams to be used for downlink transmission and/or reception, transmitting a reference signal to a Mobile Station via the at least one downlink beam, receiving the reference signal via an uplink beam from the Mobile station, and updating the at least one downlink beam to increase a Signal-to-Noise Ratio (SNR). Accordingly, a beam-link using an initial beam-link between the BS and the MS and adaptive beamforming can be rapidly constructed in a high frequency band BDMA cellular system.
US09252859B2	Method for signalling resources to a radio station and radio station therefor The present invention relates to a method for signaling a plurality of transmission parameters for a plurality of communications between a primary station and a plurality of respective secondary stations in a multi-user MIMO mode, comprising the steps of (a) signaling the value of at least one first transmission parameter in a multicast message to at least two secondary stations, the value of the first transmission parameter being common to the respective communications corresponding to the at least two secondary stations, and (b) signaling the value of at least one second transmission parameter in a plurality of unicast messages to each secondary stations of the plurality of secondary stations.
US09252857B2	Embedded control signaling for wireless systems Enhancement of wireless Channel Order and rank (ECHO) systems and ECHO repeater devices for enhancement of a wireless propagation channel for point to point or point to multipoint radio configurations are disclosed. The enhancement may be used for MIMO communications channels. Aspects support a richer multipath environment to increase the rank of the channel propagation matrix and/or to increase the magnitude of the coefficients of the propagation matrix between two or more radios. Such enhancement is applicable to backhaul radios in terms of increased range or in the number of supportable information streams. The installation provisioning optimization control monitoring and adaptation of such devices within a network of backhaul radios is also disclosed. Wireless links and control between IBR and ECHO devices and between ECHO devices and other ECHO devices are also disclosed.
US09252855B2	Signal generation method and signal generation device A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.
US09252853B2	Techniques for beamforming to mitigate multi-user leakage and interference Examples are disclosed for beamforming to mitigate multi-user leakage and interference. The examples include an evolved node B (eNB) receiving feedback from user equipment (UEs) to indicate strongest or highest channel gains for various beams included in a plurality of beam sets. A selection process or scheme may then be implemented to select individual beams for a UE that minimizes or reduces leakage caused by the UE's use of a given beam. Reducing leakage may reduce interference to other UEs using other beams. Other examples are described and claimed.
US09252845B2	Near-field communications and routing Near-field communications (NFC) with NFC reader devices are facilitated. In accordance with one or more embodiments, an apparatus includes a NFC circuit that wirelessly communicates with different types of local NFC readers using an NFC protocol, a host circuit having one or more modules that communicate with one of the types of local NFC readers via the NFC circuit, and second (e.g., secure) modules that respectively communicate with a specific one of the different types of local NFC readers, also via the NFC circuit, using secure data stored within the second module. A routing circuit is responsive to an NFC communication received from a specific one of the NFC readers, by identifying one of the first and second modules that communicates with the specific one of the NFC readers, and routing NFC communications between the specific one of the NFC readers and the identified one of the modules.
US09252842B2	Power over coaxial cable An image communication system includes a coaxial cable having first and second ends. A monitor station is coupled to the first end and a camera is coupled to the second end. The monitor station provides power to the camera through the cable, while the cable is also used to carry communication signals transmitted by the camera to the monitor station. The image communication system includes a first active inductor coupled to the first end and a second active inductor coupled to the second end. A current-compensation circuit may also be provided.
US09252839B2	Method and device for cancelling interference between a signal carried by a carrier power line and a signal carried by a telephone line The present invention concerns a method and device for cancelling interference between a signal carried by a carrier current line of a system distributing digital services at the home of a subscriber and a signal carried by a telephone line of said system that is situated close to the carrier current line. The method is characterized in that it consists of obtaining the signal carried by the carrier current line, filtering it in order to obtain an estimate of the signal that disturbs the signal carried by the telephone line and subtracting this estimate from the signal carried by the telephone line.
US09252837B1	Split diversity data combining Various exemplary embodiments relate to a wireless communications system, communications device related methods, and automotive and other vehicles including: an antenna group comprising at least one antenna; a receiver circuit configured to receive a first instance of a data symbol via the antenna group; a first swap component configured to: receive a first portion of a second instance of the data symbol from the second communications device, provide a second portion of the first instance of the data symbol to a second communications device; and a buffer configured to store a first portion of the first instance of the data symbol and the first portion of the second instance of the data symbol; and a combining processor configured to create a first portion of a combined symbol by combining the first portion of the first instance and the first portion of the second instance.
US09252836B2	Method, devices and chip block for DS-CDMA The present invention relates to a method of producing a chip block for wireless transmission in a Direct Sequence Code Division Multiple Access (DS-CDMA) communication system. The method comprises spreading a symbol over at least one chip block (17). The method also comprises segmenting the chip block to form a first sub-block (a0) of the chip block. The method also comprises segmenting the chip block to form a second sub-block (a15) of the chip block. The method also comprises arranging a first sub-sequence (18) of chips furthest to a first end of the chip block in the first sub-block. The first sub-sequence is identical to a second sub-sequence (19) furthest to a second end of the chip block in the second sub-block. The method also comprises modifying at least one chip contained in the first sub-block and not being part of the first sub-sequence. The modifying is dependent on said first sub-sequence such that the symbol can be at least partially despread from the chip block.
US09252825B2	Wideband digital spectrometer A processor, comprising a first data input configured to receive a stream of samples of a first signal having a spectral space, the stream having a data rate of at least 4 GHz; a second data input configured to receive a stream of samples of a second signal; a multitap correlator, configured to receive the first stream of samples and the second stream of samples, and producing at least one correlation output for each respective sequential sample of the first signal received; and a programmable control configured to alter a relationship of the stream of samples of the first signal and the stream of samples of the second signal, to thereby select, under program control, an alterable correlation output.
US09252817B2	Dynamic log-likelihood ratio mapping for error correcting code decoding Apparatuses, systems, methods, and computer program products are provided for error correction. A soft read module is configured to obtain soft read information for a cell of a non-volatile memory medium. The soft read information may indicate a likelihood that a data value for the cell is correct. A reliability module is configured to associate the cell with a log-likelihood ratio (LLR) mapping from a plurality of LLR mappings based on one or more reliability characteristics for a set of cells that includes the cell. An LLR map module is configured to determine an LLR value based on the soft read information by using the LLR mapping.
US09252813B2	Iterative decoding of LDPC codes with iteration scheduling A method includes accepting modulated symbols, which carry bits of a code word of a Low Density Parity Check (LDPC) code, and computing respective soft input metrics for the bits. The code word is decoded using an iterative LDPC decoding process that includes selecting, based on a predefined criterion, a number of internal iterations to be performed by an LDPC decoder (84) in the process, performing the selected number of the internal iterations using the LDPC decoder so as to estimate decoded bits and soft output metrics indicative of the input bits based on the soft input metrics, performing an external iteration that updates one or more of the soft input metrics based on one or more of the soft output metrics produced by the LDPC decoder, and repeating at least one of the internal iterations using the updated soft input metrics.
US09252811B2	Time-varying low-density parity-check convolutional codes The present disclosure is directed to communication systems and more specifically to communication devices having encoder and/or decoder blocks employing Low Density Parity Check Convolutional Codes (LDPC CCs). According to exemplary embodiments, improved LDPC CC techniques are disclosed to construct the syndrome former of an LDPC-CC code in a systematic way based on desired Rate (b/c), Memory (ms) and Period (T) while achieving specific Degree Distribution (dv and dc), Girth, and ACE constraints (nACE, dACE) for a desired configuration.
US09252808B1	Ping-pong run length limit encoder A run length limit encoder includes a subdivided threshold lookup table to encode data using multi-level enumeration.
US09252803B2	Signal processor, window provider, encoded media signal, method for processing a signal and method for providing a window A signal processor for providing a processed version of an input signal in dependence on the input signal has a windower configured to window a portion of the input signal, or of a pre-processed version thereof, in dependence on a signal processing window described by signal processing window values for a plurality of window value index values, in order to obtain the processed version of the input signal. The signal processor also has a window provider for providing the signal processing window values for a plurality of window value index values in dependence on one or more window shape parameters.
US09252795B2	Distribution system for optical reference A system for distributing a reference oscillator signal includes a clock having a reference oscillator and a femtosecond laser stabilized by the reference oscillator. The system also includes at least one beamsplitter configured to split the femtosecond laser. The system further includes one or more remote nodes that are spaced from the clock. The remote nodes are configured to generate reference signals based on the split femtosecond laser.
US09252793B2	Semiconductor device A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.
US09252791B1	Phase locked loop and method for generating an oscillator signal A phase locked loop (PLL) system generates an oscillator signal by providing a fixed control voltage to a programmable voltage to current converter having switch selection inputs and a variable current output. Logic values are provided to the switch selection inputs to adjust a control current at the variable current output and a frequency of the oscillator signal is adjusted based on the control current. The logic values are fixed when a first condition is reached, which is based on the frequency of the oscillator signal, a division factor, and an input reference signal frequency. The fixed control voltage provided to the programmable voltage to current converter is then replaced with a charge pump control voltage based on an error signal. The error signal is based on a comparison of the input reference signal frequency and a fraction of the oscillating frequency.
US09252789B2	Oscillator circuit, vibratory device, electronic apparatus, moving object, method of adjusting vibratory device, and sensitivity adjustment circuit An oscillator circuit includes a terminal T1, a terminal T2, a variable capacitance element having one end connected to the terminal T1, and a capacitance value varying in accordance with a frequency control signal, a variable capacitance element having one end connected to the terminal T2, and a capacitance value varying in accordance with the frequency control signal, a load capacitance circuit connected to the terminal T1, and a load capacitance circuit connected to the terminal T2, and oscillates a resonator element at a frequency corresponding to the frequency control signal. The oscillator circuit is capable of adjusting the capacitance values of the load capacitance circuits, a reference voltage (the electrical potential of the terminal T1), and a reference voltage (the electrical potential of the terminal T2) in accordance with configuration information.
US09252782B2	Wireless chipset with a non-temperature compensated crystal reference An apparatus includes a temperature measuring device within a thermally conductive package. A crystal within the package is thermally coupled to the temperature measuring device and subjected to a same temperature as the temperature measuring device. A controller external to the package is configured to receive a signal from the crystal and a temperature measurement from the temperature measuring device. The controller is configured to estimate a frequency error of the crystal based on the temperature measurement and to provide a frequency error estimate to an external system.
US09252779B2	Semiconductor device and metering apparatus A semiconductor device. The semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that generates a timing signal of a frequency according to a oscillation frequency of the oscillation circuit, and a frequency correction section that corrects a frequency of the timing signal based on temperature data; and a discrete device that includes at least one of a temperature sensing device that detects a peripheral temperature, that supplies the detected temperature as temperature data to the frequency correction section, and that is provided as a separate body to the semiconductor chip, or a capacitor that is electrically connected to both the oscillator and the oscillation circuit and that is provided as a separate body to the semiconductor chip, wherein the oscillator, the semiconductor chip and the discrete device are contained within a single package.
US09252778B2	Robust flexible logic unit A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit that is part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that loaded data is properly locked, to prevent overwrites. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. The invention also provides for splitting the single FLU into multiple independent reconfigurable FLU sections, with independent user clock and reset, for implementing a plurality of independent functions or for establishing redundancy for critical functions.
US09252777B2	Method and apparatus for multiplexing pins of an integrated circuit An integrated circuit within an integrated circuit package, including a configuration module and a timing module. The configuration module configures the integrated circuit using a configure operation performed via N pins of the integrated circuit package, where N is an integer greater than 1. The timing module is configured to control on/off timing of (NM) light emitting diodes arranged in N columns and M rows connected to the N pins and M pins of the integrated circuit, respectively, where M is an integer greater than 1. During a first period, the configure operation utilizes the N pins. During a second period, the NM light emitting diodes receive data from the M pins and refresh signals from the N pins. The second period is different than the first period.
US09252767B1	Integrated switch module An integrated RF switch module including a package customized to include at least one trace. The trace includes one or more of at least one connection pad and at least one landing pad. At least one switching die is connected to the at least one connection pad. At least one device is connected to the at least one landing pad, the at least one device configured to enhance the performance of the switching die.
US09252766B2	Load detecting circuits and the method thereof A no-load detecting circuit and the method thereof are disclosed. The no-load detecting circuit may be applied in switching mode power supplies or other circuits. The no-load detecting circuit comprises: a variable resistance circuit coupled in series to a load of the switching mode power supply; and a first comparison circuit coupled to the variable resistance circuit to receive the voltage across the variable resistance circuit, wherein based on the comparison of the voltage across the variable resistance circuit and a first threshold, the first comparison circuit generates a no-load detecting signal indicative of the load status; wherein the equivalent resistance of the variable resistance circuit varies based on the varying of the load of the switching mode power supply.
US09252765B2	N-well switching circuit A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.
US09252758B2	Multi-phase phase interpolator A multi-phase phase interpolator receives two input clocks to generate several equally spaced output clocks using several phase interpolators. A phase interpolator may include a first circuit branch and a second circuit branch with output nodes that are connected together to provide an output clock. The output clock may be generated at least based on resistor values of the phase interpolator.
US09252753B2	Quadrature output ring oscillator and method thereof Various circuits are described, which sustain an oscillation using a combination of four primary inverters, four feedforward inverters, and four coupling resistors for outputting a quadrature output signal while avoiding contention between a primary inverter and a feedforward inverter. In one configuration, a circuit includes four primary inverters configured in a ring topology, four coupling resistors uniformly interposed in the ring among the four primary inverters, and four feedforward inverters forming four sub-feedback loops, respectively, each sub-feedback loop comprising two primary inverters, one coupling resistor, and one feedforward inverter. In a further embodiment, the circuit further comprises a voltage-to-current converter is for receiving a control voltage and outputting a supply current to the four primary inverters and the four feedforward inverters. A corresponding method is also provided.
US09252749B2	Clock generation device, electronic apparatus, moving object, and clock generation method A clock generation device measures a frequency ratio between a clock signal CK1 (32.768 kHz+α) and a reference frequency value based on a clock signal CK3 (25 MHz), generates a clock signal CK2 obtained by masking at least one clock pulse of the clock signal CK1 based on the measurement result of the frequency ratio, and controls the measurement interval of the frequency ratio based on the difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results of the frequency ratio.
US09252747B2	Stage circuits and scan driver using the same There are provided stage circuits and a scan driver using the same, which can supply scan signals using a simultaneous method or an interlace method. Each of the stage circuits includes a progressive driver and a simultaneous driver. The progressive driver outputs a scan signal to an output terminal, corresponding to a plurality of clock signals supplied simultaneously or progressively, and the coupling between the progressive driver and the output terminal is blocked when a third control signal is supplied. The simultaneous driver outputs a scan signal to the output terminal, corresponding to first and second control signals which do not overlap each other, and the coupling between the simultaneous driver and the output terminal is blocked when a fourth control signal, which does not overlap the third control signal, is supplied.
US09252745B2	Whitening filter configuration method, program, and system A system is configured so that signals passed through an all-pass filter using warp parameter λ are whitening-filtered, and so that the frequency axis is restored by an all-pass filter using warp parameter λ. This optimizes the whitening filter by determining the optimum λ. First, the AR order p is automatically estimated using λ=0. A spectral distance dλ is computed using a discrete Fourier transform spectrum value passed through an all-pass filter using warp parameter λ and a discrete AR spectrum value passed through an all-pass filter using warp parameter λ. The λ which minimizes the spectral distance dλ is set as the warp parameter, and a whitening filter is configured in which the warp parameter has been optimized.
US09252742B2	Analog filter in wireless transmission/reception device and method for setting cut-off frequency using the same A method and an apparatus are provided for setting a cut-off frequency of an analog filter of a reception device for wireless communication. A deviation value is obtained that corresponds to an error between a first gain value based on an ideal transfer function curve and a second gain value based on a measured transfer function curve at an arbitrary frequency of a frequency band in which a constant interval is maintained between a slope of the ideal transfer function curve and a slope of the measured transfer function curve. A cut-off frequency that is used to measure the measured transfer function curve in a real environment, is corrected based on the obtained deviation value.
US09252740B1	Resonator electrode shields A MEMS resonator system that reduces interference signals arising from undesired capacitive coupling between different system elements. The system, in one embodiment, includes a MEMS resonator, electrodes, and at least one resonator electrode shield. In certain embodiments, the resonator electrode shield ensures that the resonator electrodes interact with either one or more shunting nodes or the active elements of the MEMS resonator by preventing or reducing, among other things, capacitive coupling between the resonator electrodes and the support and auxiliary elements of the MEMS resonator structure. By reducing the deleterious effects of interfering signals using one or more resonator electrode shields, a simpler, lower interference, and more efficient system relative to prior art approaches is presented.
US09252739B2	Module substrate and module A module substrate includes: a multilayered wiring substrate that includes wiring layers; and embedded duplexers that are embedded in the multilayered wiring substrate and electrically connected to the wiring layers, wherein the embedded duplexers include duplexers supporting at least two bands of Band1, Band2, Band5, and Band8.
US09252738B1	Wideband tuning probes for impedance tuners and method Multi-segment RF probes for automatic slide screw impedance tuners include a multitude of slugs, which are individually adjustable towards the center conductor of the slabline and spaced against each-other in order to create the required capacitance and transmission line space values needed for synthesizing resonant networks to match arbitrary reflection factor patterns over a given frequency range. The multi-segment probes are optimized using network synthesis software within the limits of the capacitance and inductance values allowed by the hardware. The probes allow constant phase testing for 100 MHz bandwidths or more.
US09252736B2	Network signal coupling and EMI protection circuit A network signal coupling and EMI protection circuit assembly includes a processing circuit installed in a circuit board and coupled between a voltage-mode network-on-chip at the circuit board and a network connector and drivable by a driving voltage from the voltage-mode network-on-chip to process network signals. The processing circuit includes opposing first connection end and second connection end, two-wire channels electrically connected between the first connection end and the second connection end, a coupling module and an EMI protection module installed in each two-wire channel for coupling network signals and removing noises. Each EMI protection module includes two capacitors having respective first ends thereof respectively connected to the two wires of the respective two-wire channel and respective opposite second ends thereof connected in series and grounded for filtering lower frequency part of resonant waves in the band during signal transmission to prevent electromagnetic interference and to enhance signal transmission stability.
US09252733B2	Switchable filters and design structures Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.
US09252730B2	Audio processing device and audio systems using the same An audio processing device is provided. The audio processing device includes a shaper. The shaper receives a digital input audio signal and generates an output audio signal at an output terminal according to the digital input audio signal. The shaper includes a gain adjustment unit and a shaping unit. The gain adjustment unit receives the digital input audio signal and adjusts the digital input audio signal to generate a gained audio signal. The shaping unit receives the gained audio signal. When the shaper operates in a first mode, the shaping unit shapes an envelope of the gained audio signal to generate a shaped audio signal, and the shaped audio signal serves as the output audio signal.
US09252728B2	Non-speech content for low rate CELP decoder A method and device for modifying a synthesis of a time-domain excitation decoded by a time-domain decoder, wherein the synthesis of the decoded time-domain excitation is classified into one of a number of categories. The decoded time-domain excitation is converted into a frequency-domain excitation, and the frequency-domain excitation is modified as a function of the category in which the synthesis of the decoded time-domain excitation is classified. The modified frequency-domain excitation is converted into a modified time-domain excitation, and a synthesis filter is supplied with the modified time-domain excitation to produce a modified synthesis of the decoded time-domain excitation.
US09252724B2	2G support for 2G and 3G/4G envelope tracking modulator There is provided an amplification stage including an envelope tracking modulated supply for tracking a reference signal, comprising a low frequency path for tracking low frequency variations in the reference signal and for providing a first output voltage, and a high frequency path for tracking high frequency variations in the reference signal and for providing a second output voltage, and a combiner for combining the first and second output voltages to provide a third output voltage, the amplification stage further comprising a first amplifier arranged to receive the first output voltage as a supply voltage, and a second amplifier arranged to receive the third output voltage as a supply voltage, wherein the first and second amplifiers are enabled in different modes of operation.
US09252721B2	Power decrease based on packet type Techniques for controlling one or more audio amplifiers in or associated with a device coupled on a local area network are disclosed. An example playback device includes a processor, an amplifier, a network interface, and a memory. The memory includes a software module that, when executed by the processor, causes the playback device to: operate in a first power mode in which the amplifier consumes a first amount of power; while operating in the first power mode, determine that a defined time has passed since receiving, via the network interface, a specified type of data packet; and based on determining that the defined time has passed since receiving the specified type of data packet, transition from operating in the first power mode to operate in a second power mode in which the amplifier consumes a second amount of power, wherein the first amount of power is greater than the second amount of power.
US09252717B2	Phase noise reduction in LC-VCO An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.
US09252716B2	High-frequency amplifier circuit, semiconductor device, and magnetic recording and reproducing device A high-frequency amplifier circuit includes a balanced-unbalanced converter converting a single-ended signal into differential signals. The output of a first amplifier amplifying the single-ended signal is connected to the signal terminal on the unbalanced side of the balanced-unbalanced converter. The input of a second amplifier amplifying one of the differential signals is connected to one signal terminal on the balanced side of the balanced-unbalanced converter. The input of a third amplifier amplifying another of the differential signals is connected to another signal terminal on the balanced side of the balanced-unbalanced converter. An impedance element is inserted between an element on the balanced side of the balanced-unbalanced converter and a ground.
US09252714B2	Transmission signal power control device and communication apparatus A transmission signal power control device includes: at least one low-power attenuator configured to attenuate amplitude of a transmission signal when an absolute value of the amplitude of the transmission signal is smaller than or equal to a clipping threshold; a power amplifier configured to amplify the transmission signal output from the at least one low-power attenuator; and a control unit configured to stop operation of the power amplifier when the absolute value of the amplitude of the transmission signal is smaller than or equal to a value and operate the power amplifier when the absolute value of the amplitude of the transmission signal is larger than the value.
US09252713B2	Bias circuits and methods for stacked devices Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.
US09252712B2	Hardware-efficient signal-component separator for outphasing power amplifiers Described herein is a fixed-point piece-wise linear (FP PWL) approximation technique for computations of nonlinear functions. The technique results in circuit designs having relatively few and simple arithmetic operations, short arithmetic operands and small-sized look-up tables and the circuits resultant there from can be efficiently pipelined to run at multi-GSamples/s throughputs. In one exemplary embodiment, the FP PWL approximation technique was used in the design of an energy-efficient high-throughput and high-precision signal component separator (SCS) for use with in an asymmetric-multilevel-outphasing (AMO) power amplifier. The FP PWL approximation technique is appropriate for use in any application requiring high-throughput, area and power constrained hardware implementations of nonlinear functions.
US09252708B1	Class-AB XTAL circuit A resonant element driver circuit includes a NMOS transistor and a PMOS transistor that are configured to drive a resonant element. The resonant element driver circuit includes biasing circuitry that is configured to bias the PMOS transistor. The biasing circuitry receives a reference signal that is used to set the biasing on the PMOS transistor. The resonant element driver further includes mirror circuitry that tracks current flowing through the NMOS and PMOS transistors.
US09252707B2	MEMS mass bias to track changes in bias conditions and reduce effects of flicker noise A technique for tracking changes in bias conditions of a microelectromechanical system (MEMS) device includes applying an electrode bias signal to an electrode of the MEMS device. The technique includes applying a mass bias signal to a mass of the MEMS device suspended from a substrate of the MEMS device. The technique includes generating the mass bias signal based on a target mass-to-electrode bias signal level and a signal level of the electrode bias signal.
US09252704B2	Voltage tunable oscillator using bilayer graphene and a lead zirconate titanate capacitor A voltage controlled oscillator comprising a substrate and a bilayer graphene transistor formed on the substrate. The transistor has two signal terminals and a gate terminal positioned in between the signal terminals. A voltage controlled PZT or MEMS capacitor is also formed on the substrate. The capacitor is electrically connected to the transistor gate terminal. At least one component is connected to the transistor and capacitor to form a resonant circuit.
US09252702B2	Frame for solar module and solar system using the same A bracket is used for supporting at least one solar module each of which has a frame. The bracket includes a fastener, a holder and a fixing element. The fastener includes a top portion and extended portions connected vertically to both sides of the top portion. The top portion has a concave segment at its central position. The holder includes a supporting portion for resisting the bracket. The holder has first through holes, in which the extended portions pass through a plurality of second through holes of the frame and the first through holes of the holder for sandwiching the bracket between the fastener and the holder. The fixing element is used for fixing the fastener on the holder.
US09252701B1	Ultimate renewable solar energy and storage system A system for integrating and co-generating renewable energies which achieves a combined powerful AC/DC electricity output, includes an enclosed volume chamber having an inner surface including a plurality of thermophotovoltaic cells located thereon and an opening for admitting a condensed high-temperature solar energy beam. A heat absorbing member located within the chamber for receiving a portion of the solar energy beam and acts as a thermal storage as well as a thermal emitter to supply thermal energy to the thermophotovoltaic cells to create DC electricity. Air is fed into the chamber to capture thermal energy from the emitter and any waste thermal energy, which is then converted into AC electricity. The system relies on the power of simplicity using a new twist in solar physics to allow for the highest conversion of sunlight energy to electricity at zero carbon emission while occupying significantly less space than typical solar energy systems.
US09252698B2	Inverter device and motor drive system An inverter device includes a power supply unit and a switch controller. The power supply unit supplies AC power to an AC motor whose electric characteristics in response to a rotation speed are switchable between low speed characteristics and high speed characteristics. The switch controller switches the electric characteristics of the AC motor. The switch controller executes switching control that alternately switches the electric characteristics of the AC motor between the low speed characteristics and the high speed characteristics on the basis of the rotation speed of the AC motor.
US09252697B2	Motor controller A motor controller configured to control an SRM includes an inverter connected to an SRM, a torque and flux estimator configured to estimate a torque and a flux generated in the SRM as an estimated torque and an estimated flux, based on output from the inverter and a rotor angle of the switched reluctance motor, a switching pattern selector configured to select one of a plurality of switching patterns based on comparing a result of a reference torque and the estimated torque, comparing a result of a reference flux and the estimated flux, and a flux phase angle, and performing switching of the inverter in accordance with a selected switching pattern, and a reference flux calculator configured to obtain the reference flux from a flux trajectory and the rotor angle changing the flux trajectory, the flux trajectory indicating a relationship between the rotor angle and the reference flux.
US09252696B2	Driver circuit and method A drive signal generating unit generates a drive signal used to alternately deliver a positive current and a negative current to a coil. The drive signal is such that nonconducting periods are set before and after a positive current conducting period and the nonconducting periods are set before and after a negative current conducting period. A driver unit generates the drive current in response to the drive signal generated by the drive signal generating unit and then supplies the drive current to the coil. The drive signal generating unit sets the width of a nonconducting period such that, after the drive start of the linear vibration motor, the width of a nonconducting period to be set before at least the first conducting period of the drive signal is shorter than the width of a nonconducting period to be set before each conducting period during steady operation of the linear vibration motor.
US09252694B2	Method and apparatus for detecting a state of an alternator regulator A detection circuit for an alternator regulator, and method therefor. The detection circuit comprises an input circuit arranged to receive a phase signal from an alternator regulator and to output an attenuated sense signal representative of the received phase signal, a detection component operably coupled to the input circuit and arranged to receive the attenuated sense signal output by the input circuit, and a blocking capacitance operably coupled between the input circuit and the detection component and arranged to block a DC component of the attenuated sense signal. The detection component is arranged to compare the received attenuated sense signal to at least one reference voltage signal, and to output a signal representative of a frequency of the phase signal from the alternator regulator based at least partly on the comparison of the received attenuated sense signal to the at least one reference voltage signal.
US09252692B2	Electric-motor furniture drive having a power supply device An electric-motor furniture drive includes a power supply device, a manual control for moving movable furniture components relative to each other, and an electric motor with reversible rotation direction. A speed-reducing transmission is connected downstream of the electric motor and an additional transmission is connected downstream of the speed-reducing transmission. The power supply device has a mains connection, transforms the mains-side input voltage into at least one output-side low voltage and is configured for galvanic isolation between the mains-connected input side and the output side for operating the electric-motor furniture drive. The power supply device is designed as a switched-mode power supply and has an intermediate circuit, a control device for controlling the switched-mode power supply, and a secondary unit. The power supply device provides an output-side operating voltage at the output thereof in an operating state and provides an output-side idle voltage at the output in an idle state.
US09252691B2	Back electromagnetic force (BEMF) sense system One embodiment includes a back-electromagnetic force (BEMF) sense system. The system includes a sense amplifier configured to measure an amplitude of a selected one of a plurality of phase voltages relative to a center tap voltage associated with a servo motor for the calculation of an associated BEMF voltage. The plurality of phase voltages can be provided to the sense amplifier via a respective plurality of control nodes. The selected one of the plurality of phase voltages on a respective one of the control nodes can be selected based on coupling the other of the plurality of control nodes associated with the other of the plurality of phase voltages to a voltage source configured to provide a predetermined voltage magnitude.
US09252685B2	Dust removing device and imaging device Provided is a dust removing device that can be designed and controlled appropriately and has high dust removal performance even at low temperature, and an imaging device using the dust removing device. In a dust removing device to be set on a base, including a piezoelectric element formed of a piezoelectric material and a pair of opposing electrodes, a vibration member, and a fixation member containing at least a high molecular compound component, a phase transition temperature T from a first ferroelectric crystal phase to a second ferroelectric crystal phase of the piezoelectric material is set to −60° C.≦T≦−5° C., and whereby, the dust removing device can be designed and controlled appropriately and high dust removal performance can be obtained even at low temperature.
US09252683B2	Tracking converters with input output linearization control In a preferred embodiment, a voltage inverter comprises a voltage converter circuit and a controller. The voltage inverter produces a time-varying output voltage from an input voltage, which can be a DC input voltage or an AC input voltage. The controller provides a control signal at a duty ratio determined dynamically by a set of signals. The set of signals include the time-varying output voltage, a predetermined output voltage, a gain factor and an inductor current in the voltage converter circuit. The predetermined output voltage can have an AC waveform or an arbitrary time-varying waveform. The voltage inverter operates to match the time-varying output voltage to the predetermined output voltage. Input-output linearization is used to design a buck inverter, and input-output linearization with leading edge modulation is used to design boost and buck-boost inverters under conditions where left half plane zero effects are present.
US09252681B2	Power converter with a first string having controllable semiconductor switches and a second string having switching modules A power converter includes at least one leg including a first string that includes controllable semiconductor switches, a first connecting node, and a second connecting node and that is operatively coupled across a first bus and a second bus. A second string is operatively coupled to the first string via the first connecting node and the second connecting node. The second string includes a plurality of switching modules wherein each of the plurality of switching modules includes a plurality of fully controllable semiconductor switches and at least one energy storage device. The power converter includes a system controller to control activation of the controllable semiconductor switches and switching modules such that a controlled electrical variable is maintained at a first predetermined reference voltage value and the average internal stored energy of the energy storage devices is maintained at a second predetermined reference value.
US09252678B2	Power conversion apparatus A power conversion apparatus is provided which includes a first DC/DC converter and a second DC/DC converter which are connected to each other in parallel, and a controller which changes a state of the second DC/DC converter between operation and stop, based on an input current or an output current of the power conversion apparatus, and at least one current threshold determined based on a first characteristic curve showing a relation between current and conversion efficiency in a state where the second DC/DC converter is stopped while the first DC/DC converter is operated and a second characteristic curve showing a relation between current and conversion efficiency in a state where the first DC/DC converter and the second DC/DC converter are operated.
US09252677B2	Quasi resonant push-pull converter and control method thereof The invention relates to a quasi-resonant push-pull converter and the method for controlling the same, said push-pull converter comprising: a direct current (DC) input power supply configured to supply DC input for the converter; a first power input unit and a second power input unit, connected to said DC input power supply, respectively and configured to supply input for the converter in different periods, comprising a first power switching tube and a second power switching tube, a first primary winding and a second primary winding; a power output circuit, configured to supply output of the converter, comprising secondary windings and full-bridge rectification circuits; a first output capacitor and a second output capacitor connected to said power output circuit and configured to store DC electric energy output by the power output circuit in which a resonant element is arranged to achieve a quasi-resonant switching circuit through voltage feedback; and a switching circuit being controlled through voltage feedback, whereby turns ratio of the primary windings and the secondary windings of the push-pull converter is controlled.
US09252672B2	Method of controlling phase-shift full-bridge converter in light load operation A method of controlling a phase-shift full-bridge (PSFB) converter in a light load operation is provided to switch control modes of the PSFB converter by detecting magnetizing current of a transformer thereof. The method includes following steps: First, the PSFB converter is operated in an extended PSFB control mode when the magnetizing current is larger. Afterward, the PSFB converter is operated in a modified PSFB control mode when the magnetizing current is gradually reduced and electric charges transported by the residual magnetizing current near to or less than a half of the DC input voltage. Finally, the optimal degree of soft switching of the PSFB converter is implemented when the PSFB converter is operated at the modified PSFB control mode. Accordingly, it is to improve overall efficiency, reduce switching losses, and achieve electromagnetic compatibility.
US09252665B2	DC-DC converter control apparatus In a DC-DC converter control apparatus, it is configured to have a current sensor for detecting a current flowing through a positive electrode wire connecting the second common terminal with the positive electrode terminal of the high-voltage port and to control operations of the first and second switching elements based on the current detected by the current sensor. With this, it becomes possible to accurately detect the current of the windings and appropriately control the operation of the switching elements based on the detected currents without increasing the transformer in size.
US09252664B2	DC-DC converter with short-circuit protection A DC-DC converter includes a voltage converter circuit having an FET 1, a short-circuit protection FET 3 that blocks a large current from flowing in the voltage converter circuit when a short-circuit failure occurs in the FET 1 or capacitors, and a detector that detects a short-circuit failure in the FET 1 or the capacitors to turn off the FET 3. The FET 1 is connected to a power supply line and also in series to the FET 3. The capacitors are connected to the power supply line and to a connection point between the FET 1 and FET 3. The detector detects a failure on the basis of the voltage at the connection point.
US09252662B2	Illumination device control systems and methods In various embodiments, a control system for an electronic circuit iteratively applies voltage to and senses current from a load to regulate operation of the load.
US09252660B2	System and method for generating a regulated boosted voltage using a controlled variable number of charge pump circuits A system, method, and computer program product for generating a regulated boosted load voltage. A comparator may use reduced versions of a reference voltage, a supply voltage, and a fed-back output load voltage to determine whether the output load voltage requires adjustment. If so, a controller may responsively vary the number of voltage boosting charge pumps connected in parallel to the load to best match a target voltage. The target voltage may be the reference voltage plus the supply voltage. A counter may track the number of active charge pumps, and may increment or decrement the number more slowly than the charge pumps operate. Loop gain may be limited by an integrating filter to prevent oscillation. The embodiments are of particular utility for signal conversion circuitry as they eliminate difficulties arising from gate-source voltage inadequacies and differences in switch transistors. A wider range of reference voltages may be accommodated.
US09252658B2	Level-crossing based circuit and method with offset voltage cancellation A level-crossing based circuit with offset voltage cancellation includes a first level-crossing detector section having a first output capacitor, wherein the first level-crossing section is configured to charge the first output capacitor to a first voltage corresponding to an input signal. The first voltage includes a first offset voltage. The level-crossing based circuit also includes a second level-crossing detector section having a second output capacitor, wherein the second level-crossing detector section is configured to discharge the second output capacitor to a second voltage corresponding to the input signal such that the second voltage includes a second offset voltage that is substantially equal in magnitude to the first offset voltage and opposite in polarity to the first offset voltage relative to an average of the first voltage and the second voltage.
US09252657B2	Phase-displacement of a power converter in a wind turbine A wind turbine generator comprising: an electrical generator configured to generate AC signals, a plurality of power converters operated by a gating signal, each power converter configured to convert the AC signals from electrical generator into fixed frequency AC signals, a transducer configured to measure the combined output from the power converters, and a controller configured to phase-displace the gating signal of one of the power converters to substantially minimize harmonic components of the combined output.
US09252656B2	Bridgeless interleaved power factor correction circuit using a PFC inductor with quad-winding on a single core A bridgeless interleaved power factor correction (PFC) circuit using a single PFC choke having four windings formed on a single core to form the four input inductors of the PFC circuit. An AC-to-DC converter constructed using the bridgeless interleaved PFC circuit achieves high conversion efficiency with high power factor and low total harmonic distortion. Furthermore, the size of the PFC circuit is reduced by using a single PFC choke with quad-winding.
US09252652B2	Wide input voltage range power supply circuit A wide input voltage power supply circuit for a load includes a first stage and a second stage. The first stage includes a linear regulator circuit configured to maintain an output voltage at a predetermined output voltage level. The linear regulator includes an input for shutting the linear regulator off when an input voltage exceeds a predetermined shut off threshold. The second stage includes a high voltage detection circuit coupled to the input of the linear regulator. The high voltage detection circuit is configured to detect the level of the input voltage and to shut the linear regulator off when the input voltage exceeds the predetermined shut off threshold. An under voltage lockout circuit may be included, the under voltage lockout circuit configured to set a minimum turn-on voltage for the load.
US09252647B2	Technique for electrically connecting a generator and an exciter A connection device includes a body having a first and a second end, a first connector set at the first end, and a pin type connector set at the second end. The first connector set includes a first strip element and a second strip element, which form an electrical interface of the connection device. The pin type connector set includes a first element and a second element, and thus forms another electrical interface of the connection device, different from the electrical interface formed by the first connector set. The pin type connector may be projecting pins or hollows that receive pins. The first connector set is electrically connected to the pin type connector set. Thus, the connection device is adapted for electrically connecting a generator with an exciter having incompatible electrical interfaces.
US09252646B2	Motor with diffusion stopper A motor includes a rotation shaft, a commutator, power supply brushes, and a brush holder. The brush holder includes an opposing portion that faces an end face of the commutator in an axial direction, a bearing holder, and a diffusion stopper. The diffusion stopper is arranged in a portion of the opposing portion located toward the outer side in the radial direction from the bearing holder and limits the diffusion of abrasion powder of the power supply brushes. The diffusion stopper is projected toward the commutator in the axial direction or recessed in the axial direction.
US09252644B2	Servomotor production method, servomotor production device, servomotor, and encoder This disclosure discloses a servomotor production method of a servomotor including a motor and an encoder. The encoder includes a rotating disk and an optical module. The rotating disk is mounted on a shaft of the motor and includes at least one concentric slit formed around a disk center. The optical module is provided with a light receiving element configured to receive light emitted from a light source and subjected to an action of the concentric slit on a substrate. The servomotor production method includes adjusting a position of the optical module with respect to the rotating disk by using the concentric slit by means of an output of the light receiving element when the optical module is fixed and arranged facing the rotating disk.
US09252642B2	Electrical machine The invention relates to an electric machine (100) comprising a stator (107) and a rotor (101), wherein the rotor (101) comprises a hollow shaft (102), wherein a closed hollow space (103) is formed by means of the hollow shaft (102), wherein the closed hollow space (103) is provided for receiving a cooling agent, wherein a three-dimensional transport structure (200) is provided in the closed hollow chamber (103) for transporting the cooling agent. The three-dimensional structure can, for example, be produced by means of applying an adaptive material.
US09252640B2	Generator set assembly with baffle An apparatus includes a housing having a ventilation opening. A component such as a generator set can be disposed within an interior space of the housing. A baffle can be disposed within the interior space of the housing at a location that obstructs an acoustic line of sight between the ventilation opening and the component to eliminate or otherwise reduce a sound signature of the component. The baffle can also be configured to accumulate water from the ventilation opening. A drain can also be provided to aid in the removal of water accumulated by the baffle and route the water outside the housing.
US09252639B2	Method of manufacturing index device of machine tool A method of manufacturing an index device of a machine tool includes providing a jig having an outer periphery of the same outer diameter as an outer diameter of a motor for driving the index device, inserting the jig into a casing configured to house the motor for driving the index device prior to setting the motor into the casing, filling a material with higher thermal conductivity than the air into gap space created between the casing and the outer periphery of the jig through an opening provided in the casing; removing the jig from the casing when the material filled in the gap space becomes solidified; and setting the motor into the casing with the jig removed therefrom.
US09252635B2	Rotor for an electric machine and electric machine A rotor for an electric machine includes a pole core having a coolable magnetisable rotor section which is made of a super-conducting material. The rotor section has a rotationally symmetric geometry. The pole core is formed as a cylinder and the rotor section is arranged on an outer surface of the cylinder so as to be encircling.
US09252625B2	Method and device for charging a battery of an electrical drive using components of the electrical drive The invention relates to a multi-stage charging device for a battery of a battery operated electrical motor. The multistage charging device comprises a buck converter, an intermediate circuit and a boost converter in order to generate a suitable direct charging current from a (one or three-phase) alternating current provided by a power connection. According to the invention, components of the electrical drive are used for the boost converter and the intermediate circuit: the electrical motor functions as an intermediate circuit and the drive converter functions as a boost converter. According to the invention, the coupling of the electrical motor to the network-side buck converter occurs so that at least half the charging current flows through at least one of the at least three coils of the electrical drive. The invention further relates to a corresponding method and to a corresponding use of the drive components.
US09252618B2	Terminals, terminal systems and charging/discharging methods thereof Terminals, terminal systems, charging/discharging methods for the terminals, charging/discharging methods for the terminal systems, and discharging methods are disclosed. The terminal is coupled to a second terminal including a second switching unit, a second charging unit and a second battery unit. The second charging unit is coupled to the second battery unit. The terminal includes a first switching unit and a first battery unit. The first switching unit is coupled to each of the second switching unit and the first battery unit. The first switching unit is configured to receive a control instruction or a control signal, and to switch to the second switching unit based on the control instruction or the control signal so as to supply power to the second terminal with the first battery unit, or switch to the second charging unit based on the control instruction or the control signal so as to charge the second battery unit with the first battery unit. Thus, the battery of the terminal can be used to charge the battery of the second terminal or used directly as a second battery for supplying power to the second terminal. This improves user convenience and usability of the terminals.
US09252616B2	Zinc-air battery A zinc-air cell, a battery which is a low weight, low volume, or high energy system, or a combination thereof, and an apparatus for recharging the same are disclosed.
US09252609B2	Hanging folder device charging system A device charging system includes a base that has two opposing rim edges that are substantially parallel to each other and are spaced apart by a width corresponding to a hanging folder rail width. Several jacks are on a surface of the base, each is electrically connected to a source of power. Several hanging folders, each having integrated hanging folder rails, interface to the two opposing rim edges. The hanging folder rails are of a width corresponding to the hanging folder rail width. Several devices are physically held within a corresponding hanging folder and each device is electrically connected to one of the jacks by a charging cable, thereby providing power from the source of power to charge that device.
US09252604B2	Apparatus for wireless power transmission and reception Provided is a wireless power transmission system to increase efficiency in wireless power transmission. A wireless power transmitter may include: one or more capacitors; a power inputting unit configured to receive power from a power supply and to charge the one or more capacitors; a transmitting unit configured to transmit resonance power; and a switching unit configured to control electrical connection of the one or more capacitors to the power inputting unit and to the transmitting unit. A wireless power receiver is also described.
US09252603B2	Auxiliary power device, memory system having the same, and cell balancing method thereof An auxiliary power device includes an auxiliary power source having first and second charging cells connected in series, a cell balance circuit configured to sense a charging voltage between the first and second charging cells, generate a balance voltage based on the sensed charging voltage, and applies the generated balance voltage between the first and second charging cells, and a microprocessor configured to diagnose the first and second charging cells based on the sensed charging cells and control the cell balance circuit.
US09252602B2	Electric storage cell control circuit To satisfactorily carry out balancing even when balancing control is suspended. It is selected according to a condition which of battery cell information (old state information) by the last balancing stored in a storage device and battery cell information (new state information) acquired during a start of this time is used, and the balancing control is performed.
US09252601B2	Method for controlling a power converter in a wind turbine generator A method for controlling a power converter in a wind turbine generator, the power converter being connected to a power grid, the method comprising obtaining an alternating current (AC) line voltage at a connection point between the power converter and the power grid, obtaining a frequency of the power grid based on the AC line voltage, dynamically adapting the AC line voltage to the frequency of the power grid, generating a reference signal based on at least the frequency-adapted AC line voltage, and determining a converter control signal to be provided to the power converter based on the reference signal and the grid frequency in order to generate a power at the frequency of the power grid. Further, a wind turbine generator implementing the method is provided.
US09252592B2	Semiconductor device A semiconductor device includes a rectifier coupled between a circuit ground and a terminal for coupling to an external circuit, a transistor-enhanced current path coupled to the rectifier, and a switching circuit coupled to the transistor-enhanced current path and coupled between the terminal and the circuit ground. The switching circuit is configured to turn off the transistor-enhanced current path during normal operation, and turn on the transistor-enhanced current path when an electrostatic discharge occurs at the terminal.
US09252586B2	Method for forming a seal on conductors of an electrical cable The invention provides a method of forming a seal (62) between and around conductors (12A, 12B and 12C) of an electrical power cable (10), and has particular application as a safety measure in potentially explosive applications. The method includes passing the conductors (12A, 12B and 12C) through an opening in a body (26) so as to define a cavity within the body (26) between and around the conductors (12A, 12B and 12C); introducing an absorbent material (64) into the cavity; introducing a liquid settable material (66) into the cavity; and allowing the settable material (66) to be absorbed by the absorbent material (64) and to set thereby to seal the cavity between and around the conductors (12A, 12B and 12C).
US09252585B2	Connector apparatus with shielding contact A connector apparatus having a PG screw thread in a first end section and a first traversing bore, in which a first axial clamping surface is embodied. A grounding assembly has an electrically conducting, iris spring, is arranged in the first traversing bore and lies against the first axial clamping surface. An annular clamping body having a second traversing bore, a second frontside annular clamping surface, which surrounds the second traversing bore and which is arranged in the first bore facing the grounding assembly, wherein the grounding assembly is clampable between the clamping surfaces, whereby the iris spring is radially deflectable, wherein the clamping body has an external thread for engagement in an internal thread of the base body, and wherein the connector apparatus has with reference to the first end section of the base body, behind the grounding assembly a conduit screw thread for the connection of a conduit.
US09252582B2	Plug-in type bus bar A plug-in type busbar for connecting with a relay or a breaker includes an insulating housing and a plurality of conductive busbar parts insulated from each other in the insulating housing. Two interface sets are provided on two ends of the busbar respectively. One interface set on one end of one busbar can be inserted in the other interface set of the other bus bar. The busbar is connectable with adjacent busbars through the interface sets at both ends thereof. At least an electrical connection is formed between the adjacent two busbars after the adjacent two busbars are inserted each other. When a longer busbar is demanded, an extended structure can be obtained by simply connecting two busbars together, and a connection of the busbars can be completed by connecting the insulating housing in a plugged manner.
US09252574B2	Method for inserting and removing cables A method for installing and removing a row of cables from a cable array is provided. The method includes providing an installation tool having a first body with a plurality of arms extending from one side. The plurality of arms being configured to receive a cable connector body, the plurality of arms including at least one first projection extending from one of the plurality of arms. The installation tool is moved onto a row of cables held coupled together by a bracket, each of the cables in the row of cables having a cable connector body. The connector bodies are engaged into receptacles and the bracket is moved with the at least one first projection.
US09252572B2	Media appliance and method for use of same A media appliance and method for use of the same are disclosed. In one embodiment, a housing is adapted to be mounted within a wall. A panel forms a front portion of the housing and the panel includes vents and the panel may be mounted substantially flush with the wall. A media player, which includes a set-top box, is disposed within the housing. A pair of ports, disposed within openings defined by the housing, are configured to receive respective optio-electric connectors. Each port includes optio-electrically conductive elements. The pair of ports are coupled to the media player and one port is configured for providing a connection to a television and the other port is configured for providing a connection to an external source of signal for the television.
US09252571B2	Terminal box A terminal box that can be reliably fixed to a solar cell module is provided. The terminal box includes a bottom wall facing a back surface of the solar cell module, a top wall facing the bottom wall, side walls, and a housing space defined by the bottom wall, the top wall and the side walls to accommodate a component to be mounted. The bottom wall includes a limiting wall formed in a periphery of the bottom wall to project toward the solar cell module, and a communication opening for allowing a charging space defined by the limiting wall and the bottom wall to communicate with the housing space. The limiting wall defines a gap for allowing the charging space to communicate with external space of the limiting wall.
US09252570B2	Countertop module utilities enabled via connection A connection system includes a feature module that supplies various functionalities, a portable countertop stand having an upright section that selectively receives the feature module and an umbilical connecting the portable stand to an external appliance to deliver utilities to the portable countertop stand. A utility port selectively delivers at least one utility to the feature module when engaged with the upright section. A utility receiver removably engages the utility port by hand without the use of tools and selectively receives a predetermined set of utilities when the feature module engages the upright surface. A connection interface detects when the feature module is engaged with the upright section and the predetermined utility set required by the engaged feature module. After the feature module is engaged, the connection interface prompts the utility port to release the predetermined utility set to the feature module.
US09252569B2	Spark plug A spark plug includes an insulator; a center electrode; a metallic shell; a ground electrode disposed at a forward end portion of the metallic shell and forming a gap in cooperation with a forward end portion of the center electrode; and a tip at least a portion of which is joined to at least the one of two side surfaces of the ground electrode which is disposed downstream with respect to fuel gas flow. In a first imaginary plane which contains a forward end surface of the center electrode and on which a discharge surface of the tip is projected, at least a portion of a projected image of the discharge surface is located within a range of 2.5G from the outer circumference of the forward end surface of the center electrode, where G (mm) is the size of the gap.
US09252565B2	Light-emitting element A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure.
US09252564B2	Tunable laser with directional coupler A tunable laser has a first mirror, a second mirror, a gain medium, and a directional coupler. The first mirror and the second mirror form an optical resonator. The gain medium and the directional coupler are, at least partially, in an optical path of the optical resonator. The first mirror and the second mirror comprise binary super gratings. Both the first mirror and the second mirror have high reflectivity. The directional coupler provides an output coupler for the tunable laser.
US09252561B2	Frequency comb source with large comb spacing A frequency comb laser providing large comb spacing is disclosed. At least one embodiment includes a mode locked waveguide laser system. The mode locked waveguide laser includes a laser cavity having a waveguide, and a dispersion control unit (DCU) in the cavity. The DCU imparts an angular dispersion, group-velocity dispersion (GVD) and a spatial chirp to a beam propagating in the cavity. The DCU is capable of producing net GVD in a range from a positive value to a negative value. In some embodiments a tunable fiber frequency comb system configured as an optical frequency synthesizer is provided. In at least one embodiment a low phase noise micro-wave source may be implemented with a fiber comb laser having a comb spacing greater than about 1 GHz. The laser system is suitable for mass-producible fiber comb sources with large comb spacing and low noise. Applications include high-resolution spectroscopy.
US09252559B2	Narrow bandwidth reflectors for reducing stimulated Brillouin scattering in optical cavities An optical-fiber filter system to narrow a linewidth and to reduce noise fluctuations of an optical beam is provided. The optical-fiber filter system includes an optical fiber having a first end-face and an opposing second end-face, the first end-face and the second end-face setting a fiber length; a fiber Bragg grating having a first reflectivity positioned at the first end-face; and a reflector having a second reflectivity positioned at the second end-face. When the optical beam at a first frequency is coupled from a laser into one of the first end-face or the second end-face, a resonant cavity is established at the first frequency between the fiber Bragg grating and the reflector while Brillouin scattered light shifted from the first frequency within the optical fiber is transmitted through the fiber Bragg grating.
US09252557B2	Single cavity dual-electrode discharge cavity and excimer laser A single-cavity dual-electrode discharge cavity and an excimer laser including such a discharge cavity are disclosed. The discharge cavity may comprise a cavity body and two sets of main discharge electrodes. The cavity body may comprise a left chamber and a right chamber arranged to form a symmetric dual-chamber cavity. The left and right chambers can interface and communicate with each other at a plane of symmetry of the entire discharge cavity. The two sets of main discharge electrodes can be disposed in the left and right chambers on the upper side, respectively. According to the present disclosure, the single-cavity configuration can be used to achieve functions of dual-cavity configurations, such as MOPA, MOPO, and MOPRA. Thus, it is possible to reduce system complexities and also ensure synchronization of discharging in the discharge cavity.
US09252556B2	Amplifying optical fiber and optical amplifier The first cladding 52 has a two-layer structure formed of a solid inner layer 62A passed through the center axis of the first cladding 52 and an outer layer 62B enclosing the inner layer 62A and the plurality of cores 51 with no gap. A refractive index n1 of the core 51 is provided higher than refractive indexes n2A and n2B of the inner layer 62A and the outer layer 62B, the refractive indexes n2A and n2B of the inner layer 62A and the outer layer 62B are provided higher than a refractive index n3 of the second cladding 53, and the refractive index n2A of the inner layer 62A is provided lower than the refractive index n2B of the outer layer 62B.
US09252553B2	Optical fiber laser and method for manufacturing an optical fiber laser A laser includes an optical fiber having two ends of which a first end is configured to receive light therethrough, and a doped section configured to absorb at least part of the light received by the first end and for emitting light. The laser further includes a heat-conducting material which coats at least the doped section of the optical fiber.
US09252552B2	Gas laser oscillator capable of estimating sealability of gas container A gas laser oscillator includes an output command part for outputting a power supply output command; a power supply unit for applying a discharge tube voltage corresponding to the power supply output command to the discharge tube to start discharge; a voltage detection part for detecting the discharge tube voltage; a discharge start determination part for determining whether or not the discharge has been started on the basis of a value detected by the voltage detection part when the power supply output command is gradually increased; and a sealability determination part for determining that sealability of the gas container has been reduced when a discharge start time from the application of the discharge tube voltage until when it is determined by the discharge start determination part that the discharge is started exceeds a predetermined first threshold value.
US09252551B2	Apparatus for manufacturing a connector A connector comprises a base insulator, a plurality of elongated plate shaped contacts arranged on the base insulator, and a cover insulator arranged to hold the contacts in cooperation with the base insulator and welded to the base insulator, the base insulator is provided with a pair of openings arranged to face each other across each of holders and to intersect with the direction in which the holders are arranged.
US09252549B2	Method for making a power connection The invention provides systems and methods for power connection, which may be a sealed power connection. The sealed power connection may be used with an electric machine or any device that may require electrical and/or mechanical connection for power. The sealed power connection may provide an effective electrical connection while providing a robust mechanical connection. The electric machine or device may be fluid-sealed and/or fluid-cooled. The sealed power connection may provide for electrical insulation of the connection from the machine or device enclosure, and may also be sealed to provide for fluid sealing and/or internal fluid cooling of the electric machine or device, as well as fluid cooling of the connection.
US09252548B1	High density networking component for 1U product form factor and associated rack system Systems and apparatuses are disclosed having a 3×8 stacked RJ45 connector with an integrated LEDs option for a 1U product form factor to provide increased density of an RJ45 connector which utilizes open source and non-proprietary modular connectors in conformity with published standards. For example, in one embodiment such systems and apparatuses include a networking component having therein a connector which includes a plurality of RJ45 jacks arranged into exactly three horizontal rows and a plurality of vertical columns; a printed circuit board to electrically interface with each of the plurality of RJ45 jacks; and a 1× Rack Unit (1U) chassis having the connector and printed circuit board therein, in which at least a portion of the connector extends into a horizontal plane occupied by the printed circuit board. Rack systems and methods are further described for employing such a networking component.
US09252547B2	Universal serial bus connector A universal serial bus connector includes an insulating housing, a tongue board assembly disposed to a front of the insulating housing, a plurality of first and second conductive terminals, and a shielding shell. Each of the first conductive terminals has a base strip, a fastening strip, a contact portion and a soldering strip. The fastening strips are integrally molded to the tongue board assembly with contact portions thereof projecting under a bottom of the tongue board assembly. Each of the second conductive terminals has a touching portion and a soldering slice. Each of the soldering slices is soldered to a top surface of a portion of one of the first conductive terminals facing to a bottom surface of the soldering slice. The second conductive terminals are integrally molded to the tongue board assembly with the touching portions thereof projecting beyond a top of the tongue board assembly.
US09252546B2	Distributor connection module The invention relates to a distribution connection module (1) for telecommunications and data technology, with the distribution connection module (1) comprising a first submodule (2) and a second submodule (3), with the first and second submodule (2, 3) each having contact elements (7, 13), with the contact elements (7, 13) each having an electrical connecting contact (8, 14) and an interface contact (9, 15), with the interface contacts (9) of the first submodule (2) being electrically connected to one another by the interface contacts (15) of the second submodule (3), or with the interface contacts (9) of the first submodule (2) being connected to interface contacts (61) of a further submodule (60) and the interface contacts (15) of the second submodule (3) being connected to interface contacts (62) of a further submodule (60), with the further submodules (60) being arranged between the first and the second submodules (2, 3).
US09252543B2	Dual orientation connector assembly with interior magnetic component A dual orientation connector assembly for mating with a mating connector in two directions, including: an insulative housing defining a side wall, a printed circuit board (PCB) received in the housing, a mating member soldered on the PCB, a cable extending from an end of the insulative housing, and a magnetic component disposed in the insulative housing to provide a retaining force for retaining to the mating connector. The mating member includes a mounting portion received in the insulative housing, a mating portion extending out of the side wall of the insulative housing for mating with the mating connector, and a number of terminals mounted in the mating portion. The mating portion includes a first surface and an opposite second surface. The first surface and the second surface have the same number of the terminals.
US09252539B2	Internally switched female receptacle or connector with plug-latching safety interlock An internally switched female receptacle or connector for use with IEC 60309-2 configuration plugs and the like. Various plug-latching and plug-actuated safety interlock arrangements coordinate strictly axial plug movement relative to the receptacle with the closing and opening of sleeve contacts and terminal pressure contacts. A continuous ground feature ensures grounding of the primary electrical circuit throughout plug insertion and withdrawal. An optional low-current lighting control circuit powers an LED status indicator. A modular clocking design enables variable angular positioning of the terminals during manufacture.
US09252535B2	Terminal connecting structure A terminal connecting structure is provided with a male terminal having a tab portion and a female terminal having a contact portion. The tab portion and the contact portion mutually slide. A sliding surface of the tab portion extends in a direction inclined with respect to a sliding direction of the tab portion and the contact portion and has a projecting wall and a recess portion provided alternately along the sliding direction. A sliding surface of the contact portion extends in a direction crossing the projecting wall and the recess portion and has a projecting wall and a recess portion provided alternately along the sliding portion.
US09252533B2	Data cabling jack device and data cabling assembly structure A data cabling jack device for configuring a plurality of cables on an assembly frame is provided. The data cabling jack device includes a housing and an engaging structure. The housing has an accommodation space, wherein the housing includes a jack side and a cable side opposite to the jack side. The engaging structure is disposed on the housing and has an engaging switch and an engaging portion, wherein the engaging switch is switched between a release position and an engaging position. The release position and the engaging position are respectively disposed nearby the cable side and the jack side. The engaging portion engages the assembly frame when the engaging switch is switched from the release position to the engaging position to drive the engaging portion to protrude out of the assembly frame.
US09252527B2	Multiple wire connecting terminal A relay terminal (10) made of copper or copper alloy and configured to join an aluminum wire (20) and a copper wire (30) by being electrically connected to the aluminum wire (20) and the copper wire (30) includes a first barrel portion (11) to be caulked and crimped to an aluminum core (21) of the aluminum wire (20) made of aluminum or aluminum alloy, which is a metal different from copper or copper alloy constituting the relay terminal (10), a second barrel portion (12) to be caulked and crimped to a copper core (31) of the copper wire (30), a bottom plate (13) configured to link the first barrel portion (11) and the second barrel portion (12), and a projecting portion (41) (water drainage portion (40)) provided on the bottom plate (13) and configured to restrict the intrusion of water from the second barrel portion (12) toward the first barrel portion (11).
US09252524B2	Terminal having a pair of elastic contact pieces with inwardly and outwardly bent portions A terminal includes an elastic contact piece. The elastic contact piece comes into elastic contact with a counterpart terminal in a terminal container. The elastic contact piece includes a bent portion bent and extending from a portion of a side wall of the terminal container in the terminal container, and a clamping portion extending from a front end of the bent portion in the terminal container along an extending direction of the side wall. A dimension of the clamping portion is longer than a dimension of the bent portion in the extending direction, so as to prevent a foreign substance from entering between an inner wall of the terminal container and the clamping portion.
US09252521B1	Short path circuit card A system contains a land grid array socket with a first set of socket interconnections configured to connect to a set of circuit board electrical connectors, each socket interconnection in the first set extending from a top surface to a bottom surface. A second set of socket interconnections are configured to reversibly connect to a set of circuit card electrical connectors. A circuit board can include a mounting surface fastened to the land grid array socket. A set of electrical connectors within a socket connector zone can be connected to at least some of the first set of socket interconnections. A board cutout section is located beneath a second interconnection zone and configured to receive a circuit card.
US09252519B2	Wire branching connector A metal plate contact has two slits running from an upper end towards a bottom wall. First and second trench for receiving trunk and branching cables, respectively, and a recess for mounting a contact that crosses these trenches are created in a middle portion in a lateral direction of a housing. Left and right movable ends are connected to the middle portion on the two sides in a longitudinal direction via a connection band. The movable ends can be folded towards the top of the middle portion. First and second upper side trenches for covering the top of the first trench and covering the top of the second trench, respectively, are created in these movable ends. A wire lid for positioning a cable end is formed in one end or in the two ends of the second trench or of the second upper side trench.
US09252517B2	Connector A connector is mateable with a mating connector comprising a mating contact. The connector comprises a contact which is brought into contact with the mating contact at two points under a mated state. The contact has a first spring portion, a protruding portion protruding from the first spring portion, a slide portion extending flat and a second spring portion. The protruding portion has a first contact portion while the slide portion has a second contact portion. The first contact portion is movable by first resilient deformation of the first spring portion while the second contact portion is movable by second resilient deformation of the second spring portion. One of the first contact portion and the second contact portion is moved because of both the first resilient deformation and the second resilient deformation when the connector is transited from a mating start state to the mated state.
US09252514B2	Connector A contact unit includes a first conduction path in the form of a thin film arranged along a peripheral surface of an insulating elastic body, a second conduction path arranged along the first conduction path, and a connecting conduction path electrically connecting the first and second conduction paths to each other. A frame has a through hole. The frame supports the contact unit so that the first conduction path exposed from both openings of the through hole is brought into contact with connection objects and that the second conduction path is entirely received in the through hole.
US09252511B2	Card edge connector with soldering members in different positions A card edge connector for connecting a printed circuit board, includes an insulative housing defining an elongated base portion, a first and a second end portions located on both ends of the base portion and a pair of locking arms respectively extending forwardly from the first and second end portions. A plurality of conductive terminals are received in the insulative housing. A first soldering member is mounted on the first end portion and includes a soldering portion located below the corresponding locking arm. A second soldering member is mounted on the second end portion and includes a soldering portion located below the corresponding locking arm. The distance between the soldering portion of the first soldering member and the first end portion in a front-to-rear direction is different from the distance between the soldering portion of the second soldering member and the second end portion in the front-to-rear direction.
US09252509B2	Terminal connection structure for electric cable A terminal connection structure for an electric cable includes a first terminal connected to a part of an internal conductor which is exposed by peeling off a first insulating covering, a second terminal connected to a part of an external conductor which is exposed by peeling off a second insulating covering, and a housing member that surrounds an outer periphery of the first terminal and an outer periphery of the second terminal and contains the first terminal and the second terminal which are arranged coaxially in a separated manner.
US09252508B2	Electric connector with deformable terminals An electric connector includes at least one terminal pin having, at opposite ends thereof, terminals to be inserted into through-holes formed through printed circuit boards spaced away from and facing each other, and an aligner for aligning the terminal pins in a row in such a condition that the terminal pins are movable relative to the aligner, the terminal pin including a movement-limiter which restricts movement of the terminal pin in a direction of an axis thereof.
US09252501B2	Millimeter scale three-dimensional antenna structures and methods for fabricating same Millimeter scale three dimensional antenna structures and methods for fabricating such structures are disclosed. According to one method, a first substantially planar die having a first antenna structure is placed on a first surface. A second substantially planar die having at least one conductive element is placed on a second surface that forms an oblique angle with the first surface. The first and second dies are mechanically coupled to each other such that the first die and the first antenna structure extend at the oblique angle to the second die.
US09252500B2	Circularly polarized antenna and feeding network An antenna for transmitting and/or receiving-electromagnetic waves has a flat ground plane, and an array of radiating and/or receiving elements. The radiating and/or receiving element comprises a planar conductor which is arranged in parallel to the ground plane. An L-shaped slot is arranged in the planar conductor.
US09252496B2	Methods and compositions for energy dissipation A composition for energy dissipation in at least a portion of the frequency range from about 1 GHz to about 20 GHz, the composition can comprise a dielectric and graphene mixed with at least a portion of the dielectric, wherein the percentage volume of the graphene relative to the total volume of the composition is configured such that dissipation of incident electromagnetic radiation is substantially optimized in at least a portion of the frequency range from about 1 GHz to about 20 GHz.
US09252495B1	Ultra-wideband antenna with a conical feed structure and hyperbolic cosine taper An antenna is adapted for operation over a broadband frequency. The antenna includes a conical portion and a tapered portion. The conical portion may have a bicone structure, where each cone has a tapered portion. The tapered portion tapers asymptotically with an exponential.
US09252484B2	Antenna device and method of antenna configuration A communication antenna device (D), on board a motor vehicle, for communicating with an antenna of a portable device, includes: a communication antenna (A) including a first part (A1) having a maximum number of primary windings (E1MAX) and a second part (A2) having a maximum number of secondary windings (E2MAX), a microcontroller (10) electrically connected to the antenna (A), a first switching element (M1), for connecting the first part and/or the second part to the microcontroller (10), a second switching element (M2), for connecting a determined number of primary windings (E1i) of the first part to the microcontroller (10), a third switching element (M3), for connecting a determined number of secondary windings (E2j) of the second part to the microcontroller (10), and elements for controlling (20) the first, second and third switching elements.
US09252480B2	Two-shaft hinge antenna and foldable electronic device using the same A two-shaft hinge antenna comprises a major conductor, a first rotating element and a second rotating element. The stretching arms on both sides of the major conductor are assembled to the first rotating element and the second rotating element, respectively. The first rotating element further comprises a torque device and a first vice conductor, and the second rotating element further comprises a signal feeding line, a connection device, and a second vice conductor. The signal feeding line is electrically connected to the connection device and the second vice conductor, by which a high frequency signal can be passed to the major conductor, and then passed to the torque device on the other side and the first vice conductor. The aforementioned configuration is utilized to form an antenna loop. In addition, the configuration of this antenna can be applied to a foldable electronic device.
US09252478B2	Method of manufacturing stamped antenna A method of manufacturing a stamped antenna includes providing a sheet of metallic material for a first partial stamping that forms an antenna including at least one pilot hole, traces, contacts, carriers connected to the traces, and tie-bars between the traces. The antenna is placed on a fixture having at least one fixture pin that is inserted through the at least one lot hole. A pressure sensitive adhesive including at least one die cut hole is placed on the fixture, with the fixture pin being inserted through the die cut hole aligning the antenna and the pressure sensitive adhesive such that an adhesive region of the pressure sensitive adhesive is positioned on the traces of the antenna. The pressure sensitive adhesive is then bonded to the traces of the antenna. A second complete stamping is then performed on the antenna, including pressure sensitive adhesive, to remove the carriers and tie-bars.
US09252476B2	Circuit module including a splitter and a mounting substrate In a circuit module, even if a transmission signal output from a transmission electrode of a mounting substrate to a transmission terminal of a splitter leaks into a ground electrode, the transmission signal that has leaked into the ground electrode flows into via conductors that are connected along an edge portion of the ground electrode close to the transmission electrode and connected to a ground line of a motherboard. Therefore, the transmission signal that has been output from the transmission electrode and leaked into the ground electrode is prevented from traveling along an edge portion of the ground electrode toward a reception electrode side. Thus, characteristics of isolation between the transmission electrode and the reception electrode provided on the mounting substrate on which the splitter is mounted are improved.
US09252470B2	Ultra-broadband diplexer using waveguide and planar transmission lines A hybrid diplexer combining planar transmission line(s) and a waveguide is disclosed. In one embodiment, a diplexer includes first, second, and third ports. The diplexer also includes a first signal path and a second signal path. The first signal path may be used to convey lower frequencies, and may be implemented using planar transmission lines. The second signal path may be used to convey higher frequencies, and may be implemented, at least in part, using a waveguide. The first signal path may be coupled between the first port and the second port, while the second signal path may be coupled between the first port and the third port. In one embodiment, the first signal path may implement a low-pass filter, while the second signal path may implement a high-pass filter.
US09252469B2	Microwave circuit in strip line technology A microwave circuit in strip line technology contains metallic resonator strips on one side of a dielectric layer. Alternatively another end of consecutive resonator strips is connected by means of at least one via to a metallic surface on an opposite side of said dielectric layer. Said end of each resonator strip is connected to at least one via and is formed relative to said at least one via so that the effective electrical length of each resonator strip connected through the via is identical.
US09252467B2	Fluid regulating microvalve assembly for fluid consuming cells with spring-like shape-retaining aperture cover A fluid regulating microvalve assembly for use to control fluid flow to a fluid consuming electrode, such as an oxygen reduction electrode, in an electrochemical cell is proposed. The microvalve assembly includes a stationary valve body having an aperture and microactuators movable from a first closed aperture position to at least a second position where fluid is able to pass through the microvalve body aperture. These microactuators control the movement of spring-like shape-retaining interior aperture covers, which covers can be belleville springs or flat springs. The fluid regulating microvalve assembly can utilize cell potential or a separate source. The latter assembly can be located outside or inside the cell housing, for example between a fluid inlet aperture and the fluid consuming electrode. Using a printing process to deposit at least one of the layers is proposed for making the multilayer microvalve assembly for a fluid depolarized battery.
US09252465B2	Battery recharge estimator using battery impedance response An exemplary embodiment includes a method for determining a time to recharge a rechargeable battery system including providing impedance data over a frequency range, said impedance data characterizing the operation of a rechargeable battery within a selected time window; analyzing said impedance data for predetermined behavior of said impedance data indicating an approaching state of discharge of said battery; and, determining from said predetermined behavior of said impedance data whether a recharge of said rechargeable battery is indicated.
US09252452B2	Electrode assembly and composite electrode assembly of stair-like structure Disclosed herein are an electrode assembly and a composite electrode assembly mounted in a battery case of a secondary battery. The electrode assembly and the composite electrode assembly have a stair-like structure. The stair-like structure is formed based on the curvature of a device to utilize a dead space of the device, thereby improving the capacity of the device per unit volume.
US09252448B2	Ceria-based composition including bismuth oxide, ceria-based composite electrolyte powder including bismuth oxide, method for sintering the same and sintered body made thereof Provided are a ceria-based composition having an undoped or metal-doped ceria and an undoped or metal-doped bismuth oxide, wherein the undoped or metal-doped bismuth oxide is present in an amount equal to or more than about 10 wt % and less than about 50 wt % based on the total weight of the ceria-based composition, and at least one selected from the ceria and the bismuth oxide is metal-doped. The ceria-based composition may ensure high sintering density even at a temperature significantly lower than the known sintering temperature of about 1400° C., i.e., for example at a temperature of about 1000° C. or lower, and increase ion conductivity as well.
US09252447B2	Composite anode for a solid oxide fuel cell with improved mechanical integrity and increased efficiency A composite anode for a solid oxide fuel cell (SOFC), comprising an anode support layer (ASL) of Ni—YSZ and an anode functional layer (AFL) of Ni—GDC, displays enhanced mechanical stability and similar or improved electrical efficiency to that of a Ni—GDC ASL for otherwise identical SOFCs. A SOFC employing the composite anode can be used for power generation at temperatures below 700° C., where the composite anode may include a second AFL of GDC disposed between the Ni—GDC layer and a GDC electrolyte.
US09252445B2	Nanofiber membrane-electrode-assembly and method of fabricating same In one aspect of the present invention, a fuel cell membrane-electrode-assembly (MEA) has an anode electrode, a cathode electrode, and a membrane disposed between the anode electrode and the cathode electrode. At least one of the anode electrode, the cathode electrode and the membrane is formed of electrospun nanofibers.
US09252444B2	Fuel cell system A fuel cell system calculates amount of fluid discharged from a fuel gas circulation path with water and fuel gas in accordance with an ordinary process map if inside an anode is not scavenged when a fuel cell stops electrochemical reaction; measures amount of water remaining in a fuel gas circulation path in accordance with cumulative electricity output, temperature, or elapsed time after starting the electrochemical reaction if the inside the anode is scavenged previously; and determines whether the inside the fuel gas circulation path is in dry condition or humid condition. The fuel cell system calculates amount of fluid discharged from the fuel gas circulation path with water or the fuel gas in accordance with a map predetermined for the dry condition if the fuel cell system determines that the inside the fuel gas circulation path is in the dry condition. The fuel cell system calculates the amount of the fluid to be discharged with the water or the fuel gas in accordance with the ordinary map if the fuel cell system determines that the inside the fuel gas circulation path is in the humid condition. Accordingly, wasteful discharge of fuel gas can be prevented in a purging operation after starting up the fuel cell system.
US09252442B2	System and method for controlling fuel cell system Disclosed is a system and method for controlling a fuel cell system. More specifically, a fuel cell demand current is calculated based on a driver demand current calculated from a driver demand torque. Then a target flow rate-1 of air to be supplied to a fuel cell stack is calculated based on the fuel cell demand current and a target stoichiometric ratio (SR) of air. The target flow rate-1 is then compensated for using the target SR, an RPM command value of an air blower is calculated based on a compensated target flow rate-2 and the amount of air currently measured. The operation of the air blower is subsequently controlled based on the calculated RPM command value.
US09252440B2	Gas supply system A gas supply system that supplies a gas after making confluence of the gas flows from gas containers includes: a supply pressure detector that detects supply pressure of the gas following the confluence; and a controller that permits a gas supply-destination apparatus to be activated if the supply pressure detected after an elapse of a determination time from a start of the gas supply is greater than or equal to a threshold pressure, and that prohibits the apparatus from being activated if the supply pressure is less than the threshold pressure. The controller uses a first determination time as the determination time if it is determined that internal pressures that are the gas pressures in the containers are not imbalanced between the containers, and uses a second determination time that is longer than the first as the determination time if it is determined that the internal pressures are imbalanced.
US09252437B2	Apparatus for preventing over-cooling of fuel cell An apparatus preventing over-cooling of a fuel cell is provided that includes a cooling fluid manifold which is mounted to a stack of the fuel cell and through which cooling fluid flows therethrough. End plates are arranged on both ends of the stack of a fuel cell, and at least one protrusion is provided on one surface of each of the end plates. The at least one protrusion is disposed inside a cooling fluid manifold to reduce the flow amount of the cooling fluid which flows in and out between the separating plates through the cooling fluid manifold.
US09252433B2	Liquid reserve batteries for munitions A method for producing power from a liquid reserve battery. The method including heating a liquid electrolyte and forcing the heated liquid electrolyte into gaps dispersed in a battery cell.
US09252430B2	Alkaline cell with improved high rate capability The present disclosure relates generally to an alkaline electrochemical cell, such as a battery, and in particular to an improved gelled anode suitable for use therein. More specifically, the present disclosure relates to a gelled anode that improves anode discharge efficiency by adjusting physical properties such as apparent density.
US09252429B2	Electrode additives coated with electro conductive material and lithium secondary comprising the same Provided are an electrode additive coated with a coating material made of electrically conductive materials such as metal hydroxides, metal oxides or metal carbonates, and an electrode and a lithium secondary battery comprising the same. The electrode additive in accordance with the present invention can improve high temperature storage characteristics of the battery, without deterioration of performance thereof.
US09252428B2	Negative electrode for rechargeable lithium battery, method of preparing the same, and rechargeable lithium battery including the same Disclosed is a negative electrode for a rechargeable lithium battery that includes a current collector and a negative active material layer on the current collector, the negative active material layer having an active mass density in a range of about 1.6 g/cc to about 2.1 g/cc and including graphite and a pore-forming agent.
US09252425B2	Polyacrylonitrile-sulphur composite material The invention relates to a method for preparing a polyacrylonitrile-sulfur composite material, in which, polyacrylonitrile is converted to cyclized polyacrylonitrile, and the cyclized polyacrylonitrile is reacted with sulfur to form a polyacrylonitrile-sulfur composite material. By a separation of the preparation method into two partial reactions, the reaction conditions are advantageously able to be optimized for the respective reactions and a cathode material is able to be provided for alkali-sulfur cells with improved electrochemical properties. In addition, the invention relates to a polyacrylonitrile-sulfur composite material, a cathode material, an alkali-sulfur cell or an alkali-sulfur battery as well as to an energy store.
US09252422B2	Positive electrode for rechargeable lithium battery and rechargeable lithium battery including same Disclosed is rechargeable lithium battery that includes a positive electrode including a positive active material layer, a negative electrode including a negative active material and an electrolyte wherein the positive active material layer includes a positive active material, a binder, a conductive material, and an activated carbon, the activated carbon includes micropores in which manganese ions are adsorbed and trapped, and the activated carbon is included in an amount of about 0.1 wt % to about 3 wt % based on the total weight of the positive active material layer.
US09252421B1	Surface modification of active material structures in battery electrodes Provided herein are methods of processing electrode active material structures for use in electrochemical cells or, more specifically, methods of forming surface layers on these structures. The structures are combined with a liquid to form a mixture. The mixture includes a surface reagent that chemically reacts and forms a surface layer covalently bound to the structures. The surface reagent may be a part of the initial liquid or added to the mixture after the liquid is combined with the structures. In some embodiments, the mixture may be processed to form a powder containing the structures with the surface layer thereon. Alternatively, the mixture may be deposited onto a current collecting substrate and dried to form an electrode layer. Furthermore, the liquid may be an electrolyte containing the surface reagent and a salt. The liquid soaks the previously arranged electrodes in order to contact the structures with the surface reagent.
US09252417B2	Low-floor electric bus The invention provides for a high occupancy or heavy-duty vehicle with a battery propulsion power source, which may include lithium titanate batteries. The vehicle may be all-battery or may be a hybrid, and may have a composite body. The vehicle battery system may be housed within the floor of the vehicle and may have different groupings and arrangements.
US09252416B2	Safety apparatus of battery module for vehicle A safety apparatus of a battery module for a vehicle is provided. The apparatus includes cell terminals disposed in battery cells disposed in a row. A safety bus bar electrically connects two cell terminals disposed diagonally in two battery cells adjacent to each other among the battery cells. In addition, the safety bus bar maintains the electrical connection when the battery cells are not expanded and opens a circuit to prevent electricity from flowing when at least one battery cell is expanded.
US09252415B2	Power sources suitable for use in implantable medical devices and corresponding fabrication methods Arrays of planar solid state batteries are stacked in an aligned arrangement for subsequent separation into individual battery stacks. Prior to stacking, a redistribution layer (RDL) is formed over a surface of each wafer that contains an array; each RDL includes first and second groups of conductive traces, each of the first extending laterally from a corresponding positive battery contact, and each of the second extending laterally from a corresponding negative battery contact. Conductive vias, formed before or after stacking, ultimately couple together corresponding contacts of aligned batteries. If before, each via extends through a corresponding battery contact of each wafer and is coupled to a corresponding conductive layer that is included in another RDL formed over an opposite surface of each wafer. If after, each via extends through corresponding aligned conductive traces and, upon separation of individual battery stacks, becomes an exposed conductive channel of a corresponding battery stack.
US09252407B2	Battery module A battery module including a plurality of battery cells and a cover, each battery cell having a vent portion aligned in one direction, and the cover being over the vent portions, the cover including an internal cavity and at least a portion of the internal cavity including a heat-resistance member.
US09252405B2	Rechargeable secondary battery A secondary battery including a first electrode assembly, a second electrode assembly, a case accommodating the first and second electrode assemblies, a terminal part electrically connected to the first and second electrode assemblies, and exposed to an outside of the case, and a plurality of short circuit inducing members between the first electrode assembly and the case, between the second electrode assembly and the case, and between the first electrode assembly and the second electrode assembly.
US09252398B2	Organic light emitting diode display device and method of fabricating the same A method of fabricating an organic light emitting diode display device, which include forming a thin film transistor in a display region of a substrate, forming a metal pattern on the substrate in the display region, forming a first electrode on the substrate connected to the thin film transistor, forming a bank on the substrate to expose a portion of the first electrode and a portion of the metal pattern, forming a hole common layer, an organic light emitting layer, and an electron common layer sequentially over the entire surface of the substrate provided with the first electrode, the bank and the metal pattern, forming a photoresist pattern covering the electrode common layer and removing the hole common layer, the organic light emitting layer and the electron common layer using the photoresist pattern as a mask, removing the photoresist pattern, and forming a second electrode on the electron common layer connected to the metal pattern.
US09252396B2	Organic electro-luminescence display device An organic electro-luminescence display device includes a first substrate, plural pedestals which are provided in a convex shape on the first substrate and have inclined side surfaces, plural first electrodes respectively provided on the respective side surfaces of the pedestals, an organic electro-luminescence film which is provided above the plural pedestals and includes a light-emitting layer laminated on the plural first electrodes, and a second electrode which is provided above the plural pedestals and is laminated on the organic electro-luminescence film. Light generated in the light-emitting layer is transmitted between a first reflection surface and a second reflection surface. The second electrode includes light transmission parts, through which the light passes, above upper end parts of the pedestals. A surface of the second electrode facing the organic electro-luminescence film is the second reflection surface except for the light transmission parts.
US09252395B2	Organic light-emitting device (OLED) display and method of manufacturing the same An organic light-emitting device (OLED) display is disclosed. In one aspect, the display includes a substrate, a plurality of first electrodes separated from each other over the substrate and a second electrode facing and formed across the first electrodes. The display also includes an intermediate layer interposed between the first electrodes and the second electrode, wherein the intermediate layer comprises an emission layer. The display further includes a plurality of encapsulation layer portions patterned to be separated from each other in an island form over the second electrode.
US09252393B2	Flexible display apparatus including a thin-film encapsulating layer and a manufacturing method thereof A flexible display apparatus includes: a flexible substrate; a display unit on the flexible substrate; and a thin-film encapsulating layer on the display unit. The thin-film encapsulating layer includes at least one organic layer and at least one inorganic layer. The inorganic layer comprises carbon having a concentration gradient distributed at an interface between the at least one organic layer and the at least one inorganic layer. A manufacturing method of the flexible display apparatus is also disclosed.
US09252390B2	Production method for joined body, and joined body A method for manufacturing a joined body composed of a first substrate and a second substrate joined together by sealing resin material attached to a predetermined area of the first substrate includes: attaching a sheet material to the first substrate so as to cover the predetermined area, the sheet material including a sheet base material and the resin material provided on one main surface of the sheet base material; forming, after the attaching, in the sheet material, a slit by reducing a thickness of the resin material along an outline of the predetermined area; and separating, after the forming, part of the resin material inside the slit from the sheet base material to keep the part of the resin material inside the slit on the predetermined area of the first substrate and not to keep the rest of the resin material outside the slit on the first substrate.
US09252389B2	Functional film, environmentally sensitive electronic device package, and manufacturing methods thereof An environmentally sensitive electronic device package including a first adhesive, at least one first side wall barrier, a first substrate, and a second substrate is provided. The first adhesive has a first surface and a second surface opposite to the first surface. The first side wall barrier is distributed in the first adhesive. The first substrate is bonded with the first surface. The first substrate has an environmentally sensitive electronic device formed thereon and the environmentally sensitive electronic device is surrounded by the first side wall barrier. The second substrate is bonded with the second surface. A manufacturing method of the environmentally sensitive electronic device package is also provided.
US09252388B2	Organic light emitting diode (OLED) display An organic light emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate having a light emission area and a non-emission area outside the light emission area, an organic light emitting unit formed on the light emission area and a blocking unit that is disposed on the non-emission area to surround the organic light emitting unit. The OLED display further includes a coating unit formed to coat an external surface of the blocking unit and an encapsulation unit formed by alternately stacking at least one first thin film and at least one second thin film on an area surrounded by the blocking unit so as to encapsulate the organic light emitting unit.
US09252387B2	Illumination device having light-transmitting resin defining appearance of illumination device An illumination device includes a light-emitting element, a wire connected to the light-emitting element to supply electric power to the light-emitting element, and a light-transmitting resin configured to hold the light-emitting element and the wire in one piece. The light-transmitting resin defines an appearance of the illumination device. Light emitted from the light-emitting element is transmitted through the light-transmitting resin to be radiated from an outer surface of the light-transmitting resin.
US09252386B2	Back-emitting OLED device and method for homogenizing the luminance of a back-emitting OLED device An OLED device includes a transparent anode, of sheet resistance R1, and a cathode, of sheet resistance R2, the ratio r=R2/R1 ranging from 0.01 to 2.5, a first anode electrical contact, a first cathode electrical contact, arranged above the active zone, and a reflector covering the active zone above an OLED system, and for each point B of the anode contact, the point B being in an edge of the first anodic region, on defining a distance D between B and the point C closest to the point B, and on defining a distance L between the point B and a point X of an opposite edge of the first anodic region from the first edge, and passing through Ci the following criteria are defined: if 0.01≦r<0.1, then 30%
US09252384B2	Organic light emitting device including an auxiliary electrode An organic light emitting device includes a substrate, a first electrode disposed on the substrate, a first organic layer pattern disposed on the first electrode, an auxiliary electrode pattern alternately disposed with the first organic layer pattern, and including an upper insulation layer, a lower insulation layer, and an auxiliary electrode disposed therebetween, a light emitting layer disposed on the first organic layer pattern and the auxiliary electrode pattern, a second organic layer disposed on the light emitting layer and a second electrode disposed on the second organic layer.
US09252379B2	Organic light emitting device Disclosed is an organic light emitting device that may, for example, include a red pixel including a first red emission layer and a second red emission layer that emit red lights; a green pixel including a first green emission layer and a second green emission layer that emit green lights; a blue pixel including a first blue emission layer and a second blue emission layer that emit blue lights; and a first electrode and a second electrode that supply electric charges to the red, green and blue pixels, wherein a first emission layer and a second emission layer of at least one of the red, green and blue pixels include different materials between a fluorescent material and a phosphor material.
US09252378B2	Organic light-emitting component An organic light-emitting component includes a translucent substrate, on which an optical coupling-out layer is applied. A translucent electrode overlies the coupling-out layer and an organic functional layer stack having organic functional layers overlies the translucent electrode. The organic functional layer stack includes a first organic light-emitting layer on the translucent electrode and a second organic light-emitting layer on the first organic light-emitting layer. The first organic light-emitting layer includes arbitrarily arranged emitter molecules and the second organic light-emitting layer includes anisotropically oriented emitter molecules having an anisotropic molecular structure.
US09252376B2	Composition capable of changing its solubility, hole transport material composition, and organic electronic element using the same An embodiment of the present invention relates to a composition containing a polymer or oligomer (A) having a repeating unit with hole transport properties and also having a thienyl group which may have a substituent, and an initiator (B), wherein the solubility of the composition is capable of being changed by applying heat, light, or both heat and light.
US09252373B2	Electronic devices with yielding substrates In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.
US09252372B2	Complexes for use in optoelectronic components The invention relates to the use of a multinuclear metal or transition metal complex in an organic electronic device, said complex having a small ΔE spacing, particularly between 50 cm−1 and 2000 cm−1, between the lowest triplet state and the singlet state that is higher and is achieved by thermal backfilling from the triplet. The invention further relates to the use of the strong absorptions of such multinuclear metal complexes, particularly in OSCs.
US09252370B2	Heterocyclic compounds and organic light emitting devices including the same Provided are heterocyclic compounds represented by general Formula 1 below and organic light-emitting devices including the same: Such N-substituted diarylamino derivatives of 4,5-iminophenanthrene, when included in color fluorescent or phosphorescent organic light emitting devices in a hole transporting or hole injecting charge transport role, impart high efficiency, low driving voltages, high luminances and long lifetimes to these devices.
US09252369B2	Metal complexes with organic ligands and use thereof in OLEDs The present invention relates, inter alia, to metal complexes having improved solubility, to processes for the preparation of the metal complexes, to devices comprising these metal complexes and to the use of the metal complexes. M(L)n(L′)m formula 1 where the compound contains a moiety M(L)n of the formula (2) W is equal to the formula (3).
US09252366B2	Crosslinkable compound, method for preparing the same and light emitting device comprising the same A crosslinkable compound comprising trifluorovinyl has a structure of Formula (I). A method for preparing the crosslinkable compound and a light emitting device prepared from the compound are also disclosed.
US09252364B2	Method for making organic light emitting diode array The disclosure relates to a method of making organic light emitting diode array. A base defining a plurality of convexities is provided. A number of first electrodes are applied on the plurality of convexities. A number of red light electroluminescent layers are transfer printed on a first group of the first electrodes. A number of green light electroluminescent layers are transfer printed on a second group of the first electrodes. A number of blue light electroluminescent layers are transfer printed on a third group of the first electrodes. A patterned second insulative layer is made to cover the number of first electrodes and expose the electroluminescent layers. A second electrode is electrically connected to the electroluminescent layers.
US09252361B2	Electronic device and method for fabricating the same Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate including first and second areas; a first contact plug contacted with the substrate through the interlayer dielectric layer of the second area; an anti-peeling layer formed over the interlayer dielectric layer including the first contact plug; a second contact plug contacted with the substrate through the anti-peeling layer and the interlayer dielectric layer in the first area; and a variable resistance pattern contacted with the second contact plug.
US09252355B2	Low offset and high sensitivity vertical hall effect sensor A vertical Hall Effect sensor is provided having a high degree of symmetry between its bias modes, can be adapted to exhibit a small pre-spinning systematic offset, and complies with the minimal spacing requirements allowed by the manufacturing technology (e.g., CMOS) between the inner contacts. These characteristics enable the vertical Hall Effect sensor to have optimal performance with regard to offset and sensitivity.
US09252351B2	Actuator and method for producing same The invention relates to an actuator having a sensor layer by which a temperature can be detected, and to a method for producing the same.
US09252350B2	Oscillation piece, oscillator, electronic device, electronic apparatus, and mobile object An oscillation piece includes a first oscillation arm and a second oscillation arm, a first base that connects ends of the first oscillation arm and the second oscillation arm on one side to each other and a second base that connects ends of the first oscillation arm and the second oscillation arm on the other side to each other, and weight films provided on each of the first oscillation arm and the second oscillation arm. The drive electrodes are disposed in positions where the amount of distortion produced in the first oscillation arm and the second oscillation arm is maximized, and the weight films are disposed in positions where the amount of distortion produced in the first oscillation arm and the second oscillation arm is minimized. The oscillation frequency of the oscillation piece can be precisely adjusted by removing part of the weight films.
US09252349B2	Resonator element, resonator, oscillator, and electronic device A resonator element capable of improving impact resistance is provided. A quartz crystal resonator element is a resonator element formed by etching a Z plate which is cut at predetermined angles with respect to the crystal axes of a quartz crystal. The quartz crystal resonator element includes a base, a pair of resonating arms extending from the base in the Y-axis direction, and a positive X-axis notch and a negative X-axis notch formed by notching the base in the X-axis direction. The positive X-axis notch is formed by notching the base from the negative side of the X axis towards the positive side so that the width of the positive X-axis notch increases as it approaches the outer circumference.
US09252348B2	Light emitting lamp Disclosed is a light emitting lamp including a light source module including at least one light source and a light guide layer disposed on a substrate burying the at least one light source, and a housing accommodating the light source module, and the at least one light source includes a body having a cavity, a first lead frame including one end exposed to the cavity and the other end passing through the body and exposed to one surface of the body, a second lead frame including one end exposed to one portion of the surface of the body, the other end exposed to the another portion of the surface of the body, and an intermediate part exposed to the cavity, and at least one light emitting chip including a first semiconductor layer, an active layer and a second semiconductor layer, and disposed on the first lead frame.
US09252347B2	Light emitting device package and light unit having the same Disclosed is a light emitting device package. The light emitting device package includes a package body having a first cavity and a second cavity; a plurality of reflective frames comprising a first reflective frame and a second reflective frame on the first cavity and the second cavity, respectively, and each of the first reflective frame and the second reflective frame comprises a bottom frame and at least two side wall frames extending from the bottom frame; and a light emitting device on the first reflective frame, wherein the first reflective frame and the second reflective frame are electrically separated from each other.
US09252344B2	Structural component and method for producing a structural component The invention relates to a structural component which comprises a support (1), an optoelectronic semiconductor chip (2) having at least one lateral face (2a), further comprising a connecting means (3), a first molded element (4), and a second molded element (5), the optoelectronic semiconductor chip (2) being mechanically connected to the support (1) by the connecting means (3). The first molded element (4) covers an exposed outer face of the optoelectronic semiconductor chip (2) and the first molded element (4) covers an exposed outer face of the connecting means (3). The second molded element (5) covers an exposed outer face of the first molded element (5) and the second molded element (5) has a higher modulus of elasticity at room temperature than the first molded element.
US09252339B2	Red light-emitting nitride material, and light-emitting part and light-emitting device comprising the same Disclosed are a red light-emitting nitride material, a light-emitting part and a light-emitting device comprising the same. The General Formula of the light-emitting material is: Ma(Al,B)bSicNdOe:Eum, Rn, wherein M is at least one of the alkaline earth metal elements Mg, Ca, Sr, Ba and Zn; R is at least one of the rare earth elements Y, La, Ce, Gd and Lu; and 0.9≦a<1.1, 0.9≦b≦1, 1≦c≦1.5, 2.5
US09252337B1	Composite substrate for light emitting diodes A low-cost device for packaging LED dies provides superior reflectivity and thermal conductivity without covering entire surfaces of an LED luminaire with an expensive reflective aluminum substrate. The LED packaging device includes a highly reflective substrate disposed in a hole in a printed circuit board. The substrate has a reflectivity greater than 97% and includes an insulating layer and a reflective layer disposed above a thicker aluminum layer. An LED die is disposed on the top surface of the substrate. The PCB has a layer of glass fiber in resin and a metal layer. The lower surface of the PCB and the bottom surface of the substrate are substantially coplanar. The metal layer of the PCB is electrically coupled to the LED die only through bond wires. Electronic circuitry is disposed on the upper surface of the PCB and is used to control light emitted from the LED die.
US09252336B2	Multi-cup LED assembly A substrate for an LED assembly can have a plurality of cups formed therein. At least one cup can be formed within another cup. The cups can be co-axial with respect to one another, for example. A machined surface of the substrate can enhance reflectivity of the LED assembly. A transparent and/or non-global solder mask can enhance reflectivity of the LED assembly. A transparent ring can enhance reflectivity of the LED assembly. By enhancing reflectivity of the LED assembly, the brightness of the LED assembly can be increased. Brighter LED assemblies can be used in applications such as flashlights, displays, and general illumination.
US09252335B2	Semiconductor light emitting element and method for manufacturing same According to one embodiment, a semiconductor light emitting element includes a conductive substrate, a bonding portion, an intermediate metal film, a first electrode, a semiconductor stacked body and a second electrode. The bonding portion is provided on the support substrate and including a first metal film. The intermediate metal film is provided on the bonding portion and having a larger linear expansion coefficient than the first metal film. The first electrode is provided on the intermediate metal film and includes a second metal film having a larger linear expansion coefficient than the intermediate metal film. The semiconductor stacked body is provided on the first electrode and including a light emitting portion. The second electrode is provided on the semiconductor stacked body.
US09252324B2	Heterojunction light emitting diode A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.
US09252316B2	Ultra thin hit solar cell and fabricating method of the same Disclosed is an ultra-thin HIT solar cell, including: an n- or p-type crystalline silicon substrate; an amorphous silicon emitter layer having a doping type different from that of the silicon substrate; and an intrinsic amorphous silicon passivation layer formed between the crystalline silicon substrate and the amorphous silicon emitter layer, wherein the HIT solar cell further includes a transparent conductive oxide layer made of ZnO on an upper surface thereof, and the surface of the crystalline silicon substrate is not textured but only the surface of the transparent conductive oxide layer is textured, and thereby a very thin crystalline silicon substrate can be used, ultimately achieving an ultra-thin HIT solar cell having a very low total thickness while maintaining light trapping capacity.
US09252314B2	Device and method for solar power generation A photovoltaic device comprising an array of elongate reflector elements mounted substantially parallel to one another and transversely spaced in series, at least one of the reflector elements having an elongate concave reflective surface to reflect incident solar radiation towards a forward adjacent reflector element in the array. The at least one reflector element includes a photovoltaic receptor mounted on the reflector element by a mounting arrangement to receive reflected solar radiation from a rearward adjacent reflector element. The reflector element also includes a heat sink in heat transfer relationship with the photovoltaic receptor, thermally isolating the photovoltaic receptor, at least partially, from the reflector element.
US09252308B2	Thin film structures and devices with integrated light and heat blocking layers for laser patterning Selective removal of specified layers of thin film structures and devices, such as solar cells, electrochromics, and thin film batteries, by laser direct patterning is achieved by including heat and light blocking layers in the device/structure stack immediately adjacent to the specified layers which are to be removed by laser ablation. The light blocking layer is a layer of metal that absorbs or reflects a portion of the laser energy penetrating through the dielectric/semiconductor layers and the heat blocking layer is a conductive layer with thermal diffusivity low enough to reduce heat flow into underlying metal layer(s), such that the temperature of the underlying metal layer(s) does not reach the melting temperature, Tm, or in some embodiments does not reach (Tm)/3, of the underlying metal layer(s) during laser direct patterning.
US09252307B2	Photovoltaic module support system A support system for a solar panel includes a triangular truss with connection points for mounting a photovoltaic module, and a cradle structure that supports the triangular truss and is connected to at least two side supports of the triangular truss. The cradle structure may be driven for rotation about an axis for tracking the sun and several cradle structures can be linked together for tracking movement using a buried linkage system. The truss may also be foldable for ease of transportation and storage.
US09252304B2	Solution processing of kesterite semiconductors Methods for depositing a kesterite film comprising a compound of the formula: Cu2−xZn1+ySn(S1−zSez)4+q, wherein 0≦x≦1; 0≦y≦1; 0≦z≦1; −1≦q≦1, generally include contacting a hydrazine-based solvent, a source of Cu, a source of Sn, a source of Zn carboxylate, a source of at least one of S and Se, under conditions sufficient to form a solution substantially free of solid particles; applying the solution onto a substrate to form a thin layer; and annealing the thin layer at a temperature, pressure, and length of time sufficient to form the kesterite film. Also disclosed are hydrazine-based precursor solutions for forming a kesterite film and a photovoltaic device including the kesterite film formed by the above method.
US09252303B2	Thin film photovoltaic cell structure, nanoantenna, and method for manufacturing A thin film photovoltaic cell structure (1) comprises a substrate (2); a first dielectric layer (3) on the substrate (2); an active layer (4) on the first dielectric layer (3); and a plasmonic light concentrator arrangement (5) on the active layer (4) for coupling incident light at a first wavelength band into the active layer (4). According to the present invention, the thin film photovoltaic cell structure (1) further comprises a second dielectric layer (6) formed of a dielectric material which is transparent at the first wavelength band and at a second wavelength band on the plasmonic light concentrator arrangement (5); the first dielectric layer (3), the active layer (4), the plasmonic light concentrator arrangement (5), and the second dielectric layer (6) being configured to form a resonant cavity for coupling incident light at the second wavelength band into a standing wave confined in the resonant cavity.
US09252300B2	Method for backside-contacting a silicon solar cell, silicon solar cell and silicon solar module For contacting a silicon solar cell a pre-processed silicon substrate with a frontside and a backside is provided. Then, aluminum is deposited on the backside of the pre-processed silicon substrate, wherein aluminum-free regions remain on the backside. Then, a silver-free layer suitable for soldering on the backside of the silicon substrate is deposited so that the silver-free layer suitable for soldering covers at least the aluminum-free regions on the backside.
US09252295B2	Coating material, coating film, backsheet for solar cell module, and solar cell module An object of the present invention is to provide a coating material that can form a coating film that has an excellent adherence for sealants in solar cell modules as well as an excellent resistance to blocking. Further objects are to provide this coating film, a solar cell module backsheet that has this coating film, and a solar cell module that has this coating film. The present invention relates to a coating material that contains a curable functional group-containing fluorinated polymer and a polyisocyanate compound derived from at least one isocyanate selected from the group consisting of xylylene diisocyanate and bis(isocyanatomethyl)cyclohexane.
US09252292B2	Semiconductor device and a method for forming a semiconductor device A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first doping region arranged at a main surface of the semiconductor substrate, an emitter layer arranged at a back side surface of the semiconductor substrate, at least one first conductivity type area separated from the first doping region by a second doping region of the semiconductor substrate and at least one temperature-stabilizing resistance area. The first doping region has a first conductivity type and the emitter layer has at least mainly a second conductivity type. The second doping region has the second conductivity type and the at least one first conductivity type area has the first conductivity type. The at least one temperature-stabilizing resistance area is located within the second doping region and adjacent to the at least one first conductivity type area. Further, the at least one temperature-stabilizing resistance area has a lower variation of a resistance over a range of an operating temperature of the semiconductor device than at least a part of the second doping region located adjacent to the at least one temperature-stabilizing resistance area.
US09252291B2	Nonvolatile semiconductor memory device According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.
US09252290B2	Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and method for operating nonvolatile semiconductor memory element According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
US09252287B2	Display device and electronic appliance A display device with low manufacturing cost, with low power consumption, capable of being formed over a large substrate, with a high aperture ratio of a pixel, and with high reliability is provided. The display device includes a transistor electrically connected to a light-transmitting pixel electrode and a capacitor. The transistor includes a gate electrode, a gate insulating film over the gate electrode, and a first multilayer film including an oxide semiconductor over the gate insulating film. The capacitor includes the pixel electrode and a conductive electrode formed of a second multilayer film which overlaps with the pixel electrode with a predetermined distance therebetween, and has the same layer structure as the first multilayer film. A channel formation region of the transistor is at least one layer, which is not in contact with the gate insulating film, of the first multilayer film.
US09252286B2	Semiconductor device and method for manufacturing the same A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.
US09252285B2	Display substrate including a thin film transistor and method of manufacturing the same A method of manufacturing a display substrate includes forming a gate electrode on a base substrate, forming an active pattern which includes an oxide semiconductor and overlaps with the gate electrode, forming an etch stopper which partially covers the active pattern, and performing a plasma treatment process to promote a reduction reaction to portions of the active pattern exposed by the etch stopper, thereby forming a source electrode and a drain electrode.
US09252276B2	Semiconductor device A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact.
US09252275B2	Non-planar gate all-around device and method of fabrication thereof A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.
US09252274B2	Fin field effect transistors including multiple lattice constants and methods of fabricating the same A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.
US09252273B2	Gate stack and contact structure A process for fabrication of semiconductor devices, particularly fin-shaped Field Effect Transistors (FinFETs), having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.
US09252271B2	Semiconductor device and method of making A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.
US09252259B2	Methods and apparatus of metal gate transistors Methods and devices for forming a contact over a metal gate for a transistor are provided. The device may comprise an active area, an isolation area surrounding the active area, and a metal gate above the isolation area, wherein the metal gate comprises a conductive layer. The contact comprises a first contact part within the conductive layer, above the isolation area without vertically overlapping the active area, and a second contact part above the first contact part, connected to the first contact part, and substantially vertically contained within the first contact part.
US09252253B2	High electron mobility transistor According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer having a 2-dimensional electron gas (2DEG), a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer, at least one channel depletion layer on the channel supply layer; a gate electrode on at least a part of the channel depletion layer, and at least one bridge connecting the channel depletion layer and the source electrode. The channel depletion layer is configured to form a depletion region in the 2DEG. The HEMT has a ratio of a first impedance to a second impedance that is a uniform value. The first impedance is between the gate electrode and the channel depletion layer. The second impedance is between the source electrode and the channel depletion layer.
US09252244B2	Methods of selectively growing source/drain regions of fin field effect transistor and method of manufacturing semiconductor device including a fin field effect transistor The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.
US09252239B2	Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
US09252237B2	Transistors, semiconductor devices, and methods of manufacture thereof Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V material of the sacrificial gate material to form a gate of the transistor comprising a Me-III-V compound material.
US09252235B2	Semiconductor devices and methods of forming the same According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.
US09252232B2	Multi-plasma nitridation process for a gate dielectric A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
US09252231B2	Semiconductor structure and manufacturing method for the same A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a conductive layer, a conductive architecture and a dielectric layer. The conductive layer defines adjacent first openings. The conductive architecture surrounds a portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer and the conductive architecture.
US09252230B2	Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same are provided. The device includes insulating patterns and conductive patterns stacked alternately, a channel layer formed through the insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of the channel layer, and a charge storage layer formed to surround the tunnel insulating layer. An interfacial surface of the tunnel insulating layer in contact with the charge storage layer includes a thermal oxide layer.
US09252227B2	Semiconductor device It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.
US09252226B2	Thin film transistor array panel and manufacturing method thereof Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.
US09252219B2	Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
US09252215B2	Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconductor substrate, and forming a plurality of gate stacks on the insulator layer. Each gate stack wraps around a respective portion of the semiconductor fins. The method further includes forming a dielectric layer on the insulator layer. The dielectric layer fills voids between the semiconductor fins and gate stacks, and covers the semiconductor fins. The method further includes etching at least one portion of the semiconductor fins until reaching the insulator layer such that at least one cavity is formed. The cavity exposes seed regions of the semiconductor fins located between adjacent gate stacks. The method further includes epitaxially growing a semiconductor material from the seed regions to form source/drain regions corresponding to a respective gate stack.
US09252212B2	Power semiconductor device A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.
US09252208B1	Uniaxially-strained FD-SOI finFET Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
US09252205B2	DRAM memory device with manufacturable capacitor A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.
US09252202B2	Test structure and method for determining overlay accuracy in semiconductor devices using resistance measurement Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.
US09252199B2	Integrated inductor and integrated inductor fabricating method The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate.
US09252198B2	Organic light emitting display device with reduced generation of parasitic capacitance and method for manufacturing the same An organic light emitting diode (OLED) display includes: a substrate; a first and a second thin film transistor (TFT) both disposed on the substrate and both having an active layer, a gate, a source and a drain electrode. A gate line is connected to the gate electrode of the first TFT, and a data line is connected to the source electrode of the first TFT. A common power source line is connected to the source electrode of the second TFT, intersects the gate line, and is parallel to the data line. A pixel electrode is connected to the drain electrode of the second TFT. An organic emission layer is disposed on the first electrode. A common electrode line is disposed on the organic emission layer. A secondary common power source line is formed with the same material as and is parallel to the common electrode line.
US09252191B2	Seed layer for a p+ silicon germanium material for a non-volatile memory device and method A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.
US09252190B2	Semiconductor device and method for producing semiconductor device A semiconductor device according to the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped resistance-changing layer formed on the second contact, a reset gate insulating film that surrounds the pillar-shaped resistance-changing layer, and a reset gate that surrounds the reset gate insulating film.
US09252186B1	Pixel array and display device A pixel array and a display device are provided. The pixel array includes a two-dimensional array that is formed by arranging a plurality of color sub-pixels and a plurality of white sub-pixels in the row direction and in the column direction, the color sub-pixels include color sub-pixels in three different colors. For color sub-pixels in each color in each row, color sub-pixels with the same color in the same row are arranged so that, the odd-numbered column sub-pixel and the even-numbered column sub-pixel alternate one by one, or they are disposed by way of groups each including two odd-numbered column sub-pixels alternating with even-numbered column sub-pixels or by way of groups each including two even-numbered column sub-pixels alternating with odd-numbered column sub-pixels.
US09252180B2	Bonding pad on a back side illuminated image sensor A bonding pad structure for an image sensor device and a method of fabrication thereof. The image sensor device has a radiation-sensor region including a substrate and a radiation detection device, and a bonding pad region including the bonding pad structure. The bonding pad structure includes: an interconnect layer; an interlayer dielectric layer (IDL), both layers extending from under the substrate into the bonding pad region; an isolation layer formed on IDL; a conductive pad having a planar portion and one or more bridging portions extending perpendicularly from the planar portion, through the IDL and isolation layers, and to the interconnect layer; and a plurality of non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad in such a way to adjoin its planar and the bridging portions together for releasing potential pulling stress applied thereon and preventing a conductive pad peeling.
US09252179B2	Image sensor structures An image sensor structure is provided. The image sensor structure includes a substrate including a central area and a peripheral area, a sensing area including a plurality of pixels located at the central area of the substrate, a plurality of bond pads disposed at the peripheral area of the substrate, and an array of protrusions disposed between the bond pads and the sensing area and surrounding the sensing area, wherein a largest distance between any two points of the protrusion under a top view is getting smaller from the peripheral area to the central area.
US09252177B2	Solid state imaging device According to one embodiment, a solid state image sensor has a photoelectric conversion element array, a light collecting optical element array, wavelength-selective elements and a reflecting unit. Wavelength-selective elements pass light of the color which is to be detected, and reflect other colors. The reflecting unit further reflects the light that has been reflected by the wavelength-selective elements. The cell includes photoelectric conversion elements for three different light colors. A microlens serving as a light collecting optical element is arranged corresponding to the cell. The reflecting unit includes at least a first reflecting surface and a second reflecting surface. The first reflecting surface faces the wavelength-selective elements. In every cell, the second reflecting surface is enclosed between wavelength-selective elements and the first reflecting surface.
US09252174B2	Solid-state imaging apparatus and electronic apparatus including shielding members connecting with element isolation regions There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members.
US09252167B2	Active device array substrate An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has a transistor region and a transparent region adjacent to each other. The gate electrode is disposed on the transistor region. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region has a second thickness less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are electrically connected to the channel layer. The pixel electrode is disposed on the dielectric layer which is disposed on the transparent region. The pixel electrode is electrically connected to the drain electrode.
US09252163B1	Array substrate, method for manufacturing the same, and display device In the present disclosure, it is provided an array substrate including a pad area, signal lines arranged on the substrate, conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit, and conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit. The conductive connection lines may be connected to the signal lines through a via hole, and may include a first wire and a second wire electrically connected to each other. The second wire may be arranged in such a manner that a contact area between the conductive connection lines and the flexible circuit is not less than a predetermined threshold when the flexible circuit is displaced in a first direction relative to the first wire. The first direction may be substantially perpendicular to an extending direction of the first wire.
US09252162B2	Active matrix substrate The lateral electric field liquid crystal display device (1) includes a first insulating layer (5) that has at least one first reflection enhancing film layer which is made up of two films having respective different refractive indexes and being adjacent to each other. From this, it is possible to provide the lateral electric field liquid crystal display device (1) which can reflect incoming light at a reflectance higher than an original reflectance of a reflective electrode.
US09252157B2	Method to form group III-V and Si/Ge FINFET on insulator and integrated circuit fabricated using the method A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed.
US09252156B2	Conductor structure and method A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.
US09252154B2	Non-volatile memory with silicided bit line contacts An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
US09252153B1	Method of word-line formation by semi-damascene process with thin protective conductor layer A semi-damascene method is described for fabricating wordlines without stringers while maintaining critical cell dimensions when wordline pitch is less than 40 nm. A thin conducting layer protects a storage layer during manufacture, the thin conducting layer then making contact with filled-in conducting material.
US09252151B2	Three dimensional NAND device with birds beak containing floating gates and method of making thereof A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.
US09252149B2	Device including active floating gate region area that is smaller than channel area A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.
US09252147B2	Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band and the second device corresponds to a second RF band that is different from the first RF band.
US09252134B2	Semiconductor device and structure An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the plurality of second transistors include single crystal, and where the second layer includes a through layer via with a diameter of less than 250 nm; a plurality of conductive pads, where at least one of the conductive pads overlays at least one of the second transistors; and at least one I/O circuit, where the at least one I/O circuit is adapted to interface with external devices through at least one of the plurality of conductive pads, where the at least one I/O circuit includes at least one of the first transistors.
US09252133B2	Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).
US09252130B2	Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.
US09252125B2	Stacked semiconductor device and fabrication method for same A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
US09252118B2	CMOS-compatible gold-free contacts A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.
US09252116B2	Semiconductor die mount by conformal die coating A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.
US09252114B2	Semiconductor device grid array package A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.
US09252112B2	Semiconductor package Provided is a semiconductor package, including: a lower package to which elements are mounted; a metal post connected to the lower package and including at least one metal material portion; and an upper package to which elements is mounted, and which is connected to the metal post via a solder ball.
US09252107B2	Semiconductor package having a metal paint layer Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module. Such a module can include a packaging substrate, one or more RF components mounted on the packaging substrate, a ground plane disposed within the packaging substrate, and a plurality of RF-shielding wirebonds disposed on the packaging substrate and electrically connected to the ground plane. The module can further include an overmold structure formed over the packaging substrate and dimensioned to substantially encapsulate the RF component(s) and the RF-shielding wirebonds. The overmold structure can define an upper surface that exposes upper portions of the RF-shielding wirebonds. The module can further include a conductive paint layer having silver flakes disposed on the upper surface of the overmold structure so that the conductive paint layer, the RF-shielding wirebonds, and the ground plane form an RF-shield for the RF component(s).
US09252103B2	Method for manufacturing semiconductor device An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.
US09252099B2	Semiconductor device having multilayer wiring structure and manufacturing method of the same Disclosed is a semiconductor device 1 comprising: a semiconductor chip 10; a multilayer wiring structure 30 stacked on the semiconductor chip 10; and an electronic component 60,80 embedded in the multilayer wiring structure 30.
US09252098B2	Semiconductor apparatus having power through holes connected to power pattern A semiconductor apparatus includes a multilayer interposer substrate including a power layer as an inner layer; a plurality of connection terminals provided on one surface of the interposer substrate; and a semiconductor chip mounted on the other surface of the interposer substrate. Among power terminals, ground terminals, and signal terminals provided in the semiconductor apparatus, all the power terminals are arranged in one power area and the power area includes only the power terminals.
US09252097B2	Semiconductor memory device The semiconductor memory device comprises a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction crossing the first direction, and a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in the crossing portions of the first and second wiring lines. A plurality of first dummy-wiring-line regions are formed in the peripheral area around the memory cell array. A contact is formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions. A plurality of second dummy-wiring-line regions are formed in the periphery of the contact. The mean value of the areas of the second dummy-wiring-line regions is less than the mean value of the areas of the first dummy-wiring-line regions.
US09252096B2	Wiring substrate and method of manufacturing the same A wiring substrate includes a core substrate including a first wiring layer, an interlayer insulating layer formed by a resin layer containing fiber reinforcement material formed on the core substrate and a primer layer formed on the resin layer containing fiber reinforcement material, and the interlayer insulating layer having a via hole reaching the first wiring layer, and a second wiring layer formed on the primer layer, and connected to the first wiring layer through the via hole.
US09252094B2	Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar A semiconductor device has a semiconductor die with a first conductive layer formed over an active surface of the semiconductor die. An insulation layer is formed over the active surface of the semiconductor die. A second conductive layer is conformally applied over the insulating layer and first conductive layer. Conductive pillars are formed over the first conductive layer. Conductive rings are formed around a perimeter of the conductive pillars. A conductive material is deposited over the surface of the conductive pillars within the conductive rings. A substrate has a third conductive layer formed over a surface of the substrate. The semiconductor die is mounted to a substrate with the third conductive layer electrically connected to the conductive material within the conductive rings. The conductive rings inhibit outward flow of the conductive material from under the conductive pillars to prevent electrical bridging between adjacent conductive pillars.
US09252090B2	Resin package A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin which covers the semiconductor substrate, the matching circuit substrate, and the thin plate.
US09252088B2	Semiconductor device and method of manufacturing the same A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.
US09252083B2	Semiconductor chip with power gating through silicon vias A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.
US09252081B2	Semiconductor device having plural memory chip A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.
US09252071B2	Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. The upper card includes one of a photosensor, light emitting element, radio frequency (RF) antenna, and radio frequency emitter. The lower card includes an area array input/output.
US09252068B2	Semiconductor package A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.
US09252066B2	Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.
US09252065B2	Mechanisms for forming package structure In accordance with some embodiments, a package structure and a method for forming a package structure are provided. The package structure includes a semiconductor die and a molding compound partially or completely encapsulating the semiconductor die. The package structure also includes a through package via in the molding compound. The package structure further includes an interfacial layer between the through package via and the molding compound. The interfacial layer includes an insulating material and is in direct contact with the molding compound.
US09252064B2	Fingerprint module and manufacturing method for same A fingerprint module of fingerprint identification chip is provided. The fingerprint module includes a substrate, a fingerprint identification chip, a molding layer, a color layer, and a protecting layer. The substrate includes a pair of surfaces and a plurality of pads. The surfaces are on the opposite sides of the substrate. The pads are exposed on one of the surfaces. The fingerprint identification chip electrically connects with the substrate according to at least a wire. The molding layer disposes on the substrate and covers the fingerprint identification chip and the wire. The color layer disposes on the molding layer. The protecting layer disposes on the color layer.
US09252063B2	Extended contact area for leadframe strip testing A leadframe strip includes a plurality of unit leadframes connected to a periphery of the leadframe strip, each unit leadframe having a die paddle, a plurality of leads and a semiconductor die attached to the die paddle. The leadframe strip is tested by electrically isolating at least the leads from the periphery of the leadframe strip such that at least some of the leads extend uninterrupted beyond a final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The semiconductor dies are tested, which includes probing the die paddles and the leads that extend uninterrupted beyond the final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The unit leadframes are severed from the leadframe strip along the final lead outline of the unit leadframes after testing the semiconductor dies.
US09252062B2	Semiconductor device having optical fuse and electrical fuse A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.
US09252061B2	Overlay mark dependent dummy fill to mitigate gate height variation A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.
US09252060B2	Reduction of OCD measurement noise by way of metal via slots The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.
US09252059B2	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions. During activation annealing for forming the S/D regions, the dopant ions implanted in the metal gate layer diffuse and accumulate at an upper interface of the high-K gate dielectric layer to change the characteristics of the metal gates, and at a lower interface of the high-K gate dielectric layer to form electric dipoles with appropriate polarities by interfacial reaction, so as to realize adjusting of the effective work functions of the metal gates of the opposite types of MOSFETs, respectively.
US09252056B2	Substrate dividing method A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.
US09252045B2	Method for manufacturing a composite wafer having a graphite core A composite wafer including a carrier substrate having a graphite core and a monocrystalline semiconductor substrate or layer attached to the carrier substrate and a corresponding method for manufacturing such a composite wafer is provided.
US09252040B2	Electrostatic chuck To provide an electrostatic chuck, including: a ceramic dielectric substrate having a first major surface on which an object to be processed is mounted, and a second major surface on a side opposite the first major surface, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being integrally sintered with the ceramic dielectric substrate, the ceramic dielectric substrate including a first dielectric layer between the electrode layer and the first major surface, and a second dielectric layer between the electrode layer and the second major surface, and at least the first dielectric layer of the ceramic dielectric substrate having an infrared spectral transmittance in terms of a thickness of 1 millimeter (mm) of not less than 20%.
US09252034B2	Substrate processing system and substrate transferring method A substrate processing system and substrate transferring method is capable of improving substrate-transferring efficiency by transferring a substrate bi-directionally through a substrate transferring device between two rows of processing chambers, and transferring the substrate to a precise position by rotating the substrate transferring device. The processing system includes a transfer chamber, a bi-directional substrate transferring device; and processing chambers which apply a semiconductor-manufacturing process to the substrate. The processing chambers are linearly arranged along two confronting rows, and the transfer chamber is between the two rows of processing chambers. The substrate transferring device includes a moving unit inside the transfer chamber; a bi-directional substrate transferring unit in the moving unit, that transfers the substrate to the processing chamber through a bi-directional sliding movement; and a rotating unit between the moving unit and the bi-directional substrate transferring unit, that rotates the bi-directional substrate transferring unit at a predetermined angle.
US09252032B2	Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.
US09252029B2	Thermal interface material on package A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.
US09252028B2	Power semiconductor module and method of manufacturing the same A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion.
US09252027B1	Method of forming pattern, manufacturing method of semiconductor device and template In accordance with an embodiment, a method of forming a pattern includes forming a first layer on a fabrication target film, making a mold and the first layer push each other to form a protrusion on the fabrication target film, and forming first and second regions, forming a block copolymer layer including first and second blocks in the first and second regions, phase-separating the block copolymer layer, forming second and third layers in the first region, and forming fourth and fifth layers in the second region; and removing the third and fifth layers. The first region is surrounded by the first layer and the protrusion. The second region is surrounded by the first layer and contacts the first region via the protrusion. The third layer is surrounded by the second layer. The fifth layer is surrounded by the fourth layer.
US09252025B2	Method for manufacturing silicon single crystal wafer and electronic device According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.
US09252022B1	Patterning assist feature to mitigate reactive ion etch microloading effect A method of fabricating a semiconductor device includes forming a masking layer on an upper surface of a semiconductor substrate. The masking layer is patterned to form at least one masking element that designates an active region of the semiconductor substrate and at least one patterning assist feature adjacent the at least one masking element. An etching process is performed to form a plurality of semiconductor fins on the semiconductor substrate. The plurality of semiconductor fins include at least one isolated fin formed on the active region according to the at least one masking element and at least one sacrificial fin formed according to the patterning assist feature that reduces a loading effect that occurs during the etching process.
US09252019B2	Semiconductor device and method for forming the same A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.
US09252013B2	Methods and articles including nanomaterial A method of depositing a nanomaterial onto a donor surface comprises applying a composition comprising nanomaterial to a donor surface. In another aspect of the invention there is provided a method of depositing a nanomaterial onto a substrate. Methods of making a device including nanomaterial are disclosed. An article of manufacture comprising nanomaterial disposed on a backing member is disclosed.
US09252010B2	Method for processing structure in manufacturing semiconductor device A method used for processing a structure in manufacturing of a semiconductor device may include polishing the structure to form a polished structure. The polished structure may include a metal member, a dielectric layer that contacts the metal member, and a particle that contacts at least one of the metal member and the dielectric layer. The method may further include applying an organic acid to the polished structure to remove at least a portion of the particle. The particle may be substantially removed, such that satisfactory quality of the semiconductor may be provided.
US09252006B2	Incandescent bulb, filament, and method for manufacturing filament An object of the present invention is to provide a filament showing improved conversion efficiency with a simple configuration. According to the present invention, surface of a filament material processed into a predetermined shape is processed into a mirror surface by mechanical polishing, and surface roughness (center line average roughness Ra) thereof is thereby made to be 1 μm or smaller. Reflectance of the filament can be thereby improved, and emissivity of the filament for lights of the infrared wavelength region can be suppressed.
US09252004B2	Ionization device, mass spectrometry apparatus, mass spectrometry method, and imaging system A mass spectrometry apparatus includes a holding table that holds a specimen to be ionized, a probe that identifies a portion of the specimen to be ionized, an ion extraction electrode that extracts ions obtained by ionizing the specimen, a liquid supplying unit that supplies liquid to between the specimen and the probe to form a liquid bridge between the specimen and the probe, a vibrating unit that vibrates one of the probe and the holding table, an electric field generating unit that generates an electric field between the probe and the ion extraction electrode, a mass spectrometry unit that mass analyzes ions extracted by the ion extraction electrode, and a synchronization unit configured to synchronize a time at which ions are generated from the portion with a time at which the mass spectrometry unit measures the ions.
US09252003B2	Absolute quantitation of proteins and protein modifications by mass spectrometry with multiplexed internal standards A method for absolute protein or peptide quantitation by mass spectroscopy. A sample containing a protein or peptide of interest is prepared for mass spectroscopy analysis. The sample is subjected to mass spectroscopy analysis at low resolution whereby a single additive mass spectroscopy peak is obtained, then is subjected to high resolution mass spectroscopy analysis whereby a plurality of mass spectroscopy peaks are obtained. The intensity of each of the plurality of mass spectroscopy peaks is quantitated either by comparison to an internal standard set, or by using a standard curve generated for each isotopologue set. Quantitation using a standard curve enhances quantitation across a dynamic range of analyte.
US09252001B2	Plasma processing apparatus, plasma processing method and storage medium A plasma processing apparatus includes a first electrode and a second electrode so arranged in the upper portion of a processing chamber as to face a mounting table, a gas supply unit for supplying a processing gas between the first electrode and the second electrode, a RF power supply unit for applying a RF power between the first electrode and the second electrode for converting the process gas supplied between the electrodes into a plasma, and a gas exhaust unit for evacuating the inside of the processing chamber to a vacuum level from the lower portion of the processing chamber. Since the electron temperature in the plasma is low near a substrate on the mounting table, damage to the substrate caused by the plasma can be suppressed. In addition, since a metal can be used as a material for the processing chamber, the processing chamber can have good temperature controllability.
US09251999B2	Capacitively-coupled plasma processing system having a plasma processing chamber for processing a substrate A capacitively-coupled plasma processing system having a plasma processing chamber for processing a substrate is provided. The plasma processing system includes at least an upper electrode and a lower electrode for processing the substrate, the substrate being disposed on the lower electrode during plasma processing. The plasma processing system further includes means for providing at least a first RF signal to the lower electrode, the first RF signal having a first RF frequency. The first RF signal couples with a plasma in the plasma processing chamber, thereby inducing an induced RF signal on the upper electrode. The plasma processing system further includes means for rectifying the induced RF signal to generate a rectified RF signal such that the rectified RF signal is more positively biased than negatively biased, wherein the substrate is configured to be processed while the rectified RF signal is provided to the upper electrode.
US09251996B2	Charged particle beam device, position adjusting method for diaphragm, and diaphragm position adjusting jig In a charged particle beam device that performs observation of a sample under a gas environment in atmospheric pressure or pressure substantially equal to the atmospheric pressure, a diaphragm that separates an atmospheric pressure space, in which the sample is placed, and a vacuum space in an interior of an electron optical lens barrel is made very thin in order to allow an electron beam to transmit therethrough and damaged with a high possibility. Although at the time of replacing the diaphragm, it is necessary to adjust a position of a diaphragm, it is impossible to easily perform the adjustment of the position of the diaphragm by a conventional method. In a charged particle beam device with a configuration in which a thin film that separates a vacuum environment and an atmospheric environment or a gas environment is employed, a detachable diaphragm that partitions a space, in which a sample is placed, in such a manner that pressure in the space in which the sample is placed is maintained at a level larger than pressure in an interior of a housing, and that allows transmission or passage of a primary charged particle beam therethrough, and a movable member that can move the diaphragm in a state where the pressure in the space, in which the sample is placed, and the pressure in the interior of the housing are maintained as they are, are provided.
US09251993B2	X-ray tube and anode target According to one embodiment, an X-ray tube including an electron emission source which emits an electron, an anode target which comprises a target layer emitting an X-ray by the electron from the electron emission source, and a substrate supporting the target layer and composed from a carbide-strengthened molybdenum alloy, an evacuated outer surrounding envelope which contains the electron emission source and the anode target, a diffusion barrier layer which is integrally formed with the substrate by a powder metallurgy method on a part of a top surface of the substrate and is composed of a high-melting-point metal lacking of carbon-element content compared with carbon-element content in the substrate, and a thermal radiation film which is formed on at least a part of a top surface of the diffusion barrier layer and composed of metallic oxide.
US09251990B2	Method for producing a thermoelectron emission source and method for producing a cathode A method for producing a thermoelectron emission source for an electron gun used in an electron beam writing apparatus, the thermoelectron emission source producing method comprising, preparing a first material that emits a thermoelectron, coating the first material with a second material having a work function larger than that of the first material, exposing the first material from part of the second material by machine processing, and decreasing a diameter of the exposed portion of the first material by heating treatment when the diameter of the exposed portion is larger than a predetermined diameter value.
US09251987B2	Emission surface for an X-ray device Embodiments of the disclosure relate to electron emitters for use in conjunction with X-ray devices. In one embodiment, the emitter features a round emission area capable of emitting electrons when heated, wherein the round emission area comprises at least one of a gap, a channel, or a combination thereof that separates a first portion of the round emission area from a second portion of the round emission area and permits thermal expansion of the first portion and the second portion within the at least one gap or channel without permitting the first portion and the second portion to touch one another. The two electrically conductive legs coupled to the surface at respective locations outside the round emission area and that are capable of supplying current to the round emission area.
US09251986B2	Rechargeable battery A rechargeable battery includes a case, an electrode assembly in the case, a current collecting member electrically connected to the electrode assembly, a fuse part in the current collecting member, and an elastic member adjacent to the fuse part. The elastic member is configured to provide an elastic force to the fuse part.
US09251974B2	Thin key structure and pressable module thereof A thin key structure includes a circuit module, a frame having has a retaining portion, an elastic member disposed on the circuit module and arranged in the frame, and a pressable module having a positioning sheet and a key. The positioning sheet has an assembling portion installed on the frame, a connecting portion, and an extending portion connecting there-between. The key has a key body fixed on the connecting portion and a stopping portion extended from the key body. The key body has a concaving portion aligning the extending portion. The stopping portion is movably arranged in the retaining portion. When non-center portion of the key body is pressed, part of the stopping portion, away from the pressed portion of the key body, abuts against the corresponding retaining portion for being a fulcrum, such that the pressed portion of the key body rotates to press the elastic member.
US09251973B2	Push button switch and electronic apparatus using same A switch includes a switch main body having a movable section displaceable downward by pressure to bring a movable contact into contact with a fixed contact, the movable section being displaced upward to open each contact by a release of pressure; a button section that presses the movable section in response to a downward pressing operation; and a support arm having one end portion supporting the button section. An end of the support arm not coupled to the button section is turnable and held at a location in a support surface arranged vertically. The button section bottom surface is inclined and separated from the movable section when the button section is not pressed. When the button section is pressed and is lowered to a position at which the fixed contact and the movable contact are closed, the bottom surface is in an approximately horizontal state and presses the movable section.
US09251972B2	Electric switching device and related electric apparatus An electric switching device for an electric circuit, including at least one electric phase having at least one circuit breaking unit associated with a disconnector unit. The circuit breaker unit including a circuit breaker movable contact configured to be actuated between a closed position and an open position with respect to a corresponding circuit breaker fixed contact. The disconnector unit includes at least one disconnector movable contact configured to be actuated between a connection position and a disconnection position with respect to a corresponding disconnector fixed contact. A casing that includes an insulating shell coupled to a metal shell. The casing houses at least the circuit breaker unit and the associated disconnector unit of said at least one electric phase.
US09251968B2	Free-standing hybrid nanomembrane as energy storage electrode and the fabrication method thereof Disclosed is a free-standing hybrid nanomembrane capable of energy storage. The free-standing hybrid nanomembrane includes carbon nanotube sheets and a conducting polymer coated on the carbon nanotube sheets. The carbon nanotube sheets are densified sheets formed by evaporating an alcohol from carbon nanotube aerogel sheets. The conducting polymer is coated on the carbon nanotube sheets by vapor phase polymerization. Further disclosed is a method for fabricating the free-standing hybrid nanomembrane.
US09251962B2	Dye-sensitized solar cell module using thin glass substrate and method of manufacturing the same Disclosed are a dye-sensitized solar cell module and a method of manufacturing the same. The dye-sensitized solar cell module includes a working electrode formed by stacking a collector and a photo-electrode to which a dye is adsorbed on a transparent conductive substrate; a counter electrode formed by stacking a collector and a catalytic electrode on a transparent conductive substrate; and an electrolyte filled in a space between the working electrode and the counter electrode sealed by a sealant. A glass substrate for the working electrode of glass substrates forming the transparent conductive substrates for the electrodes is a thin glass plate substrate thinner than the glass substrate for the working electrode.
US09251955B2	PZT-based ferroelectric thin film and method of forming the same A PZT-based ferroelectric thin film is formed by coating a PZT-based ferroelectric thin film-forming composition on a lower electrode of a substrate one or two or more times, pre-baking the composition, and baking the composition to be crystallized, and this thin film includes PZT-based particles having an average particle size in a range of 500 nm to 3000 nm when measured on a surface of the thin film, in which heterogeneous fine particles having an average particle size of 20 nm or less, which are different from the PZT-based particles, are precipitated on a part or all of the grain boundaries on the surface of the thin film.
US09251952B2	Method for manufacturing laminated coil devices A method of manufacturing a laminated coil device includes conductors for forming coils and insulation stacking for forming laminated bodies, and further includes the steps of: (A) manufacturing ceramic insulating thin sheets; (B) forming ceramic insulating thin sheets with conductive through-holes; (C) manufacturing coil thin sheets with coil conductors so as to embed the coil conductors inside the ceramic insulating thin sheets; (D) orderly stacking and cutting ceramic insulating thin sheets and coil thin sheets with coil conductors into unit sizes in order to obtain laminated bodies; (E) heating the laminated bodies in order to remove the binder, and then sintering the laminated bodies; (F) coating the conductive paste on the two ends of the laminated bodies so as to form external electrodes. Thus, the present invention is to provide a manufacturing method of producing a laminated coil power device with low direct current resistance, no delamination, no air space, and no lamination cracking.
US09251948B2	High efficiency on-chip 3D transformer structure A transformer structure includes a first coil having two sections of spiral, with a top section including a plurality of metal layers occupying top X metal layers and a bottom section including a plurality of metal layers occupying bottom Z metal layers, where X and Z represent a number of metal layers having a specific number selected to provide a particular performance of the first coil. A second coil of the transformer is disposed between the two sections of the first coil and includes a plurality of metal layers where Y represents a number of vertically adjacent metal layers, with the specific number chosen to provide the particular performance, such that a sum X+Y+Z represents a total number of vertical metal layers for the transformer structure.
US09251947B2	Liquid cooling arrangement of an inductive component and a method for manufacturing an inductive component The object of the invention is a liquid cooling arrangement of an inductive component and a method for manufacturing the inductive component. The inductive component comprises at least a core (1) assembled from separate structural elements (7, 7a, 7b) as well as liquid cooling ducts (8a) integrated into the core (1) for the purpose of liquid cooling and a winding structure (3) around the core (1). The core (1) is assembled from subassemblies formed from structural elements (7, 7a, 7b), which subassemblies are separately composed of e.g. vertical pillars (35), a top horizontal beam (36) and a bottom horizontal beam (37), and cooling liquid ducts (8a) or cooling liquid pipes (10) are placed in at least a part of the subassemblies before final assembly of the core (1).
US09251943B2	Multilayer type inductor and method of manufacturing the same There is provided a multilayer type inductor, including: an inductor main body; a coil part having conductive circuits and conductive vias formed in the inductor main body; and external electrodes formed on both ends of the inductor main body, wherein in the inductor main body, at least parts around the conductive circuits and the conductive vias are formed of a ferrite material or a non-magnetic material.
US09251940B2	Inductor An inductor includes a first core, a conducting wire, a second core and a first lead frame. There is an accommodating space formed on a first side of the first core and there is a recess portion formed on a second side of the first core, wherein the first side is opposite to the second side. The first core has a first height. The conducting wire is disposed in the accommodating space. The second core is disposed on the first side of the first core and covers the accommodating space. The first lead frame has an embedded portion embedded in the recess portion. The embedded portion has a second height. After embedding the embedded portion in the recess portion of the first core, a total height of the embedded portion and the first core is smaller than the sum of the first height and the second height.
US09251936B2	Resistor and method for making same A metal strip resistor is provided. The metal strip resistor includes a metal strip forming a resistive element and providing support for the metal strip resistor without use of a separate substrate. There are first and second opposite terminations overlaying the metal strip. There is plating on each of the first and second opposite terminations. There is also an insulating material overlaying the metal strip between the first and second opposite terminations. A method for forming a metal strip resistor wherein a metal strip provides support for the metal strip resistor without use of a separate substrate is provided. The method includes coating an insulative material to the metal strip, applying a lithographic process to form a conductive pattern overlaying the resistive material wherein the conductive pattern includes first and second opposite terminations, electroplating the conductive pattern, and adjusting resistance of the metal strip.
US09251933B2	Superconducting joints A superconducting joint and a cooling surface are provided as a combination. The superconducting joint joins superconducting wires each comprising superconducting filaments electrically joined together. The cooling surface comprises a thermally and electrically conductive material. An electrically isolating surface coating is provided on the cooling surface. The superconducting joint, the surface coating and the cooling surface are in thermal contact. The superconducting joint is electrically isolated from the cooling surface by the surface coating. The tails of the superconducting wires are wrapped around the electrically isolating surface coating.
US09251931B2	NbTi superconductor with peripherally distributed Al block for weight reduction A superconducting wire (1; 31), contains NbTi superconducting material and Cu, with one enclosing tube (2), in particular, a copper enclosing tube. At least three Al blocks (3a-3c) are disposed peripherally distributed in the enclosing tube (2) and at least three sections containing NbTi (4a-4c) are also disposed peripherally distributed in the enclosing tube (2) and separate the Al blocks (3a-3c) from one another in the peripheral direction. The Al blocks (3a-3c) each make large-surface contact with their adjacent sections containing NbTi (4a-4c). A stabilized NbTi superconducting wire is thereby provided, which has low weight and which can be manufactured at low cost. The superconducting wire has a reduced risk of crack formation, in particular, during wire drawing.
US09251930B1	Segmented shields for use in communication cables Cables incorporating discontinuous shields are described. A cable may include at least one twisted pair of individually insulated conductors, and a shield may be formed around the at least one twisted pair. The shield may include a plurality of segments positioned along a longitudinal direction of the cable. Each segment may include electrically conductive material, and each segment electrically isolated from the other segments. Additionally, a respective overlap may be formed between adjacent segments along a shared longitudinal edge. A jacket may be formed around the at least one twisted pair and the shield.
US09251926B2	Collective conductor and method for producing collective conductor A collective conductor includes a plurality of conductive wires that is arranged collectively; and a copper foil that is wound around the collectively-arranged conductive wires and fusion-bonded to the conductive wires, and the copper foil has a tin plating on the side in contact with the conductive wires.
US09251925B2	Conductive paste for external electrodes and multilayer ceramic electronic component using the same There are provided a conductive paste for external electrodes and a multilayer ceramic electronic component using the same. The conductive paste includes a conductive metal powder including conductive metal particles; and a conductive amorphous metal powder including amorphous metal particles having a(Si, B)-b(Li, K)-c(V, Mn) in which a+b+c=100, 20≦a≦60, 10≦b≦40, and 2≦c≦25 are satisfied.
US09251924B2	Elastomeric conductive materials and processes of producing elastomeric conductive materials Processes for the preparation of elastomeric conductive material, involving combining at least one conductive polymer with rubber latex, at least one organic acid, at least one oxidant, a pH stabilizer, optionally an organic solvent, and optionally at least one surfactant. Also disclosed are elastomeric conductive materials produced by such processes, which exhibit excellent strength, elasticity, and conductivity.
US09251923B2	Varnish containing good solvent and poor solvent A varnish comprising a ground substance consisting of a polymer or oligomer of 200 to 50′104 molecular weight or organic compound of 200 to 1000 molecular weight and a solvent containing a good solvent and a poor solvent whose boiling point (under 760 mmHg) is at least 20° C. lower than that of the good solvent, wherein the ground substance is dissolved in the solvent. Any thin film prepared from this varnish is substantially from generation of foreign matter, so that it can appropriately be used as thin films for electronic devices and those for use in other technical fields.
US09251920B2	In-situ and external nuclear reactor severe accident temperature and water level probes A system for monitoring a state of a reactor core in a nuclear reactor may include an internal monitoring device located inside the reactor core, the internal monitoring device including one or more internal sensor arrays configured to take measurements of conditions of the reactor core at different vertical regions within the reactor core to generate internal measurement data; an external monitoring device located in the reactor structure outside the reactor core, the external monitoring device including one or more external sensor arrays configured to take measurements of conditions of the reactor core at positions outside the reactor core corresponding the plurality of different vertical regions within the reactor core to generate external measurement data, and a transmitter configured to wirelessly transmit the external measurement data; and a receiver station configured to determine a state of the reactor core based on the external and internal measurement data.
US09251919B2	Pressurized water reactor The pressurized water reactor according an embodiment comprises: a cylindrical reactor pressure vessel (1) to which inlet nozzles are connected; fuel assemblies which are contained within the reactor pressure vessel (1); a cylindrical reactor core barrel (3) which surrounds the fuel assemblies and forms an annular downcomer (6) between the reactor core barrel (3) and the inner surface of the reactor pressure vessel (1); and radial supports. The radial supports are supports which are arranged below the downcomer (6) at intervals in the circumferential direction, each has vertical flow path formed therein, and position the reactor core barrel (3) and the reactor pressure vessel (1). The radial supports each has, for example, a flow path-equipped radial keys (21) and a key groove member (40).
US09251918B2	Semiconductor memory device A semiconductor memory device includes: a bank including a normal area including normal columns, and a redundancy area including redundancy columns and to be replaced with a failure column of the normal area; sense amplifiers connected to the normal area; and a redundancy sense amplifier connected to the redundancy area. A normal replacement unit is formed of normal columns allocated to each of the sense amplifiers. A redundancy replacement unit is formed of redundancy columns allocated to the redundancy sense amplifier. The redundancy replacement unit is smaller than the normal replacement unit.
US09251916B2	Integrated clock architecture for improved testing A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing overhead associated with testing. A delay may be incorporated into the path of the clock signal of one of the on-chip controllers to reduce instantaneous power draw during testing.
US09251913B2	Infrastructure for performance based chip-to-chip stacking A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
US09251911B2	Shift register circuit A shift register circuit includes first-type and second-type shift registers, each comprising a pull-down control circuit, a pull-down circuit, a key pull-down circuit, a 3D-mode pull-up circuit, and a 2D-mode pull-up circuit. The pull-down circuit is connected to the pull-down control circuit. The key pull-down circuit, connected to the pull-down circuit, pulls down a driving signal and a gate control signal. When the 2D-mode pull-up circuit operates, a first-type shift register generates a driving signal for a second-type shift register. When the 3D-mode pull-up circuit operates, a first-type shift register generates another driving signal for another first-type shift register.
US09251907B2	Memory devices and methods of operating memory devices including applying a potential to a source and a select gate between the source and a string of memory cells while performing a program operation on a memory cell in the string Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.
US09251904B2	Nonvolatile memory device and memory system including the same A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.
US09251902B2	Semiconductor storage device The semiconductor storage device of the embodiment includes memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A sense amplifier unit is connected to the bit lines. A data write operation includes a first write loop and a second write loop. The first write loop includes a first program operation and a first verify operation. The second write loop includes a second program operation and a second verify operation. A maximum value of a consumed current in the first verify operation is substantially equal to a maximum value of the consumed current in the second verify operation. The consumed current in the first verify operation is substantially same as the consumed current in the second verify operation if data input in the data write operation is all equal to first data corresponding to an erasure state.
US09251901B2	Semiconductor memory device with high threshold voltage distribution reliability method A semiconductor memory device includes: a memory array including a plurality of memory cells; and a peripheral circuit configured to change a voltage level of a bit line connected to a program target cell according to a threshold voltage of the program target cell among the memory cells during a program operation.
US09251900B2	Data scrambling based on transition characteristic of the data A method of storing data includes receiving data to be written to a memory device. The method includes selecting a scrambling operation from at least a first scrambling operation and a second scrambling operation. The scrambling operation is selected based on a transition characteristic associated with the data. The method includes scrambling the data according to the selected scrambling operation and storing the scrambled data in the memory device. Additionally, the method may include descrambling the scrambled data to produce descrambled data.
US09251892B1	Memory system and method of controlling nonvolatile memory According to an embodiment, a controller specifies a first voltage range that has a first distribution quantity, a second voltage range that is adjacent to a lower voltage side of the first voltage range, and a third voltage range that is adjacent to a higher voltage side of the first voltage range. The first distribution quantity is a minimum value of the memory cells. The controller determines a read voltage by using the first voltage range, a first representative voltage value in the first voltage range, the first distribution quantity, a second distribution quantity corresponding to the second voltage range, and a third distribution quantity corresponding to the third voltage range.
US09251887B2	Static random access memory system and operation method thereof A static random access memory system includes a static random access memory, a multiplexer, an input buffer, an output buffer, and a shifter. The input buffer writes write data stored in the input buffer to addresses of the static random access memory corresponding to a write address signal according to a write command. The output buffer reads read data of addresses of the static random access memory corresponding to a read address signal according to a read command. The multiplexer transmits the write address signal and the read address signal to the static random access memory, and generates the write command and the read command. The shifter shifts the write command to an operation clock behind the read command when the write command and the read command exist simultaneously.
US09251885B2	Throttling support for row-hammer counters Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.
US09251882B2	Magnetic random access memory with dynamic random access memory (DRAM)-like interface A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data.
US09251878B2	Nonvolatile memory device and related wordline driving method A nonvolatile memory device comprises multiple memory blocks each comprising multiple memory cells arranged at intersections of wordlines and bitlines, an address decoder configured to electrically connect first lines to wordlines of one of the memory blocks in response to an address, a line selection switch circuit configured to electrically connect the first lines to second lines in different configurations according to the address, a first line decoder configured to provide the second lines with wordline voltages needed for driving, and a voltage generator configured to generate the wordline voltages.
US09251876B1	Retiming programmable devices incorporating random access memories A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.
US09251873B1	Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.
US09251869B2	Deep sleep wakeup of multi-bank memory A deep sleep wakeup signal is received at a first memory bank. A first gated memory array supply voltage is increased in response to the receiving the deep sleep wakeup signal at the first memory bank. The first memory array supply voltage is applied to a first memory array. The deep sleep wakeup signal is forwarded to a second memory bank in response to determining the first gated memory array supply voltage has reached a specified voltage.
US09251864B2	System and method for providing voltage supply protection in a memory device The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.
US09251862B2	Semiconductor device A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
US09251858B2	Method and apparatus for providing stackable hard-disk drive carrier using pull-out drawers A method and apparatus for providing a stackable hard-disk drive (“HDD”) carrier using pull-out drawers and fasteners are disclosed. The carrier, in one embodiment, includes an inner case or drawer and an outer frame casing. The inner cage includes a base plate, a front cover, a first side panel, and a second side panel, wherein the first and second side panels are hinged to the base plate. The inner cage is configured to house a removable HDD. The first and second side panels also include fasteners for securing the HDD to the inner cage. The outer frame casing is configured to receive the inner cage via its two opposite guiding walls. The guiding walls are configured to allow extending the inner cage to a predefined distance from the outer frame casing for accessing the HDD.
US09251857B2	Method of predicting a noise component associated with a readback signal from a dedicated servo medium, noise predictor thereof, and hard disk drive system There is provided a method of predicting a noise component associated with a readback signal in a channel from a dedicated servo medium including a data recording layer and a dedicated servo layer. The method including: providing at least one noise prediction module for each of a plurality of types of servo patterns of the servo layer, and predicting the noise component by, for each of a plurality of segments of the readback signal of the data recording layer, using a selected one of the noise prediction modules. In particular, the selected one of the noise prediction module for a segment of the readback signal is selected based on the type of the servo pattern associated with the segment of the readback signal. There is also provided a corresponding noise predictor, a method of detecting data bits from the readback signal, and a hard disk drive system.
US09251842B1	Digital optical disc magazine Technology is provided for digital optical disc magazines. The disc magazine includes a cabinet, at least one disc drive positioned within the cabinet, and a plurality of drawers disposed in the cabinet. A plurality of disc trays are disposed in the plurality of drawers and each disc tray includes a plurality of disc locations. A bi-directional disc pusher is supported on a gantry between adjacent drawers and is positionable along the adjacent drawers proximate a selected target disc location corresponding to one of the plurality of disc locations. A robotic gripper is positionable adjacent the target disc location and operative to grip a disc pushed at least partially from the target disc location by the disc pusher and to transport the disc to the disc drive.
US09251840B2	Dynamically controlling tape velocity A maximum velocity is dynamically determined during a tape drive operation to obtain a statistical standard deviation of a position error signal (PES) that yields an amount of stopwrite (SW) operations that avoids backhitching. The tape velocity is adjusted to the maximum velocity.
US09251838B2	Apparatus and method for controlling transportation of tape medium An apparatus, computer readable medium device, and method for controlling transportation of a tape medium. A determination is made whether to execute a backhitch operation in response to writing a data set to tape from the buffer. If not, a determination is made whether a transaction size at which data is transferred from the buffer to the tape is less than a buffer size. If so, then a determination is made of a a new speed and whether a current speed is different from the determined new speed. If so, then a backhitch is initiated.
US09251837B2	HAMR NFT materials with improved thermal stability An apparatus that includes a near field transducer, the near field transducer including silver (Ag) and at least one other element or compound, wherein the at least one other element or compound is selected from: copper (Cu), palladium (Pd), gold (Au), zirconium (Zr), zirconium oxide (ZrO), platinum (Pt), geranium (Ge), nickel (Ni), tungsten (W), cobalt (Co), rhodium (Rh), ruthenium (Ru), tantalum (Ta), chromium (Cr), aluminum (Al), vanadium (V), iridium (Ir), titanium (Ti), magnesium (Mg), iron (Fe), molybdenum (Mo), silicon (Si), or combinations thereof oxides of V, Zr, Mg, calcium (Ca), Al, Ti, Si, cesium (Ce), yttrium (Y), Ta, W or thorium (Th), Co, or combinations thereof; or nitrides of Ta, Al, Ti, Si, indium (In), Fe, Zr, Cu, W, boron (B), halfnium (Hf), or combinations thereof.
US09251836B2	Optical disc apparatus, sheet member, and method for cleaning objective lens The present application discloses optical disc apparatus including: drive mechanism for rotating medium including processing surface to be subjected optical information process; housing for storing drive mechanism; tray mechanism for displacing medium between storage position, at which medium is stored in housing, and ejection position, at which medium is ejected from housing; at least one objective lens for condensing light onto processing surface of medium situated at storage position to perform information process; and first displacement mechanism for displacing at least one objective lens along processing surface between first position and second position which is more distant from rotational center of medium rotated by the drive mechanism than first position is. Tray mechanism defines at least one opening in position closer to second position than first position.
US09251835B2	Patterned magnetic media with offset data and servo regions A patterned magnetic media having offset servo and data regions. The media can be constructed by a method that allows both a data region and a servo region to be patterned without the patterning of one region adversely affecting the patterning of the other region. The method results in a patterned data region a patterned servo region and intermediate regions between the servo and data regions. The intermediate regions, which are most likely, but not necessarily, asymmetrical with one another indicate that the method has been used to pattern the media.
US09251834B2	Magnetic recording medium and magnetic storage apparatus A magnetic recording medium includes a substrate, a magnetic layer including an alloy having an L10 type crystal structure as a main component thereof, and a plurality of underlayers arranged between the substrate and the magnetic layer. The plurality of underlayers include at least one crystalline underlayer which has a (100) orientation, and includes W as a main component thereof and one or more kinds of elements selected from a group consisting of Fe, Ni, Co, Hf, Zr, Y, Be, Ce, La, and Sc.
US09251832B2	Hexagonal ferrite magnetic powder and magnetic recording medium An aspect of the present invention relates to hexagonal ferrite magnetic powder, which has an activation volume ranging from 900 nm3 to 1,600 nm3, and a ratio of a coefficient of plate thickness variation to a coefficient of particle diameter variation, coefficient of plate thickness variation/coefficient of particle diameter coefficient, ranging from 0.20 to 0.60.
US09251829B2	Head DFH protrusion shape calibration by HDI sensor Dynamic fly height (DFH) controlled read/write heads using multiple heaters have their heater powers set within a range of ratios that allows minimum clearances to be set between the read-gap and the write-gap and the surface of a disk, thereby providing improved touch-down detection. Determining the correct range of power ratios requires varying the ratio to create an adjustable protrusion profile for the read and write elements in the head and measuring values of the ratio and corresponding values of read gap and write gap clearances that create points of minimum clearance. By adjusting the ratio of power supplied to the heaters, different protrusion profiles can be produced, clearance control for sigma reduction can be obtained and read/write readiness and operation consistency and reliability can be improved.
US09251824B1	Bimodal modulation An apparatus and associated method employing a bridge circuit having first and second microactuators attached to the apparatus. An excitation source is configured to independently drive each of the microactuators. A computation module is connected to the bridge circuit and is configured to independently measure an electrical output of each microactuator. The computation module uses the electrical outputs to characterize a bimodal modulation of the apparatus.
US09251822B2	Assembly formed of nanotube arrays containing magnetic nanoparticles A magnetic storage medium is formed of magnetic nanoparticles that are encapsulated within nanotubes (e.g., carbon nanotubes), which are arranged in a substrate to facilitate the reading and writing of information by a read/write head. The substrate may be flexible or rigid. Information is stored on the magnetic nanoparticles via the read/write head of a storage device. These magnetic nanoparticles are arranged into data tracks to store information through encapsulation within the carbon nanotubes. As carbon nanotubes are bendable, the carbon nanotubes may be arranged on flexible or rigid substrates, such as a polymer tape or disk for flexible media, or a glass substrate for rigid disk. A polymer may assist holding the nanoparticle-filled carbon tubes to the substrate.
US09251821B1	Attenuation of a pitch mode for actuator assemblies having multiple degrees of freedom An apparatus, in one embodiment, includes: a pivot assembly pivotably supporting a head carriage assembly, a motor coupled to the head carriage assembly for rotatably positioning the head carriage assembly about an axis of skew which extends perpendicular to a plane defined by an intended direction of media movement across the head carriage assembly and a direction of fine motion of the head carriage assembly, the fine motion direction being oriented perpendicular to the intended direction of media movement, a linear assembly supporting the pivot assembly and the head carriage assembly, the linear assembly being configured to move along the fine motion direction, and a first flexure extending between the head carriage assembly and the linear assembly, the first flexure permitting the rotatable positioning of the head carriage assembly about the axis of skew, the first flexure resisting pitching movement of the head carriage assembly relative to the linear assembly.
US09251815B2	Magnetoresistive sensor with AFM-stabilized bottom shield An apparatus disclosed herein includes a sensor stack including a first layer and an AFM stabilized bottom shield in proximity to the first layer, wherein the AFM stabilized bottom shield is magnetically coupled to the first layer. The apparatus reduces shield-to-shield spacing. The pinned layer of the bottom shield and a pinned layer of the sensor stack are stabilized using the AFM layer in the bottom shield. In one implementation, the bottom shield is made of the SAF structure, with the top layer of the structure adjacent to a pinned layer in the sensor stack.
US09251805B2	Method for processing speech of particular speaker, electronic system for the same, and program for electronic system An object of the present invention is to process the speech of a particular speaker. The present invention provides a technique for collecting speech, analyzing the collected speech to extract the features of the speech, grouping the speech, or text corresponding to the speech, on the basis of the extracted features, presenting the result of the grouping to a user, and when one or more of the groups is selected by the user, enhancing, or reducing or cancelling the speech of a speaker associated with the selected group.
US09251800B2	Generation of a high band extension of a bandwidth extended audio signal An audio decoder configured to generate a high band extension of an audio signal from an envelope and an excitation. The audio decoder includes a control arrangement configured to jointly control envelope shape and excitation noisiness with a common control parameter (f).
US09251798B2	Adaptive audio signal coding Example embodiments described herein generally provide for adaptive audio signal coding of low-frequency and high-frequency audio signals. More specifically, audio signals are categorized into high-frequency audio signals and low-frequency audio signals. Then, based on a set coding and/or characteristics of the low-frequency audio signals, the low-frequency coding manner is selected. Similarly, but in addition to, a bandwidth extension mode to code the high-frequency audio signals is selected according to the low-frequency coding manner and/or characteristics of the audio signals.
US09251791B2	Multi-modal input on an electronic device A computer-implemented input-method editor process includes receiving a request from a user for an application-independent input method editor having written and spoken input capabilities, identifying that the user is about to provide spoken input to the application-independent input method editor, and receiving a spoken input from the user. The spoken input corresponds to input to an application and is converted to text that represents the spoken input. The text is provided as input to the application.
US09251789B2	Speech-recognition system, storage medium, and method of speech recognition A speech recognition system that recognizes speech data is provided. The speech recognition system includes a speech recognition part that performs speech recognition of the speech data, and calculates a likelihood of the speech data with respect to a registered word that is pre-registered, a reliability judgment part that performs reliability judgment on the speech recognition based on the likelihood, and a judgment reference change processing part that changes a judgment reference for the reliability judgment, according to an utterance speed of the speech data.
US09251787B1	Altering audio to improve automatic speech recognition Techniques for altering audio being output by a voice-controlled device, or another device, to enable more accurate automatic speech recognition (ASR) by the voice-controlled device. For instance, a voice-controlled device may output audio within an environment using a speaker of the device. While outputting the audio, a microphone of the device may capture sound within the environment and may generate an audio signal based on the captured sound. The device may then analyze the audio signal to identify speech of a user within the signal, with the speech indicating that the user is going to provide a subsequent command to the device. Thereafter, the device may alter the output of the audio (e.g., attenuate the audio, pause the audio, switch from stereo to mono, etc.) to facilitate speech recognition of the user's subsequent command.
US09251786B2	Method, medium and apparatus for providing mobile voice web service Provided are a method and apparatus for providing a mobile voice web service in a mobile terminal. The method includes analyzing a web history of a user from web search logs of the user and generating a voice access list based on the analysis results, and performing voice recognition by dynamically generating a voice recognition syntax according to the generated voice access list. Accordingly, by limiting syntax required for voice recognition by generating a syntax suitable for a web context of the user, efficient voice recognition, which can be performed in a terminal not a server, can be implemented.
US09251785B2	Call steering data tagging interface with automatic semantic clustering A system and method for providing an easy-to-use interface for verifying semantic tags in a steering application in order to generate a natural language grammar. The method includes obtaining user responses to open-ended steering questions, automatically grouping the user responses into groups based on their semantic meaning, and automatically assigning preliminary semantic tags to each of the groups. The user interface enables the user to validate the content of the groups to ensure that all responses within a group have the same semantic meaning and to add or edit semantic tags associated with the groups. The system and method may be applied to interactive voice response (IVR) systems, as well as customer service systems that can communicate with a user via a text or written interface.
US09251783B2	Speech syllable/vowel/phone boundary detection using auditory attention cues In syllable or vowel or phone boundary detection during speech, an auditory spectrum may be determined for an input window of sound and one or more multi-scale features may be extracted from the auditory spectrum. Each multi-scale feature can be extracted using a separate two-dimensional spectro-temporal receptive filter. One or more feature maps corresponding to the one or more multi-scale features can be generated and an auditory gist vector can be extracted from each of the one or more feature maps. A cumulative gist vector may be obtained through augmentation of each auditory gist vector extracted from the one or more feature maps. One or more syllable or vowel or phone boundaries in the input window of sound can be detected by mapping the cumulative gist vector to one or more syllable or vowel or phone boundary characteristics using a machine learning algorithm.
US09251780B2	Sound output device A sound output device for masking an operation sound generated by equipment, having: an operation determining unit that determines an operation mode to be executed by the equipment; and a sound output unit that outputs a masking sound on the basis of the operation mode determined by the operation determining unit, the masking sound changing at least in sound pressure level over time.
US09251776B2	System and method creating harmonizing tracks for an audio input A system and method of creating harmonizing tracks for an audio input. Audio input is received and a plurality of harmonizing tracks are created based on the received audio input. Each of the plurality of harmonizing tracks are transposed based on a transposition value for each respective track. Individual notes of the harmonizing tracks are manipulated based on a chord strictness threshold and an audio output is provided based on the audio input and the manipulated plurality of harmonizing tracks.
US09251775B2	Electronic signal processor An electronic signal processor for processing signals includes a complex first filter, one or more gain stages and a second filter. The first filter is characterized by a frequency response curve that includes multiple corner frequencies, with some corner frequencies being user selectable. The first filter also has at least two user-preset gain levels which may be alternately selected by a switch. Lower frequency signals are processed by the first filter with at least 12 db/octave slope, and preferably with 18 db/octave slope to minimize intermodulation distortion products by subsequent amplification in the gain stages. A second filter provides further filtering and amplitude control. The signal processor is particularly suited for processing audio frequency signals.
US09251773B2	System and method for determining an accent pattern for a musical performance Embodiments of the invention are related to a computer-implemented method that includes receiving musical data, identifying a succession of accentuated events in the musical data, determining a pattern in the succession of accentuated events, comparing the pattern to a plurality of reference patterns, and determining a match for the pattern using the plurality of reference patterns. The method further includes selecting one of the matching reference patterns, and generating a rhythmic musical accompaniment for the musical data based on the selected matching reference pattern. In some cases, the musical data is MIDI data or analog audio data. Analog audio data analysis includes detecting transients in the analog audio data by identifying the succession of accentuated event in the musical data. This may include identifying a plurality of events in the musical data, and determining whether each of the plurality of events is an accent.
US09251769B1	Mechanical mute for selectively muting a brass instrument A mute for a musical brass instrument comprises an external body and an adjustable muting device coupled to the external body. The adjustable muting device selectively mutes sound from the musical brass instrument. The adjustable muting device is a mechanical device, which is selectably activated and/or adjusted using mechanical and/or electronic controls, thus permitting a musician to mute/unmute the musical brass instrument without removing the mute.
US09251762B2	Runtime transformation of images to match a user interface theme An application that generates a user interface includes multiple assets, such as icons, that are overlaid onto other user interface elements, such as tool bars, menus, windows, etc. The assets may be configured at runtime to match a user interface theme that utilizes specific colors, fonts, and styles. The application, at runtime, configures an asset to match the user interface theme by adjusting the luminosity of the pixels in the asset. A subset of pixels in the asset is matched to the color of a target background color by altering the luminosity of the subset of pixels in the asset to match the luminosity of the target background color. The luminosity of the remaining pixels is adjusted to match the theme.
US09251761B2	Gray-scale correction method for display device, and method of producing display device A gray scale correction method for a display device includes a step of setting a target value including a target luminance and a target chromaticity of a color display pixel (S22), a step of measuring tristimulus values of each of a plurality of reference colors and each of a plurality of comparative colors in accordance with a prescribed gamma characteristic (S24), a step of finding a reference value and a comparative value from the measured tristimulus values (S26), and a step of correcting a gray scale based on the target value, the reference value and the comparative value (S28).
US09251759B2	Reduction of contention between driver circuitry An electronic display includes a display panel. The display panel includes a pixel array and receives a supply voltage. The display panel also includes a panel driver configured to generate a gate line voltage. The panel driver also supplies the gate line voltage to the display panel based on a comparison between the gate line voltage and the supply voltage.
US09251746B2	Liquid crystal display apparatus The liquid crystal display apparatus according to an embodiment of the present invention has a plurality of pixels including a red pixel, a green pixel and a blue pixel. In at least one example embodiment, each of the plurality of pixels has a plurality of subpixels including a first subpixel and a second subpixel. When the grayscale levels of input signals corresponding to the red, green and blue pixels are equal to one another at a given level, the ratio of the difference in luminance between the first and second subpixels of one of the red, green and blue pixels to the maximum luminance of that one of the red, green and blue pixels is greater than the ratio of the difference in luminance between the first and second subpixels of each one of the other two pixels to the maximum luminance of the respective one of the other two pixels.
US09251745B2	System and apparatus for see-through display panels Various embodiments of the present invention provide for systems and apparatus directed toward using a contact lens and deflection optics to process display information and non-display information. In one embodiment of the invention, a display panel assembly is provided, comprising: a transparent substrate that permits light to pass through substantially undistorted; a reflector disposed on the transparent substrate; and a display panel aimed toward the reflector and substantially away from a human visual system, wherein the reflector reflects light emitted from the display panel toward the human visual system. The reflector may comprise a narrow band reflector or a polarization reflector.
US09251742B2	Electrophoretic display apparatus and image-updating method thereof An electrophoretic display apparatus and an image-updating method thereof are provided. The electrophoretic display apparatus comprises a display panel and a source driver. The display panel comprises a plurality of pixels and a plurality of source lines, and each pixel electrode is electrically coupled to an AC common voltage through a corresponding capacitor. The capacitor comprises a plurality of charged particles. The source driver comprises a first data-latching circuit and a second data-latching circuit. Each of the data-latching circuits comprises a transistor, a capacitor and an inverter. The first data-latching circuit receives image data and a data shift-register output pulse. The second data-latching circuit is electrically coupled between an output terminal of the first data-latching circuit and a source line and is used for receiving a data output pulse.
US09251739B2	Stereoscopic display device and method for driving a stereoscopic display that updates a plurality of display zones A first display zone and a second display zone are displayed based on a first light source group, which corresponds to a first voltage data signal; and then the second display zone and a third display zone are displayed based on light for a second light source group, which corresponding to a second voltage data signal. The first light source group and the second light source group illuminate the display zones alternatively. Each display zone is fed with either a first data voltage signal or a second data voltage signal. While the first data voltage signal is updating each display zone in sequence, the second data voltage signal starts updating the first display zone when the first voltage signal is updating the third display zone.
US09251737B2	Pixel circuit, display panel and display apparatus A pixel circuit, display panel and display apparatus are provided. The pixel circuit comprises a driving sub-circuit, whose first terminal is connected with first reference voltage source via power supply lead, and second terminal is connected with first terminal of a light emitting device; a charging sub-circuit, whose output terminal is connected with third terminal of the driving sub-circuit, which is configured to charge the driving sub-circuit before the driving sub-circuit drives the light emitting device to emit light; and a compensation sub-circuit, whose first terminal is connected with second terminal of the light emitting device, second terminal is connected with second reference voltage source, which is configured to compensate for voltage drop on the power supply lead of voltage which is provided to the driving sub-circuit from the first reference voltage source, so as to raise the uniformity of display brightness within display area of the panel.
US09251734B2	Pixel circuit, electro-optical device, and electronic apparatus An electro-optical device formed on a semiconductor substrate, includes: a first transistor controlling a current level according to a voltage between a gate and a source; a second transistor electrically connected between a data line and the gate of the first transistor; a third transistor electrically connected between the gate and a drain of the first transistor; and a light-emitting element emitting light at a luminance according to the current level, in which one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are formed by a common diffusion layer.
US09251728B2	Method of driving a 3D display panel with enhanced left-eye image and right-eye image luminance difference and display apparatus for performing the method In a method of driving a display panel, a first data voltage having a first potential difference with respect to a reference voltage is outputted to pixel units of the display panel during a first frame which the data voltage has a same polarity with respect to the reference voltage as a data voltage of a following frame, and a second data voltage having a second potential difference less than the first potential difference is output to pixel units of the display panel during a second frame in which the data voltage has a polarity with respect to the reference voltage that is reversed with respect to a data voltage of a following frame.
US09251724B2	Beverage identification tiles A beverage identification tile is provided that includes a sheet of material and a plurality of beverage type identifiers. The sheet of material has a first face and a second face which have a polygonal shape defined by a plurality of edges. A different beverage type identifier of the plurality of beverage type identifiers is printed along each edge of the plurality of edges of the first face and of the second face. A shelf labeling system includes a shelf, a plurality of slots, and the beverage identification tile. The shelf includes a front wall, a back wall, and a base mounted between the front wall and the back wall. The sheet of material is sized to slide into a slot of the plurality of slots formed in the front wall along an edge of the front wall with a beverage type identifier visible above the edge.
US09251722B2	Map information display device, map information display method and program There is provided a map information display device including an operating tool detector for, on a display panel where map information MI and view image information VI are displayed, detecting a position and a pointing direction of an operating tool M in touch with an area corresponding to the map information; and a display controller for controlling display of the view image information in accordance with a view point on the map information indicated by the position of the operating tool and a line-of-sight direction on the map information indicated by the pointing direction of the operating tool.
US09251716B2	Corporate training system and method The disclosed embodiments include a system and method for improving corporate employee work performance. The disclosed embodiments provide an innovative approach to optimizing the talent and resources within an organization including, but not limited to, an individual employee, teams of employees, and to executives within the organization. Through the application of a multivariate model based on physiological, affective, and behavioral systems, the disclosed embodiments attempt to improve an employee's vitality, vibrancy, wellness, and overall work performance.
US09251709B2	Lateral vehicle contact warning system A vehicle contact warning system includes a detector system, a controller and a warning indicator. The detector system detects a distance between a remote vehicle and a host vehicle and whether a signal indicator on the remote vehicle is activated. The controller determines whether at least one of a signal indicator on the host vehicle is activated by a driver of the host vehicle and a speed at which the distance between the host vehicle and the remote vehicle is decreasing is greater than a predetermined speed. The warning indicator notifies the driver of the host vehicle upon the detector system detecting the signal indicator on the remote vehicle and the controller determining that at least one of the signal indicator of the host vehicle is activated and the speed at which the distance between the host vehicle and the remote vehicle is decreasing is greater than the predetermined speed.
US09251703B1	Methods of providing traffic information and supporting apparatus, readable medium, and memory A technique of providing traffic information to a navigation system that obtains (704) current traffic data having a current traffic condition associated with a location description on a road network. Historic traffic data associated with the location description are then obtained (708) from a historic traffic database to be compared (710) with the current traffic data. From the comparison, a traffic delta between the current traffic data and the historic traffic data is then provided (710), which is used to determine (714) whether this traffic delta corresponds in a predetermined way with a threshold. And if so, a traffic message is generated (716) with the current traffic condition associated with the location description.
US09251695B2	System and methods for providing notification in the event of a security crisis The present invention provides a system and methods for notifying first responders of a security crisis or threat. The alarm system can be scaled to allow the alarm system to be used effectively in facilities of differing sizes and layouts. The system is also flexible, enabling the system to integrate with currently existing systems or to operate with new devices.
US09251694B2	Vehicle system passive notification using remote device A method of vehicle monitoring includes monitoring one or more vehicle safety systems while a vehicle is in operation to detect an unsafe condition. The method also includes sending an alert to a handheld device if an unsafe condition is detected.
US09251691B2	Systems and methods for behavior monitoring and identification Various embodiments herein provide system, method, and software solutions to facilitate not only timely, compliant monitoring of individuals housed within facilities, such as detention facilities, but also solutions that discover visible and latent behavior and mental conditions, among other potential issues that may be easily overlooked. Some embodiments focus on data collection and other embodiments focus on applying analytics to collected data to discover conditions and states of individuals, groups, a facility or portion thereof, staff, and procedures. Yet further embodiments include both data collection and analytic discovery. Some embodiments may also include messaging and other data processing and communication mechanisms implemented to facilitate compliance, safety, and monitoring accuracy.
US09251681B2	Fire alarm system Provided is a fire alarm system including: a transmitter/receiver unit (4) for supplying a pulse voltage to power/signal lines (SG); a current value setting unit (5) for setting, as a current limiting value, an upper limit of a current output to the power/signal lines (SG) from the transmitter/receiver unit (4) when the pulse voltage is output; and a current control unit (6) for controlling the transmitter/receiver unit (4) to output a current having a value equal to or smaller than the current limiting value set by the current value setting unit (5). Accordingly, it is possible to prevent a malfunction from occurring in communications irrespective of a scale of the fire alarm system.
US09251676B2	Haptic self-service terminal (SST) feedback Haptic Self-Service Terminal (SST) feedback is provided. A customer transacting at a SST during a Self-Service (SS) transaction receives in-air tactile communication for assisting the customer during the SS transaction.
US09251672B2	Stacking purge-bin Apparatus and methods for a stacking purge-bin (“SPB”) are provided. The SPB may be configured to rotate. The SPB may include a plurality of receiving sections. One or more tangible items retracted by the SSK may be stored in each receiving section. Rotating the SPB between each retraction may prevent tangible items from two consecutive retractions from being stored in a single receiving section. Preventing tangible items from two consecutive retractions from being stored in a single receiving section may allow each tangible item to be associated with transaction information corresponding to a retraction. The SPB may store separators. A separator may be inserted between tangible items received from two consecutive retractions. Separating between tangible items received from two consecutive retractions may allow each tangible item to be associated with transaction information corresponding to a retraction. Transaction information associated with a retraction may be marked on the separator.
US09251669B2	Slot machine including a plurality of video reel strips On the slot machine, a slot game including a base game and free games is caused to proceed on a display. On the base game reel strips, on all of a plurality of reels, symbols whose each kind is the same, other than feature symbols and wild symbols, are arranged in succession. On the free game reel strips, on all of a plurality of reels, symbols whose each kind is the same, other than the feature symbols and the wild symbols, are arranged in succession and in addition thereto, only in a case of top symbols whose payout multiplying factor is the highest, the top symbols whose number is larger than a number of top symbols displayed on the base game reel strips are arranged in succession.
US09251664B2	Casino slot wagering system A method and apparatus for casino slot games in which at least two and preferably three games are linked together by displaying the two or three games on one video display device. The games are linked through the initial cards displayed for each game, and their bets and their outcomes. A computer calculates the probabilities of all bets and outcomes during the betting rounds in real time. As a result of the so chained games the player makes decisions in multiple betting rounds in insufficient information about the game outcomes. At any time during the game play the player can evaluate the game outcomes as presented to him by the computer and either play the next successive game or simply finish the game with no penalty.
US09251660B2	Gaming activity awarding subsequent plays using results of previous plays Techniques involving awarding subsequent plays using results of previous plays. One representative technique includes dealing a first poker hand to a player, and enabling cards of the first poker hand to be held. Replacement cards are presented for any of the cards that were not held in the first poker hand, thereby creating a first resulting poker hand. All of the cards of the first resulting poker hand are duplicated into a second poker hand, where cards in the second poker hand may again be held/discarded. Replacement cards are presented for any of the cards that were not held in the second poker hand, thereby creating a second resulting poker hand. Duplication into additional hands may also be provided.
US09251657B2	Skill calibrated hybrid game Systems in accordance with embodiments of the invention include: a gambling game; an entertainment game; and a game world engine constructed to communicate, to the real world engine, gameplay gambling event occurrences based upon a player's skillful execution of the entertainment game that triggers a wager in the gambling game, the game world engine utilizing a skill calibration module constructed to receive, from the entertainment software engine, player performance information for the player, analyze the player performance information to determine the player's skill level in playing the entertainment game, determine whether the terms of the wager of the gambling game are calibrated in a manner appropriate to the player's skill level in the entertainment game, and send, to the real world engine, a command that causes the real world engine to calibrate the terms of the wager in the gambling game.
US09251654B2	Wagering method, device, and computer readable storage medium, for wagering on pieces in a progression A method, apparatus, and computer readable storage, for wagering on a game of chance which includes (a) offering, before a game of chance progression commences, an initial wager on any of a plurality of pieces to first complete the progression, an initial payout for the initial wager based on the pieces having equal chances of winning; and (b) offering, during the progression, a real time wager on any of a plurality of pieces to first complete the progression, a real time payout for the real time wager based on computed chances of a selected piece first completing the progression based on current positions of the plurality of pieces.
US09251649B2	System and method for connecting gaming devices to a network for remote play A gaming system authenticates over a network a user of a remote device for a gaming system for a gambling game. The gaming system determines a location of the remote device. The gaming system verifies that the location of the remote device is within a jurisdiction that allows use of the gaming system by persons of age to gamble. Then the gaming system provides software to the remote device, wherein the software, when executed, causes media associated with the gambling game to be presented on the remote device.
US09251645B2	Integrating chat and wagering games A wagering game system and its operations are described herein. In some embodiments, the operations can include connecting a wagering game to a chat session and receiving a textual game command for the wagering game from a chat message sent via the chat session. The operations can further include activating a wagering game function for the wagering game in response to receiving the textual game command via the chat message.
US09251644B2	Amusement devices and games including means for processing electronic data where users can change selections Games related to the provision of information are described. Games may be formulated to exploit biases such as long shot bias and favorite bias. Games related to the provision of information are described. Games may be formulated to exploit biases relating to the Monty Hall paradox. Games related to the provision of information are described. Games may include wagering on hands of cards, e.g., poker wagering games.
US09251643B2	Multimedia interface progression bar A method comprising displaying a display area adapted to display a multimedia element, displaying a progression bar adapted to represent at least a portion of a duration of the multimedia element, and providing an indicator associated with the progression bar, the indicator being displayable at a timely position along the at least a portion of a duration of the multimedia element and is further adapted to timely enable an action when the multimedia element is played, the display bar includes a movable play position indicator and wherein the action is enabled on a basis of a proximity between the indicator and the play position indicator, the action encompassing timely displaying an image.
US09251636B2	Document validating/stacking device A document validating/stacking device is provided that has a validator 1 provided with a swingable rocker 10 formed with a head 16 and a stacker 2 detachably attached to validator 1. Stacker 2 comprises an X-linkage 20 having a driver arm 41 that is separably pushed by head 16 in the same rotational direction as head 16 swings to expand X-linkage 20, to thereby move pusher plate 18 from the initial position to the extended position and to stow the document within interim chamber 24 into storage 7.
US09251620B2	Fast pattern interpolation with parallel coherent random walk searching There is provided a method and system for fast pattern interpolation with parallel coherent random walk searching. The system includes a system processor and a system memory, and an image processing application stored in the system memory. The image processing application, under control of the system processor, is configured to receive first and second pattern exemplars and a blend map for merging the first and second pattern exemplars, and to utilize a correspondence search process to determine first and second target images for use in producing a composite image. The first and second target images correspond respectively to the first and second pattern exemplars. In addition, a constraint imposed on the correspondence search process by the image processing application is based on the blend map for merging the first and second pattern exemplars.
US09251615B2	Thermal image animation Animation of a thermal image captured by a thermal imager that includes automatically changing particular aspects of the presentation of the image. The coloring of the thermal image may automatically change through two or more color presentations. The colors which may automatically change or be “animated” may be any colors in the usual rainbow of color or in the grayscale. The animation may include a series of small, stepwise incremental changes that gradually change the image. If timed correctly and if the increments are sufficiently small, the transitions of the image may appear smooth, in the manner of a movie or cartoon.
US09251613B2	Systems and methods for automatically applying effects based on media content characteristics Disclosed are systems and methods for automatically applying special effects based on media content characteristics. A digital image is obtained and depth information in the digital image is determined. A foreground region and a background region in the digital image are identified based on the depth information. First and second effects are selected from a grouping of effects, where the first effect is applied to at least a portion of the foreground region and the second effect is applied to at least a portion of the background region.
US09251608B2	Data visualization of a datacenter Methods and systems for data visualization in a datacenter are described herein. At least some illustrative embodiments comprise a method for monitoring a datacenter, comprising collecting a plurality of real-time data samples from a plurality of data sensors, generating a plurality of processed data values based at least in part on the plurality of real-time data samples, mapping each of the plurality of processed data values to one of a plurality of colors, and displaying the plurality of processed data values as regions of color on one or more two-dimensional (2-D) planes within a three-dimensional (3-D) space representing a datacenter.
US09251599B2	Tracking assistance device, a tracking assistance system and a tracking assistance method that enable a monitoring person to perform a task of correcting tracking information A tracking assistance device includes: a target-to-be-tracked setting unit that causes captured images stored in a recorder to be displayed on a monitor and, in response to an input operation performed by a monitoring person to designate a moving object to be tracked, sets the designated moving object as a target to be tracked; a candidates selection unit that selects, as a candidate(s), a moving object(s) highly relevant with the moving object set as the target to be tracked; a candidate image presenting unit that extracts, as a candidate image(s), a captured image(s) in which the candidate moving object(s) is(are) included, and causes the monitor to display the candidate image(s) is(are) such that the monitoring person selects an appropriate candidate image; and a tracing information correction unit that changes the target to be tracked to the moving object associated with the selected candidate image and corrects the tracing information accordingly.
US09251595B2	Method of shutterless non-uniformity correction for infrared imagers A method of correcting an infrared image is provided. The method includes receiving an image from a camera comprising a first pixel with a first pixel value and a neighbor pixel with a neighbor pixel value. The first pixel and the neighbor pixel can be assumed to view the same object. The method further includes storing the first and neighbor pixel values in an image table, generating a corrected image table by adding the first pixel value to a corrected pixel value in a correction table, determining that the camera is not moving, and masking edges in the corrected image table. The method further includes updating the correction table by: determining that the first pixel value and neighbor pixel value are not edges, computing the difference between the first and neighbor pixel values, and storing the difference in the correction table. The method further includes providing an output image table.
US09251594B2	Cropping boundary simplicity Cropping boundary simplicity techniques are described. In one or more implementations, multiple candidate croppings of a scene are generated. For each of the candidate croppings, a score is calculated that is indicative of a boundary simplicity for the candidate cropping. To calculate the boundary simplicity, complexity of the scene along a boundary of a respective candidate cropping is measured. The complexity is measured, for instance, using an average gradient, an image edge map, or entropy along the boundary. Values indicative of the complexity may be derived from the measuring. The candidate croppings may then be ranked according to those values. Based on the scores calculated to indicate the boundary simplicity, one or more of the candidate croppings may be chosen e.g., to present the chosen croppings to a user for selection.
US09251593B2	Medical imaging system and a method for segmenting an object of interest The invention concerns a medical imaging system comprising means (4) of segmenting a region of interest around an object of interest within a volume of 3D data (3DV). The system according to the invention comprises means (5) of calculating a sub-regions map (CSR) within the segmented region (RS) and correction means (6) intended to exclude sub-regions of the segmented region by means of said sub-regions map (CSR). The correction can be made automatically or manually by means of control means (7) enabling a user to select the sub-regions to be excluded. Display means (3) make it possible to display a 2D representation (2DR) of the volume of 3D data (3DV) and the segmented region (RS, RS′) at various stages of the processing.
US09251592B2	Pixel object detection in digital images method and system A user touches a touch sensitive display or otherwise provides input comprising “stroke” gestures to trace areas which are to be the subject of post-processing functions. The stroke area is highlighted and can be added to or corrected by additional stroke and “erase” gestures. Pixel objects are detected proximate to the stroke area, with a precision based on the zoom level. Stroke gesture input may be received and pixel object determination may be performed in series or in parallel.
US09251584B2	Simultaneous high spatial low temporal resolution magnetic resonance (MR) sequence for dynamic contrast enhanced (DCE) magnetic resonance imaging (MRI) A dual magnetic resonance imaging method simultaneously acquires a first and a second time series of MR images wherein the temporal resolution of the first time series of images is larger than that of the second time series while the spatial resolution of the first time series of images is smaller than that of the second time series. Accordingly, in the context of DCE-MRI, the first time series can be used to determine the arterial input function (AIF) while the second time series can be used to determine the concentration time course in the tissue of interest, e.g. in a vessel wall. Therefore, both the AIF and the tissue time course can be acquired with their optimal dynamic signal range.
US09251583B2	Analysis, secure access to, and transmission of array images Systems and methods are provided the autocentering, autofocusing, acquiring, decoding, aligning, analyzing and exchanging among various parties, images, where the images are of arrays of signals associated with ligand-receptor interactions, and more particularly, ligand-receptor interactions where a multitude of receptors are associated with microparticles or microbeads. The beads are encoded to indicate the identity of the receptor attached, and therefore, an assay image and a decoding image are aligned to effect the decoding. The images or data extracted from such images can be exchanged between de-centralized assay locations and a centralized location where the data are analyzed to indicate assay results. Access to data can be restricted to authorized parties in possession of certain coding information, so as to preserve confidentiality.
US09251576B2	Digital image subtraction A system for generating a digital subtraction image of at least two input images. The system comprises a registration subsystem (1) for generating a plurality of different registrations of the input images (7, 8), based on different values of a registration parameter (6). The system further comprises a subtraction subsystem (2) for generating a plurality of subtracted images by subtracting the input images in accordance with respective ones of the plurality of registrations. The system further comprises a combining subsystem (3) for combining the plurality of subtracted images into a combined subtracted image (9). The registration parameter (6) represents an assumed depth of an object which is visible in the input images (7, 8). The combining subsystem (3) is arranged for assigning a combined pixel value to a pixel position of the combined subtracted image, based on pixel values of or around corresponding pixel positions in the plurality of subtracted images.
US09251575B2	Image processing apparatus, image pickup apparatus, image processing method, and image processing program An image processing apparatus 1 includes an image region dividing portion 105 configured to divide a shot image into a plurality of image regions so that an amount of change of an image quality is within a predetermined range when the shot image is blurred using a blur kernel depending on an object distance and an angle of view of the shot image, a blur kernel generating portion 106 configured to calculate the blur kernel for each image region divided by the image region dividing portion 105, and an image processing calculating portion 107 configured to generate a blur-added image by performing a convolution calculation for the shot image using the blur kernel calculated by the blur kernel generating portion 106.
US09251574B2	Image compensation value computation Image compensation value computation techniques are described. In one or more implementations, an image key value is calculated, by a computing device, for image data based on values of pixels of the image data. A tuning value is computed by the computing device using the image key value. The tuning value is configured to adjust how the image data is to be measured to compute an image compensation value. The image compensation value is then computed by the computing device such that a statistic computed in accordance with the tuning value approaches a target value. The image compensation value is applied by the computing device to adjust the image data.
US09251570B1	Smart image enhancements Smart image enhancements are disclosed, including: obtaining a representation of a user's face associated with a set of images associated with the user's face; obtaining a set of extrinsic information corresponding to an image of the set of images; determining a modified smoothing map by modifying a model smoothing map to correspond to the representation of the user's face; and determining an enhanced image based at least in part on the set of extrinsic information corresponding to the image, the modified model smoothing map, and the image.
US09251565B2	Hyper-resolution imaging Methods and a computer program product for deriving a super-resolution image of a physical object by fusing cameras of multiple resolutions (spatial, temporal, or spectral), the super-resolution image characterized by a resolution exceeding a “camera imaging resolution” associated with each of a sequence of lower-resolution images of the physical object. The sequence of images of the physical object is obtained at a plurality of relative displacements with respect to the object by a hybrid camera system comprising at least two imaging systems. The imaging systems are characterized by respective temporal and spatial resolution and by spectral sensitivity, and may be distinct from one another in one or more of the foregoing dimensions. The imaging systems are either fixed, or subject to know motion, relative to each other. Image sequences derived by each imaging system are coregistered and deconvolved to solve for a resultant sequence of images.
US09251562B1	Registration of low contrast images The registration of images captured at multiple locations, for purposes such as location mapping, can be improved by utilizing multiple image capture elements pointing in at least two different directions or having different viewable ranges. At least one primary image is captured at each location. If the primary image is not able to be correlated with at least one other image based on one or more matching features, image information captured by at least one other camera at substantially the same times as those images can be analyzed to attempt to determine a change in position and/or orientation of the device between those times, which can assist in correlating the primary images. In some embodiments, motion or orientation determining elements can assist in the determination of device movement, and in at least some embodiments can reduce the amount of image information to be processed for a match.
US09251557B2	System, method, and computer program product for recovering from a memory underflow condition associated with generating video signals A system, method, and computer program product for recovering from a memory underflow condition associated with generating video signals are disclosed. The method includes the steps of determining that a first counter is greater than a second counter, incrementing an address corresponding to a memory fetch request by an offset, and issuing the memory fetch request to a memory. The first counter represents a number of pixels that have been read by a display pipeline for a current frame and the second counter represents a number of pixels requested from a memory for the current frame.
US09251548B1	Object transformation for object trees utilized with multiprocessor systems A system may include a memory that stores instructions and a processor to execute the instructions to store a first set of objects in a first data structure, where the first set of objects describe a graphical scene. The processor may create a group of commands and add a command for at least one object, of the first set of objects, to the group of commands. The processor may combine the group of commands into a composite command, where the group of commands includes the added command. The processor may create a second set of objects in a second data structure based on the first set of objects in the first data structure and the composite command. The processor may also modify the second set of objects and provide the modified second set of objects to a browser for rendering the graphical scene.
US09251547B2	Method and system for placing a wager on a pari-mutuel event A method and system is provided to permit placing a wager on a pari-mutuel event in which expert handicapper's prognoses are displayed to a player to permit them to formulate either simple or complicated exotic wagers, and to be able to aggregate a wager with those of other players to satisfy wagering minimums.
US09251543B2	Predictive method, apparatus and program product Methods, Apparatus and Program Products for predicting resource usage data, weather data and econometric data, such as: demands on resources such as electrical power, water supply, communications infrastructure; temperature, humidity, wind speed, solar radiation, and degree days; and commodity price, gross domestic product, and a price index.
US09251540B1	Banking system controlled responsive to data bearing records An apparatus that operates to cause financial transfers responsive to data read from data bearing records, includes at least one processor that is in operative connection with a card reader, a check acceptor, a cash dispenser and a display. The at least one processor causes the machine to operate to read card data from a user card, and to cause a determination to be made that the read card data corresponds to an authorized financial account. The at least one processor is operative to cause data to be read from a check and/or cash to be dispensed, and a financial transfer to or from the account corresponding to the value thereof. Machine instructions are output and user transaction inputs can be received through either a primary or an auxiliary touch screen display.
US09251538B1	System and method for automatically filling webpage fields A computer-implemented method for automatically populating fields of a webpage. The method includes transmitting data from a browser add-on installed in a second webpage to a code segment inserted in a first webpage, where the code segment is configured to populate one or more fields included in the first webpage with received data, where the browser add-on is not installed in the first webpage, and where the first webpage is displayed on a display device in a web browser application executing on a computer system; and executing the code segment to populate the fields included in the first webpage with the received data.
US09251534B2	Offer inclusion for over the top (OTT) content Inspection of over the top (OTT) content to facilitate offering non-OTT content or other content and/or services as an alternative to the OTT content is contemplated. The OTT content may be inspected at an access point configured to provide a broadband or other connection between a device consuming the OTT content and a device sourcing the content. Data packets or other signaling may be added to the OTT content at the access point in order to announce the offer.
US09251532B2	Method and apparatus for providing search capability and targeted advertising for audio, image, and video content over the internet The present invention provides an apparatus and method for extracting the content of a video, image, and/or audio file or podcast, analyzing the content, and then providing a targeted advertisement, search capability and/or other functionality based on the content of the file or podcast.
US09251530B1	Apparatus and method for model-based social analytics A model based social analytic system collects social signals from social network accounts for different companies and constituents. The social signals can be used to benchmark social network performance for different contextual dimensions, such as industries, companies, brands, etc. Conversations may be identified in the signals and the types of constituents participating in the conversations may be identified. Analytics can then be determined for the contextual dimensions based on the related conversations and the types of constituents participating in the conversations.
US09251529B2	Advertisement providing system and method Provided are an advertisement providing system and method. The advertisement providing method acquires information on a user interaction, acquires a second advertisement schedule which is generated by rescheduling a first advertisement schedule on the basis of the information on the user interaction, and provides an advertisement according to the second advertisement schedule.
US09251527B2	System and method for providing personalized recommendations A system and method for providing a personalized recommendation from a series of partial preferences is presented. A preference distribution of a population including a plurality of weighted ranked lists is identified. A revealed preference of a user is compared to the plurality of ranked lists. An affinity weight between the user and each of the plurality of ranked lists is assigned, and a weighted average of each of the affinity weights is taken.
US09251526B2	Server apparatus, terminal apparatus, user's degree of interest calculation method, user's degree of interest calculation program, terminal program, recording medium having program recorded therein, and an information providing system A server apparatus according to the invention obtains, from a terminal apparatus, scroll operation information conducted on a display area of the terminal apparatus, and obtains content identification information for identifying the content displayed at the display area, and calculates the user's degree of interest in the content identified by the obtained content identification information.
US09251522B2	Pixel cluster transit monitoring for detecting click fraud Detecting click fraud that includes a client device capable of accessing a server hosting a web page containing an advertisement. The client device includes a network interface allowing access to the server and code on the client device. The code accesses and displays a web page containing an advertisement, provides mechanisms (e.g., an applet, an ActiveX control, a plugin, a JavaScript, a browser scripting language, browser extensions, or code native to the browser) associated with each pixel cluster where each mechanism captures information regarding the transit of the pixel cluster by a cursor on the web page, and collects information based on the capturing by each associated mechanism regarding the transit of the pixel cluster by a cursor on the web page.
US09251519B1	Systems and methods for monetizing subscription and archival news content A news aggregation server aggregates and monetizes restricted news content. The news aggregation server fetches the restricted news content from multiple news source servers that are remote from the news aggregation server. The news aggregation server aggregates the fetched restricted news content and searches the aggregated news content based on input received from a client. The news aggregation server provides access to selected news content from the aggregated news content that is relevant to the client input and charges the user a price for accessing the selected restricted news content.
US09251513B2	Stand-alone secure PIN entry device for enabling EMV card transactions with separate card reader A method of conducting secure electronic payments to a payment acquirer using a credit card payment unit, comprising of a smart card, a portable card reader device, a mobile phone, a stand-alone PIN entry device and a payment server. The method is based on eliminating the unsecure keyboard in a mobile phone used for entering personal identification information, and instead use a separate secure PIN entry device which fulfills the EMV Level specification. Since all sensitive payment information, communicated to the payment server from the card reader and the PIN entry device, is encrypted using unique encryption keys an unsecure mobile phone may be used for relaying the communication between the card reader device and the PIN entry device to and from the payment server.
US09251512B2	Method and apparatus for identification verification and purchase validation A computer implemented method includes receiving a request for payment-related information at a wireless device. The method also includes communicating between the wireless device and a paired vehicle computing system (VCS) to verify the presence of a known vehicle. Further, the method includes transmitting requested payment-related information, responsive to the verification of the presence of the known vehicle.
US09251511B2	Transfer account systems, computer program products, and associated computer-implemented methods Embodiments of the present invention include transfer account systems, computer program products, and associated computer-implemented methods of providing prioritized payments from the proceeds of automatic or direct deposits. Embodiments of the present invention include routing automatic deposit information to a financial institution computer managing a prioritized payment program and formulating an outgoing ACH file with both an entry for an automatic deposit destined for a customer account and an entry for a pre-authorized prioritized payment to a select creditor, so that the automatic deposit is credited to the customer account and relatively instantaneously any prioritized payment is debited from the customer account. According to embodiments of the present invention, the customer account can be a checking, deposit, savings, money market, or other account as understood by those skilled in the art, so that a customer has effective access through the customer account only to a net value of funds.
US09251506B2	User interfaces for content categorization and retrieval Methods, systems, and computer-readable media provide a scenario desktop for recording a current event scenario and a content desktop for presenting information about a previously recorded event scenario. When a first event scenario is detected on the mobile device, the scenario desktop is presented on the mobile device. The scenario desktop exists in parallel with a default primary desktop of the mobile device. An information bundle is created for the first event scenario, including one or more documents accessed through the scenario desktop during the first event scenario. Access to the one or more documents is automatically provided on the mobile device during a second event scenario related to the first event scenario. The access is provided through the content desktop existing in parallel with the primary desktop and the scenario desktop.
US09251503B2	Video viewing and tagging system Systems and methods are provided to view, manipulate, and share videos within a gaming platform implemented as an advisory services network. Within the context of a serious game designed around a complex business problem of an organization, players can review videos conveying ethnographic information, mark segments of the videos, tag the videos or segments for categorization, create discussions around the videos or segments, add the videos or segments as evidence to a dossier, embed the videos or segments into existing discussions, or the like.
US09251501B2	Cross-platform reporting user interface A user device presents, to a user, media content provided from multiple providers and logs the presented media content from the multiple providers. The user device indicates, based on the multiple providers, proportions of the presented media content from the multiple providers during a particular reporting period and determines whether particular presented media content, of the presented media content from the particular reporting period, was available for presentation from another of the multiple providers. The user device generates a report, for the user, that indicates if the presented media content could have been consolidated among fewer of the multiple providers.
US09251495B1	Method and system for reconciling transportation records Aspects of the present invention are directed to a system for next day reconciliation of transportation records. The system having a transportation record storage provider (TRSP) that receives and stores storage medium transportation requests; an outside service provider (OSP) inventory manager that receives and maintains records of transported storage mediums scanned at the OSP; and a reconciliation provider that receives a first list from the TRSP and a second list from the OSP inventory manger, for reconciliation. The reconciliation provider includes receivers for receiving the first and second list; a processing engine that reconciles the first list and the second list; and a reporting unit that reports the results of the reconciliation. The processing engine matches inbound and outbound records of the first list and second list, and processes invalid records; and analyzes and accounts for un-matched records.
US09251493B2	Medication verification and dispensing Medication errors happen frequently in hospital, home, and pharmacy environments. A medication verification and dispensing system provides protection against such errors. The apparatus includes a guide tube that receives a medication and imaging device(s) adjacent to the guide tube that take image(s) of the medication. The imaging devices(s) and light source(s) are oriented for capturing images that reveal markings, color, size, shape, etc., of the medication. A verification system uses a signature of the image to identify the medication or compares the image(s) to reference images to identify the medication and to a prescription record of the patient to ensure it is a correct medication, dose, amount, timing, etc., for administration. If the medication is correct, it is dispensed into a dispensing vessel that locks the medication inside, but unlocks when it recognizes a unique patient identifier worn by a patient that is a correct recipient for the medication.
US09251488B2	Apparatus and method of determining a likelihood of task completion from information relating to the reading of RFID tags Methods and apparatuses are provided using RFID devices to assist in determining a likelihood that the performance of a task has been completed. In one implementation, an apparatus comprises a radio frequency identification (RFID) reader and a control circuit operably coupled to the RFID reader. The control circuit is configured to: detect, using at least information received via the RFID reader regarding a reading of one or more RFID tags by the RFID reader, one or more circumstances that evidence a status of interest pertaining to performance of a task of interest; and make a determination that the performance of the task of interest has likely been completed.
US09251484B2	Predicting likelihood of on-time product delivery, diagnosing issues that threaten delivery, and exploration of likely outcome of different solutions A task effort estimator may determine a probability distribution of an estimated effort needed to complete unfinished tasks in a project based on one or more of a set of completed tasks belonging to a project and attributes associated with the completed tasks belonging to the project, a set of completed tasks not belonging to the project and attributes associated with the completed tasks not belonging to the project, or the combination of both. A project completion predictor may determine a probability distribution of completion time for the project based on the probability distribution of an estimated effort needed to complete the unfinished tasks in the project, and one or more resource and scheduling constraints associated with the project.
US09251483B2	Performance optimization of business processes by stochastic environmental changes Methods and apparatus, including computer program products, are provided for optimizing applications, such as applications included in a business process. In one aspect, there is provided a computer-implemented method. The method may include receiving information representative of one or more interfaces and aspects of each of the interfaces. The interfaces may be adjustable by a business process supervisor. The business process supervisor may adjust one or more aspects of the one or more interfaces. The results of the adjustment may be received and used to determine optimum settings to the one or more interfaces. Related apparatus, systems, methods, and articles are also described.
US09251482B2	Chronically-problematic response alert system for service request and fulfillment between a service requester and a service performer An electronic alert system and a related method of operation for identifying, determining, and reporting chronically-problematic responses for service request and fulfillment between a service requester and a service performer are disclosed. In one embodiment, the electronic alert system identifies and determines a chronically-problematic response by analyzing two relational data sets. A first set of relational data set correlates time elapsed between a first service request bell press by a service requester from a service request device, and a confirmatory signal of successful service fulfillment from a service request reception device held by the service performer, or from the service request device. Furthermore, a second set of relational data set correlates a number of repeated service request bell presses by the service requester, a time interval between each bell press, and the confirmatory signal of successful service fulfillment from the service request device or the service request reception device.
US09251479B2	Multi-interval dispatch method for enabling dispatchers in power grid control centers to manage changes A method is provided that enables dispatchers in power grid control centers to manage changes by applying multi-interval dispatch. A multi-stage resource scheduling engine and a comprehensive operating plan are used. Multiple system parameter scenarios are coordinated.
US09251470B2	Inferred identity Techniques for modifying search results associated with a search request based on a determination that a member profile attribute is inaccurate are described. According to various embodiments, an existing member profile attribute included in a member profile page of a particular member of an online social network service is identified. Member profile data and behavioral log data associated with a plurality of members of the online social network service is then accessed. Prediction modeling to verify the existing member profile attribute is performed using the accessed data. Additionally, a confidence score associated with the existing member profile attribute is generated based on the prediction modeling. Moreover, the existing member profile attribute is determined to be inaccurate based on the generated confidence score. Furthermore, the search results associated with a search request is modified based on the determination.
US09251467B2	Probabilistic parsing Probabilistic parsing is described for calculating information about the structure of text and other ordered sequences of items to enable downstream systems such as machine translation systems, information retrieval systems, document classification systems and others to use the structure information. In various embodiments, a parsing inference component comprises inference algorithm(s) compiled from a probabilistic program which defines a stochastic process for generating text or other ordered sequences of items. In examples, the parsing inference component receives one or more observations or examples of text that are compatible with the stochastic process defined by the probabilistic program. The parsing inference component may apply the inference algorithms to the text to update one or more probability distributions over strings or other values relevant to the parse. In some examples, the parsing inference component uses the inference results to complete partial examples to assist a user with information retrieval tasks.
US09251466B2	Driving an interactive decision service from a forward-chaining rule engine Disclosed techniques include generating a plurality of questions, each question based upon one or more conditions of a plurality of conditions, wherein the plurality of conditions are generated a plurality of business rules associated with a forward changing rule engine; identifying, as a side effect of evaluating the plurality of business rules for outcome data, missing information corresponding to the plurality of questions; and selecting, for presentation to a user, a first question of the plurality of questions to elicit the missing information from the user.
US09251454B2	Storage medium, transmittal system and control method thereof A storage medium including a first transmittal module and a control module. The first transmittal module includes a plurality of first transmittal pads. The control module determines whether a level state of the first transmittal module is equal to a pre-determined state. When the level state is equal to the pre-determined state, the control module operates in a secure digital (SD) mode. When the level state is not equal to the pre-determined state, the control module operates in an embedded multimedia card (eMMC) mode.
US09251453B1	Wearable device with time-varying magnetic field and single transaction account numbers An electronic transaction card communicates with an add-on slot of an intelligent electronic device. The add-on slot may be a memory card slot. The intelligent electronic device may be a mobile phone or other device with or without network connectivity. The electronic transaction card may have magnetic field producing circuitry compatible with magnetic card readers, smartcard circuitry, other point-of-sale interfaces, or any combination thereof.
US09251452B2	Labeling and authenticating using a microtag A system for encoding energy peaks of an identifier comprises an encoder. The encoder is configured to define a readable spectral range of an identifier. The identifier comprises a rugate microtag. The encoder is configured to divide the readable spectral range into a plurality of bins. The encoder is configured to encode in a center of a bin near one end of the readable spectral range a reference peak. The encoder is configured to encode in a center of each of a set of bins a set of peaks of a data pattern within the readable spectral range.
US09251450B2	Image processing system and method of print job for executing print process in normal and secure mode and creates print job cancellation log An image processing apparatus includes a determination unit that determines whether a print job received from outside is a normal print job or an authentication print job, and a control unit. When the determination unit determines that the received print job is the authentication print job, the control unit executes authentication print processing based on the received authentication print job. When the determination unit determines that the received print job is the normal print job, the control unit executes authentication print processing based on the received normal print job instead of executing normal print processing.
US09251448B2	Image processing apparatus including expansion memory An image processing apparatus includes: an interpreter processing part for creating intermediate data by analyzing a page description language; a rasterize processing part for creating RIP image data for each band for dividing each page into a plurality of parts, on the basis of the intermediate data; a characteristic value calculating part for calculating a characteristic value of RIP image data and associating the calculated characteristic value with the corresponding RIP image data; and an expansion processing part for, when the RIP image data whose characteristic value agrees with that of RIP image data that is a target for expansion are stored in a cache, reading out the RIP image data whose characteristic value agrees, the RIP image data being stored in the cache, and storing the RIP image data in an expansion memory.
US09251441B2	Apparatus, method and program An apparatus includes a presenting unit and a control unit. The presenting unit presents a plurality of options for interrupt printing along with an amount of incompletely printed sheet to be discharged while images are being printed on both surfaces of a continuous sheet in accordance with a prior job. The control unit interrupts, when one of the plurality of options presented by the presenting unit is designated, the prior job in timing according to the designated option to execute an interrupt job.
US09251439B2	Image sharpness classification system A method for predicting whether a test image (318) is sharp or blurred includes the steps of: training a sharpness classifier (316) to discriminate between sharp and blurred images, the sharpness classifier (316) being trained based on a set of training sharpness features (314) computed from a plurality of training images (306), the set of training sharpness features (314) for each training image (306) being computed by (i) resizing each training image (306) by a first resizing factor; (ii) identifying texture regions (408, 410) in the resized training image; and (iii) computing the set of sharpness features in the training image (412) from the identified texture regions; and applying the trained sharpness classifier (316) to the test image (318) to determine if the test image (318) is sharp or blurred based on a set of test sharpness features (322) computed from the test image (318), the set of test sharpness features (322) for each test image (318) being computed by (i) resizing the test image (318) by a second resizing factor that is different than the first resizing factor; (ii) identifying texture regions (408, 410) in the resized test image; and (iii) computing the set of sharpness features in the test image (412) from the identified texture regions.
US09251434B2	Techniques for spatial semantic attribute matching for location identification Techniques for spatial semantic attribute matching on image regions for location identification based on a reference dataset are provided. In one aspect, a method for matching images from heterogeneous sources is provided. The method includes the steps of: (a) parsing the images into different semantic labeled regions; (b) creating a list of potential matches by matching the images based on two or more of the images having same semantic labeled regions; and (c) pruning the list of potential matches created in step (b) by taking into consideration spatial arrangements of the semantic labeled regions in the images.
US09251433B2	Techniques for spatial semantic attribute matching for location identification Techniques for spatial semantic attribute matching on image regions for location identification based on a reference dataset are provided. In one aspect, a method for matching images from heterogeneous sources is provided. The method includes the steps of: (a) parsing the images into different semantic labeled regions; (b) creating a list of potential matches by matching the images based on two or more of the images having same semantic labeled regions; and (c) pruning the list of potential matches created in step (b) by taking into consideration spatial arrangements of the semantic labeled regions in the images.
US09251432B2	Method and apparatus for obtaining a symmetry invariant descriptor from a visual patch of an image The present invention concerns a method for deriving from an arbitrary local image descriptor a descriptor that is invariant under arbitrary mirror symmetries. For a point of interest, pi, for which the descriptor is to be determined a direction, ODi is determined. The local patch from which the descriptor is to be extracted is mirrored along ODi if a “smaller than” relation does not hold a feature extracted from the left half of the local image patch, in regard of ODi, compared to the right half of the local image patch. Thereby, the local patch is brought into a normalized intrinsic orientation. Thereafter, the descriptor is extracted. Examples include a mirror symmetry invariant version of Lowe's SIFT.
US09251430B2	Apparatus, method, and program for character recognition using minimum intensity curve of image data A character recognition apparatus may include an imaging element configured to read a character string placed on an information recording medium; an image memory configured to store image data of the character string; and a character segmenting unit configured to segment a character constituting the character string. The character segmenting unit may include a minimum intensity curve creating unit configured to detect a minimum intensity value among light intensity values, and create a minimum intensity curve of the image data according to the minimum intensity value of each pixel row; a character segmenting position detecting unit configured to calculate a space between the characters neighboring in the created minimum intensity curve, in order to detect a character segmenting position between the characters; and a character segmenting process unit configured to segment each character according to the detected character segmenting position between the characters.
US09251429B2	Superpixel-based refinement of low-resolution foreground segmentation A computer-implemented method performs foreground segmentation of an input image. The method receives a first foreground segmentation at a first resolution of the input image and determines a plurality of labelled seed points based on the first foreground segmentation of the input image. The method associates each of the plurality of pixels in the input image with one of the determined labelled seed points to obtain a second foreground/background segmentation of the input image, and performs foreground separation on the input image at a second resolution by classifying each of the segments of the second segmentation as one of foreground and background based on the label of the associated seed point.
US09251428B2	Entering information through an OCR-enabled viewfinder An improved method for entering text or objects into fields is provided. Instead of a keyboard, a viewfinder provides text segmenting, text selecting and text recognizing (optical character recognition—OCR) functionalities. Text at a marker (e.g., a cursor or crosshairs) associated with the viewfinder is recognized and insertion of the recognized text is performed. The current frame is generally not captured by a user. As the user moves the camera to position a new word at the marker, the view finder is updated to provide results of recognition associated with the new word. A user is able to identify an area of interest, select text or other object of interest, and insert the same into one or more fields. The viewfinder may operate in conjunction with a camera of the electronic device on which the viewfinder is operating. Other mechanisms and variations are described.
US09251425B2	Object retrieval in video data using complementary detectors Automatic object retrieval from input video is based on learned, complementary detectors created for each of a plurality of different motionlet clusters. The motionlet clusters are partitioned from a dataset of training vehicle images as a function of determining that vehicles within each of the scenes of the images in each cluster share similar two-dimensional motion direction attributes within their scenes. To train the complementary detectors, a first detector is trained on motion blobs of vehicle objects detected and collected within each of the training dataset vehicle images within the motionlet cluster via a background modeling process; a second detector is trained on each of the training dataset vehicle images within the motionlet cluster that have motion blobs of the vehicle objects but are misclassified by the first detector; and the training repeats until all of the training dataset vehicle images have been eliminated as false positives or correctly classified.
US09251419B2	Automated metric information network A Metric Information Network (MIN) with a plurality of Ground Control Points (GCPs) that are selected in an automated fashion. The GCP selection includes clustering algorithms as compared to prior art pair-wise matching algorithms. Further, the image processing that takes place in identifying interest points, clustering, and selecting tie points to be GCPs is all performed before the MIN is updated. By arranging for the processing to happen in this manner, the processing that is embarrassingly parallel (identifying interest points, clustering, and selecting tie points) can be performed in a distributed fashion across many computers and then the MIN can be updated.
US09251418B2	Method of detection of points of interest in a digital image A camera (10) produces a sequence of images (12) processed by a point of interest search algorithm (14) that is parameterizable with a detection threshold (τ) such that the number (N) of points of interest detected in the image varies as a function of the threshold level. The characteristic giving the number (N) of detected points of interest as a function of the threshold (τ) is modelled by a square root decreasing exponential function, which is dynamically parameterizable with values linked to the image to be analyzed. The method comprises the steps of: a) determining (18) values of parameterization of the decreasing exponential function for the current image; b) predicting (18), for this current image, an optimum value of the threshold by using the modelled characteristic, parameterized with the values determined at step a); and c) applying (14), for at least one later image, the point of interest search algorithm with the optimum threshold value (τ) computed at step b).
US09251417B1	Fast open doorway detection for autonomous robot exploration Described is a system for open doorway detection for autonomous robot exploration, the system includes an onboard range sensor that is operable for constructing a three-dimensional (3D) point cloud of a scene. One or more processors that receive the 3D point cloud from the range sensor. The 3D point cloud is then filtered and downsampled to remove cloud points outside of a predefined range and reduce a size of the point cloud and, in doing so, generate a filtered and downsampled 3D point cloud. Vertical planes are extracted from the filtered and downsampled 3D point cloud. Finally, open doorways are identified from each extracted vertical plane.
US09251414B2	Note recognition and management using color classification This disclosure describes techniques for creating and manipulating software notes representative of physical notes. For example, techniques are described for recognizing physical notes present within a physical environment, capturing information therefrom and creating corresponding digital representations of the physical notes, referred to herein as digital notes or software-based notes. At least some aspects of the present disclosure feature system and methods for note recognition using color classification. The system receives a visual representation of a scene having one or more notes, where each note has a color. The system generates indicators indicative of color classes of pixels in the visual representation. The system further determines a general boundary of one of the notes based on the indicators.
US09251409B2	Methods and apparatuses for gesture recognition Methods, apparatuses, and computer program products are herein provided for enabling hand gesture recognition using an example infrared (IR) enabled mobile terminal. One example method may include determining a hand region in at least one captured frame using an adaptive omnidirectional edge operator (AOEO). The method may further include determining a threshold for hand region extraction using a recursive binarization scheme. The method may also include determining a hand location using the determined threshold for the extracted hand region in the at least one captured frame. The method may also include determining a fingertip location based on the determined hand location. Similar and related example apparatuses and example computer program products are also provided.
US09251408B2	Gesture recognition module and gesture recognition method A gesture recognition module for recognizing a gesture of a user, includes a detecting unit, including at least one image capture device, for capturing at least one image of a hand of the user, to obtain a first position and a second position of the hand sequentially; a computing unit, electrically coupled to the detecting unit, for determining a first angle between a first virtual straight line connected between a fixed reference point and the first position and a reference plane passing through the fixed reference point, and determining a second angle between a second virtual straight line connected between the fixed reference point and the second position and the reference plane; and a determining unit, electrically coupled to the computing unit, for determining a relation between the first angle and the second angle, to decide whether a gesture of the hand is a back-and-forth gesture.
US09251404B2	Name bubble handling Apparatus has at least one processor and at least one memory having computer-readable code stored therein which when executed controls the at least one processor: to determine a name relating to a face in an image; to calculate a first maximum length attribute for a name bubble for the face at a first zoom level; to select a part of the name for inclusion in the name bubble having regard to the first maximum length attribute; to calculate a second maximum length attribute for the name bubble for the face at a second zoom level, the first and second zoom levels being different and the first and second maximum length attributes being different; and to select a part of the name for inclusion in the name bubble for the face at the second zoom level having regard to the second maximum length attribute.
US09251401B1	Facial recognition to positively identify a live person subject A method for authenticating a live person subject. The method includes receiving an authentication request from a user, generating a sequence of instructions instructing the user to point a face toward a sequence of facial directions, wherein the sequence of facial directions are randomly generated using a random sequence generation algorithm, presenting the sequence of instructions to the user, capturing, while presenting the sequence of instructions to the user, a sequence of live-captured facial images (LCFIs) based on a pre-determined frame rate, and generating an authentication result identifying the user as the live person subject by at least, matching the sequence of LCFIs to multiple reference facial images of the live person subject and validating each LCFI in the sequence of LCFIs based on a pre-determined criterion.
US09251400B2	Learning apparatus, method for controlling learning apparatus, detection apparatus, method for controlling detection apparatus and storage medium A learning apparatus comprises a plurality of detection units configured to detect a part or whole of a target object in an image and output a plurality of detection results; an estimation unit configured to estimate a state of the target object based on at least one of the plurality of detection results; a classification unit configured to classify the image into a plurality of groups based on the state of the target object; and a weight calculation unit configured to calculate weight information on each of the plurality of detection units for each of the groups based on the detection results.
US09251399B2	Method of separating object in three dimension point cloud A method of separating an object in a three dimension point cloud including acquiring a three dimension point cloud image on an object using an image acquirer, eliminating an outlier from the three dimension point cloud image using a controller, eliminating a plane surface area from the three dimension point cloud image, of which the outlier has been eliminated using the controller, and clustering points of an individual object from the three dimension point cloud image, of which the plane surface area has been eliminated using the controller.
US09251397B2	Fingerprint image capturing device and fingerprint image capturing module thereof A fingerprint image capturing module includes a light-emitting element, a light-splitting element, a first light-reflecting element, a second light-reflecting element, a lens assembly and a fingerprint image sensing element, characterized in that: a projection light beam generated by the light-emitting element is reflected by the light-splitting element and the first light-reflecting element in sequence to form an illumination light beam that passes through a light-transmitting element and is projected onto a fingerprint of a finger, the illumination light beam is reflected by the finger to form an image light beam that is reflected by the first light-reflecting element, the image light beam sequentially passes through the light-splitting element and the lens assembly and is projected onto the fingerprint image sensing element through the second light-reflecting element, and the fingerprint image sensing element receives the image light beam to obtain a fingerprint image of the fingerprint of the finger.
US09251392B2	Indicia reading apparatus There is set forth herein an indicia reading apparatus having an image sensor array including a plurality of pixels arranged in a plurality of rows and columns of pixels. The image sensor array can include a frame exposure period in which a certain subsequent and further subsequent row exposure periods have common exposure initiation times and each group of rows has sequential exposure termination times. An indicia reading apparatus can be controlled so that a light source bank of an illumination pattern assembly for projecting an illumination pattern is energized during an illumination period that overlaps a frame exposure period. The apparatus can be further controlled so that an illumination period terminates at or prior to an exposure termination time of the certain row.
US09251391B2	Method for continuous detection of a persons presence on public transportation A method for continuous determination of a person's presence in a public transport conveyance is proposed, where a customer medium comprising an RF transceiver is assigned to the person, where at least one reading device per passenger compartment or car is provided for data communication with the customer media in the conveyance, which is connected to a computer serving as an on-board unit for the purpose of data communications, where these are also connected to each other in the case that several reading devices are provided, where an on-board unit serving as the main on-board unit is assigned to a passenger compartment or car if several passenger compartments or cars are present, and the other passenger compartments or cars are assigned to on-board units serving as secondary on-board units, which are connected to the main on-board unit for the purpose of data communication, where the customer medium is in a “sleep” mode upon entering the transport in order to keep energy consumption as low as possible.
US09251390B2	Item identification device antenna An item identification device antenna which provides better field coverage for reading item identification tags. The item identification device antenna includes a first portion coupled to a tag reader for reading a tag on an item, wherein the first portion is for radiating an electromagnetic field at a predetermined frequency, and a second portion in the electromagnetic field for resonating at the predetermined frequency to radiate another electromagnetic field for reading the tag. The tags may include radio frequency identification (RFID) tags.
US09251388B2	Method for deploying large numbers of waste containers in a waste collection system A method of redeploying waste containers in a waste collection system with an active or passive signal means requires a user to aim an optical character recognition reader at a waste container comprising a unique optical waste container identifier. The optical character recognition reader reads unique waste container optical identifier. The unique waste container optical identifier is converted to a unique electronically formatted waste container identifier. A unique radio frequency signal identifier is stored on a radio frequency emitting tag and associated with the unique electronically formatted waste container identifier. The radio frequency emitting tag is attached to the waste container.
US09251383B2	Device for preventing logging of computer on-screen keyboard A device for preventing logging of computer on-screen keyboard has a pointer device and tandem device. The pointer device comprises a first transmission interface to connect the host computer, and an encryption module to encrypt and transfer data of the pointer device to the first transmission interface. This data contains pointer coordinates. A pointer data module is used to obtain, convert and save the coordinate data of the pointer device. A push-button data module is used to obtain, convert and save the push-button data of the existing pointer device. A physical interface module is used to obtain coordinates of the pointer device and original data of key events. The original data is converted into coordinates or push-button data of the pointer device by the pointer and push-button data modules. Then the encryption module decides if it is necessary to transfer the coordinate or push-button data in the form of encryption.
US09251382B2	Mapping encrypted and decrypted data via key management system A data processing system having a host computer including a key manager, a control unit connected to the host computer, a data storage unit (such as a tape drive) controlled by the control unit, and data storage medium for storing data thereon to be written to or read from by the data storage unit. The key manager stores a data structure having at least one record having a volume serial number, as start location, a length entry, and a key for encrypting and decrypting data on the data storage medium. A data storage medium (such as data tape) is mounted on the data storage unit, and a volume recorded on the tape is retrieved. The control unit retrieves the data structure from the key manager and matches the volume serial number recorded in the retrieved data structure with the volume serial number retrieved from the data storage medium. It they match, the control unit passes to the data storage unit, commands to turn on or turn off encryption dependent upon the location where data is written by the data storage unit onto the data storage medium, or to turn on or turn off decryption dependent upon the location where data is read by the data storage unit from the data storage medium.
US09251381B1	Solid-state storage subsystem security solution A solid-state storage subsystem, such as a non-volatile memory card or drive, includes a main memory area that is accessible via standard memory access commands (such as ATA commands), and a restricted memory area that is accessible only via one or more non-standard commands. The restricted memory area stores information used to control access to, and/or use of, information stored in the main memory area. As one example, the restricted area may store one or more identifiers, such as a unique subsystem identifier, needed to decrypt an executable or data file stored in the main memory area. A host software component is configured to retrieve the information from the subsystem's restricted memory area, and to use the information to control access to and/or use of the information in the main memory area.
US09251380B1	Method and storage device for isolating and preventing access to processor and memory used in decryption of text A storage drive includes a first memory that stores first text. A first processor generates a first instruction to decrypt the first text. A cryptographic module includes a second memory, a cryptographic device, a memory module, and a second processor. The second memory is inaccessible to the first processor and stores a cryptographic key. The cryptographic device accesses the second memory to obtain the cryptographic key and based on the first instruction, decrypts the first text. The memory module stores a status of execution of the first instruction by the cryptographic device. The second processor, prior to the cryptographic device decrypting the first text, forwards the first instruction to the cryptographic device and stores the status of execution of the first instruction in the memory module. The memory module is connected between the first and second processors and isolates the first processor from the second processor.
US09251373B2	Preventing stack buffer overflow attacks Improved buffer overflow protection for a computer function call stack is provided by placing a predetermined ShadowKEY value on a function's call stack frame and copying the ShadowKEY, a caller EBP, and a return pointer are pushed onto a duplicate stack. The prologue of the function may be modified for this purpose. The function epilogue is modified to compare the current values of the ShadowKEY, caller EBP, and the return pointer on the function stack to the copies stored on the duplicate stack. If they are not identical, an overflow is detected. The preserved copies of these values may be copied back to the function stack frame thereby enabling execution of the process to continue. A function prologue and epilogue may be modified during compilation of the program.
US09251370B2	Personal content control on media device using mobile user device A method for controlling personal content on a media device includes establishing, at the media device, a wireless connection with a mobile user device using a wireless communication circuit of the media device; receiving, from the mobile user device, account information for an account associated with personal content, the personal content of the account accessible by the media device from a server computer over a communication network or from a memory of the media device; receiving, from the mobile user device, a usage term for accessing or using the personal content of the account; and controlling access to or usage of the personal content of the account by the media device based on the received account information and the usage term.
US09251368B2	Provisioning transient-controlled secure environments for viewing sensitive data A new approach to customer support that protects working artifacts through their entire lifecycle by provisioning, on-demand, a transient-controlled debugging environment that preferably is associated with a particular support issue (or subset of issues) when particular artifacts (e.g., files) are securely received at the service or software provider. This approach allows for complete (or substantially complete) isolation and control of the artifacts in a contained environment for so long as necessary by the provider. Preferably, the provider owns or otherwise manages the provisioned environment, which can be augmented as needed to meet the debugging requirements of the particular issue. Preferably, the provisioned environment is restricted in access to only those engineers or others with a verifiable need to know, or that have the necessary training and skill sets for the support operation required.
US09251367B2	Device, method and program for preventing information leakage Provided is a device for preventing information leakage including: a storage unit that stores message time, request source information, and request destination information in relation to each information requesting message; a unit that suspends a response message containing personal information in response messages in response to the information requesting messages, for a predetermined suspended time from a message time of the corresponding information requesting message; a unit that counts the number of information requesting messages transmitted from the same request source to the same destination and corresponding to the suspended response message on the basis of information stored in the storage unit; and a unit that, in the case where the counted number of the information requesting messages exceeds a predetermined threshold value, applies a protection process to the suspended response message so that the personal information contained in the suspended response message is not received by the request source.
US09251362B2	Medium for storing control program, client apparatus, and control method for client apparatus A computer-readable storage medium that stores a control program for a client apparatus connectable to a repeater storing execute permission information on a plurality of codes included in an application program received from a server, the control program causing the client apparatus to execute a process including receiving the application program and the execute permission information from the repeater, updating the execute permission information received from the repeater based on evaluation information on the application program received from the repeater, and executing the application program based on the execute permission information updated based on the evaluation information.
US09251359B2	Method and apparatus for managing crowd sourced content creation A method, apparatus, computer program product and system are provided for managing crowd sourced content creation. In this regard, a method is provided that includes receiving information regarding at least one content recording device and information regarding a recording subject. The method further includes determining whether the at least one content recording device is eligible to receive at least one permission indicator, based at least in part on the information regarding the at least one content recording device and the information regarding the recording subject. The method also includes causing the at least one permission indicator to be provided to the at least one content recording device in an instance in which it is determined that the at least one content recording device is eligible to receive the at least one permission indicator.
US09251358B2	System and method for providing secure access to system memory There is provided a method of providing secure access to data stored in a system memory of a computer system, the computer system comprising a memory controller for writing data to and reading data from the system memory. The method comprises generating a random encryption key each time the computer system is booted and storing the random encryption key in a volatile memory region of the memory controller. The method additionally comprises encrypting data using the random encryption key to create encrypted data, and storing the encrypted data in the system memory. Also provided are a memory subsystem and a computer system for performing the method.
US09251357B2	Scalable precomputation system for host-opaque processing of encrypted databases A method, system, and computer program product to generate results for a query to an encrypted database stored on a host are described. The system includes a host comprising a storage device to store the encrypted database, and a a secure processor to generate indexes and index metadata from the encrypted database, each index identifying records of the encrypted database associated with a range of data for at least one field stored in the records of the encrypted database and the metadata indicating the range of data identified by the associated index. The system also includes an interface of the host to receive the query, and a host processor to generate a sub-query form the query for each field associated with the query. Based on sub-query results obtained through the index metadata, the secure processor searches a subspace of the encrypted database to generate the results of the query.
US09251355B2	Field level database encryption using a transient key Embodiments of the present invention disclose a method, system, and computer program product for implementing user specific encryption in a database system. A computer receives a query statement including a user specific key and data, the data including data needing encryption and non-encrypted data. The computer encrypts the data needing encryption using the user specific key. The computer inserts both the encrypted data and the non-encrypted data into a table row in a database. The computer creates a hash of the user specific key, and stores the hash of the user specific key in the table row with the data.
US09251351B2	System and method for grouping computer vulnerabilities A system and method in one embodiment includes modules for creating an asset tag including one or more conditions of an asset on a network, adding the asset tag to an asset report template, and generating an asset report from the asset report template. More specific embodiments include creating the asset tag by generating a query for the one or more conditions. The asset tag may include a second asset tag configured to be updated automatically, and a third asset tag configured to be updated manually, and the second asset tag may be updated automatically when the asset tag is updated. Other embodiments include creating a vulnerability set including a selection of vulnerabilities from a plurality of vulnerabilities, adding the vulnerability set to the asset report template, and scanning a plurality of assets on the network.
US09251349B2	Virtual machine migration Attesting a virtual machine that is migrating from a first environment to a second environment includes in response to initiation of migration of the virtual machine from the first environment to the second environment, accessing one or more stored trust values generated during the trusted boot of the virtual machine in the first environment, determining if the accessed trust values define a security setting sufficient for the second environment, and if the accessed trust values do not define a security setting sufficient for the second environment, performing a predetermined action in relation to the migration of the virtual machine to the second environment.
US09251348B2	Detection of return oriented programming attacks In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
US09251346B2	Preventing propagation of hardware viruses in a computing system Preventing propagation of hardware viruses in a computing system, including: determining, by a hardware virus detection module, whether an empty connector in the computing system is damaged, wherein the empty connector is blocked from receiving an attachable computing device by a bumper; determining, by the hardware virus detection module, whether a connector for the attachable computing device is damaged; and responsive to determining that the empty connector is not damaged and that the connector for the attachable computing device is not damaged, moving the bumper such that the empty connector is not blocked from receiving the attachable computing device.

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