| Document | Document Title |
|---|---|
| US09197315B2 |
Peer group diagnosis detection method and system
Systems and methods for peer group diagnosis detection are disclosed. In an example embodiment, a beam profile including a plurality of satellite beam characteristics is determined. A peer group of satellite terminals is determined. Terminal profiles with terminal characteristics for the satellite terminals in the peer group are determined. A normalized baseline profile including normalized terminal characteristics for the peer group is determined. Measured operational statistics of the satellite terminals in the peer group are received and converted into normalized operation statistics using the terminal profiles and the normalized baseline profile. Normalized peer group operational statistics including a mean and a standard deviation of normalized operational statistics are determined. A normalized deviation of the normalized operational statistics is determined for each satellite terminal. The normalized deviations for each satellite terminal are compared to a threshold deviation. Satellite terminals are diagnosed as good, degraded, or bad. |
| US09197312B2 |
Near field communication system in a local network
A system for a local network, the system being configured to extend a near field communication (NFC) between an NFC device and an NFC mobile device beyond the range defined by the NFC standards. |
| US09197307B2 |
Method and terminal apparatus for receiving reference signal
A wireless communication system and a method for detecting downlink receiving power in the system are disclosed. N cells in the system respectively transmit data to at least one receiving terminal via N resource blocks using the same time-frequency resources; multiple channel state information reference signals (CSI-RSs) of a corresponding cell are set in each resource block, and orthogonality is maintained among the CSI-RSs of all the cells, wherein N is an integer greater than 1. Said method includes: an additional demodulation reference signal (DM-RS) used for indicating a receiving power is set in a puncture position in the resource block of the first cell which corresponds to a CSI-RS set in a resource block of another cell; and the receiving power of said first cell is detected according to said additional DM-RS. By using said method, the receiving power of a single cell in N cells can be detected, and the system overhead is not increased. |
| US09197305B2 |
Precoding control indication feedback method, user equipment, and base station
Embodiments of the present invention disclose a precoding control indication feedback method, a user equipment, and a base station. Channel capacity values corresponding to precoding matrices in a precoding matrix set are calculated. A sequence number of a precoding matrix corresponding to a maximum channel capacity value is used as a PCI to be used. The PCI to be used, a CQI indicating downlink channel quality, and ACK/NACK indicating a data decoding result are borne over an uplink HS-DPCCH. The same are fed back to a corresponding base station node to instruct the base station node to select a MIMO single-stream manner or a single-antenna manner to send data to be sent. |
| US09197304B2 |
Method and apparatus for conveying antenna configuration information via masking
A method, apparatus and computer program product are provided for conveying information regarding the antenna configuration and/or the transmission diversity scheme to a recipient, such as a mobile device. In particular, information regarding the antenna configuration and/or the transmission diversity scheme can be conveyed by masking, such as cyclic redundancy check masking, to provide information regarding the antenna configuration and/or the transmission diversity scheme. In this regard, a set of masks can be determined based upon hamming distances between the masks and bit diversities between the masks and where each of the masks within the set is associated with an antenna configuration and a transmission diversity scheme. |
| US09197298B2 |
Group identification and definition within multiple user, multiple access, and/or MIMO wireless communications
Group identification and definition within multiple user, multiple access, and/or MIMO wireless communications. A group identification definition field may be transmitted to a number of receiving devices for use in interpreting current or subsequently received packets that include a group identification field (group ID). The group ID can serve a number of functions such as indicating those receiving devices for which the packet is intended, the identification of fields within the packet corresponding to the various devices, certain parameters (e.g., code type, code rate, modulation type, etc.) associated with such fields within the packet, etc. The group identification definition field may be updated or modified to allow for modification of the manner in which subsequent packets, including respective group IDs, are processed. One of a variety of events may direct the group identification definition field may be updated or modified. |
| US09197291B2 |
Circuit arrangement and method for bidirectional data transmission
A transformer arrangement for signal transmission is provided, the transformer arrangement having at least one transformer with a primary coil and a secondary coil and a controller. The controller is configured in a magnetization phase to control a first current to flow through the primary coil to increase until a predefined criterion is fulfilled, wherein the magnetization phase is longer than a time constant of the primary coil of the at least one transformer. The controller is configured in a voltage application phase to apply a voltage to the at least one transformer so that a second current flows through the primary coil, wherein the second current has a polarity which changes during the voltage application phase compared with the first current, wherein the voltage application phase is shorter than two times the time constant of the primary coil of the at least one transformer. |
| US09197288B2 |
Determining the signal quality of an electrical interconnect
One embodiment provides a network device that includes PHY circuitry comprising transmit circuitry (Tx) and receive circuitry (Rx), wherein the Tx and Rx circuitry are configured to be coupled to a respective channel to communicate with an external device via the channels, wherein the network device configured to communicate with the external device using an Ethernet communications protocol; and test circuitry. The test circuitry is configured to: designate a through channel and at least one crosstalk channel from among the channels; determine, in the time domain, an approximate available signal voltage of a first response signal, wherein the first response signal is in response to a test signal applied to the through channel; determine a first noise profile of the first response signal in response to the test signal applied on the through channel; determine a second noise profile of a second response signal, wherein the second response signal is in response to the test signal applied on a crosstalk channel and measured on the through channel; and determine a signal-to-noise ratio of the through channel based on, at least in part, the approximate available signal voltage and the first and second noise profiles. |
| US09197284B2 |
Method and apparatus for pilot signal processing in a wireless communication system
A wireless communication system is provided that spreads pilot signals, or channel state information reference signals (CSI-RSs), using a spreading code chosen from a set of mutually unbiased bases (MUBs). The advantages of such spreading with MUBs are that multiple base stations can send their pilot signals on a same time-frequency resources, making the pilot signal design very efficient and also improving channel estimation at a user equipment through orthogonal and quasi-orthogonal spreading which gives a gain above noise and interference. A short spreading code chosen from MUBs may be used for spreading pilot signals transmitted from each antenna of a base station within a time-frequency resource comprising multiple closely-spaced subcarriers in frequency and/or multiple closely-spaced symbols in time. |
| US09197280B1 |
Radio frequency switch
A radio frequency switch may include: a common port transmitting and receiving a radio frequency signal; a receive switch unit including a first switch unit having a plurality of first switch elements and a second switch unit having a plurality of second switch elements; and a transmit switch unit including a third switch unit having a plurality of third switch elements and a fourth switch unit having a plurality of fourth switch elements. The receive switch unit may further include a plurality of first capacitors connected between a first terminal and a body terminal of each of the plurality of first switch elements. The transmit switch unit may further include a plurality of second capacitors connected between a second terminal and a body terminal of each of the plurality of third switch elements. |
| US09197278B2 |
Reference oscillator arbitration and scheduling for multiple wireless subsystems
Systems and methods are described for controlling a reference oscillator shared by multiple subsystems of a communications system and arbitrating usage of the reference oscillator among these subsystems. By changing the properties of the reference oscillator (e.g., by tuning the reference oscillator) according to the needs of particular subsystem(s), the communications system can configure the reference oscillator to meet the specification requirements of these particular subsystem(s) and can later reconfigure the reference oscillator to meet the needs of other subsystems. Further, the controller can configure the subsystems based on parameters that impact multiple subsystems (e.g., by implementing geographic awareness, spectrum occupation awareness, and availability of Assisted GPS (AGPS) functionality) to achieve further optimization of the communications system. |
| US09197273B2 |
Case for mobile communication device with flash and camera controls
A mobile device case is formed with a hollow case housing for receiving a mobile device and controlling a mobile device camera therein. The mobile device includes a case connector for electronically connecting the case to the mobile device at insertion of the mobile device into the hollow case housing and at least one camera control actuator for controlling operation of the mobile device camera, when the mobile device is present in the hollow case housing. The hollow case housing comprises a first housing section and a second housing section that comes together by respective tongue and groove elements to thereby encapsulate the mobile device. |
| US09197270B2 |
Double ring antenna with integrated non-cellular antennas
Wireless electronic devices may include a ground plane, a double ring antenna and non-cellular antennas integrated within the double ring antenna. The double ring antenna may comprise first and second metal rings around the perimeter of a ground plane to operate as MIMO cellular antennas. At least one non-cellular antenna, such as a MIMO Wi-Fi antenna, may be integrated between the first and second metals rings on one or more sides of the wireless electronic device. |
| US09197268B1 |
Method and apparatus for compensating for IQ mismatch in radio frequency receivers
A receiver including a physical layer module, a function module, a residual module, an IQ mismatch module, and a compensation module. The physical layer module is configured to (i) receive a signal, and (ii) downconvert the signal to generate a downconverted signal, wherein the downconverted signal has IQ mismatch. The function module is configured to determine (i) a first value based on a first function and a resultant signal, and (ii) a second value based on a second function. The residual module is configured to estimate a residual IQ mismatch based on the first value and the second value. The IQ mismatch module is configured to estimate an IQ mismatch coefficient based on the estimate of the residual IQ mismatch. The compensation module is configured to compensate for the IQ mismatch of the downconverted signal including generating the resultant signal based on the estimate of the IQ mismatch. |
| US09197263B2 |
Compensation apparatus, signal generator and wireless communication equipment
A compensation apparatus compensates a quadrature-demodulated signal output from a quadrature demodulator 5 that performs quadrature demodulation by using a signal of a carrier frequency fc, by removing an image component caused by the quadrature demodulator 5 from the quadrature-demodulated signal. The compensation apparatus includes a signal generator 10 that generates a reference signal having a predetermined bandwidth in a reception band, and provides the reference signal to an input side of the quadrature demodulator 5. The reference signal includes a frequency band that is biased to either a higher-frequency side or a lower-frequency side with respect to the carrier frequency. |
| US09197256B2 |
Reducing effects of RF mixer-based artifact using pre-distortion of an envelope power supply signal
A radio frequency (RF) power amplifier (PA) and an envelope tracking power supply are disclosed. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using an envelope power supply signal, which at least partially envelope tracks the RF transmit signal, such that the RF input signal has an RF mixer-based artifact. The envelope tracking power supply provides the envelope power supply signal, which includes mixer-based artifact pre-distortion to at least partially remove effects of the RF mixer-based artifact from the RF transmit signal. |
| US09197254B2 |
Transmitter and method of operating a transmitter
A transmitter is provided that comprises an oscillator, a power amplifier, and a heating element. The power amplifier generates a high power signal according to the low power signal. The transmitter may be operated such that a heat production rate of the group consisting of the power amplifier and the heating element is substantially constant. The heating element may be a dummy power amplifier. A method of operating a transmitter is also disclosed. |
| US09197244B2 |
Multi-layer system for symbol-space based compression of patterns
A method and apparatus for symbol-space based compression of patterns are provided. The method comprises generating an output sequence responsive of an input sequence, the input sequence being of a first length and includes a plurality of symbols, by extraction of all common patterns, wherein a common pattern includes at least two symbols and the output sequence is of a second length that is shorter than the first length; and storing in a memory the output sequence as a data layer. |
| US09197241B2 |
Output power control for RF digital-to-analog converter
Methods and apparatus, including computer program products, are provided for power control of RF DACs. In one aspect there is provided an apparatus. The apparatus may include a multiphase clock generator to provide tunable multiphase clock signals including a first clock signal and a second clock signal; and a radio frequency digital-to-analog converter including a first input to receive digital input data, a second input to receive the first clock signal and the second clock signal, and an output to provide an analog output signal, wherein when at least one of a phase difference and a time difference between the first clock signal and the second clock signal is varied, a gain of the analog output signal is varied. Related apparatus, systems, methods, and articles are also described. |
| US09197240B1 |
Method and circuit for noise shaping SAR analog-to-digital converter
An analog-to-digital conversion system includes a track-and-hold unit configured to output an input value; a digital-to-analog (D/A) conversion unit configured to generate a feedback value; a coupling unit configured to generate an error signal value based on the input signal and the feedback value; a loop filter configured to generated a filtered error signal value; a comparison unit configured to generate a comparison result based on the input value minus the summation of the feedback value and the filtered error signal value; and a control unit. The control unit is configured to, during a sampling cycle, set an N-bit logical value accordingly to N comparison results; and to cause the coupling unit to generate the error signal value. N is a positive integer. |
| US09197238B1 |
Adaptive clocking for analog-to-digital conversion
An analog-to-digital conversion system and method includes, for example, a comparator for sampling an analogy quantity during a sampling period and for performing a series of bit-wise conversions on the sampled analog sample during a conversion period, where each bit-wise conversion occurs during a respective bit-wise conversion cycle in which successive bits of a sample are successively determined during a respective bit conversion cycle and in which a predetermined number of bit-wise conversions are to be performed. A clock generator is arranged for generating a clock signal for clocking the converter during the conversion period, wherein each bit conversion cycle includes a reset period having a first length and an amplification period having a second length, wherein one of the first and second lengths is dynamically selected. |
| US09197236B1 |
Digitizer auto aperture with trigger spacing
A method for producing sampled data, which as the requested sampling period is increased, each sample is the average of an increasing number of ADC samples such that a maximum number of ADC samples are evenly space across the sample period. The method can include choosing one of multiple ADC with varying speed versus resolution capabilities to further increase the quality of the sampled data as the sampling period increases. |
| US09197233B2 |
Low power ADC for high dynamic range integrating pixel arrays
In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes an input current buffer circuit, a signal charge integration node, a dual function comparator, a step charge subtractor, a state latch, a coarse N-bit counter, an optional residue signal buffer and a residue signal M-bit time-to-digital (TDC) converter. The circuitry is free running, meaning that it is never reset. Instead, what is tracked for each frame is how much additional charge has been accumulated since the end of the previous integration period. Between each frame, the state of the counter and the amount of charge residing in the integration node are recorded. This information from the beginning and end of a given frame is differenced and to this is added the amount of charge indicated by the number of times the counter overflowed during the integration period. |
| US09197230B2 |
Atomic oscillator, electronic apparatus, and moving object
An atomic oscillator includes a gas cell, a semiconductor laser, a light detector, a bias current control section controlling a bias current based on intensity of light detected by the light detector, a memory, and an MPU. The MPU sweeps the bias current and stores a value of the bias current and a value of the intensity of the light when the intensity of the detected light shifts from a decrease to an increase and re-sweeps to set the bias current based on the value of the bias current stored in the memory after the sweep, compares the value of the intensity of the detected light with the value of the intensity of the light stored in the memory while the bias current control section controls the bias current, and determines whether to perform the sweep again in accordance with the comparison. |
| US09197229B2 |
Panel driving circuit and ring oscillator clock automatic synchronization method thereof
A ring oscillator clock automatic synchronization method of a panel driving circuit includes steps of: when a vertical blanking interval happens, a master driver generates a pulse signal to slave drivers respectively. A pulse width of the pulse signal equals to N times of a master ring oscillator clock, wherein N is larger than 0. When a slave driver receives the pulse signal, the slave driver uses its slave ring oscillator clock to count the pulse width of the pulse signal to obtain that the pulse width of the pulse signal equals to M times of the slave ring oscillator clock, wherein M is larger than 0. The slave driver compares M with N and automatically adjusts the slave ring oscillator clock according to the comparison result to make it achieve synchronization with the master ring oscillator clock. |
| US09197228B2 |
Circuit and method for adjusting oscillating frequency of an oscillator
A circuit comprises an oscillator, a frequency divider and a comparator. The oscillator generates an oscillating signal (Fvco). The frequency divider is communicatively coupled to the oscillator, divides a frequency of the oscillating signal by a denominator and generates a divided signal. The comparator is communicatively coupled to the oscillator and the frequency divider, and is configured to obtain a first count of the divided signal (Fvco/N) within a predetermined time and a second count of a reference signal within the predetermined time; compare the first count with the second count, and generate a comparison result according to the first count and the second count. The oscillator is further configured to adjust the frequency of the oscillating signal according to the comparison result. |
| US09197226B2 |
Digital phase detector
According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase. |
| US09197222B2 |
Method and apparatus of a resonant oscillator separately driving two independent functions
Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function. |
| US09197218B2 |
Electronic device, electronic apparatus, moving object, and method for manufacturing electronic device
An electronic device includes: a support member including a first terminal, a second terminal, and a support portion extending from the first terminal and coupling the first terminal with the second terminal; an electronic component; and a bonding member connecting the first terminal with the electronic component. In a plan view along a direction in which the first terminal and the electronic component overlap each other, a portion of the first terminal is adjacent to the support portion with a notch portion therebetween and protrudes toward the extending direction side of the support portion. The support portion is bent at a portion adjacent to the protruding portion of the first terminal along the overlapping direction. |
| US09197215B1 |
Graphene-based non-boolean logic circuits
A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits. |
| US09197206B2 |
Proximity switch having differential contact surface
A proximity switch assembly and method for activating a proximity switch is provided. The assembly includes a proximity sensor generating a signal, and a contact surface proximate to the proximity sensor and having a differential elevation change feature. The proximity switch also includes control circuitry processing the signal to detect a differential increase in the activation signal indicative of a hard press on the contact surface. The control circuitry detects activation of the switch based on the differential increase exceeding a differential threshold. Activation can further be determined based on a stable signal. |
| US09197203B2 |
Cycle modulation circuit for limiting peak voltage and associated power supply
A cycle modulation circuit for limiting voltage peak value of a power supply employed an active clamp. The power supply receives an input power which is modulated through a power driving unit to become a driving power transformed through a transformer to be output. The cycle modulation circuit includes a comparison unit and a linear voltage generation unit. The comparison unit receives the input power to generate a level signal which is used as a base value to compare level with an oscillation signal generated by the linear voltage generation unit, thereby to modulate and output a pulse width limit signal with a composite cycle consisting of a high level and a low level. The pulse width limit signal is input to the power driving unit to limit the peak value of the driving power modulated by the power driving unit. |
| US09197202B2 |
Phase mixing circuit, and semiconductor apparatus and semiconductor system including the same
A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals. |
| US09197201B2 |
Impulse voltage generation device
A signal generator generates a combined signal that is generated only in the period where supply of a pulse signal is effected, a pulse signal whose frequency is of a higher impulse repetition frequency than the frequency of the period setting signal and whose amplitude represents a voltage value that is lower than the high voltage HVDC value. A semiconductor switch accumulates electric charge on a capacitative element by means of the high voltage HVDC from the high voltage generator when the voltage value of the combined signal is lower than the set gate voltage value and generates an impulse voltage whose peak value is the value of the high voltage HVDC, by means of the electric charge that is discharged from the capacitative element when the voltage value of the combined signal exceeds the set gate voltage value. |
| US09197186B2 |
Duplexer with phase shifter circuit
A duplexer comprising an improved matching circuit for matching between transmitting path and receiving path is specified. In this case, the matching circuit comprises a hybrid and matching elements. |
| US09197175B2 |
Methods and systems for pre-emphasis of an envelope tracking power amplifier supply voltage
Embodiments provide systems and methods for producing an envelope tracking (ET) PA supply voltage with minimum headroom relative to the desired RF output signal of the PA. In an embodiment, the PA supply voltage is generated by applying an ET signal to an ET path of the wireless device, and by further applying pre-emphasis to the ET signal to compensate for a frequency response of the ET path. Embodiments operate by estimating the frequency response of the ET path and determining the pre-emphasis based on the estimate of the frequency response of the ET path. In embodiments, the pre-emphasis is applied using a pre-emphasis filter, which may be within or outside of the ET path. Further, the pre-emphasis may be applied to the ET signal in digital or analog form. |
| US09197172B2 |
Switched mode high linearity power amplifier
A switched mode, high linearity power amplifier can include a dynamic quantizer, a pulse width modulator and an output driver. In one embodiment, the dynamic quantizer can include a sigma-delta modulator configured to provide a multi-level digital signal. The pulse width modulator can receive the multi-level digital signal and provide a variable pulse width signal based, at least in part, on the multi-level digital signal. The output driver can include a class D output driver. The output driver can receive the variable pulse width signal to operate the class D output driver and provide an amplified signal. In one embodiment, the output driver can adjust the amplified signal to compensate for output errors. |
| US09197171B2 |
Multi-stage amplifier with pulse width modulation (PWM) noise shaping
A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load. |
| US09197170B2 |
Active lumped element circulator
An integrated circuit can comprise: a first port, a second port, and a third port; and a plurality of microwave operational amplifiers coupled to each other and the first port, the second port, and the third port. The plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the first port to the second port while substantially isolating the signal provided to the first port from the third port; the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the second port to the third port while substantially isolating the signal provided to the second port from the first port; and the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the third port to the first port while substantially isolating the signal provided to the third port from the second port. |
| US09197166B2 |
Increasing power amplifier linearity to facilitate in-device coexistence between wireless communication technologies
A method of increasing power amplifier linearity to facilitate in-device coexistence between wireless communication technologies is provided. The method can include determining a scheduled time period during which data is received by a device via a first wireless communication technology. The method can further include adjusting an operational parameter of a power amplifier applied to a transmission from the device via a second wireless communication technology to increase a linearity of the power amplifier during the scheduled time period. |
| US09197158B2 |
Dynamic frequency divider circuit
The invention relates to a Frequency Divider Circuit for dividing an input RF signal to a frequency divided RF signal. The circuit comprises a RF pair, a switching-quad pair coupled in series with a transimpedance amplifier and a double pair of emitter followers. The circuit comprises coupling elements for providing first DC paths to first amplifier paths of the RF pair and for providing second DC paths to second amplifier paths of the series arrangement of the switching-quad pair and the transimpedance amplifier. The first DC paths are independent of the second DC paths. RF connections are provided to couple the first and the second amplifier paths for transferring a signal from the first amplifier paths to the second amplifier paths. |
| US09197156B2 |
Oscillation element, oscillator, and imaging apparatus using the same
An oscillation element includes an antenna for oscillation configured to oscillate electromagnetic waves, and multiple negative resistance elements electrically connected to the antenna in parallel, and the multiple negative resistance elements are disposed in only a place where the phases of electromagnetic waves oscillated therefrom are the common phase or opposite phase. |
| US09197153B2 |
Power tool having display that displays residual capacity of battery
A power tool includes a housing, an electric motor accommodated in the housing, a secondary battery that supplies electric power to the electric motor, a handle provided at the housing, a trigger switch provided at the handle for controlling electric power supply to the electric motor, a residual capacity display for displaying a residual capacity of the secondary battery, and a lock-release switch provided at the handle and configured to allow the trigger switch to be operable and to start displaying the residual capacity at the residual capacity display upon manipulation to the lock-release switch. |
| US09197146B2 |
Brushless direct-current motor and control for power tool
Brushless direct-current (“BLDC”) motor and control for a power tool. A BLDC motor of a power tool is controlled in either a pulse-width modulation (“PWM”) commutation mode or a centerline commutation mode. When the motor is rotating slowly, the motor is operated using PWM commutation. When the motor is rotating at a speed greater than a threshold speed value, the operation of the motor is transitioned to the centerline commutation mode. When operating in the centerline commutation mode, the high-side field-effect transistors (“FETs”) and low-side FETs can each be used for motor speed control. By switching between speed control using the high-side FETs and speed control using the low-side FETs, the heat generated by freewheeling currents can be approximately evenly distributed among the high-side and low-side FETs. |
| US09197145B2 |
Motor control apparatus and power steering apparatus
The present invention performs pulse shift control in such a manner that a difference between switching timings of PWM duty signals can reach or exceed a second predetermined value when the difference between the switching timings of the PWM duty signals of phases falls below the first predetermined value, and determines a correction amount for the phase by the pulse shift control in such a manner that a correction amount after switching becomes smaller than a correction amount before the switching of a phase on which the pulse shift control is performed in pulse shift phase switching control. |
| US09197142B2 |
Drive unit
A drive unit includes an ultrasonic actuator having an actuator body formed using a piezoelectric element, and a driving element provided on the actuator body and configured to output a driving force by moving according to the vibration of the actuator body, and a control section configured to induce the vibration in the actuator body by applying a first and a second AC voltages having a same frequency and different phases to the piezoelectric element. The control section adjusts the first AC voltage and the second AC voltage so that the first AC voltage and the second AC voltage have different voltage values from each other. |
| US09197138B2 |
Voltage step-up six-phase autotransformer passive rectification AC-DC converter
A three phase step-up autotransformer construction is discussed herein. The passive 12-pulse AC-DC converter offers simplicity, high reliability and low cost solution to AC-DC power conversion. The autotransformer is a component of the passive 12-pulse AC-DC converter. The autotransformer converts three-phase AC power into six-phase AC power. With appropriate vector design, the autotransformer may be configured to draw a near sinusoidal 12-pulse current waveform from the three-phase voltage source. The six-phase output may be configured to drive a rectifier (non-linear) load. |
| US09197136B2 |
Switched-mode power supply for providing a stable output voltage
The present invention is a switched-mode power supply for providing a stable output voltage. An excitation winding, a vice-output winding and an active snubber circuit are connected to a primary side of a flyback-based transformer. A main-output winding is connected to a secondary side of the transformer. A primary-side PWM controller and a secondary-side PWM controller are respectively connected to the primary side and the secondary side of the transformer. By a time-shared-energy-transfer method, the main-output winding and the vice-output winding are controlled to sequentially extract demand electricity from the transformer during a same switching cycle. Additionally, by a time-shared-energy transformation, the output voltage on the secondary side of the transformer is stabilized to be provided between a stable minimal voltage and a preset higher voltage for satisfying a heavy-loading status and a light-loading status. |
| US09197133B2 |
Voltage waveform detector, power controller and control method for switched-mode power supplies with primary-side control
Disclosed are a voltage waveform detector, a power controller and a control method used therein, adaptive for a switched-mode power supply having a power switch and an inductive device. A disclosed power controller has a voltage waveform detector and a constant-current control unit. The voltage waveform detector estimates a discharge time of the inductive device when the power switch is turned off. In the voltage waveform detector, a differential capacitor is coupled between an input node of a comparator and a feedback node, at which the feedback voltage corresponds to a reflection voltage of the inductive device. The constant-current control unit integrates a current-detection signal over the discharge time to control a maximum output current of the switched-mode power supply. |
| US09197132B2 |
Power converter with an adaptive controller and method of operating the same
A controller for a power converter, and method of operating the same. The controller improves power converter operating efficiency by regulating an internal power converter operating characteristic depending on a value of a power converter parameter measured after a manufacturing step, or an environmental parameter, preferably employing a table with entries dependent on the parameter value. The internal operating characteristic may be an internal bus voltage, a voltage level of a drive signal for a power switch, a number of paralleled power switches selectively enabled to conduct, or a basic switching frequency of the power converter. The controller may regulate an internal operating characteristic of the power converter using a functional relationship dependent on the parameter value. The environmental parameter may be received as a signal from an external source. The parameter measured after a manufacturing step may be a parameter measured from representative power converter(s). |
| US09197131B2 |
Voltage sensing in a voltage converter
A method for sensing an output voltage in a voltage converter includes at least one switching element and a transformer. A voltage is sampled across an auxiliary winding or a signal obtained from the voltage across an auxiliary winding in order to obtain a plurality of samples after the at least one switching element has assumed a first operation state and until the auxiliary voltage reaches a predefined threshold. The auxiliary winding is inductively coupled with the transformer. At least one sample obtained is evaluated before the auxiliary voltage reaches the predefined threshold. |
| US09197130B2 |
Regulator device having degradation detection
A regulator device includes: a power input terminal; a power output terminal; a plurality of regulators each including an operating FET and a monitoring FET to be driven together with the operating FET, the plurality of regulators being arranged in parallel between the power input terminal and the power output terminal; and a controller configured to drive the operating FET and the monitoring FET included in one of the regulators, when the controller determines whether the monitoring FET included in the one of the regulators have degraded, the controller configured to stop driving the operating FET and the monitoring FET included in the one of the regulators and configured to drive the operating FET and the monitoring FET included in another of the regulators. |
| US09197129B2 |
Boost converter topology for high efficiency and low battery voltage support
A method and apparatus for a boost converter topology for low battery voltage support. In the method, an input voltage is boosted by closing first through third switches and then opening a fourth switch to charge a capacitor. The first and second switches are then opened. The voltage is then doubled by closing the third and fourth switches to discharge the first capacitor into a second capacitor and charging a third capacitor. A further embodiment provides an additional method for selectively boosting an input voltage to an electronic device. The method first characterizes the efficiency of a circuit, and then determines a crossover point for a ratio of output voltage to input voltage, and then enabling or disabling a voltage boost converter based on the crossover point. |
| US09197128B2 |
Apparatus and methods for voltage converter bypass circuits
Apparatus and methods for voltage converter bypass circuits are provided. In one embodiment, a voltage conversion system includes a bypass circuit and a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor. The bypass circuit includes a first p-type field effect transistor, a second p-type field effect transistor, a first n-type field effect transistor, and a second n-type field effect transistor. The first and second n-type field effect transistors are electrically in series between a first end and a second end of the inductor. Additionally, the first and second p-type field effect transistor transistors are electrically connected in series between the first end and the second end of the inductor. |
| US09197123B2 |
Power supplying apparatus having a detectable useful life
There is provided a power supplying apparatus capable of determining whether to be normally operated by detecting whether a capacitor deteriorates with age based on a ripple voltage generated by switching of a primary side, the power supplying apparatus including a power supply unit switching input power to convert the input power into preset direct current (DC) power, a detecting unit setting a reference voltage based on the DC power of the power supply unit and comparing the reference voltage with a ripple voltage included in the DC power to detect a voltage level of the ripple voltage, and a controlling unit determining whether an abnormality has occurred according to a detection result of the detecting unit. |
| US09197122B2 |
Load drive circuit, load drive method, and luminaire
A load drive circuit may include a DC power source configured to provide a DC output voltage for at least one load based on an output voltage of an AC/DC converter, the DC output voltage having a ripple, a variable resistance module connected to the load, a ripple reduction module that generates, based on a reference voltage and a feedback signal from the load, a variable resistance adjusting signal for adjusting the resistance of the variable resistance module so as to reduce a ripple of the load current, wherein the reference voltage is generated based on the DC output voltage, and a reference voltage adjusting module that adjusts the average value of the reference voltage based on the variable resistance adjusting signal, so as to make the average value of the reference voltage approach the average value of the feedback signal as much as possible. |
| US09197119B2 |
Permanent magnet motor and washing machine provided therewith
A permanent magnet motor includes a rotor including a rotor core formed with magnet insertion holes and permanent magnets inserted into the insertion holes. The rotor core includes a plurality of pairs of divided cores. The divided cores of each pair are adjacent to each other, and one divided core of each pair has two ends formed with respective engagement convexities and the other divided core has two ends formed with respective engagement concavities. The permanent magnets included permanent magnets having a lower coercive force and permanent magnets having a higher coercive force. A number of the permanent magnets having the lower coercive force and a number of the permanent magnets having the higher coercive force for each of the divided cores are the same as the other divided cores such that the divided cores have an equal total flux such that the divided cores have an equal total flux. |
| US09197118B2 |
Synchronous rotary electric machine having a hybrid-excitation rotor
A machine (1) having a rotor (11) including permanent magnets (PM) and field coils (EC). The magnets are housed in first axial recesses (E1) distributed within a circumferential portion of the magnetic body, thus defining circumferential polar sections. The coils are housed in second axial recesses (E2) distributed within an intermediate portion of the magnetic body and defining pole teeth (RT). The ratio of a width of a pole tooth to a height of a permanent magnet is around 0.65 to around 1. |
| US09197116B2 |
Annular rotor for an electric machine
The invention relates to an annular rotor having a hollow shaft for an electric machine. In order to allow transport of such a machine, particularly for a very large model, the rotor is divided in the circumferential direction into a plurality of partial annular rotor segments (1). The rotor further comprises a hollow shaft, wherein the closed ring shape of the rotor can be broken by separating the rotor segments (1) from each other. |
| US09197110B2 |
Electrostatic stabilizer for a passive magnetic bearing system
Electrostatic stabilizers are provided for passive bearing systems composed of annular magnets having a net positive stiffness against radial displacements and that have a negative stiffness for vertical displacements, resulting in a vertical instability. Further embodiments are shown of a radial electrostatic stabilizer geometry (using circuitry similar to that employed in the vertical stabilizer). This version is suitable for stabilizing radial (lateral) displacements of a rotor that is levitated by annular permanent magnets that are stable against vertical displacements but are unstable against radial displacements. |
| US09197109B2 |
Electric motor configured for facilitated washability
An electric motor having a casing positioned between a head end cap and a tail end cap is provided. An output shaft passes through the head end cap and the tail end cap and a cooling fan is mounted for rotation relative to the output shaft. The electric motor includes a fluid distribution chamber adjacent the tail end cap, an inlet port for supply of fluid to the chamber, and a plurality of discharge apertures for distributing fluid from the chamber toward the cooling fan. The fluid distribution chamber facilitates the washing and cleaning of the electric motor. |
| US09197104B2 |
Venting device for electric machine
A venting device to define a venting pathway between adjacent stacked laminations of a stator assembly of an electric machine is provided. The venting device comprises a first mesh plate and a second mesh plate. The first mesh plate includes a set of angled first slats and a set of first interconnecting members connecting adjacent first slats. The second mesh plate includes a set of angled second slats and a set of second interconnecting members. The set of angled second slats are disposed above the set of first slats. The set of second interconnecting members connect adjacent second slats and are positioned offset from the set of first interconnecting members. |
| US09197099B2 |
Power supply system comprising a fuel cell
A power supply system driving a load including a main power apparatus and a backup power apparatus is disclosed. The main power apparatus provides main power to the load according to city power. The backup power apparatus provides backup power to the load when the city power does not correspond to a first pre-determined condition and includes a recombination unit, a fuel cell unit, a transformation unit, and a control unit. The recombination unit recombines a methanol component to a hydrogen component. The fuel cell unit receives the hydrogen component to generate a first power. The transformation unit detects the city power and transforms the first power to generate the backup power. When the city power does not correspond to a first pre-determined condition, the control unit activates the reformer, the fuel cell unit, and the transformation unit to generate the backup power. |
| US09197097B2 |
Temperature-controlled power supply system and method
A temperature-controlled power supply system is disclosed. The temperature-controlled power supply system comprises a power source, for supplying input power; a rechargeable battery module, for receiving the input power for power storage; a charging unit, coupled between the power source and the rechargeable battery module, for charging the rechargeable battery module with the input power; a temperature sensing unit, coupled to the rechargeable battery module, for sensing a temperature of the rechargeable battery module; and a current control unit, coupled to the temperature sensing unit and the charging unit, for controlling a current for charging the rechargeable battery module according to the temperature of the rechargeable battery module. |
| US09197095B2 |
Wireless power charging apparatus and method of charging the apparatus
A wireless power charging apparatus and method are provided, which recognizes location information of at least one wireless power receiving apparatus; selects at least one of at least one wireless power transmitter that supplies power to the at least one wireless power receiving apparatus based on the location information; and supplies power to the at least one wireless power receiving apparatus through the at least one selected wireless power transmitter. |
| US09197087B2 |
Portable charger with rotatable locking portions
A portable electrical power source configured to provide power for a portable electronic device includes a base, a chargeable battery, a connector, and at least one locking structure. The base includes a first surface and a second surface facing away from the first surface. The base defines a receiving room between the first surface and the second surface and at least one cavity. The chargeable battery is received in the receiving room. The locking structures are rotatably received in the cavities to lock the portable electronic device onto the first surface of the base. The connector is positioned on the first surface and is electrically connected to the chargeable battery and the portable electronic device. The chargeable battery charges the portable electronic device through the connector. |
| US09197084B2 |
Charge controller with protective function and battery pack
A charge controller includes a charge control circuit that, when detecting that a charging power supply is connected, controls the charging transistor to apply the charge current; a first and second control switch element connected in series between one terminal of a secondary battery and an external terminal; and a protection circuit that, when the secondary battery is over-discharged, turns off the first control switch element to stop discharge current and when deeply discharged, turns off the second control switch element. The protection circuit sends a charge inhibit signal to the charge control circuit when the secondary battery is deeply discharged, and while receiving the charge inhibit signal, the charge control circuit keeps the charging transistor off to prevent the charge current from flowing even if detecting that the charging power supply is connected. |
| US09197083B2 |
Electronic apparatus, control method, and recording medium
There is provided an electronic apparatus that can properly control a power state of an electronic apparatus by using a temperature of a battery pack. The electronic apparatus detects a temperature of a battery pack and a remaining capacity of the battery pack. If the temperature of the battery pack is less than or equal to a predetermined temperature, the electronic apparatus performs process for turning a power state of the electronic apparatus from ON to OFF based on the remaining capacity of the battery pack. |
| US09197072B2 |
Charging device including a housing recess
A charging device charges an in-vehicle battery for an electric vehicle by a power supply fed from an attachment plug extending from an external power supply. The charging device includes: a charging inlet; a housing recess formed within the charging inlet; a charging connector disposed within the housing recess; and an illumination light source embedded in an upper peripheral wall of the housing recess. The illumination light source emits light downward, and an optical axis thereof is positioned closer to an opening of the housing recess than a front surface of the charging connector. A first irradiation light emitted toward the opening of the housing recess than the optical axis is emitted obliquely downward from the charging inlet. A second irradiation light emitted toward a bottom of the housing recess than the optical axis is emitted to the charging connector. |
| US09197071B2 |
Energy storage system for supplying power to loads of a drilling rig
A system for supplying power to a drilling rig has an engine/generator with an output line so as to transfer power therefrom, an energy storage system connected to the engine/generator, and a load connected to the energy storage system such that power from the energy storage system is directly transferred to the load and such that power from the engine/generator is electrically isolated from the load. The engine/generator has a capacity greater than an maximum power requirement of the load. The energy storage system can include at least one battery. |
| US09197069B2 |
Power transmission systems
An offshore wind farm includes a plurality of wind turbines connected to an onshore converter station by means of a distributed power transmission system. The power transmission system includes a series of offshore converter platforms distributed within the wind farm. Each converter platform includes a busbar carrying an ac voltage for the converter platform and to which the wind turbines are connected. Each converter platform also includes one or more converter transformers connected to the busbar and a series of one or more converter modules. The power transmission system includes dc transmission lines which deliver generated power back to the onshore converter station. |
| US09197068B2 |
Coordinated control of multi-terminal HVDC systems
Multi-terminal HVDC systems and control methods therefore are disclosed. Methods for controlling multi-terminal HVDC systems having a plurality of converter stations may include receiving a plurality of measurements from a plurality of measurement units disposed on the HVDC system, identifying from the measurements a disruption within the HVDC system, monitoring the measurements to identify a steady-state disrupted condition for the HVDC system, calculating a new set point for at least one of the plurality of converter stations, which new set point may be based on the steady-state disrupted condition and the measurements, and transmitting the new set point to the at least one of the plurality of converter stations. In some examples, the HVDC systems may include an HVDC grid interconnecting the plurality of converter stations and a controller communicatively linked to the plurality of measurement units and the plurality of converter stations. |
| US09197067B2 |
Electric power supply-and-demand control system, electric power management apparatus, and electric power supply-and-demand control method
An electric power supply-and-demand control system includes a memory unit, an estimation unit, a first calculation unit, and a second calculation unit. The system is capable of transmitting/receiving data to/from a power management apparatus provided to each of consumers to instruct a power management apparatus to adjust electric power. The memory unit memorizes a supply, consumptions, reserve power, and response results. The estimation unit estimates a response speed on the basis of the response results. The first calculation unit calculates a target value which allows it to eliminate an unbalance between the supply and a demand. The demand is given as a total of the consumptions. The second calculation unit calculates second adjustment amounts so that a total of the second adjustment amounts approaches the target value and is in the range. |
| US09197061B2 |
Electrostatic discharge clamping devices with tracing circuitry
Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described. |
| US09197060B2 |
Inductive fault current limiter with divided primary coil configuration
An inductive fault current limiter (1) has a normally conducting primary coil assembly (2) with a multiplicity of turns (3) and a superconducting, short-circuited secondary coil assembly (4), wherein the primary coil assembly (2) and the secondary coil assembly (4) are at least substantially coaxial with respect to each other and at least partially interleaved in each other. The primary coil assembly (2) has a first coil section (2a) and a second coil section (2b), wherein the turns (3) of the first coil section (2a) of the primary coil assembly (2) are disposed radially inside the secondary coil assembly (4) and the turns (3) of the second coil section (2b) of the primary coil assembly (2) are disposed radially outside the secondary coil assembly (4). The fault current limiter has an increased inductance ratio. |
| US09197059B2 |
Near field RF communicators having refined energy sharing characteristics utilizing improved shunt current control
A near field RF communicator has an inductive coupler to enable inductive coupling with a magnetic field of an RF signal; a rectifier to rectify an AC voltage derived from an RF signal inductively coupled to the inductive coupler; and a regulator to regulate a voltage derived from an RF signal inductively coupled to the inductive coupler, the regulator having a voltage-controlled impedance and a regulator controller to provide a control voltage for the voltage controlled impedance and to vary the control voltage in dependence upon a current flowing through the voltage controlled impedance. To prevent the voltage regulator from drawing excess current and energy from an RF field in which the communicator is present the voltage regulator is controlled to provide a chosen impedance characteristic. |
| US09197054B2 |
Circuit for controlling a latch mode of a pulse width modulation circuit and method thereof
A circuit for controlling a latch mode of a pulse width modulation circuit includes a D flip-flop, a voltage generation unit, a comparator, and a logic unit. The D flip-flop generates a switch control signal according to a latch enable signal. The voltage generation unit generates a discharge current, and a voltage divider resistor group included in the voltage generation unit generates a first voltage when the voltage generation unit is turned on according to the switch control signal. A voltage of a predetermined pin of the pulse width modulation circuit is equal to a predetermined voltage when the discharge current is equal to the charge current. The comparator compares a reference voltage with the first voltage to generate a comparison signal. The logic unit generates a clear signal according to the comparison signal. The D flip-flop clears the switch control signal according to the clear signal. |
| US09197050B2 |
End-fitting for routing cables within vehicles
An end-fitting assembly for routing a cable on a vehicle chassis in a predetermined direction. The assembly includes a mounting element and end-fitting element. The mounting element includes a mounting portion, attached to the vehicle chassis, and a flange portion, having a mounting aperture with a keyway formed in the mounting aperture periphery. The end-fitting element is generally tubular in form and sized to engage the mounting aperture, and it includes a retainer element on the end-fitting, adapted to engage the mounting aperture; a locking assembly, including a key adapted to engage the keyway; and a directional tube, extending from the mounting element in the pre-determined direction, adapted to carry the cable. |
| US09197037B1 |
Spark plug
A spark plug includes a portion from a position at a distance of 0.1 mm from a base end to a distal end that is categorizable into a high hardness portion and a low hardness portion using a hardness distribution of a ground electrode, the high hardness portion being a portion from the position at a distance of 0.1 mm from a base end to a position at a distance of 0.1×n (mm) from a base end, the low hardness portion being a portion from a position at a distance of 0.1×(n+1) (mm) from the base end to the distal end, where “n” is a natural number. The low hardness portion includes a portion that has a largest curvature in the ground electrode. A highest hardness of the low hardness portion is lower than a lowest hardness of the high hardness portion. |
| US09197035B2 |
Semiconductor laser device and manufacturing method thereof
A semiconductor laser device includes an n-type clad layer, a first p-type clad layer and a ridge stripe. The device also includes an active layer interposed between the n-type clad layer and the first p-type clad layer, and a current-blocking layer formed on side surfaces of the ridge stripe. The ridge stripe of the device includes a second p-type clad layer formed into a ridge stripe shape on the opposite surface of the first p-type clad layer from the n-type clad layer. The ridge stripe is formed such that a first ridge width as the width of a surface of the second p-type clad layer exists on the same side as the first p-type clad layer and a second ridge width as the width of a surface of the second p-type clad layer exists on the opposite side from the first p-type clad layer. |
| US09197032B2 |
Systems and methods for stabilized stimulated brillouin scattering lasers with ultra-low phase noise
Systems and methods for stabilized stimulated Brillouin scattering lasers with ultra-low phase noise are provided. In one embodiment, a method for producing a Stimulated Brillouin Scattering (SBS) beam comprises: generating laser light from a tunable laser source; splitting the laser light into a first light beam and a second light beam; creating a phase modulated light beam by applying a phase modulation to the first light beam; locking a frequency of the laser light to a frequency of a ring cavity using the phase modulated light beam and a Pound-Drever-Hall servo loop coupled to the tunable laser source; coupling the second light beam into the ring cavity in a direction of travel opposite to that of the phase modulated light beam; generating a Stimulated Brillouin Scattering light beam in the ring cavity from the second light beam; and outputting the Stimulated Brillouin Scattering light beam. |
| US09197029B2 |
Mode control waveguide-type laser device
In a laser device, a control range of focal distance of a generated thermal lens is broadened and reliability is improved. A mode control waveguide-type laser device includes: a planar laser medium having a waveguide structure in a thickness direction of a cross section perpendicular to an optical axis, for generating gain with respect to laser light; a cladding bonded onto the laser medium; and a heat sink bonded onto the laser medium. The laser medium generates a lens effect, and the laser light oscillates in a waveguide mode in the thickness direction, and oscillates in a spatial mode due to the lens effect in a direction perpendicular to the optical axis and the thickness direction. The refractive index distribution within the laser medium is created by generating a temperature distribution in the laser medium depending on a junction area of the cladding and the heat sink. |
| US09197028B2 |
Laser tube with baffles
The tube includes a first electrode having a first electrode inner surface and a second electrode having a second electrode inner surface. The first electrode is separated, in a first transverse direction, from the second electrode thereby defining a gap region having a gap thickness between the first electrode inner surface and the second electrode inner surface. The tube further includes a first and a second elongated baffle member, each having a respective elongated central channel formed in an inner surface thereof. |
| US09197021B2 |
Micro SIM card socket
The micro SIM card socket of the Present Disclosure, by manufacturing the contact terminals in a “U” shape, can resolve the problem of narrowing contact terminal installation space due to miniaturization trends, and also the problem of collision between the card front end and the contact terminals when a card is inserted; it can effectively prevent the malfunction or poor contact that can occur due to the inability of the contact terminals to firmly contact the connection terminals of the SIM card when the SIM card is inserted. |
| US09197016B2 |
Self-ejectable port fixing device
The present invention provides a self-ejectable port fixing device for contact connecting with a port having a port chip. The port fixing device comprises a casing having an opening through which the port chip is allowed to insert and to contact with a receptacle chip provided in the casing. The port fixing device further comprises an elastic unit and a locking unit. The elastic unit is compressed directly or indirectly by the port so as to accumulate elastic potential energy while the port chip is getting closer to the receptacle chip. When the port chip is in contact with the receptacle chip, the locking unit locks the port chip at this contacting position. When the locking unit is unlocked, the elastic unit releases the elastic potential energy to push the port chip to be detached from the receptacle chip. |
| US09197015B2 |
Connector
A connector includes a spring portion, a lock member and a movable member. When the movable member is forced to be moved from a non-operation position to an operation position, an operation portion of the movable member operates an operated portion of the lock member to move a lock portion of the lock member from a lock position to an unlock position. When the movable member is held at the operation position, a front end of the spring portion presses a pressed portion of the movable member to move the movable member towards the non-operation position. When the movable member is released, the movable member is moved back from the operation position to the non-operation position so that the operation portion stops to operate the operated portion to move the lock portion back to the lock position. |
| US09197014B2 |
Electrical connector module
An electrical connector module, includes a first connecting part and a second connecting part. The first connecting part includes a main body and a pair of protrusion portions. The second connecting part includes a base seat, a receiving portion on the base body; and a pair of latching assemblies. The latching assembly includes a pair of first blocking members, a pair of second blocking members and a latching member. The latching member is located between the pair of first blocking members and the pair of second blocking members. The latching member includes a base body, a latching portion protruding from the base body, and a pair of cam portions on the base body, each cam portion is rotatably retained between one first blocking member and one second blocking member. |
| US09197011B2 |
Connectors providing haptic feedback
A first connector may include a housing defining a first connector face to be positioned in a first position or a second position proximate to a second connector face of a second connector. A first extremely high frequency (EHF) communication unit may be disposed in the housing for communicating with a second EHF communication unit of the second connector when the first connector face is positioned in first or second position relative to the second connector face. A first magnet may be disposed in the housing. The first magnet may align with and repel a second magnet disposed relative to the second connector face when the first connector face is positioned in the second position. The first magnet may be configured not to align with and not to repel the second magnet when first connector face is positioned in the first position relative to the second connector face. |
| US09197003B2 |
Connector and coating member used for the same
A connector includes a housing formed with a plurality of terminal insertion holes into which a plurality of terminal metal fittings is inserted, respectively, and a spacer arranged inside the housing and coating the plurality of terminal metal fittings. The spacer includes main bodies fixed inside the housing, and a plurality of slit doors provided in the main bodies and divided into a plurality of small pieces by a plurality of slits. Each of the slit doors elastically deforms by abutting a terminal metal fitting inserted into a terminal insertion hole when the terminal metal fitting passes therethrough, and is brought into contact with the terminal metal fitting when the terminal metal fitting is attached to the housing. |
| US09197002B2 |
Connector supporting structure and connector-equipped electronic device
A connector supporting structure includes a substrate, a connector mounted on the substrate, and a casing covering at least a portion of the substrate and supporting the connector. The casing includes an opening to expose a part of the connector from an inside of the casing to an outside. Side surfaces of the connector are pressed by inner surfaces of the opening. |
| US09197001B2 |
Stackable clamping carrier elements for flat assemblies
A clamping carrier element for flat assemblies includes a housing. In at least one embodiment, the clamping carrier element is configured on the upper face of the housing in such a manner that a plurality of clamping carrier elements can be stacked one above the other via a connection technique. |
| US09197000B2 |
SIM card holder, mobile terminal and method for identifying hotplug of SIM card
The disclosure provides a subscriber identity module (SIM) card holder, a base of the SIM card holder is provided with SIM card metallic contacts and first fixed metallic pins connected with the metallic contacts; the base of the SIM card holder is further provided with an additional metallic dome; the additional metallic dome is in uncompressed state and in contact with high level when the SIM card is not plugged in the SIM card holder, and is in compressed state and in contact with low level when the SIM card is plugged in the SIM card holder, delivering the high/low level with which it is in contact to a master chip of a mobile terminal to identify the plug-in and pull-out of the SIM card. The disclosure further comprises a mobile terminal and a method of identification of the hot-plug of a SIM card. With the help of the disclosure, problems of complex design, occupation of motherboard space, increased product cost in existing cell phones with hot-plug of SIM cards may be solved. |
| US09196999B2 |
Two-part modular connector and smart managed interconnect link using the two-part modular connector
Embodiments of the present invention are directed to a two-part cable connector. The connector includes two parts that when mate together the outer shape and dimensions of the connector are compatible to an outer shape and dimensions of a cable connector of a known standard. The first connector part terminated at an end of a communication cord and the second connector part detachably connected to the first connector to enable separation of said second part from said first part. The second connector part of the cable connector is insertable into a communication port and comprises an identification number to uniquely identify the communication port. |
| US09196995B2 |
Tamper resistant mechanism for 15 and 20 amp electrical receptacles
A tamper resistant shutter assembly for an electrical device includes a housing. A first shutter member is movably disposed in the housing between closed and open positions. A second shutter member is movably disposed in the housing between closed and open positions. A third shutter member is movably disposed in the housing between closed and open positions. The third shutter member is movable from the closed position to the open position by movement of the second shutter member from the closed position to the open position. A fourth shutter member is movably disposed in the housing between closed and open positions. The fourth shutter member is movable from the closed position to the open position by movement of the first shutter member from the closed position to the open position. A fifth shutter member is movably disposed in the housing between closed and open positions. The fifth shutter member is prevented from moving from the closed position to the open position when the fourth shutter member is in the closed position. |
| US09196994B2 |
Connector mechanism and related electronic device
A connecter mechanism includes a casing, a half socket and a door. The casing includes a first actuating portion, an opening and a pivot hole. The half socket is disposed inside the casing. The door is movably disposed on the casing to cover the half socket. The door includes a body, at least one pivot shaft, a cover and a second actuating portion. The pivot shaft is disposed on a side of the body. The cover is connected to an edge of the body for covering the opening. The second actuating portion is connected to the other edge of the body opposite to the cover. Position of the cover relative to the opening is adjusted via the second actuating portion and the first actuating portion. |
| US09196990B2 |
Apparatuses and methods for a plug connector
A plug connector has a housing and a plurality of metallic plug connections in the housing together with a plurality of contact feet which project from the bottom face of the housing in order to make electrical contact and be mechanically fixed to a support of a heating apparatus which is electrically connected to the plug connector. A contact foot has a U-shaped foot end with two limbs and with a cutout in-between, an upper limb merging with the contact foot, and a lower limb being provided on that side which faces away from the housing. |
| US09196988B2 |
Connector assembly
A connector assembly includes a first connector having a first mounting side that extends along a first plane. The first connector is configured to be mounted to a first circuit board along the first mounting side such that the first circuit board extends approximately parallel to the first plane. A second connector is configured to mate with the first connector. The second connector has a second mounting side that extends along a second plane that extends approximately perpendicular to the first plane. The second connector is configured to be mounted to a second circuit board along the second mounting side such that the second circuit board extends approximately parallel to the second plane. The first and second connectors are configured to move relative to each other along a float axis that extends approximately perpendicular to the second plane when the first and second connectors are mated together. |
| US09196987B2 |
Connector
A connector includes a plug and a receptacle. The plug includes: contacts; a reinforcing plate formed in an elongate plate shape; and locking parts provided at positions projected from opposite side surfaces of a housing in a width direction thereof. The receptacle includes: contacts having the number and positions corresponding to those of the contacts of the plug; and hold-down parts provided at positions projected from respective side surfaces of a housing in a width direction thereof. Each of the hold-down parts has an insertion opening and an internal space into which the locking part of the plug can be inserted in a depth direction of the housing, and a holding part for holding the locking part at a predetermined position. The insertion opening is in communication with the internal space in the depth direction of the housing. |
| US09196985B2 |
Configurable electrical connector assembly
A configurable connector system may include a connector assembly including a housing, and at least one wafer retained within the housing. The wafer(s) may include at least one active device in communication with at least one programmable memory component. The active device(s) may be configured to operate based on programming instructions or settings stored within the programmable memory component. The housing of the connector assembly may include an open programmer-receiving channel configured to receive at least a portion of an external programmer that is configured to send the programming instructions or settings to the at least one programmable memory component. |
| US09196983B2 |
Plug connector for direct contacting on a circuit board
A plug connector for direct electrical contacting of contact surfaces on a circuit board includes at least one electrical end contact of an electric line inserted into the plug connector housing in a plug-in direction and at least one separate electrical contact element, which protrudes elastically beyond one housing side of the plug connector housing transversely to the end contact for electrical contacting of a contact surface of the circuit board and is in electrically conductive contact with the end contact, at least when the contact surface has been contacted. |
| US09196980B2 |
High performance surface mount electrical interconnect with external biased normal force loading
A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. A socket substrate is provided with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are attached to the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pads to electrically and mechanically couple the electrical interconnect to the PCB. |
| US09196976B2 |
Tapered ground strap shield connector
A ground strap shield connection includes a body member disposed between an insulation layer and a ground shield of a first cable. The body member has a first tapered portion and a first threaded portion on an outer surface thereof. A cap member has a second tapered portion and a second threaded portion on an inner surface thereof. The ground shield of the first cable is disposed between the first and second tapered portions of the body member and the cap member when the first and second threaded portions are engaged. A ground strap has a first end connected to the cap member and a second end connectable to another ground strap of another ground strap shield connector connected to a second cable. |
| US09196973B2 |
Solar junction box and wire connecting structure thereof
Disclosed are a solar junction box and a wire connecting structure of the solar junction box. The solar junction box includes plural first conductive tongues separately and perpendicularly plugged onto a printed circuit board, plural solar panel conducting plates combined to the first conductive tongues, and each solar panel conducting plate including an extension plate connected to a solar panel and a U-shaped snap-in plate bent and extended from the extension plate, and each U-shaped snap-in plate being snapped onto each first conductive tongue, plural insulators sheathed on the solar panel conducting plates, a pair of second conductive tongues separately and flatly attached onto a side of the printed circuit board, and two conducting terminals electrically connected to the pair of second conductive tongues. With the installation of the wire connecting structure, the volume of the solar junction box can be reduced to provide a stable electrical connection. |
| US09196972B2 |
Crimp terminal and connector
A crimp terminal includes a crimp barrel to be crimped around a conductive core of a cable. The crimp barrel includes an inner surface which is formed with a plurality of cavities independent of one another. Each of the cavities has a predetermined shape in a plane perpendicular to a depth direction of the cavity. The predetermined shape contains a plurality of straight-line segments. Every one of the straight-line segments of the predetermined shape is not parallel with remaining ones of the straight-line segments of the predetermined shape. The straight-line segments of the predetermined shape includes at least one pair of the straight-line segments, which are closest to each other among the straight-line segments of the predetermined shape and are arranged to make an interior angle less than 90 degrees or, if not intersecting each other, are arranged on two straight lines, respectively, wherein the two straight lines make an interior angle less than 90 degrees. |
| US09196968B2 |
Antenna device
An antenna device includes a first dielectric substrate made of a high dielectric coefficient material, a plurality of first contact pads fastened on a periphery of a top surface of the first dielectric substrate, a plurality of second dielectric substrates made of the high dielectric coefficient material, and a plurality of Yagi-Uda antennae respectively disposed on top surfaces of the second dielectric substrates. The second dielectric substrates are fastened on the first dielectric substrate. Each of the Yagi-Uda antennae has a drive, and a plurality of directors disposed in an outside position of the drive and spaced from an outer side of the drive. The directors are shorter than the drive, and the directors are arranged along a direction of being gradually away from the drive and gradually become shorter. An inner side of the drive defines a signal feed point. |
| US09196966B1 |
Quad-slot antenna for dual band operation
Quad-slot antenna structures of user devices and methods of operating the user devices with the quad-slot antenna structures are described. One apparatus includes a RF feed coupled to a quad-slot antenna, including a first slot and a second slot and a third slot and a fourth slot. The first slot and the second slot are driven elements and the third slot and the fourth slot are parasitic elements. |
| US09196944B2 |
Apparatus for combining high frequency electrical energy from a plurality of sources
A broadband building block portion is provided, which may be used to construct N-way multi-port combiners. The building block portion comprises a first feeding probe that receives a first input signal, a second feeding probe that receives a second input signal, a combining probe that combines the first and second input signals to output a combined signal, and a transmission line coupled to the first and second feeding probes. |
| US09196943B2 |
Microwave filter having an adjustable bandwidth
A microwave filter includes a first adjustable coupling resonator connected via a first coupling iris to an input of the microwave filter, a frequency resonator configured to establish a transmission frequency of the microwave filter and connected to the first adjustable coupling resonator via a second coupling iris, and a second adjustable coupling resonator connected to the frequency resonator via a third coupling iris. |
| US09196939B2 |
Method for thermal management and mitigation of thermal propagation for batteries using a graphene coated polymer barrier substrate
An automotive battery module with one or more battery cells and a heat exchange member placed in thermal communication with the battery cell. Heat generated within the battery cell by, among other things, electric current that can be used to provide motive power for the automobile may be removed by the heat exchange member that is made up of a flexible substrate and one or more graphene layers disposed on the substrate. The construction of the substrate and graphene layer is such that multiple heat transfer paths are established, each defining different levels of thermal conductivity and related transfer of heat away from the battery cells. |
| US09196933B2 |
System and method for discharging a high impedance battery
An electrochemical battery system in one embodiment includes a first electrochemical cell, a memory in which command instructions are stored, and a processor configured to execute the command instructions during a discharge cycle of the first electrochemical cell to (i) establish a first discharge voltage of the first electrochemical cell based upon a first sensed discharge voltage, and (ii) permit a second discharge voltage of the first electrochemical cell after establishing the first discharge voltage, wherein the second discharge voltage is greater than the first discharge voltage. |
| US09196932B2 |
Assembled battery and assembled battery control system
An assembled battery (10) provided by this invention has a plurality of secondary batteries (2) connected in series, and has a first bypass circuit (12) including a Zener diode (6) connected in parallel so that the connection is in the inverse direction during charging with respect to the series connections, and a second bypass circuit (14) including a varistor (4) connected in parallel to the secondary batteries (2) and the Zener diode (6). The Zener voltage of the Zener diode (6) is set to a prescribed first voltage value, and the varistor voltage of the varistor (4) is set to a second voltage value equal to or greater than the first voltage value. |
| US09196928B2 |
Electrolyte solution for rechargeable lithium battery, and rechargeable lithium battery including the same
An electrolyte solution for a rechargeable lithium battery, including a lithium salt, a non-aqueous organic solvent, and an additive including fluoroethylene carbonate, a vinyl-containing carbonate, a substituted or unsubstituted C2 to C10 cyclic sulfate, and a nitrile-based compound represented by the following Chemical Formula 1: wherein, in Chemical Formula 1, R may be a substituted or unsubstituted C1 to C20 alkylene group. |
| US09196926B2 |
Gel electrolyte for lithium ion secondary battery, and lithium ion secondary battery
An object of the present invention is to provide a gel electrolyte for a lithium ion secondary battery having flame retardancy over a long period and a good capacity maintenance rate. The gel electrolyte for a lithium ion secondary battery according to the exemplary embodiment contains a lithium salt, a copolymer of at least one first monomer selected from compounds represented by chemical formulae (1) and (2) and a second monomer represented by chemical formula (4), at least one oxo-acid ester derivative of phosphorus selected from compounds represented by chemical formulae (5) to (7), and at least one disulfonate ester selected from a cyclic-chain type disulfonate ester represented by chemical formula (8) and a linear-chain type disulfonate ester represented by chemical formula (9). |
| US09196925B2 |
Glass particles
Glass particles including Li, P and S, wherein when a Raman spectrum of the glass particles is measured five times or more and a peak at 330 to 450 cm−1 in the Raman spectrum is separated into peaks of components by waveform separation, the standard deviation of the area ratio of each of the peaks of the components is 3.0 or less, the area of the peak of PS43− component obtained by the waveform separation is 10 to 95% of the total area, and the area of P2S74− component obtained by the waveform separation is 5 to 45% of the total area, and the area of the peak of PS43− component is larger than the area of the peak of P2S74− component. |
| US09196924B2 |
Solid electrolyte material, lithium battery, and method of producing solid electrolyte material
A main object of the present invention is to provide a solid electrolyte material having excellent Li ion conductivity. To attain the object, the present invention provides a solid electrolyte material represented by a general formula: Lix(La2−aM1a)(Ti3−bM2b)O9+δ, characterized in that “x” is 0 |
| US09196922B2 |
Lithium secondary battery of improved high-temperature cycle life characteristics
Disclosed is a lithium secondary battery comprising a cathode including a lithium-containing transition metal oxide, an anode including a carbon-based material, and a non-aqueous electrolyte with addition of a compound (A) and a compound (B) of formula (1). Incorporation of the compounds (A) and (B) into the electrolyte significantly improves the high-temperature performance and cycle life characteristics of the battery. |
| US09196921B2 |
Method of producing lithium ion secondary battery, and lithium ion secondary battery
A method of producing a lithium ion secondary battery includes: selecting a positive electrode active material that has a prescribed specific surface area, and preparing a nonaqueous electrolyte solution that contains a compound with a following formula (1) at a prescribed concentration. In an xy-coordinate plane that gives a relationship between a specific surface area x [m2/g] of the positive electrode active material and a concentration y [mol/kg] of the compound in the nonaqueous electrolyte solution, a combination of the prescribed specific surface area and the prescribed concentration corresponds to a combination of values that lies within a hexagonal inner region formed by connecting 6 points (x, y)=(0.80, 0.035), (2.20, 0.05), (2.60, 0.10), (2.60, 0.16), (0.80, 0.16), and (0.50, 0.10) in this sequence with straight lines. |
| US09196918B2 |
Cable-type secondary battery
A cable-type secondary battery, includes an electrode assembly including first and second polarity electrodes with a thin and long shape, each electrode having a current collector whose cross-section perpendicular to its longitudinal direction is a circular, asymmetrical oval or polygonal shape, and an electrode active material applied onto the surface of the current collector, and a separator or an electrolyte layer interposed between the first and second polarity electrodes; and a cover member surrounding the electrode assembly. Also, the cable-type secondary battery is provided with a first polarity terminal and a second polarity terminal connected to the first polarity electrode and the second polarity electrode, respectively, at the end of the cable-type secondary battery; and a housing cap configured to fix the first and second polarity terminals and cover the end of the cable-type secondary battery. |
| US09196915B2 |
Methods and systems for controlling power output of a fuel cell
A fuel cell system and a control method therefor are provided. The fuel cell system includes: a fuel cell formed of a plurality of stacked power generating elements; a cell voltage measuring unit detecting negative voltage in any one of the power generating elements; a control unit controlling electric power output from the fuel cell; and an accumulated current value measuring unit measuring an accumulated current value obtained by time integration of current output from the fuel cell. The control unit prestores a correlation between accumulated current values and current densities that are allowable for the fuel cell in a period during which negative voltage is generated. When negative voltage has been detected, the control unit executes output restricting process of restricting electric power output from the fuel cell so as to fall within an operation allowable range defined by the accumulated current values and current densities of the correlation. |
| US09196913B2 |
Multiple transition flow field and method
A fuel cell includes a membrane electrode assembly having an anode side and a cathode side, a first gas diffusion layer adjacent the cathode side of the membrane electrode assembly, and a first flow field plate contacting the first gas diffusion layer. The first flow field plate includes a reactant inlet, a reactant outlet, and a plurality of flow field chambers separated from one another by at least one rib. The reactant inlet is separated from the plurality of flow field chambers by at least one rib and the reactant outlet is separated from the plurality of flow field chambers by at least one rib. The ribs are configured to force a reactant flowing from the reactant inlet to the reactant outlet to enter the first gas diffusion layer at least twice. |
| US09196912B2 |
Epoxy methacrylate based adhesive for fuel cell flow field plates
An electrically conductive adhesive is disclosed for bonding anode and cathode flow field plates together for use in fuel cells. The adhesive formulation comprises epoxy methacrylate resin and non-fibrous carbon particles but little to no carbon fibres. The adhesive provides suitable strength, bond gap, conductivity and other properties, particularly for flow field plates made of flexible graphite, carbon, or metal. |
| US09196911B2 |
Fuel cell gas diffusion layer integrated gasket
A gas diffusion layer-integrated gasket 1 includes a first gasket 12 which is integrally molded to a periphery of a first gas diffusion layer 11 and a second gasket 14 which is integrally molded to a periphery of a second gas diffusion layer 13, and a hinge part 15 which connects the first gasket 12 and second gasket 14 to each other. The first and second gas diffusion layers sandwich a membrane-electrode assembly 2 in which catalytic electrode layers are provided on both surfaces of an electrolytic membrane from both sides, wherein a seal protrusion 12c is formed on a surface which is in tight contact with the membrane-electrode assembly 2. |
| US09196909B2 |
Fuel cell interconnect heat treatment method
Methods for fabricating an interconnect for a fuel cell stack include placing a compressed metal powder interconnect on a porous support, and sintering the interconnect in the presence of a non-oxidizing gas. The method may further include placing the sintered interconnect on a porous support, and oxidizing the interconnect in the presence of flowing air, or placing the sintered interconnect on a dense, non-porous support, and oxidizing the interconnect in the presence of a gas comprising pure oxygen or an oxygen/inert gas mixture that is substantially nitrogen-free. |
| US09196908B2 |
Fuel cell
A fuel cell includes at least one fuel cell element, which includes an anode, a cathode, a proton exchange membrane sandwiched between the anode and the cathode, a first flow guide plate, and a second flow guide plate. Each of the anode and the cathode includes a catalyst layer including a number of tube carriers having electron conductibility, a number of catalyst particles uniformly adsorbed on an inner wall of each of the tube carriers, and a proton conductor filled in each of the plurality of tube carriers. A first end of each of the tube carriers connects with the proton exchange membrane. The first flow guide plate is disposed on a surface of the anode away from the proton exchange membrane. The second flow guide plate is disposed on a surface of the cathode away from the proton exchange membrane. |
| US09196907B2 |
Air electrode for metal-air battery, membrane/air electrode assembly for a metal-air battery having such air electrode, and metal-air battery
An air electrode (6) for a metal-air battery includes an air electrode catalyst, an electrolyte for air electrodes and a; conductive material. The electrolyte for air electrodes contains a layered double hydroxide. |
| US09196906B2 |
Power storage device and method for manufacturing the same
A power storage device is reduced in weight. A metal sheet serving as a negative electrode current collector is separated and another negative electrode current collector is formed. For example, through the step of forming silicon serving as a negative electrode active material layer over a titanium sheet and then performing heating, the titanium sheet can be separated. Then, another negative electrode current collector with a thickness of more than or equal to 10 nm and less than or equal to 1 μm is formed. Thus, light weight of the power storage device can be achieved. |
| US09196902B2 |
Phosphate- and silicate-based electrode materials, more particularly for lithium ion batteries and lithium capacitors
The invention relates to the use of new crystalline phosphate- and silicate-based electrode materials, preferably having a hopeite or zeolite lattice structure, which are suitable more particularly for lithium ion batteries and lithium capacitors based on non-aqueous systems. The structure of the inventively used electrode material comprises at least a) 2 to 193 atom % of structure-forming ions M in the form of a lattice structure comprising (MX4)n− coordination polyhedra, where M is selected from one or more elements from groups 2-15, b) 8 to 772 atom % of anions X in the form of a lattice structure comprising (MX4)n− coordination polyhedra, where n=a number from 2-4, X is selected from one or more elements from groups 16 and 17, preferably oxygen, and a fraction of up to 25.01% of the anions X may be replaced by a halide ion such as F− or Cl− or by OH−, c) 0 to 5 atom % of immobile, structure-forming cations of one or more elements from groups 3-13 of the Periodic Table, and d>0 to 46 atom % of mobile cations selected from elements from group 1 or group 11 of the Periodic Table, the structure having at least one channel which is free or is filled wholly or partly with one or more species of the mobile cations and which passes through the unit cell of the structure. |
| US09196900B2 |
Substrate and secondary battery
According to one embodiment, a substrate includes a semiconductor layer. The semiconductor layer comprises tungsten oxide particles having a first peak in a range of 268 to 274 cm−1, a second peak in a range of 630 to 720 cm−1, and a third peak in a range of 800 to 810 cm−1 in Raman spectroscopic analysis. The semiconductor layer has a thickness of 1 μm or more. The semiconductor layer has a porosity of 20 to 80 vol %. |
| US09196897B2 |
Secondary battery porous electrode
An electrode having excellent charge/discharge cycle characteristics and which is capable of improving a secondary battery capacity. An electrode is formed on the surface of a collector as an assembly of multiple porous domain structures that are apart from each other, the porous domain structures each having a polygonal shape without an acute angle in a planar view, the polygonal shape having a maximum diameter of 120 μm or less. |
| US09196893B2 |
Secondary battery
A secondary battery including: a case including an accommodation space therein; an electrode assembly housed in the case, the electrode assembly including a coating portion, a first electrode including a first non-coating portion, and a second electrode including a second non-coating portion; a short circuit induction member electrically connected to at least one of the first or second non-coating portions; and a cap plate sealing the case, the short circuit induction member including a contact maintaining part extending along a longitudinal direction of the electrode assembly. |
| US09196892B2 |
Rechargeable battery
A rechargeable battery includes: an electrode assembly configured to perform charging and discharging; a case enclosing the electrode assembly; a cap plate coupled to an opening of the case; an electrode terminal engaging a terminal hole of the cap plate; and an insulator between the cap plate and the electrode terminal, wherein the insulator comprises: a fluid receiving recess at a side of the electrode terminal to receive fluid, and an outlet extending through the insulator from the fluid receiving recess to discharge the received fluid. |
| US09196891B2 |
Electrode structure and battery device manufacturing method
An electrode is provided with a metal terminal extending from a battery module main body, a bolt which has an expanded section configuring a retaining section at a rear end portion and penetrates the metal terminal upward, and an insulating body which insulates the metal terminal and the battery module case one from the other. The insulating body is provided with a drop preventing section which abuts at least a lower surface of the expanded section of the bolt and prevents the bolt from dropping from the metal terminal. |
| US09196889B2 |
Electrode structure and battery device manufacturing method
An electrode is provided with a metal terminal extending from a battery module main body, a bolt which has an expanded section configuring a retaining section at a rear end portion and penetrates the metal terminal upward, and an insulating body which insulates the metal terminal and the battery module case one from the other. The insulating body is provided with a drop preventing section which abuts at least a lower surface of the expanded section of the bolt and prevents the bolt from dropping from the metal terminal. |
| US09196888B2 |
Rechargeable battery
A rechargeable battery having a plurality of electrode assemblies, a first current collecting plate disposed at one side of the plurality of electrode assemblies, a second current collecting plate disposed at an opposite side of the plurality of the electrode assemblies, the first and second current collecting plates being electrically connected with the electrode assemblies. Each one of the first and second current collecting plates having a plurality of current collecting portions fixed to and electrically connected to the electrode assemblies, a connection portion electrically connecting at least two of the current collecting portions, and an insulating supporter supporting the current collecting portions and the connection portion by surrounding the current collecting portions and the connection portion. The insulating supporter includes a plurality of openings exposing the plurality of current collecting portions. |
| US09196884B2 |
Separator for lithium secondary battery and lithium secondary battery comprising the same
Disclosed is a separator for a lithium secondary battery and a lithium secondary battery comprising the same. The separator may include a thermoplastic polyolefin-based polymer porous sheet and an aramid-based non-woven fabric sheet stacked on at least one surface of the polyolefin-based polymer porous sheet, wherein the polyolefin-based polymer sheet and the aramid-based non-woven fabric sheet are adhered with an adhesive, and the adhesive loses an adhesive performance at 80° C. or more to separate the two sheets. The separator has a shut-down function and excellent high-temperature shape stability. |
| US09196883B2 |
Battery module
A battery module including a battery array including: a plurality of battery cells, each including a first surface at a first end of the battery cell; an electrode terminal at the first end; a second surface at a second end of the battery cell opposite the first end; and a side surface extending between the first and second ends, the second surfaces of first and second battery cells of the plurality of battery cells facing each other. |
| US09196881B2 |
Battery pack for use with a power tool and a non-motorized sensing tool
A system includes a power tool having a motor, a drive mechanism mechanically coupled to the motor, and an output element mechanically coupled to the drive mechanism. The motor is operable to drive the drive mechanism and the output element. The system also includes a non-motorized sensing tool having a printed circuit board and a sensing element electrically coupled to the printed circuit board. The sensing element is operable to detect an external characteristic and output a signal to the circuit board. The circuit board is operable to condition the signal into a human-comprehensible form. The system further includes a rechargeable battery pack removably and independently coupled to the power tool and the non-motorized sensing tool to power the motor to drive the drive mechanism and the output element when connected to the power tool and the circuit board and the sensing element when connected to the non-motorized sensing tool. |
| US09196880B2 |
Battery module with offset battery cells
A battery module including a plurality of battery cells, the battery cells being stacked along a first direction, wherein the battery cells are alternately offset in a second direction, the second direction being perpendicular to the first direction. |
| US09196878B2 |
Stackable cartridge module design
A battery assembly includes a plurality of stacked battery cartridges. Each battery cartridge includes a first receptacle unit, a battery cell stack, and a second receptacle unit positioned within first receptacle unit. The battery cell stack includes a first battery cell, a second battery cell, and a foam layer interposed between the first battery cell and the second battery cell. The battery cell stack is positioned within the first receptacle unit, with the second receptacle unit compressing the battery cell stack. The battery module assembly also includes a receiving assembly that holds the plurality of battery cartridges. |
| US09196876B2 |
Touch screen integrated organic light emitting display device and method for fabricating the same
Disclosed are a touch screen integrated organic light emitting display device which has a thin profile and is implemented in a flexible type and a method for fabricating the same. The touch screen integrated organic light emitting display device includes a film substrate, a first etch stopper layer and a first buffer layer sequentially formed on the film substrate, a thin film transistor array including thin film transistors formed on the first buffer layer, organic light emitting diodes connected to the thin film transistors, a passivation layer covering the thin film transistor array and the organic light emitting diodes, a touch electrode layer contacting the passivation layer, a second buffer layer and a second etch stopper layer sequentially formed on the touch electrode layer, and a polarizing plate formed on the second etch stopper layer. |
| US09196875B2 |
Manufacturing method for organic EL lighting device
Anodes of a plurality of organic EL elements are connected together. A forward bias voltage relative to the potential of anodes and a reverse bias voltage are alternately applied to cathodes of the plurality of organic EL elements at a predetermined period. The ratio of the time for which the reverse bias voltage is applied and the time for which the forward bias voltage is applied is increased. |
| US09196874B2 |
Structuring of OLEDs using stack modification layer comprising perfluorinated vacuum grease and/or perfluorinated vacuum pump oil
The invention relates to a method for manufacturing structured organic electroluminescent light-emitting devices (OLEDs) comprising light-emitting and non-emitting areas and to OLEDs manufactured according to this method comprising the steps of: Providing (P) a substrate (2) covered at least locally with at least one conductive layer as the first electrode (3); Depositing (D-SML) a stack modification layer (4) locally on top of the first electrode (3) to establish first areas (31) covered with the stack modification layer (4) and non-covered second areas (32) adjacent to the first areas (31) forming the desired structured pattern; —Depositing (D-OLS) the organic layer stack (5) comprising at least one organic light-emitting layer (51) on top of the first electrode (3) locally coated with the stack modification layer (4) providing an organic layer stack (5) being separated from the first electrode (3) by the stack modification layer (4) in between the organic layer stack (5) and the first electrode (3) in the first areas (31) and being in direct electrical contract to the first electrode (3) in the second areas (32); and Depositing (D-SE) a conductive metal layer as the second electrode (6) on top of the organic layer stack (5) to finish a functional layer stack (7), wherein the first areas (31) above the stack modification layer (4) remain free of the conductive metal without masking these first areas (31); —Providing an easy, variable and reliable method of a maskless structuring of the functional layer stack of OLED enabling to maintain the same the same deposition processes for the functional layer stack as applied during mask processing. |
| US09196868B2 |
Organic light-emitting device with nano-structured light extraction layer and method of manufacturing the same
An organic light-emitting device is provided comprising a stack of layers including —an electro-optical layer structure (10) having a light emissive surface (12), —a light extraction structure (20) adjacent the light emissive surface, the light extraction structure has a nanostructured layer (22); and a backfill layer (24) comprising a material having a second index of refraction different from the first index of refraction, wherein the backfill layer (24) forms a planarizing layer over the nanostructured layer (22). The light emitting device includes a barrier film that comprises a first and a second inorganic layer (22, 26) and an organic layer (24) arranged between said inorganic layers. The one (22) of the inorganic layers of the barrier film closest to the electro-optical layer structure forms the nanostructured layer and the organic layer (24) between the inorganic layers forms the backfill layer. |
| US09196867B2 |
Organic light emitting display apparatus and manufacturing method thereof
An organic light-emitting display apparatus and a method of manufacturing the same are disclosed. An organic light-emitting display apparatus including a substrate, a display unit on the substrate, an encapsulation substrate on the display unit, a sealing member on an edge of the display unit, the sealing member being for bonding the substrate and the encapsulation substrate together, and a filling material filled between the display unit and the encapsulation substrate is disclosed. The filling material has a non-uniform dispersion of fillers such that an amount of the fillers in a first region closer to the display unit is higher than an amount of the fillers in a second region closer to the encapsulation substrate. |
| US09196866B2 |
Organic optoelectronic device and method for producing an organic optoelectronic device
An organic optoelectronic device has a first substrate, on which a functional layer stack having at least one first electrode, thereabove an organic functional layer and thereabove a second electrode is arranged. A encapsulating arrangement includes a second substrate, on which a connecting material and at least one spacer facing the functional layer stack are applied. The connecting material is arranged between the first and second substrate and mechanically connects the first and second substrate together. The functional layer stack is enclosed by the connecting material in a frame-like manner. At least one of the first and second electrode includes at least one opening, above which the at least one spacer is arranged and which has a larger lateral dimension that the spacer. |
| US09196861B2 |
Method of manufacturing organic EL element and organic EL element
An organic EL element is provided having a pair of electrodes and an organic functional layer disposed therebetween, the pair of electrodes consisting of an upper electrode and a lower electrode. In the pair of electrodes, the upper electrode includes a first layer and a second layer, the first layer being in contact with the organic functional layer and the second layer being in contact with the first layer. Additionally, the first layer has a higher membrane stress than the organic functional layer and the second layer. Furthermore, the first layer has a crystalline structure and the second layer has a non-crystalline structure. |
| US09196860B2 |
Compounds for triplet-triplet annihilation upconversion
Novel compounds, and in particular, a dendritic system for improved triple-triplet annihilation upconversion (TTA-UC) are provided. The core of the dendrimer compound includes a metal complex, and on the peripheral, multiple acceptor moieties are covalently linked to the core through a spacer. Consequently, a high efficiency TTA-UC system in both solution and solid state is provided, with particularly high efficiency in the solid state. Additionally, organic light emitting devices (OLEDs) comprising a layer including these novel compounds are provided. |
| US09196858B2 |
Method for manufacturing light emitting device
An object of the present invention to improve reliability of a light emitting device having a mixed layer including an organic compound and metal oxide without reducing productivity. The above object is solved in such a way that after forming the mixed layer including the organic compound and metal oxide, the mixed layer is exposed to a nitrogen gas atmosphere without being exposed to a gas atmosphere including oxygen, and then a stacked film is formed over the mixed layer without exposing the mixed layer to a gas atmosphere including oxygen. |
| US09196856B2 |
Organic light emitting devices
The present invention relates to monochromatic organic light emitting devices. The organic light emitting device includes a substrate, an anode, a cathode and an organic electroluminescent medium disposed between the anode and the cathode, wherein the organic electroluminescent medium includes compound monochromatic luminescent layer; and the compound monochromatic luminescent layer includes host A doped with monochromatic dopant and host B doped with monochromatic dopant, wherein the host A is consisted of two kinds of materials with different transporting characteristics, one is hole-transporting material, and the other is electron-transporting material. In addition, the present invention further relates to white organic light emitting devices, wherein the organic electroluminescent medium is consisted of at least one compound monochromatic luminescent layer, which includes host A doped with monochromatic dopant and host B doped with monochromatic dopant. The present invention provides a design to improve the lifetime of the organic light emitting device markedly. |
| US09196854B2 |
Organic EL lighting emitting device, method of manufacturing the same, and organic EL light source device
An organic EL light emitting device and an organic EL light source device having the organic EL light emitting device are described. A method of manufacturing the organic EL light emitting device includes forming a scaling layer over a sealing layer base material by using at least one of chemical vapor deposition and physical vapor deposition, joining the sealing layer to an organic EL substrate having an organic EL device so as to cover the organic EL device, and removing the sealing layer base material to leave the sealing layer that covers the organic EL device. |
| US09196849B2 |
Polymer/inorganic multi-layer encapsulation film
This invention relates to a polymer/inorganic multi-layer encapsulation film, and more particularly, to a multi-layer encapsulation film, which includes a plasma polymer thin film layer formed using a cross-shaped precursor having Si—O bonding and an inorganic thin film layer, and ensures flexibility and has improved encapsulation. |
| US09196848B2 |
Display device and method of manufacturing the same
A display device includes a display panel, a top member, and a bottom member. The top member is disposed on the display panel, and has a first groove region where at least a portion of an upper surface of the display panel is exposed. The bottom member is disposed under the display panel, and has a second groove region where at least a portion of a lower surface of the display panel is exposed. The first and second groove regions are located at a bending region of the display device. |
| US09196847B2 |
Sensitizing complexes, process for the preparation thereof, semiconductive inorganic/organic hybrid material comprising them, and photovoltaic cell comprising said material
in which: F represents one or more groups capable of grafting chemically to a substrate of semiconductive porous oxide ceramic; S represents a sensitizing group for sensitizing a semiconductive porous oxide ceramic; C is a conductive polymer; E is a deconjugating spacer group which makes it possible to electrically isolate the sensitizer (S) from the electron-conductive polymer (C). |
| US09196845B2 |
Material for organic electronic device, and organic electronic device using same
The present invention provides a novel compound that is capable of largely improving a life time, efficiency, electrochemical stability, and thermal stability of an organic electronic device, and an organic electronic device that comprises an organic material layer comprising the compound. |
| US09196834B2 |
Method of manufacturing an organic light emitting structure and method of manufacturing an organic light emitting display device
A method of manufacturing an organic light emitting structure is provided as follows. A first electrode is formed on a lower substrate. A pixel defining layer is formed adjacent to the first electrode on the lower substrate. A preliminary charge transport layer is formed on the first electrode and the pixel defining layer. An organic light emitting layer is formed on the preliminary charge transport layer. The preliminary charge transport layer is selectively etched to form a charge transport layer. A second electrode is formed on the organic light emitting layer. |
| US09196830B2 |
Wrap around phase change memory
A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element. |
| US09196828B2 |
Resistive memory and fabricating method thereof
A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode. |
| US09196817B2 |
High voltage switches having one or more floating conductor layers
This patent document discloses high voltage switches that include one or more electrically floating conductor layers that are isolated from one another in the dielectric medium between the top and bottom switch electrodes. The presence of the one or more electrically floating conductor layers between the top and bottom switch electrodes allow the dielectric medium between the top and bottom switch electrodes to exhibit a higher breakdown voltage than the breakdown voltage when the one or more electrically floating conductor layers are not present between the top and bottom switch electrodes. This increased breakdown voltage in the presence of one or more electrically floating conductor layers in a dielectric medium enables the switch to supply a higher voltage for various high voltage circuits and electric systems. |
| US09196814B2 |
Light emitting device package and light unit
Embodiments provide a light emitting device package including a package body having a through-hole; a radiator disposed in the through-hole and including an alloy layer having Cu; and a light emitting device disposed on the radiator, wherein the alloy layer includes at least one of W or Mo, and wherein the package body includes cavity including a sidewall and a bottom surface, and wherein the through-hole is formed in the bottom surface. |
| US09196812B2 |
Semiconductor light emitting device and semiconductor light emitting apparatus having the same
In example embodiments, a semiconductor light emitting device includes a light emitting structure, first and second insulating layers, a barrier metal layer, and an electrode. The light emitting structure includes an active layer between a first and second conductivity-type semiconductor layer. The first insulating layer is on the light emitting structure and defines a first one and a second one of first openings that respectively expose the first and second conductivity-type semiconductor layers. The barrier metal layer is on the first insulating layer and electrically connected to the first and second conductivity-type semiconductor layers through the first and second one of the first openings. The second insulating layer is on the barrier metal layer and defines a second opening that partially exposes the barrier metal layer. The electrode is on the barrier metal layer and electrically connected to the first and second conductivity-type semiconductor layers through the barrier metal layer. |
| US09196807B2 |
Light emitting element
To provide a semiconductor light emitting element with high luminous efficiency, the light emitting element includes: a substrate; a semiconductor laminate placed above the substrate, the semiconductor laminate comprising a second semiconductor layer, an active layer and a first semiconductor layer laminated in this order from the substrate; and a first electrode and a second electrode placed between the substrate and the semiconductor laminate, wherein the semiconductor laminate is divided in a plurality of semiconductor blocks by a groove, wherein the first electrode includes protrusions that are provided in each of the plurality of semiconductor blocks and that penetrate the second semiconductor layer and the active layer to be connected to the first semiconductor layer, and wherein the second electrode is connected to the second semiconductor layer in each of the plurality of semiconductor blocks and has an external connector that is exposed on the bottom of the groove. |
| US09196803B2 |
Semiconductor light emitting element and method for manufacturing the same
[Object][Means for Solving Problem] A method for manufacturing of a semiconductor light emitting element has; forming a semiconductor layer laminated of a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer, in this order, forming an electrode including a silver-containing layer in contact with an upper surface of the second conductivity type semiconductor layer, forming an insulating layer coating over at least a side surface of the silver-containing layer from the upper surface of the second conductivity type semiconductor layer by an atomic layer deposition method. |
| US09196796B2 |
Semiconductor light emitting diode having ohmic electrode structure and method of manufacturing the same
Embodiments of the invention provide a semiconductor light emitting diode having an ohmic electrode structure, and a method of manufacturing the same. The semiconductor light emitting diode includes a light emitting structure having an upper surface constituting an N-face; and an ohmic electrode structure located on the light emitting structure. Here, the ohmic electrode structure includes a lower diffusion preventing layer, a contact layer, an upper diffusion preventing layer, and an Al protective layer from the N-face of the light emitting structure. |
| US09196795B2 |
Formation of group III-V material layers on patterned substrates
Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described. |
| US09196791B2 |
Light emitting device
A light emitting device includes a substrate, a buffer layer, a first conductive layer, an active layer and a third conductive semiconductor layer. The first conductive layer has a prescribed tensile stress, and a second conductive semiconductor layer has a prescribed compressive stress. |
| US09196789B2 |
Reflective contact layer system for an optoelectronic component and method for producing same
A reflective contact layer system and a method for forming a reflective contact layer system for an optoelectronic component are disclosed. In an embodiment the component includes a first p-doped nitride compound semiconductor layer, a transparent conductive oxide layer, a minor layer and a second p-doped nitride compound semiconductor layer arranged between the first p-doped nitride compound semiconductor layer and the transparent conductive oxide layer, wherein the second p-doped nitride compound semiconductor layer has N-face domains at an interface facing the transparent conductive oxide layer, and wherein the N-face domains at the interface have an area proportion of at least 95%. |
| US09196788B1 |
High extraction efficiency ultraviolet light-emitting diode
Ultraviolet light-emitting diodes with tailored AlGaN quantum wells can achieve high extraction efficiency. For efficient bottom light extraction, parallel polarized light is preferred, because it propagates predominately perpendicular to the QW plane and into the typical and more efficient light escape cones. This is favored over perpendicular polarized light that propagates along the QW plane which requires multiple, lossy bounces before extraction. The thickness and carrier density of AlGaN QW layers have a strong influence on the valence subband structure, and the resulting optical polarization and light extraction of ultraviolet light-emitting diodes. At Al>0.3, thinner QW layers (<2.5 nm are preferred) result in light preferentially polarized parallel to the QW plane. Also, active regions consisting of six or more QWs, to reduce carrier density, and with thin barriers, to efficiently inject carriers in all the QWs, are preferred. |
| US09196787B2 |
Nanowire LED structure with decreased leakage and method of making same
A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores located over a support and extending from portions of a semiconductor surface of the support exposed through openings in the insulating mask layer, and a plurality of semiconductor shells extending over the respective nanowire cores. Each of the plurality of semiconductor shells includes at least one semiconductor interior shell extending around the respective one of the plurality nanowire cores, and a second conductivity type semiconductor outer shell extending around the at least one semiconductor interior shell. A first electrode layer contacts the second conductivity type semiconductor outer shell of the plurality of semiconductor shells and extends into spaces between the semiconductor shells. The semiconductor interior shell includes a semiconductor foot portion which extends under the first electrode and under the respective second conductivity type semiconductor outer shell on the insulating masking layer in the spaces between the plurality of semiconductor shells. |
| US09196781B2 |
Materials, systems and methods for optoelectronic devices
A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer. |
| US09196779B2 |
Double sided barrier for encapsulating soda lime glass for CIS/CIGS materials
A method of fabricating a thin film photovoltaic device is provided. The method subjects a soda lime glass substrate having a front side, backside, and edges to a first cleaning process and forms a first coating of silicon dioxide overlying the backside and the edges. The method further subjects the substrate to a second cleaning process and forms a second coating of silicon dioxide overlying the front side and the edges of the substrate. Furthermore, the method includes causing a barrier layer comprising the first coating and the second coating to encapsulate entirely the front side, backside, and edges. The barrier layer includes at least a thickness of oxygen rich silicon dioxide to contain any sodium bearing material within the substrate. Moreover, the method includes forming a thickness of metal material overlying the second coating on the front side followed by an absorber material and window material plus a top electrode. |
| US09196778B2 |
Light concentrating optical element, light concentrating device, photovoltaic power generation device and photothermal conversion device
A light concentrating optical element includes: a substrate; and a plurality of micro-optical members dispersed inside the substrate. The plurality of micro-optical members each direct light having been transmitted through the substrate and having entered a micro-optical member along an entering direction, so that the light exits the micro-optical member along a matching direction matching the entering direction, and direct light having entered the micro-optical member along an other entering direction, so that the light exits the micro-optical member along an exiting direction, resulting in an advancing direction of light having entered the substrate through a substrate front surface and advancing through the substrate being deflected via the plurality of micro-optical members to extend along the matching direction; and the light having been deflected so as to advance through the substrate along the matching direction is concentrated at an end area of the substrate. |
| US09196772B2 |
Layered element and photovoltaic device comprising such an element
This layered element, in particular for a photovoltaic device, includes a polymer layer, a moisture-sensitive layer, and a protective coating forming a moisture barrier inserted between the polymer layer and the moisture-sensitive layer. The protective coating includes an antireflection multilayer comprising at least two thin layers differing in refractive index from each other. |
| US09196771B2 |
Deployable photovoltaic array and collapsible support unit thereof
A deployable photovoltaic array comprising a plurality of photovoltaic modules attached to a collapsible support unit, where said support unit is made up of a pair of laterally spaced similar pantographs. Each pantograph has the form of a plurality of interconnected rhombs made by pivotally joined elongated arms. Two opposite sides of each solar module are attached to a pair of corresponding nearest parallel arms on the opposite sides of said pantographs. Said array in its deployed condition for large solar elevation angles acquires a characteristic staircase-like form. Angles of said rhombs may further be adjusted to achieve an optimal inclination of said solar modules with respect to the current direction to the sun. In the stowed configuration said array may be held in a protecting container, and is readily portable. |
| US09196765B2 |
Nanostructured solar cell
Systems and methods for fabrication of nanostructured solar cells having arrays of nanostructures are described, including nanostructured solar cells having a repeating pattern of pyramid nanostructures, providing for low cost thin-film solar cells with improved PCE. |
| US09196762B2 |
Method for manufacturing solid-state imaging device, and solid-state imaging device
Certain embodiments provide a method for manufacturing a solid-state imaging device, including thinning a semiconductor substrate, forming a plurality of masking patterns, and forming a groove having inclined surfaces that are inclined relative to a front surface of the semiconductor substrate at a back surface of the semiconductor substrate. A plurality of light receiving sections are provided in a lattice pattern at the front surface of the semiconductor substrate to be thinned. A wiring layer including metal wirings is provided on the front surface of the semiconductor substrate to be thinned. The plurality of masking patterns are arranged in a lattice pattern on the back surface of the thinned semiconductor substrate. The groove is formed by etching the semiconductor substrate between the masking patterns using an etchant having an anisotropic etching property. |
| US09196761B2 |
Semiconductor optical device
A semiconductor optical device includes a stem; a semiconductor optical element mounted on the stem; a resin cap including a cylindrical body portion, a plate portion, and an edge portion; and a lens attached integrally to the plate portion of the cap. The edge portion of the cap is bonded to the stem so that the cap covers the semiconductor optical element. The cylindrical body portion of the cap has at least one first portion and second portions which are spaced apart from each other in the circumferential direction of the cylindrical body portion and which project inwardly relative to the at least one first portion. The stem has projections, and each projection vertically underlies and engages or contacts a surface of a respective one of the second portions of the cap. |
| US09196760B2 |
Methods for producing complex films, and films produced thereby
A method for producing a film, the method comprising melting a layer of precursor particles on a substrate until at least a portion of the melted particles are planarized and merged to produce the film. The invention is also directed to a method for producing a photovoltaic film, the method comprising depositing particles having a photovoltaic or other property onto a substrate, and affixing the particles to the substrate, wherein the particles may or may not be subsequently melted. Also described herein are films produced by these methods, methods for producing a patterned film on a substrate, and methods for producing a multilayer structure. |
| US09196759B2 |
High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods
Back contact back junction solar cell and methods for manufacturing are provided. The back contact back junction solar cell comprises a substrate having a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer and patterned reflective layer on the emitter form a light trapping backside mirror. An interdigitated metallization pattern is positioned on the backside of the solar cell and a permanent reinforcement provides support to the cell. |
| US09196757B2 |
Method of manufacturing solar cell module and solar cell module
A stack is obtained by stacking a glass plate, a first transparent resin sheet, a solar cell, a second transparent resin sheet, a colored resin sheet, and a first resin sheet. The stack is pressed under heat to fabricate a module including the glass plate, a first transparent bonding layer placed between the glass plate and the solar cell and formed of the first transparent resin sheet, a second transparent bonding layer placed between the first resin sheet and the solar cell and formed of the second transparent resin sheet, a colored bonding layer placed between the second transparent bonding layer and the first resin sheet and formed of the colored resin sheet, and the first resin sheet. A loss modulus of the colored resin sheet at a temperature of the pressing is higher than a loss modulus of the first transparent resin sheet at the temperature of the pressing. |
| US09196753B2 |
Select devices including a semiconductive stack having a semiconductive material
Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (Å) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack. |
| US09196751B2 |
Junction FET semiconductor device with dummy mask structures for improved dimension control and method for forming the same
A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate structures in the JFET portion of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments. The transistor channel is therefore accurately dimensioned. |
| US09196745B2 |
Semiconductor device and manufacturing method thereof
Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer. |
| US09196742B2 |
Thin film transistor substrate, method for manufacturing the same, and liquid crystal display panel
A TFT substrate (20a) includes a plurality of pixel electrodes (17a) provided in a matrix, a plurality of TFTs (5) each provided for a corresponding one of the pixel electrodes (17a), and a plurality of auxiliary capacitors (6a) each provided for a corresponding one of the pixel electrodes (17a). Each of the auxiliary capacitors (6a) includes a capacitor line (11b) made of a material identical to that of the gate electrode (11aa) of the TFT (5) and provided in a layer identical to that of the gate electrode (11aa) of the TFT (5), the gate insulating film (12) provided so as to cover the capacitor line (11b), and a corresponding one of the pixel electrodes (17a) provided on the gate insulating film (12) so as to overlap with the capacitor line (11b) and being in conduction with a drain electrode (14ca). |
| US09196741B2 |
Semiconductor device
A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used. A transistor is provided which includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer including a hole whose effective mass is 5 or more times, preferably 10 or more times, further preferably 20 or more times that of an electron in the oxide semiconductor layer, a source electrode layer in contact with the oxide semiconductor layer, and a drain electrode layer in contact with the oxide semiconductor layer. |
| US09196735B2 |
Thin film transistor and method for manufacturing the same, array substrate, and display device
The present invention discloses a thin film transistor and a method for manufacturing the same, an array substrate and a display device. The performance of the thin film transistor can be improved and thereby the image quality can be improved by an increase in the width of the conducting area of a thin film transistor without change of the capacitance of the source electrode. The thin film transistor comprises a substrate, a gate electrode, a source electrode, at least two drain electrodes, a semiconductor layer, a gate electrode protection layer located between the gate electrode and the semiconductor layer and an etch stopping layer located between the semiconductor layer and the source electrode with the drain electrode, wherein the source electrode and the drain electrodes are respectively connected with the semiconductor layer by a via hole. |
| US09196732B2 |
Fin field effect transistor having tapered sidewalls, and method of forming the same
The description relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a fin having a first height above a first surface of a substrate, where a portion of the fin has first tapered sidewalls, and the fin has a top surface. The FinFET further includes an insulation region over a portion of the first surface of the substrate, where a top of the insulation region defines a second surface. The FinFET further includes a gate dielectric over the first tapered sidewalls and the top surface. The FinFET further includes a conductive gate strip over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction perpendicular to the first height, and a first width between the second tapered sidewalls in the longitudinal direction is greater at a location nearest to the substrate than a second width at a location farthest from the substrate. |
| US09196729B2 |
Semiconductor device having buried channel array and method of manufacturing the same
A semiconductor device and a method of fabricating a semiconductor device, the device including an active region on a substrate, the active region being defined by a field region; gate trenches in the active region of the substrate; gate structures respectively formed in the gate trenches; and at least one carrier barrier layer in the substrate and under the gate trenches. |
| US09196727B2 |
High uniformity screen and epitaxial layers for CMOS devices
A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control. |
| US09196724B2 |
Lateral devices containing permanent charge
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. |
| US09196719B2 |
ESD protection circuit
A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate. |
| US09196717B2 |
High voltage metal-oxide-semiconductor transistor device
A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. |
| US09196711B2 |
Fin field effect transistor including self-aligned raised active regions
Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity. |
| US09196707B2 |
Oxygen scavenging spacer for a gate electrode
At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer. |
| US09196706B2 |
Method for manufacturing P-type MOSFET
Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer. |
| US09196704B2 |
Selective laser annealing process for buried regions in a MOS device
Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal. |
| US09196703B2 |
Selective deposition of diamond in thermal vias
A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate. |
| US09196699B1 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure. |
| US09196698B2 |
Semiconductor device having a gate dielectric film which is thinner below a source or drain electrode than below a channel region
A semiconductor device according to an embodiment, includes a source electrode, a drain electrode arranged apart from the source electrode, an oxide semiconductor film, a gate dielectric film, and a gate electrode. The oxide semiconductor film is arranged below the source electrode and the drain electrode to connect the source electrode and the drain electrode. The gate dielectric film is formed below the oxide semiconductor film such that a thickness below at least one of the source electrode and the drain electrode is made thinner than a thickness below a channel region of the oxide semiconductor film between the source electrode and the drain electrode. The gate electrode is arranged below the gate dielectric film and formed in a position where one of portions of the gate electrode overlaps with the source electrode and another one of the portions of the gate electrode overlaps with the drain electrode. |
| US09196697B2 |
Semiconductor device with an aluminum alloy gate
A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate. Therefore, the surface of the high-k metal gate after the CMP is aluminum alloy rather than pure aluminum, which can greatly reduce defects, such as corrosion, pits and damage, in the metal gate and improve reliability of the semiconductor device. |
| US09196695B2 |
High-voltage metal-oxide semiconductor transistor and method of fabricating the same
The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate. |
| US09196693B2 |
Method of manufacturing a semiconductor device having a buried field plate
A method of manufacturing a semiconductor device includes forming a first compound semiconductor material on a semiconductor substrate and forming a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material includes a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The method further includes forming a buried field plate in the first compound semiconductor material so that the 2DEG is interposed between the buried field plate and the second compound semiconductor material, and electrically connecting the buried field plate to a terminal of the semiconductor device. |
| US09196688B2 |
Delamination and crack prevention in III-nitride wafers
In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches. |
| US09196686B2 |
Diode circuit and DC to DC converter
A diode circuit includes a switching element having a first terminal and a second terminal. The switching element includes a control electrode for controlling electrical conductance between the first and second terminals. A diode has a cathode electrode connected to the first terminal of the switching element and an anode electrode connected to the control electrode of the switching element. An impedance element is connected in parallel to the diode. The switching element and the diode each comprise a gallium nitride-based semiconductor component. The switching element and the diode may optionally be disposed on the same semiconductor substrate. The diode circuit may optionally be included in a direct current to direct current converter device or other devices. |
| US09196685B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a first superlattice buffer layer formed on a substrate. A second superlattice buffer layer is formed on the first superlattice buffer layer. A first semiconductor layer is formed by a nitride semiconductor on the second superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. The first superlattice buffer layer is formed by alternately and cyclically laminating a first superlattice formation layer and a second superlattice formation layer. The second superlattice buffer layer is formed by alternately and cyclically laminating the first superlattice formation layer and the second superlattice formation layer. The first superlattice formation layer is formed by AlxGa1-xN, and the second superlattice formation layer is formed by AyGa1-yN, where x>y. A concentration of an impurity element doped into the second superlattice buffer layer is higher than that doped into the first superlattice buffer layer. |
| US09196683B2 |
Thin film transistor array substrate and method for manufacturing the same
The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole. |
| US09196682B2 |
Nanoparticle complex, method of manufacturing the same, and device including the nanoparticle complex
A nanoparticle complex, including a semiconductor nanocrystal; and a metal complex ligand on the surface of the semiconductor nanocrystal. The nanoparticle complex may further include a polymer shell contacting the metal complex ligand. |
| US09196680B1 |
Metal oxide semiconductor field effect transistor with reduced surface field folding
A laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) includes: a source contact region, a gate contact region, a drain contact region, and an n-type buried layer. The LDMOSFET also includes a p-type body region formed in an n-type epitaxial layer, the p-type body region directly contacting the source contact region and extending past an end of the source contact region toward the drain contact region. The LDMOSFET also includes a p-type reduced surface field (PRSF) region formed in the n-type epitaxial layer, the PRSF region disposed between the p-type body region and the n-type buried layer. The LDMOSFET also includes an n-type drift region formed in the n-type epitaxial layer, the n-type drift region directly contacting the drain contact region. The LDMOSFET also includes an n-type diffusion region in the n-type epitaxial layer, the n-type diffusion region electrically connecting the n-type buried layer with the n-type drift region. |
| US09196679B2 |
Schottky diode with buried layer in GaN materials
A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures. |
| US09196676B1 |
Method and apparatus for implementing a metal capacitor with L-shaped fingers
A metal capacitor includes a plurality of interconnect segments. A first plurality of L-shaped fingers is driven to a first voltage level by a first interconnect segment. A second plurality of L-shaped fingers is driven to a second voltage level by a second interconnect segment. Each of the L-shaped fingers from a set of the first plurality of L-shaped fingers is adjacent to at least one of the L-shaped fingers from a set of the second plurality of L-shaped fingers. |
| US09196673B2 |
Methods of forming capacitors
A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed. |
| US09196667B2 |
Organic light-emitting display with vertically stacked capacitor and capacitive feedback
An organic light-emitting display device includes a first electrode disposed on a substrate; a plurality of insulating layers which are sequentially disposed on the first electrode, and on which a contact hole for exposing a part of a surface of the first electrode is formed; and an organic light-emitting diode which includes a pixel electrode disposed on the plurality of insulating layers, a second electrode facing the pixel electrode and contacting the first electrode through the contact hole, and an organic emissive layer disposed between the pixel electrode and the second electrode. |
| US09196666B2 |
Organic electroluminescence display device
An organic electroluminescence display device includes: a TFT substrate on which organic electroluminescence elements are formed; a color filter substrate having a color filter layer; a fill material with which the TFT substrate is stuck onto the color filter substrate; a dam material that dams the fill material in a non-display area; and a gas barrier film made of an inorganic material which is arranged between the fill material and the color filter layer, covers the display area in a plan view, and is formed at an interval from the dam material in the non-display area in an inside of the dam material. |
| US09196665B2 |
Display device and method for manufacturing the same
A display device and method for manufacturing the same are disclosed. In one aspect, the display device includes a substrate including a display area and a pad area, a semiconductor layer formed over the substrate, and an insulating layer formed over the semiconductor layer. The display device also includes a metal wire formed over the insulating layer in the display area and a pad electrode formed over the insulating layer in the pad area, wherein the pad electrode is electrically connected to the metal wire. The display device further includes a pattern formed between an edge of the substrate and an end portion of the pad electrode. The edge of the substrate is adjacent to the pad electrodes and the pattern is spaced apart from the end portion of the pad electrode. |
| US09196662B2 |
Organic light emitting display and method for manufacturing the same
Disclosed are an organic light emitting display that has a configuration excluding a polarizing plate and exhibits improved flexibility and visibility, and a method for manufacturing the same, the organic light emitting display includes a touch electrode array facing the organic light emitting diode on the second buffer layer, the touch electrode array including first and second touch electrodes intersecting each other and an exterior light shielding layer including at least a color filter layer, an adhesive layer formed between the organic light emitting diode and the touch electrode array. |
| US09196660B2 |
Array substrate and fabrication method thereof, display device
Embodiments of the invention disclose an array substrate and a fabrication method thereof, and a display device. The array substrate comprises a plurality of pixel units disposed on a base substrate. Each pixel unit comprises a thin-film transistor region and a display region. A thin-film transistor structure is formed in the thin-film transistor region, and an organic light-emitting diode. The organic light-emitting diode comprises a transparent first electrode, a light-emitting layer, and a second electrode for reflecting light that are sequentially formed. A transflective layer is formed in the display region. A color filter film is formed in the display region and is disposed between the second electrode of the organic light-emitting diode and the transflective layer. The second electrode of the organic light-emitting diode and the transflective layer form a microcavity structure. The color filter films in the pixel units of different colors have different thicknesses. |
| US09196656B2 |
Nonvolatile memory devices
A nonvolatile memory device includes a plurality of first electrode lines including upper portions that have convex top surfaces. A plurality of second electrode lines are disposed over the plurality of first electrode lines to cross the plurality of first electrode lines, and a plurality of memory patterns are disposed between the plurality of first electrode lines and the plurality of second electrode lines. |
| US09196646B2 |
Method for reducing crosstalk in image sensors using implant technology
The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy. |
| US09196645B2 |
Photoelectric conversion device and imaging system
A photoelectric conversion device includes: a first semiconductor region of a first conductivity type, which configures a first photoelectric conversion element; a second semiconductor region of the first conductivity type, which configures a second photoelectric conversion element; a third semiconductor region of the first conductivity type; a fourth semiconductor region of the first conductivity type; a first gate electrode, configuring a first transfer transistor conjointly; and a second gate electrode, configuring a second transfer transistor. At a side of the first gate electrode which is toward the first semiconductor region in plan view of the surface of the semiconductor substrate, a length of the side of the first gate electrode toward the first semiconductor region, is shorter than a length of the active region, and a length of the side of the first gate electrode toward the first semiconductor region, is longer than a length of the first semiconductor region. |
| US09196640B2 |
Array substrate with a gate driver on array (GOA) circuit and display device
An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode. |
| US09196638B2 |
Light emitting device
An object of the present invention is to provide a light emitting device in which variations in an emission spectrum depending on a viewing angle with respect to a side from which luminescence is extracted are decreased. A light emitting device according to the invention has a transistor, an insulating layer covering the transistor and a light emitting element provided in an opening of the insulating layer. The transistor and the light emitting element are electronically connected through a connecting portion. Additionally, the connecting portion is connected to the transistor through a contact hole penetrating the insulating layer. Note that the insulating layer may be a single layer or a multilayer in which a plurality of layers including different substances is laminated. |
| US09196634B2 |
TFT array substrate, display panel and display device
The present invention discloses a TFT array substrate, comprising: a plurality of scan lines; a plurality of data lines; pixel units located in areas defined by adjacent scan lines and adjacent data lines; wherein each of the pixel units comprises a first electrode and a second electrode stacked and insulated from each other, the first electrode is flat shape, and the second electrode comprises a plurality of strip electrodes extending along a first direction and arranged along a second direction; a first pixel unit and a second pixel unit adjacent to each other form a unit group; the first pixel unit comprises a first part extending along the first direction and a second part extending from an end area of the first part to the second pixel unit; the second pixel unit comprises a third part extending along the first direction and a fourth part extending from an end area of the third part to the first pixel unit; and the second part is staggered with the fourth part. With such design, the color resistance compensation can not be needed, and also the transmittance is increased. |
| US09196633B2 |
Display device
A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved. |
| US09196632B2 |
Semiconductor device and method for manufacturing the same
An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si. |
| US09196631B1 |
Array substrate and method for manufacturing the same, and display device
Embodiments of the invention disclose an array substrate and a method for manufacturing the same, and a display device. The method for manufacturing an array substrate comprising: forming a gate metal layer, wherein the gate metal layer comprises gate lines; film-forming an active layer and film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after film-forming the active layer and before film-forming the signal line metal layer, the method further comprising: hollowing out a first region of the active layer through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines. |
| US09196622B2 |
Semiconductor device including memory cell array and power supply region
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions. |
| US09196621B2 |
Semiconductor device
A semiconductor device includes a first and a second active regions having a first conductive type and a second conductive type, respectively, being arranged in a first direction; a gate extending in the first direction; a first and a second channel regions defined under the gate in the first and the active regions, respectively; a first low-concentration doped region, having the second conductive type, formed at sides of the gate in the first active region and a first high-concentration doped region, having the second conductive type, formed at sides of the first low-concentration doped region in the first active region; and a second low-concentration doped region, having the first conductive type, formed at sides of the gate in the second active region and a second high-concentration doped region, having the first conductive type, formed at sides of the second low-concentration doped region in the second active region. |
| US09196615B2 |
Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
Under one aspect, a nanotube diode includes: a cathode formed of a semiconductor material; and an anode formed of nanotubes. The cathode and anode are in fixed and direct physical contact, and are constructed and arranged such that sufficient electrical stimulus applied to the cathode and the anode creates a conductive pathway between the cathode and the anode. In some embodiments, the anode includes a non-woven nanotube fabric having a plurality of unaligned nanotubes. The non-woven nanotube fabric may have a thickness, e.g., of 0.5 to 20 nm. Or, the non-woven nanotube fabric may include a block of nanotubes. The nanotubes may include metallic nanotubes and semiconducting nanotubes, and the cathode may include an n-type semiconductor material. A Schottky barrier can form between the n-type semiconductor material and the metallic nanotubes and/or a PN junction can form between the n-type semiconductor material and the semiconducting nanotubes. |
| US09196613B2 |
Stress inducing contact metal in FinFET CMOS
A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer. |
| US09196608B2 |
Method of chip positioning for multi-chip packaging
Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers. |
| US09196607B2 |
Stack packages and methods of manufacturing the same
A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors. |
| US09196606B2 |
Bonding transistor wafer to LED wafer to form active LED modules
LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer, containing an array of vertical MOSFETS, is aligned and bonded to an LED wafer, containing a corresponding array of vertical LEDs, and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. |
| US09196604B2 |
Power semiconductor module having pattern laminated region
A power semiconductor module includes a base plate as a metallic heat dissipating body, a first insulating layer on the base plate, and a first wiring pattern on the first insulating layer. On a predetermined region that is a part of the first wiring pattern, a second wiring pattern for a second layer is laminated via only a second insulating layer made of resin, thereby forming a pattern laminated region. A power semiconductor element is mounted in a region other than the pattern laminated region on the first wiring pattern. The base plate, the first insulating layer, the first wiring pattern, the second insulating layer, the second wiring pattern, and the power semiconductor element are integrally sealed with a transfer mold resin, thus obtaining the power semiconductor module. |
| US09196598B1 |
Semiconductor device having power distribution using bond wires
A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device. |
| US09196597B2 |
Semiconductor package with single sided substrate design and manufacturing methods thereof
A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. |
| US09196593B2 |
Semiconductor device
To provide a semiconductor device whose reliability is improved by increase in resistance to external stress and electrostatic discharge with reduction in thickness and size achieved. An IC chip provided with an integrated circuit and a resonant capacitor portion, an antenna provided over the IC chip, and a conductive blocking body provided so as to at least partially overlap the antenna with an insulating film interposed therebetween are included. A capacitor is formed with a layered structure of the antenna, the insulating film over the antenna, and the conductive blocking body over the insulating film. |
| US09196592B2 |
Methods of managing metal density in dicing channel and related integrated circuit structures
Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region. |
| US09196591B2 |
Chip with shelf life
A method of forming a semiconductor structure includes forming a recess within a silicon substrate of an IC chip near a circuit of the IC chip. A metal layer is formed in the recess and the IC chip is exposed to an oxygen-containing environment to initiate the oxidation of a portion of the silicon substrate below the metal layer and adjacent to the circuit. The oxidation process consumes the portion of the silicon substrate below the metal layer forming a silicon dioxide layer that damages the circuit and causes the IC chip to be inoperable. The time to oxidize the portion of the silicon substrate below the metal layer and damage the circuit represents the shelf life of the IC chip. |
| US09196590B2 |
Perforated electronic package and method of fabrication
An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate. |
| US09196589B2 |
Stacked wafer structure and method for stacking a wafer
A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided. |
| US09196585B2 |
Polysilicon fuse, semiconductor device having overlapping polysilicon fuse sections and method of severing polysilicon fuse
In some aspects of the invention, a first polysilicon fuse section for forming a cavity is provided in close proximity to a second polysilicon fuse section for adjusting circuit characteristics. By forming a cavity with the first polysilicon fuse section made to be blown, fused polysilicon is contained in the cavity when the second polysilicon fuse section is blown to make it possible to provide a polysilicon fuse capable of stably maintaining an electrical insulated state. This can provide a polysilicon fuse capable of stably maintaining the electrical insulated state when the fuse is blown, a semiconductor device having the polysilicon fuse and a method of severing the polysilicon fuse. |
| US09196584B2 |
Light-emitting device and lighting apparatus using the same
A light-emitting device includes a substrate, first LEDs and second LEDs mounted on the substrate, multiple wirings separately formed on the substrate, and a conductive member for connecting adjacent two wirings in multiple wirings for establishing series connection, parallel connection, or a combination of series and parallel connections of the first LEDs and the second LEDs. This achieves the light-emitting device that can support multiple different specifications, using a single type of substrate. |
| US09196576B2 |
Semiconductor package with stress relief and heat spreader
A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle. |
| US09196575B1 |
Integrated circuit package with cavity in substrate
Integrated circuit packages with heat dissipation function are disclosed. A disclosed integrated circuit package includes a first die attached on a top surface of a second die. The second die may be coupled to a thermally conductive block. The thermally conductive block may be embedded in a cavity formed in a package substrate. A heat spreading lid may be disposed over the package substrate. The integrated circuit package may be disposed on a printed circuit substrate via solder bumps or balls. The printed circuit substrate may have heat dissipation paths to dissipate heat from the integrated circuit package. |
| US09196572B2 |
Power semiconductor module
A power semiconductor module comprising a substrate. The power semiconductor module has first and second DC voltage load current connection elements and first and second power semiconductor components. The first and second power semiconductor components are arranged along a lateral first direction of the substrate. The power semiconductor module has a foil composite having a first metallic foil layer and a structured second metallic foil layer and an electrically insulating foil layer arranged between the first and second metallic foil layers. The first power semiconductor component and the second power semiconductor component are electrically conductively connected to the foil composite and to the substrate. The first and second power semiconductor components are arranged on a common side in relation to the first and second DC voltage load current connection elements. The invention provides a power semiconductor module having a particularly low-inductance construction. |
| US09196565B2 |
Fixing assembly
A fixing assembly includes a fixing frame, a fixing member, and a fastening member. The fixing frame includes a frame body and a guiding wall portion. The frame body is disposed between a circuit board and a heatsink. The guiding wall portion is connected to the frame body and has an elongated hole. The thicknesses of the guiding wall portion are reduced toward the frame body. The fixing member abuts against the guiding wall portion and is located over the heatsink. The fixing member has a screw hole communicated with the elongated hole. The fastening member is fastened to the screw hole via the elongated hole. The fastening member is retained by the elongated hole to move relative to the guiding wall portion along the elongated hole, so as to move the fixing member toward or away from the heatsink. |
| US09196564B2 |
Apparatus and method for a back plate for heat sink mounting
Apparatus and method embodiments are provided for a heat sink mounted on a printed circuit board using a back plate with preload. An apparatus comprises a circuit component, a heat sink on a first side of the circuit component a, a back plate having an initial curvature and positioned at a second side of the circuit component opposite to the heat sink, and one or more screws through the back plate and the circuit component and partially through the heat sink. A method further includes placing and flattening a curved back plate on a second side of a circuit board opposite to the first side, and fastening the back plate, the circuit board, and the heat sink together by inserting a plurality of screws through the back plate, the circuit board, and a partial depth on a single side of the heat sink. |
| US09196563B2 |
Bonded body and semiconductor module
Bondability and heat conductivity of a bonded body in which some of metal, ceramic, or semiconductor are bonded to each other are improved. In the bonded body in which a first member and a second member each comprise one of metal, ceramic, or semiconductor are bonded to each other, the second member is bonded to the first member by way of an adhesive member disposed to the surface of the first member, and the adhesive member contains a V2O5-containing glass and metal particles. In a semiconductor module having a base metal, a ceramic substrate, a metal wiring, and a semiconductor chip, the ceramic substrate is bonded to the base metal by way of a first adhesive member disposed to the surface of the base metal, the metal wiring is bonded to the ceramic substrate by way of a second adhesive member disposed to the surface of the ceramic substrate, the semiconductor chip is bonded to the metal wiring by way of a third adhesive member disposed to the surface of the metal wiring, and the first adhesive member, the second adhesive member, and the third adhesive member each comprise a V2O5-containing glass and metal particles. |
| US09196562B2 |
Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate
A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least 10 micrometers (μm), the thick metal layer comprises copper or a copper alloy, and the bonding wire or ribbon comprises copper or a copper-based material. |
| US09196561B2 |
Semiconductor device to be attached to heat radiation member
A semiconductor device includes a semiconductor module and a pressing member pressing the semiconductor module to a heat radiation member. The semiconductor module includes heat generation elements generating heat by energization, three or more conductive members each of which mounted with at least one of the heat generation elements, and a molding part integrally molding the heat generation elements and the conductive members. The semiconductor module has a heat radiation possible region in which a forcing pressure by the pressing member is equal to or greater than a predetermined pressure. The conductive member mounted with the heat generation element disposed outside the heat radiation possible region has such a shape that at least a part of the conductive member is included in the heat radiation possible region. |
| US09196555B1 |
Integrated circuit protection and ruggedization coatings and methods
An electronics package includes a substrate and at least one electronic component coupled to the substrate. The electronics package comprises an alkali silicate coating forming a hermetic seal around at least a portion of the at least one electronic component. |
| US09196554B2 |
Electronic component, arrangement and method
An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step. |
| US09196553B2 |
Semiconductor package structure and manufacturing method thereof
A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer. |
| US09196552B2 |
Display device and manufacturing and testing methods thereof
A display device is disclosed which includes: gate lines and data lines crossing each other to define unit pixel regions in a display area; a pixel electrode in each unit pixel region; a data shorting bar in a non-display area in substantially parallel with the gate lines; a gate shorting bar in the non-display area in substantially parallel with the data lines; gate link lines electrically connecting the gate lines to the gate shorting bar; data link lines electrically connecting the data lines to the data shorting bar; and shield electrodes on at least one of the gate link lines and the data link lines, the shield electrodes including a conductive material that has a higher melting temperature than that of the at least one of the gate link lines and the data link lines. |
| US09196550B2 |
Surface inspection apparatus, method for inspecting surface, exposure system, and method for producing semiconductor device
A surface inspection apparatus includes: an irradiation unit; a detection unit configured to detect a first detection signal according to a first light beam and a second detection signal according to a second light beam; a providing unit which is configured to provide a first reference data and a second reference data; and a determination unit which is configured to determine a processing condition of the pattern in the substrate as an inspection object substrate, based on consistency between the first detection signal and the first reference data, and consistency between the second detection signal and the second reference data. |
| US09196535B2 |
Method and apparatus for separating semiconductor devices from a wafer
An embodiment method for separating semiconductor devices from a wafer comprises using a carrier which acts an adjustable adhesive force upon the semiconductor devices and removing the semiconductor devices from the carrier by applying a mechanical or acoustical impulse to the carrier. |
| US09196532B2 |
Integrated circuit packages and methods for forming the same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. |
| US09196529B2 |
Contact pad for semiconductor devices
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region. |
| US09196528B2 |
Use of contacts to create differential stresses on devices
Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. |
| US09196527B2 |
Fuse structure for high integrated semiconductor device
The present invention provides a technology capable of improving an operation reliability of a semiconductor device. Particularly, a fuse material which constitutes the copper can be prevented from migrating being locked in the recesses or the grooves after a blowing process. A semiconductor device includes an insulating layer including a concave-convex-shaped upper part; and a fuse formed on the insulating layer. |
| US09196522B2 |
FinFET with buried insulator layer and method for forming
A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure. |
| US09196516B2 |
Wafer temperature measurement tool
A wafer temperature measurement tool for measuring the surface temperature of a semiconductor wafer. The tool can be used to measure temperature on different parts of the wafer to provide a high resolution temperature distribution map. The tool includes an internal calibrated weight that is slidably disposed within a tool body. A temperature sensor is attached to the bottom of the weight. Ceramic stands are attached to the bottom of the tool body. Gravity pulls down on the weight such that the temperature sensor contacts the wafer when the ceramic stands of the tool body are placed on the wafer. |
| US09196504B2 |
Thermal leadless array package with die attach pad locking feature
Embodiments of the present invention are directed to a thermal leadless array package with die attach pad locking feature and methods of producing the same. A copper layer is half-etched on both surfaces to define an array of package contacts and a die attach pad. Each die attach pad is fully embedded in encapsulate material to provide a positive mechanical locking feature for better reliability. In some embodiments, the contacts include four active corner contacts. |
| US09196502B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a substrate and memory cell transistors having a gate electrode above the substrate, and an oxide film. The gate electrode includes a charge storage layer above the substrate, a first insulating film on the charge storage layer, and a control gate electrode on the first insulating film, the control gate electrode including a metal film. The oxide film is disposed on the metal film. |
| US09196496B2 |
Method of integrating a charge-trapping gate stack into a CMOS flow
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described. |
| US09196494B2 |
Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the first line on the isolation regions being larger than a line width of the first line on the device regions. |
| US09196492B2 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes: forming a metal layer on a semiconductor layer; forming a plated layer having a pattern corresponding to a pattern of a gate bus line which couples each gate finger of a plurality of FETs on the metal layer, the pattern corresponding to the pattern of the gate bus line having a deficient part; forming a mask layer which covers the metal layer exposed in the deficient part; and patterning the metal layer by using the plated layer and the mask layer as a mask. |
| US09196487B2 |
Method for forming electrode of n-type nitride semiconductor, nitride semiconductor device, and manufacturing method thereof
According to an example embodiment, a method includes forming a nitrogen vacancy surface layer by treating a surface of an n-type nitride semiconductor with inert gas plasma, and forming an oxygen-added nitride film by treating a surface of the nitrogen vacancy surface layer with oxygen-containing gas plasma, and forming an electrode on the oxygen-added nitride film. The nitrogen vacancy surface layer lacks a nitrogen element. |
| US09196486B2 |
Inorganic phosphate containing doping compositions
A composition for doping semiconductor materials, such as silicon, may contain a) a solvent and a) an inorganic salt of a phosphor containing acid dispersed in the solvent. Also disclosed are doping methods using such composition as well as methods of making the doping composition. |
| US09196483B1 |
Carrier channel with element concentration gradient distribution and fabrication method thereof
The present disclosure provides a carrier channel with an element concentration gradient distribution. The carrier channel includes a substrate and a carrier channel structure. The carrier channel structure is stacked on the substrate, wherein a ratio of a height and a width of the carrier channel is greater than 1, and the carrier channel is crystallized from the contact surface by a rapid melting growth process, thus the carrier channel structure has the element concentration gradient distribution. |
| US09196482B2 |
Solution-based synthesis of CsSnI3
This invention discloses a solution-based synthesis of cesium tin tri-iodide (CsSnI3) film. More specifically, the invention is directed to a solution-based drop-coating synthesis of cesium tin tri-iodide (CsSnI3) films. CsSnI3 films are ideally suited for a wide range of applications such as light emitting and photovoltaic devices. |
| US09196480B2 |
Method for treating group III nitride substrate and method for manufacturing epitaxial substrate
Provided is a method for treating a group III nitride substrate capable of obtaining, in the case where a group III nitride layer is laminated thereon, a group III nitride substrate that can form an electronic device having excellent characteristics. The method for treating a group III nitride substrate includes the steps of CMPing a surface of a substrate, elevating a temperature of the group III nitride substrate after the CMP process to a predetermined annealing temperature under a nitrogen gas atmosphere, and holding the group III nitride substrate whose temperature has been elevated to the annealing temperature for four minutes or more and eight minutes or less in a first mixed atmosphere of a hydrogen gas and a nitrogen gas or a second mixed atmosphere of a hydrogen gas and an ammonia gas. |
| US09196470B1 |
Molded leadframe substrate semiconductor package
A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound. |
| US09196468B2 |
Method and system for introducing make-up flow in an electrospray ion source system
An electrospray ion source method and system is provided for detecting emitter failure comprising a liquid chromatography column suitable for chromatographic separation of a sample. The column can have an inlet for receiving the sample; and an outlet for ejecting the sample. A make-up flow channel is provided for introducing make-up flow of liquid to the sample post-column, wherein the make-up flow normalizes the spray current. An electrospray ionization source is provided having one or more electrospray ionization emitter nozzles for receiving the make-up flow containing sample. A power supply can provide a voltage to the one or more emitter nozzles, and a measurement device can measure and monitor the spray current. |
| US09196465B2 |
Method and kit for detecting hepcidin
A method for detecting hepcidin. Having a sample liquid in contact with a nanochip having a specific surface coating structure of silicon oxide, so that hepcidin is enriched with specificity; eluting the nanochip with an eluent; by performing mass spectrometric detection on the elution product, determining the hepcidin content in the elution product. The enrichment method substantially enhances the sensitivity and accuracy of mass spectrometric detection. A kit for detecting hepcidin comprising a sample diluent and a nanochip, the sample diluent comprising water, trifluoroacetic acid, and acetonitrile. |
| US09196464B2 |
Tablet for plasma coating system, method of manufacturing the same, and method of manufacturing a thin film using the method of manufacturing the tablet
A tablet for a plasma coating system having a first part that includes a first material having a first sublimation point at a first pressure and a second part that is disposed on the first part and comprises a second material having a second melting point at the first pressure, wherein the second melting point is lower than the first sublimation point. |
| US09196460B2 |
Plasma processing apparatus and plasma processing method
A ratio between gas conductances of a main gas passage and a plurality of branch gas passages is increased. A plasma processing apparatus is an apparatus for plasma-processing an object to be processed by exciting gas, and includes a processing container; a gas supply source for supplying a desired gas; a main gas passage distributing the gas supplied from the gas supply source; a plurality of branch gas passages connected to a lower stream side of the main gas passage; a plurality of throttle portions formed on the plurality of branch gas passages to narrow the branch gas passages; and one, two, or more gas discharging holes per each of the branch gas passages, for discharging the gas that has passed through the plurality of throttle portions formed on the plurality of branch gas passages into the processing container. |
| US09196458B2 |
Charged particle beam drawing apparatus and drawing chamber
A charged particle beam drawing apparatus includes: a stage configured to support a specimen as a drawing target; and an airtight drawing chamber formed into a box shape provided with a side wall and a bottom plate, and configured to house the stage. The bottom plate includes: multiple support portions connected to the side wall and configured to support the stage; and a curved portion connected to the support portions and having a convex shape curved outward. |
| US09196457B2 |
Flow cells for electron microscope imaging with multiple flow streams
Provided are flow cell devices—referred to as nanoaquariums—that are microfabricated devices featuring a sample chamber having a controllable height in the range of nanometers to micrometers. The cells are sealed so as to withstand the vacuum environment of an electron microscope without fluid loss. The cells allow for the concurrent flow of multiple sample streams and may be equipped with electrodes, heaters, and thermistors for measurement and other analysis devices. |
| US09196456B2 |
Image acquisition method and transmission electron microscope
An image acquisition method and system for use in transmission electron microscopy and capable of providing information about a wide range of frequency range. The method is initiated with setting at least one of the spherical aberration coefficient and chromatic aberration coefficient of the imaging system of the microscope to suppress attenuation of a contrast transfer function due to an envelope function. Then, an image is obtained by the imaging system placed in defocus conditions. |
| US09196453B2 |
Gas field ionization ion source and ion beam device
Provided is a gas field ionization ion source capable of emitting heavy ions with high brightness which are suitable for processing a sample. The gas field ionization ion source according to the present invention includes a temperature controller individually controlling the temperature of the tip end of an emitter electrode (1) and the temperature of a gas injection port part (3) of a gas supply unit. |
| US09196446B2 |
Hydrogen getter
A getter composition suitable for gettering hydrogen comprises a first metal oxide and a second metal oxide, said first metal oxide being more readily reducible in hydrogen at temperatures between 0° C. and 100° C. than said second metal oxide. |
| US09196443B2 |
Air circuit breaker coil adapter
Air circuit breaker coil adapter for adapting an air circuit breaker, comprises: a coil unit housing for releasably receiving an air circuit breaker coil unit, the coil unit housing having a coil retainer element for preventing or limiting upward movement of an air circuit breaker coil unit therein; a locator at a bottom end of the coil unit housing for positively locating the coil unit housing in a plunger aperture of an air circuit breaker housing, the locator having a plunger aperture therethrough by which an interior of the coil unit housing is in-use communicable with an interior of the air circuit breaker housing; and a housing retainer element for at least in part preventing or limiting vertical displacement of the coil unit housing. An air circuit breaker using such an adapter and a method of adapting an air circuit breaker are also provided. |
| US09196437B2 |
Operation input apparatus and operation input detection apparatus
An operation input apparatus configured to receive a force from an operator, including: a board 10 including a placement surface on which coils 21˜24 are placed, the coils being arranged in a circumferential direction of a circle formed by connecting points apart from a reference point by the same distance; a key 30 that is provided in a side where the force is input with respect to the board 10; and a return spring 51˜54 elastically supporting the key 30, wherein the key 30 includes an opposed surface opposed to the placement surface and an operation surface configured to receive an application of the force, and causes an inductance of at least one of the coils 21˜24 to change with an approach of the opposed surface to the placement surface due to the application of the force on the operation surface. |
| US09196435B2 |
Tuned switch system
The described embodiments relate to methods and apparatus for fine-tuning a resistance profile for a mechanical switch. In one embodiment, by combining a switch with one or more damping or support materials a tuned switch system can be formed. The damping or support materials can modify the force and displacement characteristics of the switch, thereby allowing a user experience to be customized. The damping or support materials can be arranged in series and/or in parallel with the mechanical switch. |
| US09196434B2 |
Method and device for performing diagnostics of an actuator, and actuator comprising one such device
A diagnostic method for an actuator having a coil and a control device for supplying power to the coil, by controlling a power supply to the actuator by a diagnostic device, controlling a supply of power to the coil by a control device, monitoring an electric signal supplying the actuator, and deriving a diagnostic indicator of the actuator from a result of monitoring; and a device and computer code for executing the method. |
| US09196430B2 |
Electrical circuit protection device enclosure assembly and kit with device compatibility attachment
An enclosure for an electrical circuit protection product such as a surge protection device include a three dimensional compatibility housing piece attachable to an enclosure assembly that visually provides informational feedback and enhanced state indication features for use by persons to more readily understand and locate compatible circuit protection devices and information. |
| US09196428B2 |
Gang socket and jig for manufacturing capacitor element that uses said gang socket
Provided is a gang socket with which capacitor elements can be manufactured without contaminating chemical conversion treatment liquids or semiconductor layer forming liquids even when the chemical conversion treatment liquids and semiconductor layer forming liquids are corrosive and with which heat treatment can be carried out without obstacles even when heat treatment is carried out during the manufacture of the capacitor elements. This gang socket (1) is provided with a plurality of conductive socket main units (2) provided with insertion openings (37) and an insulator part (5) forming a plurality of receiving parts (6) that can accommodate at least part of the socket main units (2) and provided with a plurality of small openings (7) connecting to the bottom surface of the receiving parts (6) on a bottom surface (5b). The insulator part (5) is constituted of a material having heat resistance and corrosion resistance. At least part of the socket main units (2) are accommodated and secured in the receiving parts (6) of the insulator part (5), and the insertion openings (37) and the small openings (7) are connected. |
| US09196424B2 |
Double-center bipyridyl cationic ion liquid, preparation method therefor and use thereof
Disclosed is a double-center bipyridyl cationic ion liquid prepared by reacting bipyridyl with haloalkane for synthesis of dialkyl bipyridyl halide, and converting the halogen ion in the dialkyl bipyridyl halide to the target anion via an ion-exchange reaction, to give the final target ionic liquid. Also disclosed are an organic electrolyte containing the double-center bipyridyl cationic ion liquid and a preparation method therefor. |
| US09196422B2 |
Multilayer ceramic capacitor having high capacity and method of manufacturing the same
There are provide a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a multilayer body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side, inner electrodes formed in the multilayer body and formed to be spaced apart from the third side or the fourth side by a predetermined distance, groove portions formed on at least one of top and bottom surfaces of the multilayer body and formed parallel to the third or fourth side by a predetermined distance from the third side or the fourth side, and outer electrodes extended from the third side and the fourth side to the top surface or the bottom surface of the multilayer body to cover the groove portions. |
| US09196421B2 |
Multilayer ceramic electronic component
There is provided a multilayer ceramic electronic component, including: a ceramic body formed by laminating dielectric layers having an average thickness of 0.7 μm or less; external electrodes formed on external surfaces of the ceramic body; and internal electrodes respectively disposed on the dielectric layer so as to have a gap formed therebetween, wherein, when a narrowest gap between the internal electrode edges adjacent to one another is denoted by Gmin, 10 μm≦Gmin≦60 μm is satisfied. |
| US09196420B2 |
Multilayer ceramic electronic component to be embedded in board and printed circuit board having multilayer ceramic electronic component embedded therein
There is provided a multilayer ceramic electronic component, including a ceramic body having first and second side surfaces facing each other, and first and second end surfaces facing each other; first and second internal electrodes having first and second lead portions; and first and second external electrodes extended from the first and second end surfaces of the ceramic body to the first and second side surfaces, respectively, wherein when a distance from an end portion of the first or second external electrode formed on the first or second side surface of the ceramic body to a point of the first or second external electrode connected to the first or second lead portion is defined as G, and a width of the first or second external electrode on the first or second side surface of the ceramic body is defined as BW, 30 μm≦G |
| US09196412B2 |
Insulation formulations
A curable epoxy resin formulation composition useful as insulation for an electrical apparatus including (a) at least one liquid epoxy resin; (b) at least one liquid cyclic anhydride hardener; (c) at least one thermally conducting and electrically insulating filler, wherein the filler includes an epoxy-silane treated filler; and (d) at least one cure catalyst with no amine hydrogens; wherein the epoxy resin formulation composition upon curing provides a cured product with a requisite balance of electrical, mechanical, and thermal properties such as Tg, tensile strength, dielectric strength, and volume resistivity such that the cured product can be used in applications operated at a temperature of greater than or equal to 120° C. |
| US09196410B2 |
Chip inductor and method of manufacturing the same
Disclosed herein are a chip inductor and a method of manufacturing the same. The chip inductor includes: a laminate in which a magnetic sheet having a C-pattern electrode formed thereon and a magnetic sheet having an I-pattern electrode formed thereon are alternately laminated; a via penetrating through the magnetic sheet and connecting the C-pattern electrode and the I-pattern electrode; and an external electrode terminal provided at either side portion of the laminate. |
| US09196404B2 |
Soft magnetic powder, dust core, and magnetic device
A soft magnetic powder containing an amorphous alloy material having an alloy composition represented by Fe100-a-b-c-dMnaSibBcCd wherein a, b, c and d each represent a proportion in terms of percent by atom, and satisfy 0.1≦a≦10, 3≦b≦15, 3≦c≦15, and 0.1≦d≦3. |
| US09196402B2 |
Electronic component assembly comprising a varistor and a semiconductor component
An electric component assembly comprising a semiconductor component (1) and a carrier is specified, wherein the carrier contains a highly thermally conductive ceramic and is connected to a varistor body. Heat from the semiconductor component can be at least partially dissipated to the carrier (3) by means of the varistor body. |
| US09196401B2 |
Insulated wire having a layer containing bubbles, electrical equipment, and method of producing insulated wire having a layer containing bubbles
An insulated wire, containing: an insulating film made from a thermosetting resin disposed on a conductor directly or via an insulating layer interposed therebetween, in which the insulating film made from a thermosetting resin is a layer containing bubbles prepared by baking a varnish of thermosetting resin, and a layer containing no bubbles is formed as an upper or lower layer of the layer containing bubbles. |
| US09196400B2 |
Systems and methods for producing cable
One embodiment relates to a method for producing cable. The method includes applying an insulative coating to each of a plurality of conductors to form a plurality of insulated conductors. The method further includes taking up the plurality of insulated conductors in a twisting system to twist the plurality of insulated conductors together and apply a first portion of a desired twist to the plurality of insulated conductors. The method further includes paying off the plurality of insulated conductors from the twisting system to further twist the plurality of insulated conductors together and apply a second portion of a desired twist to the plurality of insulated conductors to form a twisted plurality of insulated conductors. |
| US09196399B2 |
Composite superconductor, and method for producing composite superconductor
A method for producing a composite superconductor includes: a structure forming process of forming a structure including a metal covering member (20) including at least one to-be-joined portion, a superconductor (30) arranged inside the metal covering member, and a reinforcing member (40) arranged between the superconductor (30) and the at least one to-be-joined portion; and a joining process of joining thereafter the at least one to-be-joined portion. |
| US09196398B2 |
Discontinuous shielding tapes for data communications cable
The present arrangement provides a communication cable having a plurality of twisted pair communication elements, a jacket surrounding the twisted pairs and a shield element disposed between the pairs and the jacket. The shield element is constructed as a tape substrate with a plurality of foil shielding elements disposed thereon, the foil shielding elements being formed in the shape of triangles and arranged on the substrate with at least a first foil shield element having a base of its triangle shape disposed substantially parallel to a longitudinal edge of the tape substrate. Each subsequent triangle is disposed on the tape substrate at a distance apart from the first triangle foil shielding element with a base of its triangle shape disposed substantially parallel to an opposite longitudinal edge of the tape substrate. |
| US09196394B2 |
Silicone multilayer insulation for electric cable
An electric cable made from at least one elongated electric conductor and a multilayer insulation surrounding the electric conductor. The multilayer insulation has a first semiconducting layer and an electrically insulating layer, where the two layers are made from a silicone rubber based composition. The semiconducting silicone rubber based composition of the first semiconducting layer has carbon rovings as conductive filler. |
| US09196392B2 |
Assembly conducting wire for rotary electric machine winding and rotary electric machine
An assembly conducting wire for a rotary electric machine winding includes a plurality of bundled wires, the plurality of wires being twisted in a circumferential direction of the assembly conducting wire, and the plurality of wires being welded together at a predetermined distance. |
| US09196391B2 |
Polyurea electrolyte and method for manufacturing the same
A polyurea electrolyte includes a polyurea resin formed by a polymerization of a first compound having two or more isocyanate groups and a second compound having two or more amino groups. The first compound or the second compound contains ten or more carbon chains, and the first compound or the second compound contains a sulfonic acid group or a carboxylic acid group. A method for manufacturing the polyurea electrolyte includes neutralizing the sulfonic acid group or the carboxylic acid group in the first compound or the second compound by a neutralizing agent; after the neutralizing, polymerizing the first compound and the second compound; and after the polymerizing, removing the neutralizing agent from a polymer of the first compound and the second compound. |
| US09196382B2 |
Semiconductor test device
A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit. |
| US09196380B2 |
Method for measuring data retention characteristic of resistive random access memory device
A method for measuring data retention characteristic of an RRAM device includes: a) controlling a temperature of a sample stage to maintain the RRAM device at a predetermined temperature; b) setting the RRAM device to a high-resistance state or a low-resistance state; c) measuring data retention time by applying a predetermined voltage to the RRAM device so that a resistive state failure of the RRAM device occurs; d) repeating the steps a)-c) to perform a plurality of measurements; e) calculating a resistive state failure probability F(t) of the RRAM device from the data retention time in the plurality of measurements; and f) fitting the resistive state failure probability F(t), and calculating predicted data retention time tE by using parameters obtained from the fitting. The data retention time of the RRAM device may be predicted by combining voltage acceleration and temperature acceleration. |
| US09196378B2 |
Semiconductor memory device and operating method thereof
A semiconductor memory device includes a fuse array block including a plurality of fuses programmed with state information, an operation direction control block suitable for controlling a program operation direction and a boot-up operation direction of the fuse array block, and a fuse information loading block suitable for loading the state information which is programmed in the plurality of fuses of the fuse array block through the boot-up operation. |
| US09196375B2 |
Semiconductor storage device
A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are electrically connected to control gates of the memory cells. A plurality of bit lines are electrically connected to one end of a current path of the memory cells. A sense amplifier part detects data stored in the selected memory cells. A power supply part converts an external power supply voltage to an internal power supply voltage and supplies the internal power supply voltage to the sense amplifier part. A power supply wire extends above the memory cell array and is provided to range from the power supply part to the sense amplifier part. |
| US09196373B2 |
Timed multiplex sensing
Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation. |
| US09196369B2 |
Communication device and communication method
A communication device includes: a communication unit configured to perform proximity communication with a reader/writer; and a control unit configured to control writing of data as to nonvolatile memory in accordance with a command from the reader/writer; with the control unit writing data in a buffer unit that serves as a buffer to buffer data to be written, in accordance with a command from the reader/writer, writing the unit number of an object unit that is a unit to be written with data as the unit number of the buffer unit, and taking the object unit as a new buffer unit, thereby performing writing of data in the object unit; and with the control unit being activated by an RF signal being received from the reader/writer, and erasing all of the pages of the buffer unit during activation processing to be performed before receiving a command from the reader/writer. |
| US09196367B2 |
Non-volatile memory apparatus and erasing method thereof
The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different. |
| US09196364B2 |
Nonvolatile memory device having split ground selection line structures
A nonvolatile memory device includes a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal. |
| US09196363B2 |
Semiconductor device
Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data. |
| US09196362B2 |
Multiple layer forming scheme for vertical cross point reram
Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers. |
| US09196361B2 |
Memory structure and operation method therefor
Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state. |
| US09196360B2 |
Operating resistive memory cell
A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source. |
| US09196358B2 |
Nonvolatile memory device using variable resistance material and method for driving the same
The nonvolatile memory device using a variable resistance material and a method for driving the same are provided. A first clamping unit connected between a resistance memory cell and a first sensing node to provide a first clamping bias to the resistance memory cell. The first clamping bias changes over time. A first compensation unit provides a compensation current to the first sensing node. A first sense amplifier is connected to the first sensing node to sense a level change of the first sensing node. In response to if first data stored in the resistance memory cell, an output value of the first sense amplifier transitions to a different state after a first amount of time from a time point from where the first clamping bias starts. In response to second data that is different from the first data stored in the resistance memory cell, the output value of the first sense amplifier transitions to the different state after a second amount of time that is different from the first amount of time from the time point from where the first clamping bias starts. |
| US09196351B2 |
Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks
A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot. |
| US09196348B2 |
Maintenance operations in a DRAM
A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order. |
| US09196346B2 |
Non-volatile memory with LPDRAM
Memory, systems and devices are disclosed where a non-volatile memory device (such as a Flash memory device) is paired with a LPDRAM memory device or array and configures the LPDRAM by utilizing routines stored in the non-volatile memory executing on a controller or state machine of the either the LPDRAM or non-volatile memory. This allows the configuration of the LPDRAM to be self contained and occur under local control of the controller or state machine of the non-volatile memory (or LPDRAM) utilizing these pre-stored LPDRAM configuration routines, eliminating the need for the system designer to have to account for and configure the LPDRAM and its specific configuration and/or routines with the system processor or operating system. |
| US09196343B2 |
Non-volatile semiconductor memory device
A non-volatile semiconductor memory device according to an embodiment includes a memory cell array including first lines, second lines, and memory cells each including a variable resistor and each connected between one of the first lines and one of the second lines, and a control circuit configured to perform a voltage application operation of applying a first voltage to a selected first line connected to a selected memory cell and applying a second voltage having a voltage value lower than the first voltage to a selected second line connected to the selected memory cell. The control circuit is configured to select the voltage value of the second voltage from among a plurality of different voltage values and output the second voltage. |
| US09196338B2 |
Magnetoresistive memory device with reduced leakage and high speed operation in an SoC
According to one embodiment, a magnetoresistive memory device includes first and second bit lines, a memory cell, a power supply line, first and second transistors, and third and fourth transistors. The memory cell has first and second magnetoresistive elements and is connected between the first and second bit lines. The power supply line is connected between the first and second magnetoresistive elements. The first and second transistors have current paths inserted in the first and second bit lines, respectively, and have gate electrodes connected, respectively to the second and first bit lines provided on a side opposite to the memory cell. The third and fourth transistors are inserted in the first and second bit lines. Gate electrodes of the third and fourth transistors are cross-coupled, and the third and fourth transistors are controlled by current from the memory cell. |
| US09196328B2 |
Semiconductor memory apparatus and operation method using the same
A semiconductor memory apparatus includes a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation, and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal. |
| US09196327B2 |
Data storage device, storage media controller and storage media control method
A storage media control method, by which a data strobe signal is shifted by different phase shifts at different time intervals during a write-leveling operation to be received by a storage media and compared to a clock signal for returning a data signal. At the storage media side, during the write-leveling operation, a synchronous transmission between the received data strobe signal and the clock signal causes a transition event at the data signal. The number of transition-event occurrences is counted. When the count shows that just one transition event has occurred over a full round of phase shift tests of the data strobe signal, the phase shift corresponding to the transition event is used in the adjustment of the data strobe signal, which is received by the storage media as the data extraction reference of a write operation. |
| US09196324B2 |
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank. |
| US09196322B2 |
Semiconductor memory device that does not require a sense amplifier
A semiconductor memory device that does not require a sense amplifier includes a memory cell group having at least one memory cell, a buffer unit, and a bias voltage unit. The buffer unit includes a tri-state buffer that has an input terminal coupled to the memory cell group, and an output terminal coupled to a data line unit. The tri-state buffer is operable to switch between a conducting state and a non-conducting state. The bias voltage unit controls supply of a preset bias voltage to the input terminal of the tri-state buffer. By using the tri-state buffer, the parasitic capacitance attributed to the memory cell can be reduced, such that no sense amplifier is required to ensure proper operation, thereby reducing power consumption. |
| US09196315B2 |
Three dimensional gate structures with horizontal extensions
A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure. |
| US09196314B2 |
Extended-height DIMM
An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for the DIMM and a maximum number of devices allowed to reside on the DIMM. The DIMM comprises a PCB having an edge connector designed to mate with a memory system slot and a height which is greater than the maximum height specified in the applicable standard, a plurality of memory devices which exceeds the maximum number of devices specified in the applicable standard, and a memory buffer which operates as an interface between a host controller's data and command/address busses and the memory devices. This arrangement enables the extended-height DIMM to provide greater memory capacity than would a DIMM which complies with the maximum height and maximum number of devices limits. |
| US09196306B2 |
Smart scaling and cropping
Smart scaling and cropping of video clips is disclosed. According to some implementations, a video clip sequence can be generated from one or more video clips. Video clips added to the video clip sequence can be automatically modified (e.g. scaled and/or cropped) to conform to the dimensions and/or aspect ratio of video clips in the video clip sequence. Video clips can be modified based on the spatial characteristics of the video clips, for example, the location and size of objects of interest (e.g., faces) in the video clips. Implementations may also include a method, system and/or non-transitory, computer-readable medium encoded with instructions for performing smart scaling and cropping. Other aspects and implementations are also disclosed. |
| US09196304B2 |
Method and system for providing dailies and edited video to users
A method for use in providing video to a user includes establishing digital video data that includes images shot in relation to a making of content, uploading the digital video data to a server, and sending the digital video data from the server through a network to a client device for viewing by the user. A system for use in providing video to a user and a storage medium storing a computer program executable by a processor based system are also disclosed. |
| US09196303B2 |
Feedthrough connector for hermetically sealed electronic devices
The present disclosure relates to an apparatus that includes an electrical connector that is coupled to a housing and that extends through a feedthrough aperture in the housing. The electrical connector has an electrically insulating base that has multiple layers of electrically insulating material with electrical traces extending between the multiple layers. The electrically insulating base also has a first portion disposed in the interior cavity, a second portion disposed external to the interior cavity, and a sealing portion disposed between the inwardly positioned portion and the outwardly positioned portion. The electrical connector also includes a first plurality of electrical leads that are disposed on the outwardly positioned portion of the electrically insulating base and a second plurality of electrical leads disposed on the inwardly positioned portion of the electrically isolating base material. Each of the electrical leads is electrically coupled to a corresponding lead. |
| US09196302B1 |
Electronic system with media maintenance mechanism and method of operation thereof
An apparatus includes: a media; a head over the media; a read channel, coupled to the head, configured to extract data from the media; control circuitry, coupled to the read channel, configured to execute a read command; and wherein the read channel is further configured to: generate, based on extracting the data from the media, a data condition indicator, and provide, for use by the control circuitry, the data and the data condition indicator. |
| US09196298B1 |
Zero phase start for array reader magnetic recording system
An apparatus includes an array reader with multiple of read heads operable to read a preamble pattern from a magnetic storage medium. A number of analog to digital converters are operable to sample an output of each of the read heads to generate digital data streams for the preamble pattern. A zero phase start calculation circuit is operable to calculate a phase offset between the digital data streams and to generate an integer phase adjustment signal and a fractional phase adjustment signal. |
| US09196297B2 |
Systems and methods for enhanced sync mark mis-detection protection
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream. |
| US09196291B2 |
Case, magnetic tape library apparatus and method of preventing housed object from falling
A case includes a case wall, a locking member and a moving member. The case wall has an opening so as to connect inside and outside of the case. The locking member can move to a locking position set inside the case and to an unlocking position different from the locking position. The moving member can move the locking member from the unlocking position to the locking position when a housed object housed in the case goes outside of the case through the opening. |
| US09196285B2 |
Magnetic recording medium fabrication method and apparatus
A method of fabricating a magnetic recording medium sequentially forms a magnetic recording layer, a protection layer, and a lubricant layer on a stacked body. The stacked body is enclosed in a transfer container unit without exposing the stacked body to atmosphere after forming the protection layer on the stacked body by a deposition apparatus, and the transfer container unit is transported to a vapor-phase lubrication deposition apparatus. The stacked body is removed from the transfer container unit without exposing the stacked body to the atmosphere, in order to form the lubricant layer on the stacked body within the vapor-phase lubrication deposition apparatus. |
| US09196283B1 |
Method for providing a magnetic recording transducer using a chemical buffer
A method for fabricating a magnetic recording transducer is described. The magnetic recording transducer has an underlayer and at least one layer on the underlayer. The layer(s) are capable of including an aperture that exposes a portion of the underlayer. The method includes providing a neutralized aqueous solution having a chemical buffer therein. The chemical buffer forms a nonionic full film corrosion inhibitor. The method also includes exposing a portion of the magnetic recording transducer including the layer(s) to the neutralized aqueous solution including the chemical buffer. In one aspect this exposure occurs through a chemical mechanical planarization. |
| US09196281B2 |
Perpendicular magnetic recording medium having tailored granular layers
A perpendicular magnetic recording medium is disclosed. The perpendicular magnetic recording medium includes a first layer, and a second layer positioned immediately below the first layer. Among the materials in the first layer and the second layer, if the interface energy when two different materials—material a and material b—are in contact is defined as Ei(a//b), the surface energy when material a exists independently is defined as Es(a), and the energy resulting by subtracting the sum of the respective surface energies (ΣEs) from the interface energy is defined as G(a//b), then when G(1//3) |
| US09196280B2 |
Low-field magnetic domain wall injection pad and high-density storage wire
Disclosed herein are magnetic storage devices and uses therefore. The devices comprise an injection pad and a nanowire extending from an outer edge of the injection pad. The injection pad and the nanowire of the disclosed magnetic storage devices have a geometry that is designed to optimize high density memory storage via low magnetic field domain wall shifting. The devices may be utilized, for example, for generating and storing magnetic domain walls for application in memory devices, sensor devices, and logic devices. |
| US09196278B1 |
Laser array for heat assisted magnetic recording
An apparatus comprises a unitary laser diode comprising an array of two or more active regions, at least one of which outputs a light beam in response to an input current. The apparatus also includes two or more waveguides, each waveguide corresponding to an active region of the array. At least one of the waveguides receives the at least one light beam from the at least one active region. |
| US09196276B2 |
Head gimbal assembly and disk unit provided with the same
A head gimbal assembly includes a load beam, a wiring member including a metal plate disposed on the load beam, a magnetic head attached to a tip section of the wiring member, and a piezoelectric element that is fixed to and supported by supporting pads and deforms in response to a voltage applied thereto. The metal plate includes a tip section to which the magnetic head is fixed, and a base section that is spaced apart from the tip section and is fixed to the load beam. The supporting pads include first and second supporting pads proximate to the tip section and distal from the base section and a third supporting pad proximate to the base section and distal to the tip section, each of supporting pads separated from and independent of both the tip section and the base section. |
| US09196275B1 |
Magnetic head separator fin material to prevent particulate contamination on slider
An apparatus for a magnetic storage drive includes a magnetic head assembly having a first slider and a second slider arranged with a gap between the first and second sliders, the first slider comprising a first magnetic head and the second slider comprising a second magnetic head. The apparatus includes a ramp constructed of a first material, the ramp being configured to guide and hold the magnetic head assembly in place when parked; and a fin constructed of a second material different than the first material, the fin arranged with the ramp to protect the first slider from contacting the second slider when the magnetic head assembly is parked on the ramp. |
| US09196269B2 |
Heat sink layer along an aperture of a near-field transducer
A recording head includes a near-field transducer proximate a media-facing surface. The near-field transducer includes an aperture surrounded by walls of plasmonic material and a notch protruding within the aperture. The walls are oriented normal to the media-facing surface. A write pole is proximate the near-field transducer. The write pole has a back surface facing away from the media-facing surface and an aperture-facing surface proximate the aperture. A heat sink layer of the plasmonic material is disposed along the back surface and the aperture-facing surface of the write pole. The heat sink layer is thermally and optically coupled to the near-field transducer. |
| US09196264B2 |
Products with tape formats having one or more spare areas and apparatuses configured for use with such products
An apparatus includes a magnetic head having an array of transducers. The apparatus is configured to read and/or write to a magnetic recording tape according to a format. The format specifies a number of active channels and a contiguous spare area on the magnetic recording tape. The format also specifies compatibility with a second format. The second format specifies a different number of active channels than the number of active channels specified by the format. A product includes a magnetic recording tape and data stored on the product specifying the aforementioned format. |
| US09196251B2 |
Contextual conversion platform for generating prioritized replacement text for spoken content output
A contextual conversion platform, and method for converting text-to-speech, are described that can convert content of a target to spoken content. Embodiments of the contextual conversion platform can identify certain contextual characteristics of the content, from which can be generated a spoken content input. This spoken content input can include tokens, e.g., words and abbreviations, to be converted to the spoken content, as well as substitution tokens that are selected from contextual repositories based on the context identified by the contextual conversion platform. |
| US09196246B2 |
Determining word sequence constraints for low cognitive speech recognition
A method for recognizing speech including a sequence of words determines a shape of a gesture and a location of the gesture with respect to a display device showing a set of interpretations of the speech. The method determines a type of the word sequence constraint based on the shape of the gesture and determines a value of the word sequence constraint based on the location of the gesture. Next, the speech is recognized using the word sequence constraint. |
| US09196245B2 |
Semantic graphs and conversational agents
Semantic clustering techniques are described. In various implementations, a conversational agent is configured to perform semantic clustering of a corpus of user utterances. Semantic clustering may be used to provide a variety of functionality, such as to group a corpus of utterances into semantic clusters in which each cluster pertains to a similar topic. These clusters may then be leveraged to identify topics and assess their relative importance, as for example to prioritize topics whose handling by the conversation agent should be improved. A variety of utterances may be processed using these techniques, such as spoken words, textual descriptions entered via live chat, instant messaging, a website interface, email, SMS, a social network, a blogging or micro-blogging interface, and so on. |
| US09196244B2 |
Methodology for enhanced voice search experience
Arrangements are described for reducing response latency in intelligent personal assistant applications. While receiving a user request, preemptive responses are automatically prepared for a received portion of the user request. Partial classification word candidates are generated for words in the received portion of the user request, and then a predictive component is applied to generate extended classification word candidates that include the partial classification word candidates and additional classification word candidates. A preliminary search is performed of the extended classification word candidates to prepare the preemptive responses. While the input request continues, the preemptive responses are updated, and when the input request ends, the prepared preemptive responses are used to respond to the user request. |
| US09196243B2 |
Method and system for efficient spoken term detection using confusion networks
Systems and methods for spoken term detection are provided. A method for spoken term detection, comprises receiving phone level out-of-vocabulary (OOV) keyword queries, converting the phone level OOV keyword queries to words, generating a confusion network (CN) based keyword searching (KWS) index, and using the CN based KWS index for both in-vocabulary (IV) keyword queries and the OOV keyword queries. |
| US09196241B2 |
Asynchronous communications using messages recorded on handheld devices
Methods, systems, and computer program products are provided for asynchronous communications. Embodiments include receiving a recorded message, the message recorded on a handheld device; converting the recorded message to text; identifying a recipient of the message in dependence upon the text; associating the message with content under management by a library management system in dependence upon the text; and storing the message for transmission to another handheld device for the recipient. Embodiments also typically include recording a message on handheld device and transferring a media file containing the recorded message to a library management system. Embodiments also typically include transmitting message to another handheld device. |
| US09196240B2 |
Automated text to speech voice development
A group of users may be presented with text and a synthesized speech recording of the text. The users can listen to the synthesized speech recording and submit feedback regarding errors or other issues with the synthesized speech. A system of one or more computing devices can analyze the feedback, modify the voice or language rules, and recursively test the modifications. The modifications may be determined through the use of machine learning algorithms or other automated processes. |
| US09196232B2 |
Self-compensating tunable bridge for string musical instrument
A tunable bridge for a string musical instrument is provided to enable a user to rapidly switch between two pre-selected string tunings simply by movement of an actuator arm. The actuator arm controls the position of a cam roller assembly, which in turn controls the pivotal movement of a rocker arm between a lower position and an upper position. A multiplicity of string fingers are mounted for pivotable movement between respective first and second tuning positions. A plurality of manually-adjustable tuning screws with engagement tips are threadedly disposed in the rocker arm. Each engagement tip is configured to press against a respective string finger when the rocker arm is placed in its upper position, thereby further stretching the strings attached to the respective string fingers and increasing their pitch in accordance with the second pre-selected tuning. Mounting of the tunable bridge does not require permanent modification of the string instrument. |
| US09196231B2 |
Capo for a dobro, slide guitar, Hawaiian guitar, or similar raised string instrument
A capo for an instrument having a plurality of strings elevated above a fretboard such as a dobro, slide guitar, Hawaiian guitar, or similar raised stringed instrument. This capo uses a sliding wedge adjuster that is installed in the upper milled slot of bar member. The sliding link assembly is installed thru the sliding wedge adjuster slot, into the hole in the center of bar member aligned properly. The string tension bar is installed in sliding link assembly hole and cushion tubes are installed on tension rod, each side of sliding link assembly. The sliding wedge adjuster raises the sliding link assembly as sliding wedge adjuster is pushed inward into bar member. This action compresses the strings to bottom of bar member. This sliding wedge function is unique to this improved capo. |
| US09196230B1 |
Sympathetic parallel plate resonator for acoustic instruments
The disclosed invention is provides a simple, easily installed means to produce an improved quality of sound timbre in acoustic instruments at increased volume and increased audible sustain by the removable attachment of a suitable sympathetic resonator. |
| US09196229B1 |
Piano desk cover
The piano desk cover that is configured to be placed over a piano desk in order to protect the finish of the piano desk from scratches or marring. The piano desk cover includes end flaps on distal ends that are configured to engage ends of the piano desk. Each end flap includes an end flap strap that is configured to extend underneath the piano desk, and secure to an inner surface of the end flap so as to secure the respective end of the piano desk cover to the piano desk. The piano desk cover also includes a tensioning flap that extends down a middle of the piano desk cover. The tensioning flap includes a tensioning strap so as to secure the middle portion of the piano desk cover to the piano desk. |
| US09196228B2 |
Image displaying apparatus and image displaying method
An image displaying apparatus is provided, which includes: a display unit that displays an image, and which has a horizontal width and a vertical width; an image processing unit which processes the image; and a controller which controls the image processing unit, if an aspect ratio of the image is different from an aspect ratio of the display unit, to extend the image in a first direction until a horizontal width or a vertical width of the image becomes identical to any one of the horizontal width and the vertical width of the display unit, to extend the image in a second direction to maintain the aspect ratio of the image, and to move the extended image in the second direction on the display unit. |
| US09196227B2 |
Selecting techniques for enhancing visual accessibility based on health of display
In a computer system having a display screen configured to display visual content, a plurality of techniques may be identified to be considered for enhancing visual accessibility of a particular collection of visual content to be displayed to an end user on the display screen. For each technique, an algorithm may be applied to compute one or more measures of health of the display of the particular collection of visual content resulting from applying the respective technique to enhance the visual accessibility of the particular collection of visual content. Based at least in part on the computed measures of health, one or more best techniques may be selected and applied to enhance the visual accessibility of the particular collection of visual content. The enhanced particular collection of visual content may be displayed to the end user on the display screen. |
| US09196224B2 |
Managing obstructed views of multiple display surfaces
Embodiments of systems and methods for managing multiple overlapping electronic displays are disclosed, including the electronic displays of electronic paper, electronic books, computer monitors, and other electronic display devices. In one embodiment, a method includes sensing an overlap area of a first display and a second display relative to a specified view location, determining a nearest unobstructed display to the specified view location, and displaying within the overlap area of the nearest unobstructed display a highest priority information from among first and second information. |
| US09196221B2 |
Display device, and driving circuit and method thereof
A display device includes L number of display panels where L is a positive integer greater than 1; a driving circuit having L number of controllers for driving the respective display panels; and a central control unit configured to control the driving circuit. The controllers are configured to be synchronized with one another based on a clock signal from the central control unit, and each of the controllers is configured to sequentially and continuously select each one of K number of lines (where K is a positive integer greater than 1) arranged in a row in the corresponding display panel, and allow the selected line to emit light. Further, a direction for sequentially and continuously selecting each one of the lines is set to be the same in all the display panels. |
| US09196216B2 |
Frame buffer management and self-refresh control in a self-refresh display system
A system and method are disclosed is to prevent the screen tearing in a video display system with self-refresh features while limiting space used for memory size in the self-refreshing sink device. A flexible method is utilized to manage a frame buffer and control self-refresh display timing to prevent screen tearing. The sink device has capabilities including one or more of self-refreshing and applying single frame updates as well as burst single frame updates while self-refresh is active. The memory utilized by the frame buffer during self-refresh is limited to less than that needed to store two full frames of video. |
| US09196215B2 |
Power converters and E-paper devices using the same for providing a plurality of voltages
A display device including an e-paper device and a power converter is provided. The e-paper device displays information. The power converter generates a plurality of output voltages respectively at a plurality of output terminals and provides the plurality of output voltages to the e-paper device. The power converter includes a transformer and a plurality of diodes. The transformer has a primary winding and a plurality of secondary windings. The diodes are electrically connected between the secondary windings and the output terminals for generating the output voltages, respectively. |
| US09196214B2 |
Display device
A display device is characterized by including a first storage section (60) for storing first image data which a display element displays on the display screen next, a second storage section (61) for storing second image data which the display element is displaying on the display screen, a difference calculation section (71) for calculating the difference data between the second image data and the first image data, a third storage means (62) for storing the difference data calculated by the difference calculation section, and a control section for controlling a current value or writing time and the direction in which a writing current is supplied to the display element according to the difference data. |
| US09196207B2 |
System and method for controlling the slew rate of a signal
Techniques for controlling the slew rate of a signal independently of RC time constants are disclosed. In one embodiment, a gate driver circuit for an LCD panel may include a rail-to-rail operational amplifier having an output stage configured to produce a gate activation signal for switching pixels of the LCD panel. A slew rate control circuit may be provided for adjusting the slew rate of the gate activation signal by varying a bias current of the output stage relative to a compensation capacitance and a gain of the operational amplifier. For instance, the slew rate may be increased by increasing the bias current, and decreased by decreasing the bias current without the need to adjust RC variables. |
| US09196203B2 |
Device and system for a multi-color sequential LCD panel wherein the number of colors in a sequence of display colors is greater than the number of LED colors
A sequential color LCD device for displaying a color image using at least four different primary colors, with back illumination system comprising of at least three color LEDs. The device is capable of activating at least two color LEDs simultaneously, thus obtaining additional display colors. A method is disclosed for displaying more than three colors using an LCD device having three color LEDs, in which the LED back illumination system sequentially illuminates the LC array with only a first single LED color, a simultaneous operation of first and second LED colors, and then only the second LED color. The device may drive the LC cells from a first color data value directly to a subsequent color data value directly, without driving the LC cell to zero transmittance prior to loading of the subsequent color data value. The device may correct for color phase shift and for the dependency of apparent color intensity. |
| US09196200B2 |
Method of establishing look-up table for electrophoretic display and device thereof
A method of establishing a look-up table for an electrophoretic display is disclosed. The method is for establishing a plurality of driving waveforms of the electrophoretic display to the look-up table. The method includes dividing the plurality of driving waveforms to a plurality of time intervals according to a plurality of voltage values of the plurality of driving waveforms. The method also includes preparing a plurality of voltage waveform records according to the plurality of the voltage values and numbers of a unit times of the corresponding time intervals, and storing the plurality of voltage waveform records into the look-up table. Therefore, the storing capacity occupied by the look-up table of the electrophoretic display may be saved. |
| US09196197B2 |
Display device and method for driving the same
A display device includes a first sub-pixel and a second sub-pixel configured to share one data line, a first transistor configured to turn on or off by a first control signal and configured to couple the first sub-pixel to the one data line, and a second transistor configured to turn on or off alternately with the first transistor by a second control signal having a phase difference from that of the first control signal and configured to couple the second sub-pixel to the one data line. |
| US09196193B2 |
Display device including RGBW sub-pixels and method of driving the same
A display device includes a data mapping unit for extracting a minimum value among three-color input data which respectively correspond to red, green, and blue, determining white color output data by multiplying the extracted minimum value by a gain ratio, and determining red, green, and blue color output data respectively by subtracting the white color output data from the three-color input data; and a gain adjustment unit for determining the gain ratio to minimize a standard deviation respectively for the white color output data and the red, green, and blue color output data. |
| US09196192B2 |
Display device, power control device, and driving method thereof
A display device includes a plurality of pixels and a power supply controller that includes a first power supply source unit supplying a high power supply voltage, and a second power supply source unit supplying a low power supply voltage. The high power supply voltage is different from the low power supply voltage. The power supply controller connects one of the first and second power supply source units to the plurality of the pixels. The one of the first and second power supply source units is switched to another of the first and second power supply source units at a switching time, at which the one of the first and second power supply source units stops operation. |
| US09196183B2 |
Display device for high-speed data transmission and method of driving the same
A display device is provided. The display device includes: a timing controller and a data driver. The timing controller is configured to receive input data, a main clock signal, a synchronization signal, or a protocol signal, to generate an internal clock signal by using the main clock signal, to convert the input data into image data, and to transmit the synchronization signal or the protocol signal using the internal clock signal. The data driver is configured to recover the synchronization signal or the protocol signal from the internal clock signal, and to drive the image data by using the recovered synchronization signal or the protocol signal. |
| US09196180B2 |
Identification system for a surface
There is provided an identification system for identifying a predetermined surface for dynamic content control in a broadcast system. The system comprises at least one emitter element arranged to transmit an identification signal which is invisible with respect to the predetermined surface, and which comprises identification data regarding the outline of the predetermined surface. |
| US09196178B2 |
Device comprising a multilayer structure and rollers
The invention relates to a device comprising a multilayered structure with a first portion and a second portion wherein the first portion is conceived to be rolled about a first roller, said device comprising a second roller for receiving the second portion for at least partially counteracting the effects of mechanical strain induced in the multilayered structure upon said rolling. The first roller is rotated in a first direction, whereby the second roller is rotated in a second direction. Preferably, the diameters of the first roller and the second roller are equal. Alternatively, the edge portions A, B of the multilayer structure are suitably interconnected by stoppers for preventing creeping. |
| US09196177B2 |
Display for multiple types of door handles
A display assembly may be fitted with display advertisements. The assembly may be affixed to pre-existing cooler doors, including those that do not permit a bracket to completely surround it. |
| US09196176B2 |
Systems and methods for training one or more training users
Systems and methods for training users. Surgical data related to surgical procedures done by expert level users is collected from surgical robots. The surgical data is segmented into surgemes and dexemes. The training users are trained at a level of the surgemes and/or a level of the dexemes by guiding the training users with surgical simulators to practice the surgemes and/or the dexemes, wherein the surgical simulators simulate surgery done by an expert level user. |
| US09196175B2 |
Ergonomic sensor pad with feedback to user and method of use
A portable system is provided for sensing and training a user to maintain correct posture while seated in a chair with a seat portion and a back portion. The system includes a first pad attachable to the seat portion of a chair, said first pad having a front area and a rear area, and a second pad attachable to the back portion of a chair and having a lower area and an upper area. There is a first sensor located in the first pad capable of sensing that a user is seated in the seat portion of the chair, a second sensor located in the first pad capable of sensing whether the lower posterior portion of the user's body is in contact with the rear area of the first pad, a third sensor operably attached to the lower area of the second pad capable of sensing whether the user's lumbar region is in contact with the second pad, a fourth sensor operably attached to the upper area of the second pad capable of sensing the distance between the user's upper back and the upper area of the second pad and a neck-position sensor operably attached to the second pad and capable of sensing the distance between the neck-position sensor and the user's neck. The system also includes a microprocessor operably connected to the first sensor, second sensor, third sensor, fourth sensor and neck-position sensor and capable of collecting data from each of the first sensor, second sensor, third sensor, fourth sensor and neck position sensor. The system also includes software for a personal computer, which configures the personal computer to receive the data from the microprocessor and to display the data received from the microprocessor, so that the user can utilize the ergonomic seat pad to receive feedback regarding his posture and over time, improve his posture. |
| US09196173B2 |
Visualizing the mood of a group of individuals
Techniques are described for visualizing the mood of a group of individuals. In one example, a graphical display is divided into regions representing different emotions. Input indicative of an emotion is received from individuals located in an area of interest. As the input is received, a set of indicators is output in each of the regions of the graphical display. Each indicator represents a different one of the individuals who is experiencing the emotion associated with the region in which the indicator is displayed and is displayed with a color assigned to the emotion. The indicators are animated to move over time toward a center of the graphical display and are removed upon reaching the center of the graphical display. In this way, the graphical display depicts a current mood for the group and indicates a rate of change of each of the different emotions. |
| US09196172B1 |
Weight loss systems and methods
Weight loss methods and systems are described. In one embodiment, behavior modification program data indicating participation in a weight loss behavior modification program is recorded. Drug therapy program data indicating drug fulfillment of a weight loss drug therapy program drug is recorded, in which the drug fulfillment of the weight loss drug therapy program drug occurs after participation in the weight loss behavior modification program. Whether a weight loss surgical program criterion has been met is determined based on analysis of the behavior modification program data and the drug therapy program data. The weight loss surgical program criterion is based on the participation in the weight loss behavior modification program and the drug fulfillment of the weight loss drug therapy program drug. A surgical weight loss program approval is generated based on a determination that the surgical weight loss program criterion has been met. Additional methods and systems are disclosed. |
| US09196170B2 |
Multi-purpose digital coloring tools
Multi-purpose digital coloring tools for interacting with a touch screen are described. A pattern-making device provides for patterned input from a digital marking tool on a touch-screen device. The pattern-making device guides the digital marking tool with a plurality of gear teeth on an internal edge of a template frame secured to a touch-screen device using a base unit. Light images are created by a light stylus that interacts with a touch-screen device or an emulsion-surface device. An easel support structure holds a touch-screen device in an upright position during marking with the digital marking tool. Digitally animated coloring book pages are adapted to interact with a touch-screen device. Digital crayons, digital stamping devices, a digital paintbrush, a dual-tip digital stylus for creating 3-dimensional (3-D) images, and a pair of 3-D glasses are provided for interacting with a touch-screen device. |
| US09196169B2 |
Importing and analyzing external data using a virtual reality welding system
A real-time virtual reality welding system including a programmable processor-based subsystem, a spatial tracker operatively connected to the programmable processor-based subsystem, at least one mock welding tool capable of being spatially tracked by the spatial tracker, and at least one display device operatively connected to the programmable processor-based subsystem. The system is capable of simulating, in virtual reality space, a weld puddle having real-time molten metal fluidity and heat dissipation characteristics. The system is further capable of importing data into the virtual reality welding system and analyzing the data to characterize a student welder's progress and to provide training. |
| US09196168B2 |
Collision avoidance and warning system
A collision avoidance and warning system for a helicopter uses a type of emitted energy, for example radio frequency radar, from a transceiver positioned to cover a selected field of view for detecting an object or pedestrian in the vicinity of the helicopter. For helicopters that include a tail rotor assembly, the selected field of view can include a region around the tail rotor assembly so that when the helicopter is running on the ground, an alarm can be issued to persons approaching the tail rotor assembly. When the helicopter is in flight, the collision avoidance and warning system can alert the pilot when a portion of the helicopter outside of the pilot's field of view is in danger of a collision with an object. |
| US09196167B2 |
Process and device for managing the activating of a warning message in an aircraft
A process for managing the activating of emission of a given warning message in an aircraft comprises transmission, from a monitoring system to an authorization-issuing system, of an emission authorization request. The request has a priority attribute known as request priority attribute. The process also includes transmission, from the authorization-issuing system to the monitoring system, of an emission authorization. The transmission of the emission authorization is effected if the request priority attribute is higher than a current priority threshold. In addition, the process includes activation of emission of the given warning message. The activation may be effected if an alert condition associated with the given warning message is detected and if a priority attribute associated with the alert condition is higher than or equal to the request priority attribute. |
| US09196162B2 |
Vehicular driving support system
It is a task of the invention to provide an art that makes it possible to provide driving support suited for the feeling of a driver in a system that supports the avoidance of a collision of a vehicle. In order to achieve this task, according to the invention, in a system that supports the avoidance of a collision of a vehicle, a traveling range as a range of a route on which a host vehicle is to travel in a range of a driving operation to be normally performed by a driver is obtained, driving support is not provided if there is a route that allows a solid body to be avoided within the traveling range, and driving support is provided if there is no route that allows the solid body to be avoided within the traveling range. |
| US09196160B2 |
Vehicle detection apparatus and vehicle detection method
A vehicle detection apparatus according to an embodiment comprises a controller detecting a vehicle from an image obtained by photographing the vehicle. The controller extracts a plurality of line-segment components indicating a boundary between a specific region of the vehicle and a vehicle body and included in the image. The controller measures a position of the vehicle based on coordinate information between the extracted line-segment components and photographing position information of the image. |
| US09196151B2 |
Encoding location-based reminders
Systems and methods for encoding location-based reminders are provided. Data indicative of a request for a location-based reminder can be received. The data indicative of the request can include data indicative of a user placement of a reminder in a visual representation of the geographic area, such as an image captured of the geographic area or a visual representation of the three-dimensional model of the geographic area. A selected location within a three-dimensional model of a geographic area can be identified based on the data indicative of the user placement of the reminder. Three-dimensional geographic coordinates corresponding to the selected location can be determined using the three-dimensional model and associated with the location-based reminder. The location-based reminder can then be triggered based at least in part on signals indicative of user position and/or orientation in the geographic area. |
| US09196149B2 |
Mobile device alert generation system and method
A computer-implemented method for providing an alert regarding mobile device location is provided. The method includes obtaining location data corresponding to locations of a mobile device over a period of time. A location pattern is determined based on the location data. The current location of the mobile device is detected at a time based on the determined pattern, and an alert is provided regarding the current location of the mobile device. A system for providing alerts regarding mobile device location is also provided. |
| US09196148B1 |
Location based monitoring system alerts
Monitoring system alert technology, in which monitoring system data is accessed from a monitoring system that is located in a property of a user and the monitoring system data is analyzed against one or more rules that define alerts provided for the monitoring system. Based on the analysis, a determination is made that an alert for the monitoring system is needed and conditions for providing the alert are accessed. Location of a mobile device of a user associated with the monitoring system and timing related to providing the alert are monitored. The monitored location of the mobile device and the monitored timing are analyzed with respect to the accessed conditions. Based on the analysis, a determination is made that the accessed conditions for providing the alert are met and the alert is output at the mobile device. |
| US09196147B1 |
Automated object analysis system
A method and apparatus for analyzing movement of objects in a border area. Information about the movement of the objects in the border area is identified from sensor data. The information about the movement of the objects in the border area is compared with movement information for the border area to form a comparison. An alert is generated when the comparison indicates that an object of interest in the objects is present. |
| US09196145B2 |
Method and system for automated location dependent natural disaster forecast
A forecast system and method for automated location dependent natural disaster impact forecasts includes located gauging stations to measure natural disaster events. Location dependent measurement parameters for specific geotectonic, topographic or meteorological conditions associated with the natural disaster are determined and critical values of the measurement parameters are triggered to generate a dedicated event signal for forecasted impacts of the disaster event within an area of interest. In particular, the signal generation is based upon the affected population or object within the area of interest. |
| US09196143B2 |
Mobile device, method and non-transitory computer-readable storage medium for monitoring a vehicle path
The invention discloses a mobile device for monitoring a vehicle path. The mobile device includes a setting module, a satellite-positioning module, a determination module, and an alarm module. The setting module is configured to set a preset route from a starting point to a destination. The satellite-positioning module is configured to receive a satellite-positioning signal. When the mobile device is located in a vehicle, the determination module is configured to determine whether the vehicle is driving along the preset route based on the satellite-positioning signal. When the vehicle deviates from the preset route for a default alarming time, the alarm module is configured to perform an alarm action. |
| US09196142B2 |
Method and system for managing consumption of heterogeneous resources
A method for managing consumption of heterogeneous resources includes: receiving resource consumption information of a target; calculating a total energy consumption value that is associated with the target based on the resource consumption information of the target; generating a high consumption alert when the calculated total energy consumption value is higher than a first predetermined threshold value; and generating a low consumption alert when the calculated total energy consumption value is not higher than a second predetermined threshold value that is lower than the first predetermined threshold value. |
| US09196137B2 |
Two-way wireless communication enabled intrusion detector assemblies
A wireless door intrusion detection assembly including a magnet component installed on a door, and a fixed magnetic contact wireless transceiver component installed on a door frame corresponding to the door, opposite the magnet component, the fixed magnetic contact wireless transceiver component including a two-way transceiver element operable for two-way wireless communication between the fixed magnetic contact wireless transceiver component and an intrusion alarm system, an antenna facilitating the two-way wireless communication between the fixed magnetic contact wireless transceiver component and the intrusion alarm system, and an antenna ground reference plane, opposite the antenna. |
| US09196136B2 |
Device and method for monitoring locking devices
Disclosed is a lock monitor module for attachment to a locking device, comprising: a sensor in communication with a detection unit for generating a locking device status signal representative of a locked state, an unlocked state, a tampered state, or a distressed state of the locking device, the sensor proximate to a lock component of the locking device; a lock monitor and evaluation software app in communication with the detection unit for receiving the locking device status signal; and a transceiver for transmitting at least one of an alarm signal and a notification signal in response to the locking device status signal. |
| US09196131B2 |
Electronic gaming machine and gaming method
An electronic gaming machine has an electronic game controller and a display where game symbols are arranged in an array of predetermined game positions. The appearance of a first special symbol causes a group of predetermined game positions to be selected where each game symbol occupying a predetermined game position in said group is changed into a second special symbol either during a play of a game or at the completion of said play, said change into said second special symbol being visible to said player. A gaming method is also provided. |
| US09196128B2 |
Game apparatus and computer-readable recording medium
A game apparatus accepts a bet by a player on a betting target from among multiple betting targets. For each target, odds indicating a winning allotment in a first game are set. A drawing is conducted for the first game. According to the result of the drawing, a game medium is paid out. A stake is calculated for a second game whose payout ratio is 1, taking into account, along with a number of bet game media, a difference between a position payout ratio, which serves as a winning allotment expectation value per unit of game media, for the betting target bet on by the player, and a set payout ratio. |
| US09196120B2 |
System and method to award gaming patrons based on actual financial results during gaming sessions
This disclosure relates to a system configured to award a gaming patron based on gaming session financial results of the patron. The system may be configured to obtain game play information for the gaming session of the patron. The system may be configured to determine an actual financial amount lost by the patron and a theoretical financial loss amount based on the game play information. The system may use the actual financial loss amount and the theoretical financial loss amount to determine whether the patron is eligible for an award. Responsive to the patron being eligible for an award, the system may determine an award and then award the patron via a mobile computing device associated with the patron. In some implementations, the system may include one or more of a game, a game play sensor, a processor, a mobile computing device, electronic storage, external resources, and/or other components. |
| US09196119B2 |
Second player bonus game
In one embodiment, a method includes determining an event at a gaming device during game play for a first player. One or more bonus event symbols are determined in response to the event. The method sends the one or more bonus event symbols for a bonus game to a second player. When one or more of the bonus event symbols match a predetermined outcome, the second player is awarded a bonus award. In one embodiment, a method includes receiving a bonus event symbol from a second gaming device during game play on a first gaming device for a first player. It is determined if the bonus event symbol provides a match to a predetermined outcome. The first player is awarded a bonus award if the match is determined. |
| US09196117B2 |
Game support system and method
A game support system includes a DB server for storing in a DB user information including a user's unique identification and the user's own money, a web server for posting information about a plurality of game rooms, and a game processing server for admitting the user to a game room selected by the user from among the plurality of game rooms and processing a game in the selected game room. The game support system further includes a participation money designation server for providing an input window to allow the user to designate a part of the user's own money as participation money required for participation in the selected game room. The system, for example, allows the user to continue to play a game without moving out to another portal or game site. |
| US09196110B2 |
System and method for dynamic FOB synchronization and personalization
A system generally for personalizing and synchronizing fob data in the context of a distributed transaction system is disclosed. A dynamic fob synchronization system may comprise point of service (POS) devices configured with transponder-readers to initiate a transaction in conjunction with a fob, an enterprise data collection unit, and a fob object database update system. In an exemplary embodiment, a dynamic synchronization system (DSS) may comprise a personalization system and an account maintenance system configured to communicate with a fob object database update system (FODUS). Personalization of multi-function fobs may be accomplished using a security server configured to generate and/or retrieve cryptographic key information from multiple enterprise key systems during the final phase of the fob issuance process. |
| US09196103B2 |
Entry technology for building automation
A computer system accesses identity data providing unique biometric identifications and associated names for respective people. Roles are stored and associating ones of the roles are associated with ones of the people. Rules are stored, wherein each rule is configured to define one of the roles or people and define a condition and an action. The computer system receives from a device at an entryway, biometric data for a person. A named person is indicated for the received biometric data by the identity data accessed by the computer system. The computer system selects a rule corresponding to the identified person or to one of the defined roles for the identified person. The computer system performs the defined action for the selected rule when a current condition satisfies the defined condition for the selected rule. |
| US09196100B1 |
Equipment architecture for high definition data
Sensor information is received from a set of sensors. First and second sets of machine monitoring data are generated from the sensor information. The first set of machine monitoring data is sent to a control system with a display in an operator compartment of a mobile machine. The second set of machine monitoring data is sent to a processing system that is separate from the control system. |
| US09196094B2 |
Method and apparatus for augmented reality
A method for providing an augmented reality includes capturing a real image from information contained in a visible light; generating a virtual image from the captured image; displaying on an augmented reality device a view selected from the group consisting of the real image and the virtual image; displaying the view of the real image in response to detection of a motion; and displaying the view of the virtual image in the absence of detected motion. An augmented reality device and a computer program product are disclosed. |
| US09196091B2 |
Image processing method and system
A method of displaying images representative of image data includes providing a user interface for displaying a three-dimensional (3D) image and at least one two-dimensional (2D) image, setting a volumetric field of view for the 3D image, setting a respective further field of view for the at least one 2D image, and linking the volumetric field of view and the at least one further field of view so that a movement of the volumetric field of view of the 3D image automatically causes a corresponding movement of the further field of view of the at least one 2D image, and so that a movement of the further field of view or at least one of the field of view of the at least one 2D image automatically causes a corresponding movement of the volumetric field of view of the 3D image. |
| US09196088B2 |
System and method for classification of three-dimensional models in a virtual environment
A method for classification of three-dimensional structures in a virtual environment includes identifying a plurality of polygons in a structure located in a virtual environment, identifying a plurality of surface normals, each surface normal corresponding to one polygon in the plurality of polygons that are in the structure, identifying a variance of a distribution of the plurality of surface normals, generating a first classification for the structure in response to the variance being less than a predetermined threshold, and generating a graphical display of the structure with at least one visual aspect of the structure being modified with reference to the first classification. |
| US09196087B2 |
Method and apparatus for presenting geo-traces using a reduced set of points based on an available display area
An approach is provided for presenting geo-traces using a reduced set of points based on an available display area. The trace platform determines a reduced set of one or more points based on an available display area of a user interface. Next, the trace platform causes, at least in part, a presentation of at least one geo-trace in the user interface based, at least in part, on the reduced set. |
| US09196083B2 |
Time-continuous collision detection using 3D rasterization
A PCS culling technique may be augmented utilizing a motion blur (three-dimensional) rasterizer. The culling technique can be used for continuous collision detection. |
| US09196080B2 |
Medial axis decomposition of 2D objects to synthesize binocular depth
A computer-based method for generating a stereoscopic image from a two dimensional (2D) image such as a 2D cell animation. An object is selected in the 2D image, such as an animated character, and is stored in memory as the base image. With an erosion engine, the selected object is eroded to generate a set of eroded versions of the base image corresponding to a number of erosion levels. Each erosion level image may be formed by eroding or removing a set of outer or edge pixels from the image on the prior level. The method continues with calculating a parallax shift value for each of the eroded versions of the base image. An alternate eye image is then generated by compositing the set of eroded versions along with the base image. The eroded versions are horizontally offset from the base image by the level-specific parallax shift values. |
| US09196079B2 |
Accelerated compute tessellation by compact topological data structure
A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives. A hull shader is modified to compute values used by the new shaders to perform tessellation algorithms. This approach provides parallelism and customizability to the presently static tessellation engine implementation. |
| US09196077B1 |
Efficient inter-processor communication in ray tracing
Novel method and system for distributed database ray-tracing is presented, based on modular mapping of scene-data among processors. Its inherent properties include matching between geographical proximity in the scene with communication proximity between processors. |
| US09196076B1 |
Method for producing two-dimensional animated characters
A method for producing a two-dimensional (2D) animated character sequence is provided. The method includes producing a set of 2D drawings that represent one or more views of the body parts of the character being represented, analyzing an animated sequence of a three-dimensional (3D) armature in order to determine the motion of an animated character in 3D space over time, using a selection operation to determine which particular view of each body part to use to best represent that body part at any particular moment in time in the animated sequence, performing a projection operation for each bone of the armature in order to determine where, on a 2D plane, the selected drawing should be placed in a 2D animation frame, and assembling the selected body part drawings in order to produce the frames of a 2D animated character. |
| US09196074B1 |
Refining facial animation models
A system includes a computing device that includes a memory configured to store instructions. The computing device also includes a processor configured to execute the instructions to perform a method that includes producing an animation model from one or more representations of an object provided from a deformable likeness of the object. The one or more representations are based upon position information from a collection of images of the object captured by at least one camera. The method also includes refining the animation model to produce representations that substantially match the one or more representations provided by the deformable likeness of the object. Refining the animation model is based upon the position information from the collection of images of the object and one or more constraints. |
| US09196073B2 |
Audio media mood visualization
An audio media visualization method and system. The method includes receiving by a computing processor, mood description data describing different human emotions/moods. The computer processor an audio file comprising audio data and generates a mood descriptor file comprising portions of the audio data associated with specified descriptions of the mood description data. The computer processor receives a mood tag library file comprising mood tags mapped to animated and/or still objects representing various emotions/moods and associates each animated and/or still object with an associated description. The computer processor synchronizes the animated and/or still objects with the portions of said audio data and presents the animated and/or still objects synchronized with the portions of said audio data. |
| US09196071B2 |
Image splicing method and apparatus
The present invention relates to an image splicing method and apparatus. The image splicing method includes: acquiring a first image and a second image; determining a to-be-processed region within the overlapping region, where a region within the overlapping region except the to-be-processed region is a remaining region; obtaining a weight value of each adjacent pixel pair of the remaining region; setting a weight value of an adjacent pixel pair within the to-be-processed region; determining a splicing path having the least seam line intensity of all splicing paths; and performing image splicing on the first image and the second image along the optimal seam line. According to the image splicing method and apparatus of the present invention, a seam line can be excluded from a to-be-processed region, so as to ensure that the to-be-processed region is spliced naturally and to improve subjective perception of a user in viewing an image. |
| US09196067B1 |
Application specific tracking of projection surfaces
A projection, image, and depth capture system projects content into a scene and captures images of the scene as the user interacts with the content. The system uses depth analysis to determine location and distance of available surfaces in the scene onto which the content can be projected. Due to the complexity of this analysis and the inherent imperfections of the electronic and optical components, depth analysis possesses inherent noise that may adversely affect the accuracy of the projected image onto the surface. The system is configured with noise compensation technology that averages depth information over multiple image frames captured from the scene. The averaged information leads to a more consistent measurement of the distance to the surface, which in turn allows for more accurate focus of the projected content. |
| US09196063B2 |
Super-resolution apparatus and method
An image-based super-resolution method using a cone-beam-based line-of-response (LOR) reconfiguration in a positron emission tomography (PET) image is provided. That is, an apparatus and method for reconfiguring a super-resolution PET image using a cone-beam-based LOR reconfiguration is provided. |
| US09196061B2 |
Systems and methods for performing truncation artifact correction
A method for performing truncation artifact correction includes acquiring a projection dataset of a patient, the projection dataset including measured data and truncated data, generating an initial estimate of a boundary between the measured data and the truncated data, using the measured data to revise the initial estimate of the boundary, estimating the truncated data using the revised estimate of the boundary, and using the measured data and the estimated truncated data to generate an image of the patient. |
| US09196057B2 |
Medical image diagnosis apparatus, medical image display apparatus, medical image processing apparatus, and medical image processing program
An inner wall extractor extracts the inner wall of a vital tissue based on medical image data. An outer wall extractor extracts the outer wall of the vital tissue based on the medical image data. A first raised portion calculator obtains information including the presence of a first raised portion in which the inner wall of the vital tissue is raised inward, based on the extracted inner wall of the vital tissue. A second raised portion calculator obtains information including the presence of a second raised portion in which the outer wall of the vital tissue is raised outward, based on the extracted outer wall of the vital tissue. A display controller superimposes the information of the first raised portion obtained by the first raised portion calculator and the information of the second raised portion obtained by the second raised portion calculator on an image of the vital tissue, and causes the image to be displayed on a display unit. |
| US09196054B2 |
Method and system for recovery of 3D scene structure and camera motion from a video sequence
An improved method and a system are disclosed for recovering a three-dimensional (3D) scene structure from a plurality of two-dimensional (2D) image frames obtained from imaging means. Sets of 2D features are extracted from the image frames, and sets corresponding to successive image frames are matched, such that at least one pair of matched 2D features refers to a same 3D point in a 3D scene captured in 2D in the image frames. A 3D ray is generated by back-projection from each 2D feature, and the generated 3D rays are subjected to an anchor-based minimization process, for determining camera motion parameters and 3D scene points coordinates, thereby recovering a structure of the 3D scene. |
| US09196053B1 |
Motion-seeded object based attention for dynamic visual imagery
Described is a system for object detection from dynamic visual imagery. Video imagery is received as input, and the system processes each frame to detect a motion region exhibiting unexpected motion representing a moving object. Object-based feature extraction is applied to each frame containing a detection motion region. Each frame is then divided into feature-consistent regions. A motion seeded region (MSR) is identified in each frame containing a detected motion region, where the MSR corresponds to a spatial location of the detected motion region. Similar feature-consistent regions that are adjacent to and include the MSR are joined to compute a boundary around the plurality of similar feature-consistent regions. Finally, the system outputs a computed boundary surrounding an object in the detected motion region. |
| US09196051B2 |
Electronic equipment with image analysis function and related method
An electronic equipment for analyzing an image inside a light-proof container having a portable electronic device with a display screen therein is provided. The electronic equipment analyzes the gray values of each two adjacent pixels of the image to determine a number of boundary points of an area which is illumined by the display screen, linearly fits a number of straight-lines based on the boundary points in different directions, and determines an area bound by the intersections formed by the straight-lines. |
| US09196044B2 |
False alarm rejection for boat detection candidates
A method for rejecting false alarms in preliminary detected ship candidates includes: receiving an image including the plurality of preliminary ship candidates; computing intensity and gradient statistics from an image background around each of the preliminary ship candidates; determining a set of thresholds from the computed intensity and gradient statistics; determining an outline and an orientation for each of the preliminary ship candidates, using the computed intensity and gradient statistics; extracting a plurality of features from each of the outlines and orientations of the preliminary ship candidates, wherein the plurality of features includes intensity-based features, gradient-based features, texture-based features and shape-based features; and rejecting false alarms in the plurality of preliminary detected ship candidates using the extracted features and the determined thresholds and statistical distance classifiers. |
| US09196040B2 |
Method and apparatus for movement estimation
A method for estimating movement of a mobile device includes: obtaining images from a camera communicatively coupled to a processor of the mobile device; identifying a stationary light source using at least one image of the images; calculating a displacement of the stationary light source based on a first location of the stationary light source in a first image of the images and a second location of the stationary light source in a second image of the images, the first image and the second image being captured at different times; and estimating movement of the mobile device based on the displacement. |
| US09196038B2 |
Recipe based method for time-lapse image analysis
A computerized recipe station for time-lapse image analysis method includes the steps of inputting an image sequence and an initial recipe to a computer storage; performing by a computer program an incremental apply using the image sequence and the initial recipe to generate an incremental output; pausing the incremental apply; using the incremental output to perform an incremental output assurance operation, which may be an intermediate result analysis to generate an analysis output, a recipe update to generate an updated recipe, or a result editing to generate an edited incremental output; and continuing the incremental apply until pausing or completion to generate a processing output. The analysis output generated by the intermediate result analysis may be used to guide the recipe update step or used to guide the result editing step. |
| US09196036B2 |
Device and method for determining objects in a color recording
A device for determining objects in a color recording has an identifier, a feature extractor and a classifier. The identifier is implemented to identify the connected regions whose size or shape correspond to a predetermined condition from a plurality of connected regions existing in a binary image derived from a color recording based on a size or a shape of these connected regions. The feature extractor is implemented, for each of the identified connected regions, to extract a feature set from the color recording. The classifier is implemented to classify the identified connected regions into at least two disjunct groups based on the extracted feature sets for the identified connected regions. |
| US09196035B2 |
Computer apparatus for image creation and analysis
Image processing, creation and analysis techniques include using computer technology to identify a plurality of structures of interest in an image, such as spinal discs in a medical diagnostic image. Such techniques can also be used to improve image creation through the use of localizers which can help identify portions of an image, and the use of computer programs to combine multiple images into a single image for review. |
| US09196028B2 |
Context-based smartphone sensor logic
Methods employ sensors in portable devices (e.g., smartphones) both to sense content information (e.g., audio and imagery) and context information. Device processing is desirably dependent on both. For example, some embodiments activate certain processor intensive operations (e.g., content recognition) based on classification of sensed content and context. The context can control the location where information produced from such operations is stored, or control an alert signal indicating, e.g., that sensed speech is being transcribed. Some arrangements post sensor data collected by one device to a cloud repository, for access and processing by other devices. Multiple devices can collaborate in collecting and processing data, to exploit advantages each may have (e.g., in location, processing ability, social network resources, etc.). A great many other features and arrangements are also detailed. |
| US09196024B2 |
Method and apparatus for enhancing color
Embodiments of the present invention disclose a method and an apparatus for enhancing color, and relate to the image processing field, so as to solve a case of over enhancement on a region having high luminance in an original image which is caused after enhancement processing is performed. A specific solution is: obtaining a luminance component of a currently processed image; performing Gaussian filtering processing on the luminance component to obtain an illumination component; obtaining a first reflection component of the currently processed image according to the luminance component and the illumination component; performing enhancement adjustment on the first reflection component to obtain a second reflection component; obtaining a luminance gain according to the luminance component and the second reflection component; and performing enhancement processing on the currently processed image, to obtain a first enhanced image. The present invention is applicable to a process of color enhancement. |
| US09196023B1 |
Method and apparatus for adjusting a property of an image based on rotations of a transfer function
Some of the embodiments of the present disclosure provide a method comprising receiving an input image; based on the input image, generating a first output image, such that a contrast of the first output image is the same as a contrast of the input image; generating a first line in an x-y plane, wherein the first line represents a transfer function between (i) pixel values of pixels of the input image and (ii) pixel values of pixels of the first output image; receiving an input to modify the contrast of the input image; and based on receiving the input to modify the contrast of the input image, (i) rotating the first line to generate a second line in the x-y plane, and (ii) based on the second line, generating a second output image having a contrast that is different from the contrast of the input image. |
| US09196022B2 |
Image transformation and multi-view output systems and methods
An image transformation and multi-view output system and associated method generates output view data from raw image data using a coordinate mapping that reverse maps pixels of the output view data onto the raw image data. The coordinate mapping is stored in a lookup table and incorporates perspective correction and/or distortion correction for a wide angle lens used to capture the raw image data. The use of the lookup table with reverse mapping improves performance of the image transformation and multi-view output system to allow multi-view video streaming of images corrected for one or both of perspective and distortion. |
| US09196021B2 |
Video enhancement using related content
A method and systems of enhancing a video using a related image are provided. One or more patches are identified in the video, with each patch identifying a region that is present in one of the frames of the video that can be mapped to a similar region in at least one other frame of the video. For each identified patch in the video, a best matching patch in the related image is found. The video is enhanced using the best matching patch in the related image for each identified patch in the video. |
| US09196014B2 |
Buffer clearing apparatus and method for computer graphics
According to one exemplary embodiment of a buffer clearing apparatus for computer graphics, a buffer clearing (BC) hardware agent is configured to interface between one or more system buses and a memory controller, to execute one or more frame buffer clearing operations while performing memory access or power of buffer-related operations at the same time. The BC hardware agent keeps track of a plurality of status to read from and/or write to a frame buffer. When the frame buffer is to be cleared, the BC hardware agent clears a clear tag table. When a background pixel of the frame buffer is to be read, the BC hardware agent returns a background value stored in itself. |
| US09195991B2 |
Display of user selected advertising content in a digital environment
A system and method for placing an advertisement in a digital environment based upon a user's choice, subject to certain predetermined parameters, is disclosed. Through the method, a user is assigned a rating based upon, for example, his performance in a game. A list of advertisements which correspond to that rating is displayed to the user, who may then select a desired advertisement from the list. The selected advertisement is then displayed in the digital environment. Reports may be generated based upon the advertisements selected and the number of selections and/or impressions (e.g., uses or viewings) by the user, which may be sent to advertisers. |
| US09195988B2 |
Systems and methods for an analysis cycle to determine interest merchants
The method of processing an analysis cycle to determine interest merchants may include selecting a seed merchant relevant to a topic interest, identifying consumers that have completed a transaction with the seed merchant to generate a list of identified consumers, determining merchants visited by the identified consumers, scoring all the merchants based on network connectivity, activity, and merchant over-index, updating the seed merchant in response to the list of scored merchants relative to a scoring threshold, and scoring the list of identified consumers based on the number of distinct merchants in transaction and over-indexing. Additionally, the method may further comprise producing a list of updated interest merchants and a list of updated identified consumers, where the updated interest merchants and the updated identified consumers are relevant to the topic interest. |
| US09195982B2 |
System and method for interfacing a client device with a point of sale system
An information technology system taking the form of a management console, central server, point of sale system, software running on a point of sale system and software running on a customer's mobile phone. The software on the customer's mobile phone lets a customer interact with the point of sale system, allowing the customer to view a pending economic transaction, optionally add or remove items to the transaction, and pay for the transaction using payment information stored on the mobile phone. |
| US09195979B2 |
Gold and precious metal buying machine and method
The gold and precious metal buying machine and method has a housing, a vault and inboard processing stations for: weighing, detecting constituent elements with x-rays and measuring volume based upon gas or fluid displacement. Weight, elemental data and volume is used to calculate gold weight and discounted market value based upon exchange rate, gold weight and a discount factor. Market value is displayed and if accepted, the system generates payment instruction and vault storage command. A rejection negates the acceptance upon request or error signal and generates rejection command. Machine transports item to various stations and, upon the storage command to the vault, and upon rejection to the item return port in the housing. An air displacement test uses a processor measuring a differential volume and a chambered item at a different pressure by a differential position of a piston movable in the chamber. |
| US09195976B2 |
Device, charging method, and system
A device includes a display control unit configured to display a Web page on an operations panel, the Web page including a standard script and an extended script for controlling the device, an execution unit configured to cause the device to perform a process according to an instruction indicated by the extended script, and a storing unit configured to store information indicating whether respective instructions indicated by extended scripts require charges. The execution unit is configured to determine whether the instruction indicated by the extended script included in the Web page requires a charge by referring to the information stored in the storing unit, and to update charging information for the process performed according to the instruction indicated by the extended script when the instruction requires the charge. |
| US09195974B2 |
Remote deposit capture compatible check image generation
A check image generator application generates a remote deposit capture RDC compatible check image. The RDC compatible check image is sent from a sender mobile device to a recipient mobile device. The RDC compatible check image may pass through a server and may be encrypted. The recipient mobile device receives the RDC compatible check image and forwards it to a financial institution for deposit. |
| US09195971B2 |
Method and system for planning a meeting in a cloud computing environment
A method for planning a meeting in a cloud computing environment is disclosed. The method embodiment includes receiving by a server a meeting configuration file including information identifying a meeting, a plurality of meeting collaborators, and/or a plurality of meeting participants. When the meeting configuration file is received, the server is configured to generate a virtual planning space associated with the meeting and located in a cloud computing environment, to transmit a message to the plurality of meeting collaborators that includes an invitation to collaborate in the meeting via the virtual planning space, and to receive an indication to load planning content that includes at least one data object. In response to receiving the indication, the server associates the planning content with the virtual planning space so that the planning content is accessible by the meeting collaborators via the virtual planning space in the cloud computing environment. |
| US09195969B2 |
Presenting quick list of contacts to communication application user
Methods and systems of presenting a quick list of contacts to an instant messaging user are disclosed. A set of contacts is identified. From the set of contacts, a first subset is selected based on first predefined criteria and a second subset is selected from second predefined criteria. The first and second predefined criteria may include contact interaction criteria, user activity criteria, and connectedness criteria. From the first and second subsets, one or more lists of contacts are generated. The one or more lists may be displayed in a display region of an instant messaging application. |
| US09195965B2 |
Systems and methods providing collaborating among a plurality of users each at a respective computing appliance, and providing storage in respective data layers of respective user data, provided responsive to a respective user input, and utilizing event processing of event content stored in the data layers
A plurality of computing appliances, each used by a respective user, provide for collaboration on a common project having an associated base image display. Data is stored in each of a plurality of separate respective data layers, of respective user data associated with a respective display for a respective user, responsive to user input. The user data is comprised of event content data (comprised of change reference data, and change content data, wherein the event content data is representative of a unique event, for each input by the respective user) generated in a defined order of entry relative to other of the events. Mapping logic defines a mapping of event content to corresponding respective data layers. A plurality of events is selected as a selected set of events. Event content data for said events in the selected set are retrieved from respective data layers, and used to generate presentation data. |
| US09195964B2 |
Method of determining optimal change interval for a functional fluid
The present invention relates to a tool for determining, improving and/or optimizing the change interval of a functional fluid utilized in a piece of equipment by using information on the piece of the equipment and its operating conditions. In particular, the present invention relates to the optimization of the oil drain interval of a vehicle by using a base change interval and optimizing it based on the operating conditions the vehicle experiences. |
| US09195962B2 |
Generating a subgraph of key entities in a network and categorizing the subgraph entities into different types using social network analysis
A method, system and computer-program product for generating a subgraph of key entities in a network and organizing entities in the subgraph are disclosed. The technique uses social network analysis centrality metrics to identify key entities in a network. The technique also uses social network analysis centrality metrics to categorize key entities into different types. |
| US09195961B1 |
System, method, and computer program for generating channel specific heuristics
A system, method, and computer program product are provided for generating channel specific heuristics. In use, at least one channel filter including a characteristic associated with a communications channel is identified. Additionally, the at least one channel filter is applied to at least one design heuristic. Furthermore, at least one channel specific heuristic is generated based on the application of the at least one channel filter to the at least one design heuristic. |
| US09195960B2 |
Mobile terminal and control method thereof
A mobile terminal and method for communicating with a refrigerator, are discussed. According to an embodiment, the mobile terminal includes a communication unit configured to receive an electronic receipt containing purchased article information from a settlement terminal, and to receive storage article information from the refrigerator, the purchased article information identifying at least one purchased article that has been purchased, the storage article information identifying at least one stored article that is stored in the refrigerator; a display unit configured to display the purchased article information and the storage article information; and a controller configured to update the storage article information using the purchased article information based on a user input. |
| US09195949B2 |
Data analysis and predictive systems and related methodologies
A method, computer system, and computer memory medium optimizing a transductive model Mx suitable for use in data analysis and for determining a prognostic outcome specific to a particular subject are disclosed. The particular subject may be represented by an input vector, which includes a number of variable features in relation to a scenario of interest. Samples from a global dataset D also having the same features relating to the scenario and for which the outcome is known are determined. In an embodiment, a subset of the variable features within a neighborhood formed by the samples are ranked in order of importance to an outcome. The prognostic transductive model is then created based, at least in part, on the subset, the ranking, and the neighborhood. The subset and the neighborhood are then optimized until the accuracy of the transductive model is maximized. |
| US09195948B2 |
Clinical diagnosis support method and system based on hierarchical fuzzy inference technology
Disclosed is a clinical diagnosis supporting method and system based on hierarchical fuzzy inference. The clinical diagnosis supporting method includes the steps of: (a) extracting check data of a plurality of check items for each of a plurality of patients from a respective check item database; (b) selecting a characteristic from the check data of each of the check items; (c) hierarchical fuzzy-inferring the check data from which the characteristic is selected, for each check item; (d) extracting a check opinion for each disease based on an output value of the fuzzy inference for each check item; and (e) making a synthetic clinical estimation based on the extracted check opinion. |
| US09195946B2 |
Auto-maintained document classification
Machines, systems and methods for maintaining a representative data set in a document classification system, the method comprising: including an initial set of seed representative data in a representative data set (RDS) implemented for a knowledge base (KB), wherein the KB is trained to classify documents provided to a document classification system based on analysis of the representative documents included in the RDS and a set of rules, wherein the seed representative data includes a balanced number of representative data across a plurality of classes; updating the RDS by adding or removing representative data from the RDS based on feedback received about accuracy of classification of one or more documents by the classification system; and retraining the KB, wherein the retraining is performed based on occurrence of one or more events. |
| US09195940B2 |
Jabba-type override for correcting or improving output of a model
Example methods, apparatuses, or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate or otherwise support one or more processes or operations for a Jabba-type override for correcting or improving output of a model, such as a machine-learned model, for example. |
| US09195937B2 |
System and method for intelligent state management
A method is provided in one example embodiment and it includes receiving a state request and determining whether a state exists in a translation dictionary for the state request. The method further includes reproducing the state if it is not in the dictionary and adding a new state to the dictionary. In more specific embodiments, the method includes compiling a rule, based on the state, into a given state table. The rule affects data management for one or more documents that satisfy the rule. In yet other embodiments, the method includes determining that the state represents a final state such that a descriptor is added to the state. In one example, if the state is not referenced in the algorithm, then the state is released. If the state is referenced in the algorithm, then the state is replaced with the new state. |
| US09195936B1 |
System and method for updating or modifying an application without manual coding
The invention provides, in some aspects, a computer-implemented method for enabling enhanced functionality in a software application. The method includes executing, on a computer, an enhancement engine that is communicatively coupled to a rules base (or other store that contains rules) and/or a rules engine that executes rules (e.g., from the rules base). The enhancement engine receives a request to enable enhanced functionality in an application that is defined, at least in part, by a plurality of such rules, where the request specifies a selected rule in the application for such enhancement. The enhancement engine identifies (or ascertains) a new rule at least partially providing the enhanced functionality and (i) updates the rules base (or other store) to include the new rule along with the others that define at least a portion of the application and/or (ii) effects execution by the rules engine of the new rule along with those others. |
| US09195931B2 |
Switching between internal and external antennas
The present disclosure is directed to a system and method for switching between internal and external antennas. In some implementations, a system includes an antenna, a connector, and a housing. The antenna is configured to communicate wirelessly transactions with transaction terminals. The connector is connected to the antenna and configured to connect a transaction card to the antenna in response to at least insertion in the housing. The housing enclosing at least a portion of the antenna and at least a portion of the connector and including one or more elements that form an opening for receiving the transaction card. In addition, the housing is substantially rectangular and includes a first portion with a first thickness and a second portion with a second thickness different from the first thickness and at least the thickness of the transaction card. |
| US09195929B2 |
Chip card assembling structure and method thereof
Disclosed are a chip card assembling structure and a method thereof, including at least one base plate, at least one fixing element having a side forming a fixing trough corresponding to the base plate, at least one adhesive film disposed on one side of the fixing element to cover the fixing trough, and at least one thin-film chip received in the fixing trough and bonded to the adhesive film. To use the present invention, the adhesive film, together with the thin-film chip, is lifted and the base plate is placed into the fixing trough, following setting the adhesive film and the thin-film chip back to have the thin-film chip coupled to the base plate. Then, the adhesive film is lifted to remove the coupled thin-film chip and base plate, so that the relative position between the thin-film chip and the base plate is precise and correct. |
| US09195928B2 |
Customer medium to record the utilization of services
A customer medium (1) for detecting the utilization of services is proposed, comprising a first and a second antenna (2, 3) for long-range data communication, a third antenna (4), an integrated circuit (6) comprising at least one crypto-engine, one microprocessor (5) connected with the integrated circuit (6) or integrated into the integrated circuit (6), an operational amplifier (8) and an RF transceiver (7) connected to the second antenna (3), where the third antenna (4) is connected to an NFC-module in the integrated circuit (6) and is used for the short-range data communication in an active mode of the customer medium (1), where the first antenna (2) is used as a wake-up antenna for receiving an amplitude-modulated wake-up signal if the customer medium is in a “sleep” mode, where the signal received by the wake-up antenna (2) is demodulated and amplified by the operational amplifier (8) serving as the wake-up detection module and is evaluated by the microprocessor (5) partially activated in the “sleep” mode, where the microprocessor (5) is completely activated in the event of a valid wake-up signal, by which the customer medium (1) enters the active mode and where the operational amplifier (8) is the only component of the customer medium (1) that is fully active in “sleep”-mode. |
| US09195925B2 |
Method and system for improved wireless sensing
In one embodiment, a RF sensor comprising a sensing antenna and a reference antenna, wherein a sensing material is disposed upon said sensing antenna and wherein the sensing antenna is configured to test for specific analyte by measurement of the resonant impedance spectra, and the reference antenna is configured to mitigate and correct for environmental parameters and positionn. In a further embodiment, a method for sensing comprising; utilizing an RF sensor, wherein the RF sensor comprises a sensing antenna and a reference antenna, wherein said RF sensor is configured to test for a specific analyte; and, measuring a resonant impedance spectra of the sensing antenna and reference antennaat multiple frequencies to provide a subsequent multivariate analysis of a signal response from the RF sensor. |
| US09195924B2 |
Band-gap reference self-starting circuit and a passive radio frequency identification tag
The present invention relates to the field of radio frequency, and provides a band-gap reference self-starting circuit and a passive radio frequency identification tag. The self-starting circuit comprises: a first switch device unit, configured to generate a first leakage current in an off state; a second switch device unit, configured to generate a second leakage current lower than the first leakage current in the off state, and generate a control voltage according to the first leakage current and the second leakage current; a control unit, configured to generate a starting control signal according to the control voltage; and a band-gap reference generating unit, configured to generate a reference voltage according to the starting control signal, and control the second switch device unit to enter dormancy using the reference voltage. The present invention boosts the control voltage using the leakage current generated by a field effect transistor in the off state, thereby implementing self-starting and generating the reference voltage, and controls the starting control unit to enter dormancy after the reference voltage is generated, thereby reducing system power consumption. |
| US09195923B2 |
In-line document puncher/voider in a document personalization machine
Document personalization machines with a mechanism designed to operate as an in-line document puncher/voider. The document personalization machine includes a document personalization mechanism that performs a personalization operation on the document, a document transport mechanism that transports the document along a document path through the document personalization machine and a document punch mechanism that creates a punch hole on the document. The document can be, for example, a card such as a financial (e.g. credit and debit) card, drivers' license, and a national identification document, or another documents such as a passport. A punched hole can, for example, indicate that the document is void, destroy a magnetic stripe, integrated circuit chip or other information storage medium on the document, or provide access for a lanyard, a key ring and the like. |
| US09195919B2 |
Fixed memory rendering
A method of forming print instructions in a host for rendering within a fixed amount of memory on a printer receives intermediate data comprising regions which are associated with drawing instructions. A first amount of memory available to render the intermediate data is calculated based on a second amount of memory needed by the printer to store the intermediate data. The host determines a subset of the drawing instructions as complex drawing instructions and renders the complex drawing instructions to the printer as simpler drawing instructions. For regions associated with the complex drawing instructions, the host reassociates the regions with the corresponding simpler drawing instructions to form altered intermediate data which can be rendered on the printer within the determined first amount of memory. The print instructions, including the altered intermediate print data, can then be rendered by the printer to pixel data within the fixed amount of memory. |
| US09195918B2 |
Light scanning device capable of executing automatic light amount control and image forming apparatus equipped with the same
A light scanning device that performs rapid scanning synchronization timing detection to thereby enable automatic light amount control to be executed rapidly and with high accuracy. A light amount sensor disposed on a scanning line of the laser light receives the laser light. A controller controls the timing of emission by the laser emitting device and a light amount of the laser light based on image data, according to an output from the light amount sensor. A temperature sensor detects the temperature of the laser emitting device or in the light scanning device. A storage section stores data indicative of a relationship between temperature, current supplied to the laser emitting device, and light amount. A controller controls current to be supplied to the laser emitting device based on temperature detected by the temperature detecting unit and data stored in the storage section. |
| US09195915B2 |
Printing apparatus, method of changing layout, and storage medium
Logical pages are laid out on a physical page according to setting of a multipage printing condition. When a user drags a logical page, a layout of logical pages is changed based on an area to which the logical page is dragged. |
| US09195914B2 |
Construction zone sign detection
Methods and systems for detection of a construction zone sign are described. A computing device, configured to control the vehicle, may be configured to receive, from an image-capture device coupled to the computing device, images of a vicinity of the road on which the vehicle is travelling. Also, the computing device may be configured to determine image portions in the images that may depict sides of the road at a predetermined height range. Further, the computing device may be configured to detect a construction zone sign in the image portions, and determine a type of the construction zone sign. Accordingly, the computing device may be configured to modify a control strategy associated with a driving behavior of the vehicle; and control the vehicle based on the modified control strategy. |
| US09195905B2 |
Method and system for graph based interactive detection of curve structures in 2D fluoroscopy
A method and system for detecting a curve structure in a 2D fluoroscopic image is disclosed. A plurality of curve segments are detected in the image. A graph is generated based on the detected curve segments. A curve structure is detected in the image by determining a path between a source node and a destination node in the graph. A hyper-graph can be constructed from the graph in order to impose geometric constraints on segments of the detected the curve structure, and the curve structure can be detected by finding a shortest path in the hyper-graph. |
| US09195902B2 |
Straight line detection apparatus and straight line detection method
To detect a straight line using the Hough transform taking into consideration not only the number of points but also other properties of the straight line, the Hough transform unit performs a Hough transform on contour-enhanced binary image data. The Hough table stores a count after the Hough transform. The adjustment unit adjusts the count. The straight line detection unit detects a straight line based on the adjusted count. Additionally, to detect a straight line, independent of its direction or location in the image, for each straight line in the binary image data, the straight line calculation unit determines the intersections where that straight line cuts up the binary image data to calculate the intersection distance. The normalization unit divides the count stored in the Hough table by the intersection distance to normalize the count. The straight line detection unit detects a straight line based on the normalized count. |
| US09195896B2 |
Methods and systems for image recognition
A method and system for image recognition are disclosed. The method includes the steps of acquiring image information for a target object to be recognized at a terminal device; transferring said image information to a server, wherein the server applies feature recognition techniques to the image information, and returns a recognition result; and presenting the recognition result returned by the server at the terminal device. The method and system consistent with the present disclosure may simplify user operations and improve the efficiency and intelligence level of an image recognition system. |
| US09195895B1 |
Systems and methods for detecting traffic signs
Systems and methods are provided for detecting traffic signs. In one implementation, a traffic sign detection system for a vehicle include at least one image capture device configured to acquire at least one image of a scene including a traffic sign ahead of the vehicle. The traffic sign detection system also includes a data interface and at least one processing device programmed to receive the at least one image via the data interface, transform the at least one image, sample the transformed at least one image to generate a plurality of images having different sizes, convolve each of the plurality of images with a template image, compare each pixel value of each convolved image to a predetermined threshold, and select local maxima of pixel values within local regions of each convolved image as attention candidates, the local maxima being greater than the predetermined threshold. |
| US09195893B2 |
Biometric matching technology
Biometric matching technology, in which a watch list is managed, multiple images of a potential suspect are accessed, and parallel pre-processing of the multiple images is controlled. Based on the pre-processing, an image of the potential suspect to use in matching against the watch list is determined and the determined image is used to search sorted biometric data included in the watch list. A subset of persons from the watch list is identified based on the search and parallel analysis of the determined image of the potential suspect against detailed biometric data associated with the subset of persons in the watch list is controlled. Based on the parallel analysis, it is determined whether the potential suspect matches a person in the watch list and a result is outputted based on the determination. |
| US09195892B2 |
System for and method of detecting strobe using spatial features in video frames
A video processing device includes a histogram generating component, an analyzing component, a comparator and an encoding component. The histogram generating component can generate a histogram for image data of an image frame. The analyzing component can analyze the histogram, can identify an isolated spike in the histogram and can output at least one strobe parameter. The comparator can compare the at least one strobe parameter with at least one predetermined threshold, can output a first instruction signal when the at least one comparison operation is indicative of a strobe and can output a second instruction signal when the at least one comparison operation is not indicative of a strobe. The encoding component can encode the image data in a first manner based on the first instruction signal and can encode the image data in a second manner based on the second instruction signal. |
| US09195891B2 |
Method of predicting crop yield loss due to n-deficiency
A method for determining the yield loss of a crop using remote sensor data is described. The yield loss is determined using the reflectivity of green light by the crop canopy measured from remote sensor data such as an aerial photograph that is digitized and spatially referenced to the field's longitude and latitude. Green pixel values from the aerial photograph, expressed relative to green pixel values from well-fertilized areas of the field, are transformed to yield losses using a linear transformation that was developed using empirical data. A similar method is described to determine recommended nitrogen fertilization rates for the crop fields. The yield loss data is useful for nitrogen fertilization management, as it allows a producer of crops to weigh the expense of fertilization against the loss of revenue due to yield loss. |
| US09195890B2 |
Iris biometric matching system
A method and apparatus for biometric iris matching comprising pre-processing an input image capturing one or more eyes to produce one or more rectified iris images, coding the one or more rectified iris images into one or more multiresolution iris codes and matching the one or more multiresolution iris code with a set of stored multiresolution iris codes to determine whether a match exists. |
| US09195888B2 |
Document registration apparatus and non-transitory computer readable medium
A document registration apparatus includes a receiving unit that receives a request for registration of a registration candidate document from a new registrant, a word extracting unit that extracts a word from the registration candidate document, a registrant information acquiring unit that acquires information on the new registrant, an associating unit that associates the extracted word with a group to which the new registrant belongs, a first storage unit that stores history information, a second storage unit that stores an identifier of a previous registrant and a group to which the previous registrant has belonged, an extracting unit that extracts an identifier of a previous registrant who registered a word identical to the extracted word, and extracts a group to which the previous registrant has belonged, a registration permission determining unit that determines whether to allow registration, and a document registering unit that registers the registration candidate document. |
| US09195885B2 |
Positional locating system and method
A method and system are disclosed for locating or otherwise generating positional information for an object, such as but not limited generating positional coordinates for an object attached to an athlete engaging in an athletic event. The positional coordinates may be processed with other telemetry and biometrical information to provide real-time performance metrics while the athlete engages in the athletic event. |
| US09195884B2 |
Method, apparatus, and manufacture for smiling face detection
A method, apparatus, and manufacture for smiling face detection is provided. For each frame, a list of new smiling faces for the frame is generated by performing smiling face detection employing an object classifier that trained is to distinguish between smiling faces and all objects in the frame that are not smiling faces. For the first frame, the list of new smiling faces is employed as an input smiling face list for the next frame. For each frame after the first frame, a list of tracked smiles for the frame is generated by tracking smiling faces in the frame from the input smiling list for the frame. Further, a list of new smiling faces is generated for the next frame by combining the list of new smiling faces for the frame with the list of tracked smiles for the frame. |
| US09195883B2 |
Object tracking and best shot detection system
A method and system using face tracking and object tracking is disclosed. The method and system use face tracking, location, and/or recognition to enhance object tracking, and use object tracking and/or location to enhance face tracking. |
| US09195880B1 |
Interactive viewer for image stacks
An image-stack viewer may switch between images in an image stack based on detected interactions with the images that are displayed in the viewer. In particular, a region-of-interest (ROI) in an image may be determined based on an interaction, and image characteristics of the ROI may be evaluated in two or more images in the image stack where the ROI best represents the evaluated characteristics. |
| US09195879B1 |
Air/object determination for biometric sensors
A fingerprint sensing apparatus may include a fingerprint sensor system and a control system capable of receiving fingerprint sensor data from the fingerprint sensor system. The control system may be capable of determining fingerprint sensor data blocks for at least a portion of the fingerprint sensor data and of calculating statistical variance values for fingerprint sensor data corresponding to each of the fingerprint sensor data blocks. The control system may be capable of determining, based at least in part the statistical variance values, whether an object is positioned proximate a portion of the fingerprint sensor system. |
| US09195875B1 |
Method and apparatus for defining fields in standardized test imaging
Disclosed herein, among other things, are method and apparatus for defining fields in a standardized test imaging system. In various embodiments, at least one page of a standardized exam is converted into a raster image. One or more bubble response fields are automatically identified on the raster image and a location of one or more bubble response fields is stored in a database. According to various embodiments, a portion of the raster image is defined that includes one or more bubble response fields. A size of the bubbles of the one or more bubble response fields is selected, and one or more bubbles of the size selected are automatically detected. A position of each bubble detected is determined and stored, according to various embodiments. |
| US09195874B2 |
Apparatus and method for recognizing barcode
An apparatus and method for recognizing a barcode is disclosed, the recognizing method including steps of selecting and interpolating X-axis data at an arbitrary Y-axis of the barcode, detecting peaks of black and white modules of the barcode and restoring the barcode, and estimating widths of the black and white modules, extracting binary data and decoding the binary data. |
| US09195870B2 |
Copy-resistant symbol having a substrate and a machine-readable symbol instantiated on the substrate
A variety of forms of machine-readable symbols are disclosed, as well as methods and systems of constructing machine-readable symbols, methods and systems of acquiring machine-readable symbols, and methods and systems of decoding machine-readable symbols. |
| US09195869B2 |
Theme park photograph tracking and retrieval system for park visitors and associated methods
A photography database is configured to interface with at least one camera and includes a memory to store pictures of distinct bar codes and of theme park guests in the order in which they were taken so that the distinct bar codes separate the respective pictures of the theme park guests. A processor is coupled to the memory to retrieve stored pictures based on the distinct bar codes being presented by the theme park guests by detecting the stored distinct bar code matching the distinct bar code presented by the theme park guest, and detecting a stored next distinct bar code that does not match the distinct bar code presented by the theme park guest. All pictures between the matching and non-matching stored distinct bar codes are retrieved. At least one display is coupled to the photography database for displaying the retrieved pictures. |
| US09195867B2 |
System and method for automated identification of a photographed subject at a resort area
A system and method monitor skier behavior. An identifier is read from a lift access product when the lift access product is in the vicinity of a lift boarding area and a scan record containing the identifier, location information of the lift boarding area and a time stamp if generated. The scan record is processed to generate a location event record that is stored within a location database. The location database is processed to determine skier behavior based upon the location event records. |
| US09195866B1 |
Systems and methods for tracking subjects
A radio frequency identification (RFID) network and methods thereof for tracking subjects in a closed environment includes distributing RFID readers across the environment, at least some being at environment entry points. Readers have unique reader identifiers and communicate with a computer system. These identifiers and reader locations are stored. The ingress and/or egress of subjects bearing passive RFID tags is acquired by reading the unique subject identifiers off the tags from up to forty feet along with the reader identifiers of the readers making the readings. This informs a map comprising positions, on an environment diagram, of the subjects. The status of the readers is maintained by receiving and analyzing status signals from the readers. A subject data store is maintained and includes the ingress/egress data and electronic addresses of the subjects. An instruction set data store, each set corresponding to one of a plurality of events, is also maintained. |
| US09195863B2 |
Magnetic card reader mounting system
One example of a magnetic card reader mounting system includes a card reader mounting system for attaching to a kiosk in which a tablet computer is housed. The card reader mounting system includes a swipe path accessory panel, a swipe path plate, and a reader head subassembly. The swipe path plate and the reader head subassembly are secured to the swipe accessory panel. The system also includes a swipe cap secured to the reader head subassembly, wherein the swipe path plate and the reader head subassembly are configurable to support a plurality of reader head geometries. |
| US09195860B1 |
Adaptively combining waveforms
A circuit may be configured to adaptively combine two or more waveforms into a single waveform. The circuit can generate weighting factors based on received error signals, and can apply the weighting factors to the two or waveforms to be combined. |
| US09195856B2 |
Data processing lock signal transmission
In accordance with one aspect of the present description, a node of the distributed computing system has multiple communication paths to a data processing resource lock which controls access to shared resources, for example. In this manner, at least one redundant communication path is provided between a node and a data processing resource lock to facilitate reliable transmission of data processing resource lock signals between the node and the data processing resource lock. Other features and aspects may be realized, depending upon the particular application. |
| US09195855B2 |
Data processing lock signal transmission
In accordance with one aspect of the present description, a node of the distributed computing system has multiple communication paths to a data processing resource lock which controls access to shared resources, for example. In this manner, at least one redundant communication path is provided between a node and a data processing resource lock to facilitate reliable transmission of data processing resource lock signals between the node and the data processing resource lock. Other features and aspects may be realized, depending upon the particular application. |
| US09195854B2 |
System and method for controlling the on and off state of features at runtime
Methods and systems are provided for turning on and off features at run time. The method includes providing a unique enabling predicate (e.g., an “if enabled” statement) for one or more executable features (blocks of code), configuring a permissions library, and caching the configured permissions library. The method further includes interrogating the cache with the first “if enabled” predicate, executing the block of code (feature) if the cache yields “true” for the requesting user, and not executing the code block if the cache yields “false” for the requesting user. |
| US09195849B2 |
Cloud application installed in client terminal connected to cloud server
A cloud application system installed in a client terminal that is connected to a cloud server via a network, the cloud application system comprising: a first driver controlling module configured to display a list of folders of a relevant user in the cloud server by communicating with the cloud server; a second cloud driver controlling module configured to encrypt a file of the cloud server to store it as the encrypted security file when the file is stored in the client terminal. |
| US09195844B2 |
System and method for securing sensitive data
An approach is provided for securing data in a technical environment. In one embodiment, a processor obtains a first file, which when executed installs a first portion of a second file and an assembly key to assemble the second file. The processor executes this first file and then obtains the second portion of the second file. The processor assembles the second file using the first portion, the second portion, and the assembly key. |
| US09195840B2 |
Application-specific file type generation and use
Techniques are described for facilitating file access control of a storage service. In response to a third-party application requesting access to a user's file, the service extracts an application-specific ID from a file type associated with the retrieved file; and grants access to the requested file in response to a determination that an application-specific ID for the third-party application matches an application-specific ID extracted from the file. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09195834B1 |
Cloud authentication
An authentication system is disclosed. A first user's response(s) to an authentication challenge for the first user is received. The first user is associated with a first service provider. A score is determined based on the user response(s). The first service provider is sent an assessment based on the determined score. |
| US09195828B2 |
System and method for prevention of malware attacks on data
The present invention relates to data encryption and more particularly to data encryption for prevention of malware attacks designed to access user data. The present invention protects user data against regular malware and advance malware like rootkit attacks, zero day attacks and anti-malware disabler attacks. In one embodiment, the present invention uses encryption, application whitelisting, and application binding to prevent malware from accessing a victim's data files. In another embodiment, the present invention uses application path binding to further contain the malware from accessing the victim's data. |
| US09195827B2 |
Defensive techniques to increase computer security
Among other disclosed subject matter, a computer-implemented method includes initializing a first descriptor table and a second descriptor table. The first descriptor table is associated with a first permission level and the second descriptor table is associated with a second permission level that is different from the first permission level. The first descriptor table and the second descriptor table are associated with a hardware processor and initialized by an operating system kernel. The method also includes providing a memory address associated with the first descriptor table, in response to a descriptor table address request. The descriptor table address request is provided by a software process. The method also includes updating the second descriptor table, in response to an update request. |
| US09195821B2 |
System and methods for remote software authentication of a computing device
The current disclosure relates to techniques for system and methods for software-based management of remote software authentication of at least one entity machine, addressing various vulnerabilities of software authentication based upon the genuinity based scheme. The disclosure is using challenge execution on at least one suspect machine, providing a technique for CPU event monitoring of a combined count of at least two events monitored on the entity machine during execution of the authentication challenge. The authentication challenge allows further detection functionality of virtual machine or a hypervisor installed. The techniques measures execution time of authentication challenge, comparing the received challenge result with the expected challenge result and accordingly rejects or allows the entity machine through the authentication process. |
| US09195820B2 |
System and method for graduated security in user authentication
A computer system for authenticating user access to at least one computer application of a plurality of computer applications is provided. The computer system includes a memory device and a processor. The computer system is programmed to identify a security level from a plurality of security levels for each computer application within the plurality of computer applications. The plurality of security levels include at least a first-tier security level and a second-tier security level. The second-tier security level requires additional authentication information as compared to the first-tier security level. The computer system is also programmed to create a user account for a user within the memory device with the first-tier security level, and to determine that the user account requires the second-tier security level, and prompt the user to enter the additional authentication information. The computer system is also programmed to promote the user account to the second-tier security level. |
| US09195817B2 |
Techniques for biometric authentication of user of mobile device
A method for biometric authentication of a user of a mobile device, and a case for performing the method is provided. The method includes, by the case, coupling the mobile device to the case, receiving from the mobile device biometric data of the user of the mobile device that was captured by the mobile device, storing the biometric data, receiving a request from the mobile device for authenticating the user of the mobile device, the request including biometric data captured by the mobile device, comparing the biometric data stored in the case and the biometric data included in the request, and sending to the mobile device a response to the request for authenticating the user of the mobile device based on a result of the comparison, wherein the response to the request is for use by the mobile device to perform an operation based on the authentication of the user. |
| US09195816B2 |
Intelligent graphics interface in a handheld wireless device
Various embodiments of the invention may allow applications and information to be clustered together in ways that simplify and automate various tasks. Other embodiments may present a graphical user interface to the user that allows the user to choose from a matrix of information categories and applications that can help provide that information. Still other embodiments may provide different user interface methods based on status awareness. |
| US09195815B2 |
Systems and methods for automated selection of a restricted computing environment based on detected facial age and/or gender
Systems and methods to select and launch a restricted computing environment on an information handing system in an automated manner based on detected facial age and/or gender of a current user of the information handling system. |
| US09195814B1 |
Credential tracking
In one implementation, a credential associated with a user identifier and a location is stored at a client device. A request to output a representation of the credential in a manner that enables a credential authority to validate the representation is received. Responsive to receiving the request to render the representation of the credential, a location of the client device is obtained and a determination that the location of the client device is within a predefined distance of the location associated with the credential is made. Responsive to determining that the location of the client device is within the predefined distance of the location associated with the credential, data indicating that the user has entered the location associated with the credential is stored in a memory of the client device. |
| US09195810B2 |
Identifying factorable code
Various embodiments are disclosed that relate to the automated identification of one or more computer program functions for potentially placing on a remote computing device in a split-computational computing environment. For example, one disclosed embodiment provides, on a computing device, a method of determining a factorable portion of code to locate remotely from other portions of the code of a program to hinder unauthorized use and/or distribution of the program. The method includes, on a computing device, receiving an input of a representation of the code of the program, performing analysis on the representation of the code, the analysis comprising one or more of static analysis and dynamic analysis, and based upon the analysis of the code, outputting a list of one or more functions determined from the analysis to be candidates for locating remotely. |
| US09195809B1 |
Automated vulnerability and error scanner for mobile applications
In an embodiment, a method comprises downloading an application program to a first storage coupled to a first device, wherein the application program comprises an encrypted portion based on a set of personally identifying data stored on the first storage; configuring the application program to load and execute a pre-compiled library when the application program is launched and which when executed by the first device, causes storing an unencrypted version of the application program on the first storage; launching the application program. |
| US09195808B1 |
Systems and methods for proactive document scanning
A method and system for detecting and removing sensitive or hidden information in an electronic document. Detection and removal are performed according to one or more document cleansing policies, which specify the types of sensitive or hidden information to detect and remove, for example, confidential information, financial data, profanity, and the like. Individual policies may be distributed to user clients, and may operate in the form of a “plug-in” to various software programs such as word processors, spreadsheet programs, and e-mail clients. When a user creates or edits an electronic document containing undesirable information, the “plug-in” prevents the user from taking an action (such as saving, printing, moving or sending) with respect to the document if it violates the installed policy or policies, until the document is cleansed. |
| US09195804B2 |
Daisy chain array of medications cabinets
A group of locking medical storage are connected together using a daisy-chain connection based on i2C protocol. Each of the storage cabinets has one or more locking compartments. A control PC computer is connected to a first one of the cabinets, and that cabinet is connected to each of the other cabinets using i2C daisy chain cabling. The cabinets each have a control circuit module that controls locking and unlocking of doors and drawers, and sensors to detect open or closed status and locked or unlocked status. RFID readers detect which items or medications have been removed from the cabinet. Each cabinet is assigned a unique independent address for identification when it is joined to the daisy chain, which can include an unlimited number of cabinets. |
| US09195801B1 |
Systems and methods for treatment planning based on plaque progression and regression curves
Systems and methods are disclosed for evaluating a patient with vascular disease. One method includes receiving patient-specific data regarding a geometry of the patient's vasculature; creating an anatomic model representing at least a portion of a location of disease in the patient's vasculature based on the received patient-specific data; identifying one or more changes in geometry of the anatomic model based on a modeled progression or regression of disease at the location; calculating one or more values of a blood flow characteristic within the patient's vasculature using a computational model based on the identified one or more changes in geometry of the anatomic model; and generating an electronic graphical display of a relationship between the one or more values of the calculated blood flow characteristic and the identified one or more changes in geometry of the anatomic model. |
| US09195791B2 |
Custom module generation
Some embodiments of the present invention create a layout for a circuit design which includes one or more circuit modules. The system can receive a nominal implementation of a circuit module, and a user-defined module generator capable of generating one or more custom implementations of the circuit module from an existing implementation of the circuit module. Next, the system can create the layout for the circuit design by executing the user-defined module generator on at least one processor to generate one or more custom implementations of the circuit module from the nominal implementation. The system can then use the one or more custom implementations of the circuit module in the layout. |
| US09195789B2 |
Incremental functional verification of a circuit design
A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module. |